MCP47FXB2XT-EMQ_技术文档

MCP47FXBX4/8

8/10/12-Bit Quad/Octal Voltage Output, 6 LSb INL

Digital-to-Analog Converters with I²C Interface

Features

Package Types

• Operating Voltage Range:

- 2.7V to 5.5V - Full specifications

- 1.8V to 2.7V - Reduced device specifications

• Output Voltage Resolutions:

A1

V

A0 1

15

14

13

12

MCP47FXBX4

20-Lead VQFN

5x5 mm Quad

-

8-bit: MCP47FXB0X (256 steps)

V_REF0

2

3

4

5

REF1

- 10-bit: MCP47FXB1X (1024 steps)

- 12-bit: MCP47FXB2X (4096 steps)

• Rail-to-Rail Output

21 EP⁽¹⁾

V_OUT0

V_OUT2

NC

V

OUT1

OUT3

11 NC

• Fast Settling Time of 7.8 µs (Typical)

• DAC Voltage Reference Source Options:

- Device V_DD

- External V_REFpin (buffered or unbuffered)

- Internal band gap (1.22V typical)

• Output Gain Options:

LAT1 1

20 LAT0/HVC

19 SDA

18 SCL

17 A1

V_DD

2

A0 3

V_{REF0 4}

MCP47FXBX4

20-Lead TSSOP

Quad

- 1x (unity)

V_OUT0

5

16 V_REF1

15 V_OUT1

14 V_OUT3

13 NC

- 2x (available when not using internal V_DDas

voltage source)

V_{OUT2 6}

NC

7

8

• Nonvolatile Memory (EEPROM) Option:

V_{SS 9}

- User-programmed Power-on Reset

(POR)/Brown-out Reset (BOR) output setting

and device Configuration bits recall

12 NC

NC 10

11 NC

- Auto recall of saved DAC register setting

- Auto recall of saved device configuration

(voltage reference, gain, power-down)

• Power-on/Brown-out Reset Protection

• Power-Down Modes:

A0 1

15 A1

MCP47FXBX8

20-Lead VQFN

5x5 mm Octal

V_REF0

2

3

4

5

14 V_REF1

13 V_OUT1

12 V_OUT3

11 V_OUT5

V_OUT0

V_OUT2

- Disconnects output buffer (high-impedance)

21 EP⁽¹⁾

- Selection of V_OUTpull-down resistors

(125 k or 1 k)

V_OUT4

• Low-Power Consumption:

- Normal operation: < 1 mA (Quad), 1.8 mA

(Octal)

- Power-Down operation: 680 nA typical

- EEPROM write cycle: 2.7 mA maximum

• I²C Interface:

LAT1 1

V_{DD 2}

20 LAT0/HVC

19 SDA

A0 3

V_{REF0 4}

V_{OUT0 5}

18 SCL

MCP47FXBX8

20-Lead TSSOP

Octal

17 A1

- Slave address options: four predefined

addresses or user-programmable (all 7 bits)

16 V_REF1

15 V_OUT1

14 V_OUT3

13 V_OUT5

12 V_OUT7

11 NC

V_OUT2

6

- Standard (100 kbps), Fast (400 kbps), and

High-Speed (up to 3.4 Mbps) modes

V_OUT4

7

V_{OUT6 8}

• Package Types:

V_SS

9

- 20-lead TSSOP

NC 10

- 20-lead 5 x 5 mm VQFN

• Extended Temperature Range: -40°C to +125°C

Note 1: Includes Exposed Thermal Pad (EP); see

Table 3-1 and Table 3-2.

 2020 Microchip Technology Inc.

DS20006368A-page 1

MCP47FXBX4/8

This family of devices features WiperLock™

functionality, which prevents inadvertent changes of

the output value. It uses a high voltage on a specific

pin, with dedicated commands, to lock the values that

are stored in memory.

General Description

The MCP47FXBX4/8 devices are a family of buffered

voltage output Digital-to-Analog Converters (DAC),

with the following options:

• quad or octal output channel configurations

• 8/10/12-bit resolution

The MCP47FXBX4/8 devices communicate with the

host controller using an I²C compatible interface, sup-

porting the following data transfer rates: Standard (100

kHz), Fast (400 kHz) and High-Speed (1.7 MHz and

3.4 MHz). They can only function as slave devices.

• Volatile or nonvolatile user memory

The quad and octal options differ only by the number of

output channels. The volatile and nonvolatile versions

have an identical analog circuit structure.

Applications

There are three voltage reference sources: the external

V_REFpin, the device’s V_DDor an internal band gap volt-

age source.

• Set Point or Offset Trimming

• Sensor Calibration

When the V_DDmode is selected, it is internally con-

nected to the DAC’s reference circuit. When the exter-

nal V_REFpin is used, the user has the option to select

between a gain of 1 and 2 if the Buffered mode is used,

or the internal buffer can be bypassed entirely in the

external V_REFUnbuffered mode.

• Low-Power Portable Instrumentation

• PC Peripherals

• Data Acquisition Systems

• Motor Control

In the internal band gap voltage reference mode, the

gain can be selected between 2 and 4.

MCP47FXBX4/8 DAC Output Channel Block Diagram

V

DD

VRnB:VRnA/PDnB:PDnA

PDnB:PDnA

V

REF

PDnB:PDnA

VRnB:VRnA

Band Gap

V_DD

V

GAIN

OUT

PDnB:PDnA

VRnB:VRnA

LAT

1 kΩ

125 kΩ

DS20006368A-page 2

 2020 Microchip Technology Inc.

MCP47FXBX4/8

MCP47FXBX4 Block Diagram (Quad-Channel Output)

V_DD

Power-up/Brown-out Control

V_SS

SDA

SCL

A0

A1

I²C Serial Interface Module

MEMORY

and Control Logic

VOLATILE

(WiperLock™ Technology)

NONVOLATILE

DAC CHANNELS

0, 2

V_REF0

V_REF

V_OUT0

V_OUT2

LAT

LAT0/HVC

V_REF1

DAC CHANNELS

1, 3

V_OUT1

V_OUT3

V_REF

LAT

LAT1

MCP47FXBX8 Block Diagram (Octal-Channel Output)

V_DD

Power-up/Brown-out Control

V_SS

SDA

SCL

A0

A1

I²C Serial Interface Module

MEMORY

and Control Logic

VOLATILE

(WiperLock™ Technology)

NONVOLATILE

DAC CHANNELS

0, 2, 4, 6

V_OUT0

V_OUT2

V_OUT4

V_OUT6

V_REF0

V_REF

LAT

LAT0/HVC

DAC CHANNELS

1, 3, 5, 7

V_OUT1

V_OUT3

V_OUT5

V_OUT7

V_REF1

V_REF

LAT

LAT1

 2020 Microchip Technology Inc.

DS20006368A-page 3

MCP47FXBX4/8

Device Features

DAC

Output

Internal

Band

Gap

Device

Package Type

Memory

POR/BOR

Setting⁽¹⁾

MCP47FVB04

MCP47FVB14

MCP47FVB24

MCP47FVB08

MCP47FVB18

MCP47FVB28

MCP47FEB04

MCP47FEB14

MCP47FEB24

MCP47FEB08

MCP47FEB18

MCP47FEB28

VQFN-20 5 x 5, TSSOP-20

4

8

4

8

7Fh

1FFh

7FFh

7Fh

2

Yes

RAM

10

12

8

RAM

10

12

8

1FFh

7FFh

7Fh

RAM

EEPROM

10

12

8

1FFh

7FFh

7Fh

10

12

1FFh

7FFh

Note 1: The factory default value. The DAC output POR/BOR value can be modified via the nonvolatile DAC

output register (available only on nonvolatile devices - MCP47FEBXX).

DS20006368A-page 4

 2020 Microchip Technology Inc.

MCP47FXBX4/8

1.0

ELECTRICAL CHARACTERISTICS

(†)

Absolute Maximum Ratings

Voltage on V_DDwith Respect to V_SS........................................................................................................ -0.6V to +6.5V

Voltage on all Pins with Respect to V_SS............................................................................................. -0.6V to V_DD+0.3V

Input Clamp Current, I_IK(V_I< 0, V_I> V_DD, V_I> V_PPon HV Pins) ........................................................................±20 mA

Output Clamp Current, I_OK(V_O< 0 or V_O> V_DD) .................................................................................................±20 mA

Maximum Current out of the V_SSPin (Quad)........................................................................................................150 mA

(Octal)..........................................................................................................150 mA

Maximum Current into the V_DDPin (Quad) .........................................................................................................150 mA

(Octal)..........................................................................................................150 mA

Maximum Current Sourced by the V_OUTPin...........................................................................................................20 mA

Maximum Current Sunk by the V_OUTPin................................................................................................................20 mA

Maximum Current Sunk by the V_REFPin ...............................................................................................................125 µA

Maximum Input Current Source/Sunk by the SDA, SCL Pins ..................................................................................2 mA

Maximum Output Current Sunk by the SDA Output Pin .........................................................................................25 mA

Total Power Dissipation⁽¹⁾....................................................................................................................................400 mW

Package Power Dissipation (T_A= +50°C, T_J= +150°C)

TSSOP-20...............................................................................................................................................1300 mW

VQFN-20 (5 x 5, ML)...............................................................................................................................2800 mW

ESD Protection on all Pins±6 kV (HBM)

±400V (MM)

±2 kV (CDM)

Latch-Up (per JEDEC^®JESD78A) at +125°C ...................................................................................................±100 mA

Storage Temperature ..............................................................................................................................-65°C to +150°C

Ambient Temperature with Power Applied .............................................................................................-55°C to +125°C

Soldering Temperature of Leads (10 seconds) ..................................................................................................... +300°C

Maximum Junction Temperature (T_J).................................................................................................................... +150°C

† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is

a stress rating only and functional operation of the device at those or any other conditions above those indicated in the

operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods

may affect device reliability.

Note 1: Power dissipation is calculated as follows:

P_DIS= V_DD× {I_DD-  I_OH} +  {(V_DD– V_OH) × I_OH} + (V_OL× I_OL

)

 2020 Microchip Technology Inc.

DS20006368A-page 5

MCP47FXBX4/8

DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise specified)

Operating Temperature: -40°C  T_A +125°C (Extended)

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, V_REF= +2.048V to V_DD, V_SS= 0V, Gx = 0, R_L= 5 k from V_OUTto GND, C_L= 100 pF.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Supply Voltage

Sym.

Min.

Typ.

Max.

Units

Conditions

V_DD

2.7

1.8

—

5.5

2.7

V

Serial interface operational

DAC operation with reduced analog

specifications

V_DDVoltage

(Rising) to Ensure Device

Power-on Reset

V_POR/BOR

—

1.7

V

RAM retention voltage (V_RAM) < V_POR

V_DDvoltages greater than the V_POR/BOR

limit ensure that the device is out of reset

V_DDRise Rate to Ensure

Power-on Reset

V_DDRR

V_HV

V_IHHEN

V_IHHEX

(Note 3)

V/ms

High-Voltage Commands

Voltage Range (HVC Pin)

V_SS

9.0

—

12.5

—

V

The HVC pin will be at one of the three

(1)

input levels (V_IL, V_IHor V_IHH

)

High-Voltage

Input Entry Voltage

Threshold for entry into WiperLock™

Technology

High-Voltage

—

V_DD+ 0.8V

Note 1

Input Exit Voltage

Note 1

Note 3

This parameter is ensured by design.

POR/BOR voltage trip point is not slope dependent. Hysteresis is implemented with time delay.

DS20006368A-page 6

 2020 Microchip Technology Inc.

MCP47FXBX4/8

DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature: -40°C  T_A +125°C (Extended)

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, V_REF= +2.048V to V_DD, V_SS= 0V, Gx = 0, R_L= 5 k from V_OUTto GND, C_L= 100 pF.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym.

Min.

Typ.

Max.

Units

Conditions

Supply Current

I_DD

—

1.0

1.8

mA

Quad Serial interface active⁽²⁾

(not High-Voltage Command)

Octal

V_OUTis unloaded, V_DD= 5.5V

VRnB:VRnA = 10⁽⁴⁾

Volatile DAC register = Midscale

I²C: F_SCL= 3.4 MHz

—

0.85

1.60

µA

Quad Serial interface inactive⁽²⁾

(not High-Voltage Command)

Octal

VRnB:VRnA = All Modes

SCL = SDA = V_SS, V_OUTis unloaded

Volatile DAC register = Midscale

—

2.5

3.0

mA

Quad EE write current

V_REF= V_DD= 5.5V

Octal

(after write, serial interface is inactive)

write all 7FFhto nonvolatile DAC0

(address 10h), V_OUTpins are

unloaded.

—

560

700

µA

Quad HVC = 12.5V (High-Voltage

command), serial interface inactive

1100

1300

Octal

V_REF= V_DD= 5.5V, LAT/HVC = V_IHH

DAC registers = Midscale

V_OUTpins are unloaded

Power-Down

Current

I_DDP

—

0.68

3.8

µA

PDnB:PDnA = 01⁽⁵⁾

V_OUTnot connected

Note 2

Note 4

Note 5

This parameter is ensured by characterization.

Supply current is independent of current through the resistor ladder in mode VRnB:VRnA = 10.

The PDnB:PDnA = 00, 10, and 11configurations should have the same current.

 2020 Microchip Technology Inc.

DS20006368A-page 7

MCP47FXBX4/8

DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature: -40°C  T_A +125°C (Extended)

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, V_REF= +2.048V to V_DD, V_SS= 0V, Gx = 0, R_L= 5 k from V_OUTto GND, C_L= 100 pF.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym.

Min.

Typ.

Max.

Units

Conditions

VRnB:VRnA = 10

Resistor Ladder

Resistance

R_L

100

140

180

k

(6)

V_REF= V_DD

Resolution

(# of Resistors and # of

Taps)

N

256

Taps

8-bit No missing codes

10-bit No missing codes

12-bit No missing codes

1024

4096

(see C.1 “Resolution”)

Nominal V_OUTMatch⁽¹¹⁾

|V_OUT- V_OUTMEAN

|

—

0.5

—

1.0

1.2

—

%

2.7V  V_DD 5.5V⁽²⁾

1.8V⁽²⁾

/V_OUTMEAN

V_OUTTemperature

Coefficient (see C.19

“V_OUTTemperature

Coefficient”)

V_OUT/T

15

ppm/°C Code = Midscale

(7Fh, 1FFh or 7FFh)

V_REFPin Input Voltage

Range

V_REF

V_SS

—

V_DD

V

1.8V  V_DD 5.5V⁽¹⁾

Note 1

Note 2

Note 6

This parameter is ensured by design.

This parameter is ensured by characterization.

Resistance is defined as the resistance between the V_REFpin (mode VRnB:VRnA = 10) to V_SSpin. For

octal-channel devices (MCP47FXBX8), this is the effective resistance of each resistor ladder. The

resistance measurement is one of the two resistor ladders measured in parallel.

Note 11

Variation of one output voltage to mean output voltage.

DS20006368A-page 8

 2020 Microchip Technology Inc.

MCP47FXBX4/8

DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature: -40°C  T_A +125°C (Extended)

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, V_REF= +2.048V to V_DD, V_SS= 0V, Gx = 0, R_L= 5 k from V_OUTto GND, C_L= 100 pF.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym.

Min.

Typ.

Max.

Units

Conditions

Zero-Scale Error

(Code = 000h)

E_ZS

—

0.75

LSb

8-bit VRnB:VRnA = 10, Gx = 0,

V_REF= V_DD,no load

(see C.5 “Zero-Scale

Error (EZS)”)

—

3

LSb 10-bit VRnB:VRnA = 10, Gx = 0,

V_REF= V_DD, no load

12

LSb 12-bit VRnB:VRnA = 10, Gx = 0,

V_REF= V_DD, no load

See Section 2.0 “Typical

LSb

VRnB:VRnA = 11, Gx = 0, Gx = 1,

V_REF= 0.5 × V_DD= 2.7_,no load

Performance Curves”⁽²⁾

See Section 2.0 “Typical

VRnB:VRnA = 10, Gx = 0, Gx = 1,

V_REF= V_DD/2, V_{REF =}V_DD,

V_DD= 2.7 – 5.5V_,no load

Performance Curves”⁽²⁾

See Section 2.0 “Typical

LSb

VRnB:VRnA = 10, Gx = 0, Gx= 1,

V_REF= V_DD/2, V_{REF =}V_DD,

V_DD= 2.7 – 5.5V_,no load

Performance Curves”⁽²⁾

See Section 2.0 “Typical

LSb

VRnB:VRnA = 00, Gx = 0,

V_REF= V_DD= 2.7–5.5V, no load

Performance Curves”⁽²⁾

Full-Scale Error (see

C.4 “Full-Scale Error

(EFS)”)

E_FS

—

4.5

18

70

8-bit VRnB:VRnA = 10, Gx = 0,

V_REF= V_DD,no load

LSb 10-bit VRnB:VRnA = 10, Gx = 0,

_REF= V_DD, no load

V

LSb 12-bit VRnB:VRnA = 10, Gx = 0,

V_REF= V_DD, no load

See Section 2.0 “Typical

LSb

VRnB:VRnA = 11, Gx = 0, Gx = 1,

V_REF= 0.5 × V_DD= 2.7_,no load

Performance Curves”⁽²⁾

See Section 2.0 “Typical

VRnB:VRnA = 10, Gx = 0, Gx = 1,

V_REF= V_DD/2, V_REF= V_DD,

Performance Curves”⁽²⁾

V_DD= 2.7 – 5.5V_,no load

See Section 2.0 “Typical

LSb

VRnB:VRnA = 10, Gx = 0, Gx = 1,

V_REF= V_DD/2, V_REF= V_DD,

V_DD= 2.7 – 5.5V_,no load

Performance Curves”⁽²⁾

See Section 2.0 “Typical

VRnB:VRnA = 00, Gx = 0,

V_REF= V_DD= 2.7 – 5.5V, no load

Performance Curves”⁽²⁾

Offset Error

E_OS

-15

±1.5

+15

mV VRnB:VRnA = 00, Gx = 0, no load

(see C.7 “Offset

Error (EOS)”)

Offset Voltage

Temperature

Coefficient

V_OSTC

—

±10

—

µV/°C

Note 2

This parameter is ensured by characterization.

 2020 Microchip Technology Inc.

DS20006368A-page 9

MCP47FXBX4/8

DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature: -40°C  T_A +125°C (Extended)

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, V_REF= +2.048V to V_DD, V_SS= 0V, Gx = 0, R_L= 5 k from V_OUTto GND, C_L= 100 pF.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Gain Error

Sym.

Min.

Typ.

Max.

Units

Conditions

E_G

-1.0

±0.1

+1.0

% of

FSR

Code = 250, no load

VRnB:VRnA = 00, Gx = 0

8-bit

10-bit

12-bit

(see C.9 “Gain Error

(EG)”)⁽⁸⁾

-1.0

—

±0.1

-3

+1.0

—

% of

FSR

Code = 1000, no load

VRnB:VRnA = 00, Gx = 0

% of

FSR

Code = 4000, no load

VRnB:VRnA = 00, Gx = 0

Gain Error Drift (see

C.10 “Gain Error Drift

(EGD)”)

G/°C

ppm/°C

Total Unadjusted Error

(see C.6 “Total

Unadjusted Error

(ET)”)⁽²⁾

E_T

-2.5

-10.0

-40.0

—

+0.5

+2.0

+8.0

LSb

8-bit VRnB:VRnA = 10, Gx = 0,

_REF= V_DD,no load

V

10-bit VRnB:VRnA = 10, Gx = 0,

V_REF= V_DD, no load

12-bit VRnB:VRnA = 10, Gx = 0,

V_REF= V_DD, no load

See Section 2.0 “Typical

VRnB:VRnA = 11, Gx = 0,

Gx = 1,

Performance Curves”⁽²⁾

V_REF= 0.5 × V_DD= 2.7_,no load

See Section 2.0 “Typical

VRnB:VRnA = 10, Gx = 0,

Gx = 1,

Performance Curves”⁽²⁾

V_REF= V_DD/2, V_{REF =}V_DD,

V_DD= 2.7 – 5.5V_,no load

See Section 2.0 “Typical

VRnB:VRnA = 10, Gx = 0,

Gx = 1,

Performance Curves”⁽²⁾

V_REF= V_DD/2, V_{REF =}V_DD,

V_DD= 2.7 – 5.5V_,no load

See Section 2.0 “Typical

VRnB:VRnA = 00, Gx = 0,

V_REF= V_DD= 2.7 – 5.5V, no load

Performance Curves”⁽²⁾

Note 2

This parameter is ensured by characterization.

DS20006368A-page 10

 2020 Microchip Technology Inc.

MCP47FXBX4/8

DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature: -40°C  T_A +125°C (Extended)

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, V_REF= +2.048V to V_DD, V_SS= 0V, Gx = 0, R_L= 5 k from V_OUTto GND, C_L= 100 pF.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Integral

Sym.

Min.

Typ.

Max.

Units

Conditions

INL

-0.5

±0.1

+0.5

LSb

8-bit VRnB:VRnA = 10, Gx = 0,

Nonlinearity

V_REF= V_DD,no load

(see C.11 “Integral

Nonlinearity

(INL)”)^{(7, 10)}

-1.5

-6

±0.4

±1.5

+1.5

+6

LSb

10-bit VRnB:VRnA = 10, Gx = 0,

V_REF= V_DD, no load

12-bit VRnB:VRnA = 10, Gx = 0,

V_REF= V_DD, no load

See Section 2.0 “Typical

VRnB:VRnA = 11, Gx = 0, Gx = 1,

V_REF= 0.5 × V_DD= 2.7_,no load

Performance Curves”⁽²⁾

See Section 2.0 “Typical

VRnB:VRnA = 10, Gx = 0, Gx = 1,

V_REF= V_DD/2, V_REF= V_DD,

V_DD= 2.7 – 5.5V_,no load

Performance Curves”⁽²⁾

See Section 2.0 “Typical

LSb

VRnB:VRnA = 10, Gx = 0, Gx = 1,

V_REF= V_DD/2, V_REF= V_DD,

V_DD= 2.7 – 5.5V_,no load

Performance Curves”⁽²⁾

See Section 2.0 “Typical

VRnB:VRnA = 00, Gx = 0,

V_REF= V_DD= 2.7 – 5.5V, no load

Performance Curves”⁽²⁾

Note 2

Note 7

This parameter is ensured by characterization.

INL and DNL are measured at V_OUTwith V_RL= V_DD(VRnB:VRnA = 00)_.

Note 10 Code range dependent on resolution: 8-bit, codes 6 to 250; 10-bit, codes 25 to 1000; 12-bit, 100 to 4000.

 2020 Microchip Technology Inc.

DS20006368A-page 11

MCP47FXBX4/8

DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature: -40°C  T_A +125°C (Extended)

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, V_REF= +2.048V to V_DD, V_SS= 0V, Gx = 0, R_L= 5 k from V_OUTto GND, C_L= 100 pF.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Differential

Sym.

Min.

Typ.

Max. Units

LSb 8-bit

Conditions

DNL

-0.25

±0.0125 +0.25

VRnB:VRnA = 10, Gx = 0,

Nonlinearity

(see C.12

“Differential

Nonlinearity

(DNL)”)^{(7, 10)}

V_REF= V_DD,no load

-0.5

-1.0

±0.05

±0.2

+0.5

+1.0

LSb 10-bit VRnB:VRnA = 10, Gx = 0,

V_REF= V_DD, no load

LSb 12-bit VRnB:VRnA = 10, Gx = 0,

V_REF= V_DD, no load

See Section 2.0 “Typical

LSb

VRnB:VRnA = 11, Gx = 0, Gx = 1,

V_REF= 0.5 × V_DD= 2.7_,no load

Performance Curves”⁽²⁾

See Section 2.0 “Typical

VRnB:VRnA = 10, Gx = 0, Gx = 1,

V_REF= V_DD/2, V_REF= V_DD,

V_DD= 2.7 – 5.5V_,no load

Performance Curves”⁽²⁾

See Section 2.0 “Typical

LSb

VRnB:VRnA = 10, Gx = 0, Gx = 1,

V_REF= V_DD/2, V_REF= V_DD,

V_DD= 2.7 – 5.5V_,no load

Performance Curves”⁽²⁾

See Section 2.0 “Typical

VRnB:VRnA = 00, Gx = 0

V_REF= V_DD= 2.7 – 5.5V, no load

Performance Curves”⁽²⁾

Note 2 This parameter is ensured by characterization.

Note 7 INL and DNL are measured at V_OUTwith V_RL= V_DD(VRnB:VRnA = 00)_.

Note 10 Code range dependent on resolution: 8-bit, codes 6 to 250; 10-bit, codes 25 to 1000; 12-bit, 100 to 4000.

DS20006368A-page 12

 2020 Microchip Technology Inc.

MCP47FXBX4/8

DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature: -40°C  T_A +125°C (Extended)

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, V_REF= +2.048V to V_DD, V_SS= 0V, Gx = 0, R_L= 5 k from V_OUTto GND, C_L= 100 pF.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym.

Min.

Typ.

Max.

Units

Conditions

-3 dB Bandwidth

(see C.16 “-3 dB

Bandwidth”)

BW

—

86.5

—

kHz

V_REF= 2.048V ± 0.1V,

VRnB:VRnA = 10, Gx = 0

—

67.7

0.01

—

kHz

V_REF= 2.048V ± 0.1V,

VRnB:VRnA = 10, Gx = 1

Output Amplifier

Minimum Output

Voltage

V_OUT(MIN)

V_OUT(MAX)

—

V

1.8V  V_DD 5.5V,

Output Amplifier’s minimum drive

Maximum Output

Voltage

V_DD

–

1.8V  V_DD 5.5V,

Output Amplifier’s maximum drive

0.016

Phase Margin

Slew Rate⁽⁹⁾

PM

SR

I_SC

—

3

58

0.44

9

—

22

°C

V/µs

mA

C_L= 400 pF, R_L= 

R_L= 5 k

Short-Circuit Current

Short to V_SSDAC code = Full Scale

Short to V_DDDAC code = 000h

3

9

Internal Band Gap

Band Gap Voltage

V_BG

1.18

—

1.22

15

1.26

—

V

Band Gap Voltage

Temperature

Coefficient

V_BGTC

ppm/°C

Operating Range

V_DD

2.0

2.2

—

5.5

V

V_REFpin voltage stable

V_OUToutput linear

External Reference (V_REF

)

Input Range⁽¹⁾

V_REF

V_SS

—

1

V_DD– 0.04

V

VRnB:VRnA = 11(Buffered mode)

VRnB:VRnA = 10(Unbuffered mode)

V_DD

—

Input Capacitance

C_REF

THD

pF

dB

Total Harmonic

Distortion⁽¹⁾

—

-64

—

V_REF= 2.048V ± 0.1V,

VRnB:VRnA = 10, Gx = 0,

Frequency = 1 kHz

Dynamic Performance

Major Code

—

45

—

nV-s

1 LSb change around major carry

(7FFh to 800h)

Transition Glitch (see

C.14 “Major Code

Transition Glitch”)

Digital Feedthrough

(see C.15 “Digital

Feed-through”)

< 10

Note 1

Note 9

This parameter is ensured by design.

Within 1/2 LSb of final value when code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in a 12-bit

device).

 2020 Microchip Technology Inc.

DS20006368A-page 13

MCP47FXBX4/8

DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature: -40°C  T_A +125°C (Extended)

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, V_REF= +2.048V to V_DD, V_SS= 0V, Gx = 0, R_L= 5 k from V_OUTto GND, C_L= 100 pF.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym.

Min.

Typ.

Max.

Units

Conditions

Digital Inputs/Outputs (LAT0, LAT1, HVC)

Schmitt Trigger

V_IH

0.7 V_DD

—

V

2.7V  V_DD 5.5V (allows 2.7V digital

High Input Threshold

V_DDwith 5V analog V_DD

)

0.7 V_DD

—

V

1.8V  V_DD 2.7V

Schmitt Trigger

V_IL

0.3 V_DD

Low Input Threshold

Hysteresis of Schmitt

Trigger Inputs

V_HYS

—

0.1 V_DD

—

V

Input Leakage Current

Pin Capacitance

I_IL

-1

—

1

µA V_IN= V_DDand V_IN= V_SS

C_IN,C_OUT

—

10

—

pF

f_C= 3.4 MHz

Digital Interface (SDA, SCL)

Output Low Voltage

V_OL

—

0.4

0.2 V_DD

—

V

V_DD 2.0V, I_OL= 3 mA

V_DD< 2.0V, I_OL= 1 mA

1.8V  V_DD 5.5V

Input High Voltage

(SDA and SCL Pins)

V_IH

V_IL

0.7 V_DD

Input Low Voltage

(SDA and SCL Pins)

—

-1

—

10

0.3 V_DD

V

1.8V  V_DD 5.5V

Input Leakage

I_LI

1

µA SCL = SDA = V_SSor SCL = SDA =

V_DD

Pin Capacitance

C_PIN

—

pF

f_C= 3.4 MHz

DS20006368A-page 14

 2020 Microchip Technology Inc.

MCP47FXBX4/8

DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature: -40°C  T_A +125°C (Extended)

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, V_REF= +2.048V to V_DD, V_SS= 0V, Gx = 0, R_L= 5 k from V_OUTto GND, C_L= 100 pF.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

RAM Value

Sym.

Min.

Typ.

Max.

Units

Conditions

Value Range

N

0h

—

FFh

3FFh

FFFh

Hex

8-bit

—

10-bit

12-bit

8-bit

—

DAC Register POR/BOR

Value

N

See Table 4-2

10-bit

12-bit

PDCON Initial

Factory Setting

EEPROM

Endurance

EN_EE

DR_EE

N

—

0h

1M

—

Cycles Note 1, Note 2

Years At +25°C^{(1, 2)}

Data Retention

EEPROM Range

200

—

FFh

3FFh

FFFh

Hex

8-bit

DACn register(s)

—

10-bit DACn register(s)

12-bit DACn register(s)

—

See Table 4-2

11

Initial Factory Setting

N

EEPROM Programming

Write Cycle Time

t_WC

—

16

ms

V_DD= +1.8V to 5.5V

Power Requirements

Power Supply Sensitivity

(C.17 “Power-Supply

Sensitivity (PSS)”)

PSS

—

0.002

0.005

%/% 8-bit

Code = 7Fh

%/% 10-bit Code = 1FFh

%/% 12-bit Code = 7FFh

Note 1

Note 2

This parameter is ensured by design.

This parameter is ensured by characterization.

 2020 Microchip Technology Inc.

DS20006368A-page 15

MCP47FXBX4/8

DC Notes:

1. This parameter is ensured by design.

2. This parameter is ensured by characterization.

3. POR/BOR voltage trip point is not slope dependent. Hysteresis is implemented with time delay.

4. Supply current is independent of current through the resistor ladder in mode VRnB:VRnA = 10.

5. The PDnB:PDnA = 00, 10, and 11configurations should have the same current.

6. Resistance is defined as the resistance between the V_REFpin (mode VRnB:VRnA = 10) to V_SSpin. For

octal-channel devices (MCP47FXBX8), this is the effective resistance of each resistor ladder. The resistance

measurement is one of the two resistor ladders measured in parallel.

7. INL and DNL are measured at V_OUTwith V_RL= V_DD(VRnB:VRnA = 00).

8. This gain error does not include offset error.

9. Within 1/2 LSb of final value when code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in a 12-bit

device).

10. Code range dependent on resolution: 8-bit, codes 6 to 250; 10-bit, codes 25 to 1000; 12-bit, 100 to 4000.

11. Variation of one output voltage to mean output voltage.

DS20006368A-page 16

 2020 Microchip Technology Inc.

MCP47FXBX4/8

1.1

Timing Waveforms and Requirements

1.1.1

WIPER SETTLING TIME

± 0.5 LSb

New Value

Old Value

V_OUT

FIGURE 1-1:

V

_OUTSettling Time Waveforms.

WIPER SETTLING TIMING

Standard Operating Conditions (unless otherwise specified):

TABLE 1-1:

Operating Temperature: -40°C  T_A +125°C (Extended)

Timing Characteristics

All parameters apply across the specified operating ranges unless noted.

V_DD= +1.8V to 5.5V, V_SS= 0V, R_L= 2 k from V_OUTto GND, C_L= 100 pF.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym. Min. Typ. Max. Units

t_S7.8 µs

Conditions

V

_OUTSettling Time

—

12-bit Code = 400h  C00h; C00h  400h⁽¹⁾

(±0.5 LSb Error

Band, C_L= 100 pF)

(see C.13 “Settling

Time”)

Note 1: Within 1/2 LSb of final value when code changes from 1/4 to 3/4 of FSR.

1.1.2 LATCH PIN (LAT) TIMING

LATx

t

LAT

SCK

Wx

FIGURE 1-2:

LAT Pin Waveforms.

TABLE 1-2:

LAT PIN TIMING

Standard Operating Conditions (unless otherwise specified):

Operating Temperature: -40°C  T_A +125°C (Extended)

Timing Characteristics

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, V_SS= 0V, RL = 2 k from V_OUTto GND, C_L= 100 pF.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym.

Min.

Typ.

Max.

Units

Conditions

LATx Pin Pulse Width

t_LAT

20

—

ns

 2020 Microchip Technology Inc.

DS20006368A-page 17

MCP47FXBX4/8

1.1.3

RESET AND POWER-DOWN TIMING

V_POR

V_BOR

t_BORD

V_DD

t_PORD

V_IH

SCL

SDA

V_IH

V_OUTat High-Z

V_OUT

I²C Interface is operational

Power-on and Brown-out Reset Waveforms.

FIGURE 1-3:

Stop Start

ACK

SDA

SCL

t_PDE

t_PDD

V_OUT

FIGURE 1-4:

I²C Power-Down Command Waveforms.

TABLE 1-3:

RESET AND POWER-DOWN TIMING

Standard Operating Conditions (unless otherwise specified):

Operating Temperature: -40°C  T_A +125°C (Extended)

Unless otherwise noted, all parameters apply across these specified operating ranges:

V_DD= +2.7V to 5.5V, V_SS= 0V

Timing Characteristics

R_L= 5 k from V_OUTto V_SS, C_L= 100 pF

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym. Min. Typ. Max. Units

Conditions

Power-on Reset Delay t_PORD

Brown-out Reset Delay t_BORD

—

60

45

—

µs

µs V_DDtransitions from V_DD(MIN) > V_POR

V_OUTdriven to V_OUTdisabled

Power-Down

DAC Output Disable

Time Delay

T_PDE

—

10.5

1

—

µs PDnB:PDnA = 00 11, 10or 01started from the

falling edge of the SCL at the end of the 8th clock cycle,

V_OUT= V_OUT– 10 mV. V_OUTnot connected.

Power-Down

DAC Output Enable

Time Delay

T_PDD

µs PDnB:PDnA = 11, 10or 01-> 00started from the falling

edge of the SCL at the end of the 8th clock cycle.

Volatile DAC Register = FFh, V_OUT= 10 mV.

V_OUTnot connected.

DS20006368A-page 18

 2020 Microchip Technology Inc.

MCP47FXBX4/8

2

1.2

I C Mode Timing Waveforms and Requirements

Start

Condition

ACK/ACK

Pulse

Stop

Condition

90

SCL

SDA

LAT

91

92

93

96

95

96

FIGURE 1-5:

I²C Bus Start/Stop Bits and LAT Timing Waveforms.

V_IH

SCL

SDA

90

91

92

93

111

V_IL

Start

Condition

Stop

Condition

FIGURE 1-6:

I²C Bus Start/Stop Bits Timing Waveforms.

 2020 Microchip Technology Inc.

DS20006368A-page 19

MCP47FXBX4/8

TABLE 1-4:

I²C BUS START/STOP BITS AND LAT REQUIREMENTS

I²C AC Characteristics

Standard Operating Conditions (unless otherwise specified)

Operating Temperature: -40C  T_A +125C (Extended)

The operating voltage range is described in DC Characteristics.

Param.

Sym.

No.

Characteristic

Standard mode

Min.

Max. Units

Conditions

—

D102

90

F_SCL

0

100

400

1.7

3.4

400

100

—

kHz C_b= 400 pF, 1.8V - 5.5V⁽²⁾

Fast mode

kHz C_b= 400 pF, 2.7V - 5.5V

High-Speed 1.7

High-Speed 3.4

100 kHz mode

400 kHz mode

1.7 MHz mode

3.4 MHz mode

100 kHz mode

400 kHz mode

1.7 MHz mode

3.4 MHz mode

0

MHz C_b= 400 pF, 4.5V - 5.5V

0

MHz C_b= 100 pF, 4.5V - 5.5V

C_b

Bus Capacitive

Loading

—

pF

—

T_SU:STAStart condition

Setup time

4700

600

160

ns

Note 2

—

(only relevant for

repeated Start

condition)

—

91

T_HD:STAStart condition

Hold time

100 kHz mode

400 kHz mode

1.7 MHz mode

3.4 MHz mode

4000

600

160

—

ns

(after this period, the

first clock pulse is

generated)

92

93

T_SU:STOStop condition

Setup time

100 kHz mode

400 kHz mode

1.7 MHz mode

3.4 MHz mode

100 kHz mode

400 kHz mode

1.7 MHz mode

3.4 MHz mode

4000

600

160

4000

600

160

250

—

ns

Note 2

T_HD:STOStop condition

Hold time

Note 2

95

96

T_LATHDSCL ↑ to LAT↑ (write data ACK bit)

Write data delayed⁽³⁾

Hold Time

T_LAT

LAT High or Low time

50

—

ns

Note 2 Not Tested. This parameter is ensured by characterization.

Note 3 The transition of the LAT signal between 10 ns before the rising edge (Spec 94) and 250 ns after the rising

edge (Spec 95) of the SCL signal is indeterminate whether the change in V_OUTis delayed or not.

DS20006368A-page 20

 2020 Microchip Technology Inc.

MCP47FXBX4/8

100

101

102

92

103

SCL

90

106

107

91

SDA

In

110

109

SDA

Out

FIGURE 1-7:

I²C Bus Timing Waveforms.

2

I C BUS REQUIREMENTS (SLAVE MODE)

I²C AC Characteristics

Standard Operating Conditions (unless otherwise specified)

Operating Temperature: -40C  T_A +125C (Extended)

The operating voltage range is described in DC Characteristics.

Param.

No.

Sym.

Characteristic

Min.

Max. Units

Conditions

Clock High Time 100 kHz mode

400 kHz mode

4000

600

—

ns

1.8V-5.5V⁽²⁾

100

T_HIGH

2.7V-5.5V

4.5V-5.5V

1.8V-5.5V⁽²⁾

2.7V-5.5V

4.5V-5.5V

1.7 MHz mode

120

—

3.4 MHz mode

60

—

101

T_LOW

Clock Low Time 100 kHz mode

400 kHz mode

4700

1300

320

—

1.7 MHz mode

—

3.4 MHz mode

160

—

102A⁽²⁾

T_RSCL

SCL Rise Time

100 kHz mode

400 kHz mode

1.7 MHz mode

—

1000

300

80

C_bis specified to be from

10 to 400 pF (100 pF

maximum for 3.4 MHz

mode)

20 + 0.1C_b

20

1.7 MHz mode

20

160

ns

After a repeated Start

condition or an

Acknowledge bit

3.4 MHz mode

10

40

80

ns

After a repeated Start

condition or an

Acknowledge bit

102B⁽²⁾

T_RSDA

SDA Rise Time

100 kHz mode

400 kHz mode

1.7 MHz mode

3.4 MHz mode

—

20 + 0.1C_b

20

1000

300

160

80

ns

Cb is specified to be from

10 to 400 pF (100 pF

maximum for 3.4 MHz

mode)

10

Note 2

Not Tested. This parameter is ensured by characterization.

 2020 Microchip Technology Inc.

DS20006368A-page 21

MCP47FXBX4/8

2

I C BUS REQUIREMENTS (SLAVE MODE) (CONTINUED)

I²C AC Characteristics

Standard Operating Conditions (unless otherwise specified)

Operating Temperature: -40C  T_A +125C (Extended)

The operating voltage range is described in DC Characteristics.

Param.

No.

Sym.

Characteristic

Min.

Max. Units

Conditions

103A⁽²⁾

T_FSCL

SCL Fall Time 100 kHz mode

—

300

80

ns

C_bis specified to be from

10 to 400 pF

400 kHz mode

1.7 MHz mode

3.4 MHz mode

100 kHz mode

400 kHz mode

1.7 MHz mode

3.4 MHz mode

20 + 0.1C_b

(100 pF maximum for

20

10

3.4 MHz mode)⁽⁴⁾

40

103B⁽²⁾

T_FSDASDA Fall Time

—

300

160

80

C_bis specified to be from

10 to 400 pF

20 + 0.1C_b

20

(100 pF maximum for

3.4 MHz mode)⁽⁴⁾

10

106

T_HD:DATData Input Hold 100 kHz mode

0

—

1.8V-5.5V^{(2, 5)}

2.7V-5.5V⁽⁵⁾

4.5V-5.5V⁽⁵⁾

Note 2, Note 6

Note 6

Time

400 kHz mode

0

—

1.7 MHz mode

3.4 MHz mode

0

—

0

—

107

109

T_SU:DATData Input

Setup Time

100 kHz mode

400 kHz mode

1.7 MHz mode

3.4 MHz mode

100 kHz mode

400 kHz mode

1.7 MHz mode

250

100

10

—

10

—

T_AA

Output Valid

from Clock

—

3450

900

150

310

150

—

Note 2, Note 7

Note 7

C_b= 100 pF^{(7, 8)}

C_b= 400 pF^{(2, 7)}

C_b= 100 pF⁽⁷⁾

—

3.4 MHz mode

100 kHz mode

400 kHz mode

1.7 MHz mode

3.4 MHz mode

100 kHz mode

400 kHz mode

1.7 MHz mode

3.4 MHz mode

—

110

111

T_BUF

Bus Free Time

4700

1300

N.A.

—

Time when the bus must

be free before a new

—

transmission can start⁽²⁾

—

T_SP

Input Filter

Spike

Suppression

(SDA and SCL)

50

NXP Spec states N.A.⁽²⁾

—

50

—

10

Spike suppression

—

10

Note 2

Note 4

Note 5

Not Tested. This parameter is ensured by characterization.

Use Cb in pF for the calculations.

A master transmitter must provide a delay to ensure that the difference between SDA and SCL fall times

does not unintentionally create a Start or Stop condition.

A Fast mode (400 kHz) I²C bus device can be used in a standard mode (100 kHz) I²C bus system, but the

Note 6

requirement t_SU;DAT 250 ns must then be met. This will automatically be the case if the device does not

stretch the Low period of the SCL signal. If such a device does stretch the Low period of the SCL signal, it

must output the next data bit to the SDA line, T_Rmax. + t_SU;DAT= 1000 + 250 = 1250 ns (according to the

standard mode I²C bus specification) before the SCL line is released.

Note 7

Note 8

As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

Ensured by the T_AA3.4 MHz specification test.

DS20006368A-page 22

 2020 Microchip Technology Inc.

MCP47FXBX4/8

Timing Table Notes:

1. Within 1/2 LSb of final value when code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in 12- bit device).

2. Not Tested. This parameter is ensured by characterization.

3. The transition of the LAT signal between 10 ns before the rising edge (Spec 94) and 250 ns after the rising edge

(Spec 95) of the SCL signal is indeterminate whether the change in V_OUTis delayed or not.

4. Use C_bin pF for the calculations.

5. A master transmitter must provide a delay to ensure that the difference between SDA and SCL fall times does

not unintentionally create a Start or Stop condition.

6. A Fast mode (400 kHz) I²C bus device can be used in a standard mode (100 kHz) I²C bus system, but the

requirement t_SU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch

the Low period of the SCL signal. If such a device does stretch the Low period of the SCL signal, it must output

the next data bit to the SDA line, T_Rmax. + t_SU;DAT= 1000 + 250 = 1250 ns (according to the standard mode I²C

bus specification) before the SCL line is released.

7. As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (mini-

mum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

8. Ensured by the T_AA3.4 MHz specification test.

 2020 Microchip Technology Inc.

DS20006368A-page 23

MCP47FXBX4/8

TEMPERATURE SPECIFICATIONS

Electrical Specifications: Unless otherwise indicated, V_DD= +2.7V to +5.5V, V_SS= GND.

Parameters

Temperature Ranges

Sym.

Min.

Typ.

Max. Units

Conditions

Specified Temperature Range

Operating Temperature Range

Storage Temperature Range

Thermal Package Resistances

Thermal Resistance, 20L-TSSOP

T_A

-40

-65

—

+125

+150

°C

Note 1

_JA

—

°C/W

90

Thermal Resistance, 20L-VQFN (5 x 5,

P8X)

36.1

Note 1: Operation in this range must not cause T_Jto exceed the Maximum Junction Temperature of +150°C.

DS20006368A-page 24

 2020 Microchip Technology Inc.

MCP47FXBX4/8

2.0

TYPICAL PERFORMANCE CURVES

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

2.1

Electrical Data

Note:

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

FIGURE 2-1:

Average Device Supply

FIGURE 2-4:

Average Device Supply

Current vs. F_SCLFrequency, Voltage and

Temperature - Active Interface,

VRnB:VRnA = 00, (V_DDMode).

Current - Inactive Interface (SCL = V_IHor V_IL) vs.

Voltage and Temperature, VRnB:VRnA = 00

(V_DDMode).

FIGURE 2-2:

Average Device Supply

FIGURE 2-5:

Average Device Supply

Current vs. F_SCLFrequency, Voltage and Tem-

perature - Active Interface, VRnB:VRnA = 01

(Band Gap Mode).

Current - Inactive Interface (SCL = V_IHor V_IL) vs.

Voltage and Temperature, VRnB:VRnA = 01

(Band Gap Mode).

FIGURE 2-3:

Average Device Supply

FIGURE 2-6:

Average Device Supply

Current vs. F_SCLFrequency, Voltage and Tem-

perature - Active Interface, VRnB:VRnA = 11

(V_REFBuffered Mode).

Current - Inactive Interface (SCL = V_IHor V_IL) vs.

Voltage and Temperature, VRnB:VRnA = 11

(V_REFBuffered Mode).

 2020 Microchip Technology Inc.

DS20006368A-page 25

MCP47FXBX4/8

Note:

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

FIGURE 2-7:

Average Device Supply

FIGURE 2-9:

Average Device Supply

Current vs. F_SCLFrequency, Voltage and

Temperature - Active Interface,

VRnB:VRnA = 10 (V_REFUnbuffered Mode).

Current - Inactive Interface (SCL = V_IHor V_IL) vs.

Voltage and Temperature, VRnB:VRnA = 10

(V_REFUnbuffered Mode).

FIGURE 2-8:

Active Current (I_DDA) (at 5.5V and

_SCL= 3.4 MHz) vs. Temperature and DAC

Average Device Supply

FIGURE 2-10:

Power-Down Currents.

F

Reference Voltage Mode.

DS20006368A-page 26

 2020 Microchip Technology Inc.

MCP47FXBX4/8

2.2

Linearity Data

2.2.1

TOTAL UNADJUSTED ERROR (TUE) - MCP47FXB28 (12-BIT), V_REF= V_DD

(VRNB:VRNA = 00), GAIN = 1X, CODE 100-4000

Note:

Unless otherwise indicated: T_A= +25°C, V_DD= 5.5V

FIGURE 2-11:

Total Unadjusted Error

FIGURE 2-14:

Total Unadjusted Error

(V_OUT) vs. DAC Code, T = -40°C, V_DD= 5.5V.

(V_OUT) vs. DAC Code, T = -40°C, V_DD= 2.7V.

FIGURE 2-12:

Total Unadjusted Error

FIGURE 2-15:

Total Unadjusted Error

(V_OUT) vs. DAC Code, T = +25°C, V_DD= 5.5V.

(V_OUT) vs. DAC Code, T = +25°C, V_DD= 2.7V.

FIGURE 2-13:

(V_OUT) vs. DAC Code, T = +125°C, V_DD= 5.5V.

Total Unadjusted Error

FIGURE 2-16:

(V_OUT) vs. DAC Code, T = +125°C, V_DD= 2.7V.

Total Unadjusted Error

 2020 Microchip Technology Inc.

DS20006368A-page 27

MCP47FXBX4/8

2.2.2

INTEGRAL NONLINEARITY (INL) - MCP47FXB28 (12-BIT), V_REF= V_DD(VRNB:VRNA = 00),

GAIN = 1X, CODE 64-4032

Note:

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

FIGURE 2-17:

INL Error vs. DAC Code,

FIGURE 2-20:

INL Error vs. DAC Code,

T = 40°C, V_DD= 5.5V.

T = -40°C, V_DD= 2.7V.

FIGURE 2-18:

INL Error vs. DAC Code,

FIGURE 2-21:

INL Error vs. DAC Code,

T = +25°C, V_DD= 5.5V.

T = +25°C, V_DD= 2.7V.

FIGURE 2-19:

INL Error vs. DAC Code,

FIGURE 2-22:

INL Error vs. DAC Code,

T = +125°C, V_DD= 5.5V.

T = +125°C, V_DD= 2.7V.

DS20006368A-page 28

 2020 Microchip Technology Inc.

MCP47FXBX4/8

2.2.3

Note:

DIFFERENTIAL NONLINEARITY (DNL) - MCP47FXB28 (12-BIT), V_REF= V_DD

(VRNB:VRNA = 00), GAIN = 1X, CODE 64-4032

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

FIGURE 2-23:

DNL Error vs. DAC Code,

FIGURE 2-26:

DNL Error vs. DAC Code,

T = -40°C, V_DD= 5.5V.

T = -40°C, V_DD= 2.7V.

FIGURE 2-24:

DNL Error vs. DAC Code,

FIGURE 2-27:

DNL Error vs. DAC Code,

T = +25°C, V_DD= 5.5V.

T = +25°C, V_DD= 2.7V.

FIGURE 2-25:

DNL Error vs. DAC Code,

FIGURE 2-28:

DNL Error vs. DAC Code,

T = +125°C, V_DD= 5.5V.

T = +125°C, V_DD= 2.7V.

 2020 Microchip Technology Inc.

DS20006368A-page 29

MCP47FXBX4/8

2.2.4

TOTAL UNADJUSTED ERROR (TUE) - MCP47FXB28 (12-BIT), BANDGAP MODE

(VRNB:VRNA = 01), GAIN = 2X, CODE 100-4000

Note:

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

FIGURE 2-29:

Total Unadjusted Error

FIGURE 2-32:

Total Unadjusted Error

(V_OUT) vs. DAC Code, T = -40°C, V_DD= 5.5V.

(V_OUT) vs. DAC Code, T = -40°C, V_DD= 2.7V.

FIGURE 2-30:

Total Unadjusted Error

FIGURE 2-33:

Total Unadjusted Error

(V_OUT) vs. DAC Code, T = +25°C, V_DD= 5.5V.

(V_OUT) vs. DAC Code, T = +25°C, V_DD= 2.7V.

FIGURE 2-31:

Total Unadjusted Error

FIGURE 2-34:

Total Unadjusted Error

(V_OUT) vs. DAC Code, T = +125°C, V_DD= 5.5V.

(V_OUT) vs. DAC Code, T = +125°C, V_DD= 2.7V.

DS20006368A-page 30

 2020 Microchip Technology Inc.

MCP47FXBX4/8

2.2.5

Note:

TOTAL UNADJUSTED ERROR (TUE) - MCP47FXB28 (12-BIT), BAND GAP MODE

(VRNB:VRNA = 01), GAIN = 4X, CODE 100-4000

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

FIGURE 2-35:

Total Unadjusted Error

FIGURE 2-37:

Total Unadjusted Error

(V_OUT) vs. DAC Code, T = -40°C, V_DD= 5.5V.

(V_OUT) vs. DAC Code, T = +125°C, V_DD= 5.5V.

FIGURE 2-36:

Total Unadjusted Error

(V_OUT) vs. DAC Code, T = +25°C, V_DD= 5.5V.

 2020 Microchip Technology Inc.

DS20006368A-page 31

MCP47FXBX4/8

2.2.6

INTEGRAL NONLINEARITY (INL) - MCP47FXB28 (12-BIT), BAND GAP MODE

(VRNB:VRNA = 01), GAIN = 2X, CODE 100-4000

Note:

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

FIGURE 2-38:

INL Error vs. DAC Code,

FIGURE 2-41:

INL Error vs. DAC Code,

T = -40°C, V_DD= 5.5V.

T = -40°C, V_DD= 2.7V.

FIGURE 2-39:

INL Error vs. DAC Code,

FIGURE 2-42:

INL Error vs. DAC Code,

T = +25°C, V_DD= 5.5V.

T = +25°C, V_DD= 2.7V.

FIGURE 2-40:

INL Error vs. DAC Code,

FIGURE 2-43:

INL Error vs. DAC Code,

T = +125°C, V_DD= 5.5V.

T = +125°C, V_DD= 2.7V.

DS20006368A-page 32

 2020 Microchip Technology Inc.

MCP47FXBX4/8

2.2.7

Note:

INTEGRAL NONLINEARITY (INL) - MCP47FXB28 (12-BIT), BAND GAP MODE

(VRNB:VRNA = 01), GAIN = 4X, CODE 100-4000

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

FIGURE 2-46:

T = +125°C, V_DD= 5.5V.

INL Error vs. DAC Code,

FIGURE 2-44:

T = -40°C, V_DD= 5.5V.

INL Error vs. DAC Code,

FIGURE 2-45:

INL Error vs. DAC Code,

T = +25°C, V_DD= 5.5V.

 2020 Microchip Technology Inc.

DS20006368A-page 33

MCP47FXBX4/8

2.2.8

DIFFERENTIAL NONLINEARITY ERROR (DNL) - MCP47FXB28 (12-BIT), BAND GAP MODE

(VRNB:VRNA = 01), GAIN = 2X, CODE 100-4000

Note:

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

FIGURE 2-47:

DNL Error vs. DAC Code,

FIGURE 2-50:

DNL Error vs. DAC Code,

T = -40°C, V_DD= 5.5V.

T = -40°C, V_DD= 2.7V.

FIGURE 2-48:

DNL Error vs. DAC Code,

FIGURE 2-51:

DNL Error vs. DAC Code,

T = +25°C V_DD= 5.5V.

T = +25°C V_DD= 2.7V.

FIGURE 2-49:

DNL Error vs. DAC Code,

FIGURE 2-52:

DNL Error vs. DAC Code,

T = +125°C, V_DD= 5.5V.

T = +125°C, V_DD= 2.7V.

DS20006368A-page 34

 2020 Microchip Technology Inc.

MCP47FXBX4/8

2.2.9

Note:

DIFFERENTIAL NONLINEARITY ERROR (DNL) - MCP47FXB28 (12-BIT), BAND GAP MODE

(VRNB:VRNA = 01), GAIN = 4X, CODE 100-4000

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

FIGURE 2-55:

T = +125°C, V_DD= 5.5V.

DNL Error vs. DAC Code,

FIGURE 2-53:

T = -40°C, V_DD= 5.5V.

DNL Error vs. DAC Code,

FIGURE 2-54:

DNL Error vs. DAC Code,

T = +25°C, V_DD= 5.5V.

 2020 Microchip Technology Inc.

DS20006368A-page 35

MCP47FXBX4/8

2.2.10

TOTAL UNADJUSTED ERROR (TUE) - MCP47FXB28 (12-BIT), EXTERNAL V_REFUNBUFF-

ERED MODE (VRNB:VRNA = 10), V_REF= V_DD, GAIN = 1X, CODE 100-4000

Note:

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

FIGURE 2-56:

Total Unadjusted Error

FIGURE 2-59:

Total Unadjusted Error

(V_OUT) vs. DAC Code, T = -40°C, V_DD= 5.5V.

(V_OUT) vs. DAC Code, T = -40°C, V_DD= 2.7V.

FIGURE 2-57:

Total Unadjusted Error

FIGURE 2-60:

Total Unadjusted Error

(V_OUT) vs. DAC Code, T = +25°C,V_DD= 5.5V.

(V_OUT) vs. DAC Code, T = +25°C, V_DD= 2.7V.

FIGURE 2-58:

Total Unadjusted Error

FIGURE 2-61:

Total Unadjusted Error

(V_OUT) vs. DAC Code, T = +125°C, V_DD= 5.5V.

(V_OUT) vs. DAC Code, T = +125°C, V_DD= 2.7V.

DS20006368A-page 36

 2020 Microchip Technology Inc.

MCP47FXBX4/8

2.2.11

TOTAL UNADJUSTED ERROR (TUE) - MCP47FXB28 (12-BIT), EXTERNAL V_REF

UNBUFFERED MODE (VRNB:VRNA = 10), V_REF= V_DD/2, GAIN = 2X, CODE 100-4000

Note:

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

FIGURE 2-62:

Total Unadjusted Error

FIGURE 2-65:

Total Unadjusted Error

(V_OUT) vs. DAC Code, T = -40°C, V_DD= 5.5V.

(V_OUT) vs. DAC Code, T = -40°C, V_DD= 2.7V.

FIGURE 2-63:

Total Unadjusted Error

FIGURE 2-66:

Total Unadjusted Error

(V_OUT) vs. DAC Code, T = +25°C,V_DD= 5.5V.

(V_OUT) vs. DAC Code, T = +25°C, V_DD= 2.7V.

FIGURE 2-64:

Total Unadjusted Error

FIGURE 2-67:

Total Unadjusted Error

(V_OUT) vs. DAC Code, T = +125°C, V_DD= 5.5V.

(V_OUT) vs. DAC Code, T = +125°C, V_DD= 2.7V.

 2020 Microchip Technology Inc.

DS20006368A-page 37

MCP47FXBX4/8

2.2.12

INTEGRAL NONLINEARITY ERROR (INL) - MCP47FXB28 (12-BIT), EXTERNAL V_REFMODE,

UNBUFFERED (VRNB:VRNA = 10), V_REF= V_DD, GAIN = 1X, CODE 100-4000

Note:

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

FIGURE 2-68:

INL Error vs. DAC Code,

FIGURE 2-71:

INL Error vs. DAC Code,

T = -40°C, V_DD= 5.5V.

T = -40°C, V_DD= 2.7V.

FIGURE 2-69:

INL Error vs. DAC Code,

FIGURE 2-72:

INL Error vs. DAC Code,

T = +25°C, V_DD= 5.5V.

T = +25°C, V_DD= 2.7V.

FIGURE 2-70:

INL Error vs. DAC Code,

FIGURE 2-73:

INL Error vs. DAC Code,

T = +125°C, V_DD= 5.5V.

T = +125°C, V_DD= 2.7V.

DS20006368A-page 38

 2020 Microchip Technology Inc.

MCP47FXBX4/8

2.2.13

INTEGRAL NONLINEARITY ERROR (INL) - MCP47FXB28 (12-BIT), EXTERNAL V_REFMODE,

UNBUFFERED (VRNB:VRNA = 10), V_REF= V_DD/2, GAIN = 2X, CODE 100-4000

Note:

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

FIGURE 2-74:

INL Error vs. DAC Code,

FIGURE 2-77:

INL Error vs. DAC Code,

T = -40°C, V_DD= 5.5V.

T = -40°C, V_DD= 2.7V.

FIGURE 2-75:

INL Error vs. DAC Code,

FIGURE 2-78:

INL Error vs. DAC Code,

T = +25°C, V_DD= 5.5V.

T = +25°C, V_DD= 2.7V.

FIGURE 2-76:

INL Error vs. DAC Code,

FIGURE 2-79:

INL Error vs. DAC Code,

T = +125°C, V_DD= 5.5V.

T = +125°C, V_DD= 2.7V.

 2020 Microchip Technology Inc.

DS20006368A-page 39

MCP47FXBX4/8

2.2.14

DIFFERENTIAL NONLINEARITY ERROR (DNL) - MCP47FXB28 (12-BIT), EXTERNAL V_REF

MODE, UNBUFFERED (VRNB:VRNA = 10), V_REF

= _VDD, GAIN = 1X, CODE 100-4000

Note:

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

.

FIGURE 2-80:

DNL Error vs. DAC Code,

FIGURE 2-83:

DNL Error vs. DAC Code,

T = -40°C, V_DD= 5.5V.

T = -40°C, V_DD= 2.7V.

FIGURE 2-81:

DNL Error vs. DAC Code,

FIGURE 2-84:

DNL Error vs. DAC Code,

T = +25°C, V_DD= 5.5V.

T = +25°C, V_DD= 2.7V.

FIGURE 2-82:

DNL Error vs. DAC Code,

FIGURE 2-85:

DNL Error vs. DAC Code,

T = +125°C, V_DD= 5.5V.

T = +125°C, V_DD= 2.7V.

DS20006368A-page 40

 2020 Microchip Technology Inc.

MCP47FXBX4/8

2.2.15

DIFFERENTIAL NONLINEARITY ERROR (DNL) - MCP47FXB28 (12-BIT), EXTERNAL V_REF

MODE, UNBUFFERED (VRNB:VRNA = 10), V_REF= V_DD/2, GAIN = 2X, CODE 100-4000

Note:

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

.

FIGURE 2-86:

DNL Error vs. DAC Code,

FIGURE 2-89:

DNL Error vs. DAC Code,

T = -40°C, V_DD= 5.5V.

T = -40°C, V_DD= 2.7V.

FIGURE 2-87:

DNL Error vs. DAC Code,

FIGURE 2-90:

DNL Error vs. DAC Code,

T = +25°C, V_DD= 5.5V.

T = +25°C, V_DD= 2.7V.

FIGURE 2-88:

DNL Error vs. DAC Code,

FIGURE 2-91:

DNL Error vs. DAC Code,

T = +125°C, V_DD= 5.5V.

T = +125°C, V_DD= 2.7V.

 2020 Microchip Technology Inc.

DS20006368A-page 41

MCP47FXBX4/8

2.2.16

TOTAL UNADJUSTED ERROR (TUE) - MCP47FXB28 (12-BIT), EXTERNAL V_REFBUFFERED

MODE (VRNB:VRNA = 10), V_REF= V_DD, GAIN = 1X, CODE 100-4000

Note:

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

FIGURE 2-92:

Total Unadjusted Error

FIGURE 2-95:

Total Unadjusted Error

(V_OUT) vs. DAC Code, T = -40°C, V_DD= 5.5V.

(V_OUT) vs. DAC Code, T = -40°C, V_DD= 2.7V.

FIGURE 2-93:

Total Unadjusted Error

FIGURE 2-96:

Total Unadjusted Error

(V_OUT) vs. DAC Code, T = +25°C,V_DD= 5.5V.

(V_OUT) vs. DAC Code, T = +25°C, V_DD= 2.7V.

FIGURE 2-94:

Total Unadjusted Error

FIGURE 2-97:

Total Unadjusted Error

(V_OUT) vs. DAC Code, T = +125°C, V_DD= 5.5V.

(V_OUT) vs. DAC Code, T = +125°C, V_DD= 2.7V.

DS20006368A-page 42

 2020 Microchip Technology Inc.

MCP47FXBX4/8

2.2.17

TOTAL UNADJUSTED ERROR (TUE) - MCP47FXB28 (12-BIT), EXTERNAL V_REFBUFFERED

MODE (VRNB:VRNA = 10), V_REF= V_DD/2, GAIN = 2X, CODE 100-4000

Note:

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

FIGURE 2-98:

Total Unadjusted Error

FIGURE 2-101:

Total Unadjusted Error

(V_OUT) vs. DAC Code, T = -40°C, V_DD= 5.5V.

(V_OUT) vs. DAC Code, T = -40°C, V_DD= 2.7V.

FIGURE 2-99:

Total Unadjusted Error

FIGURE 2-102:

Total Unadjusted Error

(V_OUT) vs. DAC Code, T = +25°C,V_DD= 5.5V.

(V_OUT) vs. DAC Code, T = +25°C, V_DD= 2.7V.

FIGURE 2-100:

Total Unadjusted Error

FIGURE 2-103:

Total Unadjusted Error

(V_OUT) vs. DAC Code, T = +125°C, V_DD= 5.5V.

(V_OUT) vs. DAC Code, T = +125°C, V_DD= 2.7V.

 2020 Microchip Technology Inc.

DS20006368A-page 43

MCP47FXBX4/8

2.2.18

INTEGRAL NONLINEARITY ERROR (INL) - MCP47FXB28 (12-BIT), EXTERNAL V_REFMODE,

BUFFERED (VRNB:VRNA = 11), V_REF= V_DD, GAIN = 1X, CODE 100-4000

Note:

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

FIGURE 2-104:

INL Error vs. DAC Code,

FIGURE 2-107:

INL Error vs. DAC Code,

T = -40°C, V_DD= 5.5V.

T = -40°C, V_DD= 2.7V.

FIGURE 2-105:

INL Error vs. DAC Code,

FIGURE 2-108:

INL Error vs. DAC Code,

T = +25°C, V_DD= 5.5V.

T = +25°C, V_DD= 2.7V.

FIGURE 2-106:

INL Error vs. DAC Code,

FIGURE 2-109:

INL Error vs. DAC Code,

T = +125°C, V_DD= 5.5V.

T = +125°C, V_DD= 2.7V.

DS20006368A-page 44

 2020 Microchip Technology Inc.

MCP47FXBX4/8

2.2.19

INTEGRAL NONLINEARITY ERROR (INL) - MCP47FXB28 (12-BIT), EXTERNAL V_REFMODE,

BUFFERED (VRNB:VRNA = 11), V_REF= V_DD/2, GAIN = 2X, CODE 100-4000

Note:

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

FIGURE 2-110:

INL Error vs. DAC Code,

FIGURE 2-113:

INL Error vs. DAC Code,

T = -40°C, V_DD= 5.5V.

T = -40°C, V_DD= 2.7V.

FIGURE 2-111:

INL Error vs. DAC Code,

FIGURE 2-114:

INL Error vs. DAC Code,

T = +25°C, V_DD= 5.5V.

T = +25°C, V_DD= 2.7V.

FIGURE 2-112:

INL Error vs. DAC Code,

FIGURE 2-115:

INL Error vs. DAC Code,

T = +125°C, V_DD= 5.5V.

T = +125°C, V_DD= 2.7V.

 2020 Microchip Technology Inc.

DS20006368A-page 45

MCP47FXBX4/8

2.2.20

DIFFERENTIAL NONLINEARITY ERROR (DNL) - MCP47FXB28 (12-BIT), EXTERNAL V_REF

MODE, BUFFERED (VRNB:VRNA = 11), V_REF= V_DD, GAIN = 1X, CODE 100-4000

Note:

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

.

FIGURE 2-116:

DNL Error vs. DAC Code,

FIGURE 2-119:

DNL Error vs. DAC Code,

T = -40°C, V_DD= 5.5V.

T = -40°C, V_DD= 2.7V.

FIGURE 2-117:

DNL Error vs. DAC Code,

FIGURE 2-120:

DNL Error vs. DAC Code,

T = +25°C, V_DD= 5.5V.

T = +25°C, V_DD= 2.7V.

FIGURE 2-118:

DNL Error vs. DAC Code,

FIGURE 2-121:

DNL Error vs. DAC Code,

T = +125°C, V_DD= 5.5V.

T = +125°C, V_DD= 2.7V.

DS20006368A-page 46

 2020 Microchip Technology Inc.

MCP47FXBX4/8

2.2.21

DIFFERENTIAL NONLINEARITY ERROR (DNL) - MCP47FXB28 (12-BIT), EXTERNAL V_REF

MODE, BUFFERED (VRNB:VRNA = 11), V_REF= V_DD/2, GAIN = 2X, CODE 100-4000

Note:

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

.

FIGURE 2-122:

DNL Error vs. DAC Code,

FIGURE 2-125:

DNL Error vs. DAC Code,

T = -40°C, V_DD= 5.5V.

T = -40°C, V_DD= 2.7V.

FIGURE 2-123:

DNL Error vs. DAC Code,

FIGURE 2-126:

DNL Error vs. DAC Code,

T = +25°C, V_DD= 5.5V.

T = +25°C, V_DD= 2.7V.

FIGURE 2-124:

DNL Error vs. DAC Code,

FIGURE 2-127:

DNL Error vs. DAC Code,

T = +125°C, V_DD= 5.5V.

T = +125°C, V_DD= 2.7V.

 2020 Microchip Technology Inc.

DS20006368A-page 47

MCP47FXBX4/8

NOTES:

DS20006368A-page 48

 2020 Microchip Technology Inc.

MCP47FXBX4/8

3.0

PIN DESCRIPTIONS

Overviews of the pin functions are provided in

Section 3.1 “Positive Power Supply Input (V_DD)”

through Section 3.7 “I²C - Serial Data Pin (SDA)”.

The descriptions of the pins for the quad-DAC output

devices are listed in Table 3-1 and descriptions for the

octal-DAC output devices are listed in Table 3-2.

TABLE 3-1:

MCP47FXBX4 (QUAD-DAC) PIN FUNCTION TABLE

Description

20-Lead 20-Lead

Buffer

Type

Symbol

I/O

TSSOP

VQFN

1

19

LAT1

I

ST

DAC Register Latch Pin.

The Latch 1 Pin allows the value in the volatile DAC1/DAC3

registers (Wiper and Configuration bits) to be transferred to the

DAC1/DAC3 outputs (V_OUT1, V_OUT3).

2

3

4

5

6

20

1

V_DD

A0

—

I

P

Supply Voltage Pin

I²C Slave Address Bit 0 Pin

ST

2

V_REF0

V_OUT0

V_OUT2

NC

A

—

Analog Voltage Reference Input 0 Pin

3

Analog Buffered Analog Voltage Output – Channel 0 Pin

Analog Buffered Analog Voltage Output – Channel 2 Pin

4

7, 8, 10, 5, 6, 8, 9,

—

Not Internally Connected

11, 12, 13

10,11

9

7

V_SS

V_OUT3

V_OUT1

V_REF1

A1

—

A

I

P

Ground Reference Pin for all circuitries on the device

Buffered Analog Voltage Output - Channel 3 Pin

Buffered Analog Voltage Output - Channel 1 Pin

14

15

16

17

18

19

20

12

13

14

15

16

17

18

—

Analog Voltage Reference Input 1 Pin

I²C Slave Address Bit 1 Pin

—

I²C Serial Clock Pin

ST

SCL

I

I²C Serial Data Pin

ST

SDA

I

LAT0/HVC

I

ST

DAC Register Latch/High-Voltage Command Pin.

The Latch 0 pin allows the value in the volatile DAC0/DAC2

registers (Wiper and Configuration bits) to be transferred to the

DAC0/DAC2 outputs (V_OUT0, V_OUT2). The High-Voltage

command allows user Configuration bits to be written.

Exposed Thermal Pad⁽¹⁾

—

21

EP

—

Note 1: A = Analog, ST = Schmitt Trigger, HV = High Voltage, I = Input, O = Output, I/O = Input/Output,

P = Power.

 2020 Microchip Technology Inc.

DS20006368A-page 49

MCP47FXBX4/8

TABLE 3-2:

MCP47FXBX8 (OCTAL-DAC) PIN FUNCTION TABLE

Description

TSSOP VQFN

Buffer

Type

Symbol

I/O

20L

1

19

LAT1

I

ST

DAC Register Latch Pin.

The Latch 1 pin allows the value in the volatile

DAC1/DAC3/DAC5/DAC7 registers (Wiper and Configuration bits)

to be transferred to the DAC1/DAC3/DAC5/DAC7 outputs

(V_OUT1, V_OUT3, V_OUT5, V_OUT7).

2

3

4

5

6

7

8

9

20

1

V_DD

A0

—

I

P

Supply Voltage Pin

I²C Slave Address Bit 0 Pin

ST

2

V_REF0

V_OUT0

V_OUT2

V_OUT4

V_OUT6

V_SS

A

—

Analog Voltage Reference Input 0 Pin

3

Analog Buffered Analog Voltage Output – Channel 0 Pin

Analog Buffered Analog Voltage Output – Channel 2 Pin

Analog Buffered Analog Voltage Output – Channel 4 Pin

Analog Buffered Analog Voltage Output – Channel 6 Pin

4

5

6

7

P

Ground Reference Pin for all circuitries on the device

Not Internally Connected

10, 11

12

8, 9

10

NC

—

A

—

V_OUT7

Analog Buffered Analog Voltage Output – Channel 7 Pin

Analog Buffered Analog Voltage Output – Channel 5 Pin

Analog Buffered Analog Voltage Output – Channel 3 Pin

Analog Buffered Analog Voltage Output – Channel 1 Pin

Analog Voltage Reference Input 1 Pin

13

14

15

16

17

18

19

20

11

12

13

14

15

16

17

18

V_OUT5

V_OUT3

V_OUT1

V_REF1

A1

A

I

I²C Slave Address Bit 1 Pin

—

I²C Serial Clock Pin

ST

SCL

I

I²C Serial Data Pin

ST

SDA

I

LAT0/HVC

I

ST

DAC Register Latch/High-Voltage Command Pin.

The Latch 0 pin allows the value in the volatile

DAC0/DAC2/DAC4/DAC6 registers (Wiper and Configuration bits)

to be transferred to the DAC0/DAC2/DAC4/DAC6 outputs (V_OUT0

,

V_OUT2, V_OUT4, V_OUT6). The High-Voltage command allows user

Configuration bits to be written.

Exposed Thermal Pad⁽¹⁾

—

21

EP

—

Note 1: A = Analog, ST = Schmitt Trigger, HV = High Voltage, I = Input, O = Output, I/O = Input/Output,

P = Power.

DS20006368A-page 50

 2020 Microchip Technology Inc.

MCP47FXBX4/8

3.1

Positive Power Supply Input (V

)

3.4

Analog Output Voltage Pins

DD

V_DDis the positive supply voltage input pin. The input

supply voltage is relative to V_SS

The power supply at the V_DDpin should be as clean as

possible for good DAC performance. It is

(V

)

OUTn

.

V_OUTis the DAC analog voltage output pin. The DAC

output has an output amplifier. The DAC output range

depends on the selection of the voltage reference

source (and potential output gain selection). These are:

a

recommended to use an appropriate bypass capacitor

of about 0.1 µF (ceramic) to ground. An additional

10 µF capacitor (tantalum) in parallel is also

recommended to further attenuate noise present in

application boards.

• Device V_DD– The full-scale range of the DAC out-

put is from V_SSto approximately V_DD

.

• V_REFpin – The full-scale range of the DAC output

is from V_SSto G × V_RL, where G is the gain selec-

tion option (1x or 2x).

3.2

Ground (V

)

SS

• Internal Band Gap – The full-scale range of the

DAC output is from V_SSto G × (2 × V_BG), where G

is the gain selection option (1x or 2x).

The V_SSpin is the device ground reference.

The user must connect the V_SSpin to a ground plane

through a low-impedance connection. If an analog

ground path is available in the application PCB (Printed

Circuit Board), it is highly recommended that the V_SS

pin be tied to the analog ground path or isolated within

an analog ground plane of the circuit board.

In Normal mode, the DC impedance of the output pin is

about 1. In Power-Down mode, the output pin is

internally connected to a known pull-down resistor of

1 k, 125 k, or open. The power-down selection bits

settings are shown in Register 4-3 and Table 5-4.

3.5

Latch Pin (LAT)/High-Voltage

Command (HVC)

3.3

Voltage Reference Pins (V

)

REF

The V_REFpin is either an input or an output. When the

DAC’s voltage reference is configured as the V_REFpin,

the pin is an input. When the DAC’s voltage reference is

configured as the internal band gap, the pin is an output.

The DAC output value update event can be controlled

and synchronized using the LAT pins, for one or both

channels, on a single or different devices.

The LAT pins control the effect of the Volatile Wiper

registers, VRnB:VRnA, PDnB:PDnA and Gx bits on the

DAC output.

When the DAC’s voltage reference is configured as the

V_REFpin, there are two options for this voltage input:

• V_REFpin voltage buffered

• V_REFpin voltage unbuffered

If the LAT pins are held at V_IH, the values sent to the

Volatile Wiper registers and Configuration bits have no

effect on the DAC outputs.

The buffered option is offered in cases where the exter-

nal reference voltage does not have sufficient current

capability to not drop its voltage when connected to the

internal resistor ladder circuit.

Once voltage on the pin transitions to V_IL, the values in

the Volatile Wiper registers and Configuration bits are

transferred to the DAC outputs.

When the DAC’s voltage reference is configured as the

device V_DD, the V_REFpin is disconnected from the

internal circuit.

The pin is level-sensitive, so writing to the Volatile

Wiper registers and Configuration bits, while it is being

held at V_IL, will trigger an immediate change in the

outputs.

When the DAC’s voltage reference is configured as the

internal band gap, the V_REFpin’s drive capability is min-

imal, so the output signal should be buffered.

The HVC pin allows the device’s nonvolatile user Con-

figuration bits to be programmed when the voltage on

the pin is greater than the V_IHHentry voltage.

There are two V_REFpins, each corresponding to a

group of output channels. V_REF0is connected to even

channels: 0-6, while V_REF1is connected to odd chan-

nels: 1-7. See Section 5.2 “Voltage Reference Selec-

tion” and Register 4-2 for more details on the

Configuration bits.

2

3.6

I C - Serial Clock Pin (SCL)

The SCL pin is the serial clock pin of the I²C interface.

The MCP47FXBX4/8 I²C interface only acts as a slave

and the SCL pin accepts only external serial clocks.

The input data from the master device is shifted into the

SDA pin on the rising edges of the SCL clock and

output from the device occurs at the falling edges of the

SCL clock. The SCL pin is an open-drain, N-channel

driver. Therefore, it needs an external pull-up resistor

from the V_DDline to the SCL pin. Refer to Section 6.0

“I²C Serial Interface Module” for more details on the

I²C serial interface communication.

 2020 Microchip Technology Inc.

DS20006368A-page 51

MCP47FXBX4/8

2

3.7

I C - Serial Data Pin (SDA)

3.9

No Connect (NC)

The SDA pin is the serial data pin of the I²C interface.

The SDA pin is used to write or read the DAC registers

and Configuration bits. The SDA pin is an open-drain,

N-channel driver. Therefore, it needs an external

pull-up resistor from the V_DDline to the SDA pin. Except

for Start and Stop conditions, the data on the SDA pin

must be stable during the high period of the clock. The

High or Low state of the SDApin can only change when

the clock signal on the SCL pin is low. See Section 6.0

“I²C Serial Interface Module”.

The NC pins are not connected to the device.

3.10 Exposed Pad

This pad is conductively connected to the device's

substrate. It should be tied to the same potential as the

V_SSpin (or left unconnected). This pad could be used

to assist in heat dissipation for the device, when con-

nected to a PCB heat sink. The pad is only present on

the VQFN package.

3.8

A0 and A1 Slave Address Bits

These pins control the last two bits of the I²C address.

Connect them to V_DDto make the corresponding

address bit a ‘1’, or to V_SSfor a ‘0’. See Section 6.8

“Device I²C Slave Addressing” and Register 4-5 for

more details.

DS20006368A-page 52

 2020 Microchip Technology Inc.

MCP47FXBX4/8

4.1

Power-on Reset/Brown-out Reset

(POR/BOR)

4.0

GENERAL DESCRIPTION

The MCP47FXBX4 (MCP47FXB04, MCP47FXB14,

and MCP47FXB24) devices are quad-channel voltage

output devices. The MCP47FXBX8 (MCP47FXB08,

MCP47FXB18 and MCP47FXB28) devices are octal-

channel voltage output devices.

The internal POR/BOR circuit monitors the power

supply voltage (V_DD) during operation. This circuit

ensures correct device start-up at system power-up

and power-down events. The device’s RAM retention

voltage (V_RAM) is lower than the POR/BOR voltage trip

point (V_POR/V_BOR). The maximum V_POR/V_BORvoltage

is less than 1.8V.

These devices are offered with 8-bit (MCP47FXB0X),

10-bit (MCP47FXB1X) and 12-bit (MCP47FXB2X) res-

olutions and include nonvolatile memory (EEPROM),

an I²C serial interface and two write Latch pins (LAT0,

LAT1) to control the update of the written DAC value to

the DAC output pin.

POR occurs as the voltage rises (typically from 0V),

while BOR occurs as the voltage falls (typically from

V_DD(MIN)or higher).

The devices use a resistor ladder architecture. The

resistor ladder DAC is driven from a software-

selectable voltage reference source. The source can

be either the device’s internal V_DD, an external V_REF

pin voltage (buffered or unbuffered), or an internal

band gap voltage source.

The POR and BOR trip points are at the same voltage and

the condition is determined by whether the V_DDvoltage is

rising or falling (see Figure 4-1). What occurs is different

depending on whether the reset is a POR or BOR.

When

V_POR/V_BOR< V_DD< 2.7V,

the

electrical

performance may not meet the data sheet

specifications. In this region, the device is capable of

reading and writing to its EEPROM and reading and

writing to its volatile memory if the proper serial

command is executed.

The DAC output is buffered with a low power and

precision output amplifier (op amp). This output

amplifier provides a rail-to-rail output with low offset

voltage and low noise. The gain (1x or 2x) of the out-

put buffer is software configurable.

This device family also has user-programmable non-

volatile memory (EEPROM) option, which allows the

user to save the desired POR/BOR value of the DAC

register and device Configuration bits.

High-voltage lock bits can be used to ensure that the

device’s output settings are not accidentally modified.

The device operates from a single-supply voltage. This

voltage is specified from 2.7V to 5.5V for full specified

operation, and from 1.8V to 5.5V for digital operation.

The device can operate between 1.8V and 2.7V, but its

analog performance is significantly reduced; therefore,

most device parameters are not specified for this

range.

The main functional blocks are:

• Power-on Reset/Brown-out Reset (POR/BOR)

• Device Memory

• Resistor Ladder

• Output Buffer/V_OUTOperation

• Internal Band Gap

• I²C Serial Interface Module

 2020 Microchip Technology Inc.

DS20006368A-page 53

MCP47FXBX4/8

4.1.1

POWER-ON RESET

4.1.2

BROWN-OUT RESET

The Power-on Reset is the case where the V_DDhas

power applied to it, ramping up from the V_SSvoltage

level. As the device powers up, the V_OUTpin floats to

an unknown value. When V_DDis above the transistor

threshold voltage of the device, the output starts to be

pulled low. After the V_DDis above the POR/BOR trip

point (V_BOR/V_POR), the resistor network’s wiper is

loaded with the POR value (midscale). The volatile

memory determines the analog output (V_OUT) pin volt-

age. After the device is powered up, the user can

update the device’s memory.

The Brown-out Reset occurs when a device has power

applied to it and that power (voltage) drops below the

specified range.

When the falling V_DDvoltage crosses the V_PORtrip

point (BOR event), the following occurs:

• The serial interface is disabled.

• EEPROM writes are disabled.

• The device is forced into a Power-Down state

(PDnB:PDnA = ‘11’). Analog circuitry is turned off.

• The volatile DAC register is forced to 000h.

When the rising V_DDvoltage crosses the V_PORtrip

point, the following occurs:

• Volatile Configuration bits VRnB:VRnA and Gx

are forced to ‘0’.

• The nonvolatile DAC register value is latched into

volatile DAC register.

If the V_DDvoltage decreases below the V_RAMvoltage,

all volatile memory may become corrupted.

• The nonvolatile Configuration bit values are

latched into volatile Configuration bits.

As the voltage recovers above the V_POR/V_BORvoltage,

see Section 4.1.1 “Power-on Reset”.

• The POR Status bit is set (‘1’).

Serial commands not completed due to a brown-out

condition may cause the memory location (volatile and

nonvolatile) to become corrupted.

• The reset delay timer (t_PORD) starts; when the

reset delay timer (t_PORD) times out, the I²C serial

interface is operational. During this delay time, the

I²C interface will not accept commands.

Figure 4-1 illustrates the conditions for power-up and

power-down events under typical conditions.

• The Device Memory Address pointer is forced to

00h.

The Analog Output (V_OUT) state is determined by the

state of the volatile Configuration bits and the DAC reg-

ister. This is called a Power-on Reset (event).

Figure 4-1 illustrates the conditions for power-up and

power-down events under typical conditions.

POR Starts Reset Delay Timer;

After it Times Out, the Serial

Default Device Configuration

Latched into Volatile Configura-

tion Bits and DAC Register.

POR Status Bit is Set (‘1’)

Interface can Operate (if V_DD

V

)

DD(MIN)

BOR,

VolatileMemoryRetains

Volatile DAC Register = 000h

Volatile VRnB:VRnA = ‘00’

Volatile Gx = ‘0’

Data Value

POR Forced

Active

T_PORD

Volatile PDnB:PDnA = ‘11’

V_DD(MIN)

V_POR

Volatile Memory

becomes Corrupted

V_BOR

V_RAM

Device in Unknown

State

Device in

Unknown

State

Device in

Power-

Down

Normal Operation

Below Min.

Device

inPOR

State

Operating

Voltage

State

FIGURE 4-1:

Power-On/Brown-Out Reset Operation.

DS20006368A-page 54

 2020 Microchip Technology Inc.

MCP47FXBX4/8

4.2.3

DEVICE CONFIGURATION

MEMORY

4.2

Device Memory

User memory includes the following types:

There are up to seventeen nonvolatile user bits that are

not directly mapped into the address space. These

nonvolatile device Configuration bits control the follow-

ing functions:

• Volatile Register Memory (RAM)

• Nonvolatile Register Memory

• Device Configuration Memory

Each memory address is 16 bits wide. There are up to

17 nonvolatile user control bits that do not reside in

memory-mapped register space (see Section 4.2.3

“Device Configuration Memory”).

• WiperLock technology for DAC registers and Con-

figuration (2 bits per DAC)

• I²C Slave Address Write Protect (Lock)

The STATUS register shows the states of the device

WiperLock technology Configuration bits. The STA-

TUS register is described in Register 4-6.

4.2.1

VOLATILE REGISTER MEMORY

(RAM)

There are up to twelve volatile memory locations:

The operation of WiperLock technology is discussed in

Section 4.2.6 “WiperLock Technology”, while I²C

Slave Address Write Protect is discussed in

Section 4.2.7 “I2C Slave Address Write Protect”.

• DAC0 through DAC7 Output Value registers

• V_REFSelect register

• Power-Down Configuration register

• Gain and STATUS register

4.2.4

READ commands of

unimplemented bits as ‘0’.

UNIMPLEMENTED REGISTER BITS

• WiperLock Technology STATUS register

a

valid location will read

The volatile memory starts functioning when the

device V_DDis at (or above) the RAM retention voltage

(V_RAM). The volatile memory will be loaded with the

default device values when the V_DDrises across the

V_POR/V_BORvoltage trip point.

4.2.5

UNIMPLEMENTED (RESERVED)

LOCATIONS

Normal (voltage) commands (READ or WRITE) to any

unimplemented memory address (reserved) will result

in a command error condition (NACK). READ com-

mands of a reserved location will read bits as ‘1’.

4.2.2

NONVOLATILE REGISTER

MEMORY

This device family uses the nonvolatile memory for the

DAC output value and Configuration registers:

High-Voltage commands (enable or disable) to any

unimplemented Configuration bits will result in a

command error condition (NACK).

• Nonvolatile DAC0 through DAC7 Output Value

registers

4.2.5.1

Default Factory POR Memory State

of Nonvolatile Memory (EEPROM)

• Nonvolatile V_REFSelect register

• Nonvolatile Power-Down Configuration register

• Nonvolatile Gain and I²C Address register

Table 4-2 shows the default factory POR initialization

of the device memory map for the 8, 10 and 12-bit

devices. In case of volatile memory devices

(MCP47FVBXX), the factory default values cannot be

modified.

The nonvolatile memory starts functioning below the

device’s V_POR/V_BORtrip point, and is loaded into the

corresponding volatile registers whenever the device

rises above the POR/BOR voltage trip point.

The device starts writing the nonvolatile (EEPROM)

memory location at the completion of the serial inter-

face command, after the Acknowledge pulse of the

WRITESingle command. Continuous write commands

addressing the nonvolatile memory are not permitted.

Note:

The volatile memory locations will be

determined by the nonvolatile memory

states (registers and device Configuration

bits).

Note:

When the nonvolatile memory is written,

the corresponding volatile memory is not

modified.

Nonvolatile DAC registers enable the stand-alone

operation of the device (without microcontroller control)

after being programmed to the desired value.

 2020 Microchip Technology Inc.

DS20006368A-page 55

MCP47FXBX4/8

TABLE 4-1:

MCP47FXBX4/8 MEMORY MAP

Function

00h Volatile DAC0 Register

01h Volatile DAC1 Register

02h Volatile DAC2 Register

03h Volatile DAC3 Register

04h Volatile DAC4 Register

05h Volatile DAC5 Register

06h Volatile DAC6 Register

07h Volatile DAC7 Register

CL0

CL1

CL2

CL3

CL4

CL5

CL6

CL7

—

Y

10h Nonvolatile DAC0 Register

11h Nonvolatile DAC1 Register

12h Nonvolatile DAC2 Register

13h Nonvolatile DAC3 Register

14h Nonvolatile DAC4 Register

15h Nonvolatile DAC5 Register

16h Nonvolatile DAC6 Register

17h Nonvolatile DAC7 Register

DL0

DL1

DL2

DL3

DL4

DL5

DL6

DL7

—

Y

—

Y

—

Y

08h

V

Register

18h Nonvolatile V

Register

REF

09h Power-Down Register

—

Y

19h Nonvolatile Power-Down

—

Y

Register

2

0Ah Gain and STATUS Register

—

Y

1Ah NV Gain and I C 7-bits Slave SALCK

Address

Y

0Bh WiperLock™ Technology

STATUS Register

1Bh Reserved

—

Volatile Memory Address Range

Nonvolatile Memory Address Range

Note 1: Device Configuration Memory bits require a high-voltage enable or disable command

(LATn = V ) to modify the bit value.

IHH

TABLE 4-2:

FACTORY DEFAULT POR/BOR VALUES

POR/BOR Value

Function

00h Volatile DAC0 Register

01h Volatile DAC1 Register

02h Volatile DAC2 Register

03h Volatile DAC3 Register

04h Volatile DAC4 Register

05h Volatile DAC5 Register

06h Volatile DAC6 Register

07h Volatile DAC7 Register

7Fh

1FFh 7FFh

3FFh FFFh

10h Nonvolatile DAC0 Register

11h Nonvolatile DAC1 Register

12h Nonvolatile DAC2 Register

13h Nonvolatile DAC3 Register

14h Nonvolatile DAC4 Register

15h Nonvolatile DAC5 Register

16h Nonvolatile DAC6 Register

17h Nonvolatile DAC7 Register

7Fh

1FFh 7FFh

3FFh FFFh

7Fh

FFh

7Fh

FFh

08h

V

Register

0000h 0000h 0000h

18h Nonvolatile V

Register

REF

0000h 0000h 0000h

REF

09h Power-Down Register

19h Nonvolatile Power-Down

Register

2

0Ah Gain and STATUS Register 0080h 0080h 0080h

1Ah NV Gain and I C 7-bit Slave 00E0h 00E0h 00E0h

(1)

Address

(2)

0Bh WiperLock™ Technology

STATUS Register

0000h 0000h 0000h

1Bh Reserved

—

Volatile Memory Address Range

Nonvolatile Memory Address Range

2

Note 1: Default I C 7-bit Slave Address is ‘110 0000’ and the SALCK bit is enabled (‘1’).

2: READor WRITE commands to a reserved memory location will generate a NACK.

DS20006368A-page 56

 2020 Microchip Technology Inc.

MCP47FXBX4/8

4.2.6

WIPERLOCK TECHNOLOGY

Note:

During device communication, if the

device address/command combination is

invalid or an unimplemented address is

specified, the MCP47FXBX4/8 will NACK

that byte. To reset the I²C state machine,

the I²C communication must detect a Start

bit.

The MCP47FXBX4/8 WiperLock technology allows

application-specific device settings (DAC register and

configuration) to be secured without requiring the use

of an additional write-protect pin. There are two Con-

figuration bits (DLn:CLn) for each DAC channel (DAC0

through DAC7).

Dependent on the state of the DLn:CLn Configuration

bits, WiperLock technology prevents the serial

commands from the following actions on the DACn

registers and bits:

4.2.6.1

POR/BOR Operation with

WiperLock Technology Enabled

The WiperLock Technology state is not affected by a

POR/BOR event. A POR/BOR event will load the

volatile DACn register values with the nonvolatile or

default factory values (in case of volatile memory only

devices).

• Writing to the specified volatile DACn register

memory location

• Writing to the specified nonvolatile DACn register

memory location

• Writing to the specified volatile DACn Configura-

tion bits

4.2.7

I²C SLAVE ADDRESS WRITE

PROTECT

• Writing to the specified nonvolatile DACn

Configuration bits

The MCP47FEBX4/8 I²C Slave Address is stored in the

EEPROM memory. This allows the address to be mod-

ified to the application’s requirement. To ensure that the

I²C Slave address is not unintentionally modified, the

memory has a high-voltage write protect bit. This Con-

figurations bit is shown in Table 4-3.

Each pair of these Configuration bits controls one of

the four modes. These modes are shown in Table 4-4.

The addresses for the Configuration bits are shown in

Table 4-4.

To modify the Configuration bits, the HVC pin must be

forced to the V_IHHstate and then an enable or disable

command must be received for the desired pair of

DAC register addresses.

Note:

To modify the SALCK bit, the Enable or

Disable command specifies address 1Ah.

TABLE 4-3:

SALCK FUNCTIONAL

DESCRIPTION

Example: To modify the CL0 bit, the enable or disable

command specifies address 00h, while to modify the

DL0 bit, the enable or disable command specifies

address 10h.

SALCK Operation

1

The nonvolatile I²C Slave Address bits

(ADD6:ADD2) are locked

The nonvolatile I²C Slave Address bits

(ADD6:ADD2) are unlocked

Refer to Section 7.4.2 “Enable Configuration Bit

(High-Voltage)” and Section 7.4.3 “Disable Config-

uration Bit (High-Voltage)” commands for operation.

0

TABLE 4-4:

DLn:CLn⁽¹⁾

WIPERLOCK™ TECHNOLOGY CONFIGURATION BITS - FUNCTIONAL DESCRIPTION

Register/Bits

DACn Wiper

Volatile Nonvolatile Volatile Nonvolatile

DACn Configuration⁽¹⁾

Comments

11

10

Locked

All DACn registers are locked.

Unlocked

All DACn registers are locked, except for volatile

DACn Configuration registers.

This allows operation of Power-Down modes.

01

00

Unlocked

Locked

Unlocked

Locked

Volatile DACn registers unlocked, nonvolatile

DACn registers locked.

Unlocked

Unlocked All DACn registers are unlocked.

Note 1: The state of these Configuration bits (DLn:CLn) is reflected in WLnB:WLnA bits, as shown in Register 4-6.

DAC Configuration bits include Voltage Reference Control bits (VRnB:VRnA), Power-Down Control bits

(PDnB:PDnA), and Output Gain bits (Gx).

 2020 Microchip Technology Inc.

DS20006368A-page 57

MCP47FXBX4/8

4.2.8

DEVICE REGISTERS

Register 4-1 shows the format of the DAC Output

Value registers for both volatile and nonvolatile mem-

ory locations. These registers will be either 8 bits, 10

bits, or 12 bits wide. The values are right justified.

REGISTER 4-1:

DAC0 TO DAC7 OUTPUT VALUE REGISTERS

ADDRESSES 00H THROUGH 07H/10H THROUGH 17H

(VOLATILE/NONVOLATILE)

R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n

U-0

—

U-0

—

U-0

—

U-0

—

12-bit

10-bit

8-bit

D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00

(1)

—

D09 D08 D07 D06 D05 D04 D03 D02 D01 D00

(1)

—

D07 D06 D05 D04 D03 D02 D01 D00

bit 0

bit 15

Legend:

R = Readable bit

-n = Value at POR

= 12-bit device

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

= 10-bit device

= 8-bit device

12-bit

10-bit

8-bit

bit 15-12 bit 15-10 bit 15-8 Unimplemented: Read as ‘0’

bit 11-0

—

bit 9-0

—

D11-D00: DAC Output Value - 12-bit devices

FFFh =Full-Scale output value

7FFh =Mid-Scale output value

000h =Zero-Scale output value

—

D09-D00: DAC Output Value - 10-bit devices

3FFh =Full-Scale output value

1FFh =Mid-Scale output value

000h =Zero-Scale output value

—

bit 7-0

D07-D00: DAC Output Value - 8-bit devices

FFh =Full-Scale output value

7Fh =Mid-Scale output value

000h=Zero-Scale output value

Note 1: Unimplemented bit, read as ‘0’.

DS20006368A-page 58

 2020 Microchip Technology Inc.

MCP47FXBX4/8

Register 4-2 shows the format of the Voltage

Reference Control register. Each DAC has two bits to

control the source of the DAC’s voltage reference. This

register is for both volatile and nonvolatile memory

locations.

REGISTER 4-2:

VOLTAGE REFERENCE (VREF) CONTROL REGISTER

ADDRESSES 08H AND 18H (VOLATILE/NONVOLATILE)

R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n

Octal VR7B VR7A VR6B VR6A VR5B VR5A VR4B VR4A VR3B VR3A VR2B VR2A VR1B VR1A VR0B VR0A

(1)

Quad

—

VR3B VR3A VR2B VR2A VR1B VR1A VR0B VR0A

bit 0

bit 15

Legend:

R = Readable bit

-n = Value at POR

= Quad-channel device

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

= Octal-channel device

Octal

Quad

bit 15-8 Unimplemented: Read as ‘0’

bit 15-0 bit 7-0 VRnB-VRnA: DAC Voltage Reference Control bits

—

11=V_REFpin (buffered); V_REFbuffer enabled

10=V_REFpin (unbuffered); V_REFbuffer disabled

01=Internal band gap (1.22V typical); V_REFbuffer enabled

V_REFvoltage driven when powered down

00=V_DD(unbuffered); V_REFbuffer disabled

Use this state with Power-Down bits for lowest current.

Note 1: Unimplemented bit, read as ‘0’.

 2020 Microchip Technology Inc.

DS20006368A-page 59

MCP47FXBX4/8

Register 4-3 shows the format of the Power-Down

Control register. Each DAC has two bits to control the

Power-Down state of the DAC. This register is for both

volatile and nonvolatile memory locations.

REGISTER 4-3:

POWER-DOWN CONTROL REGISTER

(VOLATILE/NONVOLATILE) (ADDRESSES 09h, 19h)

R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n

Octal PD7B PD7A PD6B PD6A PD5B PD5A PD4B PD4A PD3B PD3A PD2B PD2A PD1B PD1A PD0B PD0A

(1)

Quad

—

PD0B PD0A PD0B PD0A PD0B PD0A PD0B PD0A

bit 0

bit 15

Legend:

R = Readable bit

-n = Value at POR

= Quad-channel device

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

= Octal-channel device

Octal

Quad

bit 15-8 Unimplemented: Read as ‘1’

bit 15-0 bit 7-0

PDnB-PDnA: DAC Power-Down Control bits⁽²⁾

—

11=Powered Down - V_OUTis open circuit

10=Powered Down - V_OUTis loaded with a 125 k resistor to ground

01=Powered Down - V_OUTis loaded with a 1 k resistor to ground

00=Normal Operation (not powered down)

Note 1: Unimplemented bit, read as ‘0’.

2: See Table 5-4 for more details.

DS20006368A-page 60

 2020 Microchip Technology Inc.

MCP47FXBX4/8

Register 4-4 shows the format of the volatile Gain

Control and System STATUS register. Each DAC has

one bit to control the gain of the DAC and three Status

bits.

REGISTER 4-4:

GAIN CONTROL AND SYSTEM STATUS REGISTER

ADDRESS 0Ah (VOLATILE)

R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/C-1

R-0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

Octal

Quad

G7

G6

G5

G4

G3

G2

G1

G0 POR EEWA

(1)

—

bit 15

bit 0

Legend:

R = Readable bit

-n = Value at POR

= Quad-channel device

W = Writable bit

‘1’ = Bit is set

C = Clear-able bit

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

x = Bit is unknown

= Octal-channel device

Octal

Quad

bit 15-12 Unimplemented: Read as ‘0’

bit 11-8 Gn: DAC Channel n Output Driver Gain Control bit

—

bit 15-8

1

0

= 2x Gain

= 1x Gain

bit 7

POR: Power-on Reset (Brown-out Reset) Status bit

This bit indicates if a POR or BOR event has occurred since the last READcommand of

this register. Reading this register clears the state of the POR Status bit.

1

= A POR (BOR) event has occurred since the last read of this register. Reading this register

clears this bit.

0 = A POR (BOR) event has not occurred since the last read of this register.

bit 6

EEWA: EEPROM Write Active Status bit

This bit indicates if the EEPROM Write Cycle is occurring.

1

=

An EEPROM Write Cycle is currently occurring. Only serial commands to the volatile

memory are allowed.

0 = An EEPROM Write Cycle is NOT currently occurring.

bit 5-0

Unimplemented: Read as ‘0’

Note 1: Unimplemented bit, read as ‘0’.

 2020 Microchip Technology Inc.

DS20006368A-page 61

MCP47FXBX4/8

Register 4-5 shows the format of the nonvolatile Gain

Control register. Each DAC has one bit to control the

gain of the DAC.

REGISTER 4-5:

GAIN CONTROL AND I²C SLAVE ADDRESS REGISTER

ADDRESS 1Ah (NONVOLATILE)

R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n

R

R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n

Octal

Quad

G7

G6

G5

G4

G3

G2

G1

G0 ADLCK ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0

bit 0

(1)

—

bit 15

Legend:

R = Readable bit

-n = Value at POR

= Quad-channel device

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

= Octal-channel device

Octal

Quad

bit 15-12 Unimplemented: Read as ‘0’

bit 15-8 bit 11-8 Gn: DACn Output Driver Gain Control bits

—

1

0

= 2x Gain

= 1x Gain

bit 7

ADLCK: I²C Address Lock Status bit (reflects the state of the high-voltage SALCK bit).

1= I²C Slave Address is Locked (requires HV command to disable, so I²C address can be

changed)

0= I²C Slave Address is NOT Locked, the nonvolatile I²C Slave Address can be changed

bit 6-0

ADD6-ADD0: I²C 7-bit Slave Address bits.

For nonvolatile devices, the ADD6-ADD2 bits form the upper five bits of the I²C address and

can be user-modified.

For volatile devices, the upper five bits of the I²C address are fixed at '0b11000' and cannot be

changed by the user. Other values could be available on demand, contact a sales representa-

tive for more information.

The lower two bits are determined by the state of the A0 and A1 pins. A V_IHlevel corresponds

to a bit value of '1', while a V_ILlevel to a '0'. Leaving the pins unconnected is the equivalent of a

'0' bit value.

Note 1: Unimplemented bit, read as ‘0’.

DS20006368A-page 62

 2020 Microchip Technology Inc.

MCP47FXBX4/8

Register 4-6 shows the format of the DAC WiperLock

technology STATUS register.

REGISTER 4-6:

DAC WIPERLOCK™ TECHNOLOGY STATUS REGISTER

(VOLATILE, ADDRESS 0BH)

(1)

R-0

WL7B WL7A WL6B WL6A WL5B WL5A WL4B WL4A WL3B WL3A WL2B WL2A WL1B WL1A WL0B WL0A

Octal

Quad

(2)

—

WL3B WL3A WL2B WL2A WL1B WL1A WL0B WL0A

bit 0

bit 15

Legend:

R = Readable bit

-n = Value at POR

= Quad-channel device

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

= Octal-channel device

Octal

Quad

bit 15-8 Unimplemented: Read as ‘0’

—

bit 15-0 bit 7-0

WLnB-WLnA: WiperLock™ Technology Status bits: These bits reflect the state of the DLn:CLn

nonvolatile Configuration bits.

11 =DAC Wiper and DAC Configuration (volatile and nonvolatile registers) are locked

(DLn = CLn = Enabled).

10 =DAC Wiper (volatile and nonvolatile) and DAC Configuration (nonvolatile registers) are

locked (DLn = Enabled; CLn = Disabled).

01 =DAC Wiper (nonvolatile) and DAC Configuration (nonvolatile registers) are locked

(DLn = Disabled; CLn = Enabled).

00=DAC Wiper and DAC Configuration are unlocked (DLn = CLn = Disabled).

Note 1: POR value depends on the programmed values of the DLn:CLn Configuration bits. The devices are

shipped with a default DLn:CLn Configuration bit state of ‘0’.

2: Unimplemented bit, read as ‘0’.

 2020 Microchip Technology Inc.

DS20006368A-page 63

MCP47FXBX4/8

NOTES:

DS20006368A-page 64

 2020 Microchip Technology Inc.

MCP47FXBX4/8

The functional blocks of the DAC include:

5.0

DAC CIRCUITRY

• Resistor Ladder

The Digital-to-Analog Converter circuitry converts a

digital value into its analog representation. The

description shows the functional operation of the device.

• Voltage Reference Selection

• Output Buffer/V_OUTOperation

• Internal Band Gap

The DAC circuit uses a resistor ladder implementation.

Devices have up to eight DACs.

• Latch Pins (LATn)

• Power-Down Operation

Figure 5-1 shows the functional block diagram for the

MCP47FXBX4/8 DAC circuitry.

Power-Down

Operation

V_DD

PDnB:PDnA and

VRnB:VRnA

Internal Band Gap

V_DD

Voltage

Reference

Selection

V_REF

VRnB:VRnA and

PDnB:PDnA

Band Gap

(1.22V typical)

V_DD

PDnB:PDnA

VRnB:VRnA

Power-Down

Operation

V

A (RL)

RL

DAC

Output

Selection

V_DD

R_{S(2 )}

n

PDnB:PDnA

R_S(2

n

- 1)

V_W

R_S(2n _{- 2)}

V_OUT

R_S(2n _{- 3)}

PDnB:PDnA

Gain

(1x or 2x)

R_RL

(~120 k)

Output Buffer/V_OUT

Operation

Power-Down

Operation

R_S(2)

R_S(1)

DAC Register Value

V_W= ---------------------------------------------------------------------  V_RL

# Resistor in Resistor Ladder

B

Where:

# Resistors in Resistor Ladder =

Resistor Ladder

256 (MCP47FXB0X)

1024 (MCP47FXB1X)

4096 (MCP47FXB2X)

FIGURE 5-1:

MCP47FXBX4/8 DAC Module Block Diagram.

 2020 Microchip Technology Inc.

DS20006368A-page 65

MCP47FXBX4/8

Equation 5-1 shows the calculation for the step

resistance:

5.1

Resistor Ladder

The resistor ladder is a digital potentiometer with the B

Terminal internally grounded and the A Terminal

connected to the selected reference voltage (see

Figure 5-2). The volatile DAC register controls the

wiper position. The wiper voltage (V_W) is proportional to

the DAC register value divided by the number of resis-

tor elements (R_S) in the ladder (256, 1024 or 4096)

related to the V_RLvoltage.

EQUATION 5-1:

R_SCALCULATION

R_RL

R_S= -------------

8-bit Device

256

R_RL

R_S= ----------------

10-bit Device

12-bit Device

1024

The output of the resistor network will drive the input of

an output buffer.

R_RL

R_S= ----------------

4096

V

RL

DAC

The maximum wiper position is 2ⁿ– 1,

while the number of resistors in the

resistor ladder is 2ⁿ. This means that

when the DAC register is at full scale,

there is one resistor element (R_S)

between the wiper and the V_RLvoltage.

Register

Note:

PDnB:PDnA

R_{S(2 )}

n

(1)

2ⁿ- 1

2ⁿ- 2

R_W

R_S(2

n

( )

1

- 1)

If the unbuffered V_REFpin is used as the V_RLvoltage

source, this voltage source should have a low output

impedance.

R_S(2n _{- 2)}

( )

1

R_W

2ⁿ- 3

When the DAC is powered down, the resistor ladder is

disconnected from the selected reference voltage.

V_W

R_S(2n _{- 3)}

( )

1

R_W

5.2

Voltage Reference Selection

R_RL

2

The resistor ladder has up to four sources for the

reference voltage. Two user control bits (VRnB:VRnA)

are used to control the selection, with the selection con-

nected to the V_RLnode (see Figure 5-3 and Figure 5-4).

R_S(2)

( )

1

0

R_S(1)

( )

1

R_W

VRnB:VRnA

V_REF

Analog Mux

V_DD

Band Gap

Note 1:

The analog switch resistance (R_W)

does not affect performance due to the

voltage divider configuration.

V_RL

Buffer

FIGURE 5-2:

Resistor Ladder Model.

FIGURE 5-3:

Resistor Ladder Reference

The resistor network is made of these three parts:

Voltage Selection Block Diagram.

• Resistor ladder (string of R_Selements)

• Wiper switches

• DAC register decode

The four voltage source options for the resistor ladder

are:

1. V_DDpin voltage

The resistor ladder (R_RL) has a typical impedance of

approximately 120 k. This resistance may vary from

device to device by up to ±20%. Since this is a voltage

divider configuration, the actual R_RLresistance does

2. Internal voltage reference (V_BG

3. _REFpin voltage unbuffered

4. V_REFpin voltage internally buffered

)

V

not affect the output given a fixed voltage at V_RL

.

DS20006368A-page 66

 2020 Microchip Technology Inc.

MCP47FXBX4/8

The selection of the voltage is specified with the volatile

VRnB:VRnA Configuration bits (see Register 4-2).

There are nonvolatile and volatile VRnB:VRnA Configu-

ration bits. On a POR/BOR event, the state of the non-

volatile VRnB:VRnA Configuration bits is latched into the

volatile VRnB:VRnA Configuration bits.

5.2.2

UNBUFFERED MODE

The V_REFpin voltage may be from V_SSto V_DD

.

Note 1: The voltage source should have a low

output impedance. If the voltage source

has a high output impedance, then the

voltage on the V_REFpin is lower than

expected. The resistor ladder has a

typical impedance of 140 k and a

typical capacitance of 29 pF.

When the user selects the V_DDas reference, the V_REF

pin voltage is not connected to the resistor ladder.

V_DD

2: If the V_REFpin is tied to the V_DDvoltage,

the V_DDmode (VRnB:VRnA = ‘00’) is

recommended.

PDnB:PDnA and

VRnB:VRnA

PDnB:PDnA and

5.2.3

BAND GAP MODE

VRnB:VRnA

(1)

If the internal band gap is selected, then the external

V_REFpin should not be driven and should only use

high-impedance loads.

Band Gap

(1.227V typical)

V_REF

V_RL

The band gap output is buffered, but the internal

switches limit the current that the output should source

to the V_REFpin. The resistor ladder buffer is used to

drive the band gap voltage for the cases of multiple

DAC outputs. This ensures that the resistor ladders are

always properly sourced when the band gap is

selected.

V_DD

5.3

Internal Band Gap

PDnB:PDnA and

VRnB:VRnA

The internal band gap is designed to drive the resistor

ladder buffer.

Note 1: The band gap voltage (V_BG) is 1.22V

typical. The band gap output goes

through the buffer with a 2x gain to

create the V_RLvoltage. See Table 5-1

for additional information on the band

gap circuit.

The resistance of a resistor ladder (R_RL) is targeted to

be 140 k (40 k), which means a minimum resis-

tance of 100 k.

The band gap selection can be used across the V_DD

voltages while maximizing the V_OUTvoltage ranges.

For V_DDvoltages below the 2 × Gain × V_BGvoltage, the

output for the upper codes will be clipped to the V_DD

voltage. Table 5-1 shows the maximum DAC register

code given device V_DDand Gain bit setting.

FIGURE 5-4:

Reference Voltage

Selection Implementation Block Diagram.

If the V_REFpin is selected, then a selection has to be

made between the Buffered and Unbuffered mode.

TABLE 5-1:

V_OUTUSING BAND GAP

Max DAC Code⁽¹⁾

5.2.1

BUFFERED MODE

Comment

The V_REFpin voltage may be from 0.01V to V_DD

-

12-bit 10-bit 8-bit

0.04V. The input buffer (amplifier) provides low offset

voltage, low noise, and a very high input impedance,

with only minor limitations on the input range and

frequency response.

(2)

1

2

1

2

FFFh 3FFh FFh

V

= 2.44V

OUT(max)

5.5

2.7

= 4.88V

= 2.44V

OUT(max)

Note 1: Any variation or noises on the reference

source can directly affect the DAC output.

The reference voltage needs to be as

clean as possible for accurate DAC

performance.

8CDh 233h 8Ch ~ 0 to 56% range

pin voltage being clipped.

Note 1: Without the V

OUT

2: When V = 1.22V typical.

BG

3: Band gap performance achieves full

2: If the V_REFpin is tied to the V_DDvoltage,

the V_DDmode (VRnB:VRnA = ‘00’) is

recommended.

performance starting from a V of 2.0V.

DD

 2020 Microchip Technology Inc.

DS20006368A-page 67

MCP47FXBX4/8

5.4.2

OUTPUT VOLTAGE

5.4

Output Buffer/V

Operation

OUT

The volatile DAC register values, along with the

device’s Configuration bits, control the analog V_OUT

voltage. The volatile DAC register’s value is unsigned

binary. The formula for the output voltage is given in

Equation 5-2. Table 5-5 shows examples of volatile

DAC register values and the corresponding theoretical

The Output Driver buffers the wiper voltage (V_W) of the

resistor ladder.

The DAC output is buffered with a low power and preci-

sion output amplifier (op amp). This amplifier provides a

rail-to-rail output with low offset voltage and low noise.

The amplifier’s output can drive the resistive and high-

capacitive loads without oscillation. The amplifier provides

a maximum load current which is enough for most pro-

grammable voltage reference applications. See

Section 1.0 “Electrical Characteristics” for the

specifications of the output amplifier.

V

_OUTvoltage for the MCP47FXBX4/8 devices.

EQUATION 5-2: CALCULATING OUTPUT

VOLTAGE (V_OUT

V_RL DAC Register Value

)

V_OUT= ---------------------------------------------------------------------  Gain

# Resistor in Resistor Ladder

Note:

The load resistance must be kept higher

than 5 k for the stable and expected

analog output (to meet electrical

specifications).

Where:

# Resistors in R-Ladder = 4096 (MCP47FXB2X)

1024 (MCP47FXB1X)

256 (MCP47FXB0X)

Figure 5-5 shows the block diagram of the output driver

circuit.

Note:

When Gain = 2 (V_RL= V_REF) and

The user can select the output gain of the output ampli-

fier. The gain options are:

if V_REF> V_DD/2, the V_OUTvoltage will be

limited to V_DD. So if V_REF= V_DD, then the

V_OUTvoltage will not change for volatile

DAC register values mid-scale and greater,

since the op amp is at full-scale output.

a) Gain of 1, when either the V_DD, external V_REF, or

Band Gap mode are used. In case of the Band

Gap mode, the effective gain is 2, see

Section 5.3 “Internal Band Gap”.

b) Gain of 2, when the external V_REFor internal

Band Gap modes are used. In case of the Band

Gap mode, the effective gain is 4, see

Section 5.3 “Internal Band Gap”.

The following events update the DAC register value

and therefore the analog voltage output (V_OUT):

• POR

• BOR

• WRITEcommand

V_DD

The V_OUTvoltage starts driving to the new value after

the event has occurred.

PDnB:PDnA

5.4.3

STEP VOLTAGE (V_S)

The step voltage depends on the device resolution and

the calculated output voltage range. 1 LSb is defined

as the ideal voltage difference between two successive

codes. The step voltage can be easily calculated by

using Equation 5-3 (DAC register value is equal to 1).

Theoretical step voltages are shown in Table 5-2 for

several V_REFvoltages.

V_W

V_OUT

PDnB:PDnA

Gain

(1x or 2x)

EQUATION 5-3:

V_SCALCULATION

FIGURE 5-5:

Output Driver Block Diagram.

V_RL

V_S= ---------------------------------------------------------------------  Gain

# Resistor in Resistor Ladder

5.4.1 PROGRAMMABLE GAIN

The amplifier’s gain is controlled by the Gain (G)

Configuration bit (see Register 4-5) and the V_RL

reference selection.

Where:

# Resistors in R-Ladder = 4096 (12-bit)

1024 (10-bit)

The volatile Gain bit value can be modified by:

• POR events

256 (8-bit)

• BOR events

• I²C WRITEcommands

DS20006368A-page 68

 2020 Microchip Technology Inc.

MCP47FXBX4/8

TABLE 5-2:

5.0

THEORETICAL STEP

VOLTAGE (V_S)⁽¹⁾

5.4.5

DRIVING RESISTIVE AND

CAPACITIVE LOADS

The V_OUTpin can drive up to 100 pF of capacitive load

in parallel with a 5 k resistive load (to meet electrical

specifications).

V_REF

2.7

1.8

1.5

1.0

1.22 mV 659 µV 439 µV 366 µV 244 µV 12-bit

V_S4.88 mV 2.64 mV 1.76 mV 1.46 mV 977 µV 10-bit

19.5 mV 10.5 mV 7.03 mV 5.86 mV 3.91 mV 8-bit

Note 1:When Gain = 1x, V_FS= V_RL, and V_ZS= 0V.

V_OUTdrops slowly as the load resistance decreases

after about 3.5 k. It is recommended to use a load

with R_Lgreater than 5 k.

Driving large capacitive loads can cause stability

problems for voltage feedback op amps. As the load

capacitance increases, the feedback loop’s phase mar-

gin decreases and the closed-loop bandwidth is

reduced. This produces gain peaking in the frequency

response with overshoot and ringing in the step

response. That is, since the V_OUTpin’s voltage does

not quickly follow the buffer’s input voltage (due to the

large capacitive load), the output buffer will overshoot

the desired target voltage. Once the driver detects this

overshoot, it compensates by forcing it to a voltage

below the target. This causes voltage ringing on the

V_OUTpin.

5.4.4

OUTPUT SLEW RATE

Figure 5-6 shows an example of the slew rate for the

V_OUTpin. The slew rate can be affected by the charac-

teristics of the circuit connected to the V_OUTpin.

V_OUT(B)

V_OUT(A)

DACn = A

When driving large capacitive loads with the output buf-

fer, a small series resistor (R_ISO) at the output (see

Figure 5-7) improves the output buffer’s stability (feed-

back loop’s phase margin) by making the output load

resistive at higher frequencies. The bandwidth will be

generally lower than the bandwidth with no capacitive

load.

DACn = B

Time

V

_OUTB– V_OUTA

Slew Rate = --------------------------------------------------

T

FIGURE 5-6:

V_OUTPin Slew Rate.

V_OUT

5.4.4.1

Small Capacitive Load

V_W

R_ISO

R_L

V_CL

With a small capacitive load (C_L), the output buffer’s

current is not affected. But the V_OUTpin’s voltage is not

a step transition from one output value (DAC register

value) to the next output value. The change of the V_OUT

voltage is limited by the output buffer’s characteristics,

so the V_OUTpin voltage will have a slope from the old

voltage to the new one. This slope is fixed for the output

buffer and is referred to as the buffer slew rate (SR_BUF).

C_L

Gain

FIGURE 5-7:

Circuit to Stabilize Output

Buffer for Large Capacitive Loads (C_L).

The R_ISOresistor value for your circuit needs to be

selected. The resulting frequency response peaking

and step response overshoot for this R_ISOresistor

value should be verified on the bench. Modify the

R_ISO’s resistance value until the output characteristics

meet your requirements.

5.4.4.2

Large Capacitive Load

With a larger capacitive load, the slew rate is deter-

mined by two factors:

• The output buffer’s short-circuit current (I_SC

• The V_OUTpin’s external load

)

A method to evaluate the system’s performance is to

inject a step voltage on the V_REFpin and observe the

V_OUTpin’s characteristics.

I_OUTcannot exceed the output buffer’s short-circuit

current (I_SC), which fixes the output buffer slew rate

(SR_BUF). The voltage on the capacitive load, V_CL

,

changes at a rate proportional to I_OUT, which fixes a

capacitive load slew rate (SR_CL).

Note:

Additional insight into circuit design for

driving capacitive loads can be found in

AN884 – “Driving Capacitive Loads with

Op Amps” (DS00884).

The V_CLvoltage slew rate is limited to the slower of the

output buffer’s internally set slew rate (SRBUF) and the

capacitive load slew rate (SR_CL).

 2020 Microchip Technology Inc.

DS20006368A-page 69

MCP47FXBX4/8

5.5

Power-Down Operation

TABLE 5-3:

PDnB PDnA

POWER-DOWN BITS AND

OUTPUT RESISTIVE LOAD

To allow the application to conserve power when the

DAC operation is not required, three Power-Down

modes are available. The Power-Down Configuration

bits (PDnB:PDnA) control the power-down operation

(Figure 5-8 and Table 5-3). On devices with multiple

DACs, each DACs Power-Down mode is individually

controllable. All Power-Down modes do the following:

Function

0

1

0

1

0

1

Normal operation

1 k resistor to ground

125 k resistor to ground

Open circuit

• Turn off most DAC module’s internal circuits (out-

put op amp, resistor ladder, et al.)

Table 5-4 shows the current sources for the DAC based

on the selected source of the DAC’s reference voltage

and if the device is in a normal operating mode or in

one of the Power-Down modes.

• Op amp output becomes high impedance to the

V_OUTpin

• Disconnect the resistor ladder from the Reference

Voltage (V_RL

)

TABLE 5-4:

DAC CURRENT SOURCES

• Retain the value of the volatile DAC register and

Configuration bits and the nonvolatile (EEPROM)

DAC register and Configuration bits

PDnB:A = ‘00’,

PDnB:A  ‘00’,

Device V_DD

Current

VRnB:A =

Source

Depending on the selected Power-Down mode, the fol-

lowing will occur:

00 01 10 11 00 01 10 11

Output

Op Amp

Y

N

• V_OUTpin is switched to one of the two resistive

pull-downs (see Table 5-4):

Resistor

Ladder

Y

N⁽¹⁾

Y

N

N⁽¹⁾

N

- 125 k (typical)

- 1 k (typical)

• Op amp is powered down and the V_OUTpin

becomes high impedance

RL Op Amp

Band Gap

N

Y

N

Y

N

Y

N

Note 1: Current is sourced from the V_REFpin, not

the device V_DD

There is a delay (T_PDE) between the PDnB:PDnA bits

changing from ‘00’ to either ‘01’, ‘10’ or ‘11’ with the op

amp no longer driving the V_OUToutput and the pull-

down resistors sinking current.

.

Section 7.0 “I2C Device Commands” describes the I²C

commands for writing the power-down bits. The com-

mands that can update the volatile PDnB:PDnA bits are:

V_DD

• Write(normal and high-voltage)

• General Call Reset

• General Call Wake-up

PDnB:PDnA

Note:

The I²C serial interface circuit is not

affected by the Power-Down mode. This

circuit remains active in order to receive

any command that might come from the

I²C master device.

V_W

V_OUT

PDnB:PDnA

Gain

(1x or 2x)

FIGURE 5-8:

V_OUTPower-Down Block

Diagram.

In any of the Power-Down modes where the V_OUTpin

is not externally connected (sinking or sourcing

current), the power-down current will typically be

680 nA for a quad-DAC device. As the number of DACs

increases, the device’s power-down current will also

increase.

The Power-Down bits are modified by using a WRITE

command to the volatile Power-Down register, or a

POR event which transfers the nonvolatile

Power-Down register to the volatile Power-Down regis-

ter.

DS20006368A-page 70

 2020 Microchip Technology Inc.

MCP47FXBX4/8

5.5.1

EXITING POWER-DOWN

5.6

DAC Registers, Configuration

Bits, and Status Bits

When the device exits Power-Down mode, the

following occurs:

The MCP47FXBX4/8 device family has both volatile

and nonvolatile (EEPROM) memory options. Table 4-2

shows the volatile and nonvolatile memory and their

interaction due to a POR event.

• Disabled circuits (op amp, resistor ladder, et al.)

are turned on

• The resistor ladder is connected to the selected

Reference Voltage (V_RL

)

There are five Configuration bits, DAC registers, and

two volatile status bits in both the volatile and nonvola-

tile memory. The DAC registers (volatile and nonvola-

tile) will be either twelve bits (MCP47FXB2X), ten bits

(MCP47FEB1X), or eight bits (MCP47FXB0X) wide.

• The selected pull-down resistor is disconnected

• The V_OUToutput will be driven to the voltage

represented by the volatile DAC register’s value

and Configuration bits

When the device is first powered-up, it automatically

uploads the EEPROM memory values or factory

default values (in case of MCP47FVBXX devices) to

the volatile memory. The volatile memory determines

the analog output (V_OUT) pin voltage. After the device

is powered-up, the user can update the memory.

This memory is read and written through the I²C inter-

face. See Section 6.0 “I²C Serial Interface Module”

and Section 7.0 “I2C Device Commands” for more

details on reading and writing the device’s memory.

The V_OUToutput signal requires time as these circuits

are powered up and the output voltage is driven to the

specified value as determined by the volatile DAC

register and Configuration bits.

Note:

Since the op amp and resistor ladder are

powered-off (0V), the op amp’s Input

Voltage (V_W) can be considered 0V. There

is

a

delay (T_PDD

)

between the

PDnB:PDnA bits updating to ‘00’ and the

op amp driving the V_OUToutput. The op

amp’s settling time (from 0V) needs to be

taken into account to ensure the V_OUT

voltage reflects the selected value.

When the nonvolatile memory is written, the device

starts writing the EEPROM cell at the Acknowledge

pulse of the WRITEsingle memory location command.

Register 4-4 shows the operation of the device status

bits and Table 4-2 shows the factory default value of a

POR/BOR event for the device Configuration bits.

The following events change the PDnB:PDnA bits to ‘00’

and therefore exit the Power-Down mode. These are:

• Any I²C WRITEcommand where the PDnB:PDnA

bits are ‘00’

• I²C General Call Wake-up command

• I²C General Call Reset command (if nonvolatile

There are two status bits. These are only in volatile

memory and indicate the status of the device. The POR

bit indicates if the device V_DDis above or below the

POR trip point. During normal operation, this bit should

be ‘1’. The EEWA bit indicates if an EEPROM write

cycle is in progress. While the EEWA bit is ‘1’ (during

the EEPROM writing), all commands are ignored,

except for the READcommand.

PDnB:PDnA bits are ‘00’).

Note:

On quad-channel devices, after issuing a

General Call Wake-up command,

a

current higher than normal will be drawn.

To avoid this issue, on quad-channel

devices, General Call Wake-up should be

followed by

a

General Call Reset

command. No other functionality is

affected.

5.5.2

RESET COMMANDS

When the MCP47FXBX4/8 devices are in the valid

operating voltage range, the I²C General Call Reset

command forces a Reset event. This is similar to the

POR, except that the Reset delay timer is not started.

If the I²C interface bus does not seem to be respon-

sive, the technique shown in Section 8.1.3 “Software

I²C Interface Reset Sequence” can be used to force

the I²C interface to reset.

 2020 Microchip Technology Inc.

DS20006368A-page 71

MCP47FXBX4/8

5.7

Latch Pins (LATn)

Serial Shift Reg.

The Latch pins control when the volatile DAC register

value is transferred to the DAC wiper. This is useful for

applications that need to synchronize the wiper(s)

updates to an external event, such as zero crossing or

updates to the other wipers on the device. The LAT pin

functionality is asynchronous to the serial interface

operation.

Register Address

Write Command

16 Clocks

Vol. DAC Register n

LAT

SYNC

(internal signal)

Transfer

Data

When the LAT pin is high, transfers from the volatile DAC

register to the DAC wiper are inhibited. The volatile DAC

register value(s) can continue to update.

DAC Wiper n

Transfer

Data

LAT SYNC

Comment

When the LAT pin is low, the volatile DAC register value

is transferred to the DAC wiper.

1

0

1

0

1

0

1

0

No Transfer

Note:

This allows the volatile DAC0 through

DAC7 registers to be updated while the

LATn pins are high, and to have outputs

synchronously updated as the LATn pins

are driven low.

Vol. DAC Register n  DAC Wiper n

No Transfer

FIGURE 5-9:

LAT and DAC Interaction.

Since the DAC wiper n is updated from the volatile DAC

register n, all DACs that are associated with a given

LAT pin can be updated synchronously.

Figure 5-9 shows the interaction of the LAT pin and the

loading of the DAC Wiper n (from the volatile DAC

register n). The transfers are level-driven. If the LAT pin

is held low, the corresponding DAC wiper is updated as

soon as the volatile DAC register value is updated.

If the application does not require synchronization, then

this signal should be tied low.

The LAT pin allows the DAC wiper to be updated to an

Figure 5-10 shows two examples of using the LAT pin

to control when the wiper register is updated relative to

the value of a sine wave signal.

external

event

and

have

multiple

DAC

channels/devices updating at a common event.

Case 1: Zero Crossing of Sine Wave to update the volatile DAC0 register (using LAT pin)

Case 2: Fixed Point Crossing of Sine Wave to update the volatile DAC0 register (using LAT pin)

Indicates where LAT pin pulses active (volatile DAC0 register updated)

FIGURE 5-10:

LAT Pin Operation Example.

DS20006368A-page 72

 2020 Microchip Technology Inc.

MCP47FXBX4/8

TABLE 5-5:

Device

DAC INPUT CODE VS. CALCULATED ANALOG OUTPUT (V_OUT) (V_DD= 5.0V)

(3)

LSb

Equation

5.0V/4096 1,220.7

2.5V/4096 610.4

V_OUT

Equation

Volatile DAC

Register Value

Gain

(1)

V_RL

Selection⁽²⁾

µV

V

1111 1111 1111 5.0V

1x

2x⁽²⁾

V_RL (4095/4096)  1

V_RL (4095/4096)  2)

V_RL (2047/4096)  1)

V_RL (2047/4096)  2)

V_RL (1023/4096)  1)

V_RL (1023/4096)  2)

V_RL (0/4096) * 1)

V_RL (0/4096) * 2)

V_RL (1023/1024)  1

V_RL (1023/1024)  2

V_RL (511/1024)  1

V_RL (511/1024)  2

V_RL (255/1024)  1

V_RL (255/1024)  2

V_RL (0/1024)  1

4.998779

2.499390

4.998779

2.498779

1.249390

2.498779

1.248779

0.624390

1.248779

0

2.5V

0111 1111 1111 5.0V

5.0V/4096 1,220.7

2.5V/4096 610.4

1x

2.5V

1x

2x⁽²⁾

0011 1111 1111 5.0V

5.0V/4096 1,220.7

2.5V/4096 610.4

1x

2.5V

1x

2x⁽²⁾

0000 0000 0000 5.0V

5.0V/4096 1,220.7

2.5V/4096 610.4

1x

2.5V

1x

2x⁽²⁾

0

11 1111 1111

01 1111 1111

00 1111 1111

00 0000 0000

1111 1111

5.0V

2.5V

5.0V/1024 4,882.8

2.5V/1024 2,441.4

1x

4.995117

2.497559

4.995117

2.495117

1.247559

2.495117

1.245117

0.622559

1.245117

0

1x

2x⁽²⁾

5.0V

2.5V

5.0V/1024 4,882.8

2.5V/1024 2,441.4

1x

2x⁽²⁾

5.0V

2.5V

5.0V/1024 4,882.8

2.5V/1024 2,441.4

1x

2x⁽²⁾

5.0V

2.5V

5.0V/1024 4,882.8

2.5V/1024 2,441.4

1x

2x⁽²⁾

V_RL (0/1024)  1

0

V_RL (0/1024)  1

0

5.0V

2.5V

5.0V/256 19,531.3

1x

V_RL (255/256)  1

V_RL (255/256)  2

V_RL (127/256)  1

V_RL (127/256)  2

V_RL (63/256)  1

4.980469

2.490234

4.980469

2.480469

1.240234

2.480469

1.230469

0.615234

1.230469

0

2.5V/256

9,765.6

1x

2x⁽²⁾

0111 1111

5.0V

2.5V

5.0V/256 19,531.3

2.5V/256 9,765.6

1x

2x⁽²⁾

0011 1111

5.0V

2.5V

5.0V/256 19,531.3

2.5V/256 9,765.6

1x

2x⁽²⁾

V_RL (63/256)  1

V_RL (63/256)  2

0000 0000

5.0V

2.5V

5.0V/256 19,531.3

2.5V/256 9,765.6

1x

V_RL (0/256)  1

1x

2x⁽²⁾

V_RL (0/256)  1

0

V_RL (0/256)  2

0

Note 1: V_RLis the resistor ladder’s reference voltage. It is independent of the VRnB:VRnA selection.

2: Gain selection of 2x (Gx = ‘1‘) requires the voltage reference source to come from the V_REFpin

(VRnB:VRnA = ‘10‘ or ‘11’) and requires a V_REFpin voltage (or V_RL) ≤ V_DD/2, or from the internal band

gap (VRnB:VRnA = ‘01’).

3: These theoretical calculations do not take into account the offset, gain and nonlinearity errors.

 2020 Microchip Technology Inc.

DS20006368A-page 73

MCP47FXBX4/8

NOTES:

DS20006368A-page 74

 2020 Microchip Technology Inc.

MCP47FXBX4/8

2

6.3

Communication Data Rates

6.0

I C SERIAL INTERFACE

The I²C interface specifies different communication bit

rates. These are referred to as Standard, Fast or High-

Speed modes. The MCP47FXBX4/8 supports these

three modes. The clock rates (bit rate) of these modes

are:

MODULE

The MCP47FXBX4/8’s I²C serial interface module

supports the I²C serial protocol specification. This I²C

interface is a two-wire interface (clock and data).

Figure 6-1 shows a typical I²C interface connection.

• Standard mode: up to 100 kHz (kbit/s)

• Fast mode: up to 400 kHz (kbit/s)

The I²C specification only defines the field types, field

lengths, timings, etc., of a frame. The frame content

defines the behavior of the device. The frame content

(commands) for the MCP47FXBX4/8 is defined in

Section 7.0 “I2C Device Commands”.

• High-Speed mode (HS mode): up to 3.4 MHz

(Mbit/s)

A description on how to enter High-Speed mode is

provided in Section 6.9 “Entering High-Speed (HS)

Mode”.

An overview of the I²C protocol is available in

Section Appendix B: “I²C Serial Interface”.

Typical I²C Interface Connections

6.4

POR/BOR

On a POR/BOR event, the I²C Serial Interface Module

state machine is reset and the device’s memory

address pointer is forced to 00h.

MCP47FXBXX

(Slave)

Host

Controller

(Master)

SCL

SDA

6.5

Device Memory Address

SDA

The memory address is the 5-bit value that provides

the location in the device’s memory that the specified

command will operate on.

Other Devices

Typical I²C Interface.

On a POR/BOR event, the device’s memory address

pointer is forced to 00h.

FIGURE 6-1:

6.1

Overview

The MCP47FXBX4/8 retains the last “Device Memory

Address” received. That is, the MCP47FXBX4/8 does

not “corrupt” the “Device Memory Address” after

repeated Start or Stop conditions.

This section discusses some of the specific

characteristics of the MCP47FXBX4/8’s I²C serial

interface module. This is to assist in the development of

your application.

6.6

General Call Commands

The following sections discuss some of these device-

specific characteristics:

The General Call commands utilize the I²C

specification reserved General Call command address

and command codes. The MCP47FXBX4/8 also imple-

ments a nonstandard General Call command.

• Interface Pins (SCL and SDA)

• Communication Data Rates

• POR/BOR

The General Call commands are:

• Device Memory Address

• General Call Commands

• Device I²C Slave Addressing

• Entering High-Speed (HS) Mode

• General Call Reset

• General Call Wake-up (MCP47FXBX4/8 defined)

The General Call Wake-up command will cause all the

MCP47FXBX4/8 devices to exit their Power-Down

state.

6.2

Interface Pins (SCL and SDA)

The MCP47FXBX4/8 I²C module SCL pin does not

generate the serial clock since the device operates in

Slave mode. Also, the MCP47FXBX4/8 will not stretch

the clock signal (SCL) since memory read access

occurs fast enough.

6.7

Multi-Master Systems

The MCP47FXBX4/8 is not a master device (one that

generates the interface clock), but can be used in

Multi-Master applications.

The MCP47FXBX4/8 I²C module implements slope

control on the SDA pin output driver.

 2020 Microchip Technology Inc.

DS20006368A-page 75

MCP47FXBX4/8

Figure 6-2 shows the I²C Slave address byte format,

2

6.8

Device I C Slave Addressing

which contains the seven address bits and

Read/Write (R/W) bit.

a

The MCP47FXBX4/8 implements 7-bit Slave

addressing. The address byte is the first byte received

following the Start condition from the master device

(see Figure 6-2).

Acknowledge bit

Start bit

Read/Write bit

Note:

The I²C 10-bit Addressing mode is not

supported.

R/W ACK

Slave Address

For volatile devices (MCP47FVBX4/8), the I²C Slave

address bits ADD6:ADD2 are fixed (‘110 0000’). The

user still has Slave address programmability with the

A1:A0 address pins.

Address Byte

Slave Address (7 bits)

Factory Default

Address

For nonvolatile devices, the Slave address is

implemented in a nonvolatile register (Register 4-5)

which is protected from accidental register writes via

the Slave Address Lock (SALCK) Configuration bit.

The SALCK Configuration bit requires a high voltage

(V_IHH) to be modified. The SALCK Configuration bit

must be disabled (see Section 7.4.3 “Disable

Configuration Bit (High-Voltage)”) before a write to

the nonvolatile Slave addresses register can modify the

value.

1

0

ADD6 ADD5 ADD4 ADD3 ADD2 PIN A1 PIN A0 (1)

ADD6 ADD5 ADD4 ADD3 ADD2 PIN A1 PIN A0

(2)

Note 1: Address Bits (ADD6:ADD2) can be

reprogrammed by the customer (nonvol-

atile device), but a High-Voltage com-

mand must be used to unlock the Slave

Address Lock bit.

Note:

After modifying the nonvolatile Slave

address value (Register 4-5), it is strongly

2: The state of the A1:A0 pins creates the

7-bit I²C Address.

recommended

that

the

SALCK

Configuration bit be enabled (see

Section 7.4.2 “Enable Configuration

Bit (High-Voltage)”).

FIGURE 6-2:

Slave Address Bits in the

I²C Control Byte.

DS20006368A-page 76

 2020 Microchip Technology Inc.

MCP47FXBX4/8

The MCP47FXBX4/8 devices do not acknowledge the

HS Select byte. However, upon receiving this

command, the device switches to HS mode.

6.9

Entering High-Speed (HS) Mode

The I²C specification requires that a High-Speed mode

device be activated to operate in High-Speed

(3.4 Mbit/s) mode. This is accomplished by the master

sending a special address byte following the Start bit.

This byte is referred to as the High-Speed Master Mode

Code (HSMMC).

Figure 6-3 illustrates the HS mode command

sequence.

For more information on the HS mode, or other I²C

modes, refer to the “NXP I²C Specification”.

The device can now communicate at up to 3.4 Mbit/s

on SDA and SCL lines. The device will switch out of the

HS mode on the next Stop condition.

6.9.1

SLOPE CONTROL

The slope control on the SDA output for the Fast/Stan-

dard Speed is different from the one of the High-Speed

clock modes of the interface.

The master code is sent as follows:

1. Start condition (S)

6.9.2

PULSE GOBBLER

2. High-Speed Master Mode Code (‘0000 1XXX’),

The XXXbits are unique to the HS master mode.

The pulse gobbler on the SCL pin is automatically

adjusted to suppress spikes < 10 ns during HS mode.

3. No Acknowledge (A)

After switching to the HS mode, the next transferred

byte is the I²C control byte, which specifies the device

to communicate with and any number of data bytes

plus acknowledgments. The master device can then

either issue a repeated Start bit to address a different

device (at high-speed) or a Stop bit to return to the

fast/standard bus speed. After the Stop bit, any other

master device (in a Multi-Master system) can arbitrate

for the I²C bus.

F/S mode

HS mode

P

F/S mode

S

‘

0000 1XXX

’

b

Sr Slave Address R/W

Data

A

A/A

HS mode continues

Sr ‘Slave Address’ R/W A

HS Select Byte

Control Byte

Command/Data Byte(s)

S = Start bit

Sr = Repeated Start bit

Control Byte

A = Acknowledge bit

A = Not Acknowledge bit

R/W = Read/Write bit

P = Stop bit (Stop condition terminates HS Mode)

FIGURE 6-3: HS Mode Sequence.

 2020 Microchip Technology Inc.

DS20006368A-page 77

MCP47FXBX4/8

NOTES:

DS20006368A-page 78

 2020 Microchip Technology Inc.

MCP47FXBX4/8

2

7.0.1

ABORTING A TRANSMISSION

7.0

I C DEVICE COMMANDS

A Restart or Stop condition in an expected data bit

position will abort the current command sequence. If

the command was a write, that data word will not be

written to the MCP47FXBX4/8. Also, the I²C state

machine will be reset.

This section documents the commands supported by

the device.

The commands can be grouped into the following

categories:

• WRITEcommand (normal and high-voltage)

(C1:C0 = ‘00’)

If the condition is a Restart (Start), then the following

byte will be expected to be the Slave Address byte.

• READcommand (normal and high-voltage)

(C1:C0 = ‘11’)

If the condition is a Stop, the device will monitor for the

Start condition.

• General Call commands

• Modify Device Configuration Bit command

(HVC = V_IHH

)

- Enable Configuration bit (C1:C0 = ‘10’)

- Disable Configuration bit (C1:C0 = ‘01’)

The supported commands are shown in Table 7-1. These

commands allow both single or continuous data

operation. Continuous data operation means that the I²C

master does not generate a Stop bit but repeats the

required data/clocks. This allows faster updates since the

overhead of the I²C control byte is removed. Table 7-1

also shows the required number of bit clocks for each

command’s different mode of operation.

TABLE 7-1:

DEVICE COMMANDS – NUMBER OF CLOCKS

Command

Data Update Rate

(8-bit/10-bit/12-bit)

(Data Words/Second)

# of Bit

Clocks

Code

Comments

(1)

(6)

Operation

HV

Mode

(5)

C1 C0

100 kHz 400 kHz 3.4 MHz

Write Command (Normal

and High-Voltage)

3

Single

38

2,632

3,559

2,083

4,762

3,448

5,000

10,526

14,235

8,333

89,474

0

Continuous

Random

27n + 11

48

120,996

70,833

For 10 data words

READ Command (Nor-

1

(2)

mal and High-Voltage)

Continuous

Last Address

Single

18n + 11

29

19,048

13,793

20,000

161,905

117,241

170,000

1

General Call Reset

Command

—

20

Note 4

General Call Wake-up

Command

—

3

Single

20

5,000

20,000

170,000

Enable Configuration Bit

(High-Voltage)

Command

Yes Single

20

5,000

9,901

20,000

39,604

170,000

336,634

1

0

Yes Continuous

9n + 11

For 10 data words

Disable Configuration Bit

(High-Voltage)

Command

Yes Single

20

5,000

9,901

20,000

39,604

170,000

336,634

0

1

Yes Continuous

9n + 11

Note 1: “n” indicates the number of times the command operation is to be repeated.

2: This command is useful to determine when an EEPROM programming cycle has completed.

3: This command can be either normal voltage or high voltage.

2

4: Determined by the General Call Command byte after the I C General Call address.

5: There is a minimal overhead to enter into 3.4 MHz mode.

6: Nonvolatile registers can only use the Single mode.

 2020 Microchip Technology Inc.

DS20006368A-page 79

MCP47FXBX4/8

During an EEPROM write cycle, access to the volatile

memory is allowed when using the appropriate com-

mand sequence. Commands that address nonvolatile

7.1

Write Command

(Normal and High-Voltage)

WRITE commands are used to transfer data to the

desired memory location (from the host controller). The

WRITE command can be issued to both volatile and

nonvolatile memory locations.

memory are ignored until the EEPROM write cycle (t_wc

completes. This allows the host controller to operate on

the volatile DAC registers.

)

Note:

The EEWA status bit indicates if an

EEPROM write cycle is active (see

Register 4-4).

WRITEcommands can be structured as either single or

continuous. The continuous format allows the fastest

data update rate for the device’s memory locations, but

it is not supported for nonvolatile memory locations.

Figure 7-1 shows the command format for a single

write to volatile or nonvolatile memory location.

The format of the command is shown in Figure 7-1

(single) and Figure 7-3 (continuous). For the

ACK/NACK behavior, see Figure 7-2.

7.1.3

CONTINUOUS WRITES TO

VOLATILE MEMORY

A WRITE command to a volatile memory location

changes that location after a properly formatted WRITE

command and the A/A clock has been received.

AContinuous Write mode of operation is possible when

writing to the device’s volatile memory registers (see

Table 7-2). This Continuous Write mode allows writes

without a Stop or Restart condition or repeated trans-

missions of the I²C Control Byte. Figure 7-3 shows the

sequence for three continuous writes. The writes do not

need to be to the same volatile memory address. The

sequence ends with the Master sending a Stop or

Restart condition.

A WRITE command to a nonvolatile memory location

starts an EEPROM write cycle only after a properly for-

matted WRITE command has been received and the

Stop condition has occurred.

Note 1: Writes to certain memory locations

depend on the state of the WiperLock™

Technology status bits.

TABLE 7-2:

VOLATILE MEMORY

ADDRESSES

2: During device communication, if the

device address/command combination is

invalid or an unimplemented device

address is specified, the MCP47FXBX4/8

will NACK that byte. To reset the I²C state

machine, the I²C communication must

detect a Start bit.

Address

Quad-Channel

Octal-Channel

00h-03h

04h-07h

08h

Yes

No

Yes

09h

7.1.1

SINGLE WRITE TO VOLATILE

MEMORY

0Ah

7.1.4

CONTINUOUS WRITES TO

NONVOLATILE MEMORY

For volatile memory locations, data are written to the

MCP47FXBX4/8 after every data word transfer (during

the Acknowledge). If a Stop or Restart condition is

generated during a data transfer (before the A), the

data will not be written to the MCP47FXBX4/8. After the

A bit, the master can initiate the next sequence with a

Stop or Restart condition.

If a continuous write is attempted on a nonvolatile

memory, the missing Stop condition will cause the

command to be an error condition (A). A Start bit is

required to reset the command state machine.

7.1.5

HIGH-VOLTAGE COMMAND (HVC)

SIGNAL

Refer to Figure 7-1 for the byte write sequence.

7.1.2

SINGLE WRITE TO NONVOLATILE

MEMORY

The High-Voltage command (HVC) signal is used to

indicate that the command or sequence of commands

are in the high-voltage operational state. HVC

commands allow the device’s WiperLock Technology

and write protect features to be enabled and disabled.

The sequence to write to a single nonvolatile memory

location is the same as a single write to a volatile

memory with the exception that the EEPROM write

cycle (t_WC) is started after a properly formatted

command, including the Stop bit, if received. After the

Stop condition occurs, the serial interface may

Note:

Writes to a volatile DAC register will not

transfer to the output register until the LAT

(HVC) pin is transitioned from the V_IHHEN

voltage to a V_ILvoltage.

immediately be re-enabled by initiating

condition.

a Start

DS20006368A-page 80

 2020 Microchip Technology Inc.

MCP47FXBX4/8

Control byte

Write command

SA SA SA SA SA SA SA

AD AD AD AD AD

S

0

A

0

X

A

6

5

4

3

2

1

0

4

3

2

1

0

Data to write MSB

Data to write LSB

D

A

P

15 14 13 12 11 10 09 08

07 06 05 04 03 02 01 00

Legend:

I²C Start bit

Reserved, should be set to ‘0’

A

I²C ACK bit⁽¹⁾

S

X

AD

n

D

nn

SA

n

I²C Slave Address

I²C Write bit

Memory Address

Register data (to be written)⁽²⁾

I²C Stop bit⁽³⁾

P

Write command

0

Note 1: The Acknowledge bit is generated by the MCP47FXBX4/8.

2: At the falling edge of the SCL pin for the WRITEcommand ACK bit, the MCP47FXBX4/8 device updates

the value of the specified device register.

3: This command sequence does not need to terminate (using the Stop bit) and the WRITEcommand can

be repeated.

FIGURE 7-1:

Write Random Address Command (Volatile and Nonvolatile Memory).

Write 1 Word Command

S

Slave Address

Command

Data Byte

P

Master

0

x

Example 1 (No Command Error)

Master S 1 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0 x 1 d d d d d d d d 1 d d d d d d d d 1 P

MCP47FXBX4/8

I²C Bus

0

S 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 x 0 d d d d d d d d 0 d d d d d d d d 0 P

Example 2 (Command Error)

Master

S 1 1 0 0 0 0 0 0 1 0 1 1 1 1 0 0 x 1 d d d d d d d d 1 d d d d d d d d 1 P

MCP47FXBX4/8

0

1

I²C Bus

S 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 x 0 d d d d d d d d 1 d d d d d d d d 1 P

Note: Once a command error occurs (example 2), the device will NACK until a Start condition occurs.

FIGURE 7-2:

I²C ACK/NACK Behavior (Write Command Example).

 2020 Microchip Technology Inc.

DS20006368A-page 81

MCP47FXBX4/8

Control byte

Write command

SA SA SA SA SA SA SA

AD AD AD AD AD

S

0

A

0

X

A

6

5

4

3

2

1

0

4

3

2

1

0

Data to write MSB

Data to write LSB

D

A

15 14 13 12 11 10 09 08

07 06 05 04 03 02 01 00

Write command

AD AD AD AD AD

0

X

D

A

4

3

2

1

0

Data to write MSB

Data to write LSB

D

A

15 14 13 12 11 10 09 08

07 06 05 04 03 02 01 00

Write command

AD AD AD AD AD

0

X

A

4

3

2

1

0

Data to write MSB

Data to write LSB

D

A

P

15 14 13 12 11 10 09 08

07 06 05 04 03 02 01 00

Legend:

I²C ACK bit ⁽¹⁾

I²C Start bit

Reserved, should be set to ‘0’

A

S

X

AD

n

D

nn

SA

n

I²C Slave Address

I²C Write bit

Memory Address

Register data (to be written) ⁽²⁾

I²C Stop bit ⁽³⁾

P

Write command

0

Note 1: The Acknowledge bit is generated by the MCP47FXBX4/8.

2: At the falling edge of the SCL pin for the WRITE command ACK bit, the MCP47FXBX4/8 device

updates the value of the specified device register.

3: This command sequence does not need to terminate (using the Stop bit) and the WRITEcommand

can be repeated.

FIGURE 7-3:

Continuous WRITE Commands (Volatile Memory Only).

DS20006368A-page 82

 2020 Microchip Technology Inc.

MCP47FXBX4/8

7.2.1

SINGLE READ

7.2

READ Command

(Normal and High-Voltage)

The READ command format writes two bytes, the

Control byte and the READ command byte (desired

memory address and the READ command), and then

has a Restart condition. Then, a 2^ndControl byte is

transmitted, but this control byte indicates an I²C read

operation (R/W bit = ‘1’).

READ commands are used to transfer data from the

specified memory location to the host controller. The

READ command can be issued to both volatile and

nonvolatile memory locations.

During an EEPROM write cycle (write to nonvolatile

memory location or Enable/Disable Configuration Bit

command) the READcommand can only read the vola-

tile memory locations. By reading the STATUS register

(0Ah), the host controller can determine when the write

cycle has been completed (via the state of the EEWA

bit).

7.2.1.1

Single Memory Address

Figure 7-4 shows the sequence for reading a specified

memory address.

7.2.1.2

Last Memory Address Accessed

Figure 7-5 shows the waveforms for a single read of

the last memory location accessed.

The READcommand formats include:

• Single Read

This command allows faster communication when

checking the status of the EEPROM Write Active

(EEWA) bit (see Register 4-4), as long as the register

address of the device’s last command is 0Ah.

- Single Memory Address

- Last Memory Address Accessed

• Continuous Reads

The MCP47FXBX4/8 retains the last device memory

address received. That is the MCP47FXBX4/8 does

not corrupt the device memory address after repeated

Start or Stop conditions.

7.2.2

CONTINUOUS READS

Continuous reads allow the device’s memory to be

read quickly. Continuous reads are possible to all

memory locations. If a nonvolatile memory write cycle

occurs, then READ commands may only access the

volatile memory locations.

If the address pointer is for a nonvolatile memory

location during a nonvolatile write cycle (t_WC), the

MCP47FXBX4/8 will respond with an A bit.

Figure 7-7 shows the sequence for three continuous

reads.

Note 1: During device communication, if the

device address/command combination is

invalid or an unimplemented address is

specified, then the MCP47FXBX4/8 will

NACK that byte. To reset the I²C state

machine, the I²C communication must

detect a Start bit.

For continuous reads, instead of transmitting a Stop or

Restart condition after the data transfer, the master

continually reads the data byte. The sequence ends

with the master Not Acknowledging and then sending a

Stop or Restart.

This is useful in reading the System STATUS register

(0Ah) to determine if an EEPROM write cycle has been

completed (EEWA bit).

2: If the LAT pin is high (V_IH), reads of the

volatile DAC register read the output

value, not the internal register.

7.2.3

IGNORING AN I²C TRANSMISSION

AND “FALLING OFF” THE BUS

3: READ commands operate the same

regardless of the state of the High-

Voltage command signal.

The MCP47FXBX4/8 expects to receive complete,

valid I²C commands and will assume any command not

defined as a valid command. This is due to a bus

corruption, thus entering a passive High condition on

the SDA signal. All signals will be ignored until the next

valid Start condition and Control byte are received.

 2020 Microchip Technology Inc.

DS20006368A-page 83

MCP47FXBX4/8

Control byte

Read command

SA SA SA SA SA SA SA

AD AD AD AD AD

S

0

A

1

X

1

A

6

5

4

3

2

1

0

4

3

2

1

0

Control byte

SA SA SA SA SA SA SA

Sr

6

5

4

3

2

1

0

Data Read MSB

Data Read LSB

D

A

P

0

11 10 09 08

07 06 05 04 03 02 01 00

Legend:

I²C Read bit

Data (read from memory)

P

I2C Stop bit^{(4, 5)}

AD

n

I²C Start bit

Memory Address⁽⁵⁾

1

S

SA

n

D

nn

I²C Slave Address

I²C Write bit

Read command

1

2

(2)

Reserved, set to ‘0‘

I C ACK bit

0

X

A

I²C Start bit, repeated

A

I²C ACK bit⁽¹⁾

Sr

I²C NACK bit⁽³⁾

Note 1: The Acknowledge bit is generated by the MCP47FXBX4/8.

2: The master device is responsible for the A/A signal. If an A signal occurs, the MCP47FXBX4/8 will

abort this transfer and release the bus.

3: The master device will Not Acknowledge, and the MCP47FXBX4/8 will release the bus so the master

device can generate a Stop or repeated Start condition.

4: At the falling edge of the SCL pin for the READcommand ACK bit, the MCP47FXBX4/8 device updates

the value of the specified device Register.

5: This command sequence does not need to terminate (using the Stop bit) and the READcommand can

be repeated (see continuous read format, Section 7.2.2 “Continuous Reads”).

FIGURE 7-4:

READ Command – Single Memory Address.

DS20006368A-page 84

 2020 Microchip Technology Inc.

MCP47FXBX4/8

Control byte

SA SA SA SA SA SA SA

S

1

A

6

5

4

3

2

1

0

Data Read MSB

Data Read LSB

D

A

P

0

11 10 09 08

07 06 05 04 03 02 01 00

Legend:

I²C Read bit

S

I²C NACK bit^{(3, 4)}

I²C Stop bit⁽⁵⁾

I²C Start bit

A

P

1

SA

n

D

nn

I²C Slave Address

I²C ACK bit ⁽¹⁾

Data (read from memory)

2

(2)

I C ACK bit

A

Note 1: The Acknowledge bit is generated by the MCP47FXBX4/8.

2: The master device is responsible for the A/A signal. If an A signal occurs, the MCP47FXBX4/8 will

abort this transfer and release the bus.

3: The master device will Not Acknowledge, and the MCP47FXBX4/8 will release the bus so the master

device can generate a Stop or repeated Start condition.

4: At the falling edge of the SCL pin for the READcommand ACK bit, the MCP47FXBX4/8 device updates

the value of the specified device register.

5: This command sequence does not need to terminate (using the Stop bit) and the READcommand can

be repeated (see continuous read format, Section 7.2.2 “Continuous Reads”).

FIGURE 7-5:

READ Command – Last Memory Address Accessed.

 2020 Microchip Technology Inc.

DS20006368A-page 85

MCP47FXBX4/8

Read 1 Word Command

S

Slave Address

Command

Master

0

1

Slave Address

Data Byte

P

Master (Continued)

1 P

1 1

1

Ex.1 (No Command Error)

Master

MCP47FXBXXA0

I²C Bus S 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 x 0

S 1 1 0 0 0 0 0 0 1 0 0 0 0 1 1 1 x 1

0

Master (Continued)

S 0 0 0 0 1 0 0 1 1

1

1 P

MCP47FXBXXA0 (Continued)

I²C Bus (Continued)

0 d d d d d d d d 0 d d d d d d d d 0

S 0 0 0 0 0 0 0 1 0 d d d d d d d d 0 d d d d d d d d 0 P

Ex.2 (With Command Error)

Master

S 1 1 0 0 0 0 0 0 1 0 1 1 1 1 0 0 x 1

MCP47FXBXXA0

0

1

I²C Bus S 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 x 1

Master (Continued)

S 1 1 0 0 0 0 0 1 1

0 ? ? ? ? ? ? ? ? 0 ? ? ? ? ? ? ? ? 1

S 1 1 0 0 0 0 0 1 0 ? ? ? ? ? ? ? ? 0 ? ? ? ? ? ? ? ? 1 P

1

1 P

MCP47FXBXXA0 (Continued)

I²C Bus (Continued)

Note 1: Once a command error occurs (example 2), the MCP47FXBX4/8 will NACK until a Start condition occurs.

2: For the command error case (Example 2), the data read are from the register of the last valid address

loaded into the device.

FIGURE 7-6:

I²C ACK/NACK Behavior (READ Command Example).

DS20006368A-page 86

 2020 Microchip Technology Inc.

MCP47FXBX4/8

Control byte

Read command

SA SA SA SA SA SA SA

AD AD AD AD AD

S

0

A

Sr

D

1

X

1

A

6

5

4

3

2

1

0

4

3

2

1

0

Control byte

SA SA SA SA SA SA SA

A

D

6

5

4

3

2

1

0

Data Read MSB

Data Read LSB

D

A

0

11 10 09 08

07 06 05 04 03 02 01 00

Data Read MSB

Data Read LSB

D

A

0

11 10 09 08

07 06 05 04 03 02 01 00

Data Read MSB

Data Read LSB

D

P

0

11 10 09 08

07 06 05 04 03 02 01 00

Legend:

I²C Read bit

Data (read from memory)

I²C Stop bit⁽⁴⁾

AD

n

I²C Start bit

Memory Address

P

1

S

D

nn

SA

n

I²C Slave Address

I²C Write bit

Read command

1

2

(2)

I C ACK bit

A

Reserved, set to ‘0‘

X

0

I²C NACK bit⁽³⁾

I²C Start bit, repeated

Sr

I²C ACK bit⁽¹⁾

A

Note 1: The Acknowledge bit is generated by the MCP47FXBX4/8.

2: The master device is responsible for A/A signal. If an A signal occurs, the MCP47FXBX4/8 will abort

this transfer and release the bus.

3: The master device will Not Acknowledge and the MCP47FXBX4/8 will release the bus so the master

device can generate a Stop or repeated Start condition.

4: At the falling edge of the SCL pin for the READcommand ACK bit, the MCP47FXBX4/8 updates the

value of the specified device register.

FIGURE 7-7:

Continuous READ Command of Specified Address.

 2020 Microchip Technology Inc.

DS20006368A-page 87

MCP47FXBX4/8

The General Call Reset command format is specified

by the I²C specification. The General Call Wake-Up

command is a Microchip-defined format. The General

Call Wake-Up command will have all devices wake up

(that is, exit the Power-Down mode).

The other two I²C specification command codes (04h

and 00h) are not supported. Therefore those com-

mands are Not Acknowledged.

If these 7-bit commands conflict with other I²C devices

on the bus, then the customer will need two I²C buses

and ensure that the devices are on the correct bus for

their desired application functionality.

7.3

General Call Commands

The MCP47FXBX4/8 acknowledges the General Call

Address command (00h in the first byte). General Call

commands can be used to communicate to all devices

on the I²C bus (at the same time) that understand the

General Call command. The meaning of the general

call address is always specified in the second byte (see

Figure 7-8).

If the second byte has a ‘1’ in the LSb, the specification

intends this to indicate a “Hardware General Call”. The

MCP47FXBX4/8 will ignore this byte and all following

bytes (and A), until a Stop bit (P) is encountered.

The MCP47FXBX4/8 devices support the following I²C

General Call commands:

Note:

Refer to the NXP specification #UM10204,

Rev. 03 19 June 2007 document for more

details on the General Call specifications.

The I²C specification does not allow

‘00000000’ (00h) in the second byte.

• General Call Reset (06h)

• General Call Wake-up (0Ah)

“7-bit command”

General Call address

S

A

0

x

0

A

P

0

Legend:

I²C ACK bit⁽¹⁾

GC command

I²C Start bit

x

P

I²C Stop bit^(2,3)

A

S

Note 1: The Acknowledge bit is generated by the MCP47FXBX4/8.

2: This command sequence does not need to terminate (using the Stop bit) and the General Call

command can be repeated, or another General Call command can be sent. Only the first

command will be accepted by the MCP47FXBX4/8.

FIGURE 7-8:

General Call Format.

DS20006368A-page 88

 2020 Microchip Technology Inc.

MCP47FXBX4/8

7.3.1

GENERAL CALL RESET

7.3.2

GENERAL CALL WAKE-UP

The I²C General Call Reset command forces a reset

event. This is similar to the Power-on Reset, except

that the reset delay timer is not started. This command

allows multiple MCP47FXBX4/8 devices to be reset

synchronously.

The I²C General Call Wake-up command forces the

device to exit its Power-Down state (forces the

PDnB:PDnA bits to ‘00’). This command allows multiple

MCP47FXBX4/8 devices to wake up synchronously.

The device performs General Call Wake-up if the sec-

ond byte (after the General Call Address) is

‘00001010’ (0Ah). At the acknowledgment of this byte,

the device will perform the following task: the device’s

volatile Power-Down bits (PDnB:PDnA) are forced to

‘00’. The nonvolatile (EEPROM) Power-Down bit

values are not affected by this command.

The device performs a General Call Reset if the second

byte is ‘00000110’ (06h). At the acknowledgment of

this byte, the device will abort the current conversion

and perform the following tasks:

• Internal reset similar to a POR. The contents of

the EEPROM are loaded into the DAC registers

and the analog output is available immediately

(following the acknowledgment pulse).

• The V_OUTwill be available immediately, but after a

short time delay following the acknowledgment

pulse. The V_OUTvalue is determined by the

EEPROM contents.

“7-bit command”

General Call address

S

A

0

1

0

A

P

0

Legend:

I²C Stop bit^(2,3)

I²C ACK bit⁽¹⁾

Reset command

I²C Start bit

0

1

P

A

S

Note 1: The Acknowledge bit is generated by the MCP47FXBX4/8.

2: At the falling edge of the SCL pin for the General Call Reset command ACK bit, the MCP47FXBX4/8

device is reset.

3: This command sequence does not need to terminate (using the Stop bit) and the General Call Reset

command can be repeated, or the General Call Wake-Up command can be sent. Only the first command

will be accepted by the MCP47FXBX4/8.

FIGURE 7-9:

General Call Reset Command.

“7-bit command”

General Call address

S

A

0

1

0

1

0

A

P

0

Legend:

I²C Stop bit⁽³⁾

I²C ACK bit⁽¹⁾

Wake-Up command

P

I²C Start bit

1

0

1

A

S

Note 1: The Acknowledge bit is generated by the MCP47FXBX4/8.

2: At the rising edge of the last data bit for the General Call Wake-Up command, the volatile Power-Down

bits (PDnB:PDnA) are forced to ‘00’.

3: This command sequence does not need to terminate (using the Stop bit) and the General Call Wake-

Up command can be repeated, or the General Call Reset command can be sent.

FIGURE 7-10:

General Call Wake-Up Command.

 2020 Microchip Technology Inc.

DS20006368A-page 89

MCP47FXBX4/8

7.4

Modify Device Configuration Bit

Commands

Note 1: There is a required delay after the HVC

pin is driven to the V_IHHlevel to the 1^st

edge of the SCL pin.

These commands are used to program the device Con-

figuration bits. These commands require a high voltage

(V_IHH) on the HVC pin.

2: Issuing an enable or disable command to

a nonvolatile location will cause an error

condition (A will be generated).

The MCP47FXBX4/8 devices support the following

Modify Device Configuration Bit commands:

7.4.2

ENABLE CONFIGURATION BIT

(HIGH-VOLTAGE)

• Enable Configuration Bit (High-Voltage)

• Disable Configuration Bit (High-Voltage)

Figure 7-11 shows the formats for a single Modify Write

Protect or WiperLock Technology command.

These Configuration bits are used to inhibit the DAC

values from inadvertent modification.

A Modify Write Protect or WiperLock Technology

command will only start an EEPROM write cycle (t_wc

)

7.4.1

THE HIGH-VOLTAGE COMMAND

(HVC) SIGNAL

after a properly formatted command has been received

and the Stop condition occurs. During an EEPROM

write cycle, only serial commands to volatile memory

are accepted. All other serial commands are ignored

until the EEPROM write cycle (t_wc) completes. This

allows the host controller to operate on the volatile

DAC, the volatile V_REF, Power-Down, Gain, Status, and

WiperLock technology STATUS registers. The EEWA

bit in the STATUS register indicates the status of an

EEPROM write cycle.

The High-Voltage command signal is used to indicate

that the command, or sequence of commands, are in

the High-Voltage mode. Signals > V_IHH(~9.0V) on the

HVC pin put the device into High-Voltage mode. High-

Voltage commands allow the device’s WiperLock Tech-

nology and write-protect features to be enabled and

disabled.

Enable command

Control byte

SA SA SA SA SA SA SA

AD AD AD AD AD

S

0

A

1

0

X

A

6

5

4

3

2

1

0

4

3

2

1

0

Enable command

AD AD AD AD AD

.....

4

3

2

1

0

Enable command

AD AD AD AD AD

1

0

X

P

4

3

2

1

0

Legend:

I²C Write bit

I²C ACK bit

AD

n

I²C Start bit

Memory Address

Reserved, set to ‘0‘

X

0

S

Enable command

I²C Stop bit⁽²⁾

SA

n

I²C Slave Address

P

A

1

0

2

(1)

I C ACK bit

A

Note 1: This command sequence does not need to terminate (using the Stop bit) and can change to any other

desired command sequence (Enable, read or write).

2: This command byte is not required and the Stop bit may occur immediately after the 2^ndACK bit in this

sequence.

FIGURE 7-11:

I²C Enable Command Sequence.

DS20006368A-page 90

 2020 Microchip Technology Inc.

MCP47FXBX4/8

During an EEPROM write cycle, only serial commands

to volatile memory are accepted. All other serial com-

7.4.3

DISABLE CONFIGURATION BIT

(HIGH-VOLTAGE)

mands are ignored until the EEPROM write cycle (t_wc

)

Figure 7-12 shows the formats for a single Modify Write

Protect or WiperLock Technology command.

completes. This allows the host controller to operate on

the volatile DAC, the volatile V_REF, Power-Down, Gain,

Status, and WiperLock Technology STATUS registers.

The EEWA bit in the STATUS register indicates the sta-

tus of an EEPROM write cycle.

A Modify Write Protect or WiperLock Technology com-

mand will only start an EEPROM write cycle (t_wc) after

a properly formatted command has been received and

the Stop condition occurs.

Disable command

Control byte

SA SA SA SA SA SA SA

AD AD AD AD AD

S

0

A

0

1

X

A

6

5

4

3

2

1

0

4

3

2

1

0

Disable command

AD AD AD AD AD

.....

4

3

2

1

0

Disable command

AD AD AD AD AD

0

1

X

P

4

3

2

1

0

Legend:

I²C Write bit

I²C ACK bit

AD

n

I²C Start bit

Memory Address

Reserved, set to ‘0‘

X

0

S

Disable command

I²C Stop bit⁽²⁾

SA

n

I²C Slave Address

P

A

0

1

2

(1)

I C ACK bit

A

Note 1: This command sequence does not need to terminate (using the Stop bit) and can change to any other

desired command sequence (Enable, read or write).

2: This command byte is not required and the Stop bit may occur immediately after the 2^ndACK bit in this

sequence.

FIGURE 7-12:

I²C Disable Command Sequence.

 2020 Microchip Technology Inc.

DS20006368A-page 91

MCP47FXBX4/8

NOTES:

DS20006368A-page 92

 2020 Microchip Technology Inc.

MCP47FXBX4/8

8.0

APPLICATIONS INFORMATION

Address byte

The MCP47FXBX4/8 devices are general purpose,

quad/octal-channel voltage output DACs for various

applications where a precision operation with low-power

and nonvolatile EEPROM memory is needed.

SCL

SDA

1

2

3

4

5

6

7

8

9

Since the devices include a nonvolatile EEPROM

memory, the user can utilize these devices for

applications that require the output to return to the

previous set-up value on subsequent power-ups.

A6 A5 A4 A3 A2 A1 A0

Address bits

1

Start

Bit

Stop

Bit

R/W

2

8.1

I C Bus Connection

Considerations

Device

Response

FIGURE 8-1:

8.1.3

I²C Bus Connection Test.

8.1.1

CONNECTING TO THE I²C BUS

USING PULL-UP RESISTORS

SOFTWARE I²C INTERFACE RESET

SEQUENCE

The SCL and SDA pins of the MCP47FXBX4/8 devices

are open-drain configurations. These pins require a

pull-up resistor, as shown in Figure 8-3.

Note:

This technique is documented in AN1028.

The pull-up resistor values (R₁and R₂) for SCL and

SDA pins depend on the operating speed (standard,

fast and high speed) and loading capacitance of the I²C

bus line. A higher value of the pull-up resistor consumes

less power, but increases the signal transition time

(higher RC time constant) on the bus line. Therefore, it

can limit the bus operating speed. The lower resistor

value, on the other hand, consumes higher power, but

allows higher operating speed. If the bus line has higher

capacitance due to long metal traces or multiple device

connections to the bus line, a smaller pull-up resistor is

needed to compensate the long RC time constant. The

pull-up resistor is typically chosen between 1 kand

10 kranges for Standard and Fast modes, and less

than 1 kfor High-Speed mode.

At times, it may become necessary to perform a

Software

Reset

Sequence

to

ensure

the

MCP47FXBX4/8 devices are in a correct and known I²C

interface state. This technique only resets the I²C state

machine.

This is useful if the MCP47FXBX4/8 devices power-up

in an incorrect state (due to excessive bus noise, etc),

or if the master device is reset during communication.

Figure 8-2 shows the communication sequence to

software reset the device.

S

‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’

S

P

Nine bits of ‘1’

Start bit

Stop bit

8.1.2

DEVICE CONNECTION TEST

Start bit

The user can test the presence of the device on the I²C

bus line by using a simple I²C command. This test can

be achieved by checking an acknowledge response

from the device after sending a READ or WRITE

command. Figure 8-1 shows an example with a READ

command. The steps are:

FIGURE 8-2:

Format.

Software Reset Sequence

The 1^stStart bit will cause the device to reset from a

state in which expects to receive data from the master

device. In this mode, the device monitors the data bus

in Receive mode and can detect if the Start bit forces

an internal reset.

1. Set the R/W bit “High” in the device’s address byte.

2. Check the ACK bit of the address byte.

If the device acknowledges (ACK = 0) the

command, then the device is connected.

Otherwise, it is not connected.

The nine bits of ‘1’ are used to force a reset of those

devices that could not be reset by the previous Start bit.

This occurs only if the MCP47FXBX4/8 devices drive

an A bit on the I²C bus, or are in Output mode (from a

READcommand) and are driving a data bit of ‘0’ onto

the I²C bus. In both of these cases, the previous Start

bit could not be generated due to the MCP47FXBX4/8

holding the bus low. By sending out nine ‘1’ bits, it is

ensured that the device will see an A bit (the master

device does not drive the I²C bus low to acknowledge

the data sent by the MCP47FXBX4/8), which also

forces the MCP47FXBX4/8 to reset.

3. Send Stop bit.

 2020 Microchip Technology Inc.

DS20006368A-page 93

MCP47FXBX4/8

The second Start bit is sent to address the rare

possibility of an erroneous write. This could occur if the

master device was reset while sending a WRITEcom-

mand to the MCP47FXBX4/8, and then as the master

device returns to normal operation and issues a Start

condition, while the MCP47FXBX4/8 devices issue an

acknowledge. In this case, if the second Start bit is not

sent (and the Stop bit was sent) the MCP47FXBX4/8

could initiate a write cycle.

V

DD

R₂

R₁

V_DD

SDA

SCL

To MCU

C₁

C₂

V_REF

V_OUT0

LAT/HVC

V_SS

Analog

Output

Note:

The potential for this erroneous write

ONLY occurs if the master device is reset

while sending a WRITE command to the

MCP47FEBXX.

V_OUTN

C₃

Optional

C_N

The Stop bit terminates the current I²C bus activity. The

MCP47FXBX4/8 waits to detect the next Start

condition.

(a) Circuit when V_DDis selected as reference.

(Note: V is connected to the reference circuit internally.)

DD

This sequence does not affect any other I²C devices

which may be on the bus, as they should disregard this

for being an invalid command.

V

DD

C₁

C₂

R₂

R₁

8.2

Power Supply Considerations

Analog

V_REF

SDA

SCL

V_DD

To MCU

The power source should be as clean as possible. The

power supply to the device is also used for the DAC

voltage reference internally if the internal V_DDis

selected as the resistor ladder’s reference voltage

(VRnB:VRnA = ‘00’).

V_REF

LAT/HVC

V_SS

V_OUT0

Any noise induced on the V_DDline can affect the DAC

performance. Typical applications will require a bypass

capacitor in order to filter out high-frequency noise on

the V_DDline. The noise can be induced onto the power

supply’s traces or as a result of changes on the DAC out-

put. The bypass capacitor helps to minimize the effect of

these noise sources on signal integrity. Figure 8-3

shows an example of using two bypass capacitors (a

10 µF tantalum capacitor and a 0.1 µF ceramic capaci-

tor) in parallel on the V_DDline. These capacitors should

be placed as close to the V_DDpin as possible (within

4 mm). If the application circuit has separate digital and

analog power supplies, the V_DDand V_SSpins of the

device should reside on the analog plane.

Analog

Output

V_OUTN

C₃

Optional

C_N

(b) Circuit when external reference is used.

2

R and R are I C pull-up resistors:

1

2

R and R :

=

1

2

5 k - 10 k for f

100 kHz to 400 kHz

3.4 MHz

SCL

~700 for f

When setting the part voltage reference to Band Gap

mode, the use of the V_REFpin decoupling capacitors is

not recommended.

C : 0.1 µF capacitor

Ceramic

1

C : 10 µF capacitor

Tantalum

2

C : ~ 0.1 µF

Optional to reduce noise

3

in V

OUT

C : 0.1 µF capacitor

Ceramic

=

4

C : 10 µF capacitor

Tantalum

Ceramic

5

C : 0.1 µF capacitor

6

FIGURE 8-3:

Circuit Example.

DS20006368A-page 94

 2020 Microchip Technology Inc.

MCP47FXBX4/8

8.3.2

PCB AREA REQUIREMENTS

8.3

Layout Considerations

In some applications, PCB area is a criteria for device

selection. Table 8-1 shows the typical package

dimensions and area for the different package options.

Several layout considerations may be applicable to

your application. These may include:

• Noise

)

TABLE 8-1:

Package

PACKAGE FOOTPRINT⁽¹

• PCB Area Requirements

Package Footprint

8.3.1

NOISE

Dimensions

(mm)

Particularly harsh environments may require shielding

of critical signals. Inductively-coupled AC transients

and digital switching noise can degrade the input and

output signal integrity, potentially masking the

MCP47FXBX4/8’s performance. Careful board layout

minimizes these effects and increases the Signal-to-

Noise Ratio (SNR).

Type

Code

Area (mm²)

Length Width

20 TSSOP

20 VQFN

ST

3.00

5

4.90

5

14.70

25

MQ

Note 1: Does not include recommended land

pattern dimensions. Dimensions are

typical values.

Multi-layer boards utilizing a low-inductance ground

plane, isolated inputs, isolated outputs and proper

decoupling are critical to achieving the performance

that the silicon is capable to provide.

Separate digital and analog ground planes are

recommended. In this case, the V_SSpin and the ground

pins of the V_DDcapacitors should be terminated to the

analog ground plane.

Note:

Breadboards and wire-wrapped boards

are not recommended.

 2020 Microchip Technology Inc.

DS20006368A-page 95

MCP47FXBX4/8

NOTES:

DS20006368A-page 96

 2020 Microchip Technology Inc.

MCP47FXBX4/8

9.2

Technical Documentation

9.0

DEVELOPMENT SUPPORT

Several additional technical documents are available to

assist you in your design and development. These

technical documents include Application Notes,

Technical Briefs, and Design Guides. Table 9-2 shows

some of these documents.

Development support can be classified into two groups.

These are:

• Development Tools

• Technical Documentation

9.1

Development Tools

Several development tools are available to assist in your

design and evaluation of the MCP47FXBX4/8 devices.

The currently available tools are shown in Table 9-1.

Figure 9-1 shows how the TSSOP20EV bond-out PCB

can be populated to easily evaluate the

MCP47FXBX4/8 devices. The PICkit™ Serial Analyzer

can be used to control the DAC output registers and

state of the configuration, control and STATUS register.

The TSSOP20EV boards may be purchased directly

from the Microchip website at www.microchip.com.

TABLE 9-1:

DEVELOPMENT TOOLS (Note 1)

Board Name Part #

Comment

20-Pin TSSOP and SSOP Evaluation Board TSSOP20EV Most Flexible option - Recommended Bond-out PCB

Note 1: Supports the PICkit™ Serial Analyzer. See the User’s Guide for additional information and requirements.

TABLE 9-2:

TECHNICAL DOCUMENTATION

Application

Note Number

Title

Literature #

AN1326

Using the MCP4728 12-Bit DAC for LDMOS Amplifier Bias Control Applications

Signal Chain Design Guide

DS01326

DS21825

DS01005

—

Analog Solutions for Automotive Applications Design Guide

 2020 Microchip Technology Inc.

DS20006368A-page 97

MCP47FXBX4/8

MCP47FXBX8-20E/ST

installed in U3 footprint

Connected to

Digital Ground

(DGND) Plane

Connected to

Digital Power (V_L) Plane

LAT1

LAT0/HVC

1.0 µF

4.7k 

0 

V

SDA

SCL

DD

V

REF0

V

OUT0

REF1

OUT7

V

OUT2

V

OUT4

OUT6

OUT5

OUT3

V

SS

OUT1

0 

Two blue wire jumpers to connect

PICkit™ Serial Interface (I²C) to device pins

1x6 male header, with 90° right angle

FIGURE 9-1:

MCP47FXBX4/8 Evaluation Board Circuit Using TSSOP20EV.

DS20006368A-page 98

 2020 Microchip Technology Inc.

MCP47FXBX4/8

10.0 PACKAGING INFORMATION

10.1 Package Marking Information

20-Lead 5 x 5 mm VQFN

Example

MCP47FE

B04

-E/MQ

2010256

20-Lead TSSOP

Example

MCP47FVB

0420E256

2010

Legend: XX...X Customer-specific information

Y

Year code (last digit of calendar year)

YY

Year code (last 2 digits of calendar year)

WW

NNN

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

e

3

e

3

*

)

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

 2020 Microchip Technology Inc.

DS20006368A-page 99

MCP47FXBX4/8

20-Lead Plastic Quad Flat, No Lead Package (MQ) – 5x5x1.0 mm Body [VQFN]

With 0.40 mm Contact Length

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

A

B

E

N

NOTE 1

1

2

(DATUM B)

(DATUM A)

2X

0.20 C

2X

TOP VIEW

0.20 C

0.10 C

A1

C

A

SEATING

PLANE

20X

(A3)

0.08 C

C A B

SIDE VIEW

0.10

D2

0.10

C A B

E2

2

1

NOTE 1

K

N

L

20X b

0.10

0.05

C A B

C

e

BOTTOM VIEW

Microchip Technology Drawing C04-139C (MQ) Sheet 1 of 2

DS20006368A-page 100

 2020 Microchip Technology Inc.

MCP47FXBX4/8

20-Lead Plastic Quad Flat, No Lead Package (MQ) – 5x5x1.0 mm Body [VQFN]

With 0.40 mm Contact Length

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units

Dimension Limits

MILLIMETERS

NOM

MIN

MAX

Number of Terminals

Pitch

Overall Height

N

20

0.65 BSC

0.90

0.02

0.20 REF

5.00 BSC

3.25

5.00 BSC

3.25

0.30

0.40

e

A

A1

(A3)

D

D2

E

E2

b

0.80

0.00

1.00

0.05

Standoff

Contact Thickness

Overall Length

Exposed Pad Length

Overall Width

Exposed Pad Width

Contact Width

3.15

3.35

3.15

0.25

0.35

0.20

3.35

0.35

0.45

-

Contact Length

Contact-to-Exposed Pad

L

K

-

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Package is saw singulated

3. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-139C (MQ) Sheet 2 of 2

 2020 Microchip Technology Inc.

DS20006368A-page 101

MCP47FXBX4/8

20-Lead Plastic Quad Flat, No Lead Package (MQ) – 5x5x1.0 mm Body [VQFN]

With 0.40 mm Contact Length

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

C1

X2

EV

20

1

ØV

2

G

Y2

C2

EV

Y1

E

X1

SILK SCREEN

RECOMMENDED LAND PATTERN

Units

Dimension Limits

E

MILLIMETERS

NOM

0.65 BSC

MIN

MAX

Contact Pitch

Optional Center Pad Width

Optional Center Pad Length

Contact Pad Spacing

W2

T2

C1

C2

X1

Y1

G

3.35

4.50

Contact Pad Spacing

Contact Pad Width (X20)

Contact Pad Length (X20)

Distance Between Pads

Thermal Via Diameter

Thermal Via Pitch

0.40

0.55

0.20

V

EV

0.30

1.00

Notes:

1. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during

reflow process

Microchip Technology Drawing C04-2139B (MQ)

DS20006368A-page 102

 2020 Microchip Technology Inc.

MCP47FXBX4/8

 2020 Microchip Technology Inc.

DS20006368A-page 103

MCP47FXBX4/8

DS20006368A-page 104

 2020 Microchip Technology Inc.

MCP47FXBX4/8

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2020 Microchip Technology Inc.

DS20006368A-page 105

MCP47FXBX4/8

NOTES:

DS20006368A-page 106

 2020 Microchip Technology Inc.

MCP47FXBX4/8

APPENDIX A: REVISION HISTORY

Revision A (June 2020)

• Original release of this document.

 2020 Microchip Technology Inc.

DS20006368A-page 107

MCP47FXBX4/8

NOTES:

DS20006368A-page 108

 2020 Microchip Technology Inc.

MCP47FXBX4/8

The I²C serial protocol allows multiple master devices

on the I²C bus. This is referred to as Multi-master. For

this, all master devices must support Multi-master

operation. In this configuration, all master devices mon-

itor their communication. If they detect that they wish to

transmit a bit that is a logic high but is detected as a

logic low (some other master device driving), they “get

off” the bus. That is, they stop their communication and

continue to listen to determine if the communication is

directed towards them.

The I²C serial protocol only defines the field types, field

lengths, timings, etc. of a frame. The frame content

defines the behavior of the device. For details on the

frame content (commands/data), refer to Section 7.0

“I2C Device Commands”.

2

APPENDIX B: I C SERIAL

INTERFACE

This I²C interface is a two-wire interface that allows

multiple devices to be connected to this two-wire bus.

Figure B-1 shows a typical I²C interface connection.

Typical I²C Interface Connections

Slave

Master

SCL

SDA

The I²C serial protocol defines some commands called

“General Call Addressing”, which allows the master

device to communicate to all slave devices on the I²C

bus.

Other Devices

TYPICAL I²C INTERFACE.

FIGURE B-1:

B.1

Overview

Note:

Refer to the NXP Specification

#UM10204, Rev. 03 19 June 2007

document for more details on the I²C

specifications.

A device that sends data onto the bus is defined as

transmitter, and a device receiving data is defined as

receiver. The bus must be controlled by a master

device which generates the Serial Clock (SCL),

controls the bus access and generates the Start and

Stop conditions. Devices that do not generate a serial

clock work as slave devices. Both master and slave

can operate as transmitter or receiver, but the master

device determines which mode is activated.

Communication is initiated by the master (micro-

controller), which sends the Start bit followed by the

slave address byte. The first byte transmitted is always

the slave address byte, which contains the device

code, the address bits and the R/W bit.

The I²C interface specifies different communication bit

rates. These are referred to as Standard, Fast or High-

Speed modes. The MCP47FXBX4/8 supports these

three modes. The clock rates (bit rate) of these modes

are:

• Standard mode: up to 100 kHz (kbit/s)

• Fast mode: up to 400 kHz (kbit/s)

• High-Speed mode (HS mode): up to 3.4 MHz

(Mbit/s)

The I²C protocol supports two addressing modes:

• 7-bit slave addressing

• 10-bit slave addressing (allows more devices on

the I²C bus)

Only 7-bit slave addressing will be discussed in this

section.

 2020 Microchip Technology Inc.

DS20006368A-page 109

MCP47FXBX4/8

B.3.1.2

Data Bit

B.2

Signal Descriptions

The I²C interface uses two pins (signals). These are:

The SDA signal may change state while the SCL signal

is low. While the SCL signal is high, the SDA signal

MUST be stable (see Figure B-3).

• SDA (Serial Data)

• SCL (Serial Clock)

B.2.1

SERIAL DATA (SDA)

2^ndBit

1^stBit

SDA

SCL

The Serial Data (SDA) signal is the data signal of the

device. The value on this pin is latched on the rising

edge of the SCL signal when the signal is an input.

Data Bit

With the exception of the Start (Restart) and Stop con-

ditions, the High or Low state of the SDA pin can only

change when the clock signal on the SCL pin is low.

During the high period of the clock, the SDA pin’s value

(high or low) must be stable. Changes in the SDA pin’s

value while the SCL pin is high will be interpreted as a

Start or a Stop condition.

FIGURE B-3:

DATA BIT.

B.3.1.3

Acknowledge (A) Bit

The A bit (see Figure B-4) is typically a response from

the receiving device to the transmitting device.

Depending on the context of the transfer sequence, the

A bit may indicate different things. Typically, the slave

device will supply an A response after the Start bit and

eight data bits have been received. An A bit has the

SDA signal low, while the A bit has the SDA signal high.

B.2.2

SERIAL CLOCK (SCL)

The Serial Clock (SCL) signal is the clock signal of the

device. The rising edge of the SCL signal latches the

value on the SDA pin.

Depending on the Clock Rate mode, the interface will

display different characteristics.

SDA

SCL

D0

A

8

9

2

B.3

I C Operation

I²C BIT STATES AND SEQUENCE

FIGURE B-4:

WAVEFORM.

ACKNOWLEDGE

B.3.1

Figure B-8 shows the I²C transfer sequence, while

Figure B-7 shows the bit definitions. The Serial Clock is

generated by the master. The following definitions are

used for the bit states:

Table B-1 shows some of the conditions where the

slave device issues the A or Not A (A).

If an error condition occurs (such as an A instead of A),

then a Start bit must be issued to reset the command

state machine.

• Start bit (S)

• Data bit

• Acknowledge (A) bit (driven low)/

No Acknowledge (A) bit (not driven low)

TABLE B-1:

MCP47FXBX4/8 A/A

RESPONSES

• Repeated Start bit (Sr)

• Stop bit (P)

Acknowledge

Event

Comment

Bit Response

B.3.1.1

Start Bit

General Call

A

The Start bit (see Figure B-2) indicates the beginning of

a data transfer sequence. The Start bit is defined as the

SDA signal falling when the SCL signal is high.

Slave Address

Valid

Slave Address

Not Valid

A

2^ndBit

1^stBit

Communication

during

EEPROM Write

Cycle

After the device

has received

address and com-

mand, and valid

conditions for

SDA

SCL

S

EEPROM write

FIGURE B-2:

START BIT.

Bus Collision

N/A

I²C module resets,

or a “Don’t Care” if

the collision occurs

on the master’s

Start bit

DS20006368A-page 110

 2020 Microchip Technology Inc.

MCP47FXBX4/8

B.3.1.4

Repeated Start Bit

B.3.1.5

Stop Bit

The Repeated Start bit (see Figure B-5) indicates that

the current master device wishes to continue

communicating with the current slave device without

releasing the I²C bus. The Repeated Start condition is

the same as the Start condition, except that the

Repeated Start bit follows a Start bit (with the Data bits

+ A bit) and not a Stop bit.

The Stop bit (see Figure B-6) Indicates the end of the

I²C data transfer sequence. The Stop bit is defined as

the SDA signal rising when the SCL signal is high.

A Stop bit should reset the I²C interface of the slave

device.

The Start bit is the beginning of a data transfer

sequence and is defined as the SDAsignal falling when

the SCL signal is high.

SDA

SCL

A/A

P

Note 1: A bus collision during the Repeated Start

condition occurs if:

FIGURE B-6:

STOP CONDITION

•SDA is sampled low when SCL goes

from low to high.

RECEIVE OR TRANSMIT MODE.

B.3.2 CLOCK STRETCHING

•SCL goes low before SDA is asserted

low. This may indicate that another

master is attempting to transmit a

data ‘1’.

Clock Stretching is something that the receiving device

can do, to allow additional time to respond to the data

that have been received.

B.3.3

ABORTING A TRANSMISSION

If any part of the I²C transmission does not meet the

command format, it is aborted. This can be intentionally

accomplished with a Start or Stop condition. This is done

so that noisy transmissions (usually an extra Start or Stop

condition) are aborted before they corrupt the device.

1st Bit

SDA

SCL

Sr = Repeated Start

FIGURE B-5:

REPEAT START

CONDITION WAVEFORM.

SDA

SCL

S

1^stBit 2^ndBit 3^rdBit 4^thBit 5^thBit 6^thBit 7^thBit 8^thBit

TYPICAL 8-BIT I²C WAVEFORM FORMAT.

A/A

P

FIGURE B-7:

SDA

SCL

Data allowed

to change

Data or

A valid

Stop

Condition

Start

Condition

FIGURE B-8:

I²C DATA STATES AND BIT SEQUENCE.

 2020 Microchip Technology Inc.

DS20006368A-page 111

MCP47FXBX4/8

B.3.4

SLOPE CONTROL

B.3.6

HS MODE

As the device transitions from HS mode to FS mode,

the slope control parameter changes from the HS

specification to the FS specification.

The I²C specification requires that a High-Speed mode

device be activated to operate in HS (3.4 Mbit/s) mode.

This is done by the master sending a special address

byte following the Start bit. This byte is referred to as

the High-Speed Master Mode Code (HSMMC).

For FS and HS modes, the device has a spike suppres-

sion and a Schmitt Trigger at SDA and SCL inputs.

The device can now communicate at up to 3.4 Mbit/s

on SDA and SCL lines. The device will switch out of the

HS mode on the next Stop condition.

B.3.5

DEVICE ADDRESSING

The I²C slave address control byte is the first byte

received following the Start condition from the master

device. This byte has seven bits to specify the slave

address and the Read/Write control bit.

Figure B-9 shows the I²C slave address byte format,

which contains the seven address bits and

Read/Write (R/W) bit.

The master code is sent as follows:

1. Start condition (S)

2. High-Speed Master Mode Code (0000 1XXX),

The XXXbits are unique to the HS mode master.

a

3. No Acknowledge (A)

After switching to the HS mode, the next transferred

byte is the I²C control byte, which specifies the device

to communicate with and any number of data bytes

plus acknowledgments. The master device can then

either issue a Repeated Start bit to address a different

device (at high speed) or a Stop bit to return to

fast/standard bus speed. After the Stop bit, any other

master device (in a Multi-master system) can arbitrate

for the I²C bus.

Acknowledge Bit

Start Bit

Read/Write Bit

R/W ACK

A2 A1 A0

A6 A5 A4 A3

7-bit Slave Address

Address Byte

FIGURE B-9:

CONTROL BYTE.

I²C SLAVE ADDRESS

See Figure B-10 for an illustration of the HS mode com-

mand sequence.

For more information on the HS mode, or other I²C

modes, refer to the “NXP I²C Specification”.

B.3.6.1

Slope Control

The slope control on the SDA output is different

between the Fast/Standard Speed and the High-Speed

clock modes of the interface.

B.3.6.2

Pulse Gobbler

The pulse gobbler on the SCL pin is automatically

adjusted to suppress spikes < 10 ns during HS mode.

F/S mode

HS mode

P

F/S mode

S ‘0 0 0 0 1 X X X’b A Sr Slave Address R/W A

Data

A/A

HS mode continues

Sr Slave Address

R/W A

HS Select Byte

S = Start bit

Control Byte

Command/Data Byte(s)

Control Byte

Sr = Repeated Start bit

A = Acknowledge bit

A = Not Acknowledge bit

R/W = Read/Write bit

P = Stop bit (Stop condition terminates HS mode)

FIGURE B-10:

HS MODE SEQUENCE.

DS20006368A-page 112

 2020 Microchip Technology Inc.

MCP47FXBX4/8

For details on the operation of the MCP47FXBX4/8’s

General Call commands, see Section 7.3 “General

Call Commands”.

B.3.7

GENERAL CALL

The General Call is a method used by the master

device to communicate with all other slave devices. In

a Multi-master application, the other master devices

operate in Slave mode. The General Call address has

two documented formats. These are shown in

Figure B-11.

Note:

Only one General Call command per issue

of the General Call control byte. Any

additional General Call commands are

ignored and Not Acknowledged.

The I²C specification documents three 7-bit command

bytes.

The I²C specification does not allow ‘00000000’ (00h)

in the second byte. Also, ‘00000100’ and ‘00000110’

functionality is defined by the specification. Lastly, a

data byte with a ‘1’ in the LSb indicates a Hardware

General Call.

Second Byte

S

0

A

x

0

A

P

General Call Address

7-bit Command

Reserved 7-bit commands (by I²C Specification – “NXP Specification # UM10204”, Rev. 03, 19 June 2007)

‘0000 011’b- Reset and Write Programmable Part of Slave Address by Hardware

‘0000 010’b- Write Programmable Part of Slave Address by Hardware

‘0000 000’b- NOT Allowed

The Following is a Hardware General Call Format

n Occurrences of (Data + A)

Second Byte

S

0

0 0

A

x

1

A

x

A P

General Call Address

Master Address

This indicates a Hardware General Call

FIGURE B-11:

GENERAL CALL FORMATS.

 2020 Microchip Technology Inc.

DS20006368A-page 113

MCP47FXBX4/8

NOTES:

DS20006368A-page 114

 2020 Microchip Technology Inc.

MCP47FXBX4/8

C.3

Monotonic Operation

APPENDIX C: TERMINOLOGY

Monotonic operation means that the device’s output

voltage (V_OUT) increases with every one code step

(LSb) increment (from V_SSto the DAC’s reference

voltage (V_DDor V_REF)).

C.1

Resolution

The resolution is the number of DAC output states that

divide the Full-Scale Range (FSR). For the 12-bit DAC,

the resolution is 2¹², meaning the DAC code ranges

from 0 to 4095.

V_S64

40h

3Fh

V_S63

Note:

When there are 2^Nresistors in the resistor

ladder and 2^Ntap points, the full-scale

DAC register code is the resistor element

(1 LSb) from the source reference voltage

(V_DDor V_REF).

3Eh

V_S3

03h

02h

V_S1

C.2

Least Significant Bit (LSb)

This is the voltage difference between two successive

codes. For a given output voltage range, it is divided by

the resolution of the device (Equation C-1). The range

may be V_DD(or V_REF) to V_SS(ideal), the DAC register

codes across the linear range of the output driver

(Measured 1), or full scale to zero scale (Measured 2).

V_S0

01h

00h

V_W(@ tap)

n = ?

V_W

=

V_Sn+ V_{ZS(@ Tap 0)}

n = 0

EQUATION C-1:

Ideal

LSb VOLTAGE

CALCULATION

Voltage (V_W~= V_OUT

)

FIGURE C-1:

V_W(V_OUT).

V

DD

REF

---------------

N

or

V

= ------------

LSb(IDEAL)

N

2

Measured 1

V

– V

OUT(@4000)

OUT(@100)

V

= -----------------------------------------------------------------------------

LSb(Measured)

4000 – 100

Measured 2

V

– V

OUT(@FS)

OUT(@ZS)

V

= ---------------------------------------------------------------------

LSb

N

2

– 1

2^N= 4096 (MCP47FEB2X)

= 1024 (MCP47FEB1X)

= 256 (MCP47FEB0X)

 2020 Microchip Technology Inc.

DS20006368A-page 115

MCP47FXBX4/8

C.4

Full-Scale Error (E )

C.6

Total Unadjusted Error (E )

T

FS

The Full-Scale error (see Figure C-3) is the error on

the V_OUTpin relative to the expected V_OUTvoltage

(theoretical) for the maximum device DAC register

code (code FFFh for 12-bit, code 3FFh for 10-bit, and

code FFh for 8-bit), see Equation C-2. The error

depends on the resistive load on the V_OUTpin (and

where that load is tied to, such as V_SSor V_DD). For

loads (to V_SS) greater than specified, the Full-Scale

error will be greater.

The Total Unadjusted error (E_T) is the difference

between the ideal and measured V_OUTvoltage. Typi-

cally, calibration of the output voltage is implemented

to improve system’s performance.

The error in bits is determined by the theoretical voltage

step size to give an error in LSb.

Equation C-4 shows the Total Unadjusted error

calculation:

The error in bits is determined by the theoretical voltage

step size to give an error in LSb.

EQUATION C-4:

TOTAL UNADJUSTED

ERROR CALCULATION

EQUATION C-2:

FULL-SCALE ERROR

V

– V



OUT_Actual(@Code)

OUT_Ideal(@Code)

E

= ------------------------------------------------------------------------------------------------------------------------

T

V

LSb(Ideal)

V

– V

OUT(@FS)

IDEAL(@FS)

E

= --------------------------------------------------------------------------

FS

V

LSb(IDEAL)

Where:

E_Tis expressed in LSb.

Where:

V_{OUT_Actual(@Code)}= The measured DAC

output voltage at the

E

is expressed in LSb.

FS

V

is the V

voltage when the DAC

OUT

OUT(@FS)

specified code

register code is at full scale.

V_{OUT_Ideal(@Code)}= The calculated DAC

output voltage at the

V

is the ideal output voltage when the

DAC register code is at full scale.

IDEAL(@FS)

specified code

is the theoretical voltage step size.

LSb(IDEAL)

(code × V_LSb(Ideal)

)

V_LSb(Ideal)= V_REF/# Steps

C.5

Zero-Scale Error (E )

ZS

12-bit = V_REF/4096

10-bit = V_REF/1024

8-bit = V_REF/256

The Zero-Scale error (see Figure C-2) is the difference

between the ideal and the measured V_OUTvoltage with

the DAC register code equal to 000h (Equation C-3).

The error depends on the resistive load on the V_OUTpin

(and where that load is tied to, such as V_SSor V_DD). For

loads (to V_DD) greater than specified, the Zero-Scale

error will be greater.

The error in bits is determined by the theoretical voltage

step size to give an error in LSb.

EQUATION C-3:

ZERO SCALE ERROR

V

OUT(@ZS)

E

= ---------------------------------

ZS

V

LSb(IDEAL)

Where:

E

is expressed in LSb.

FS

V

is the V

voltage when the DAC

OUT

OUT(@ZS)

register code is at zero scale.

V

is the theoretical voltage step size.

LSb(IDEAL)

DS20006368A-page 116

 2020 Microchip Technology Inc.

MCP47FXBX4/8

C.7

Offset Error (E

)

C.9

Gain Error (E )

G

OS

The Offset error is the delta voltage of the V_OUT

voltage from the ideal output voltage at the specified

code. This code is specified where the output amplifier

is in the linear operating range; for the

MCP47FXBX4/8, we specify code 100 (decimal). Off-

set error does not include Gain error, see Figure C-2.

Gain error is a calculation based on the ideal slope

using the voltage boundaries for the linear range of the

output driver (code 100 and code 4000) (see Figure C-

3). The Gain error calculation nullifies the device’s

Offset error.

The Gain error indicates how well the slope of the

actual transfer function matches the slope of the ideal

transfer function. The gain error is usually expressed

as a percent of Full-Scale Range (% of FSR) or in LSb.

FSR is the ideal full-scale voltage of the DAC (see

Equation C-5).

This error is expressed in mV. Offset error can be neg-

ative or positive. The Offset error can be calibrated by

software in application circuits.

Gain Error (E )

G

(at code = 4000)

Actual

Transfer

Function

V

REF

Actual

Transfer

Function

Full-Scale

Error (E

)

FS

Zero-Scale

Ideal Transfer

Function

Ideal Transfer

Function Shifted by

Error (E

)

ZS

Offset Error

(crosses at start of

defined linear range)

0

100

4000

DAC Input Code

Ideal Transfer

Function

Offset

Error (E

)

OS

0

100

4000 4095

DAC Input Code

FIGURE C-2:

GAIN ERROR).

OFFSET ERROR (ZERO

FIGURE C-3:

SCALE ERROR EXAMPLE.

GAIN ERROR AND FULL-

C.8

Offset Error Drift (E

)

OSD

EQUATION C-5:

EXAMPLE GAIN ERROR

The Offset Error Drift is the variation in Offset error due

to a change in ambient temperature. The Offset Error

Drift is typically expressed in ppm/°C or µV/°C.

V

– V



OUT(@4000)

OS

OUT_Ideal(@4000)

E

= ----------------------------------------------------------------------------------------------------------------------  1 0 0

G

V

Full-Scale Range

Where:

E_Gis expressed in % of FSR.

V_OUT(@4000)= The measured DAC

output voltage at the

specified code

V_{OUT_Ideal(@4000)}= The calculated DAC

output voltage at the

specified code

(4000 × V_LSb(Ideal)

)

V_OS= Measured offset voltage

V_{Full-Scale Range}= Expected full-scale

output value (such as the

V_REFvoltage)

C.10 Gain Error Drift (E

)

GD

The Gain Error Drift is the variation in Gain error due to

a change in ambient temperature. The Gain Error Drift

is typically expressed in ppm/°C (of FSR).

 2020 Microchip Technology Inc.

DS20006368A-page 117

MCP47FXBX4/8

C.11 Integral Nonlinearity (INL)

C.12 Differential Nonlinearity (DNL)

The Integral Nonlinearity (INL) error is the maximum

deviation of an actual transfer function from an ideal

transfer function (straight line) passing through the

defined end points of the DAC transfer function (after

Offset and Gain errors have been removed).

The Differential Nonlinearity (DNL) error (see

Figure C-5) is the measure of step-size between codes

in an actual transfer function. The ideal step-size

between codes is 1 LSb. A DNL error of zero would

imply that every code is exactly 1 LSb wide. If the DNL

error is less than 1 LSb, the DAC guarantees monotonic

output and no missing codes. Equation C-7 shows how

to calculate the DNL error between any two adjacent

codes in LSb.

For the MCP47FXBX4/8, INL is calculated using the

defined end points, DAC code 100 and code 4000. INL

can be expressed as a percentage of FSR or in LSb.

INL is also called Relative Accuracy. Equation C-6

shows how to calculate the INL error in LSb and

Figure C-4 shows an example of INL accuracy.

EQUATION C-7:

DNL ERROR

Positive INL means V_OUTvoltage higher than the ideal

one. Negative INL means V_OUTvoltage lower than the

ideal one.

V

– V



OUT(code = n+1)

OUT(code = n)

E

= ---------------------------------------------------------------------------------------------------- – 1

DNL

V

LSb(Measured)

Where:

EQUATION C-6:

INL ERROR

– V

DNL is expressed in LSb.

V



OUT

Calc_Ideal

V_{OUT(code = n)}= The measured DAC output

voltage with a given DAC

E

= ---------------------------------------------------------

INL

V

LSb(Measured)

register code.

Where:

V_{LSb(Measured)}= For Measured:

(V_OUT(4000)– V_OUT(100))/3900

INL is expressed in LSb.

V_{Calc_Ideal}= Code × V_{LSb(Measured)}+ V_OS

V_{OUT(Code = n)}= The measured DAC output

voltage with a given DAC

register code

7

DNL = 0.5 LSb

V_{LSb(Measured)}= For Measured:

6

(V_OUT(4000)– V_OUT(100))/3900

V_OS= Measured offset voltage

5

DNL = 2 LSb

4

3

Analog

Output

(LSb)

7

2

1

0

INL = < -1 LSb

6

INL = -1 LSb

5

Analog 4

Output

000 001 010 011 100 101 110 111

DAC Input Code

INL = 0.5 LSb

3

2

1

0

(LSb)

Ideal Transfer Function

Actual Transfer Function

FIGURE C-5:

DNL ACCURACY.

000 001 010 011 100 101 110 111

DAC Input Code

Ideal Transfer Function

Actual Transfer Function

FIGURE C-4:

INL ACCURACY.

DS20006368A-page 118

 2020 Microchip Technology Inc.

MCP47FXBX4/8

C.13 Settling Time

C.17 Power-Supply Sensitivity (PSS)

The settling time is the time delay required for the V_OUT

voltage to settle into its new output value. This time is

measured from the start of code transition to when the

PSS indicates how the output of the DAC is affected by

changes in the supply voltage. PSS is the ratio of the

change in V_OUTto a change in V_DDfor mid-scale output

of the DAC. The V_OUTis measured while the V_DDis

varied from 5.5V to 2.7V as a step (V_REFvoltage held

constant), and expressed in %/%, which is the %

change of the DAC output voltage with respect to the %

change of the V_DDvoltage.

V_OUTvoltage is within the specified accuracy.

For the MCP47FXBX4/8, the settling time is a mea-

surement of the time delay until the V_OUTvoltage

reaches within 0.5 LSb of its final value, when the vol-

atile DAC register changes from 1/4 to 3/4 of the FSR

(12-bit device: 400h to C00h).

EQUATION C-8:

PSS CALCULATION

C.14 Major Code Transition Glitch

V

– V

  V

OUT(@5.5V)

OUT(@2.7V)

OUT(@5.5V)

PSS = ----------------------------------------------------------------------------------------------------------------------------

Major code transition glitch is the impulse energy

injected into the DAC analog output when the code in

the DAC register changes the state. It is normally spec-

ified as the area of the glitch in nV-Sec and is measured

when the digital code is changed by 1 LSb at the major

carry transition (Example: 011...111 to 100...

000, or 100... 000to 011 ... 111).

5.5V – 2.7V  5.5V

Where:

PSS is expressed in % / %.

V_OUT(@5.5V)= The measured DAC output

voltage with V_DD= 5.5V

V_OUT(@2.7V)= The measured DAC output

voltage with V_DD= 2.7V

C.15 Digital Feed-through

The digital feed-through is the glitch that appears at the

analog output caused by coupling from the digital input

pins of the device. The area of the glitch is expressed

in nV-Sec and is measured with a full-scale change

(Example: all ‘0’s to all ‘1’s and vice versa) on the digital

input pins. The digital feed-through is measured when

the DAC is not written to the output register.

C.18 Power-Supply Rejection Ratio

(PSRR)

PSRR indicates how the output of the DAC is affected

by changes in the supply voltage. PSRR is the ratio of

the change in V_OUTto a change in V_DDfor full-scale

output of the DAC. The V_OUTis measured while the

V_DDis varied ±10% (V_REFvoltage held constant) and

expressed in dB or µV/V.

C.16 -3 dB Bandwidth

This is the frequency of the signal at the V_REFpin that

causes the voltage at the V_OUTpin to fall -3 dB from a

static value on the V_REFpin. The output decreases due

to the RC characteristics of the resistor ladder and the

characteristics of the output buffer.

C.19

V

Temperature Coefficient

OUT

The V_OUTtemperature coefficient quantifies the error in

the resistor ladder’s resistance ratio (DAC register

code value) and output buffer due to temperature drift.

C.20 Absolute Temperature Coefficient

The absolute temperature coefficient quantifies the

error in the end-to-end output voltage (nominal output

voltage V_OUT) due to temperature drift. For a DAC, this

error is typically not an issue due to the ratiometric

aspect of the output.

C.21 Noise Spectral Density

The noise spectral density is a measurement of the

device’s internally generated random noise and is

characterized as a spectral density (voltage per √Hz).

It is measured by loading the DAC to the mid-scale

value and measuring the noise at the V_OUTpin. It is

measured in nV/√Hz.

 2020 Microchip Technology Inc.

DS20006368A-page 119

MCP47FXBX4/8

NOTES:

DS20006368A-page 120

 2020 Microchip Technology Inc.

MCP47FXBX4/8

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Examples:

PART NO.

Device

X

/XX

XX

a) MCP47FEB04-E/MQ:

Quad-Channel, 8-Bit Nonvolatile

DAC, Extended Temperature,

20LD VQFN.

Tape and

Reel

Temperature Package

Range

Count

b) MCP47FEB08T-E/MQ:

Octal-Channel, 8-Bit Nonvolatile

DAC, Tape and Reel, Extended

Temperature, 20LD VQFN.

Device:

MCP47FXB0X: Quad/Octal-Channel, 8-Bit DAC

with I²C Interface

c) MCP47FEB18-20E/ST: Octal-Channel, 10-Bit Nonvolatile

DAC, Extended Temperature,

MCP47FXB1X: Quad/Octal-Channel, 10-Bit DAC

with I²C Interface

20LD TSSOP.

d) MCP47FEB18T-20E/ST: Octal-Channel, 10-Bit Nonvolatile

DAC, Tape and Reel, Extended

MCP47FXB2X: Quad/Octal-Channel, 12-Bit DAC

with I²C Interface

Temperature, 20LD TSSOP.

e) MCP47FVB28-E/MQ:

f) MCP47FVB28T-E/MQ:

Octal-Channel, 12-Bit Volatile

DAC, Extended Temperature,

20LD VQFN.

Octal-Channel, 12-Bit Volatile

DAC, Tape and Reel, Extended

Temperature, 20LD VQFN.

Tape and Reel:

Pin Count:

T

=

Tape and Reel

Tube

Blank

20-Lead

Temperature

Range:

E

=

-40°C to +125°C (Extended)

Package:

MQ

ST

=

Plastic Quad Flat, No Lead Package

(VQFN), 5 x 5 mm, 20-Lead

Note 1:

Tape and Reel identifier only appears in the

catalog part number description. This

identifier is used for ordering purposes and

is not printed on the device package. Check

with your Microchip Sales Office for package

availability with the Tape and Reel option.

Plastic Thin Shrink Small Outline

Package (TSSOP), 20-Lead

 2020 Microchip Technology Inc.

DS20006368A-page 121

MCP47FXBX4/8

NOTES:

DS20006368A-page 122

 2020 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights unless otherwise stated.

Trademarks

The Microchip name and logo, the Microchip logo, Adaptec,

AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT,

chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex,

flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck,

LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi,

Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer,

PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire,

Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST,

SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,

TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA

are registered trademarks of Microchip Technology Incorporated in

the U.S.A. and other countries.

APT, ClockWorks, The Embedded Control Solutions Company,

EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load,

IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision

Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire,

SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub,

TimePictra, TimeProvider, Vite, WinPath, and ZL are registered

trademarks of Microchip Technology Incorporated in the U.S.A.

Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any

Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard,

CryptoAuthentication, CryptoAutomotive, CryptoCompanion,

CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average

Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial

Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker,

KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF,

MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,

Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,

PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple

Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,

SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,

USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and

ZENA are trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in

the U.S.A.

The Adaptec logo, Frequency on Demand, Silicon Storage

Technology, and Symmcom are registered trademarks of Microchip

Technology Inc. in other countries.

GestIC is a registered trademark of Microchip Technology Germany

II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in

other countries.

All other trademarks mentioned herein are property of their

respective companies.

ISBN: 978-1-5224-6267-5

For information regarding Microchip’s Quality Management Systems,

please visit www.microchip.com/quality.

 2020 Microchip Technology Inc.

DS20006368A-page 123

Worldwide Sales and Service

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://www.microchip.com/

support

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Tel: 61-2-9868-6733

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Tel: 91-80-3090-4444

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Denmark - Copenhagen

Tel: 45-4485-5910

Fax: 45-4485-2829

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Tel: 86-28-8665-5511

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Web Address:

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Tel: 33-1-69-53-63-20

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Tel: 86-769-8702-9880

Japan - Tokyo

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Atlanta

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Tel: 678-957-9614

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Tel: 886-3-577-8366

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

Israel - Ra’anana

Tel: 972-9-744-7705

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Tel: 86-755-8864-2200

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Tel: 886-7-213-7830

Italy - Milan

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Fax: 39-0331-466781

China - Suzhou

Tel: 86-186-6233-1526

Taiwan - Taipei

Tel: 886-2-2508-8600

Detroit

Novi, MI

Tel: 248-848-4000

China - Wuhan

Tel: 86-27-5980-5300

Thailand - Bangkok

Tel: 66-2-694-1351

Italy - Padova

Tel: 39-049-7625286

Houston, TX

Tel: 281-894-5983

China - Xian

Tel: 86-29-8833-7252

Vietnam - Ho Chi Minh

Tel: 84-28-5448-2100

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Indianapolis

Noblesville, IN

Tel: 317-773-8323

Fax: 317-773-5453

Tel: 317-536-2380

China - Xiamen

Tel: 86-592-2388138

Norway - Trondheim

Tel: 47-7288-4388

China - Zhuhai

Tel: 86-756-3210040

Poland - Warsaw

Tel: 48-22-3325737

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

Tel: 951-273-7800

Romania - Bucharest

Tel: 40-21-407-87-50

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

Raleigh, NC

Tel: 919-844-7510

Sweden - Gothenberg

Tel: 46-31-704-60-40

New York, NY

Tel: 631-435-6000

Sweden - Stockholm

Tel: 46-8-5090-4654

San Jose, CA

Tel: 408-735-9110

Tel: 408-436-4270

UK - Wokingham

Tel: 44-118-921-5800

Fax: 44-118-921-5820

Canada - Toronto

Tel: 905-695-1980

Fax: 905-695-2078

DS20006368A-page 124

 2020 Microchip Technology Inc.

02/28/20


型号：	MCP47FXB2XT-EMQ
厂家：	MICROCHIP
描述：	8/10/12-Bit Quad/Octal Voltage Output, 6 LSb INL Digital-to-Analog Converters with IÂ²C Interface
文件：	总124页 (文件大小：9591K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MCP47FXB2XT-EMQ [MICROCHIP]

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