MCP42050-E/P
更新时间:2024-09-18 01:50:29
品牌:MICROCHIP
描述:Single/Dual Digital Potentiometer with SPI⑩ Interface
MCP42050-E/P 概述
Single/Dual Digital Potentiometer with SPI⑩ Interface 单/双通道数字电位SPI⑩接口 数字电位器 数字电位计
MCP42050-E/P 规格参数
是否无铅: | 不含铅 | 是否Rohs认证: | 符合 |
生命周期: | Active | 零件包装代码: | DIP |
包装说明: | DIP, DIP14,.3 | 针数: | 14 |
Reach Compliance Code: | compliant | ECCN代码: | EAR99 |
HTS代码: | 8542.39.00.01 | Factory Lead Time: | 14 weeks |
风险等级: | 1.63 | Samacsys Confidence: | |
Samacsys Status: | Released | Samacsys PartID: | 586887 |
Samacsys Pin Count: | 14 | Samacsys Part Category: | Integrated Circuit |
Samacsys Package Category: | Other | Samacsys Footprint Name: | DIP254P762X432-14 |
Samacsys Released Date: | 2017-01-11 17:13:05 | Is Samacsys: | N |
标称带宽: | 0.28 kHz | 控制接口: | 3-WIRE SERIAL |
转换器类型: | DIGITAL POTENTIOMETER | JESD-30 代码: | R-PDIP-T14 |
JESD-609代码: | e3 | 长度: | 19.05 mm |
功能数量: | 2 | 位置数: | 256 |
端子数量: | 14 | 最高工作温度: | 125 °C |
最低工作温度: | -40 °C | 封装主体材料: | PLASTIC/EPOXY |
封装代码: | DIP | 封装等效代码: | DIP14,.3 |
封装形状: | RECTANGULAR | 封装形式: | IN-LINE |
峰值回流温度(摄氏度): | NOT APPLICABLE | 电源: | 3/5 V |
认证状态: | Not Qualified | 电阻定律: | LINEAR |
最大电阻器端电压: | 5 V | 最小电阻器端电压: | |
座面最大高度: | 4.32 mm | 子类别: | Digital Potentiometers |
标称供电电压: | 5 V | 表面贴装: | NO |
技术: | CMOS | 标称温度系数: | 800 ppm/°C |
温度等级: | AUTOMOTIVE | 端子面层: | Matte Tin (Sn) |
端子形式: | THROUGH-HOLE | 端子节距: | 2.54 mm |
端子位置: | DUAL | 处于峰值回流温度下的最长时间: | NOT APPLICABLE |
标称总电阻: | 50000 Ω | 宽度: | 7.62 mm |
Base Number Matches: | 1 |
MCP42050-E/P 数据手册
通过下载MCP42050-E/P数据手册来全面了解它。这个PDF文档包含了所有必要的细节,如产品概述、功能特性、引脚定义、引脚排列图等信息。
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MCP41XXX/42XXX
Single/Dual Digital Potentiometer with SPI™ Interface
Features
Description
• 256 taps for each potentiometer
The MCP41XXX and MCP42XXX devices are 256-
position, digital potentiometers available in 10 kΩ,
50 kΩ and 100 kΩ resistance versions. The
MCP41XXX is a single-channel device and is offered in
an 8-pin PDIP or SOIC package. The MCP42XXX con-
tains two independent channels in a 14-pin PDIP, SOIC
or TSSOP package. The wiper position of the
MCP41XXX/42XXX varies linearly and is controlled via
an industry-standard SPI interface. The devices con-
sume <1 µA during static operation. A software shut-
down feature is provided that disconnects the “A”
terminal from the resistor stack and simultaneously con-
nects the wiper to the “B” terminal. In addition, the dual
MCP42XXX has a SHDN pin that performs the same
function in hardware. During shutdown mode, the con-
tents of the wiper register can be changed and the
potentiometer returns from shutdown to the new value.
The wiper is reset to the mid-scale position (80h) upon
power-up. The RS (reset) pin implements a hardware
reset and also returns the wiper to mid-scale. The
MCP42XXX SPI interface includes both the SI and SO
pins, allowing daisy-chaining of multiple devices. Chan-
nel-to-channel resistance matching on the MCP42XXX
varies by less than 1%. These devices operate from a
single 2.7 - 5.5V supply and are specified over the
extended and industrial temperature ranges.
• Potentiometer values for 10 kΩ, 50 kΩ and
100 kΩ
• Single and dual versions
• SPI™ serial interface (mode 0,0 and 1,1)
•
±1 LSB max INL & DNL
• Low power CMOS technology
• 1 µA maximum supply current in static operation
• Multiple devices can be daisy-chained together
(MCP42XXX only)
• Shutdown feature open circuits of all resistors for
maximum power savings
• Hardware shutdown pin available on MCP42XXX
only
• Single supply operation (2.7V - 5.5V)
• Industrial temperature range: -40°C to +85°C
• Extended temperature range: -40°C to +125°C
Block Diagram
SHDN
RS
VDD
VSS
PB0
Resistor
Wiper
Control
Logic
Array 0
Register
Package Types
PDIP/SOIC
PA0
PW0
PB1
PA1
PW1
CS
SI
CS
SCK
SI
1
2
3
4
VDD
8
7
6
5
Wiper Resistor
Register
16-Bit
Shift
Array 1*
PB0
PW0
PA0
Register
SCK
VSS
S0
*Potentiometer P1 is only available on the dual
PDIP/SOIC/TSSOP
MCP42XXX version.
14
1
VDD
CS
13
12
11
10
9
2
3
4
5
6
7
SCK
SI
VSS
PB1
PW1
PA1
SO
SHDN
RS
PB0
PW0
PA0
8
2003 Microchip Technology Inc.
DS11195C-page 1
MCP41XXX/42XXX
1.0
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS: 10 kΩ VERSION
Electrical Characteristics: Unless otherwise indicated, V = +2.7V to 5.5V, T = -40°C to +85°C (TSSOP devices are only specified at +25°C and
DD
A
+85°C). Typical specifications represent values for V = 5V, V = 0V, V = 0V, T = +25°C.
DD
SS
B
A
Parameters
Rheostat Mode
Nominal Resistance
Rheostat Differential Non Linearity
Rheostat Integral Non Linearity
Rheostat Tempco
Sym
Min
Typ
Max
Units
Conditions
T = +25°C (Note 1)
A
Note 2
Note 2
R
8
10
±1/4
±1/4
800
52
73
—
0.2
12
+1
+1
—
100
125
+1
1
kΩ
LSB
LSB
ppm/°C
Ω
R-DNL
R-INL
-1
-1
—
—
—
-1
—
∆R /∆T
AB
Wiper Resistance
R
R
V
V
= 5.5V, I = 1 mA, code 00h
W
= 2.7V, I = 1 mA, code 00h
W
W
W
DD
DD
Ω
Wiper Current
I
mA
%
W
Nominal Resistance Match
Potentiometer Divider
Resolution
∆R/R
MCP42010 only, P0 to P1; T = +25°C
A
N
N
DNL
INL
8
8
—
—
±1/4
±1/4
1
-0.7
-0.7
+0.7
+0.7
—
—
+1
+1
—
0
0
+2
+2
Bits
Bits
LSB
LSB
Monotonicity
Differential Non-Linearity
Integral Non-Linearity
Voltage Divider Tempco
Full Scale Error
-1
-1
—
-2
-2
0
Note 3
Note 3
∆V /∆T
ppm/°C Code 80h
W
V
V
V
V
LSB
LSB
LSB
LSB
Code FFh, V = 5V, see Figure 2-25
DD
Code FFh, V = 3V, see Figure 2-25
DD
Code 00h, V = 5V, see Figure 2-25
DD
Code 00h, V = 3V, see Figure 2-25
DD
WFSE
WFSE
WZSE
WZSE
Zero Scale Error
0
Resistor Terminals
Voltage Range
Capacitance (C or C )
Capacitance
V
0
—
—
—
15
5.6
V
—
—
Note 4
A,B,W
DD
pF
pF
f = 1 MHz, Code = 80h, see Figure 2-30
f = 1 MHz, Code = 80h, see Figure 2-30
A
B
CW
Dynamic Characteristics (All dynamic characteristics use V = 5V)
DD
Bandwidth -3dB
BW
—
1
—
—
MHz
µS
V = 0V, Measured at Code 80h,
B
Output Load = 30 PF
= V ,V = 0V, ±1% Error Band, Transition
Settling Time
t
—
2
V
A
S
DD
B
from Code 00h to Code 80h, Output Load = 30 pF
= Open, Code 80h, f =1 kHz
Resistor Noise Voltage
Crosstalk
e
—
—
9
-95
—
—
nV/√Hz
dB
V
A
NWB
C
V = V , V = 0V (Note 5)
A DD B
T
Digital Inputs/Outputs (CS, SCK, SI, SO) See Figure 2-12 for RS and SHDN pin operation
Schmitt Trigger High-Level Input Voltage
Schmitt Trigger Low-Level Input Voltage
Hysteresis of Schmitt Trigger Inputs
Low-Level Output Voltage
V
V
0.7V
—
—
—
—
0.05V
—
—
0.3V
—
0.40
—
V
V
IH
DD
IL
DD
V
HYS
DD
V
—
V
V
I
I
= 2.1 mA, V = 5V
DD
= -400 µA, V = 5V
OH DD
OL
OL
High-Level Output Voltage
V
V
- 0.5
—
OH
DD
Input Leakage Current
Pin Capacitance (All inputs/outputs)
Power Requirements
I
-1
—
—
10
+1
—
µA
pF
CS = V , V = V or V , includes V SHDN=0
DD IN SS DD A
LI
C
, C
V
= 5.0V, T = +25°C, f = 1 MHz
A c
IN
OUT
DD
Operating Voltage Range
Supply Current, Active
V
2.7
—
—
340
5.5
500
V
µA
DD
I
V
= 5.5V, CS = V , f
= 10 MHz,
DDA
DD
SS SCK
SO = Open, Code FFh (Note 6)
Supply Current, Static
Power Supply Sensitivity
I
—
—
—
0.01
0.0015
0.0015
1
µA
%/%
%/%
CS, SHDN, RS = V = 5.5V, SO = Open (Note 6)
DDS
DD
PSS
PSS
0.0035
0.0035
V
V
= 4.5V - 5.5V, V = 4.5V, Code 80h
A
DD
DD
= 2.7V - 3.3V, V = 2.7V, Code 80h
A
Note 1:
2:
V
= V , no connection on wiper.
AB DD
Rheostat position non-linearity R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum
resistance wiper positions. R-DNL measures the relative step change from the ideal between successive tap positions. I = 50 µA for
W
V
= 3V and I = 400 µA for V = 5V for 10 kΩ version. See Figure 2-26 for test circuit.
W DD
DD
3:
4:
INL and DNL are measured at V with the device configured in the voltage divider or potentiometer mode. V = V and V = 0V. DNL
W A DD B
specification limits of ±1 LSB max are specified monotonic operating conditions. See Figure 2-25 for test circuit.
Resistor terminals A,B and W have no restrictions on polarity with respect to each other. Full-scale and zero-scale error were measured
using Figure 2-25.
5:
6:
Measured at V pin where the voltage on the adjacent V pin is swinging full-scale.
W W
Supply current is independent of current through the potentiometers.
DS11195C-page 2
2003 Microchip Technology Inc.
MCP41XXX/42XXX
DC CHARACTERISTICS: 50 kΩ VERSION
Electrical Characteristics: Unless otherwise indicated, V = +2.7V to 5.5V, T = -40°C to +85°C (TSSOP devices are only specified at +25°C and
DD
A
+85°C). Typical specifications represent values for V = 5V, V = 0V, V = 0V, T = +25°C.
DD
SS
B
A
Parameters
Rheostat Mode
Nominal Resistance
Rheostat Differential Non-Linearity
Rheostat Integral Non-Linearity
Rheostat Tempco
Sym
Min
Typ
Max
Units
Conditions
T = +25°C (Note 1)
A
Note 2
Note 2
R
35
-1
-1
—
—
—
-1
—
50
±1/4
±1/4
800
125
175
—
65
+1
+1
—
175
250
+1
1
kΩ
LSB
LSB
ppm/°C
Ω
R-DNL
R-INL
∆R /∆T
AB
Wiper Resistance
R
R
V
V
= 5.5V, I = 1 mA, code 00h
W
= 2.7V, I = 1 mA, code 00h
W
W
W
DD
DD
Ω
Wiper Current
I
mA
%
W
Nominal Resistance Match
Potentiometer Divider
Resolution
∆R/R
0.2
MCP42050 only, P0 to P1;T = +25°C
A
N
N
DNL
INL
8
8
—
—
±1/4
±1/4
1
-0.25
-0.35
+0.25
+0.35
—
—
+1
+1
—
0
0
+1
+1
Bits
Bits
LSB
LSB
Monotonicity
Differential Non-Linearity
Integral Non-Linearity
Voltage Divider Tempco
Full-Scale Error
-1
-1
—
-1
-1
0
Note 3
Note 3
∆V /∆T
ppm/°C Code 80h
W
V
V
V
V
LSB
LSB
LSB
LSB
Code FFh, V = 5V, see Figure 2-25
DD
Code FFh, V = 3V, see Figure 2-25
DD
Code 00h, V = 5V, see Figure 2-25
DD
Code 00h, V = 3V, see Figure 2-25
DD
WFSE
WFSE
WZSE
WZSE
Zero-Scale Error
0
Resistor Terminals
Voltage Range
Capacitance (C or C )
Capacitance
V
0
—
—
—
11
5.6
V
—
—
Note 4
A,B,W
DD
pF
pF
f =1 MHz, Code = 80h, see Figure 2-30
f =1 MHz, Code = 80h, see Figure 2-30
A
B
C
W
Dynamic Characteristics (All dynamic characteristics use V = 5V)
DD
Bandwidth -3dB
BW
—
280
—
—
MHz
µS
V = 0V, Measured at Code 80h,
B
Output Load = 30 PF
= V ,V = 0V, ±1% Error Band, Transition
Settling Time
t
—
8
V
A
S
DD
B
from Code 00h to Code 80h, Output Load = 30 pF
= Open, Code 80h, f =1 kHz
Resistor Noise Voltage
Crosstalk
e
—
—
20
-95
—
—
nV/√Hz
dB
V
A
NWB
C
V = V , V = 0V (Note 5)
A DD B
T
Digital Inputs/Outputs (CS, SCK, SI, SO) See Figure 2-12 for RS and SHDN pin operation.
Schmitt Trigger High-Level Input Voltage
Schmitt Trigger Low-Level Input Voltage
Hysteresis of Schmitt Trigger Inputs
Low-Level Output Voltage
V
V
0.7V
—
—
—
—
0.05V
—
—
0.3V
—
0.40
—
V
V
IH
DD
IL
DD
V
HYS
DD
V
—
V
V
I
I
= 2.1 mA, V = 5V
DD
OL
OL
High-Level Output Voltage
V
V
- 0.5
—
= -400 µA, V = 5V
OH DD
OH
DD
Input Leakage Current
Pin Capacitance (All inputs/outputs)
Power Requirements
I
-1
—
—
10
+1
—
µA
pF
CS = V , V = V or V , includes V SHDN=0
DD IN SS DD A
LI
C
, C
V
= 5.0V, T = +25°C, f = 1 MHz
A c
IN
OUT
DD
Operating Voltage Range
Supply Current, Active
V
2.7
—
—
340
5.5
500
V
µA
DD
I
V
= 5.5V, CS = V , f
= 10 MHz,
DDA
DD
SS SCK
SO = Open, Code FFh (Note 6)
Supply Current, Static
Power Supply Sensitivity
I
—
—
—
0.01
0.0015
0.0015
1
µA
%/%
%/%
CS, SHDN, RS = V = 5.5V, SO = Open (Note 6)
DDS
DD
PSS
PSS
0.0035
0.0035
V
V
= 4.5V - 5.5V, V = 4.5V, Code 80h
A
DD
DD
= 2.7V - 3.3V, V = 2.7V, Code 80h
A
Note 1:
2:
V
= V , no connection on wiper.
AB DD
Rheostat position non-linearity R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum
resistance wiper positions. R-DNL measures the relative step change from the ideal between successive tap positions. I = V /R for
W
DD
+3V or +5V for 50 kΩ version. See Figure 2-26 for test circuit.
INL and DNL are measured at V with the device configured in the voltage divider or potentiometer mode. V = V and V = 0V. DNL
3:
4:
W
A
DD
B
specification limits of ±1 LSB max are specified monotonic operating conditions. See Figure 2-25 for test circuit.
Resistor terminals A,B and W have no restrictions on polarity with respect to each other. Full-scale and zero-scale error were measured
using Figure 2-25.
5:
6:
Measured at V pin where the voltage on the adjacent V pin is swinging full scale.
W W
Supply current is independent of current through the potentiometers.
2003 Microchip Technology Inc.
DS11195C-page 3
MCP41XXX/42XXX
DC CHARACTERISTICS: 100 kΩ VERSION
Electrical Characteristics: Unless otherwise indicated, V = +2.7V to 5.5V, T = -40°C to +85°C (TSSOP devices are only specified at +25°C and
DD
A
+85°C). Typical specifications represent values for V = 5V, V = 0V, V = 0V, T = +25°C.
DD
SS
B
A
Parameters
Rheostat Mode
Nominal Resistance
Rheostat Differential Non-Linearity
Rheostat Integral Non-Linearity
Rheostat Tempco
Sym
Min
Typ
Max
Units
Conditions
T = +25°C (Note 1)
A
Note 2
Note 2
R
70
-1
-1
—
—
—
-1
—
100
±1/4
±1/4
800
125
175
—
130
+1
+1
—
175
250
+1
1
kΩ
LSB
LSB
ppm/°C
Ω
R-DNL
R-INL
∆R /∆T
AB
Wiper Resistance
R
R
V
V
= 5.5V, I = 1 mA, code 00h
W
= 2.7V, I = 1 mA, code 00h
W
W
W
DD
DD
Ω
Wiper Current
I
mA
%
W
Nominal Resistance Match
Potentiometer Divider
Resolution
∆R/R
0.2
MCP42010 only, P0 to P1;T = +25°C
A
N
N
DNL
INL
8
8
—
—
±1/4
±1/4
1
-0.25
-0.35
+0.25
+0.35
—
—
+1
+1
—
0
0
+1
+1
Bits
Bits
LSB
LSB
Monotonicity
Differential Non-Linearity
Integral Non-Linearity
Voltage Divider Tempco
Full-Scale Error
-1
-1
—
-1
-1
0
Note 3
Note 3
∆V /∆T
ppm/°C Code 80h
W
V
V
V
V
LSB
LSB
LSB
LSB
Code FFh, V = 5V, see Figure 2-25
DD
Code FFh, V = 3V, see Figure 2-25
DD
Code 00h, V = 5V, see Figure 2-25
DD
Code 00h, V = 3V, see Figure 2-25
DD
WFSE
WFSE
WZSE
WZSE
Zero-Scale Error
0
Resistor Terminals
Voltage Range
Capacitance (CA or CB)
Capacitance
V
0
—
—
—
11
5.6
V
—
—
Note 4
A,B,W
DD
pF
pF
f =1 MHz, Code = 80h, see Figure 2-30
f =1 MHz, Code = 80h, see Figure 2-30
C
W
Dynamic Characteristics (All dynamic characteristics use V = 5V.)
DD
Bandwidth -3dB
BW
—
145
—
—
MHz
µS
V = 0V, Measured at Code 80h,
B
Output Load = 30 PF
= V ,V = 0V, ±1% Error Band, Transition
Settling Time
t
—
18
V
A
S
DD
B
from Code 00h to Code 80h, Output Load = 30 pF
= Open, Code 80h, f =1 kHz
Resistor Noise Voltage
Crosstalk
e
—
—
29
-95
—
—
nV/√Hz
dB
V
A
NWB
C
V = V , V = 0V (Note 5)
A DD B
T
Digital Inputs/Outputs (CS, SCK, SI, SO) See Figure 2-12 for RS and SHDN pin operation.
Schmitt Trigger High-Level Input Voltage
Schmitt Trigger Low-Level Input Voltage
Hysteresis of Schmitt Trigger Inputs
Low-Level Output Voltage
V
V
0.7V
—
—
—
—
0.05V
—
—
0.3V
—
0.40
—
V
V
IH
DD
IL
DD
V
HYS
DD
V
—
V
V
I
I
= 2.1 mA, V = 5V
DD
OL
OL
High-Level Output Voltage
V
V
- 0.5
—
= -400 µA, V = 5V
OH DD
OH
DD
Input Leakage Current
Pin Capacitance (All inputs/outputs)
Power Requirements
I
-1
—
—
10
+1
—
µA
pF
CS = V , V = V or V , includes V SHDN=0
DD IN SS DD A
LI
C
, C
V
= 5.0V, T = +25°C, f = 1 MHz
A c
IN
OUT
DD
Operating Voltage Range
Supply Current, Active
V
2.7
—
—
340
5.5
500
V
µA
DD
I
V
= 5.5V, CS = V , f
= 10 MHz,
DDA
DD
SS SCK
SO = Open, Code FFh (Note 6)
Supply Current, Static
Power Supply Sensitivity
I
—
—
—
0.01
0.0015
0.0015
1
µA
%/%
%/%
CS, SHDN, RS = V = 5.5V, SO = Open (Note 6)
DDS
DD
PSS
PSS
0.0035
0.0035
V
V
= 4.5V - 5.5V, V = 4.5V, Code 80h
A
DD
DD
= 2.7V - 3.3V, V = 2.7V, Code 80h
A
Note 1:
2:
V
= V , no connection on wiper.
AB DD
Rheostat position non-linearity R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum
resistance wiper positions. R-DNL measures the relative step change from the ideal between successive tap positions. I = 50 µA for
W
V
= 3V and I = 400 µA for V = 5V for 10 kΩ version. See Figure 2-26 for test circuit.
W DD
DD
3:
4:
INL and DNL are measured at V with the device configured in the voltage divider or potentiometer mode. V = V and V = 0V. DNL
W A DD B
specification limits of ±1 LSB max are specified monotonic operating conditions. See Figure 2-25 for test circuit.
Resistor terminals A,B and W have no restrictions on polarity with respect to each other. Full-scale and zero-scale error were measured
using Figure 2-25.
5:
6:
Measured at V pin where the voltage on the adjacent V pin is swinging full-scale.
W W
Supply current is independent of current through the potentiometers.
DS11195C-page 4
2003 Microchip Technology Inc.
MCP41XXX/42XXX
Absolute Maximum Ratings †
VDD...................................................................................7.0V
All inputs and outputs w.r.t. VSS ............... -0.6V to VDD +1.0V
Storage temperature.....................................-60°C to +150°C
Ambient temp. with power applied................-60°C to +125°C
ESD protection on all pins..................................................≥ 2 kV
† Notice: Stresses above those listed under “maximum rat-
ings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied. Expo-
sure to maximum rating conditions for extended periods may
affect device reliability.
AC TIMING CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, V = +2.7V to 5.5V, T = -40°C to +85°C.
DD
A
Parameter
Sym
Min.
Typ.
Max.
Units
Conditions
= 5V (Note 1)
Clock Frequency
Clock High Time
Clock Low Time
F
—
40
40
40
40
10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
10
—
—
—
—
—
80
—
—
—
—
—
—
—
—
—
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
DD
CLK
t
HI
t
LO
CS Fall to First Rising CLK Edge
Data Input Setup Time
Data Input Hold Time
SCK Fall to SO Valid Propagation Delay
SCK Rise to CS Rise Hold Time
SCK Rise to CS Fall Delay
CS Rise to CLK Rise Hold
CS High Time
t
CSSR
t
t
t
SU
HD
DO
C = 30 pF (Note 2)
L
t
30
10
100
40
150
150
40
100
150
CHS
t
t
t
CS0
CS1
CSH
Reset Pulse Width
t
Note 2
Note 2
Note 3
Note 3
Note 3
RS
RS Rising to CS Falling Delay Time
CS rising to RS or SHDN falling delay time
CS low time
t
RSCS
t
SE
t
CSL
Shutdown Pulse Width
t
SH
Note 1:
When using the device in the daisy-chain configuration, maximum clock frequency is determined by a combination of propagation delay
time (t ) and data input setup time (t ). Max. clock frequency is therefore ~ 5.8 MHz based on SCK rise and fall times of 5 ns, t
=
HI
DO
SU
40 ns, t = 80 ns and t = 40 ns.
DO
SU
2:
3:
Applies only to the MCP42XXX devices.
Applies only when using hardware pins to exit software shutdown mode, MCP42XXX only.
2003 Microchip Technology Inc.
DS11195C-page 5
MCP41XXX/42XXX
tCSH
CS
1/FCLK
tCSSR
tCHS
tHI
tLO
tCS1
tCSO
SCK
tSU
tHD
SI
msb in
tDO
(First 16 bits out are always zeros)
SO
VOUT
tS
±1% Error Band
±1%
FIGURE 1-1:
Detailed Serial interface Timing.
Wiper position is changed to
Code 80h is latched
on rising edge of RS
mid-scale (80h) if RS is held
low for 150 ns
CS
RS
tRSCS
tRS
tS
±1%
±1% Error Band
VOUT
FIGURE 1-2:
Reset Timing.
tCSL
CS
RS
tSE
tRS
tSE
tSH
SHDN
FIGURE 1-3:
Software Shutdown Exit Timing.
DS11195C-page 6
2003 Microchip Technology Inc.
MCP41XXX/42XXX
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, curve represents 10 kΩ, 50 kΩ and 100 kΩ devices, VDD = 5V, VSS = 0V, TA = +25°C,
VB = 0V.
14
12
10
8
1
0.8
0.6
0.4
0.2
0
VDD = +3V to +5V
RAB
RWB
Code = 80h
6
RWB
RWA
4
2
MCP41010, MCP42010 (10 kΩ potentiometers)
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
0
32
64
96
128 160 192 224 256
Code (Decimal)
FIGURE 2-1:
Normalized Wiper to End
FIGURE 2-4:
Nominal Resistance 10 kΩ
Terminal Resistance vs. Code.
vs. Temperature.
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
70
60
50
40
30
20
10
TA = -40°C to +85°C
Refer to Figure 2-25
RAB
RWB
Code = 80h
MCP41050, MCP42050 (50 kΩpotentiometers)
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
0
32
64
96 128 160 192 224 256
Code (Decimal)
FIGURE 2-2:
Potentiometer INL Error vs.
FIGURE 2-5:
Nominal Resistance 50 kΩ
Code.
vs. Temperature.
70
60
50
40
30
20
10
0
140
120
100
80
TA = -40°C to +85°C
VA = 3V
RAB
RWB
Code = 80h
60
40
20
MCP41100, MCP42100 (100 kΩpotentiometers)
0
-10
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
32
64
96 128 160 192 224 256
Code (Decimal)
FIGURE 2-3:
Potentiometer Mode
FIGURE 2-6:
Nominal Resistance 100 kΩ
Tempco vs. Code.
vs. Temperature.
2003 Microchip Technology Inc.
DS11195C-page 7
MCP41XXX/42XXX
Note: Unless otherwise indicated, curve represents 10 kΩ, 50 kΩ and 100 kΩ devices, VDD = 5V, VSS = 0V, TA = +25°C,
VB = 0V.
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
280
230
180
130
80
Refer to Figure 2-27
VDD = 5V
FCLK = 3 MHz
Code = FFh
TA = +85°C
TA = +25°C
TA = -40°C
VDD = 3V
30
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
0
32
64
96 128 160 192 224 256
Code (Decimal)
FIGURE 2-7:
Rheostat INL Error vs.
FIGURE 2-10:
Active Supply Current vs.
Code.
Temperature.
1000
3000
2500
2000
1500
1000
500
A - VDD = 5.5V, Code = AAh
B - VDD = 3.3V, Code = AAh
C - VDD = 5.5V, Code = FFh
D - VDD = 3.3V, Code = FFh
TA = -40°C to +85°C,
900
800
700
600
500
400
300
200
100
0
V
A = no connect,
R
WB measured
B
C
A
0
0
D
32 64 96 128 160 192 224 256
Code (Decimal)
1k
10k
100k
Clock Frequency (Hz)
1M
10M
FIGURE 2-8:
Rheostat Mode Tempco vs.
FIGURE 2-11:
Active Supply Current vs.
Code.
Clock Frequency.
1
0
1000
100
10
VDD = 5.5V
-1
-2
-3
-4
-5
-6
1
-7
0
-40 -25 -10
5
20 35 50 65 80 95 11 12
0
5
2
4
6
RS & SHDN Pin Voltage (V)
Temperature (°C)
FIGURE 2-9:
Static Current vs.
FIGURE 2-12:
Reset & Shutdown Pins
Temperature.
Current vs. Voltage.
DS11195C-page 8
2003 Microchip Technology Inc.
MCP41XXX/42XXX
Note: Unless otherwise indicated, curve represents 10 kΩ, 50 kΩ and 100 kΩ devices, VDD = 5V, VSS = 0V, TA = +25°C,
VB = 0V.
180
MCP41010,MCP42010
CL = 27 pF
160
140
120
100
80
Code = 00h,
Sample Size = 400
VOUT
FFh
60
40
00h
20
0
CS
47 48 49 50 51 52 53 54 55 56 57 58 59
Wiper Resistance (Ω)
FIGURE 2-13:
10 kΩ Device Wiper
FIGURE 2-16:
Full-Scale Settling Time.
Resistance Histogram.
140
120
100
80
MCP41050, MCP41100,
MCP42050, MCP42100
Code = 00h,
CL = 27 pF
Code = 80h
Sample Size = 796
VOUT
60
40
20
CS
0
115 117 119 121 123 125 127 129 131 133
Wiper Resistance (Ω)
FIGURE 2-17:
Digital Feed through vs.
FIGURE 2-14:
50 kΩ, 100 kΩ Device Wiper
Time.
Resistance Histogram.
6
0
-6
-12
-18
-24
-30
-36
-42
-48
Code = FFh
Code = 80h
Code = 40h
CL = 17 pF
Code = 80h
Code = 20h
Code = 10h
Code = 08h
VOUT
Code = 7Fh
Code = 04h
Code = 02h
Code = 01h
CS
CL = 30pF, Refer to Figure 2-29
MCP41010, MCP42010 (10kΩ potentiometers)
-54
-60
100 1k 10k 100k
1M
10M
Frequency (Hz)
FIGURE 2-18:
Gain vs. Frequency for
FIGURE 2-15:
One Position Settling Time.
10 kΩ Potentiometer.
2003 Microchip Technology Inc.
DS11195C-page 9
MCP41XXX/42XXX
Note: Unless otherwise indicated, curve represents 10 kΩ, 50 kΩ and 100 kΩ devices, VDD = 5V, VSS = 0V, TA = +25°C,
VB = 0V.
6
0
-6
40
Code = FFh
Code = 80h
Code = 40h
Code = 20h
VDD = 4.5V to 5.5V,
Code = 80h,
10 kΩ Potentiometer
35
30
25
20
15
10
5
CL = 27 pF,
VA = 4V
-12
-18
-24
-30
-36
-42
-48
-54
-60
Refer to Figure 2-28
Code = 10h
Code = 08h
Code = 04h
50 kΩ Potentiometer
Code = 02h
100 kΩ Potentiometer
Code = 01h
CL = 30pF, Refer to Figure 2-29
MCP41050, MCP42050 (50kΩ potentiometers)
0
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
FIGURE 2-19:
Gain vs. Frequency for
FIGURE 2-22:
Power Supply Rejection
50kΩ Potentiometer.
Ratio vs. Frequency.
6
0
-6
-12
-18
-24
-30
-36
-42
-48
700
600
500
400
300
200
100
0
Code = FFh
Code = 80h
MCP41010, MCP42010
Iw = 1 mA, Code = 00h,
Refer to Figure 2-27
VDD = 2.7V
Code = 40h
Code = 20h
Code = 10h
Code = 08h
Code = 04h
Code = 02h
VDD = 5V
Code = 01h
CL = 30pF, Refer to Figure 2-29
MCP41100, MCP42100 (100kΩ potentiometers)
-54
-60
0
1
2
3
4
5
100
1k
10k
100k
1M
Terminal B Voltage (V)
Frequency (Hz)
FIGURE 2-20:
Gain vs. Frequency for
FIGURE 2-23:
10 kΩ Wiper Resistance vs.
100kΩ Potentiometer.
Voltage.
0
-6
450
400
350
300
250
200
150
100
50
Code = 00h
Refer to Figure 2-27
1.06 MHz
145 kHz
279 kHz
VDD = 2.7V
-12
-18
-24
10 kΩ
VDD = 5V
50 kΩ
-30
CL = 30 pF, Code = 80h
0
100 kΩ
Refer to Figure 2-29
-36
0
1
2
3
4
5
1k
10k
100k
1M
10M
Terminal B Voltage (V)
Frequency (Hz)
FIGURE 2-21:
-3 dB Bandwidths.
FIGURE 2-24:
50 kΩ & 100 kΩ Wiper
Resistance vs. Voltage.
DS11195C-page 10
2003 Microchip Technology Inc.
MCP41XXX/42XXX
2.1
Parametric Test Circuits
VA
V+ = VDD
1LSB = V+/256
A
VDD
A
V+
V+
W
W
B
B
DUT
+
-
DUT
+
-
VMEAS
*
VMEAS
*
*Assume infinite input impedance
V+ = VDD ± 10%
FIGURE 2-25:
Potentiometer Divider Non-
∆VDD
PSRR (dB) = 20LOG
(
)
Linearity Error Test Circuit (DNL, INL).
∆VMEAS
PSS (%/%) = ∆VDD
∆VMEAS
No Connection
*Assume infinite input impedance
FIGURE 2-28:
Power Supply Sensitivity
A
IW
Test Circuit (PSS, PSRR).
W
B
DUT
+
-
A
VMEAS
*
+5V
W
VIN
VOUT
+
~
-
*Assume infinite input impedance
OFFSET
GND
DUT
B
FIGURE 2-26:
Resistor Position Non-
Linearity Error Test Circuit (Rheostat operation
DNL, INL).
2.5V DC
Rsw = 0.1V
Isw
FIGURE 2-29:
Gain vs. Frequency Test
Circuit.
A
Code = 00h
W
DUT
DUT
B
+
-
ISW
B
A
0.1V
+5V
VSS = 0 to VDD
VOUT
-
+
VIN
~
MCP601
2.5V DC
Offset
FIGURE 2-27:
Wiper Resistance Test
Circuit.
FIGURE 2-30:
Capacitance Test Circuit.
2003 Microchip Technology Inc.
DS11195C-page 11
MCP41XXX/42XXX
3.9
Shutdown (SHDN)
3.0
PIN DESCRIPTIONS
(MCP42XXX devices only)
3.1
PA0, PA1
The Shutdown pin has a Schmitt Trigger input. Pulling
this pin low will put the device in a power-saving mode
where A terminal is opened and the B and W terminals
are connected for all potentiometers. This pin should
not be toggled low when the CS pin is low. In order to
minimize power consumption, this pin has an active
pull-up circuit. The performance of this circuit is shown
in Figure 2-12. This pin will draw negligible current at
logic level ‘0’ and logic level ‘1’. Do not leave this pin
floating.
Potentiometer Terminal A Connection.
3.2
PB0, PB1
Potentiometer Terminal B Connection.
3.3
PW0, PW1
Potentiometer Wiper Connection.
3.4
Chip Select (CS)
TABLE 3-1:
Pin # Name
MCP41XXX Pins
Function
This is the SPI port chip select pin and is used to exe-
cute a new command after it has been loaded into the
shift register. This pin has a Schmitt Trigger input.
1
2
3
4
5
6
7
8
CS Chip Select
SCK Serial Clock
SI Serial Data Input
3.5
Serial Clock (SCK)
This is the SPI port clock pin and is used to clock-in
new register data. Data is clocked into the SI pin on the
rising edge of the clock and out the SO pin on the falling
edge of the clock. This pin is gated to the CS pin (i.e.,
the device will not draw any more current if the SCK pin
is toggling when the CS pin is high). This pin has a
Schmitt Trigger input.
VSS Ground
PA0 Terminal A Connection For Pot 0
PW0 Wiper Connection For Pot 0
PB0 Terminal B Connection For Pot 0
VDD Power
3.6
Serial Data Input (SI)
TABLE 3-2:
Pin # Name
MCP42XXX Pins
Function
This is the SPI port serial data input pin. The command
and data bytes are clocked into the shift register using
this pin. This pin is gated to the CS pin (i.e., the device
will not draw any more current if the SI pin is toggling
when the CS pin is high). This pin has a Schmitt Trigger
input.
1
2
CS Chip Select
SCK Serial Clock
SI Serial Data Input
3
4
VSS Ground
3.7
Serial Data Output (SO)
5
PB1 Terminal B Connection For Pot 1
PW1 Wiper Connection For Pot 1
PA1 Terminal A Connection For Pot 1
PA0 Terminal A Connection For Pot 0
PW0 Wiper Connection For Pot 0
PB0 Terminal B Connection For Pot 0
RS Reset Input
(MCP42XXX devices only)
6
This is the SPI port serial data output pin used for
daisy-chaining more than one device. Data is clocked
out of the SO pin on the falling edge of clock. This is a
push-pull output and does not go to a high-impedance
state when CS is high. It will drive a logic-low when CS
is high.
7
8
9
10
11
12
13
14
3.8
Reset (RS)
SHDN Shutdown Input
(MCP42XXX devices only)
SO Data Out for Daisy-Chaining
VDD Power
The Reset pin will set all potentiometers to mid-scale
(Code 80h) if this pin is brought low for at least 150 ns.
This pin should not be toggled low when the CS pin is
low. It is possible to toggle this pin when the SHDN pin
is low. In order to minimize power consumption, this pin
has an active pull-up circuit. The performance of this
circuit is shown in Figure 2-12. This pin will draw negli-
gible current at logic level ‘0’ and logic level ‘1’. Do not
leave this pin floating.
DS11195C-page 12
2003 Microchip Technology Inc.
MCP41XXX/42XXX
4.0
APPLICATIONS INFORMATION
The MCP41XXX/42XXX devices are 256 position
single and dual digital potentiometers that can be used
in place of standard mechanical pots. Resistance val-
ues of 10 kΩ, 50 kΩ and 100 kΩ are available. As
shown in Figure 4-1, each potentiometer is made up of
a variable resistor and an 8-bit (256 position) data reg-
ister that determines the wiper position. There is a
nominal wiper resistance of 52Ω for the 10 kΩ version,
125Ω for the 50 kΩ and 100 kΩ versions. For the dual
devices, the channel-to-channel matching variation is
less than 1%. The resistance between the wiper and
either of the resistor endpoints varies linearly according
to the value stored in the data register. Code 00h
effectively connects the wiper to the B terminal. At
power-up, all data registers will automatically be loaded
with the mid-scale value (80h). The serial interface pro-
vides the means for loading data into the shift register,
which is then transferred to the data registers. The
serial interface also provides the means to place indi-
vidual potentiometers in the shutdown mode for maxi-
mum power savings. The SHDN pin can also be used
to put all potentiometers in shutdown mode and the RS
pin is provided to set all potentiometers to mid-scale
(80h).
PW0
PW1
PA0
PB0 PA1
PB1
D0
RDAC2
RDAC1
Data Register 0
D7
Data Register 1
D7
D0
RS
CS
Decode
Logic
D7
D0
16-bit Shift Register
SCK
SI
SO
SHDN
FIGURE 4-1:
Block diagram showing the MCP42XXX dual digital potentiometer. Data register 0 and
data register 1 are 8-bit registers allowing 256 positions for each wiper. Standard SPI pins are used with
the addition of the Shutdown (SHDN) and Reset (RS) pins. As shown, reset affects the data register and
wipers, bringing them to mid-scale. Shutdown disconnects the A terminal and connects the wiper to B,
without changing the state of the data registers.
When laying out the circuit for your digital potentiome-
VDD
ter, bypass capacitors should be used. These capaci-
tors should be placed as close as possible to the device
pin. A bypass capacitor value of 0.1 µF is recom-
mended. Digital and analog traces should be separated
as much as possible on the board, with no traces run-
ning underneath the device or the bypass capacitor.
Extra precautions should be taken to keep traces with
high-frequency signals (such as clock lines) as far as
possible from analog traces. Use of an analog ground
plane is recommended in order to keep the ground
potential the same for all devices on the board.
VDD
0.1 uF
0.1 uF
B
W
A
µC
Data Lines
To Application
Circuit
2003 Microchip Technology Inc.
DS11195C-page 13
MCP41XXX/42XXX
4.1.2
POTENTIOMETER MODE
4.1
Modes of Operation
In the potentiometer mode, all three terminals of the
device are tied to different nodes in the circuit. This
allows the potentiometer to output a voltage propor-
tional to the input voltage. This mode is sometimes
called voltage divider mode. The potentiometer is used
to provide a variable voltage by adjusting the wiper
position between the two endpoints as shown in
Figure 4-3. Note that reversing the polarity of the A and
B terminals will not affect operation.
Digital potentiometer applications can be divided into
two categories: rheostat mode and potentiometer, or
voltage divider, mode.
4.1.1
RHEOSTAT MODE
In the rheostat mode, the potentiometer is used as a
two-terminal resistive element. The unused terminal
should be tied to the wiper, as shown in Figure 4-2.
Note that reversing the polarity of the A and B terminals
will not affect operation.
V1
A
A
V2
W
W
B
B
MCP4XXXX
MCP4XXXX
Resistor
FIGURE 4-3:
Three terminal or voltage
divider mode.
FIGURE 4-2: Two-terminal or rheostat
In this configuration, the ratio of the internal resistance
defines the temperature coefficient of the device. The
resistor matching of the RWB resistor to the RAB resistor
performs with a typical temperature coefficient of
1 ppm/°C (measured at code 80h). At lower codes, the
wiper resistance temperature coefficient will dominate.
Figure 2-3 shows the effect of the wiper. Above the
lower codes, this figure shows that 70% of the states
will typically have a temperature coefficient of less than
5 ppm/°C. 30% of the states will typically have a
ppm/°C of less than 1.
configuration for the digital potentiometer. Acting
as a resistive element in the circuit, resistance is
controlled by changing the wiper setting.
Using the device in this mode allows control of the total
resistance between the two nodes. The total measured
resistance would be the least at code 00h, where the
wiper is tied to the B terminal. The resistance at this
code is equal to the wiper resistance, typically 52Ω for
the 10 kΩ MCP4X010 devices, 125Ω for the 50 kΩ
(MCP4X050), and 100 kΩ (MCP4X100) devices. For
the 10 kΩ device, the LSB size would be 39.0625Ω
(assuming 10 kΩ total resistance). The resistance
would then increase with this LSB size until the total
measured resistance at code FFh would be 9985.94Ω.
The wiper will never directly connect to the A terminal
of the resistor stack.
In the 00h state, the total resistance is the wiper resis-
tance. To avoid damage to the internal wiper circuitry in
this configuration, care should be taken to ensure the
current flow never exceeds 1 mA.
For dual devices, the variation of channel-to-channel
matching of the total resistance from A to B is less than
1%. The device-to-device matching, however, can vary
up to 30%. In the rheostat mode, the resistance has a
positive temperature coefficient. The change in wiper-
to-end terminal resistance over temperature is shown
in Figure 2-8. The most variation over temperature will
occur in the first 6% of codes (code 00h to 0Fh) due to
the wiper resistance coefficient affecting the total resis-
tance. The remaining codes are dominated by the total
resistance tempco RAB, typically 800 ppm/°C.
DS11195C-page 14
2003 Microchip Technology Inc.
MCP41XXX/42XXX
In order for these circuits to work properly, care must be
taken in a few areas. For linear operation, the analog
input and output signals must be in the range of VSS to
VDD for the potentiometer and input and output rails of
the op-amp. The circuit in Figure 4-4 requires a virtual
ground or reference input to the non-inverting input of
the amplifier. Refer to Application Note 682, “Using
Single-Supply Operational Amplifiers in Embedded
Systems” (DS00682), for more details. At power-up or
reset (RS), the resistance is set to mid-scale, with RA
and RB matching. Based on the transfer function for the
circuit, the gain is -1 V/V. As the code is increased and
the wiper moves towards the A terminal, the gain
increases. Conversely, when the wiper is moved
towards the B terminal, the gain decreases. Figure 4-6
shows this relationship. Notice the pseudo-logarithmic
gain around decimal code 128. As the wiper
approaches either terminal, the step size in the gain
calculation increases dramatically. Due to the
mismatched ratio of RA and RB at the extreme high and
low codes, small increments in wiper position can
dramatically affect the gain. As shown in Figure 4-3,
recommended gains lie between 0.1 and 10 V/V.
4.2
Typical Applications
4.2.1
PROGRAMMABLE SINGLE-ENDED
AMPLIFIERS
Potentiometers are often used to adjust system refer-
ence levels or gain. Programmable gain circuits using
digital potentiometers can be realized in a number of
different ways. An example of a single-supply, inverting
gain amplifier is shown in Figure 4-4. Due to the high
input impedance of the amplifier, the wiper resistance
is not included in the transfer function. For a single-sup-
ply, non-inverting gain configuration, the circuit in
Figure 4-5 can be used.
.
MCP41010
B
A
W
VIN
VDD
-
-IN
VOUT
MCP606
+IN
+
VREF
VSS
10
RB
RA
RB
-------
RA
VOUT = –VIN
+ VREF 1 + -------
Where:
1
R
AB(256 – Dn)
RABDn
256
RA = -------------------------------------- RB = ------------------
256
RAB = Total Resistance of pot
Dn = Wiper setting forDn = 0 to 255
0.1
0
64
128
192
256
Decimal code (0-255)
FIGURE 4-4:
Single-supply,
programmable, inverting gain amplifier using a
digital potentiometer.
FIGURE 4-6:
Gain vs. Code for inverting
and differential amplifier circuits.
VDD
4.2.2
PROGRAMMABLE DIFFERENTIAL
AMPLIFIER
+
VIN
+IN
-IN
W
VOUT
MCP606
An example of a differential input amplifier using digital
potentiometers is shown in Figure 4-7. For the transfer
function to hold, both pots must be programmed to the
same code. The resistor-matching from channel-to-
channel within a dual device can be used as an advan-
tage in this circuit. This circuit will also show stable
operation over temperature due to the low potentiome-
ter temperature coefficient. Figure 4-6 also shows the
relationship between gain and code for this circuit. As
the wiper approaches either terminal, the step size in
the gain calculation increases dramatically. This circuit
is recommended for gains between 0.1 and 10 V/V.
-
VSS
RA
RB
MCP41010
RB
VOUT = VIN 1 + -------
RA
Where:
R
AB(256 – Dn)
RABDn
RA = -------------------------------------- RB = ------------------
256
256
RAB = Total Resistance of pot
Dn = Wiper setting forDn = 0 to 255
FIGURE 4-5:
Single-supply,
programmable, non-inverting gain amplifier.
2003 Microchip Technology Inc.
DS11195C-page 15
MCP41XXX/42XXX
4.3
Calculating Resistances
1/2
When programming the digital potentiometer settings,
the following equations can be used to calculate the
resistances. Programming code 00h effectively brings
the wiper to the B terminal, leaving only the wiper resis-
tance. Programming higher codes will bring the wiper
closer to the A terminal of the potentiometer. The equa-
tions in Figure 4-9 can be used to calculate the terminal
resistances. Figure 4-10 shows an example calculation
using a 10 kΩ potentiometer.
MCP42010
VB
A
B
VDD
(SIG -)
+
-IN
VA
VOUT
MCP601
A
B
(SIG +)
+IN
-
VSS
RB
RA
PA
PW
VOUT = (VA – VB)-------
VREF
Where:
PB
R
AB(256 – Dn)
RABDn
256
RA = -------------------------------------- RB = ------------------
256
(RAB)(256 – Dn)
R
R
WA(Dn) = ------------------------------------------- + RW
RAB = Total Resistance of pot
Dn = Wiper setting forDn = 0 to 255
256
(RAB)(Dn)
WB(Dn) = --------------------------- + RW
256
NOTE: Potentiometer values must be equal
Where:
FIGURE 4-7:
Single Supply
programmable differential amplifier using digital
potentiometers.
PA is the A terminal
PB is the B terminal
PW is the wiper terminal
R
R
R
R
D
is resistance between Terminal A and wiper
is resistance between Terminal B and Wiper
is overall resistance for pot (10 kΩ, 50 kΩ or 100 kΩ)
WA
WB
AB
W
n
4.2.3
PROGRAMMABLE OFFSET TRIM
is wiper resistance
is 8-bit value in data register for pot number n
For applications requiring only a programmable voltage
reference, the circuit in Figure 4-8 can be used. This
circuit shows the device used in the potentiometer
mode along with two resistors and a buffered output.
This creates a circuit with a linear relationship between
voltage-out and programmed code. Resistors R1 and
R2 can be used to increase or decrease the output volt-
age step size. The potentiometer in this mode is stable
over temperature. The operation of this circuit over
temperature is shown in Figure 2-3. The worst perfor-
mance over temperature will occur at the lower codes
due to the dominating wiper resistance. R1 and R2 can
also be used to affect the boundary voltages, thereby
eliminating the use of these lower codes.
FIGURE 4-9:
Potentiometer resistances
are a function of code. It should be noted that,
when using these equations for most feedback
amplifier circuits (see Figure 4-4 and Figure 4-5),
the wiper resistance can be omitted due to the
high impedance input of the amplifier.
Example:
PA
R = 10 kΩ
Code = C0h = 192d
PW
10 kΩ
PB
(RAB)(256 – Dn)
R
WA(Dn) = ------------------------------------------- + RW
VDD
256
VDD
(10kΩ)(256 – 192)
R1
R
R
WA(C0h) = -------------------------------------------------- + 52Ω
256
-
-IN
WA(C0h) = 2552Ω
MCP606
+
A
B
OUT
+IN
(RAB)(Dn)
R
WB(Dn) = --------------------------- + RW
VSS
256
0.1 uF
(10kΩ)(192)
R
R
WB(C0h) = ---------------------------------- + 52Ω
R2
256
VSS
WB(C0h) = 7552Ω
FIGURE 4-8:
By changing the values of
Note: All values shown are typical and
actual results will vary.
R and R , the voltage output resolution of this
1
2
programmable voltage reference circuit is
affected.
FIGURE 4-10:
calculations.
Example Resistance
DS11195C-page 16
2003 Microchip Technology Inc.
MCP41XXX/42XXX
5.3
Using The Shutdown Command
5.0
SERIAL INTERFACE
Communications from the controller to the
MCP41XXX/42XXX digital potentiometers is accom-
plished using the SPI serial interface. This interface
allows three commands:
The shutdown command allows the user to put the
application circuit into a power-saving mode. In this
mode, the A terminal is open-circuited and the B and W
terminals are shorted together. The command select
bits C1, C0 are set to 1,0. The potentiometer selection
bits P1 and P0 allow each potentiometer to be shut-
down independently. If either P1 or P0 are high, the
respective potentiometer will enter shutdown mode. A
‘0’ for P1 or P0 will have no effect. The eight data bits
following the command byte still need to be transmitted
for the shutdown command, but they are ‘don’t care’
bits. See Figure 5-2 for command format summary.
Once a particular potentiometer has entered the shut-
down mode, it will remain in this mode until:
• A new value is written to the potentiometer data
register, provided that the SHDN pin is high. The
device will remain in the shutdown mode until the
rising edge of the CS is detected, at which time
the device will come out of shutdown mode and
the new value will be written to the data regis-
ter(s). If the SHDN pin is low when the new value
is received, the registers will still be set to the new
value, but the device will remain in shutdown
mode. This scenario assumes that a valid com-
mand was received. If an invalid command was
received, the command will be ignored and the
device will remain in the shutdown mode.
It is also possible to use the hardware shutdown pin
and reset pin to remove a device from software shut-
down. To do this, a low pulse on the chip select line
must first be sent. For multiple devices, sharing a single
SHDN or RESET line allows you to pick an individual
device on that chain to remove from software shutdown
mode. See Figure 1-3 for timing. With a preceding chip
select pulse, either of these situations will also remove
a device from software shutdown:
• A falling edge is seen on the RS pin and held low
for at least 150 ns, provided that the SHDN pin is
high. If the SHDN pin is low, the registers will still
be set to mid-scale, but the device will remain in
shutdown mode. This condition assumes that CS
is high, as bringing the RS pin low while CS is low
is an invalid state and results are indeterminate.
1. Write a new value to the potentiometer data
register(s).
2. Cause a channel to enter low power shutdown
mode.
3. NOP (No Operation) command.
Executing any command is accomplished by setting
CS low and then clocking-in a command byte followed
by a data byte into the 16-bit shift register. The com-
mand is executed when CS is raised. Data is clocked-
in on the rising edge of clock and out the SO pin on the
falling edge of the clock (see Figure 5-1). The device
will track the number of clocks (rising edges) while CS
is low and will abort all commands if the number of
clocks is not a multiple of 16.
5.1
Command Byte
The first byte sent is always the command byte, fol-
lowed by the data byte. The command byte contains
two command select bits and two potentiometer select
bits. Unused bits are ‘don’t care’ bits. The command
select bits are summarized in Figure 5-2. The com-
mand select bits C1 and C0 (bits 4:5) of the command
byte determine which command will be executed. If the
command bits are both 0’s or 1’s, then a NOP com-
mand will be executed once all 16 bits have been
loaded. This command is useful when using the daisy-
chain configuration. When the command bits are 0,1, a
write command will be executed with the 8 bits sent in
the data byte. The data will be written to the potentiom-
eter(s) determined by the potentiometer select bits. If
the command bits are 1,0, then a shutdown command
will be executed on the potentiometers determined by
the potentiometer select bits.
For the MCP42XXX devices, the potentiometer select
bits P1 and P0 (bits 0:1) determine which potentiome-
ters are to be acted upon by the command. A corre-
sponding ‘1’ in the position signifies that the command
for that potentiometer will get executed, while a ‘0’ sig-
nifies that the command will not effect that
potentiometer (see Figure 5-2).
• A rising edge on the SHDN pin is seen after being
low for at least 100 ns, provided that the CS pin is
high. Toggling the SHDN pin low while CS is low
is an invalid state and results are indeterminate.
5.2
Writing Data Into Data Registers
When new data is written into one or more of the poten-
tiometer data registers, the write command is followed
by the data byte for the new value. The command
select bits C1, C0 are set to 0,1. The potentiometer
selection bits P1 and P0 allow new values to be written
to potentiometer 0, potentiometer 1 (or both) with a sin-
gle command. A ‘1’ for either P1 or P0 will cause the
data to be written to the respective data register and a
‘0’ for P1 or P0 will cause no change. See Figure 5-2
for the command format summary.
• The device is powered-down and back up.
Note:
The hardware SHDN pin will always put
the device in shutdown regardless of
whether a potentiometer has already been
put in the shutdown mode using the
software command.
2003 Microchip Technology Inc.
DS11195C-page 17
MCP41XXX/42XXX
Data is always latched
Data is always clocked out
of the SO pin after the
falling edge of SCK.
in on the rising edge
of SCK.
Data Registers are
loaded on rising
CS†
edge of CS. Shift
register is loaded
with zeros at this time.
1
2
3
4
5
6
7
8
9
10
11 12 13 14 15 16
SCK
COMMAND Byte
Data Byte
Don’t
Don’t
Channel
Select
Bits
Care
Bits
Command Care
New Register Data
Bits
Bits
X
X
X
C0
X
P1*
P0
D7 D6 D5 D4 D3 D2 D1 D0
C1
SI
SO pin will always
drive low when CS
goes high.
First 16 bits shifted out will always be zeros
X
SO‡
† There must always be multiples of 16 clocks while CS is low or commands will abort.
‡ The serial data out pin (SO) is only available on the MCP42XXX device.
* P1 is a ‘don’t care’ bit for the MCP41XXX.
FIGURE 5-1:
Timing Diagram for Writing Instructions or Data to a Digital Potentiometer.
COMMAND BYTE
X
X C1 C0 X X P1* P0
Potentiometer
Selection
Bits
Command
Selection
Bits
C1 C0 Command
Command Summary
P1* P0
Potentiometer Selections
0
0
0
1
None
No Command will be executed.
0
0
1
1
0
1
0
1
Dummy Code: Neither Potentiometer
affected.
Command executed on
Potentiometer 0.
Command executed on
Potentiometer 1.
Command executed on both
Potentiometers.
Write Data Write the data contained in Data Byte to the
potentiometer(s) determined by the potenti-
ometer selection bits.
1
1
0
1
Shutdown
Potentiometer(s) determined by potentiome-
ter selection bits will enter Shutdown Mode.
Data bits for this command are ‘don’t cares’.
None
No Command will be executed.
FIGURE 5-2:
Command Byte Format.
DS11195C-page 18
2003 Microchip Technology Inc.
MCP41XXX/42XXX
When using the daisy-chain configuration, keep in mind
that the shift register of each device is automatically
loaded with zeros whenever a command is executed
(CS = high). Because of this, the first 16 bits that come
out of the SO pin once the CS line goes low will always
be zeros. This means that when the first command is
being loaded into a device, it will always shift a NOP
command into the next device on the chain because
the command bits (and all the other bits) will be zeros.
This feature makes it necessary only to send command
and data bytes to the device farthest down the chain
that needs a new command. For example, if there were
three devices on the chain and it was desired to send a
command to the device in the middle, only 32 bytes of
data need to be transmitted. The last device on the
chain will have a NOP loaded from the previous device
so no registers will be affected when the CS pin is
raised to execute the command. The user must
always ensure that multiples of 16 clocks are
always provided (while CS is low), as all commands
will abort if the number of clocks provided is not a
multiple of 16.
5.4
Daisy-Chain Configuration
Multiple MCP42XXX devices can be connected in a
daisy-chain configuration, as shown in Figure 5-4, by
connecting the SO pin from one device to the SI pin on
the next device. The data on the SO pin is the output of
the 16-bit shift register. The daisy-chain configuration
allows the system designer to communicate with sev-
eral devices without using a separate CS line for each
device. The example shows a daisy-chain configura-
tion with three devices, although any number of
devices (with or without the same resistor values) can
be configured this way. While it is not possible to use a
MCP41XXX at the beginning or middle of a daisy-chain
(because it does not provide the serial data out (SO)
pin), it is possible to use the device at the end of a
chain. As shown in the timing diagram in Figure 5-3,
data will be clocked-out of the SO pin on the falling
edge of the clock. The SO pin has a CMOS push-pull
output and will drive low when CS goes high. SO will
not go to a high-impedance state when CS is held high.
When using the daisy-chain configuration, the maxi-
mum clock speed possible is reduced to ~5.8 MHz,
because of the propagation delay of the data coming
out of the SO pin.
Data Registers for all
devices are loaded
on Rising Edge of CS
CS
1 2 3 4 5 6 7 8 9 10111213141516
1 2 3 4 5 6 7 8 9 10111213141516 1 2 3 4 5 6 7 8 9 10111213141516
SCK
Command Byte
for Device 3
Data Byte
Command Byte
for Device 2
Data Byte
Command Byte
for Device 1
Data Byte
for Device 3
for Device 2
for Device 1
X X C C X X P P D D D D D D D D
X X C C X X P P D D D D D D D D
X X C C X X P P D D D D D D D D
SI
Command and Data for Device 3
Command and Data for Device 2
start shifting out after the first 16 clocks
start shifting out after the first 32 clocks
First 16 bits shifted out
will always be zeros
SO
X X C C X X P P D D D D D D D D
X X C C X X P P D D D D D D D D
†
There must always be multiples of 16 clocks while CS is low or commands will abort.
The serial data out pin (SO) is only available on the MCP42XXX device.
‡
FIGURE 5-3:
Timing Diagram for Daisy-Chain Configuration.
2003 Microchip Technology Inc.
DS11195C-page 19
MCP41XXX/42XXX
CS
SCK
SO
Microcontroller
CS
SCK
SI
CS
SCK
SI
SO
CS
SCK
SI
Device 1
SO
EXAMPLE:
Device 2
If you want to load the following
command/data into each part
in the chain.
Device 3*
Device 1
Device 2
XX10XX11 11001100
Device 3
XX01XX10 11110000
XX10XX00 10101010
After 16 clocks, Device 2 and
Device 3 will both have all
zeros clocked in from the
previous part’s shift register.
c
Start by setting CS low and
clocking in the command and
data that will end up in Device
3 (16 clocks).
Device 1
Device 2
XX10XX00 10101010
Device 3
00000000 00000000
00000000 00000000
After 32 clocks, Device 2 has
the data previously loaded
into Device 1 and Device 3
gets 16 more zeros.
d
Clock-In the command and
data for Device 2 (16 more
clocks). The data that was pre-
viously loaded gets shifted to
the next device on the chain.
Device 1
Device 2
XX01XX10 11110000
Device 3
XX10XX00 10101010
00000000 00000000
e
After 48 clocks, all 3 devices
have the proper command/
data loaded into their shift
registers.
Clock-In the data for Device 1
(16 more clocks). The data that
was previously loaded into
Device 1 gets shifted into
Device 2 and Device 3 contains
the first byte loaded. Raise the
CS line to execute the com-
mands for all 3 devices at the
same time.
Device 1
Device 2
XX10XX11 11001100
Device 3
XX01XX10 11110000
XX10XX00 10101010
* Last device on a daisy-chain may be a single channel MCP41XXX device.
FIGURE 5-4:
Daisy-Chain Configuration.
DS11195C-page 20
2003 Microchip Technology Inc.
MCP41XXX/42XXX
5.5
Reset (RS) Pin Operation
TABLE 5-1:
TRUTH TABLE FOR LOGIC
INPUTS
The Reset pin (RS) will automatically set all potentiom-
eter data latches to mid-scale (Code 80h) when pulled
low (provided that the pin is held low at least 150 ns
and CS is high). The reset will execute regardless of
the position of the SCK, SHDN and SI pins. It is possi-
ble to toggle RS low and back high while SHDN is low.
In this case, the potentiometer registers will reset to
mid-scale, but the potentiometer will remain in
shutdown mode until the SHDN pin is raised.
SCK CS RS SHDN
Action
X
Ø
H
H
Communication is initiated with
device. Device comes out of
standby mode.
L
L
H
H
No action. Device is waiting for
data to be clocked into shift
register or CS to go high to
execute command.
¦
L
L
H
H
X
X
Shift one bit into shift register.
The shift register can be loaded
while the SHDN pin is low.
Shift one bit out of shift register
on the SO pin. The SO pin is
active while the SHDN pin is
low.
Note:
Bringing the RS pin low while the CS pin is
low constitutes an invalid operating state
and will result in indeterminate results
when RS and/or CS are brought high.
Ø
5.6
Shutdown (SHDN) Pin Operation
When held low, the shutdown pin causes the applica-
tion circuit to go into a power-saving mode by open-cir-
cuiting the A terminal and shorting the B and W
terminals for all potentiometers. Data register contents
are not affected by entering shutdown mode (i.e., when
the SHDN pin is raised, the data register contents are
the same as before the shutdown mode was entered).
X
¦
H
H
Based on command bits, either
load data from shift register into
data latches or execute shut-
down command. Neither com-
mand executed unless
multiples of 16 clocks have
been entered while CS is low.
SO pin goes to a logic low.
While in shutdown mode, it is still possible to clock in
new values for the data registers, as well as toggling
the RS pin to cause all data registers to go to mid-scale.
The new values will take affect when the SHDN pin is
raised.
If the device is powered-up with the SHDN pin held low,
it will power-up in the shutdown mode with the data reg-
isters set to mid-scale.
X
X
H
H
H
Ø
H
H
Static Operation.
All data registers set and
latched to code 80h.
X
X
X
H
H
H
Ø
H
H
L
Ø
¦
All data registers set and
latched to code 80h. Device is
in hardware shutdown mode
and will remain in this mode.
All potentiometers put into
hardware shutdown mode;
terminal A is open and W is
shorted to B.
Note:
Bringing the SHDN pin low while the CS
pin is low constitutes an invalid operating
state and will result in indeterminate
results when SHDN and/or CS are brought
high.
All potentiometers exit hard-
ware shutdown mode. Potenti-
ometers will also exit software
shutdown mode if this rising
edge occurs after a low pulse
on CS. Contents of data
5.7
Power-up Considerations
latches are restored.
When the device is powered on, the data registers will
be set to mid-scale (80h). A power-on reset circuit is
utilized to ensure that the device powers up in this
known state.
2003 Microchip Technology Inc.
DS11195C-page 21
MCP41XXX/42XXX
5.8
Using the MCP41XXX/42XXX in
SPI Mode 1,1
It is possible to operate the devices in SPI modes 0,0
and 1,1. The only difference between these two modes
is that, when using mode 1,1, the clock idles in the high
state, while in mode 0,0, the clock idles in the low state.
In both modes, data is clocked into the devices on the
rising edge of SCK and data is clocked out the SO pin
once the falling edge of SCK. Operations using mode
0,0 are shown in Figure 5-1. The example in
Figure 5-5 shows mode 1,1.
Data is always latched in
on the rising edge of SCK.
Data is always clocked out the SO
pin after the falling edge of SCK.
Data Registers are
loaded on rising
CS†
edge of CS. Shift
register is loaded
with zeros at this time.
1
2
3
4
5
6
7
8
9
10
11 12 13 14 15 16
SCK
COMMAND BYTE
DATA BYTE
Don’t
Don’t
Care
Bits
Channel
Select
Bits
Care
Bits
Command
Bits
New Register Data
X
X
P1*
P0
X
C0
X
D7 D6 D5 D4 D3 D2 D1 D0
C1
SI
SO pin will always
drive low when CS
goes high.
First 16 bits Shifted out will always be zeros
X
SO‡
†
There must always be multiples of 16 clocks while CS is low or commands will abort.
The serial data out pin (SO) is only available on the MCP42XXX device.
‡
FIGURE 5-5:
Timing Diagram for SPI Mode 1,1 Operation.
DS11195C-page 22
2003 Microchip Technology Inc.
MCP41XXX/42XXX
6.0
6.1
PACKAGING INFORMATION
Package Marking Information
8-Lead PDIP (300 mil)
Example:
XXXXXXXX
XXXXXNNN
MCP41010
I/P256
YYWW
0313
8-Lead SOIC (150 mil)
Example:
XXXXXXXX
XXXXYYWW
MCP41050
I/SN0313
NNN
256
14-Lead PDIP (300 mil)
Example:
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
MCP42010
I/P
YYWWNNN
0313256
14-Lead SOIC (150 mil)
Example:
42050ISL
XXXXXXXXXXX
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
0313256
14-Lead TSSOP (4.4mm) *
Example:
XXXXXXXX
YYWW
42100I
0313
256
NNN
Legend: XX...X Customer specific information*
YY
Year code (last 2 digits of calendar year)
WW
NNN
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
*
Standard marking consists of Microchip part number, year code, week code, facility code, mask rev#,
and assembly code.
2003 Microchip Technology Inc.
DS11195C-page 23
MCP41XXX/42XXX
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
A1
β
B1
B
p
eB
Units
Dimension Limits
INCHES*
NOM
MILLIMETERS
MIN
MAX
MIN
NOM
8
MAX
n
p
A
A2
A1
E
E1
D
L
c
B1
B
eB
α
β
Number of Pins
Pitch
8
.100
.155
.130
2.54
3.94
3.30
Top to Seating Plane
.140
.170
.145
3.56
2.92
4.32
3.68
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
Tip to Seating Plane
Lead Thickness
.115
.015
.300
.240
.360
.125
.008
.045
.014
.310
5
0.38
7.62
6.10
9.14
3.18
0.20
1.14
0.36
7.87
5
.313
.250
.373
.130
.012
.058
.018
.370
10
.325
.260
.385
.135
.015
.070
.022
.430
15
7.94
6.35
9.46
3.30
0.29
1.46
0.46
9.40
10
8.26
6.60
9.78
3.43
0.38
1.78
0.56
10.92
15
Upper Lead Width
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
DS11195C-page 24
2003 Microchip Technology Inc.
MCP41XXX/42XXX
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
E
E1
p
D
2
B
n
1
h
α
45°
c
A2
A
φ
β
L
A1
Units
Dimension Limits
INCHES*
NOM
MILLIMETERS
MIN
MAX
MIN
NOM
MAX
n
p
A
A2
A1
E
E1
D
h
L
φ
Number of Pins
Pitch
8
8
.050
.061
.056
.007
.237
.154
.193
.015
.025
4
1.27
1.55
1.42
0.18
6.02
3.91
4.90
0.38
0.62
4
Overall Height
.053
.069
1.35
1.75
Molded Package Thickness
.052
.004
.228
.146
.189
.010
.019
0
.061
.010
.244
.157
.197
.020
.030
8
1.32
0.10
5.79
3.71
4.80
0.25
0.48
0
1.55
0.25
6.20
3.99
5.00
0.51
0.76
8
Standoff
§
Overall Width
Molded Package Width
Overall Length
Chamfer Distance
Foot Length
Foot Angle
Lead Thickness
Lead Width
c
.008
.013
0
.009
.017
12
.010
.020
15
0.20
0.33
0
0.23
0.42
12
0.25
0.51
15
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
0
12
15
0
12
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
2003 Microchip Technology Inc.
DS11195C-page 25
MCP41XXX/42XXX
14-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
A1
B1
β
eB
p
B
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
14
MAX
n
p
A
A2
A1
E
E1
D
L
c
B1
B
Number of Pins
Pitch
14
.100
.155
.130
2.54
3.94
3.30
Top to Seating Plane
.140
.170
.145
3.56
2.92
0.38
7.62
6.10
18.80
3.18
0.20
1.14
0.36
7.87
5
4.32
3.68
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
.115
.015
.300
.240
.740
.125
.008
.045
.014
.310
5
.313
.250
.750
.130
.012
.058
.018
.370
10
.325
.260
.760
.135
.015
.070
.022
.430
15
7.94
6.35
19.05
3.30
0.29
1.46
0.46
9.40
10
8.26
6.60
19.30
3.43
0.38
1.78
0.56
10.92
15
Tip to Seating Plane
Lead Thickness
Upper Lead Width
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-005
DS11195C-page 26
2003 Microchip Technology Inc.
MCP41XXX/42XXX
14-Lead Plastic Small Outline (SL) – Narrow, 150 mil (SOIC)
E
E1
p
D
2
B
n
1
α
h
45°
c
A2
A
φ
A1
L
β
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
MAX
n
p
A
A2
A1
E
E1
D
Number of Pins
Pitch
14
14
.050
.061
.056
.007
.236
.154
.342
.015
.033
4
1.27
1.55
1.42
0.18
5.99
3.90
8.69
0.38
0.84
4
Overall Height
.053
.069
1.35
1.75
Molded Package Thickness
.052
.004
.228
.150
.337
.010
.016
0
.061
.010
.244
.157
.347
.020
.050
8
1.32
0.10
5.79
3.81
8.56
0.25
0.41
0
1.55
0.25
6.20
3.99
8.81
0.51
1.27
8
Standoff
§
Overall Width
Molded Package Width
Overall Length
Chamfer Distance
Foot Length
Foot Angle
Lead Thickness
Lead Width
h
L
φ
c
B
α
.008
.014
0
.009
.017
12
.010
.020
15
0.20
0.36
0
0.23
0.42
12
0.25
0.51
15
Mold Draft Angle Top
Mold Draft Angle Bottom
β
0
12
15
0
12
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-065
2003 Microchip Technology Inc.
DS11195C-page 27
MCP41XXX/42XXX
14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
E
E1
p
D
2
1
n
B
α
A
c
φ
A1
A2
β
L
Units
INCHES
NOM
MILLIMETERS*
Dimension Limits
MIN
MAX
MIN
NOM
14
MAX
n
p
A
Number of Pins
Pitch
14
.026
0.65
Overall Height
.043
1.10
0.95
0.15
6.50
4.50
5.10
0.70
8
Molded Package Thickness
A2
A1
E
E1
D
L
φ
c
.033
.002
.246
.169
.193
.020
0
.035
.004
.251
.173
.197
.024
4
.037
.006
.256
.177
.201
.028
8
0.85
0.05
6.25
4.30
4.90
0.50
0
0.90
0.10
6.38
4.40
5.00
0.60
4
Standoff
§
Overall Width
Molded Package Width
Molded Package Length
Foot Length
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
.004
.007
0
.006
.010
5
.008
.012
10
0.09
0.19
0
0.15
0.25
5
0.20
0.30
10
B
α
β
0
5
10
0
5
10
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.005” (0.127mm) per side.
JEDEC Equivalent: MO-153
Drawing No. C04-087
DS11195C-page 28
2003 Microchip Technology Inc.
MCP41XXX/42XXX
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
PART NO.
X
/XX
a)
b)
c)
MCP41010-I/SN:
MCP41010-E/P:
I-Temp., 8LD SOIC pkg.
E-Temp., 8LD PDIP pkg.
Device
Temperature
Range
Package
MCP41010T-I/SN: Tape and Reel, I-Temp.,
8LD SOIC pkg.
d)
e)
f)
MCP41050-E/SN: E-Temp., 8LD SOIC pkg.
MCP41050-I/P:
I-Temp., 8LD PDIP pkg.
Device:
MCP41010: Single Digital Potentiometer (10 kΩ)
MCP41010T: Single Digital Potentiometer (10 kΩ)
(Tape and Reel)
MCP41050-E/SN: E-Temp., 8LD SOIC pkg.
g)
MCP41100-I/SN:
I-Temp., 8LD SOIC
package.
E-Temp., 8LD PDIP pkg.
MCP41050: Single Digital Potentiometer (50 kΩ)
(Tape and Reel)
h)
i)
MCP41100-E/P:
MCP41100T-I/SN: I-Temp., 8LD SOIC pkg.
MCP41050T: Single Digital Potentiometer (50 kΩ)
MCP41100: Single Digital Potentiometer (100 kΩ)
(Tape and Reel)
a)
b)
c)
MCP42010-E/P:
MCP42010-I/SL:
E-Temp., 14LD PDIP pkg.
I-Temp., 14LD SOIC pkg.
MCP41100T: Single Digital Potentiometer (100 kΩ)
MCP42010-E/ST: E-Temp., 14LD TSSOP
pkg.
MCP42010: Dual Digital Potentiometer (10 kΩ)
MCP42010T: Dual Digital Potentiometer (10 kΩ)
(Tape and Reel)
d)
MCP42010T-I/ST: Tape and Reel, I-Temp.,
14LD TSSOP pkg.
MCP42050: Dual Digital Potentiometer (50 kΩ)
MCP42050T: Dual Digital Potentiometer (50 kΩ)
(Tape and Reel)
e)
f)
MCP42050-E/P:
E-Temp., 14LD PDIP pkg.
MCP42050T-I/SL: Tape and Reel, I-Temp.,
14LD SOIC pkg.
MCP42100: Dual Digital Potentiometer (100 kΩ)
MCP42100T: Dual Digital Potentiometer (100 kΩ)
(Tape and Reel)
g)
h)
MCP42050-E/SL: E-Temp., 14LD SOIC pkg.
MCP42050-I/ST:
I-Temp., 14LD TSSOP
pkg.
i)
j)
MCP42050T-I/SL: Tape and Reel, I-Temp.,
14LD SOIC pkg.
Temperature Range:
Package:
I
=
=
-40°C to +85°C
-40°C to +125°C
E
MCP42050T-I/ST: Tape and Reel, I-Temp.,
14LD TSSOP pkg.
k)
l)
MCP42100-E/P:
MCP42100-I/SL:
E-Temp., 14LD PDIP pkg.
I-Temp., 14LD SOIC pkg.
P
=
=
=
=
Plastic DIP (300 mil Body), 8-lead, 14-lead
Plastic SOIC (150 mil Body), 8-lead
Plastic SOIC (150 mil Body), 14-lead
TSSOP (4.4mm Body), 14-lead
SN
SL
ST
m) MCP42100-E/ST: E-Temp., 14LD TSSOP
pkg.
n)
MCP42100T-I/SL: Tape and Reel, I-Temp.,
14LD SOIC pkg.
MCP42100T-I/ST: Tape and Reel, I-Temp.,
14LD TSSOP pkg.
o)
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
2003 Microchip Technology Inc.
DS11195C-page 29
MCP41XXX/42XXX
NOTES:
DS11195C-page 30
2003 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical
components in life support systems is not authorized except
with express written approval by Microchip. No licenses are
conveyed, implicitly or otherwise, under any intellectual
property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, MPLAB, PIC, PICmicro, PICSTART, PRO MATE and
PowerSmart are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL
and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Accuron, Application Maestro, dsPICDEM, dsPICDEM.net,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-
Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
PICC, PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo,
PowerMate, PowerTool, rfLAB, rfPIC, Select Mode,
SmartSensor, SmartShunt, SmartTel and Total Endurance are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2003, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
®
PICmicro 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of development
systems is ISO 9001 certified.
2003 Microchip Technology Inc.
DS11195C-page 31
M
WORLDWIDE SALES AND SERVICE
Korea
AMERICAS
ASIA/PACIFIC
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea 135-882
Corporate Office
Australia
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Suite 22, 41 Rawson Street
Epping 2121, NSW
Australia
Tel: 82-2-554-7200 Fax: 82-2-558-5932 or
82-2-558-5934
Fax: 480-792-7277
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
Singapore
Technical Support: 480-792-7627
Web Address: http://www.microchip.com
200 Middle Road
China - Beijing
#07-02 Prime Centre
Singapore, 188980
Unit 915
Atlanta
Bei Hai Wan Tai Bldg.
No. 6 Chaoyangmen Beidajie
Beijing, 100027, No. China
Tel: 86-10-85282100
Fax: 86-10-85282104
3780 Mansell Road, Suite 130
Alpharetta, GA 30022
Tel: 770-640-0034
Fax: 770-640-0307
Tel: 65-6334-8870 Fax: 65-6334-8850
Taiwan
Kaohsiung Branch
30F - 1 No. 8
Boston
Min Chuan 2nd Road
Kaohsiung 806, Taiwan
Tel: 886-7-536-4818
Fax: 886-7-536-4803
China - Chengdu
2 Lan Drive, Suite 120
Westford, MA 01886
Tel: 978-692-3848
Fax: 978-692-3821
Rm. 2401-2402, 24th Floor,
Ming Xing Financial Tower
No. 88 TIDU Street
Taiwan
Chengdu 610016, China
Tel: 86-28-86766200
Taiwan Branch
Chicago
11F-3, No. 207
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: 630-285-0071
Fax: 630-285-0075
Fax: 86-28-86766599
Tung Hua North Road
Taipei, 105, Taiwan
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
China - Fuzhou
Unit 28F, World Trade Plaza
No. 71 Wusi Road
Dallas
Fuzhou 350001, China
Tel: 86-591-7503506
Fax: 86-591-7503521
EUROPE
Austria
4570 Westgrove Drive, Suite 160
Addison, TX 75001
Tel: 972-818-7423
Fax: 972-818-2924
Durisolstrasse 2
China - Hong Kong SAR
A-4600 Wels
Unit 901-6, Tower 2, Metroplaza
223 Hing Fong Road
Austria
Detroit
Tel: 43-7242-2244-399
Fax: 43-7242-2244-393
Denmark
Kwai Fong, N.T., Hong Kong
Tel: 852-2401-1200
Tri-Atria Office Building
32255 Northwestern Highway, Suite 190
Farmington Hills, MI 48334
Tel: 248-538-2250
Fax: 852-2401-3431
Regus Business Centre
Lautrup hoj 1-3
China - Shanghai
Fax: 248-538-2260
Room 701, Bldg. B
Ballerup DK-2750 Denmark
Tel: 45-4420-9895 Fax: 45-4420-9910
Far East International Plaza
No. 317 Xian Xia Road
Shanghai, 200051
Kokomo
France
2767 S. Albright Road
Kokomo, IN 46902
Tel: 765-864-8360
Fax: 765-864-8387
Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
Batiment A - ler Etage
91300 Massy, France
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Tel: 86-21-6275-5700
Fax: 86-21-6275-5060
China - Shenzhen
Los Angeles
Rm. 1812, 18/F, Building A, United Plaza
No. 5022 Binhe Road, Futian District
Shenzhen 518033, China
Tel: 86-755-82901380
18201 Von Karman, Suite 1090
Irvine, CA 92612
Germany
Tel: 949-263-1888
Steinheilstrasse 10
D-85737 Ismaning, Germany
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Fax: 949-263-1338
Fax: 86-755-8295-1393
Phoenix
China - Shunde
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7966
Fax: 480-792-4338
Room 401, Hongjian Building
No. 2 Fengxiangnan Road, Ronggui Town
Shunde City, Guangdong 528303, China
Tel: 86-765-8395507 Fax: 86-765-8395571
Italy
Via Quasimodo, 12
20025 Legnano (MI)
Milan, Italy
China - Qingdao
San Jose
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408-436-7950
Rm. B505A, Fullhope Plaza,
No. 12 Hong Kong Central Rd.
Qingdao 266071, China
Fax: 408-436-7955
Tel: 86-532-5027355 Fax: 86-532-5027205
P. A. De Biesbosch 14
NL-5152 SC Drunen, Netherlands
Tel: 31-416-690399
India
Toronto
Divyasree Chambers
1 Floor, Wing A (A3/A4)
No. 11, O’Shaugnessey Road
Bangalore, 560 025, India
Tel: 91-80-2290061 Fax: 91-80-2290062
Japan
6285 Northam Drive, Suite 108
Mississauga, Ontario L4V 1X5, Canada
Tel: 905-673-0699
Fax: 31-416-690340
United Kingdom
505 Eskdale Road
Fax: 905-673-6509
Winnersh Triangle
Wokingham
Berkshire, England RG41 5TU
Tel: 44-118-921-5869
Fax: 44-118-921-5820
Benex S-1 6F
3-18-20, Shinyokohama
Kohoku-Ku, Yokohama-shi
Kanagawa, 222-0033, Japan
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
07/28/03
DS11195C-page 32
2003 Microchip Technology Inc.
This datasheet has been download from:
www.datasheetcatalog.com
Datasheets for electronics components.
MCP42050-E/P 替代型号
型号 | 制造商 | 描述 | 替代类型 | 文档 |
MCP42050-I/P | MICROCHIP | DUAL 50K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDIP14, 0. | 类似代替 |
MCP42050-E/P 相关器件
型号 | 制造商 | 描述 | 价格 | 文档 |
MCP42050-E/SL | MICROCHIP | Single/Dual Digital Potentiometer with SPI⑩ Interface | 获取价格 | |
MCP42050-E/ST | MICROCHIP | DUAL 50K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO14, 4.40 MM, PLASTIC, TSSOP-14 | 获取价格 | |
MCP42050-EP | MICROCHIP | Single/Dual Digital Potentiometer with SPI Interface | 获取价格 | |
MCP42050-ESL | MICROCHIP | Single/Dual Digital Potentiometer with SPI Interface | 获取价格 | |
MCP42050-I | MICROCHIP | Single/Dual Digital Potentiometer with SPI Interface | 获取价格 | |
MCP42050-I/P | MICROCHIP | DUAL 50K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDIP14, 0.300 INCH, PLASTIC, DIP-14 | 获取价格 | |
MCP42050-I/SL | MICROCHIP | 暂无描述 | 获取价格 | |
MCP42050-I/SN | MICROCHIP | IC,DIGITAL POTENTIOMETER,CMOS,SOP,8PIN,PLASTIC | 获取价格 | |
MCP42050-I/ST | MICROCHIP | Single/Dual Digital Potentiometer with SPI⑩ Interface | 获取价格 | |
MCP42050-I/STG | MICROCHIP | DUAL 50K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO14, 4.40 MM, PLASTIC, TSSOP-14 | 获取价格 |
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