MCP23X08/17_技术文档

AN1043

Unique Features of the MCP23X08/17 GPIO Expanders

I/O PORT DESCRIPTION

Author:

Pat Richards

Microchip Technology Inc.

The I/O port is highly configurable for maximum

flexibility. Figure 1 is a simplified block diagram of an

I/O port pin. The port can either drive logic levels on the

pin, or read logic levels from the pad. The level on the

pad can be read at any time, regardless if the pin is

configured as an input or an output.

INTRODUCTION

GPIO expanders provide easy I/O expansion using

standard serial interfaces. GPIO products are used to

increase the I/O on an MCU or provide remote I/O

using a serial interface.

The IODIR register controls the direction of the pins

(input or output). More specifically, the IODIR registers

simply enables/disables the output driver. When the

driver is activated (IODIR = 0), the pad is driven to the

state in the latch register (OLAT). When deactivated

(IODIR = 1), the driver is high impedance.

This application note discusses the feature set and use

of the MCP23X08/17 (8-bit and 16-bit) GPIO Expand-

ers.

The MCP23X08 are 8-bit GPIO Expanders:

• MCP23008: I²C™ Interface

The I/O port has multiple, individual configurations.

^{Each pin can}…

• MCP23S08: SPI Interface

• …be configured as an input. The output driver is

The MCP23X17 are 16-bit GPIO Expanders:

• MCP23017: I²C Interface

disabled (high impedance)

^•…be configured as an output. The output driver

is enabled and the value in the latch is driven on

the pin.

• MCP23S17: SPI Interface

The functions and features of the MCP23X08 and

MCP23X17 are basically the same, except where

otherwise noted.

^•…enable a weak pull-up resistor

^•…emulate an open-drain configuration. This is

accomplished by clearing the output latch (OLAT)

bit to a zero and using the direction register

(IODIR) to set the level on the pin. A pull-up

resistor is required to pull the pin to voltage when

the pin is an input

FEATURES

This application note discusses some of the features of

the MCP23X08/17 and how they may be used in an

application:

- To drive a 0: configure the pin as an output

(IODIR = 0) so the port drives whatever is in

OLAT (logic 0 in this case)

• I/O Port Description

• 8/16-Bit Mode (MCP23X17 only)

• Interrupt Features

- To float a 1: set the pin as an input

(IODIR = 1). The output driver is disabled

and the pull-up resistor pulls the pin to a

logic 1

- Mapping Interrupts

- Mirroring Interrupts (MCP23X17 only)

- Servicing Interrupts

• Internal Address Pointer Control

• Hardware Address Pin on SPI

DS01043A-page 1

AN1043

FIGURE 1:

I/O PORT BLOCK DIAGRAM

TABLE 1:

MEMORY MAP

8-bit Mode

16-bit Mode

V_DD

Register

Name

Address

(hex)

Register Address

MCP23X08/17

Name

(hex)

IODIRA

IPOLA

00

01

02

03

04

05

06

07

08

09

0A

10

11

12

13

14

15

16

17

18

19

1A

IODIRA

IODIRB

IPOLA

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

SET

Data Bus

Write

D

Q

I/O

Pad

CLR

Q

GPINTENA

DEFVALA

INTCONA

IOCON

OLAT or

GPIO

IPOLB

SET

Input

Buffer

D

Q

GPINTENA

GPINTENB

DEFVALA

DEFVALB

INTCONA

INTCONB

IOCON

Write

CLR

Q

IODIR

GPPUA

INTFA

SET

CLR

Q

D

INTCAPA

GPIOA

Read

Port

OLATA

IODIRB

IPOLB

IOCON

8/16 BIT MODE (MCP23X17 ONLY)

GPPUA

GPPUB

INTFA

GPINTENB

DEFVALB

INTCONB

IOCON

The MCP23X17 has the unique ability to appear to the

MCU as either two (2) 8-bit GPIO expanders, or as a

single 16-bit GPIO expander.

INTFB

This is accomplished by splitting the 16 I/O ports into

two separate 8-bit I/O ports (Port A and Port B) via

IOCON.bank.

INTCAPA

INTCAPB

GPIOA

GPPUA

INTFB

12

13

14

15

Each port has a group of dedicated registers. Table 1

shows how the register groups (Port A and Port B) are

mapped when in 8-bit or 16-bit mode.

INTCAPB

GPIOB

OLATA

OLATB

Note:

Unlike all other registers which are not

shared between the two ports (Port A and

Port B), there is one register (IOCON).

which is shared between the ports and

affects both equally.

8-Bit Mode:

When in 8-bit mode, the ports’ registers are separated:

• Port A register addresses range from 00h – 0Ah

• Port B register addresses range from 10h – 1Ah

16-bit Mode:

When in 16-bit mode, the ports’ registers are

interleaved to emulate 16-bit wide registers:

• Port A and Port B register addresses range from

00h – 15h. The registers are still addressed as

8-bit ports, meaning that the 16-bit mapping pair

is always an even number (e.g., IODIR starts at

00h, IPOL starts at 02h, etc.)

DS01043A-page 2

AN1043

Interrupt Conditions

INTERRUPT FEATURES

There are several configurable interrupt conditions

which allow flexible configurations.

The MCP23X08 has one interrupt pin and the

MCP23X17 has two interrupt pins.

For the MCP23X17, each interrupt pin is associated

with an 8-bit port. INTA is associated with Port A and

INTB is associated with Port B.

INTERRUPT-ON-PIN-CHANGE

Pins configured for interrupt-on-pin-change will

cause an interrupt to occur if a pin changes to the

opposite state. The default state is reset after an

interrupt is serviced. For example, an interrupt occurs

by an input changing from 1 to 0. The interrupt is then

serviced while the pin state is still 0 by reading GPIO or

INTCAP register. The new initial state for the pin is a

logic 0. Likewise, if the pin is toggled back to a logic 1

before servicing the interrupt, the new default state is a

logic 1.

Interrupt Mapping

The MCP23X17 interrupt pins can be mapped in two

ways (see Figure 2) as controlled by IOCON.MIRROR:

1. Interrupt pins operate independently. INTA

reflects interrupt conditions on Port A and INTB

reflects interrupt conditions on Port B.

2. Both interrupt pins go active when an interrupt

occurs on either port.

The interrupt condition is cleared by reading either

INTCAP or GPIO register. The new pin state default is

set when the interrupt is cleared.

Interrupt Polarity and Open-Drain

INTERRUPT-ON-CHANGE FROM DEFVAL

REGISTER VALUE

The interrupts can be configured to operate in three

modes:

1. Active-High.

2. Active-Low.

3. Open-Drain.

Pins configured for interrupt-on-change from

register value will cause an interrupt to occur if the

corresponding input pin differs from the register bit. The

interrupt condition will remain as long as the condition

exists, regardless if the INTCAP or GPIO is read.

The interrupt polarity and open-drain is configured via

INTPOL and ODR bits in the IOCON register.

For example, if DEFVAL<b0> = 0. An interrupt will

occur if the pin changes to a logic 1 and the interrupt

will remain as long as the pin remains a logic 1. The

interrupt condition will clear if the pin changes back to

a logic 0 and INTCAP or GPIO is read.

Note:

For the MCP23X17, the polarity and open-

drain configuration of the INTA and INTB

pins are not independent. Both pins are

configured the same.

FIGURE 2:

INTERRUPT BLOCK DIAGRAM

IOCON.ODR

IOCON.INTPOL

IOCON.MIRROR

0

1

INTA

Open-

Polarity

A

B

Drain

Control

INTB

0

1

DS01043A-page 3

AN1043

FIGURE 3:

INTERRUPT-ON-PIN-CHANGE EXAMPLE

Change cause interrupt.

Port state captured in

INTCAP

Change cause interrupt.

Port state captured in

INTCAP

No affect on INT pin or

INTCAP

GP3

INT

Interrupt cleared and

re-enabled

SPI

Read INTCAP or GPIO

Given:

- GP3 configured to “interrupt-on-pin-change”

- INT pin configured for “active low”

FIGURE 4:

INTERRUPT-ON-CHANGE-FROM-DEFVAL EXAMPLE

GPINTEN – GPIO Interrupt-on-Change Enable Register

GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0

X

1

X

INTCON – Interrupt Control Register

IOC7

X

IOC6

X

IOC5

X

IOC4

X

IOC3

1

IOC2

X

IOC1

X

IOC0

X

DEFVAL – Default Value Register

DEF7

X

DEF6

X

DEF5

X

DEF4

X

DEF3

0

DEF2

X

DEF1

X

DEF0

X

Interrupt will occur if GP3 logic level = 1

Change cause interrupt.

Port state captured in

INTCAP

GP3 = DEF3

INT deactivates

after SPI read

GP3

INT remains

because GP3 = 1

(opposite of DEF3)

No affect on INT

pin or INTCAP

INT

SPI

Read INTCAP or GPIO

DS01043A-page 4

AN1043

For example, when configuring the device, it may be

desirable to allow the address pointer to automatically

increment so the device does not have to be re-

addressed after every byte.

INTERNAL ADDRESS POINTER

CONTROL

Some slave serial devices automatically increment

their internal address pointer after each byte is clocked

by the master. This allows the master to sequentially

access multiple registers without re-sending the write

or read command.

Likewise, when performing a continuous operation on

a register (e.g., changing the outputs on a regular basis

by writing to GPIO or OLAT), it may be beneficial to

disable the address incrementing feature so that the

register is always accessed without re-addressing the

register.

Other slave devices do not automatically increment

their internal address pointer.

The MCP23X08/17 family of devices have the ability to

do either by configuring a control bit (IOCON.SEQOP).

This allows maximum flexibility when accessing the

registers.

FIGURE 5:

8-BIT MODE: ADDRESS POINTER DISABLED (MCP23008 EXAMPLE)

When the address pointer is DISABLED and the device is in

8-bit mode, the address pointer will not increment the

address pointer.

S 0 1 0 0 a a a 0 A 0 0 0 0 1 0 1 0 A 1 0 1 0 1 0 1 0 A 0 1 0 1 0 1 0 1 A 1 0 1 0 1 0 1 0 P

MCP23X08

Opcode

Register

Addr = 09h

Data @

09h

Data @

09h

Data @

09h

GPIOA

OLATA

09

0A

10

11

12

13

14

15

16

17

18

19

1A

IODIRB

IPOLB

GPINTENB

DEFVALB

INTCONB

IOCON

GPPUB

INTFB

INTCAPB

GPIOB

See Figure 5 and Figure 6 for address pointer examples for the

MCP23X08 8-bit devices and Figure 7 and Figure 8 for the

MCP23X17 examples.

OLATB

DS01043A-page 5

AN1043

FIGURE 6:

8-BIT MODE: ADDRESS POINTER ENABLED (MCP23008 EXAMPLE)

When the address pointer is ENABLED and the device is in

8-bit mode, the address pointer will increment after every

byte is clocked. The address pointer will roll over to 00h

after exceeding 1Ah (which is the last location of Port B).

S 0 1 0 0 a a a 0 A 0 0 0 0 1 0 1 0 A 1 0 1 0 1 0 1 0 A 0 1 0 1 0 1 0 1 A 1 0 1 0 1 0 1 0 P

MCP23X08

Opcode

Register

Addr = 09h

Data @

09h

Data @

0Ah

Data @

10h

GPIOA

OLATA

09

0A

10

11

12

13

14

15

16

17

18

19

1A

IODIRB

IPOLB

GPINTENB

DEFVALB

INTCONB

IOCON

GPPUB

INTFB

INTCAPB

GPIOB

Note: The address pointer jumps

from 0Ah to 10h when transitioning

from Port A to Port B

OLATB

FIGURE 7:

16-BIT MODE: ADDRESS POINTER DISABLED (MCP23017 EXAMPLE)

When the address pointer is DISABLED and the device is in

16-bit mode, the address pointer will alternate between the

register pair. Also, the initial address can be either register

address (e.g., 14h or 15h) and the pointer will still alternate

between the registers.

S 0 1 0 0 a a a 0 A 0 0 0 1 0 0 1 0 A 1 0 1 0 1 0 1 0 A 0 1 0 1 0 1 0 1 A 1 0 1 0 1 0 1 0 P

MCP23X17

Opcode

Register

Addr = 12h

Data @

12h

Data @

13h

Data @

12h

INTCONB

09

0A

0B

0C

0D

0E

0F

10

11

12

13

14

15

IOCON

GPPUA

GPPUB

INTFA

INTFB

INTCAPA

INTCAPB

GPIOA

GPIOB

OLATA

OLATB

DS01043A-page 6

AN1043

FIGURE 8:

16-BIT MODE: ADDRESS POINTER ENABLED (MCP23017 EXAMPLE)

When the address pointer is ENABLED and the device is in

16-bit mode, the address pointer will increment after every

byte is clocked. The address pointer will roll over to 00h

after exceeding 15h.

S 0 1 0 0 a a a 0 A 0 0 0 1 0 0 1 0 A 1 0 1 0 1 0 1 0 A 0 1 0 1 0 1 0 1 A 1 0 1 0 1 0 1 0 P

MCP23X17

Opcode

Register

Addr = 12h

Data @

12h

Data @

13h

Data @

14h

INTCONB

09

0A

0B

0C

0D

0E

0F

10

11

12

13

14

15

IOCON

GPPUA

GPPUB

INTFA

INTFB

INTCAPA

INTCAPB

GPIOA

GPIOB

OLATA

OLATB

DS01043A-page 7

AN1043

The “S” devices (MCP23S08 and MCP23S17) have

SPI interfaces. These devices use a chip select for

selecting the part, however, these parts also have hard-

ware address pins, thereby giving the advantage of

attaching multiple devices on the bus while only

consuming one MCU pin for chip select (see Figure 9).

HARDWARE ADDRESS PINS

Address pins are typically used on I²C devices to allow

multiple devices with the same base slave address to

operate on the bus.

Slave devices with SPI interfaces typically use only a

chip select pin to select the device. This requirement

consumes one MCU pin for every SPI device on the

bus.

FIGURE 9:

ADDRESS PINS ON SPI DEVICES

MCP23S17

CS

SCK

SDI

GP15

.

SPI

MCP23S08

SDO

GPIO

Port

GP7

.

MCP23S08

.

A2

A1

A0

.

Addr

Pins

A1

A0

GP0

A2 A1 A0

S 0 1 0 0 1 0 0 0 A 0 0 0 0 1 0 1 0 A

MCP23X17

Opcode

Register Addr

SUMMARY

The MCP23X08/17 family of GPIO Expanders have

some unique features, giving the system and module

engineer maximum flexibility when designing with the

MCP23X08/17.

DS01043A-page 8

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DS01043A-page 9

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DS00000A-page 10


型号：	MCP23X08/17
厂家：	MICROCHIP
描述：	Unique Features of the MCP23X08/17 GPIO Expanders 在MCP23X08 / 17 GPIO扩展器的独特功能
文件：	总10页 (文件大小：297K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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