LE87536NQCT [MICROCHIP]
Line Driver, 4 Func, 4 Driver;
| 型号： | LE87536NQCT |
| 厂家： | 
MICROCHIP |
| 描述： | Line Driver, 4 Func, 4 Driver 驱动 接口集成电路 驱动器 |
| 文件： | 总14页 (文件大小：179K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Le87536
Worldwide ADSL2+ Dual Channel
Line Driver BD870 Series
Advance Data Sheet
Version 2
Aug 2010
134329
Features
Document Number
•
•
•
Fixed Voltage Gain Of 13
450 mA Peak Output Drive Capability
Ordering Information
Le87536NQC
Le87536NQCT
16 pin QFN Green Pkg.
16 pin QFN Green Pkg.
Tray
Tape & Reel
±5 V to ±12 V Dual Supplies Or 10 V to 24 V
Single Supply
The green package meets RoHS Directive 2002/95/EC of the
European Council to minimize the environmental impact of electrical
equipment.
•
•
•
•
•
•
•
44 V Differential Output Into a 100 Ω Load
p-p
40.5 V
Differential Output Into a 60 Ω Load
p-p
Low-power Disable Mode For Each Driver
4 mA Per Amplifier Quiescent Supply Current
-75dBc THD With 1MHz Signal Into a 60 Ω load
16-pin (4 mm x 4 mm) QFN Package
RoHS Compliant
Logic
Control
VS+
ENAB
VS-
Logic
Control
ENCD
VINA
GND
+
–
VOUTA
VS+
Applications
A
7.5kΩ
7.5kΩ
.
.
RF
•
•
Dual Port Full Rate ADSL2+ Line Drivers
HDSL Line Drivers
50kΩ
50kΩ
.
VCMAB
RG
RF
–
Description
.
The Le87536 is a dual channel differential amplifier
designed to drive full rate ADSL2+ signals with very
low power dissipation. The Le87536 contains two pairs
of wide band amplifiers designed with Zarlink’s HV30
Bipolar SOI process for low power consumption in
DSL systems. The amplifiers have an internal fixed
gain, which helps to eliminate external feedback and
gain setting resistors.
VS-
VOUTB
VOUTC
B
+
VINB
VINC
+
–
VS+
C
7.5kΩ
7.5kΩ
.
.
RF
50kΩ
50kΩ
.
VCMCD
RG
The drivers achieve better than -75 dB THD while
driving a 1MHz, 16Vp_p signal into a 60Ω load. The
amplifiers are enabled by forcing the ENAB/ENCD
pins to ground. Leaving the ENAB/ENCD pins floating
or forcing them high will disable the two amplifiers. The
ENAB and ENCD pins are pulled up to an internal 2.5V
through on-chip 50kΩ resistors.
RF
–
.
VS-
VOUTD
D
+
VIND
Figure 1 - Block Diagram
Le87536 device is one of the most cost-effective and
high performance line drivers for ADSL2+ applications.
1
Zarlink Semiconductor Inc.
Zarlink, ZL, the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc
Copyright 2009, Zarlink Semiconductor Inc. All Rights Reserved.
Le87536
Advance Data Sheet
1.0 Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.0 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1.1 Input Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1.2 Output Driving Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1.3 Power Supplies and Component Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1.4 Stability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Cable Termination Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3 Line Driver Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.0 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 Thermal Resistance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 Package Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.0 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.0 Device Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6.0 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.1 16-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7.0 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.1 Rev 1.0 to Rev 2.0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Zarlink documents marked "Preliminary Data Sheet” or “Advance Data Sheet” relate to Zarlink products which are not yet released to production.
2
Zarlink Semiconductor Inc.
Le87536
Advance Data Sheet
1.0 Pin Diagram
Top View
VINA
VINB
GND
VINC
1
2
3
4
12
11
10
9
VOUTB
GND
16-pin QFN
VOUTC
VOUTD
EXPOSED PAD
Notes:
1. Pin 1 is marked for orientation.
2. The Le87536 device incorporates an exposed die pad on the underside of its package. The pad acts as a heat sink and must be
connected to a copper plane through thermal vias, for proper heat dissipation. The exposed pad is electrically floating. It may be
tied to ground or any other quiet signal reference node.
1.1 Pin Description
Pin Name
Type
Description
Note
ENAB
ENCD
VINA
Input
Input
DSL channel #1 enable/disable control pin
DSL channel #2 enable/disable control pin
Amplifier A non-inverting input
Amplifier B non-inverting input
Amplifier C non-inverting input
Amplifier D non-inverting input
Bias voltage for amplifier A and B
Bias voltage for amplifier C and D
Positive power supply
Reference Circuit 1
Reference Circuit 1
Reference Circuit 2
Reference Circuit 2
Reference Circuit 2
Reference Circuit 2
Input
VINB
Input
VINC
Input
VIND
Input
VCMAB
VCMCD
VS+
Input
Input
Power
Power
Ground
Output
Output
Output
Output
VS-
Negative power supply
GND
Ground connection
VOUTA
VOUTB
VOUTC
VOUTD
Amplifier A output
Reference Circuit 2
Reference Circuit 2
Reference Circuit 2
Reference Circuit 2
Amplifier B output
Amplifier C output
Amplifier D output
Note 1: Amplifiers A and B comprise DSL channel #1. ENAB allows enable/disable control for DSL channel #1.
Note 2: Amplifiers C and D comprise DSL channel #2. ENCD allows enable/disable control for DSL channel #2.
Note 3: Reference circuits 1 and 2 are shown in Figure 2.
3
Zarlink Semiconductor Inc.
Le87536
Advance Data Sheet
2.5V
VS+
50K
150K
ENAB/CD
Reference circuit 1
GND
VS+
VINx
VOUTx
x = A, B, C, D
Internal
Circuit
Reference circuit 2
VS-
Figure 2 - Reference Circuit
4
Zarlink Semiconductor Inc.
Le87536
Advance Data Sheet
2.0 Applications
The Le87536 integrates two sets of high-power line driver amplifiers that can be connected for full duplex
differential line transmission. The amplifiers are designed to be used with signals up to 10 MHz with low signal
distortion. The driver can put out 20.5 dBm power level onto the telephone line and can drive 450 mA current, which
exceeds the level required when using a transformer with 1:2 ratio.
2.1 Typical Application Circuit
A typical application interface circuit (one channel) is shown in Figure 3.
ROUT
CTX
VINA
+
–
TX+
VOUTA
RF
2RG
100
RF
ROUT
CTX
–
VOUTB
RX1
+
VINB
TX-
RF
–
RX+
RX-
+
RX2
RX1
+
–
Data Receive
RF
RX2
Figure 3 - Typical Application Interface Circuit
As shown in Figure 3 the amplifiers have identical positive gain connections with common-mode rejection. Any DC
input errors are duplicated and create common-mode rather than differential line errors. The component values for
Typical Application is listed in Table 1.
Item
Quantity
Type
Value
Tolerance
Rating
R
C
2
2
SMT
X7R
49.9 Ω
1%
1/16 W
50V
OUT
TX
0.22 µF
10%
Table 1 - Parts List for Typical Application Circuit
2.1.1 Input Considerations
The driving source impedance should be less than 100nH to avoid any ringing or oscillation. This inductance is
equivalent to about 4" of unshielded wiring, or 6" of unterminated transmission line. Normal high-frequency
construction obviates any such problem.
5
Zarlink Semiconductor Inc.
Le87536
Advance Data Sheet
2.1.2 Output Driving Considerations
While the drive amplifiers can output in excess of 450 mA peak, the internal metallization is not designed to carry
more than 100 mA of steady DC current and there is no current limit mechanism. The device can safely drive
sinusoidal currents of 2 x 100 mArms, or 200 mArms. This current is more than that required to drive line
impedance to large output levels, but output short circuits can not be tolerated. The series output resistor will
usually limit currents to safe values in the event of line shorts. Driving lines with no series resistor is not
recommended.
The amplifiers are sensitive to capacitive loading. More than 100pF may cause peaking of the frequency response.
The same is true of badly terminated lines connected without a series matching resistor.
When in power down mode, several volts of differential voltage may appear across the line driver outputs. If a DC
current path exists between the two outputs, a large DC current can flow from the positive supply rail to the negative
supply rail through the outputs. To avoid DC current flow, the most effective solution is to place DC blocking
capacitors in series at the output, as shown in the typical application circuit.
2.1.3 Power Supplies and Component Placement
The power supplies should be well bypassed close to the Le87536 device. A 2.2 µF tantalum capacitor and a 0.1 µF
ceramic capacitor for each supply is recommended. The ground terminal of the positive and negative bypass
capacitors should be connected to each other directly and then returned to circuit ground to prevent ground current
loops.
The Le87536 can also be powered from a single positive voltage supply. When operating in this mode, the VS+ pin
is connected to the positive supply. The VS- pin is connected to GND.
2.1.4 Stability
The Le87536 features improved frequency compensation for all applications, allowing stable operation at very low
power levels and eliminating any need for external “snubber” circuit. Differential circuits, such as ADSL line driver
applications, can be especially prone to common-mode oscillation. The Le87536 is specifically compensated to
eliminate this type of instability and allows for reliable operation even at very low power levels.
2.2 Cable Termination Technique
There are various techniques available. Figure 4 shows a passive termination technique. Figure 5 shows an active
termination technique. A quick comparison of the reduction in voltage and power requirements for the driver with
passive or active termination is shown in Table 2.
The output impedance and the voltage gain of the circuit in Figure 5 are shown in the following equations.
ZOUT = K • RBM
VO
VIN
RD(P2)
---------
----------------------------------------------------
=
2(RD(G) – RD(P1))
where
ZOUT is the output impedance. VO/VIN represents the voltage gain.
1
-----------------------------
1 –
K =
RD(P1)
-------------------
RD(G)
RP1
---------------------------
RP2
RP1 + RP2
RG
RG + RF
---------------------------
----------------------
RD(P1) =
,
RD(P2) =
,
RD(G) =
RP1 + RP2
6
Zarlink Semiconductor Inc.
Le87536
Advance Data Sheet
RG
RF
RBM
–
+
ZL
VO
VIN
RL
Figure 4 - Passive Termination Technique
RG
RF
RBM
–
+
ZL
VO
RP1
RP2
RL
VIN
Figure 5 - Active Termination Technique
Passive Termination
Active Termination
16.5 V
into a 100 Ω line
16.5 V
into a 100 Ω line
P-P
P-P
V
= V
+ V
V
= V
+ V
RBM RLOAD
OUT DRIVER
RBM
RLOAD
OUT DRIVER
RBM = R
RBM = R
/5
LOAD
LOAD
V
V
V
= V
V
V
V
= V
/5
RLOAD
RBM
RLOAD
RBM
OUT DRIVER
= 33.52 V
= 20.11 V
OUT DRIVER
= 37.52 V
= 24.11 V
SUPPLY
SUPPLY
I
= 31.6 mA
I
= 31.6 mA
OUT
OUT
P
= V
* I
= 0.714 W
P
= V
* I
= 1.185 W
OUT DRIVER
SUPPLY
OUT
OUT DRIVER
SUPPLY OUT
(plus quiescent power)
(plus quiescent power)
Table 2 - Passive and Active Termination Comparison
7
Zarlink Semiconductor Inc.
Le87536
Advance Data Sheet
2.3 Line Driver Protection
High voltage transients such as lightning can appear on the telephone lines. Transient protection devices are used to absorb the
energy and clamp the voltages. However, large transient voltages can still couple to the primary side of the transformer.
As shown in Figure 6 and 7, the series output termination resistors limit the current going into the line driver. These termination
resistors should be specified at 0.5W. The resistance can be 2.2Ω or greater required by the sensing and termination impedance.
A protection scheme is shown in Figure 6, assuming that the isolation of the data transformer is sufficient and the diodes on the
secondary side of the data transformer are not causing degradation of data performance.
To avoid the possible concerns in Figure 6 on board secondary protection may be added, as shown in Figure 7. The external
diodes may be moved to the outputs of the line driver. The grounded protector, U1, is on the line side to limit the peak surge
voltage seen by the data transformer. The series components, U21 and U22, can be Positive Temperature Coefficient (PTC)
devices or fuses.
The protection scheme can vary depending on the type of data transformer used, the data rate, the intended protection criteria to
meet and trade offs between performance and cost. Consult your Zarlink representatives for more specific details on protection.
VS+
+
–
RBM
VIN+
VO+
VS -
VS+
RF
RF
2RG
VO-
–
+
RBM
VIN-
VS -
Figure 6 - Line Driver Protection Diagram (1)
VS+
+
–
RBM
VIN+
U21
VO+
VS -
VS+
RF
RF
2RG
U1
VO-
U22
–
+
RBM
VIN-
VS -
Figure 7 - Line Driver Protection Diagram (2)
8
Zarlink Semiconductor Inc.
Le87536
Advance Data Sheet
3.0 Absolute Maximum Ratings
Stresses above the values listed under Absolute Maximum Ratings can cause permanent device failure.
Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods
can affect device reliability.
Storage Temperature
−65 ≤ T ≤ +150°C
A
Operating Ambient Temperature
−40 ≤ T ≤ +85°C
A
Operating Junction Temperature
(See Notes 1 and 2)
−40 ≤ T ≤ +150°C
A
VS+ to VS- Supply Voltage
−0.3 V to 30 V
−0.3 V to 30 V
−30 V to +0.3 V
VS- to VS+
VS+ with respect to GND
VS- with respect to GND
Driver inputs VINA/B/C/D
Control inputs ENAB/ENCD with respect to GND
Maximum current on any input
−0.3 V to 6 V
10 mA
Maximum current at amplifier output (DC continuous)
ESD Immunity (Human Body Model)
ESD Immunity (Charge Device Model)
100 mA
JESD22 Class 2 compliant
JESD22 Class IV compliant
Note: Continuous operation above 145°C junction temperature may degrade device reliability.
3.1 Thermal Resistance
The thermal performance of a thermally enhanced package is assured through optimized printed circuit
board layout. Specified performance requires that the exposed thermal pad be soldered to an equally sized
exposed copper surface, which, in turn, conducts heat through multiple vias to larger internal copper
planes.Please refer to the QFN Package application note, available from http://www.zarlink.com, for layout and
heat sinking guidelines.
When the QFN package is mounted on 4 layers JEDEC PCB in still air the following thermal characteristics are
expected:
Θ
35.3°C/W, Θ 22.0°C/W, Θ 15.6°C/W and Ψ 0.4°C/W.
JC JB JT
JA
The maximum junction temperature is 150°C.
3.2 Package Assembly
The green package devices are assembled with enhanced, environmental compatible lead-free, halogen-free, and
antimony-free materials. The leads possess a matte-tin plating which is compatible with conventional board
assembly processes or newer lead-free board assembly processes.
Refer to IPC/JEDEC J-Std-020 Table 4-2 for recommended peak soldering temperature and Table 5-2 for the
recommended solder reflow temperature profile.
9
Zarlink Semiconductor Inc.
Le87536
Advance Data Sheet
4.0 Operating Ranges
Zarlink guarantees the performance of this device over commercial (0°C to 70°C) and industrial (−40°C to 85°C)
temperature ranges by conducting electrical characterization over each range and by conducting a single insertion
production test coupled with periodic sampling. These characterization and test procedures comply with section
4.6.2 of Bellcore GR-357-CORE Component Reliability Assurance Requirements for Telecommunications
Equipment.
Ambient temperature
-40°C to +85°C
+12 V ± 5%
-12 V ± 5%
VS+ with respect to GND
VS- with respect to GND
Single battery operation, VS+ with respect to GND (VS- to GND) +24V ± 5%
5.0 Device Specifications
Typical Conditions: VS = ±12V, RL = 65Ω, unless otherwise specified, TA = 25°C.
Min/Max Parameters: TA = −40 to +85°C
Amplifiers are tested separately.
Parameter
Description
Condition
Min.
Typ.
Max.
Unit
Supply Current Characteristics
IS+ (Full IS)
IS- (Full IS)
Positive Supply Current
per Amplifier
All outputs at 0V, ENAB = ENCD = 0V
All outputs at 0V, ENAB = ENCD = 0V
All outputs at 0V, ENAB = ENCD = 5V
All outputs at 0V, ENAB = ENCD = 5V
All outputs at 0V
3.2
4.0
-3.8
0.2
5.3
-3.0
0.4
mA
mA
mA
mA
mA
Negative Supply Current
per Amplifier
-5.1
IS+ (power down)
IS- (power down)
IGND
Positive Supply Current
per Amplifier
Negative Supply Current
per Amplifier
-0.3
1.6
0.1
GND Supply Current per
Amplifier
0.25
Control Input (C0 and C1) Characteristics
VIH
VIL
IIH
IIL
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
ENAB and ENCD inputs
ENAB and ENCD inputs
ENAB = ENCD = 5V
ENAB = ENCD = 0V
V
V
0.8
40
5
20
µA
µA
-85
-50
-30
Amplifier Input (VINx+ and VINx-) Characteristics
VOS
∆VOS
IB
Input Offset Voltage
VOS mismatch
Input Bias Current
IB Mismatch
-10
-5
0
0
10
5
mV
mV
µA
-15
-25
14
25
∆IB
0
µA
VCM
Driver common mode
voltage
|VS+| +
|VS-|
pins VCMAB/CD floating, reference to VS-
0.475
0.5
0.525
Transimpedance1
ROL
eN
5
MΩ
Input Noise Voltage1
3.5
nV/ Hz
pA/ Hz
iN
Input Noise Current1
13
Table 3 - Electrical Specifications
10
Zarlink Semiconductor Inc.
Le87536
Advance Data Sheet
Parameter
Description
Condition
Min.
Typ.
Max.
Unit
Amplifier Output (VOUT) Characteristics
VOUT
RL = 100Ω
±10.3 ±11.1
V
V
Loaded Output Swing
RL = 30Ω (+)
RL = 30Ω (−)
10.1
10.7
-10.5
600
(RL Single-ended to
GND)
-10.1
V
1
IOUT
VOUT = 0.6V, RL = 1Ω
mA
Output Current
Amplifier Dynamic Characteristics
THD
Total Harmonic Distortion
f = 1MHz, RL = 50Ω, VOUT = 16Vpp
-75
-70
dBc
dBc
26kHz to 1.1MHz, RL = 100Ω,
PLINE =20.4dBm
MTPR
Multi-Tone Power Ratio
1
SR
AV
VOUT from -8V to +8V measured at ±4V
200
400
V/µs
V/V
Slew rate (single-ended)
Voltage Gain
VOUT = 16Vpp, RL = 100Ω
12.9
13.0
13.1
Note 1: This parameter is not tested in production. It is guaranteed by design and device characterization.
Table 3 - Electrical Specifications
11
Zarlink Semiconductor Inc.
Le87536
Advance Data Sheet
6.0 Physical Dimensions
6.1 16-Pin QFN
12
Zarlink Semiconductor Inc.
Le87536
Advance Data Sheet
7.0 Revision History
7.1 Rev 1.0 to Rev 2.0
•
Added package thermal data on page 9.
13
Zarlink Semiconductor Inc.
For more information about all Zarlink products
visit our Web Site at
www.zarlink.com
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application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may
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that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property
rights owned by Zarlink.
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of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other
information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the
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any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and
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not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in
significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request.
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