LE58QL063HVC [MICROCHIP]
4CH SLAC 3V GCI 28 I/0 LQFP64;
| 型号： | LE58QL063HVC |
| 厂家： | 
MICROCHIP |
| 描述： | 4CH SLAC 3V GCI 28 I/0 LQFP64 PC 电信 电信集成电路 |
| 文件： | 总108页 (文件大小：1037K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Le58QL061/063
Quad Low Voltage Subcriber Line
Audio-Processing Circuit - Ve580 Series
Data Sheet
Document ID#: 080754
Version 8
June 2011
Features
•
Low-power, 3.3 V CMOS technology with 5 V
tolerant digital inputs
Ordering Information
Device
Package1 (Green) Packing2
•
•
Pin programmable PCM/MPI or GCI interface
Le58QL061BVC
Le58QL063HVC
44-pin TQFP
64-pin LQFP
Trays
Trays
Software and coefficient compatible to the
Le79Q061/063 QSLAC device
1. The green package meets RoHS Directive 2002/95/EC of the
European Council to minimize the environmental impact of
electrical equipment.
•
Standard PCM/microprocessor interface
(PCM/MPI mode)
2. For delivery using a tape and reel packing system, add a "T"
suffix to the OPN (Ordering Part Number) when placing an
order.
•
•
Single or Dual PCM ports available
Time slot assigner (up to 128 channels per
port)
•
256 kHz or 293 kHz chopper clock for Zarlink
SLIC devices with switching regulator
•
•
•
Clock slot and transmit clock edge options
Optional supervision on the PCM highway
•
Maximum channel bandwidth for V.90 modems
1.536, 1.544, 2.048, 3.072, 3.088, 4.096,
6.144, 6.176, or 8.192 MHz master clock
derived from MCLK or PCLK
Applications
•
Codec function on telephone switch line cards
•
•
µP access to PCM data
Real Time Data with interrupt (open drain or
TTL)
GCI/PCM
Interface
Analog
VIN1
DXA/DU
DRA/DD
TSCA
DXB
Signal Processing
Channel 1 (CH 1)
•
Broadcast mode
VOUT1
PMC & GCI Interface
&
VIN2
Signal Processing
Channel 2 (CH 2)
•
General Circuit Interface (GCI mode)
Time Slot Assigner
(TSA)
VOUT2
DRB
VIN3
•
•
•
Control and PCM data on a single port
2.048 Mbits/s data rate
Signal Processing
Channel 3 (CH 3)
TSCB
VOUT3
VIN4
Signal Processing
Channel 4 (CH 4)
VOUT4
VREF
SLIC
2.048 MHz or 4.096 MHz clock option
Clock
&
Reference
Circuits
CD11
CD21
C31
•
•
Performs the functions of four codec/filters
Software programmable:
C41
FS/FSC
C51
PCLK/DCL
MCLK/E1
C61
C71
•
SLIC device input impedance and Transhybrid
balance
CD12
CD22
C32
C42
•
•
Transmit and receive gains and Equalization
C52
C62
C72
SLIC
Interface
(SLI)
Programmable Digital I/O pins with
debouncing
DCLK/S0
CD13
CD23
CS/PG
DIO/S1
GCI Control Logic &
Microprocessor Interface
(MPI)
C33
C43
C53
C63
C73
INT
•
•
A-law, µ-law, or linear coding
RST
CD14
CD24
Built-in test modes with loopback, tone
generation, and µP access to PCM data
C34
C44
C54
C64
•
Mixed state (analog and digital) impedance
scaling
C74
CHCLK
•
•
Performance guaranteed over a 12 dB gain range
Supports multiplexed SLIC device outputs
Figure 1 - Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2009-2011, Zarlink Semiconductor Inc. All Rights Reserved.
Le58QL061/063
Data Sheet
Description
The Le58QL061/063 Quad Low Voltage Subscriber Line Audio-Processing Circuit (QLSLAC™) devices integrate
the key functions of analog line cards into high-performance, very-programmable, four-channel codec-filter devices.
The QLSLAC devices are based on the proven design of Zarlink’s reliable SLAC™ device families. The advanced
architecture of the QLSLAC devices implements four independent channels and employs digital filters to allow
software control of transmission, thus providing a cost-effective solution for the audio-processing function of
programmable line cards. The QLSLAC devices are software and coefficient compatible to the QSLAC devices.
Advanced submicron CMOS technology makes the Le58QL061/063 QLSLAC devices economical, with both the
functionality and the low power consumption needed in line card designs to maximize line card density at minimum
cost. When used with four Zarlink SLIC devices, a QLSLAC device provides a complete software-configurable
solution to the BORSCHT functions.
The Le58QL061/063 device supports the feature set of the Le58QL02/021/031 device and provides a General
Circuit Interface as a programmable mode.
Related Literature
•
•
•
080753 Le58QL02/021/031 QLSLAC™ Data Sheet
080761 QSLAC™ to QLSLAC™ Design Conversion Guide
080758 QSLAC™ to QLSLAC™ Guide to New Designs
Revision History
Below are the changes from the September 2007 version to the June 2011 version.
Page
Item
Description
1
Ordering Information
Obsoleted Le58QL061FJC package.
32
9.1, “GCI Timing
Specifications“
Corrected t Data Setup Min. to 20.
sD
2
Zarlink Semiconductor Inc.
Le58QL061/063
Data Sheet
Table of Contents
1.0 Product Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.0 Block Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Clock and Reference Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Microprocessor Interface (MPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Time Slot Assigner (TSA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 Signal Processing Channels (CHx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.5 SLIC Device Interface (SLI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.0 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.0 Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.0 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1 Package Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.0 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.1 Environmental Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.2 Electrical Ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.0 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.1 Transmission Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.2 Attenuation Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.3 Group Delay Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.4 Gain Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.5 Total Distortion Including Quantizing Distortion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.6 Discrimination Against Out-of-Band Input Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.7 Discrimination Against 12- and 16-kHz Metering Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.8 Spurious Out-of-Band Signals at the Analog Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.9 Overload Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8.0 Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9.0 Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9.1 GCI Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.2 GCI Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
10.0 OPERATING THE QLSLAC DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
10.1 Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
10.2 PCM and GCI State Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
10.3 Channel Enable (EC) Register (PCM/MPI Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
10.4 SLIC Device Control and Data Lines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
10.5 Clock Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
10.6 E1 Multiplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
10.7 Debounce Filters Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
10.8 Real-Time Data Register Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10.9 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10.10 Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10.11 Active State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10.12 Inactive State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10.13 Chopper Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
10.14 Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
11.0 Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
11.1 Overview of Digital Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
11.2 Two-Wire Impedance Matching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
11.3 Frequency Response Correction and Equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
11.4 Transhybrid Balancing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
11.5 Gain Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
11.6 Transmit Signal Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
11.7 Transmit PCM Interface (PCM/MPI Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3
Zarlink Semiconductor Inc.
Le58QL061/063
Data Sheet
Table of Contents
11.8 Data Upstream Interface (GCI Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
11.9 Receive Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
11.10 Receive PCM Interface (PCM/MPI Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
11.11 Data Downstream Interface (GCI Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
11.12 Analog Impedance Scaling Network (AISN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
11.13 Speech Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
11.14 Double PCLK (DPCK) Operation (PCM/MPI Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
11.15 Signaling on the PCM Highway (PCM/MPI Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
11.16 Robbed-Bit Signaling Compatibility (PCM/MPI Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
11.17 Default Filter Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
12.0 Command Description and Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
12.1 Command Field Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
12.2 Microprocessor Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
13.0 Summary of MPI Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
14.0 MPI Command Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
14.1 00h Deactivate (Standby State). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
14.2 02h Software Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
14.3 04h Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
14.4 06h No Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
14.5 0Eh Activate Channel (Operational State). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
14.6 40/41h Write/Read Transmit Time Slot and PCM Highway Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . 56
14.7 42/43h Write/Read Receive Time Slot and PCM Highway Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
14.8 44/45h Write/Read Transmit Clock Slot, Receive Clock Slot, and Transmit Clock Edge . . . . . . . . . . . . 57
14.9 46/47h Write/Read Chip Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
14.10 4A/4Bh Write/Read Channel Enable and Operating Mode Register. . . . . . . . . . . . . . . . . . . . . . . . . . . 58
14.11 4D/4Fh Read Real-Time Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
14.12 50/51h Write/Read AISN and Analog Gains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
14.13 52/53h Write/Read SLIC Device Input/Output Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
14.14 54/55h Write/Read SLIC Device Input/Output Direction, Read Status Bits. . . . . . . . . . . . . . . . . . . . . . 60
14.15 60/61h Write/Read Operating Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
14.16 6C/6Dh Write/Read Interrupt Mask Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
14.17 70/71h Write/Read Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
14.18 73h Read Revision Code Number (RCN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
14.19 80/81h Write/Read GX Filter Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
14.20 82/83h Write/Read GR Filter Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
14.21 84/85h Write/Read Z Filter Coefficients (FIR and IIR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
14.22 86/87h Write/Read B1 Filter Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
14.23 88/89h Write/Read X Filter Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
14.24 8A/8Bh Write/Read R Filter Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
14.25 96/97h Write/Read B2 Filter Coefficients (IIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
14.26 98/99h Write/Read FIR Z Filter Coefficients (FIR only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
14.27 9A/9Bh Write/Read IIR Z Filter Coefficients (IIR only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
14.28 C8/C9h Write/Read Debounce Time Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
14.29 CDh Read Transmit PCM Data (PCM/MPI Mode Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
14.30 E8/E9h Write/Read Ground Key Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
15.0 General Circuit Interface (GCI) Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
15.1 GCI General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
15.2 GCI Format and Command Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
15.3 Signaling and Control (SC) Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
15.4 Monitor Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
15.5 Programming with the Monitor Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
15.6 Channel Identification Command (CIC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
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Zarlink Semiconductor Inc.
Le58QL061/063
Data Sheet
Table of Contents
15.7 General Structure of Other Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
16.0 Summary of Monitor Channel Commands (GCI Commands) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
16.1 TOP (Transfer Operation) Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
16.2 SOP (Status Operation) Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
16.3 SOP Control Byte Command Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
16.4 COP (Coefficient Operation) Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
16.5 Details of COP, CSD Data Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
17.0 Programmable Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
17.1 User Test States and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
17.2 A-Law and µ-Law Companding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
18.0 APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
19.0 Application Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
20.0 Line Card Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
21.0 Physical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
21.1 44-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
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Zarlink Semiconductor Inc.
Le58QL061/063
Data Sheet
List of Figures
Figure 1 - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - Transmit Path Attenuation vs. Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 3 - Receive Path Attenuation vs. Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 4 - Group Delay Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 5 - A-law Gain Linearity with Tone Input (Both Paths) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 6 - µ-law Gain Linearity with Tone Input (Both Paths). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 7 - Total Distortion with Tone Input (Both Paths). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 8 - Discrimination Against Out-of-Band Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 9 - Spurious Out-of-Band Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 10 - Analog-to-Analog Overload Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 11 - Input and Output Waveforms for AC Tests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 12 - Microprocessor Interface (Input Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 13 - Microprocessor Interface (Output Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 14 - PCM Highway Timing for XE = 0 (Transmit on Negative PCLK Edge) . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 15 - PCM Highway Timing for XE = 1 (Transmit on Positive PCLK Edge) . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 16 - Double PCLK PCM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 17 - Master Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 18 - 4.096 MHz DCL Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 19 - 2.048 MHz DCL Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 20 - Clock Mode Options (PCM/MPI Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 21 - SLIC Device I/O, E1 Multiplex and Real-Time Data Register Operation . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 22 - E1 Multiplex Internal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 23 - MPI Real-Time Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 24 - QLSLAC Device Transmission Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 25 - Robbed-Bit Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 26 - Time Slot Control and GCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 27 - Multiplexed GCI Time Slot Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 28 - Security Procedure for C/I Downstream Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 29 - Maximum Speed Monitor Handshake Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 30 - Monitor Transmitter Mode Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 31 - Monitor Receiver State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 32 - Le7920 SLIC/QLSLAC Device Application Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
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Zarlink Semiconductor Inc.
Le58QL061/063
Data Sheet
List of Tables
Table 1 - QLSLAC Device Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2 - 0 dBm0 Voltage Definitions with Unity Gain in X, R, GX, GR, AX and AR . . . . . . . . . . . . . . . . . . . . . . . 18
Table 3 - PCM/GCI Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 4 - Channel Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 5 - Channel Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 6 - Global Chip Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 7 - Global Chip Status Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 8 - GCI Channel Assignment Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 9 - Generic Byte Transmission Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 10 - Byte Transmission Sequence for TOP Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 11 - General Transmission Sequence of SOP Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 12 - Generic Transmission Sequence for COP Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 13 - A-Law: Positive Input Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 14 - µ-Law: Positive Input Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
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Zarlink Semiconductor Inc.
Le58QL061/063
Data Sheet
1.0 Product Description
The QLSLAC device performs the codec/filter and two-to-four-wire conversion functions required of the subscriber
line interface circuitry in telecommunications equipment. These functions involve converting audio signals into
digital PCM samples and converting digital PCM samples back into audio signals. During conversion, digital filters
are used to band limit the voice signals. All of the digital filtering is performed in digital signal processors operating
from a master clock, which can be derived either from PCLK or MCLK in the PCM/MPI mode and DCL in the GCI
mode.
Four independent channels allow the QLSLAC device to function as four SLAC™ devices. In PCM/MPI mode, each
channel has its own enable bit (EC1, EC2, EC3, and EC4) to allow individual channel programming. If more than
one Channel Enable bit is High or if all Channel Enable bits are High, all channels enabled will receive the
programming information written; therefore, a Broadcast mode can be implemented by simply enabling all channels
in the device to receive the information. The Channel Enable bits are contained in the Channel Enable (EC)
register, which is written and read using Commands 4A/4Bh. The Broadcast mode is useful in initializing QLSLAC
devices in a large system.
In GCI mode, one GCI channel controls two channels of the QLSLAC device. The Monitor channel and SC channel
within the GCI channel are used to read/write filter coefficient data, read/write operating conditions and to read/write
data to/from the programmable I/O ports of the two channels. Two consecutive GCI channels control all four
channels of the QLSLAC device. The two GCI channels used, of the eight total available, are determined by S0 and
S1 inputs.
The user-programmable filters set the receive and transmit gain, perform the transhybrid balancing function, permit
adjustment of the two-wire termination impedance, and provide equalization of the receive and transmit paths. All
programmable digital filter coefficients can be calculated using the WinSLAC™ device software.
In PCM/MPI mode, Data transmitted or received on the PCM highway can be 8-bit companded code (with an
optional 8-bit signaling byte in the transmit direction) or 16-bit linear code. The 8-bit codes appear 1 byte per time
slot, while the 16-bit code appears in two consecutive time slots. The compressed PCM codes can be either 8-bit
companded A-law or µ-law. The PCM data is read from and written to the PCM highway in user-programmable time
slots at rates of 128 kHz to 8.192 MHz. The transmit clock edge and clock slot can be selected for compatibility with
other devices that can be connected to the PCM highway.
In GCI mode, two 8-bit companded codes are received or transmitted per GCI channel. The compressed PCM
codes can be either 8-bit companded A-law or µ-law. There is no Signaling or Linear mode available when GCI
mode is selected.
Table 1 lists the features available for each device.
Programmable I/O
Part Number
Le58QL061BVC
Le58QL063HVC
PCM/GCI Highway
Single/Single
Chopper Clock
Package
44-Pin TQFP
64-Pin LQFP
per Channel
Five I/O
No
Five I/O
Two Output
Dual/Single
Yes
Table 1 - QLSLAC Device Features
2.0 Block Descriptions
2.1 Clock and Reference Circuits
This block generates a master clock and a frame sync signal for the digital circuits. It also generates an analog
reference voltage for the analog circuits.
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Zarlink Semiconductor Inc.
Le58QL061/063
Data Sheet
2.2 Microprocessor Interface (MPI)
This block communicates with the external control microprocessor over a serial interface. It passes user control
information to the other blocks, and it passes status information from the blocks to the user. In addition, this block
contains the reset circuitry. When GCI is selected, this block is combined with the TSA block.
2.3 Time Slot Assigner (TSA)
This block communicates with the PCM highway, where the PCM highway is a time division mutiplexed bus
carrying the digitized voice samples. The block implements programmable time slots and clocking arrangements in
order to achieve a first layer of switching. Internally, this block communicates with the Signal Processing Channels
(CHx). When GCI is selected, this block is combined with the TSA block.
2.4 Signal Processing Channels (CHx)
These blocks do the transmission processing for the voice channels. Part of the processing is analog and is
interfaced to the VIN and VOUT pins. The remainder of the processing is digital and is interfaced to the Time Slot
Assigner (TSA) block.
2.5 SLIC Device Interface (SLI)
This block communicates digitally with the SLIC device circuits. It sends control bits to the SLIC devices to control
modes and to operate LEDs and optocouplers. It also accepts supervision information from the SLIC devices and
performs some filtering.
3.0 Connection Diagrams
44 43 42 41 40 39 38 37 36 35 34
1
33
32
31
30
29
28
27
26
25
24
23
VOUT1
VIN1
CS/PG
DCLK/S0
DIO/S1
TSCA
2
3
VOUT2
VIN2
4
5
VCCA
VREF
AGND
VIN3
DGND
PCLK/DCL
VCCD
Le58QL061BVC
44-Pin TQFP
6
7
8
DXA/DU
FS/FSC
RST
9
VOUT3
VIN4
10
11
VOUT4
INT
12 13 14 15 16 17 18 19 20 21 22
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Zarlink Semiconductor Inc.
Le58QL061/063
Data Sheet
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VOUT1
1
48
47
46
45
44
43
42
41
CS/PG
DCLK/S0
DIO/S1
TSCA
VIN1
RSVD
VOUT2
VIN2
2
3
4
TSCB
5
DGND
DGND
PCLK/DCL
RSVD
RSVD
VCCA
VCCA
VREF
AGND
AGND
VIN3
6
7
Le58QL063HVC
64-Pin LQFP
8
40
9
VCCD
39
38
10
11
12
13
14
15
16
VCCD
37
36
35
34
33
DXA/DU
DXB
VOUT3
RSVD
VIN4
FS/FSC
RST
INT
VOUT4
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Notes:
1. NC= No connect. Pins 3 and 14 on the Le58QL063HVC device should be grounded if the inputs to VIN1 and VIN4 have an impedance larger
than 300 Ω.
2. Pins of same name on the Le58QL063HVC device are internally connected (AGND, pins 10, 11; VCCA, pins 7, 8; VCCD, pins 38, 39; DGND,
pins 42, 43).
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Zarlink Semiconductor Inc.
Le58QL061/063
Data Sheet
4.0 Pin Descriptions
Pin Names
Type
Power
Description
Separate analog and digital grounds are provided to allow noise isolation; however, the two grounds
are connected inside the part, and the grounds must also be connected together on the circuit board.
AGND, DGND
Control and Data. CD1 and CD2 are TTL compatible programmable Input or Output (I/O) ports. They
can be used to monitor or control the state of SLIC device or any other device associated with the
subscriber line interface. The direction, input or output, is programmed using MPI Command 54/55h
or GCI Command SOP 8. As outputs, CD1 and CD2 can be used to control relays, illuminate LEDs,
or perform any other function requiring a latched TTL compatible signal for control. In PCM/MPI mode,
the output state of CD1 and CD2 is written using MPI Command 52h. In GCI mode, the output state
of CD1 and CD2 is determined by the C1 and C2 bits contained in the down stream C/I channel for
the respective channel. As inputs, CD1 and CD2 can be processed by the QLSLAC device (if
programmed to do so). CD1 can be debounced before it is made available to the system. The
debounce time is programmable from 0 to 15 ms in 1 ms increments using MPI Command C8/C9h
and GCI Command SOP 11. CD2 can be filtered using the up/down counter facility and programming
the sampling interval using MPI Command E8/E9h or GCI Command SOP 12.
Additionally, CD1 can be demultiplexed into two separate inputs using the E1 demultiplexing function.
The E1 demultiplexing function of the QLSLAC device was designed to interface directly to Zarlink
SLIC devices supporting the ground key function. With the proper Zarlink SLIC device and the E1
function of the QLSLAC device enabled, the CD1 bit can be demultiplexed into an Off-Hook/Ring Trip
signal and Ground Key signal. In the demultiplex mode, the second bit, Ground Key, takes the place
of the CD2 as an input. The demultiplexed bits can be debounced (CD1) or filtered (CD2) as explained
previously. A more complete description of CD1, CD2, debouncing, and filtering functions is contained
in the Operating the QLSLAC Device section on page 35.
CD11–CD14,
CD21–CD24
Inputs/Outputs
Once the CD1 and CD2 inputs are processed (Debounced, Filtered and/or Demultiplexed) by the
QLSLAC device, the information can be accessed by the system in two ways in the PCM/MPI mode:
1) on a per channel basis along with C3, C4, and C5 of the specific channel using MPI Command 53h,
or 2) by using MPI Command 4D/4Fh, which obtain the CD1 and CD2 bits from all four channels
simultaneously. This feature reduces the processor overhead and the time required to retrieve time-
critical signals from the line circuits, such as off-hook and ring trip. With this feature, hookswitch status
and ring trip information, for example, can be obtained from all four channels of a QLSLAC device with
one read command.
In the GCI mode, the processed CD1 and CD2 inputs are transmitted upstream on the CD1 and CD2
bits for the respective analog channel, 1 or 2, using the C/I channel.
Control. C3, C4, and C5 are TTL-compatible programmable Input or Output (I/O) ports. They can be
used to monitor or control the state of the SLIC device or any other device associated with subscriber
line interface. The direction, input or output, is programmed using MPI Command 54/55h or GCI
Command SOP 8. As outputs, C3, C4, and C5 can be used to control relays, illuminate LEDs, or
perform any other function requiring a latched TTL compatible signal for control. In PCM/MPI mode,
the output state of C3, C4, and C5 is written using MPI Command 52h. In GCI mode, the output state
of C3, C4, and C5 is determined by the C3, C4, and C5 bits contained in the down stream C/I channel
for the respective analog channel. As inputs, C3, C4, and C5 can be accessed by the system in
PCM/MPI mode by using MPI Command 53h. In GCI mode, C3 is transmitted upstream, along with
CD1 and CD2, for the respective analog channel using C3 of the C/I channel. Also, in GCI mode, C3,
C4, and C5 can be read along with CD1 and CD2 using GCI Command SOP 10.
C31–C34,
C41–C44,
C51–C54
Inputs/Outputs
The Le58QL061 QLSLAC device contains a single PCM highway or GCI Interface and five
programmable I/Os per channel (CD1, CD2, C3, C4, and C5) in a TQFP package.
C61–C64,
C71–C74
Outputs
Output
Control. Two additional outputs per channel are available on the Le58QL063HVC device.
Chopper Clock. This output provides a 256 kHz or a 292.57 kHz, 50% duty cycle, TTL-compatible
clock for use by up to four SLIC devices with built-in switching regulators. The CHCLK frequency is
synchronous to the master clock, but the phase relationship to the master clock is random. The
chopper clock is not available in all package types.
CHCLK
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Zarlink Semiconductor Inc.
Le58QL061/063
Data Sheet
Pin Names
Type
Description
Chip Select/PCM-GCI. The CS/PG input along with the DCLK/S0 input are used to determine the
operating state of the programmable PCM/GCI interface. On power up, the QLSLAC device will
initialize to GCI mode if CS/PG is low and there is no toggling (no high to low or low to high transitions)
of the DCLK/S0 input. The device will initialize to the PCM/MPI mode if either CS is high or DCLK is
toggling.
Once the device is in PCM/MPI mode, it is ready to receive commands through its serial interface pins,
DIO and DCLK. Once a valid command has been sent through the MPI serial interface, GCI mode
cannot be entered unless a hardware reset is asserted or power is removed from the part. If a valid
command has not been sent since the last hardware reset or power up, then GCI mode can be re-
entered (after a delay of one PCM frame) by holding CS/PG low and keeping DCLK static. While the
part is in GCI mode, then CS/PG going high or DCLK toggling will immediately place the device in
PCM/MPI mode.
CS/PG
Input
In the PCM/MPI mode, the Chip Select input (active Low) enables the device so that control data can
be written to or read from the part. The channels selected for the write or read operation are enabled
by writing 1s to the appropriate bits in the Channel Enable Register of the QLSLAC device prior to the
command. See EC1, EC2, EC3, and EC4 of the Channel Enable Register and Command 4A/4Bh for
more information. If Chip Select is held Low for 16 rising edges of DCLK, a hardware reset is executed
when Chip Select returns High.
Data Clock. In addition to providing both a data clock input and an S0 GCI address input, DCLK/S0
acts in conjunction with CS/PG to determine the operational mode of the system interface, PCM/MPI
or GCI. See CS/PG for details.
Input
Input
In the PCM/MPI mode, the Data Clock input shifts data into and out of the microprocessor interface of
the QLSLAC device. The maximum clock rate is 8.192 MHz.
DCLK/S0
DIO/S1
Select Bit 0. In GCI mode, S0 is one of two inputs (S0, S1) that is decoded to determine on which GCI
channels the QLSLAC device transmit and receives data.
Data Input/Output. In the PCM/MPI mode, control data is serially written into and read out of the
QLSLAC device via the DIO pin, most significant bit first. The Data Clock determines the data rate.
DIO is high impedance except when data is being transmitted from the QLSLAC device.
Input/Output
Input
Select Bit 1. In GCI mode, S1 is the second of two inputs (S0, S1) that is decoded to determine on
which GCI channels the QLSLAC device transmits and receives data.
PCM Data Receive (A/B). In the PCM/MPI mode, the PCM data for channels 1, 2, 3, and 4 is serially
received on either the DRA or DRB port during user-programmed time slots. Data is always received
with the most significant bit first. For compressed signals, 1 byte of data for each channel is received
every 125 µs at the PCLK rate. In the Linear mode, 2 consecutive bytes of data for each channel are
received every 125 µs at the PCLK rate. DRB is not available on all package types.
Inputs
Input
DRA/DD,
DRB
GCI Data Downstream. In GCI mode, the B1, B2, Monitor and SC channel data is serially received on
the Data Downstream input for all four channels of the QLSLAC device. The QLSLAC device requires
two of the eight GCI channels for operation. The two GCI Channels, out of the eight possible, are
determined by the S0 and S1 inputs. Data is always received with the most significant bit first. 4 bytes
of data for each GCI channel is received every 125 µs at the 2.048 Mbit/s data rate.
PCM Data Transmit. In the PCM/MPI mode, the transmit data from channels 1, 2, 3, and 4 is sent
serially out on either the DXA or DXB port or on both ports during user-programmed time slots. Data
is always transmitted with the most significant bit first. The output is available every 125 µs and the
data is shifted out in 8-bit (16-bit in Linear or PCM Signaling mode) bursts at the PCLK rate. DXA and
DXB are High impedance between time slots, while the device is in the Inactive mode with no PCM
signaling, or while the Cutoff Transmit Path bit (CTP) is on. DXB is not available on all package types.
Outputs
Output
DXA/DU, DXB
GCI Data Upstream. In the GCI mode, the B1, B2, Monitor and SC channel data is serially transmitted
on the Data Upstream output for all four channels of the QLSLAC device. Which GCI channels the
device uses is determined by the S0 and S1 inputs. Data is always transmitted with the most significant
bit first. 4 bytes of data for each GCI channel is transmitted every 125 µs at the DCL rate.
Frame Sync. In the PCM/MPI mode, the Frame Sync (FS) pulse is an 8 kHz signal that identifies Time
Slot 0 and Clock Slot 0 of a system’s PCM frame. The QLSLAC device references individual time slots
with respect to this input, which must be synchronized to PCLK.
Input
Input
FS/FSC
Frame Sync. In GCI mode, the Frame Sync (FSC) pulse is an 8 kHz signal that identifies the beginning
of GCI channel 0 of a system’s GCI frame. The QLSLAC device references individual GCI channels
with respect to this input, which must be synchronized to DCL.
12
Zarlink Semiconductor Inc.
Le58QL061/063
Data Sheet
Pin Names
Type
Description
Interrupt. INT is an active Low output signal, which is programmable as either TTL-compatible or open
drain. The INT output goes Low any time one of the input bits in the Real Time Data register changes
state and is not masked. It also goes Low any time new transmit data appears if this interrupt is armed.
INT remains Low until the appropriate register is read via the microprocessor interface, or the QLSLAC
device receives either a software or hardware reset. The individual CDxC bits in the Real Time Data
INT
Output
register can be masked from causing an interrupt by using MPI Command 6C/6Dh or GCI Command
SOP 14. The transmit data interrupt must be armed with a bit in the Operating Conditions Register.
Master Clock/Enable CD1 Multiplex. In PCM/MPI mode only, the Master Clock can be a 1.536 MHz,
1.544 MHz, or 2.048 MHz (times 1, 2, or 4) clock for use by the digital signal processor. If the internal
clock is derived from the PCM Clock Input (PCLK) or if GCI mode is selected, this pin can be used as
an E1 output to control Zarlink SLIC devices having multiplexed hook switch and ground key detector
outputs.
MCLK/E1
NC
Input/Output
—
No connect. This pin is not internally connected.
PCM Clock. In the PCM/MPI mode, the PCM clock determines the rate at which PCM data is serially
shifted into or out of the PCM ports. PCLK is an integer multiple of the frame sync frequency. The
maximum clock frequency is 8.192 MHz and the minimum clock frequency is 128 kHz for dual PCM
highway versions and 256 kHz for single PCM highway versions. The minimum clock rate must be
doubled if Linear mode or PCM signaling is used. PCLK frequencies between 1.03 MHz and 1.53 MHz
are not allowed. Optionally, the digital signal processor clock can be derived from PCLK rather than
MCLK. In PCM/MPI mode, PCLK can be operated at twice the PCM data rate in the Double PCLK
mode (bit 1 of PCM/MPI Command C8/C9h).
Input
PCLK/DCL
GCI Data Clock. In GCI mode, DCL is either 2.048 MHz or 4.096 MHz, which is an integer multiple of
the frame sync frequency. Circuitry internal to the QLSLAC device monitors this input to determine
which frequency is being used, 2.048 MHz or 4.096 MHz. When 4.096 MHz clock operation is
detected, internal timing is adjusted so that DU and DD operate at the 2.048 Mbit/s rate.
Input
Input
Reset. A logic Low signal at this pin resets the QLSLAC device to its default state.
RST
Time Slot Control. The Time Slot Control outputs are open-drain outputs (requiring pull-up resistors to
VCCD) and are normally inactive (high impedance). In the PCM/MPI mode, TSCA or TSCB is active
(low) when PCM data is transmitted on the DXA or DXB pin, respectively. In GCI mode, TSCA is active
(low) during the two GCI time slots selected by the S1 and S0. TSCB is not available on all package
types.
TSCA, TSCB
Outputs
Power
Analog and digital power supply inputs. VCCA and VCCD are provided to allow for noise isolation and
proper power supply decoupling techniques. For best performance, all of the VCC power supply pins
should be connected together at the connector of the printed circuit board.
VCCA, VCCD
VIN1–VIN4
Analog Input. The analog voice band signal is applied to the VIN input of the QLSLAC device. The VIN
input is biased at VREF by a large internal resistor. The audio signal is sampled, digitally processed
and encoded, and then made available at the TTL-compatible PCM output (DXA or DXB) or in the B1
and B2 of the GCI channel. If the digitizer saturates in the positive or negative direction, VIN is pulled
by a reduced resistance toward AGND or VCCD, respectively. VIN1 is the input for channel 1, VIN2 is
Inputs
the input for channel 2, VIN3 is the input for channel 3, and VIN4 is the input for channel 4.
Analog Output. The received digital data at DRA/DRB or DD (GCI mode) is processed and converted
to an analog signal at the VOUT pin. VOUT1 is the output from channel 1, VOUT2 is the output for
VOUT1–
VOUT4
Outputs
Output
channel 2, VOUT3 is the output from channel 3, and VOUT4 is the output for channel 4. The VOUT
voltages are referenced to VREF.
Analog Voltage Reference. The VREF output is provided in order for an external capacitor to be
connected from VREF to ground, filtering noise present on the internal voltage reference. VREF is
buffered before it is used by internal circuitry. The voltage on VREF and the output resistance are
given in “Electrical Characteristics” on page 16. The leakage current in the capacitor must be low.
VREF
13
Zarlink Semiconductor Inc.
Le58QL061/063
Data Sheet
5.0 Absolute Maximum Ratings
Stresses above those listed under "Absolute Maximum Ratings" can cause permanent device failure. Functionality
at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods can affect
device reliability.
–60° C < T < +125° C
Storage Temperature
A
–40° C < T < +85° C
Ambient Temperature, under Bias
Ambient relative humidity (non condensing)
A
5 to 95%
V
V
V
V
with respect to AGND
with respect to VCCD
with respect to DGND
–0.4 to + 4.0 V
±0.4 V
CCA
CCA
CCD
–0.4 to + 4.0 V
with respect to AGND
–0.4 V to (V
±50 mV
+ 0.4 V)
CCA
IN
AGND with respect to DGND
Digital pins with respect to DGND
Total combined CD1–C7 current per device:
Source from VCCD
–0.4 to 5.5 V or VCCD + 2.37 V, whichever is smaller
40 mA
Sink into DGND
40 mA
Latch up immunity (any pin)
± 100 mA
Total VCC current if rise rate of VCC > 0.4 V/µs 0.5 A
5.1 Package Assembly
The green package devices are assembled with enhanced environmental compatible lead (Pb), halogen, and
antimony-free materials. The leads possess a matte-tin plating which is compatible with conventional board
assembly processes or newer lead-free board assembly processes.
Refer to IPC/JEDEC J-Std-020 Table 4-2 for recommended peak soldering temperature and Table 5-2 for the
recommended solder reflow temperature profile.
14
Zarlink Semiconductor Inc.
Le58QL061/063
Data Sheet
6.0 Operating Ranges
Zarlink guarantees the performance of this device over commercial (0 to 70º C) and industrial (-40 to 85ºC)
temperature ranges by conducting electrical characterization over each range and by conducting a production test
with single insertion coupled to periodic sampling. These characterization and test procedures comply with section
4.6.2 of Bellcore GR-357-CORE Component Reliability Assurance Requirements for Telecommunications
Equipment.
6.1 Environmental Ranges
−40° C < T < +85° C
Ambient Temperature
A
Ambient Relative Humidity
15 to 85%
6.2 Electrical Ranges
+3.3 V ± 5%
Analog Supply V
Digital Supply V
CCA
V
± 50 mV
CCD
+3.3 V ± 5%
0 V
CCD
DGND
AGND
±10 mV
CFIL Capacitance: VREF to AGND
Digital Pins
0.1 µF ± 20%
DGND to +5.25 V
15
Zarlink Semiconductor Inc.
Le58QL061/063
Data Sheet
7.0 Electrical Characteristics
Typical values are for TA = 25º C and nominal supply voltages. Minimum and maximum values are over the
temperature and supply voltage ranges shown in Operating Ranges, except where noted.
Symbol
Parameter Descriptions
Digital Input Low voltage
Min.
Typ.
Max.
Unit
Note
VIL
0.8
V
VIH
Digital Input High voltage
2.0
Digital Input leakage current
0 < V < VCCD
–7
+7
IIL
µA
V
Otherwise
–120
0.16
+180
0.34
VHYS
Digital Input hysteresis
0.25
Digital Output Low voltage
CD1–C7 (IOL = 4 mA)
0.4
0.8
0.4
0.4
CD1–C7 (IOL = 8 mA)
VOL
V
V
1
1
TSCA/ TSCB (IOL =14 mA)
Other digital outputs (IOL = 2 mA)
Digital Output High voltage
CD1–C7 (IOH = 4 mA)
VCCD – 0.4 V
VCCD – 0.8 V
2.4
VOH
CD1–C7 (IOH = 8 mA)
Other digital outputs (IOH = 400 µA)
Digital Output leakage current (Hi-Z state)
0 < V < VCCD
–7
+7
IOL
µA
Otherwise
–120
+180
Input attenuator gain
DGIN = 0
GIN
0.6438
1
V/V
DGIN = 1
Analog input voltage range (Relative to VREF)
AX = 0 dB, attenuator on (DGIN = 0)
±1.584
±0.792
±1.02
VIR
AX = 6.02 dB, attenuator on (DGIN = 0)
AX = 0 dB, attenuator off (DGIN = 1)
Vpk
AX = 6.02 dB, attenuator off (DGIN = 1)
±0.51
VIOS
ZIN
Offset voltage allowed on VIN
–50
600
50
50
1400
115
130
10
mV
Analog input impedance to VREF, 300 to 3400 Hz
Current into analog input for an input voltage of 3.3 V
Current out of analog input for an input voltage of –0.3 V
VOUT output impedance
kΩ
IIP
2
2
µA
IIN
50
ZOUT
CLOUT
IOUT
VREF
ZREF
1
Ω
pF
Allowable capacitance, VOUT to AGND
500
4
–4
1.43
70
mApk
V
3
VOUT output current (F< 3400 Hz)
VREF output open circuit voltage (leakage < 20 nA)
VREF output impedance (F <3400 Hz)
1.5
1.57
130
kΩ
VOUT analog output voltage range (Relative to VREF)
±1.02
±0.51
VOR
AR = 0 dB
AR = −6.02 dB
Vpk
mV
VOOS
VOUT offset voltage (AISN off)
VOUT offset voltage (AISN on)
–40
–80
40
80
4
VOOSA
16
Zarlink Semiconductor Inc.
Le58QL061/063
Data Sheet
Symbol
Parameter Descriptions
Min.
Typ.
Max.
Unit
Note
AISN gain - expected gain (input = 0 dBm0, 1014 Hz)
Attenuator on (DGIN = 0)
GAISN
–0.016
–0.024
0.016
0.024
V/V
mW
Attenuator off (DGIN = 1)
Power dissipation
All channels active
1 channel active
130
40
170
80
PD
All channels inactive
13
18
CI
Digital Input capacitance
Digital Output capacitance
4
4
pF
dB
CO
Power supply rejection ratio (1.02 kHz, 100 mVRMS, either
path, GX = GR = 0 dB)
PSRR
40
Notes:
1. The CD1, CD2, C3–C7 outputs are resistive for less than a 0.8 V drop. Total current must not exceed absolute maximum ratings.
2. When the digitizer saturates, a resistor of 50 kΩ ± 20 kΩ is connected either to AGND or to VCCA as appropriate to discharge the coupling
capacitor.
3. When the QLSLAC device is in the Inactive state, the analog output will present either a VREF DC output level through a 15 kΩ resistor
(VMODE = 0) or a high impedance (VMODE = 1).
4. If there is an external DC path from VOUT to VIN with a gain of GDC and the AISN has a gain of hAISN, then the output offset will be multiplied
by 1 / [1 – (hAISN • GDC)].
5. Power dissipation in the Inactive state is measured with all digital inputs at VIH = VCCD and VIL = DGND and with no load connected to
VOUT1, VOUT2, VOUT3, or VOUT4.
17
Zarlink Semiconductor Inc.
Le58QL061/063
Data Sheet
7.1 Transmission Characteristics
Transmit
Transmit
Signal at Digital Interface
A-law digital mW or equivalent (0 dBm0)
µ-law digital mW or equivalent (0 dBm0)
±22,827 peak linear coded sine wave
(DGIN = 0)
(DGIN = 1)
Receive
0.5024
0.4987
0.5024
Unit
0.7804
0.7746
0.7804
0.5024
0.4987
Vrms
0.5024
Table 2 - 0 dBm0 Voltage Definitions with Unity Gain in X, R, GX, GR, AX and AR
When relative levels (dBm0) are used in any of the following transmission specifications, the specification holds for
any setting of the GX gain from 0 dB to 12 dB, the GR loss from 0 dB to 12 dB, and the input attenuator (GIN) on or
off.
Description
Test Conditions
0 dBm0, 1014 Hz
Min.
Typ.
Max.
Unit
Note
AX = AR = 0 dB
0 to 85° C
–0.25
–0.30
+0.25
+0.30
–40° C
Gain accuracy, D/A or A/D
AX = +6.02 dB and/or
AR = –6.02 dB
0 to 85° C
–0.30
–0.40
+0.30
+0.40
–40° C
dB
Gain accuracy digital-to-digital
Gain accuracy analog-to-analog
–0.25
–0.25
+0.25
+0.25
–
Attenuation distortion
300 Hz to 3 kHz
+0.125
1
2
0.125
Single frequency distortion
–46
–55
Second harmonic distortion, D/A
GR = 0 dB
Idle channel noise
Analog out
Digital looped backweighted
unweighted
Digital input = 0 A-law
Digital input = 0 µ-law
Analog VIN = 0 VACA-law
–68
–55
–78
12
–68
16
dBm0p
dBm0
dBm0p
dBrnc0
dBm0p
dBrnc0
3
3
3
3, 6
3
3, 6
0
0
Digital out
Analog VIN = 0 VAC µ-law
Crosstalk TX to RX
same channel RX to TX
0 dBm0
0 dBm0
300 to 3400 Hz
300 to 3400 Hz
–75
–75
dBm0
0 dBm0
SLIC imped. <300 Ω (Le58QL061),
<5000 Ω (Le58QL063)
1014 Hz, Average
Crosstalk between channels
dBm0
µs
4
5
TX or RX to TX
TX or RX to RX
–76
–78
1014 Hz, Average
End-to-end group delay
B = Z = 0; X = R = 1
678
Notes:
1. See Figure 2 and Figure 3.
2. 0 dBm0 input signal, 300 Hz to 3400 Hz; measurement at any other frequency, 300 Hz to 3400 Hz.
3. No single frequency component in the range above 3800 Hz may exceed a level of –55 dBm0.
4. The weighted average of the crosstalk is defined by the following equation, where C(f) is the crosstalk in dB as a function of frequency, fN
=
18
Zarlink Semiconductor Inc.
Le58QL061/063
Data Sheet
3300 Hz, f1 = 300 Hz, and the frequency points (fj, j = 2..N) are closely spaced:
1
1
------
------
• C(fj)
• C(fj – 1)
1020
+ 1020
fj
⎛
⎜
⎝
⎞
⎟
⎠
---------------------------------------------------------------
---------
• log
∑
2
fj – 1
j
---------------------------------------------------------------------------------------------------------
Average = 20 • log
f
⎛
⎜
⎝
⎞
⎟
⎠
N
----
log
f1
5. The End-to-End Group Delay is the sum of the transmit and receive group delays (both measured using the same time and clock slot).
6. Typical values not tested in production.
7.2 Attenuation Distortion
The signal attenuation in either path is nominally independent of the frequency. The deviations from nominal
attenuation will stay within the limits shown in Figure 2 and Figure 3. The reference frequency is 1014 Hz and the
signal level is –10 dBm0.
1.8
0.75
0.125
Acceptable Region
Frequency (Hz)
0
0
-0.125
0
Figure 2 - Transmit Path Attenuation vs. Frequency
19
Zarlink Semiconductor Inc.
Le58QL061/063
Data Sheet
2
1
0.75
0.125
0
-0.125
Acceptable Region
Frequency (Hz)
0
0
Figure 3 - Receive Path Attenuation vs. Frequency
7.3 Group Delay Distortion
For either transmission path, the group delay distortion is within the limits shown in Figure 4. The minimum value of
the group delay is taken as the reference. The signal level should be 0 dBm0.
420
Delay (µS)
150
Acceptable
Region
90
0
Frequency (Hz)
Figure 4 - Group Delay Distortion
20
Zarlink Semiconductor Inc.
Le58QL061/063
Data Sheet
7.4 Gain Linearity
The gain deviation relative to the gain at –10 dBm0 is within the limits shown in Figure 5 (A-law) and Figure 6 (µ-
law) for either transmission path when the input is a sine wave signal of 1014 Hz.
1.5
0.55
0.25
Input
Level
Acceptable Region
Gain (dB)
0
-55 -50
-40
-10
0
+3
(dBm0)
-0.25
-0.55
-1.5
Figure 5 - A-law Gain Linearity with Tone Input (Both Paths)
1.4
0.45
0.25
Input
Level
(dBm0)
Acceptable Region
Gain (dB)
0
+3
-55 -50
-37
-10
0
-0.25
-0.45
-1.4
Figure 6 - µ-law Gain Linearity with Tone Input (Both Paths)
21
Zarlink Semiconductor Inc.
Le58QL061/063
Data Sheet
7.5 Total Distortion Including Quantizing Distortion
The signal to total distortion ratio will exceed the limits shown in Figure 7 for either path when the input signal is a
sine wave signal of frequency 1014 Hz.
Acceptable Region
B
A
A-Law
µ-Law
A
B
C
D
35.5dB 35.5dB
35.5dB 35.5dB
C
D
30dB
25dB
31dB
27dB
Signal-to-Total
Distortion (dB)
-45 -40
-30
0
Input Level (dBm0)
Figure 7 - Total Distortion with Tone Input (Both Paths)
7.6 Discrimination Against Out-of-Band Input Signals
When an out-of-band sine wave signal of frequency f, and level A is applied to the analog input, there may be
frequency components below 4 kHz at the digital output which are caused by the out-of-band signal. These
components are at least the specified dB level below the level of a signal at the same output originating from a
1014 Hz sine wave signal with a level of A dBm0 also applied to the analog input. The minimum specifications are
shown in the following table.
Frequency of Out-of-Band Signal
16.6 Hz < f < 45 Hz
Amplitude of Out-of-Band Signal
–25 dBm0 < A ≤ 0 dBm0
–25 dBm0 < A ≤ 0 dBm0
–25 dBm0 < A ≤ 0 dBm0
–25 dBm0 < A ≤ 0 dBm0
–25 dBm0 < A ≤ 0 dBm0
Level below A
18 dB
45 Hz < f < 65 Hz
25 dB
65 Hz < f < 100 Hz
10 dB
3400 Hz < f < 4600 Hz
4600 Hz < f < 100 kHz
see Figure 8
32 dB
22
Zarlink Semiconductor Inc.
Le58QL061/063
Data Sheet
0
-10
-20
Levelbelow
A(dB)
-28dB
-32dB
-30
-40
-50
3.4
4.0
4.6
Frequency(kHz)
Figure 8 - Discrimination Against Out-of-Band Signals
Note:
The attenuation of the waveform below amplitude A, between 3400 Hz and 4600 Hz, is given by the formula:
π(4000 – f)
⎛
⎝
⎞
⎠
----------------------------
Attenuation (db) = 14 – 14sin
1200
7.7 Discrimination Against 12- and 16-kHz Metering Signals
If the QLSLAC device is used in a metering application where 12 kHz or 16 kHz tone bursts are injected onto the
telephone line toward the subscriber, a portion of these tones also may appear at the VIN terminal. These
out-of-band signals may cause frequency components to appear below 4 kHz at the digital output. For a 12 kHz or
16 kHz tone, the frequency components below 4 kHz are reduced from the input by at least 70 dB. The sum of the
peak metering and signal voltages must be within the analog input voltage range.
7.8 Spurious Out-of-Band Signals at the Analog Output
With PCM code words representing a sine wave signal in the range of 300 Hz to 3400 Hz at a level of 0 dBm0
applied to the digital input, the level of the spurious out-of-band signals at the analog output is less than the limits
shown below.
Frequency
Level
4.6 kHz to 40 kHz
40 kHz to 240 kHz
240 kHz to 1 MHz
–32 dBm0
–46 dBm0
–36 dBm0
With code words representing any sine wave signal in the range 3.4 kHz to 4.0 kHz at a level of 0 dBm0 applied to
the digital input, the level of the signals at the analog output are below the limits in Figure 9. The amplitude of the
spurious out-of-band signals between 3400 Hz and 4600 Hz is given by the formula:
π(f – 4000)
⎛
⎝
⎞
⎠
----------------------------
Level = – 14 – 14sin
dBm0
1200
23
Zarlink Semiconductor Inc.
Le58QL061/063
Data Sheet
0
-10
Level (dBm0)
-20
-28 dBm0
-32 dBm0
-30
-40
-50
3.4
4.0
4.6
Frequency (kHz)
Figure 9 - Spurious Out-of-Band Signals
7.9 Overload Compression
Figure 10 shows the acceptable region of operation for input signal levels above the reference input power
(0 dBm0). The conditions for this figure are:
1. 1.2 dB < GX ≤ + 12 dB
2. –12 dB ≤ GR < –1.2 dB
3. Digital voice output connected to digital voice input.
4. Measurement analog-to-analog.
9
8
7
6
Fundamental
Output Power
Acceptable
5
(dBm0)
Region
4
3
2.6
2
1
7
8
9
1
2
3
4
5
6
Fundamental Input Power (dBm0)
Figure 10 - Analog-to-Analog Overload Compression
24
Zarlink Semiconductor Inc.
Le58QL061/063
Data Sheet
8.0 Switching Characteristics
The following are the switching characteristics over operating range (unless otherwise noted). Min and max values
are valid for all digital outputs with a 115 pF load, except CD1–C7 with a 30 pF load. (See Figure 12 and Figure 13
for the microprocessor interface timing diagrams.)
Microprocessor Interface
No.
1
Symbol
Parameter
Data clock period
Min.
122
48
Typ.
Max.
Unit
Note
t
DCY
t
2
Data clock HIGH pulse width
Data clock LOW pulse width
Rise time of clock
DCH
t
3
48
DCL
t
4
25
25
DCR
t
5
Fall time of clock
DCF
t
t
t
–10
6
Chip select setup time, Input mode
Chip select hold time, Input mode
Chip select pulse width, Input mode
Chip select off time, Input mode
Input data setup time
30
0
ICSS
DCY
DCH
t
–20
7
ICSH
t
8t
DCY
8
ICSL
t
9
2500
25
1
ICSO
t
10
11
12
IDS
t
Input data hold time
30
ns
IDH
t
SLIC device output latch valid
2500
OLH
Chip select setup time, Output
mode
t
t
t
–10
–20
13
14
15
30
0
OCSS
DCY
DCH
t
Chip select hold time, Output mode
OCSH
Chip select pulse width, Output
mode
t
8t
DCY
OCSL
t
16
17
18
19
20
21
Chip select off time, Output mode
Output data turn on delay
Output data hold time
Output data turn off delay
Output data valid
2500
3
1
2
OCSO
t
36
ODD
t
ODH
t
36
36
ODOF
t
ODC
t
Reset pulse width
50
µs
RST
25
Zarlink Semiconductor Inc.
Le58QL061/063
Data Sheet
PCM Interface
PCLK not to exceed 8.192 MHz.
Pull-up resistors to V
interface timing diagrams.)
of 240 Ω are attached to TSCA and TSCB. (See Figure 14 through Figure 16 for the PCM
CCD
No.
22
23
24
25
26
27
28
30
31
32
33
34
35
36
Symbol
Parameter
PCM clock period
Min.
122
48
Typ.
Max.
Unit
Note
t
3
PCY
t
PCM clock HIGH pulse width
PCM clock LOW pulse width
Fall time of clock
PCH
t
48
PCL
t
15
15
PCF
t
Rise time of clock
PCR
t
t
–30
PCY
FS setup time
25
50
5
FSS
t
FS hold time
FSH
ns
t
Delay to TSC valid
80
4
TSD
t
Delay to TSC off
5
80
70
70
70
4,5
TSO
t
PCM data output delay
PCM data output hold time
PCM data output delay to High-Z
PCM data input setup time
PCM data input hold time
5
DXD
t
5
DXH
t
5
DXZ
t
25
5
DRS
t
DRH
Master Clock
(See Figure 7 for the Master Clock timing diagram.)
No.
37
38
39
40
41
Symbol
Parameter
Master clock jitter
Min.
Typ.
Max.
50
Unit
Notes
J
6
MCY
t
Rise time of clock
15
MCR
t
Fall time of clock
15
ns
MCF
t
MCLK HIGH pulse width
MCLK LOW pulse width
48
48
MCH
t
MCL
26
Zarlink Semiconductor Inc.
Le58QL061/063
Data Sheet
Auxiliary Output Clocks
No.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
Chopper clock frequency:
f
42
kHz
7
CHP = 0
CHP = 1
256
292.57
CHP
DC
42A
43
Chopper click duty cycle
50
%
kHz
µs
7
7
7
CHP
f
E1 output frequency (CMODE = EE1 = 1)
E1 pulse width (CMODE = EE1 = 1)
4.923
31.25
E1
t
44
E1
Notes:
1. If CFAIL = 1 (Command 55h), GX, GR, Z, B1, X, R, and B2 coefficients must not be written or read without first deactivating all channels or
switching them to default coefficients; otherwise, a chip select off time of 25 µs is required.
2. The first data bit is enabled on the falling edge of CS or on the falling edge of DCLK, whichever occurs last.
3. The PCM clock frequency must be an integer multiple of the frame sync frequency. The maximum allowable PCM clock frequency is 8.192
MHz. The actual PCM clock rate is dependent on the number of channels allocated within a frame. The minimum clock frequency is 128 kHz
in Companded state and 256 kHz in Linear state, PCM Signaling state, or double PCLK state. The minimum PCM clock rates should be
doubled for parts with only one PCM highway in order to allow simultaneous access to all four channels.
4. TSC is delayed from FS by a typical value of N •tPCY, where N is the value stored in the time/clock-slot register.
5.
tTSO is defined as the time at which the output achieves the Open Circuit state.
6. PCLK and MCLK are required to be integer multiples of the frame sync (FS) frequency. Frame sync is expected to be an accurate 8 kHz
pulse train. If PCLK or MCLK has jitter, care must be taken to ensure that all setup, hold, and pulse width requirements are met.
7. Phase jumps of 81 nS will be present when the master clock frequency is a multiple of 1.544 MHz.
27
Zarlink Semiconductor Inc.
Le58QL061/063
Data Sheet
9.0 Switching Waveforms
2.4 V
2.0 V
0.8 V
2.0 V
TEST
POINTS
0.8 V
0.45 V
Figure 11 - Input and Output Waveforms for AC Tests
1
2
5
VIH
VIH
DCLK
VIL
VIL
3
7
9
4
CS
6
8
10
11
Data
Valid
Data
Valid
Data
Valid
DI/O
12
Data
Valid
Outputs
CD1 - C7
Data
Valid
Figure 12 - Microprocessor Interface (Input Mode)
28
Zarlink Semiconductor Inc.
Le58QL061/063
Data Sheet
VIH
VIL
DCLK
14
13
16
CS
15
20
18
17
Three-State
19
VOH
VOL
Three-State
Data
Valid
Data
Valid
Data
Valid
DI/O
Figure 13 - Microprocessor Interface (Output Mode)
Time Slot Zero
Clock Slot Zero
22
26
25
VIH
VIL
PCLK
23
24
27
28
FS
30
31
TSCA/
TSCB
32
33
34
VOH
DXA/DXB
DRA/DRB
First Bit
VOL
35
36
VIH
First
Bit
Second
Bit
VIL
Figure 14 - PCM Highway Timing for XE = 0 (Transmit on Negative PCLK Edge)
29
Zarlink Semiconductor Inc.
Le58QL061/063
Data Sheet
Time Slot Zero
Clock Slot Zero
22
25
26
VIH
VIL
PCLK
23
30
24
27
28
FS
31
34
TSCA/
TSCB
32
33
VOH
DXA/DXB
DRA/DRB
First Bit
VOL
35
36
VIH
First
Bit
Second
Bit
VIL
Figure 15 - PCM Highway Timing for XE = 1 (Transmit on Positive PCLK Edge)
30
Zarlink Semiconductor Inc.
Le58QL061/063
Data Sheet
PCLK
FS
First Bit
Second Bit
DXA/DXB,
DRA/DRB
Detail Below
26
25
tPCR
tPCF
PCLK
23
22
tPCH
tPCY
tPCL
24
FS
27
28
tFSH
tFSS
DXA/DXB
DRA/DRB
tDXD
32
36
35
tDRS
tDRH
Figure 16 - Double PCLK PCM Timing
31
Zarlink Semiconductor Inc.
Le58QL061/063
Data Sheet
37
40
V
IH
V
IL
41
39
38
Figure 17 - Master Clock Timing
9.1 GCI Timing Specifications
Symbol
Signal
Parameter
Min.
Typ.
Max.
Unit
Notes
t , t
DCL
Rise/fall time
DCL jitter
60
r
f
F
F
= 2.048 kHz
= 4.096 kHz
50
50
DCL
DCL
J
t
DCL
DCL
1
DCL
Period
F
F
= 2.048 kHz
= 4.096 kHz
488
244
DCL
DCL
DCL
t
, t
DCL
FS
Pulse width
Rise/fall time
Setup time
Hold time
90
2
wH wL
t , t
60
r
f
ns
t
t
– 50
DCL
FS
70
50
sF
t
FS
hF
t
FS
High pulse width
130
wFH
t
DU
DU
DD
DD
Delay from DCL edge
Delay from FS edge
Data setup
100
150
dDC
t
dDF
t
20
50
sD
t
Data hold
hD
Notes:
1. If DCL has jitter, care must be taken to ensure that all setup, hold, and pulse width requirements are met.
2. The Data Clock (DCL) can be stopped in the high or low state without loss of information.
32
Zarlink Semiconductor Inc.
Le58QL061/063
Data Sheet
9.2 GCI Waveforms
DCL
4.096 MHz
FS
Bit 7
Bit 6
DD, DU
Detail Below
tr
tf
DCL
twH
tDCL
twL
FS
tsF
thF
twFH
tdDF
DU
tdDC
tsD
thD
DD
Figure 18 - 4.096 MHz DCL Operation
33
Zarlink Semiconductor Inc.
Le58QL061/063
Data Sheet
DCL
2.048 MHz
FS
Bit 7
Bit 6
Bit 5
DD, DU
Detail Below
tr
tf
DCL
twH
tDCL
twL
FS
tsF
thF
twFH
tdDF
DU
tdDC
tsD
thD
DD
Figure 19 - 2.048 MHz DCL Operation
34
Zarlink Semiconductor Inc.
Le58QL061/063
Data Sheet
10.0 OPERATING THE QLSLAC DEVICE
The following sections describe the operation of the four independent channels of the QLSLAC device. The
description is valid for channel 1, 2, 3, or 4; consequently, the channel subscripts have been dropped. For example,
VOUT refers to either VOUT , VOUT , VOUT , or VOUT .
1
2
3
4
10.1 Power-Up Sequence
The recommended QLSLAC device power-up sequence is to apply:
1. Analog and digital ground
2. VCC, signal connections, and Low on RST
3. High on RST
The software initialization should then include:
1. Wait 1 ms.
2. For PCM/MPI mode, select master clock frequency and source (Command 46/47h). This should turn off the
CFAIL bit
(Command 55h) within 400 µs.
In GCI mode, DCL is the clock source. The CFAIL bit (GCI Command SOP 8) is set to 1 until the device has
determined and synchronized to the DCL frequency, 4.096 MHz or 2.048 MHz. If channels are activated while
CFAIL is a 1, no device damage will occur, but high audible noise may appear on the line. Also, the CD1, CD2,
and C3 - C7 bits may not be stable.
3. Program filter coefficients and other parameters as required.
4. Activate (MPI Command 0Eh, GCI Command SOP 4).
If the power supply (VCCD) falls below an internal threshold, the device is reset and will require complete
reprogramming with the above sequence. A reset may be initiated by connection of a logic Low to the RST pin, or if
chip select (CS) is held low for 16 rising edges of DCLK, a hardware reset is generated when CS returns high. The
RST pin may be tied to VCCD if it is not used in the system.
10.2 PCM and GCI State Selection
The Le58QL061/063 QLSLAC device can switch between PCM/MPI and GCI modes. Table 3 lists the selection
requirements.
From State
To State
Requirement
Power On or Hardware Reset
PCM
GCI
CS = 1 or DCLK has ac clock present
CS = 0 and DCLK does not have ac clock
present
Power On or Hardware Reset
GCI
PCM
CS = 1 or DCLK has ac clock present
No commands yet sent in PCM state and
CS = 0 (for more than 2 FS) and DCLK does
not have ac clock present
PCM
GCI
Power On or Hardware
Reset
Commands have been sent in PCM state
and Hardware Reset generated
PCM
GCI
Power On or Hardware
Reset
Not allowed
Table 3 - PCM/GCI Mode Selection
35
Zarlink Semiconductor Inc.
Le58QL061/063
Data Sheet
10.3 Channel Enable (EC) Register (PCM/MPI Mode)
In PCM/MPI mode, a channel enable (EC) register has been implemented in the QLSLAC device in order to reduce
the effort required to address individual or multiple channels of the QLSLAC device. The register is written using
MPI Command 4A/4Bh. Each bit of the register is assigned to one unique channel, bit 0 for channel 1, bit 1 for
channel 2, bit 2 for channel 3, and bit 3 for channel 4. The channel or channels are enabled when their
corresponding enable bits are High. All enabled channels receive the data written to the QLSLAC device. This
enables a Broadcast mode (all channels enabled) to be implemented simply and efficiently, and multiple channel
addressing is accomplished without increasing the number of I/O pins on the device. The Broadcast mode can be
further enhanced by providing the ability to select many chips at once; however, care must be taken not to enable
more than one chip in the Read state. This can lead to an internal bus contention, where excess power is
dissipated. (Bus contention will not damage the device.)
In GCI mode, the individual channels are controlled by their respective Monitor and SC channels embedded in the
GCI channels selected by the device (S0, S1).
10.4 SLIC Device Control and Data Lines
The QLSLAC device has up to five SLIC device programmable digital input/output pins per channel (CD1–C5).
Each of these pins can be programmed as either an input or an output using the I/O Direction register (MPI
Command 54/55h, GCI Command SOP 8). Also, the Le58QL063HVC 64-pin package includes two additional
output pins per channel, C6-C7 (see Figure 21). The output latches can be written with MPI Command 52h or
through the CI1 to CI5 bits present in the downstream SC channel; however, only those bits programmed as
outputs will actually drive the pins. The inputs can be read with MPI Command 53h, GCI Command SOP 10 or on
the Upstream CI bits, in the SC channel. If a pin is programmed as an output, the data read from it will be the
contents of the output latch. In GCI mode, this data can be read using GCI Command SOP 10, but the output bits
are not sent upstream in the SC channel. It is recommended that any of the SLIC device input/output control and
data pins, which are to be programmed as outputs, be written to their desired state before writing the data which
configures them as outputs with the I/O direction register MPI Command 54/55h, GCI Command SOP 8. This
ensures that when the output is activated, it is already in the correct state, and will prevent unwanted data from
being driven from the SLIC device output pins. It is possible to make a SLIC device control output pull up to a non-
standard voltage (V < 5.25 V) by connecting a resistor from the output to the desired voltage, sending zero to the
output, and using the DIO bit to tri-state the output.
10.5 Clock Mode Operation
The QLSLAC device operates with multiple clock signals. The master clock is used for internal timing including
operation of the digital signal processing. In PCM/MPI mode, the master clock may be derived from either the
MCLK or PCLK source. When MCLK is used as the master clock, it should be synchronous to FS. In GCI mode, the
master clock is obtained from the DCL clock only. The allowed frequencies are listed under Command 46/47h for
PCM/MPI mode. In GCI mode, DCL can be only 2.048 MHz or 4.096 MHz.
36
Zarlink Semiconductor Inc.
Le58QL061/063
Data Sheet
In PCM/MPI mode, the PCM clock (PCLK) is used for PCM timing and is an integer multiple of the frame sync
frequency. The internal master clock can be optionally derived from the PCLK source by setting the CMODE bit (bit
4, Command 46/47h) to one. In this mode, the MCLK/E1 pin is free to be used as an E1 signal output. In GCI mode,
since the master clock is derived only from the DCL clock, this MCLK/E1 pin is always available as an E1 output.
Clock mode options and E1 output functions are shown in Figure 20.
MCLK/E1
PCLK
(= 0)
(= 1)
E1
Time
Slot
Assigner
(= 1)
(= 0)
CMODE
(= 1)
(= 0)
EE1
÷ N
DSP
Engine
CSEL
E1
Pulses
E1P
Figure 20 - Clock Mode Options (PCM/MPI Mode)
Notes:
1. CMODE = Command 46/47h
2. CSEL = Command 46/47h
3. EE1 = Command C8/C9h
4. E1P = Command C8/C9h
Bit 4
Bits 0–3
Bit 7
Bit 6
37
Zarlink Semiconductor Inc.
Le58QL061/063
Data Sheet
10.6 E1 Multiplex Operation
The QLSLAC device can multiplex input data from the CD1 SLIC device I/O pin into two separate status bits per
channel (CD1 and CD1B bits in the SLIC device Input/Output register, MPI Command 52/53h, GCI Command SOP
10 and CDA and CDB bits in the Real Time Data register, MPI Command 4D/4Fh, GCI Command SOP 13, GCI C/I
Channel) using the E1 multiplex mode. This multiplex mode provides the means to accommodate dual detect
states when connected to an Zarlink SLIC device, which also supports ground-key detection in addition to loop
detect. Zarlink SLIC devices that support ground-key detect use their E1 pin as an input to switch the SLIC device’s
single detector (DET) output between internal loop detect or ground-key detect comparators. Using the E1
multiplex mode, a single QLSLAC device can monitor both loop detect and ground-key detect states of all four
connected SLIC devices without additional hardware. Although normally used for ground key detect, this multiplex
function can also be used for monitoring other signal states.
The E1 multiplex mode is selected by setting the EE1 bit (bit 7, MPI Command C8/C9h, GCI Command SOP 11)
and CMODE bit (bit 4, Command 46/47h) in the QLSLAC device. In PCM/MPI mode, the CMODE bit must be
selected (CMODE = 1) for the master clock to be derived from PCLK so that the MCLK/E1 pin can be used as an
output for the E1 signal. The multiplex mode is then turned on by setting the EE1 bit. With the E1 multiplex mode
enabled, the QLSLAC device generates the E1 output signal. This signal is a 31.25 µs (1/32 kHz) duration pulse
occurring at a 4.923 kHz (64 kHz/13) rate. If EE1 is reset, MCLK/E1 is programmed as an input and should be
connected to ground if it is not connected to a clock source. The polarity of this E1 output is selected by the E1P bit
(bit 6, MPI Command C8/C9h, GCI Command SOP 11) allowing this multiplex mode to accommodate all SLIC
devices regardless of their E1 high/low logic definition.
Figure 21 shows the SLIC device Input/Output register, I/O pins, E1 multiplex hardware operation for one QLSLAC
device channel. It also shows the operation of the Real Time Register. The QLSLAC device E1 output signal
connects directly to the E1 inputs of all four connected SLIC devices and is used by those SLIC devices to select an
internal comparator to route to the SLIC device’s DET output. This E1 signal is also used internally by the QLSLAC
device for controlling the multiplex operation and timing.
The CD1 and CD1B bits of the SLIC device Input/Output register are isolated from the CD1 pin by transparent
latches. When the E1 pulse is off, the CD1 pin data is routed directly to the CD1 bit of the SLIC device I/O register
and changes to the CD1B bit of that register are disabled by its own latch. When E1 pulses on, the CD1 latch holds
the last CD1 state in its register. At the same time, the CD1B latch is enabled, which allows CD1 pin data to be
routed directly to the CD1B bit. Therefore, during this multiplexing, the CD1 bit always has loop-detect status and
the CD1B bit always has ground-key detect status.
This multiplexing state changes almost instantaneously within the QLSLAC device but the SLIC device may require
a slightly longer time period to respond to this detect state change before its DET output settles and becomes valid.
To accommodate this delay difference, the internal signals within the QLSLAC device are isolated by 15.625 µs
before allowing any change to the CD1 bit and CD1B bit latches. This operation is further described by the E1
multiplex timing diagram in Figure 22. In this timing diagram, the E1 signal represents the actual signal presented to
the E1 output pin. The GK Enable pulse allows CD1 pin data to be routed through the CD1B latch. The LD Enable
pulse allows CD1 pin data to be routed through the CD1 latch. The uncertain states of the SLIC device’s DET
output, and the masked times where that DET data is ignored are shown in this timing diagram. Using this isolation
of masked times, the CD1 and CD1B registers are guaranteed to contain accurate representations of the SLIC
device detector output.
38
Zarlink Semiconductor Inc.
Le58QL061/063
Data Sheet
SLIC Input Register
MPI Command 53h
or GCI Upstream
SC Channel Data
C7 C6 CD1B C5
C4
C3 CD2 CD1
D
Q
EN/HOLD
*
CD1
CD2
C3
C4
C5
C6
C7
D
Q
EN/HOLD
I/O Direction
Register
1
0
*
MUX
MPI Command
54/55h or GCI
Command SOP 8
Output Latch
LD Enable
GK Enable
SLIC Output
Register
MPI Command 52h
or GCI Downstream
SC Channel Data
Ground Key Filter (time set via
MPI Command E8/E9h or GCI
Command SOP 12)
Debounce Time
(set via MPI Command C8/C9h or
GCI Command SOP 11)
(Channel 1
Shown)
EE1 Bit
E1 Source
(Internal)
Same for
Channels
2, 3, 4
{
Delay
(See Figure
for details)
MCLK/E1
Real Time Data Register
(MPI Command 4D/4Fh
or GCI UpstreamSC Channel data)
E1P
CDB4 CDA4 CDB3 CDA3 CDB2 CDA2 CDB1 CDA1
INT
Interrupt Mask Register
(MPI Command 6C/6Dh
or GCI Command SOP 14)
(MPI Command 70/71h
or GCI Command SOP 5)
ATI
MCDB4 MCDA4 MCDB3 MCDA3 MCDB2 MCDA2 MCDB1 MCDA1
Figure 21 - SLIC Device I/O, E1 Multiplex and Real-Time Data Register Operation
Note:
* Transparent latches: When enable input is high, Q output follows D input. When enable input goes low, Q output is latched at last state.
39
Zarlink Semiconductor Inc.
Le58QL061/063
Data Sheet
Pulse Period 203.125 µs
4.923 kHz (64 kHz/13) pulse rate
31.25 µs
15.625 µs
E1
15.625 µs
GK Enable
LD Enable
15.625 µs
DET Output
from SLIC
(CD1 Pin Input)
Contains
Valid LD
Status
Contains
Valid LD
Status
Contains
Valid GK
Status
CD1 Pin
State
Ignored
CD1 Pin
State
Ignored
CD1 Pin
Input Data
CD1
Register
Operation
Tracks
DET State
Tracks
DET State
Hold Last State
CD1B
Register
Operation
Tracks
DET State
Hold Last State
Hold Last State
Figure 22 - E1 Multiplex Internal Timing
10.7 Debounce Filters Operation
Each channel is equipped with two debounce filter circuits to buffer the logic status of the CD1 and CD2/CD1B bits
of the SLIC device Input Data Register (MPI Command 53h and GCI Command SOP 10) before providing filtered
bit’s outputs to the Real-Time Data Register (MPI Command 4D/4Fh or GCI Command SOP 13). One filter is used
only for the CD1 bit. The other filter either acts upon the CD1B bit if E1 multiplexing is enabled or on the CD2 bit if
the multiplexing is not enabled.
The CD1 bit normally contains SLIC device loop-detect status. The CD1 debouncing time is programmable with the
Debounce Time Register (MPI Command C8/C9h or GCI Command SOP 11), and even though each channel has
its own filter, the programmed value is common to all four channels. This debounce filter is initially clocked at the
frame sync rate of 125 µs, and any occurrence of changing data at this sample rate resets a programmable counter.
This programmable counter is clocked at a 1 ms rate, and the programmed count value of 0 to 15 ms, as defined by
the Debounce Time Register, must be reached before updating the CDA bit of the Real Time Data register with the
CD1 state. Refer to Figure 23a for this filter’s operation.
The ground-key filter (Figure 23b) provides a buffering of the signal, normally ground-key detect, which appears in
the CD1B bit of the Real-Time Data Register and the SC upstream channel in GCI mode. Each channel has its own
filter, and each filter’s time can be individually programmed. The input to the filter comes from either the CD2 bit of
the SLIC device I/O Data Register (MPI Command 53h), when E1 multiplexing is not enabled, or from the CD1B bit
of that register when E1 multiplexing is enabled. The feature debounces ground-key signals before passing them to
the Real Time Data Register, although signals other than ground-key status can be routed to the CD2 pin and then
through the registers.
40
Zarlink Semiconductor Inc.
Le58QL061/063
Data Sheet
The ground-key debounce filter operates as a duty-cycle detector and consists of an up/down counter which can
range in value between 0 and 6. This six-state counter is clocked by the GK timer at the sampling period of 1–15
ms, as programmed by the value of the four GK bits (GK3, GK2, GK1, GK0) of the Ground-Key Filter Data register
(MPI Command E8/E9h, GCI Command SOP 12). This sampling period clocks the counter, which buffers the
CD2/CD1B bit’s status before it is valid for presenting to the CDB bit of the Real Time Data Register. When the
sampled value of the ground-key (or CD2) input is high, the counter is incremented by each clock pulse. When the
sampled value is low, the counter is decremented. Once the counter increments to its maximum value of 6, it sets
a latch whose output is routed to the corresponding CDB bit. If the counter decrements to its minimum value of 0,
this latch is cleared and the output bit is set to zero. All other times, the latch (and the CDB status) remains in its
previous state without change. It therefore takes at least six consecutive GK clocks with the debounce input
remaining at the same state to effect an output change. If the GK bit value is set to zero, the buffering is bypassed
and the input status is passed directly to CDB.
CD1
CDA
D
Q
Debounce Counter
DSH0 – DSH3
D
Q
D
Q
D
Q
EN/HOLD
*
Debounce Period
(0 – 15 ms)
Q
CK
RST
8
FS (8 kHz)
Figure 23 - MPI Real-Time Data Register
a. Loop Detect Debounce Filter
Notes:
*Transparent latch: Output follows input when EN is high; ouput holds last state when EN is low.
Debounce counter: Output is high after counting to programmed (DSH) number of 1 ms clocks; counter is reset for CD1 input changes at 125 µs
sample period. DSH0 - DSH3 programmed value is common for all four channels, but debounce counter is separate per channel.
MUX
CD2 or CD1B
GK
=
=
0
0
CDB
UP/DN
Q
GK0 – GK3
Ground-Key
Sampling Interval
1 – 15 ms
GK
GK
Six-State
Up/Down
Counter
RST
1 kHz
Clock Divider
(1 – 15 ms
clock output)
b. Ground-Key Filter
Notes:
Programmed value of GK0 - GK3 determines clock rate (1 - 15 ms) of six-state counter.
If GK value = 0, the counter is bypassed and no buffering occurs.
Six-state up/down counter: Counts up when input is high; counts down when input is low.
Output goes and stays high when maximum count is reached; output goes and stays low when count is down to zero.
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Data Sheet
10.8 Real-Time Data Register Operation
To obtain time-critical data such as off/on-hook and ring trip information from the SLIC device with a minimum of
processor time and effort, the QLSLAC device contains an 8-bit Real Time Data register. This register contains
CDA and CDB bits from all four channels. The CDA bit for each channel is a debounced version of the CD1 input.
The CDA bit is normally used for hook switch. The CDB bit for each channel normally contains the debounced
value of the CD2 input bit; however, if the E1 multiplex operation is enabled, the CDB bit will contain the debounced
value of the CD1B bit. CD1 and CD2 can be assigned to off-hook, ring trip, ground key signals, or other signals.
Frame sync is needed for the debounce and the ground-key signals. If Frame sync is not provided, the real-time
register will not work. The register is read using MPI Command 4D/4Fh, GCI Command SOP 13, and may be read
at any time regardless of the state of the Channel Enable Register. This allows off/on-hook, ring trip, or ground key
information for all four channels to be obtained from the QLSLAC device with one read operation versus one read
per channel. If these data bits are not used for supervision information, they can be accessed on an individual
channel basis in the same way as C3–C5; however, CD1 and CD1B will not be debounced. This Real-Time Data
register is available in both MPI and GCI modes. In the GCI mode, this real-time data is also available in the field of
the upstream SC octet.
10.9 Interrupt
In addition to the Real Time Data register, an interrupt signal has been implemented in the QLSLAC device. The
interrupt signal is an active Low output signal which pulls Low whenever the unmasked CD bits change state (Low
to High or High to Low); or whenever the transmit PCM data changes on a channel in which the Arm Transmit
Interrupt (ATI) bit is on. The interrupt control is shown in Figure . The interrupt remains Low until the appropriate
register is read. This output can be programmed as TTL or open drain output by the INTM bit, MPI Command
46/47h or GCI Command SOP 6. When an interrupt is generated, all of the unmasked bits in the Real Time Data
register latch and remain latched until the interrupt is cleared. The interrupt is cleared by reading the register with
MPI Command 4Fh or GCI Command SOP 13, by writing to the interrupt mask register (MPI Command 6Ch, GCI
Command SOP 14), or by a reset. If any of the inputs to the unmasked bits in the Real Time Data register are
different from the register bits when the interrupt is cleared by reading the register, a new interrupt is immediately
generated with the new data latched into the Real Time Data register. For this reason, the interrupt logic in the
controller should be level-sensitive rather than edge-sensitive.
10.10 Interrupt Mask Register
The Real Time Data register data bits can be masked from causing an interrupt to the processor using the interrupt
mask register. The contents of the mask register can be written or read via the MPI Command 6C/6Dh, GCI
Command SOP 14.
10.11 Active State
Each channel of the QLSLAC device can operate in either the Active (Operational) or Inactive (Standby) state. In
the Active state, individual channels of the QLSLAC device can transmit and receive PCM or linear data and analog
information. The Active state is required when a telephone call is in progress. The activate command ( MPI
Command 0Eh, GCI Command SOP 4) puts the selected channels (see channel enable register for PCM/MPI
Mode) into this state (CSTAT = 1). Bringing a channel of the QLSLAC device into the Active state is only possible
through the MPI command or the GCI command.
10.12 Inactive State
All channels of the QLSLAC device are forced into the Inactive (Standby) state by a power-up or hardware reset.
Individual channels can be programmed into this state (CSTAT = 0) by the deactivate command (MPI Command
00h, GCI Command SOP 1) or by the software reset command (MPI Command 02h, GCI Command SOP 2).
Power is disconnected from all nonessential circuitry, while the MPI remains active to receive commands. The
analog output is tied to VREF through a resistor whose value depends on the VMODE bit. All circuits that contain
programmed information retain their data in the Inactive state.
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Zarlink Semiconductor Inc.
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Data Sheet
10.13 Chopper Clock
The Le58QL063 device provides a chopper clock output to drive the switching regulator on some Zarlink SLIC
devices. The clock frequency is selectable as 256 or 292.57 kHz by the CHP bit (MPI Command 46/47h, GCI
Command SOP 6). The duty cycle is given in the Switching Characteristics section. The chopper output must be
turned on with the ECH bit (MPI Command C8/C9h, GCI Command SOP 11).
10.14 Reset States
The QLSLAC device can be reset by application of power, by an active Low on the hardware Reset pin (RST), by a
hardware reset command, or by CS Low for 16 or more rising edges of DCLK. This resets the QLSLAC device to
the following state:
1. A-law companding is selected.
2. Default B, X, R, and Z filter values from ROM are selected and the AISN is set to zero.
3. Default digital gain blocks (GX and GR) from ROM are selected. The analog gains, AX and AR, are set to 0 dB
and the input attenuator is turned on (DGIN = 0).
4. The previously programmed B, Z, X, R, GX, and GR filters in RAM are unchanged.
5. SLIC device input/outputs CD1, CD2, C3, C4, and C5 are set to the Input mode.
6. All of the test states in the Operating Conditions register are turned off (0s).
7. All four channels are placed in the Inactive (Standby) mode.
8. For PCM/MPI mode, transmit time slots and receive time slots are set to 0, 1, 2, and 3 for channels 1, 2, 3, and
4, respectively. The clock slots are set to 0, with transmit on the negative edge. For GCI mode, operation is
determined by S0 and S1.
9. DXA/DU port is selected for all channels.
10.DRA/DD port is selected for all channels.
11.The master clock frequency in PCM/MPI mode is selected to be 8.192 MHz and is programmed to come from
PCLK. In GCI mode, DCL is 2.048 or 4.096 MHz and is determined by the QLSLAC device.
12.All four channels are selected in the Channel Enable Register for PCM/MPI mode.
13.Any pending interrupts are cleared, all interrupts are masked, and the Interrupt Output state is set to open drain.
14.The supervision debounce time is set to 8 ms.
15.The chopper clock frequency is set to 256 kHz, but the chopper clock is turned off.
16.The E1 Multiplex state is turned off (E1 is Hi-Z) and the polarity is set for high going pulses.
17.No signaling on the PCM highway (PCM/MPI mode).
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Data Sheet
11.0 Signal Processing
11.1 Overview of Digital Filters
Several of the blocks in the signal processing section are user programmable. These allow the user to optimize the
performance of the QLSLAC device for the system. Figure 24 shows the QLSLAC device signal processing and
indicates the programmable blocks.
The advantages of digital filters are:
•
•
•
•
•
•
High reliability
No drift with time or temperature
Unit-to-unit repeatability
Superior transmission performance
Flexibility
Maximum possible bandwidth for V.90 modems
Cutoff
Transmit
Path
High Pass Filter (HPF)
(CTP)
VIN
*
Deci-
mator
Deci-
mator
LPF &
HPF
Com-
pressor
+
Digital
TX
AX
ADC
GX
*
X
*
TSA
GIN
TSA Loopback
(TLB)
AISN
Full
*
Z
B
*
*
Digital
Loopback
(FDL)
Cutoff Receive
Path (CRP)
*
Inter-
polator
Inter-
polator
Ex-
pander
+
+
AR DAC
GR
*
R
*
LPF
TSA
Digital
RX
VOUT
VREF
Lower Receive
Gain (LRG)
1 kHz Tone
(TON)
0
* programmable blocks
Figure 24 - QLSLAC Device Transmission Block Diagram
11.2 Two-Wire Impedance Matching
Two feedback paths on the QLSLAC device synthesize the two-wire input impedance of the SLIC device by
providing a programmable feedback path from VIN to VOUT. The Analog Impedance Scaling Network (AISN) is a
programmable analog gain of −0.9375 • GIN to +0.9375 • GIN from VIN to VOUT. (See GIN in 7.0, “Electrical
Characteristics“ on page 16.) The Z filter is a programmable digital filter providing an additional path and
programming flexibility over the AISN in modifying the transfer function from V to V
. Together, the AISN and
IN
OUT
the Z-Filter enable the user to synthesize virtually all required SLIC device input impedances.
11.3 Frequency Response Correction and Equalization
The QLSLAC device contains programmable filters in the receive (R) and transmit (X) directions that may be
programmed for line equalization and to correct any attenuation distortion caused by the Z filter.
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Data Sheet
11.4 Transhybrid Balancing
The QLSLAC device’s programmable B filter is used to adjust transhybrid balance (MPI Commands 86/87h and
96/97h, GCI Commands COP 5 and COP 8). The filter has a single pole IIR section (BIIR) and an eight-tap FIR
section (BFIR), both operating at 16 kHz.
11.5 Gain Adjustment
The QLSLAC device’s transmit path has three programmable gain blocks. Gain block GIN is an attenuator with a
gain of GIN (see 7.0, “Electrical Characteristics“ on page 16 for the value). Gain block AX is an analog gain of 0 dB
or 6.02 dB (unity gain or gain of 2.0), located immediately before the A/D converter. GX is a digital gain block that is
programmable from 0 dB to +12 dB, with a worst-case step size of 0.1 dB for gain settings below +10 dB, and a
worst-case step size of 0.3 dB for gain settings above +10 dB. The filters provide a net gain in the range of 0 dB to
18 dB.
The QLSLAC device receive path has two programmable loss blocks. GR is a digital loss block that is
programmable from 0 dB to 12 dB, with a worst-case step size of 0.1 dB. Loss block AR is an analog loss of 0 dB or
6.02 dB (unity gain or gain of 0.5), located immediately after the D/A converter. This provides a net loss in the range
of 0 dB to 18 dB.
An additional 6 dB attenuation is provided as part of GR, which can be inserted by setting the LRG bit of MPI
Command 70/71h, GCI Command SOP 5. This allows writing of a single bit to introduce 6 dB of attenuation into the
receive path without having to reprogram GR. This 6 dB loss is implemented as part of GR and the total receive path
attenuation must remain in the specified 0 to –12 dB range. If the LRG bit is set, the programmed value of GR must not
introduce more than an additional 6 dB attenuation.
11.6 Transmit Signal Processing
In the transmit path (A/D), the analog input signal (VIN) is A/D converted, filtered, companded (for A-law or µ-law),
and made available to the PCM highway or General Circuit Interface (GCI). Linear mode is only available in the
PCM/MPI mode. If linear form is selected, the 16-bit data will be transmitted in two consecutive time slots starting at
the programmed time slot. The signal processor contains an ALU, RAM, ROM, and control logic to implement the
filter sections. The B, X, and GX blocks are user-programmable digital filter sections with coefficients stored in the
coefficient RAM, while AX is an analog amplifier that can be programmed for 0 dB or 6.02 dB gain. The B, X, and
GX filters can also be operated from an alternate set of default coefficients stored in ROM (MPI Command 60/61h,
GCI Command SOP 7).
The decimator reduces the high input sampling rate to 16 kHz for input to the B, GX, and X filters. The X filter is a
six-tap FIR section which is part of the frequency response correction network. The B filter operates on samples
from the receive signal path in order to provide transhybrid balancing in the loop. The high-pass filter rejects low
frequencies such as 50 Hz or 60 Hz, and may be disabled.
11.7 Transmit PCM Interface (PCM/MPI Mode)
In PCM/MPI mode, the transmit PCM interface transmits a 16-bit linear code (when programmed) or an 8-bit
compressed code from the digital A-law/µ-law compressor. Transmit logic controls the transmission of data onto the
PCM highway through output port selection and time/clock slot control circuitry. The linear data requires two
consecutive time slots, while a single time slot is required for A-law/µ-law data.
In the PCM Signaling state (SMODE = 1), the transmit time slot following the A-law or µ-law data is used for
signaling information. The two time slots form a single 16-bit data block.
The frame sync (FS) pulse identifies time slot 0 of the transmit frame and all channels (time slots) are referenced to
it. The logic contains user-programmable Transmit Time Slot and Transmit Clock Slot registers.
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Zarlink Semiconductor Inc.
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Data Sheet
The Time Slot register is 7 bits wide and allows up to 128 8-bit channels (using a PCLK of 8.192 MHz) in each
frame. This feature allows any clock frequency between 128 kHz and 8.192 MHz (2 to 128 channels) in a system.
The data is transmitted in bytes, with the most significant bit first.
The Clock Slot register is 3 bits wide and may be programmed to offset the time slot assignment by 0 to 7 PCLK
periods to eliminate any clock skew in the system. An exception occurs when division of the PCLK frequency by 64
kHz produces a nonzero remainder, R, and when the transmit clock slot is greater than R. In that case, the R-bit
fractional time slot after the last full time slot in the frame will contain random information and will have the TSC
output turned on. For example, if the PCLK frequency is 1.544 MHz (R = 1) and the transmit clock slot is greater
than 1, the 1-bit fractional time slot after the last full time slot in the frame will contain random information, and the
TSC output will remain active during the fractional time slot. In such cases, problems can be avoided by not using
the last time slot.
The PCM data may be user programmed for output onto either the DXA or DXB port or both ports simultaneously.
Correspondingly, either TSCA or TSCB or both are Low during transmission.
The DXA/DXB and TSCA/TSCB outputs can be programmed to change either on the negative or positive edge of
PCLK.
Transmit data can also be read through the microprocessor interface using Command CDh.
11.8 Data Upstream Interface (GCI Mode)
In the GCI mode, the Data Upstream (DU) interface transmits a total of 4 bytes per GCI channel. Two bytes are
from the A-law or µ-law compressor, one for voice channel 1, one for voice channel 2, a single Monitor channel
byte, and a single SC channel byte. Transmit logic controls the transmission of data onto the GCI bus as
determined by the frame synchronization signal (FSC) and the S0 and S1 channel select bits. No signaling or
Linear mode options are available when GCI mode is selected.
The frame synchronization signal (FSC) identifies GCI channel 0 and all GCI channels are referenced to it.
Upstream Data is always transmitted at a 2.048 MHz data rate.
11.9 Receive Signal Processing
In the receive path (D/A), the digital signal is expanded (for A-law or µ-law), filtered, converted to analog, and
passed to the VOUT pin. The signal processor contains an ALU, RAM, ROM, and Control logic to implement the
filter sections. The Z, R, and GR blocks are user-programmable filter sections with their coefficients stored in the
coefficient RAM, while AR is an analog amplifier which can be programmed for a 0 dB or 6.02 dB loss. The Z, R,
and GR filters can also be operated from an alternate set of default coefficients stored in ROM (MPI Command
60/61h, GCI Command SOP 7).
The low-pass filter band limits the signal. The R filter is composed of a six-tap FIR section operating at a 16 kHz
sampling rate and a one-tap IIR section operating at 8 kHz. It is part of the frequency response correction network.
The Analog Impedance Scaling Network (AISN) is a user-programmable gain block providing feedback from VIN to
VOUT to emulate different SLIC device input impedances from a single external SLIC device impedance. The Z
filter provides feedback from the transmit signal path to the receive path and is used to modify the effective input
impedance to the system. The interpolator increases the sampling rate prior to D/A conversion.
11.10 Receive PCM Interface (PCM/MPI Mode)
The receive PCM interface logic controls the reception of data bytes from the PCM highway, transfers the data to
the A-law or µ-law expansion logic for compressed signals, and then passes the data to the receive path of the
signal processor. If the data received from the PCM highway is programmed for linear code, the A-law or µ-law
expansion logic is bypassed and the data is presented to the receive path of the signal processor directly. The
linear data requires two consecutive time slots, while the A-law or µ-law data requires a single time slot.
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Data Sheet
The frame sync (FS) pulse identifies time slot 0 of the receive frame, and all channels (time slots) are referenced to
it. The logic contains user-programmable Receive Time Slot and Receive Clock Slot registers. The Time Slot
register is 7 bits wide and allows up to 128 8-bit channels (using a PCLK of 8.192 MHz) in each frame. This feature
allows any clock frequency between 128 kHz and 8.192 MHz (2 to 128 channels) in a system.
The Clock Slot register is 3 bits wide and can be programmed to offset the time slot assignment by 0 to 7 PCLK
periods to eliminate any clock skews in the system. An exception occurs when division of the PCLK frequency by
64 kHz produces a nonzero remainder (R), and when the receive clock slot is greater than R. In this case, the last
full receive time slot in the frame is not usable. For example, if the PCLK frequency is 1.544 MHz (R = 1), the
receive clock slot can be only 0 or 1 if the last time slot is to be used. The PCM data can be user-programmed for
input from either the DRA or DRB port.
11.11 Data Downstream Interface (GCI Mode)
The Data Downstream (DD) interface logic controls the reception of data bytes from the GCI highway. The GCI
channels received by the QLSLAC device is determined by the logic levels on S0 and S1, the GCI channel select
bits. The two compressed voice channel data bytes of the GCI channel are transferred to the A-law or µ-law
expansion logic. The expanded data is passed to the receive path of the signal processor. The Monitor channel and
SC channel bytes are transferred to the GCI control logic for processing.
The frame synchronization signal (FSC) identifies GCI channel 0 of the GCI frame, and all other GCI channels are
referenced to it.
Downstream Data is always received at a 2.048 MHz data rate.
11.12 Analog Impedance Scaling Network (AISN)
The AISN is incorporated in the QLSLAC device to scale the value of the external SLIC device impedance. Scaling
this external impedance with the AISN (along with the Z filter) allows matching of many different line conditions
using a single impedance value. Line cards can meet many different specifications without any hardware changes.
The AISN is a programmable transfer function connected from VIN to VOUT of each QLSLAC device channel. The
AISN transfer function can be used to alter the input impedance of the SLIC device to a new value (Z ) given by:
IN
ZIN = ZSL • (1 – G44 • hAISN) ⁄ (1 – G440 • hAISN
)
where G
is the SLIC device echo gain into an open circuit, G is the SLIC device echo gain into a short circuit,
440
44
and Z is the SLIC device input impedance without the QLSLAC device.
SL
The gain can be varied from −0.9375 • GIN to +0.9375 • GIN in 31 steps of 0.0625 • GIN. The AISN gain is
determined by the following equation:
4
⎛
⎜
⎜
⎝
⎞
i
⎟
hAISN = 0.0625 • GIN
AISNi • 2 – 16
∑
⎟
⎠
i = 0
where AISN = 0 or 1
i
There are two special cases to the formula for h
: 1) a value of AISN = 00000 specifies a gain of 0 (or cutoff),
AISN
and 2) a value of AISN = 10000 is a special case where the AISN circuitry is disabled and VOUT is connected
internally to VIN after the input attenuator with a gain of 0 dB. This allows a Full Digital Loopback state where an
input digital PCM signal is completely processed through the receive section, looped back, processed through the
transmit section, and output as digital PCM data. During this test, the VIN input is ignored and the VOUT output is
connected to VREF.
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Data Sheet
11.13 Speech Coding
The A/D and D/A conversion follows either the A-law or the µ-law standard as defined in ITU-T Recommendation
G.711. A-law or µ-law operation is programmed using MPI Command 60/61h or GCI Command SOP 7. Alternate bit
inversion is performed as part of the A-law coding. In PCM/MPI mode, the QLSLAC device provides linear code as
an option on both the transmit and receive sides of the device. Linear code is selected using MPI Command
60/61h. Two successive time slots are required for linear code operation. The linear code is a 16-bit two’s-
complement number which appears sign bit first on the PCM highway. Linear code occupies two time slots.
11.14 Double PCLK (DPCK) Operation (PCM/MPI Mode)
The Double PCLK Operation allows the PCM clock (PCLK) signal to be clocked at a rate of twice that of the PCM
data. This mode provides compatibility of the QLSLAC device with other existing system architectures, such as a
GCI interface system in terminal mode operating at a 768 kHz data rate with a 1.536 MHz clock rate.
The operation is enabled by setting the DPCK bit of Command C8/C9h. When set to zero, operation is unchanged
from normal PCM clocking and the PCM data and clock rates are the same. When the bit is set to 1, clocking of
PCM data is divided by two and occurs at one half of the PCLK PCM clock rate. The internal PLL used for
synchronization of the master DSP clock (MCLK) receives its input from either the MCLK or PCLK pin, depending
on the clock mode (CMODE) selection. If PCLK is used for MCLK (CMODE = 1), then the clock input is routed to
both the DSP clock input and to the time slot assigner. The timing division related to the double PCLK mode occurs
only within the time slot assigner, and therefore, double PCLK operation is available with either CMODE setting.
This allows the MCLK/E1 pin to be available for E1 multiplexing operation if both double PCLK and E1 multiplexing
modes are simultaneously required.
Specifications for Double PCLK Operation are shown in the Switching Characteristics section on page 25.
11.15 Signaling on the PCM Highway (PCM/MPI Mode)
If the SMODE bit is set in the Configuration register (MPI Command 46/47h), each data point occupies two
consecutive time slots. The first time slot contains A-law or µ-law data and the second time slot contains the
following information:
Bit 7:
Bit 6:
Debounced CD1 bit (usually hook switch)
CD2 bit or CD1B bit
Bits 5–3: Reserved
Bit 2: CFAIL
Bits 1–0: Reserved
Bit 7 of the signaling byte appears immediately after bit 0 of the data byte. A-law or µ-law Companded mode must
be specified in order to put signaling information on the PCM highway. The signaling time slot remains active, even
when the channel is inactive.
11.16 Robbed-Bit Signaling Compatibility (PCM/MPI Mode)
The QLSLAC device supports robbed bit signaling compatibility. Robbed bit signaling allows periodic use of the
least significant bit (LSB) of the receive path PCM data to be used to carry signaling information. In this scheme,
separate circuitry within the line card or system intercepts this bit out of the PCM data stream and uses this bit to
control signaling functions within the system. The QLSLAC device does not perform any processing of any of the
robbed bits during this operation; it simply allows for the robbed bit presence by performing the LSB substitution.
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Data Sheet
If the RBE bit is set in the Channel Enable and Operating Mode register (MPI Command 4A/4Bh), then the robbed-
bit signaling compatibility mode is enabled. Robbed-bit signaling is only available in the µ-law companding mode of
the device. Also, only the receive (digital-to-analog) path is involved. There is no change of operation to the transmit
path and PCM data coming out of the QLSLAC device will always contain complete PCM byte data for each time
slot, regardless of robbed-bit signaling selection.
In the absence of actual PCM data for the affected time slots, there is an uncertainty of the legitimate value of this
bit to accurately reconstruct the analog signal. This bit can always be assumed to be a 1 or 0; hence, the
reconstructed signal is correct half the time. However, the other half of the time, there is an unacceptable
reconstruction error of a significance equal to the value weighting of the LSB. To reduce this error and provide
compatibility with the robbed bit signaling scheme, when in the robbed-bit signaling mode, the QLSLAC device
ignores the LSB of each received PCM byte and replaces its value in the expander with a value of half the LSB’s
weight. This then guarantees the reconstruction is in error by only half this LSB weight. In the expander, the eight
bits of the companded PCM byte are expanded into linear PCM data of several more bits within the internal signal
processing path of the device. Therefore, accuracy is not limited to the weight of the LSB, and a weight of half this
value is realizable.
When this robbed-bit mode is selected, not every frame contains bits for signaling, and therefore not every byte
requires its LSB substituted with the half-LSB weight. This substitution only occurs for valid PCM time slots within
frames for which this robbed bit has been designated. To determine which time slots are affected, the device
monitors the frame sync (FS) pulse. The current frame is a robbed-bit frame and this half-LSB value is used only
when this criteria is met:
•
•
•
•
The RBE bit is set, and
The device is in the µ-law companding mode, and
The current frame sync pulse (FS) is two PCLK cycles long, and
The previous frame sync pulse (FS) was not two PCLK cycles long.
The frame sync pulse is sampled on the falling edge of PCLK. As shown in Figure 25, if the above criteria is met,
and if FS is high for two consecutive falling edges of PCLK then low for the third falling edge, it is considered a
robbed-bit frame. Otherwise, it is a normal frame.
PCLK
FS
Normal Frame (Not Robbed-Bit)
PCLK
FS
Robbed-Bit Frame
Figure 25 - Robbed-Bit Frame
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Data Sheet
11.17 Default Filter Coefficients
The QLSLAC device contains an internal set of default coefficients for the programmable filters. The default filter
gains are calculated calculated based on the application circuit shown on page 104. This SLIC device has a
transmit gain of 0.5 (GTX) and a current gain of 500 (K1). The transmit relative level is set to +0.28 dBr, and the
receive relative level is set to –4.39 dBr. The equalization filters (X and R) are not optimized and the Z and B filters
are set to zero. The nominal input impedance was set to 812 Ω. If the SLIC device circuit differs significantly from
this design, the default gains cannot be used and must be replaced by programmed coefficients. The balance filter
(B) must always be programmed to an appropriate value.
To obtain this above-system response, the default filter coefficients are set to produce these values:
GX gain = +6 dB, GR gain = –8.984 dB
AX gain = 0 dB, AR gain = 0 dB, input attenuator on (DGIN = 0)
R filter: H(z) = 1, X filter: H(z) = 1
Z filter: H(z) = 0
B filter: H(z) = 0
AISN = cutoff
Notice that these default coefficient values are retained in a read-only memory area within the QLSLAC device, and
those values cannot be read back using any data commands. When the device is selected to use default
coefficients, it obtains those values directly from the read-only memory area, where the coefficient read operations
access the programmable random access data memory only. If an attempt is made to read back any filter values
without those values first being written with known programmed data, the values read back are totally random and
do not represent the default or any other values.
12.0 Command Description and Formats
12.1 Command Field Summary
A microprocessor can program and control the QLSLAC device using the MPI and GCI. Data programmed
previously can be read out for verification. See the tables below for the channel and global chip parameters
assigned.
Commands are provided to assign values to the following channel parameters:
Parameter
TTS
RTS
GX
Description
MPI
GCI
—
Transmit time slot
Receive time slot
Transmit gain
40/41h
42/43h
80/81h
82/83h
86/87h
96/97h
88/89h
8A/8Bh
98/99h
—
COP 2
COP 3
COP 5
COP 8
COP 6
COP 7
COP 4
GR
Receive loss
B1
B1-filter coefficients
B2-filter coefficients
X-filter coefficients
R-filter coefficients
Z-FIR filter coefficients
B2
X
R
ZFIR
Table 4 - Channel Parameters
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Zarlink Semiconductor Inc.
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Data Sheet
Parameter
ZIIR
Z
Description
Z-IIR filter coefficients
MPI
GCI
9A/9Bh
84/85h
50/51h
52h
COP 9
—
Z-filter coefficients (both FIR and IIR)
AISN coefficient
AISN
CD1–C7
IOD1–5
A/µ
COP1
SOP 10
SOP 8
SOP 7
—
Read SLIC device Outputs
SLIC device Input/Output Direction
Select A-law or µ-law
54/55h
60/61h
60/61h
40/41h
44/45h
42/43h
60/61h
60/61h
60/61h
60/61h
60/61h
60/61h
50/51h
50/51h
50/51h
70/71h
70/71h
70/71h
70/71h
70/71h
70/71h
70/71h
70/71h
E8/E9h
C/L
Compressed/linear
TPCM
TAB
RPCM
EB
Select Transmit PCM highway A or B
Transmit on A and B
—
—
Select Receive PCM highway A or B
Programmed/Default B filter
Programmed/Default Z filter
Programmed/Default X filter
Programmed/Default R filter
Programmed/Default GX filter
Programmed/Default GR filter
Disable input attenuator
Enable/disable AX amplifier
Enable/disable AR amplifier
Cutoff Transmit Path
—
SOP 7
SOP 7
SOP 7
SOP 7
SOP 7
SOP 7
COP 1
COP 1
COP 1
SOP 5
SOP 5
SOP 5
SOP 5
SOP 5
SOP 5
SOP 5
SOP 5
SOP 12
EZ
EX
ER
EGX
EGR
DGIN
AX
AR
CTP
CRP
HPF
LRG
ATI
Cutoff Receive Path
Disable High Pass Filter
Lower Receive Gain
Arm Transmit Interrupt
ILB
Interface Loopback
FDL
TON
GK
Full Digital Loopback
1 kHz Tone On
Ground Key Filter
55h
00h, 0Eh
SOP 8
SOP 1, SOP 4
CSTAT
Select Active or Inactive (Standby) mode
Table 4 - Channel Parameters
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Data Sheet
Commands are provided to read values from the following channel monitors:
Monitor
CD1–C5
CD1B
Description
Read SLIC device Inputs
Multiplexed SLIC device Input
Transmit PCM data
MPI
53h
53h
CDh
GCI
SOP 10
SOP 10
—
XDAT
Table 5 - Channel Monitors
Commands are provided to assign values to the following global chip parameters:
Parameter
XE
Description
Transmit PCM Clock Edge
Receive Clock Slot
MPI
GCI
—
44/45h
44/45h
44/45h
46/47h
46/47h
C8/C9h
46/47h
46/47h
46/47h
4A/4Bh
4A/4Bh
4A/4Bh
C8/C9h
C8/C9h
C8/C9h
C8/C9h
6C/6Dh
RCS
—
TCS
Transmit Clock Slot
—
INTM
CHP
Interrupt Output Drive Mode
Chopper Clock Frequency
Enable Chopper Clock Output
Select Signaling on the PCM Highway
Select Master Clock Mode
Select Master Clock Frequency
Robbed Bit Enable
SOP 6
SOP 6
SOP 11
—
ECH
SMODE
CMODE
CSEL
RBE
—
—
—
VMODE
EC
VOUT Mode
SOP 9
—
Channel Enable Register
Debounce Time for CD1
Enable E1 Output
DSH
SOP 11
SOP 11
SOP 11
—
EE1
E1P
E1 Polarity
DPCK
Double PCLK Operation
Interrupt Mask Register
Table 6 - Global Chip Parameters
MCDx
SOP 14
C
Commands are provided to read values from the following global chip status monitors:
Monitor
Description
Real Time Data Register
Clock Failure Bit
MPI
4D/4Fh
54/55h
73h
GCI
CDx
SOP 13, C/I
SOP 8
TOP 1
CIC
C
CFAIL
RCN
CONF
DT
Revision Code Number
Configuration (0000)
Device Type (10)
—
—
CIC
Table 7 - Global Chip Status Monitors
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Data Sheet
12.2 Microprocessor Interface Description
When PCM/MPI mode is selected via the CS/PG and DCLK/S0 pins, a microprocessor can be used to program the
QLSLAC device and control its operation using the Microprocessor Interface (MPI). Data programmed previously
can be read out for verification.
The following description of the MPI (Microprocessor Interface) is valid for channels 1– 4. If desired, multiple
channels can be programmed simultaneously with identical information by setting multiple Channel Enable bits.
Channel enables are contained in the Channel Enable register and are written or read using Command 4A/4Bh. If
multiple Channel Enable bits are set for a read operation, only data from the first enabled channel will be read.
The MPI physically consists of a serial data input/output (DIO), a data clock (DCLK), and a chip select (CS).
Individual Channel Enable bits EC1, EC2, EC3, and EC4 are stored internally in the Channel Enable register of the
QLSLAC device. The serial input consists of 8-bit commands that can be followed with additional bytes of input
data, or can be followed by the QLSLAC device sending out bytes of data. All data input and output is MSB (D7)
first and LSB (D0) last. All data bytes are read or written one at a time, with CS going High for at least a minimum off
period before the next byte is read or written. Only a single channel should be enabled during read commands.
All commands that require additional input data to the device must have the input data as the next N words written
into the device (for example, framed by the next N transitions of CS). All unused bits must be programmed as 0 to
ensure compatibility with future parts. All commands that are followed by output data will cause the device to output
data for the next N transitions of CS going Low. The QLSLAC device will not accept any commands until all the data
has been shifted out. The output values of unused bits are not specified.
An MPI cycle is defined by transitions of CS and DCLK. If the CS lines are held in the High state between accesses,
the DCLK may run continuously with no change to the internal control data. Using this method, the same DCLK can
be run to a number of QLSLAC devices, and the individual CS lines will select the appropriate device to access.
Between command sequences, DCLK can stay in the High state indefinitely with no loss of internal control
information regardless of any transitions on the CS lines. Between bytes of a multibyte read or write command
sequence, DCLK can also stay in the High state indefinitely. DCLK can stay in the Low state indefinitely with no loss
of internal control information, provided the CS lines remain at a High level.
If a low period of CS contains less than 8 positive DCLK transitions, it is ignored. If it contains 8 to 15 positive
transitions, only the last 8 transitions matter. If it contains 16 or more positive transitions, a hardware reset in the
part occurs. If the chip is in the middle of a read sequence when CS goes Low, data will be present at the DIO pin
even if DCLK has no activity. If CS is held low for two or more cycles of Frame Sync (FS) and DCLK is static (no
toggling), then the QLSLAC device switches to the General Circuit Interface mode of operation.
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Data Sheet
13.0 Summary of MPI Commands
Hex*
Description
00h
02h
Deactivate (Standby state)
Software Reset
04h
Hardware Reset
06h
No Operation
0Eh
Activate (Operational state)
40/41h
42/43h
44/45h
46/47h
4A/4Bh
4Dh
Write/Read Transmit Time Slot and PCM Highway Selection
Write/Read Receive Time Slot and PCM Highway Selection
Write/Read REC & TX Clock Slot and TX Edge
Write/Read Configuration Register
Write/Read Channel Enable & Operating Mode Register
Read Real Time Data Register
4Fh
Read Real Time Data Register and Clear Interrupt
Write/Read AISN and Analog Gains
Write/Read SLIC device Input/Output Register
Write/Read SLIC device Input/Output Direction and Status Bits
Write/Read Operating Functions
50/51h
52/53h
54,55h
60/61h
6C/6Dh
70/71h
73h
Write/Read Interrupt Mask Register
Write/Read Operating Conditions
Read Revision Code Number (RCN)
Write/Read GX Filter Coefficients
80/81h
82/83h
84/85h
86/87h
88/89h
8A/8Bh
96/97h
98/99h
9A/9Bh
C8/C9h
CDh
Write/Read GR Filter Coefficients
Write/Read Z Filter Coefficients (FIR and IIR)
Write/Read B1 Filter Coefficients (FIR)
Write/Read X Filter Coefficients
Write/Read R Filter Coefficients
Write/Read B2 Filter Coefficients (IIR)
Write/Read Z Filter Coefficients (FIR only)
Write/Read Z Filter Coefficients (IIR only)
Write/Read Debounce Time Register
Read Transmit PCM Data
E8/E9h
Write/Read Ground Key Filter Sampling Interval
Note:
*All codes not listed are reserved by Zarlink and should not be used.
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Data Sheet
14.0 MPI Command Structure
This section details each MPI command. Each command is shown along with the format of any additional data
bytes that follow. For details of the filter coefficients of the form Cxymxy, refer to the General Description of CSD
Coefficients section page 98.
Unused bits are indicated by “RSVD”; 0’s should be written to them, but 0’s are not guaranteed when they are read.
*Default field values are marked by an asterisk. A hardware reset forces the default values.
14.1 00h Deactivate (Standby State)
MPI Command
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
Command
In the Deactivate (Standby) state:
All programmed information is retained.
The Microprocessor Interface (MPI) remains active.
The PCM inputs are disabled and the PCM outputs are high impedance unless signaling on the
PCM highway is programmed (SMODE = 1).
The analog output (VOUT) is disabled and biased at VREF.
The channel status (CSTAT) bit in the SLIC device I/O Direction and Channel Status Register is set to
0.
14.2 02h Software Reset
MPI Command
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
1
D0
0
Command
The action of this command is identical to that of the RST pin except that it only operates on the channels selected
by the Channel Enable Register and it does not change clock slots, time slots, PCM highways, ground key
sampling interval or global chip parameters. See the note under the hardware reset command that follows.
14.3 04h Hardware Reset
MPI Command
D7
0
D6
0
D5
0
D4
0
D3
0
D2
1
D1
0
D0
0
Command
Hardware reset is equivalent to pulling the RST on the device Low. This command does not depend on the state of
the Channel Enable Register.
Note:
The action of a hardware reset is described in Reset States on page 43 of the section Operating the QLSLAC Device.
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Zarlink Semiconductor Inc.
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Data Sheet
14.4 06h No Operation
MPI Command
D7
0
D6
0
D5
0
D4
0
D3
0
D2
1
D1
1
D0
Command
0
14.5 0Eh Activate Channel (Operational State)
MPI Command
D7
0
D6
0
D5
0
D4
0
D3
1
D2
1
D1
1
D0
0
Command
This command places the device in the Active mode and sets CSTAT = 1. No valid PCM data is transmitted until
after the second FS pulse is received following the execution of the Activate command.
14.6 40/41h Write/Read Transmit Time Slot and PCM Highway Selection
MPI Command
R/W = 0: Write
R/W = 1: Read
D7
D6
D5
D4
D3
D2
D1
D0
Command
I/O Data
0
1
0
0
0
0
0
R/W
TPCM
TTS6
TTS5
TTS4
TTS3
TTS2
TTS1
TTS0
Transmit PCM Highway
TPCM = 0*
TPCM = 1
Transmit on Highway A (see TAB in Commands 44/45h)
Transmit on Highway B (see TAB in Commands 44/45h)
Transmit Time Slot
TTS = 0–127
Time Slot Number (TTS0 is LSB, TTS6 is MSB)
PCM Highway B is not available on the Le58QL061 QLSLAC device.
* Power Up and Hardware Reset (RST) Value = 00h, 01h, 02h, 03h for channels 1, 2, 3, and 4, respectively.
14.7 42/43h Write/Read Receive Time Slot and PCM Highway Selection
MPI Command
R/W = 0: Write
R/W = 1: Read
D7
D6
D5
D4
D3
D2
D1
D0
Command
I/O Data
0
1
0
0
0
0
1
R/W
RPCM
RTS6
RTS5
RTS4
RTS3
RTS2
RTS1
RTS0
Receive PCM Highway
RPCM = 0*
RPCM = 1
Receive on Highway A
Receive on Highway B
Receive Time Slot
RTS = 0–127 Time Slot Number (RTS0 is LSB, RTS6 is MSB)
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Data Sheet
PCM Highway B is not available on the Le58QL061 device.
* Power Up and Hardware Reset (RST) Value = 00h, 01h, 02h, 03h for channels 1, 2, 3, and 4, respectively.
14.8 44/45h Write/Read Transmit Clock Slot, Receive Clock Slot, and Transmit Clock Edge
MPI Command
R/W = 0: Write
R/W = 1: Read
D7
D6
D5
D4
D3
D2
D1
D0
Command
I/O Data
0
1
0
0
0
1
0
R/W
TAB
XE
RCS2
RCS1
RCS0
TCS2
TCS1
TCS0
Transmit on A and B
TAB = 0*
TAB = 1
Transmit data on highway selected by TPCM (see Commands 40/41h).
Transmit data on both highways A and B
Transmit Edge (Global parameter)
XE = 0*
XE = 1
Transmit changes on negative edge of PCLK
Transmit changes on positive edge of PCLK
Receive Clock Slot (Global parameter)
RCS = 0*–7
Receive Clock Slot number
Transmit Clock Slot (Global parameter)
TCS = 0*–7
Transmit Clock Slot number
The XE bit and the clock slots apply to all four channels; however, they cannot be written or read unless at least one
channel is selected in the Channel Enable Register; however, TAB is channel specific.
* Power Up and Hardware Reset (RST) Value = 00h.
14.9 46/47h Write/Read Chip Configuration Register
MPI Command
R/W = 0: Write
R/W = 1: Read
D7
D6
D5
D4
D3
D2
D1
D0
Command
I/O Data
0
1
0
0
0
1
1
R/W
INTM
CHP
SMODE
CMODE
CSEL3
CSEL2
CSEL1
CSEL0
Interrupt Mode (Global parameter)
INTM = 0
TTL-compatible output
Open drain output
INTM = 1*
Chopper Clock Control (Global parameter)
CHP = 0*
CHP = 1
Chopper Clock is 256 kHz (2048/8 kHz)
Chopper Clock is 292.57 kHz (2048/7 kHz)
PCM Signaling Mode (Global parameter)
SMODE = 0*
SMODE = 1
No signaling on PCM highway
Signaling on PCM highway
Clock Source Mode (Global parameter)
CMODE = 0
CMODE = 1*
MCLK used as master clock; no E1 multiplexing allowed
PCLK used as master clock; E1 multiplexing allowed if enabled in Command
C8/C9h.
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Zarlink Semiconductor Inc.
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Data Sheet
The master clock frequency can be selected by CSEL. The master clock frequency selection affects all channels.
Master Clock Frequency (Global parameter)
CSEL = 0000 1.536 MHz
CSEL = 0001 1.544 MHz
CSEL = 0010 2.048 MHz
CSEL = 0011 Reserved
CSEL = 01xx
Two times frequency specified above (2 x 1.536 MHz,
2 x 1.544 MHz, or 2 x 2.048 MHz)
CSEL = 10xx
Four times frequency specified above (4 x 1.536 MHz,
4 x 1.544 MHz, or 4 x 2.048 MHz)
CSEL = 11xx
Reserved
CSEL = 1010* 8.192 MHz is the default
These commands do not depend on the state of the Channel Enable Register.
* Power Up and Hardware Reset (RST) Value = 9Ah.
14.10 4A/4Bh Write/Read Channel Enable and Operating Mode Register
MPI Command
R/W = 0: Write
R/W = 1: Read
D7
D6
D5
D4
D3
D2
D1
D0
Command
I/O Data
0
1
0
0
1
0
1
R/W
EC1
RSVD
RBE
VMODE
LPM
EC4
EC3
EC2
RSVD
Reserved for future use. Always write as 0, but 0 is not guaranteed when read
Robbed-bit Mode (Global parameter)
RBE = 0*
RBE = 1
Robbed-bit Signaling mode is disabled
Robbed-bit Signaling mode is enabled on PCM receiver if µ-law is selected
VOUT Mode (Global parameter)
VMODE = 0*
VOUT = VREF through a resistor when channel is deactivated
VOUT high impedance when channel is deactivated
VMODE = 1
Low Power Mode (Global parameter)
LPM
LPM reduced the power in the QSLAC device, but it is not needed and not used
in the QLSLAC device
Channel Enable 4
Channel Enable 3
Channel Enable 2
Channel Enable 1
EC4 = 0
EC4 = 1*
Disabled, channel 4 cannot receive commands
Enabled, channel 4 can receive commands
EC3 = 0
EC3 = 1*
Disabled, channel 3 cannot receive commands
Enabled, channel 3 can receive commands
EC2 = 0
EC2 = 1*
Disabled, channel 2 cannot receive commands
Enabled, channel 2 can receive commands
EC1 = 0
EC1 = 1*
Disabled, channel 1 cannot receive commands
Enabled, channel 1 can receive commands
* Power Up and Hardware Reset (RST) Value = 0Fh.
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Data Sheet
14.11 4D/4Fh Read Real-Time Data Register
MPI Command
C = 0: Do not clear interrupt
C = 1: Clear interrupt
This register reads real-time data with or without clearing the interrupt.
D7
D6
D5
D4
D3
D2
D1
D0
Command
0
1
0
0
1
1
C
1
CDB4
CDA4
CDB3
CDA3
CDB2
CDA2
CDB1
CDA1
Output Data
Real Time Data
CDA
Debounced data bit 1 on channel 1
1
1
2
2
3
3
4
4
CDB
CDA
CDB
CDA
CDB
CDA
CDB
Data bit 2 or multiplexed data bit 1 on channel 1
Debounced data bit 1 on channel 2
Data bit 2 or multiplexed data bit 1 on channel 2
Debounced data bit 1 on channel 3
Data bit 2 or multiplexed data bit 1 on channel 3
Debounced data bit 1 on channel 4
Data bit 2 or multiplexed data bit 1 on channel 4
This command does not depend on the state of the Channel Enable Register.
14.12 50/51h Write/Read AISN and Analog Gains
MPI Command
R/W = 0: Write
R/W = 1: Read
D7
D6
D5
D4
D3
D2
D1
D0
Command
I/O Data
0
1
0
1
0
0
0
R/W
DGIN
AX
AR
AISN4
AISN3
AISN2
AISN1
AISN0
Disable Input Attenuator (GIN)
DGIN = 0*
Input attenuator on
Input attenuator off
DGIN = 1
Transmit Analog Gain
AX = 0*
0 dB gain
AX = 1
6.02 dB gain
Receive Analog Loss
AR = 0*
0 dB loss
AR = 1
6.02 dB loss
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Data Sheet
AISN coefficient
AISN = 0* – 31 See below (Default value = 0)
The Impedance Scaling Network (AISN) gain can be varied from −0.9375 •GIN to +0.9375 •
GIN in multiples of 0.0625 •GIN.
The gain coefficient is decoded using the following equation:
hAISN = 0.0625 • GIN [(16 • AISN4 + 8 • AISN3 + 4 • AISN2 + 2 • AISN1 + AISN0) – 16]
where h
is the gain of the AISN. A value of AISN = 10000 turns on the Full Digital Loopback
AISN
mode and a value of AISN = 0000* indicates a gain of 0 (cutoff).
* Power Up and Hardware Reset (RST) Value = 00h.
14.13 52/53h Write/Read SLIC Device Input/Output Register
MPI Command
R/W = 0: Write
R/W = 1: Read
D7
D6
D5
D4
D3
D2
D1
D0
Command
I/O Data
0
1
0
1
0
0
1
R/W
CD1
C7
C6
CD1B
C5
C4
C3
CD2
Pins CD1, CD2, and C3 through C7 are set to 1 or 0. The data appears latched on the CD1, CD2, and C3 through
C5 SLIC device I/O pins, provided they were set in the Output mode (see Command 54/55h).
The data sent to any of the pins set to the Input mode is latched, but does not appear at the pins.
The CD1B bit is only valid if the E1 Multiplex mode is enabled (EE1 = 1). C7 and C6 are outputs
only and are not available on all package types.
* Power Up and Hardware Reset (RST) Value = 00h
14.14 54/55h Write/Read SLIC Device Input/Output Direction, Read Status Bits
MPI Command
R/W = 0: Write
R/W = 1: Read
D7
D6
D5
D4
D3
D2
D1
D0
Command
Input Data
0
1
0
1
0
1
0
R/W
RSVD
CSTAT
CFAIL
IOD5
IOD4
IOD3
IOD2
IOD1
RSVD
Reserved for future use. Always write as 0, but 0 is not guaranteed when read.
Channel Status (Read status only, write as 0)
CSTAT = 0
CSTAT = 1
Channel is inactive (Standby state).
Channel is active.
Clock Fail (Read status only, write as 0) (Global status bit)
CFAIL* = 0
CFAIL = 1
The internal clock is synchronized to frame synch.
The internal clock is not synchronized to frame synch.
* The CFAIL bit is independent of the Channel Enable Register.
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Data Sheet
I/O Direction (Read/Write)
IOD5 = 0*
C5 is an input
IOD5 = 1
IOD4 = 0*
C5 is an output
C4 is an input
IOD4 = 1
IOD3 = 0*
C4 is an output
C3 is an input
IOD3 = 1
IOD2 = 0*
IOD2 = 1
IOD1 = 0*
C3 is an output
CD2 is an input
CD2 is an output
CD1 is an input
CD1 is an output
IOD1 = 1
Pins CD1, CD2, and C3 through C5 are set to Input or Output modes individually.
* Power Up and Hardware Reset (RST) Value = 00h
14.15 60/61h Write/Read Operating Functions
MPI Command
R/W = 0: Write
R/W = 1: Read
D7
D6
D5
D4
D3
D2
D1
D0
Command
I/O Data
0
1
1
0
0
0
0
R/W
EB
C/L
A/µ
EGR
EGX
EX
ER
EZ
Linear Code
A-law or µ-law
GR Filter
GX Filter
X Filter
C/L = 0*
C/L = 1
Compressed coding
Linear coding
A/µ = 0*
A/µ = 1
A-law coding
µ-law coding
EGR = 0*
EGR = 1
Default GR filter enabled
Programmed GR filter enabled
EGX = 0*
EGX = 1
Default GX filter enabled
Programmed GX filter enabled
EX = 0*
EX = 1
Default X filter enabled
Programmed X filter enabled
R Filter
ER = 0*
ER = 1
Default R filter enabled
Programmed R filter enabled
Z Filter
EZ = 0*
EZ = 1
Default Z filter enabled
Programmed Z filter enabled
B Filter
EB = 0*
EB = 1
Default B filter enabled
Programmed B filter enabled
* Power Up and Hardware Reset (RST) Value = 00h.
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Data Sheet
14.16 6C/6Dh Write/Read Interrupt Mask Register
MPI Command
R/W = 0: Write
R/W = 1: Read
D7
D6
D5
D4
D3
D2
D1
D0
Command
I/O Data
0
1
1
0
1
1
0
R/W
MCDB4
MCDA4
MCDB3
MCDA3
MCDB2
MCDA2
MCDB1
MCDA1
Mask CD Interrupt
MCDx = 0
CDx bit is NOT MASKED
C
C
MCDx = 1*
CDx bit is MASKED
C
C
x
Bit number (A or B)
C
Channel number (1 through 4)
Masked: A change does not cause the Interrupt Pin to go Low.
This command does not depend on the state of the Channel Enable Register.
* Power Up and Hardware Reset (RST) Value = FFh.
14.17 70/71h Write/Read Operating Conditions
MPI Command
R/W = 0: Write
R/W = 1: Read
D7
D6
D5
D4
D3
D2
D1
D0
Command
I/O Data
0
1
1
1
0
0
0
R/W
TON
CTP
CRP
HPF
LRG
ATI
ILB
FDL
Cutoff Transmit Path
CTP = 0*
CTP = 1
Transmit path connected
Transmit path cut off
Cutoff Receive Path
CRP = 0*
CRP = 1
Receive path connected
Receive path cutoff (see note)
High Pass Filter
HPF = 0*
HPF = 1
Transmit Highpass filter enabled
Transmit Highpass filter disabled
Lower Receive Gain
LRG = 0*
LRG = 1
6 dB loss not inserted
6 dB loss inserted
Arm Transmit Interrupt
ATI = 0*
ATI = 1
Transmit Interrupt not Armed
Transmit Interrupt Armed
Interface Loopback
ILB = 0*
ILB = 1
TSA loopback disabled
TSA loopback enabled
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Full Digital Loopback
FDL = 0*
FDL = 1
Full digital loopback disabled
Full digital loopback enabled
1 kHz Receive Tone
TON = 0*
TON = 1
1 kHz receive tone off
1 kHz receive tone on
* Power Up and Hardware Reset (RST) Value = 00h.
The B Filter is disabled during receive cutoff.
14.18 73h Read Revision Code Number (RCN)
MPI Command
D7
D6
D5
D4
D3
D2
D1
D0
Command
I/O Data
0
1
1
1
0
0
1
1
RCN7
RCN6
RCN5
RCN4
RCN3
RCN2
RCN1
RCN0
This command returns an 8-bit number (RCN) describing the revision number of the QLSLAC device. The revision
code of the QLSLAC device will be 14h or higher. This command does not depend on the state of the Channel
Enable Register.
14.19 80/81h Write/Read GX Filter Coefficients
MPI Command
R/W = 0: Write
R/W = 1: Read
D7
D6
0
D5
D4
0
D3
D2
0
D1
D0
Command
1
0
0
0
R/W
I/O Data Byte 1
I/O Data Byte 2
C40
C20
m40
m20
C30
C10
m30
m10
Cxy = 0 or 1 in the command above corresponds to Cxy = +1 or −1, respectively, in the equation below.
The coefficient for the GX filter is defined as:
HGX = 1 + (C10 • 2–m10{1 + C20 • 2–m20[1 + C30 • 2–m30(1 + C40 • 2–m40)]}
Power Up and Hardware Reset (RST) Values = A9F0 (Hex) (H = 1.995 (6 dB)).
GX
Note:
The default value is contained in a ROM register separate from the programmable coefficient RAM. There is a filter enable bit in Operating Func-
tions Register to switch between the default and programmed values.
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14.20 82/83h Write/Read GR Filter Coefficients
MPI Command
R/W = 0: Write
R/W = 1: Read
D7
D6
0
D5
D4
0
D3
D2
0
D1
D0
R/W
Command:
1
0
0
1
I/O Data Byte 1
I/O Data Byte 2
C40
C20
m40
m20
C30
C10
m30
m10
Cxy = 0 or 1 in the command above corresponds to Cxy = +1 or −1, respectively, in the equation below.
The coefficient for the GR filter is defined as:
HGR = C10 • 2–m10{1 + C20 • 2–m20[1 + C30 • 2–m30(1 + C40 • 2–m40)]}
Power Up and Hardware Reset (RST) Values = 23A1 (Hex) (H = 0.35547 (–8.984 dB)).
GR
See note under Command 80/81h on page 63.
14.21 84/85h Write/Read Z Filter Coefficients (FIR and IIR)
MPI Command
R/W = 0: Write
R/W = 1: Read
This command writes and reads both the FIR and IIR filter sections simultaneously.
D7
D6
0
D5
D4
0
D3
D2
1
D1
D0
Command
1
0
0
0
R/W
I/O Data Byte 1
I/O Data Byte 2
I/O Data Byte 3
I/O Data Byte 4
I/O Data Byte 5
I/O Data Byte 6
I/O Data Byte 7
I/O Data Byte 8
I/O Data Byte 9
I/O Data Byte 10
I/O Data Byte 11
I/O Data Byte 12
I/O Data Byte 13
I/O Data Byte 14
I/O Data Byte 15
C40
C20
C41
C21
C42
C22
C43
C23
C44
C24
C45
C25
C26
C47
C27
m40
m20
m41
m21
m42
m22
m43
m23
m44
m24
m45
m25
m26
m47
m27
C30
C10
C31
C11
C32
C12
C33
C13
C34
C14
C35
C15
C16
C37
C17
m30
m10
m31
m11
m32
m12
m33
m13
m34
m14
m35
m15
m16
m37
m17
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Cxy = 0 or 1 in the command above corresponds to Cxy = +1 or −1, respectively, in the equation below.
The Z-transform equation for the Z filter is defined as:
z5 • z6 • z7 • z–1
Hz(z) = z0 + z1 • z–1 + z2 • z–2 + z3 • z–3 + z4 • z–4
------------------------------------------
+
1 – z7 • z–1
Sample rate = 32 kHz
For i = 0 to 5 and 7
zi = C1i • 2–m1i{1 + C2i • 2–m2i[1 + C3i • 2–m3i(1 + C4i • 2–m4i)]}
z6 = C16 • 2–m16{1 + C26 • 2–m26
Power Up and Hardware Reset (RST) Values = 0190 0190 0190 0190 0190 0190 01 0190 (Hex)
}
(H (z) = 0)
z
See note under Command 80/81h on page 63.
Note:
Z6 is used for IIR filter scaling only. Its value is typically greater than zero but less than or equal to one. The input to the IIR filter section is first
increased by a gain of 1/Z6, improving dynamic range and avoiding truncation limitations through processing within this filter. The IIR filter output
is then multiplied by Z6 to normalize the overall gain. Z5 is the actual IIR filter gain value defined by the programmed coefficients, but it also in-
cludes the initial 1/Z6 gain. The theoretical effective IIR gain, without the Z6 gain and normalization, is actually Z5/Z6.
14.22 86/87h Write/Read B1 Filter Coefficients
MPI Command
R/W = 0: Write
R/W = 1: Read
D7
D6
0
D5
D4
0
D3
D2
1
D1
D0
Command
1
0
0
1
R/W
I/O Input Data Byte 1
I/O Input Data Byte 2
I/O Input Data Byte 3
I/O Input Data Byte 4
I/O Input Data Byte 5
I/O Input Data Byte 6
I/O Input Data Byte 7
I/O Input Data Byte 8
I/O Input Data Byte 9
I/O Input Data Byte 10
I/O Input Data Byte 11
I/O Input Data Byte 12
I/O Input Data Byte 13
I/O Input Data Byte 14
C32
C12
C23
C34
C14
C25
C36
C16
C27
C38
C18
C29
C310
C110
m32
m12
m23
m34
m14
m25
m36
m16
m27
m38
m18
m29
m310
m110
C22
C33
C13
C24
C35
C15
C26
C37
C17
C28
C39
C19
C210
RSVD
m22
m33
m13
m24
m35
m15
m26
m37
m17
m28
m39
m19
m210
RSVD
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Cxy = 0 or 1 in the command above corresponds to Cxy = +1 or −1, respectively, in the equation below.
The Z-transform equation for the B filter is defined as:
B10 • z–10
HB(z) = B2 • z–2 + … + B9 • z–9
--------------------------------
+
1 – B11 • z–1
Sample rate = 16 kHz
The coefficients for the FIR B section and the gain of the IIR B section are defined as:
For i = 2 to 10,
Bi = C1i • 2–mli[1 + C2i • 2–m2i(1 + C3i • 2–m3i)]
The feedback coefficient of the IIR B section is defined as
B11 = C111 • 2–m111{1 + C211 • 2–m211[1 + C311 • 2–m311(1 + C411 • 2–m411)]}
Refer to Command 96/97h for programming of the B coefficients.
11
Power Up and Hardware Reset (RST) Values = 09 00 90 09 00 90 09 00 90 09 00 90 09 00 (Hex)
HB(z) = 0
See note under Command 80/81h on page 63.
RSVD
Reserved for future use. Always write as 0, but 0 is not guaranteed when read.
14.23 88/89h Write/Read X Filter Coefficients
MPI Command
R/W = 0: Write
R/W = 1: Read
D7
D6
0
D5
D4
0
D3
D2
0
D1
D0
Command
1
0
1
0
R/W
I/O Input Data Byte 1
I/O Input Data Byte 2
I/O Input Data Byte 3
I/O Input Data Byte 4
I/O Input Data Byte 5
I/O Input Data Byte 6
I/O Input Data Byte 7
I/O Input Data Byte 8
I/O Input Data Byte 9
I/O Input Data Byte 10
I/O Input Data Byte 11
I/O Input Data Byte 12
C40
C20
C41
C21
C42
C22
C43
C23
C44
C24
C45
C25
m40
m20
m41
m21
m42
m22
m43
m23
m44
m24
m45
m25
C30
C10
C31
C11
C32
C12
C33
C13
C34
C14
C35
C15
m30
m10
m31
m11
m32
m12
m33
m13
m34
m14
m35
m15
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Cxy = 0 or 1 in the command above corresponds to Cxy = +1 or −1, respectively, in the equation below.
The Z-transform equation for the X filter is defined as:
Hx(z) = x0 + x1z–1 + x2z–2 + x3z–3 + x4z–4 + x5z–5
Sample rate = 16 kHz
For i = 0 to 5, the coefficients for the X filter are defined as:
Xi = C1i • 2–m1i{1 + C2i • 2–m2i[1 + C3i • 2–m3i(1 + C4i • 2–m4i)]}
Power Up and Hardware Reset (RST) Values = 0111 0190 0190 0190 0190 0190 (Hex)
(Hx(z) = 1)
See note under Command 80/81h on page 63.
14.24 8A/8Bh Write/Read R Filter Coefficients
MPI Command
R/W = 0: Write
R/W = 1: Read
D7
D6
0
D5
D4
0
D3
D2
0
D1
D0
Command
1
0
1
1
R/W
I/O Input Data Byte 1
I/O Input Data Byte 2
I/O Input Data Byte 3
I/O Input Data Byte 4
I/O Input Data Byte 5
I/O Input Data Byte 6
I/O Input Data Byte 7
I/O Input Data Byte 8
I/O Input Data Byte 9
I/O Input Data Byte 10
I/O Input Data Byte 11
I/O Input Data Byte 12
I/O Input Data Byte 13
I/O Input Data Byte 14
C46
C26
C40
C20
C41
C21
C42
C22
C43
C23
C44
C24
C45
C25
m46
m26
m40
m20
m41
m21
m42
m22
m43
m23
m44
m24
m45
m25
C36
C16
C30
C10
C31
C11
C32
C12
C33
C13
C34
C14
C35
C15
m36
m16
m30
m10
m31
m11
m32
m12
m33
m13
m34
m14
m35
m15
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Cxy = 0 or 1 in the command above corresponds to Cxy = +1 or −1, respectively, in the equation below.
HR = HIIR • HFIR
The Z-transform equation for the IIR filter is defined as:
1 – z–1
-----------------------------------
=
HIIR
–1
⎞
⎠
⎛
1 – R6 • z
⎝
Sample rate = 8 kHz
The coefficient for the IIR filter is defined as:
R6 = C16 • 2–ml6{1 + C26 • 2–m26[1 + C36 • 2–m36(1 + C46 • 2–m46)]}
The Z-transform equation for the FIR filter is defined as:
HFIR(z) = R0 + R1z–1 + R2z–2 + R3z–3 + R4z–4 + R5z–5
Sample rate = 16 kHz
For i = 0 to 5, the coefficients for the R2 filter are defined as:
Ri = C1i • 2–m1i{1 + C2i • 2–m2i[1 + C3i • 2–m3i(1 + C4i • 2–m4i)]}
Power Up and Hardware Reset (RST) Values = 2E01 0111 0190 0190 0190 0190 0190 (Hex)
(HFIR (z) = 1, R6 = 0.9902)
See note under Command 80/81h on page 63.
14.25 96/97h Write/Read B2 Filter Coefficients (IIR)
MPI Command
R/W = 0: Write
R/W = 1: Read
D7
D6
0
D5
D4
1
D3
D2
1
D1
D0
Command
1
0
0
1
R/W
I/O Data Byte 1
I/O Data Byte 2
C411
C211
m411
m211
C311
C111
m311
m111
This function is described in Write/Read B1 Filter Coefficients (FIR) on page 65.
Power Up and Hardware Reset (RST) Values = 0190 (Hex) (B = 0)
11
See note under Command 80/81h on page 63.
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14.26 98/99h Write/Read FIR Z Filter Coefficients (FIR only)
MPI Command
R/W = 0: Write
R/W = 1: Read
This command writes and reads only the FIR filter section without affecting the IIR.
D7
D6
0
D5
D4
1
D3
D2
0
D1
D0
R/W
Command
1
0
1
0
I/O Data Byte 1
I/O Data Byte 2
I/O Data Byte 3
I/O Data Byte 4
I/O Data Byte 5
I/O Data Byte 6
I/O Data Byte 7
I/O Data Byte 8
I/O Data Byte 9
I/O Data Byte 10
C40
C20
C41
C21
C42
C22
C43
C23
C44
C24
m40
m20
m41
m21
m42
m22
m43
m23
m44
m24
C30
C10
C31
C11
C32
C12
C33
C13
C34
C14
m30
m10
m31
m11
m32
m12
m33
m13
m34
m14
Cxy = 0 or 1 in the command above corresponds to Cxy = +1 or −1, respectively, in the equation below.
The Z-transform equation for the Z filter is defined as:
z5 • z6 • z7 • z–1
Hz(z) = z0 + z1 • z–1 + z2 • z–2 + z3 • z–3 + z4 • z–4
------------------------------------------
+
1 – z7 • z–1
Sample rate = 32 kHz
For i = 0 to 5 and 7
zi = C1i • 2–m1i{1 + C2i • 2–m2i[1 + C3i • 2–m3i(1 + C4i • 2–m4i)]}
z6 = C16 • 2–m16{1 + C26 • 2–m26
}
Power Up and Hardware Reset (RST) Values = 0190 0190 0190 0190 0190 0190 01 0190 (Hex)
(Hz(z) = 0)
See note under Command 80/81h on page 63.
Note:
Z6 is used for IIR filter scaling only. Its value is typically greater than zero but less than or equal to one. The input to the IIR filter section is first
increased by a gain of 1/Z6, improving dynamic range and avoiding truncation limitations through processing within this filter. The IIR filter output
is then multiplied by Z6 to normalize the overall gain. Z5 is the actual IIR filter gain value defined by the programmed coefficients, but it also in-
cludes the initial 1/Z6 gain. The theoretical effective IIR gain, without the Z6 gain and normalization, is actually Z5/Z6.
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14.27 9A/9Bh Write/Read IIR Z Filter Coefficients (IIR only)
MPI Command
R/W = 0: Write
R/W = 1: Read
This command writes/reads the IIR filter section only, without affecting the FIR.
D7
D6
0
D5
D4
1
D3
D2
0
D1
D0
R/W
Command
1
0
1
1
I/O Data Byte 1
I/O Data Byte 2
I/O Data Byte 3
I/O Data Byte 4
I/O Data Byte 5
C45
C25
C26
C47
C27
m45
m25
m26
m47
m27
C35
C15
C16
C37
C17
m35
m15
m16
m37
m17
Cxy = 0 or 1 in the command above corresponds to Cxy = +1 or −1, respectively, in the equation below.
The Z-transform equation for the Z filter is defined as:
z5 • z6 • z7 • z–1
Hz(z) = z0 + z1 • z–1 + z2 • z–2 + z3 • z–3 + z4 • z–4
------------------------------------------
+
1 – z7 • z–1
Sample rate = 32 kHz
For i = 0 to 5 and 7
zi = C1i • 2–m1i{1 + C2i • 2–m2i[1 + C3i • 2–m3i(1 + C4i • 2–m4i)]}
z6 = C16 • 2–m16{1 + C26 • 2–m26
}
Power Up and Hardware Reset (RST) Values = 0190 0190 0190 0190 0190 0190 01 0190 (Hex)
(Hz(z) = 0)
See note under Command 80/81h on page 63.
Note:
Z6 is used for IIR filter scaling only. Its value is typically greater than zero but less than or equal to one. The input to the IIR filter
section is first increased by a gain of 1/Z6, improving dynamic range and avoiding truncation limitations through processing within
this filter. The IIR filter output is then multiplied by Z6 to normalize the overall gain. Z5 is the actual IIR filter gain value defined by
the programmed coefficients, but it also includes the initial 1/Z6 gain. The theoretical effective IIR gain, without the Z6 gain and
normalization, is actually Z5/Z6.
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14.28 C8/C9h Write/Read Debounce Time Register
This command applies to all channels and does not depend on the state of the Channel Enable Register.
MPI Command
R/W = 0: Write
R/W = 1: Read
D7
D6
D5
D4
D3
D2
D1
D0
Command
I/O Data
1
1
0
0
1
0
0
R/W
ECH
EE1
E1P
DSH3
DSH2
DSH1
DSH0
DPCK
Enable E1 (Global parameter)
EE1 = 0*
E1 multiplexing turned off
E1 multiplexing turned on
EE1 = 1
E1 Polarity (Global parameter)
E1P = 0*
E1P = 1
E1 is a high-going pulse
E1 is a low-going pulse
There is no E1 output unless CMODE = 1.
Debounce for hook switch (Global parameter)
DSH = 0–15 Debounce period in ms
DSH contains the debouncing time (in ms) of the CD1 data (usually hook switch) entering the
Real Time Data register described earlier. The input data must remain stable for the debouncing
time in order to change the appropriate real time bit.
Default = 8 ms
Double PCLK Operation (Global parameter)
DPCK = 0* Double PCLK operation is off. PCLK and PCM data at same rate.
DPCK = 1
Double PCLK enabled. PCLK operates at twice the PCM data rate.
Enable Chopper (Global parameter)
ECH = 0*
ECH = 1
Chopper output (CHCLK) turned off
Chopper output (CHCLK) turned on
* Power Up and Hardware Reset (RST) Value = 20h.
14.29 CDh Read Transmit PCM Data (PCM/MPI Mode Only)
MPI Command
D7
D6
D5
D4
D3
D2
D1
D0
Command
1
1
0
0
1
1
0
1
Output Data Byte 1
Output Data Byte 2
XDAT7
RSVD
XDAT6
RSVD
XDAT5
RSVD
XDAT4
RSVD
XDAT3
RSVD
XDAT2
RSVD
XDAT1
RSVD
XDAT0
RSVD
RSVD
Upper Transmit Data
XDAT contains A-law or µ-law transmit data in Companded mode.
Reserved for future use. Always write as 0, but 0 is not guaranteed when read.
XDAT contains upper data byte in Linear mode with sign in XDAT7.
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14.30 E8/E9h Write/Read Ground Key Filter
MPI Command
R/W = 0: Write
R/W = 1: Read
D7
D6
D5
D4
D3
D2
D1
D0
Command
I/O Data
1
1
1
0
1
0
0
R/W
GK0
RSVD
RSVD
RSVD
RSVD
GK3
GK2
GK1
Filter Ground Key
GK = 0–15
Filter sampling period in 1 ms
GK contains the filter sampling time (in ms) of the CD1B data (usually Ground Key) or CD2 entering the Real Time
Data register described earlier. A value of 0 disables the Ground Key filter for that particular channel.
Power Up and Hardware Reset (RST) Value = x0h.
RSVD
Reserved for future use. Always write as 0, but 0 is not guaranteed when read.
15.0 General Circuit Interface (GCI) Specifications
15.1 GCI General Description
When the CS/PG device pin is connected to DGND and DCLK/S0 is static (not toggling), GCI operation is selected.
The QLSLAC device conforms to the GCI standard where data for eight GCI channels are combined into one serial
bit stream. A GCI channel contains the control and voice data for two analog channels of the QLSLAC device. Two
GCI channels are required to access all four channels of the QLSLAC device. The QLSLAC device sends Data
Upstream out of the DU pin and receives Downstream Data on the DD pin. Data clock rate and frame
synchronization information goes to the QLSLAC device on the DCL (Data Clock) and FSC input pins, respectively.
Two of eight GCI channels are selected by connecting the S0 and S1 channel selection pins on the QLSLAC device
to DGND or VCCD as shown in Table 8.
S1
S0
GCI Channels #
0 & 1
DGND
DGND
VCCD
VCCD
DGND
VCCD
DGND
VCCD
2 & 3
4 & 5
6 & 7
Table 8 - GCI Channel Assignment Codes
In the time slot control block (shown in Figure 26), the Frame Sync (FSC) pulse identifies the beginning of the
Transmit and Receive frames and all GCI channels are referenced to it. Voice (B1 and B2), C/I, and monitor data
are sent to the Upstream Multiplexer where they are combined and serially shifted out of the DU pin during the
selected GCI Channels. The Downstream Demultiplexer uses the same channel control block information to
demultiplex the incoming GCI channels into separate voice (B1 and B2), C/I, and monitor data bytes.
The QLSLAC device supports an eight GCI channel bus (16 analog channels). The external clock applied to the
DCL pin is either 2.048 MHz or 4.096 MHz. The QLSLAC device determines the incoming clock frequency and
adjusts internal timing automatically to accommodate single or double clock rates.
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Voice data for B1 byte
Voice data for B2 byte
Upstream
DU
Multiplexer
C/I Data
Monitor Data
FS
S0
S1
Time Slot
Control
DCL
Voice data for B1 byte
Voice data for B2 byte
Downstream
Demultiplexer
DD
C/I Data
Monitor Data
Figure 26 - Time Slot Control and GCI Interface
15.2 GCI Format and Command Structure
The GCI interface provides communication of both control and voice data between the GCI highway and subscriber
line circuits over a single pair of pins on the QLSLAC device. A complete GCI frame is sent upstream on the DU pin
and received downstream on the DD pin every 125 µs. Each frame consists of eight 4 byte GCI channels (CHN0
to 7) that contain voice and control information for eight pairs of channels. A particular channel pair is identified by
its position within the frame (see Figure 27). Therefore, a total of 16 voice channels can be uniquely addressed
each frame. The overall structure of the GCI frame is shown in Figure 27.
The 4 byte GCI channel contains the following:
•
•
•
2 bytes; B1 and B2 for voice channels 1 and 2.
One Monitor (M) byte for reading/writing control data/coefficients to the QLSLAC device for both channels.
One Signaling and Control (SC) byte containing a 6-bit Command/Indicate (C/I) channel for control
information and a 2-bit field with Monitor Receive and Monitor Transmit (MR, MX) bits for handshaking
functions for both channels. All principal signaling (real-time critical) information is carried on the C/I
channel. The QLSLAC device utilizes the full C/I channel capacity of the GCI channel.
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FS
0−3
4−7
8−11
12−15
16−19
20−23
24−27
28−31
CHN7
CHN0
CHN1
CHN2
CHN3
CHN4
CHN5
CHN6
DU, DD
8
8
8
8
B1
B2
M
2
SC
0
1
3
6
1
1
C/I
MR
M
Figure 27 - Multiplexed GCI Time Slot Structure
15.3 Signaling and Control (SC) Channel
The upstream and downstream SC channels are continuously carrying I/O information every frame to and from the
QLSLAC device in the C/I field. This allows the upstream processor to have immediate access to the output
(downstream) and input (upstream) data present on the QLSLAC device’s programmable I/O port.
The MR and MX bits are used for handshaking during data exchanges on the monitor channel.
Downstream C/I Channel
The QLSLAC device receives the MSBs first.
The downstream C/I channel SC octet definition depends on the device package type. The 44-pin package does
not have provisions for pin connections to accommodate all SLIC device outputs, which otherwise are available on
the higher pin count devices. For the 44-pin package device, the downstream SC octet is defined as:
<---------------- Downstream SC Octet ------------------>
MSB
LSB
0
7
6
5
4
3
2
1
C5x
C4x
C3x
CD2x CD1x
A
MR
MX
|<------------------- C/I Field ------------------->|
For the 64-pin package, this octet is defined as:
<---------------- Downstream SC Octet ------------------>
MSB
LSB
0
7
6
5
4
3
2
1
C7C
C6C
C5C
C4C
C3C
A
MR
MX
|<------------------- C/I Field ------------------->|
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Data Sheet
A: Channel Address Bit
0: Selects CH 1 or 3 as the downstream data destination
1: Selects CH 2 or 4 as the downstream data destination
C5 –CD2 CD1 : SLIC device output latch bits 5–1 for CHx of the channel selected by A. (44-pin package)
C
C
C
C7 –C3 : SLIC device output latch bits 7–3 of the channel selected by A. (64-pin package)
C
C
C = 1 or 2, the channel selected by A
If the QLSLAC device’s programmable I/O ports, CD1, CD2, and C3 are programmed for Input mode, then data is
obtained through the Upstream C/I channel.
Figure 28 shows the transmission protocol for the downstream C/I. Whenever the received pattern of C/I bits 6–1 is
different from the pattern currently in the C/I input register, the new pattern is loaded into a secondary C/I register
and a latch is set. When the next pattern is received (in the following frame) while the latch is set, the following rules
apply:
1. If the received pattern corresponds to the pattern in the secondary register, the new pattern is loaded into the C/I
register for the addressed channel and the latch is reset. The updated C/I register data appears at the program-
mable I/O pins of the device one frame (125 µs) later if they are programmed as outputs.
2. If the received pattern is different from the pattern in the secondary register and different from the pattern cur-
rently in the C/I register, the newly received pattern is loaded into the secondary C/I register and the latch
remains set. The data at the PI/O port remains unchanged.
3. If the received pattern is the same as the pattern currently in the C/I register, the C/I register is unchanged and
the latch is reset.
Receive New C/I Code
Yes
=
I ?
No
I: C/I Register Contents
Store in S
S: C/I Secondary Register Contents
Receive New C/I Code
Yes
Yes
Load C/I Register
with New Code
=
S ?
No
=
I ?
No
Figure 28 - Security Procedure for C/I Downstream Bytes
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Data Sheet
Upstream C/I Channel
The SC channel, which includes the six C/I channel bits, is transmitted upstream every frame. The bit definitions for
the upstream C/I channel are shown below. These bits are transmitted by the QLSLAC device (Most significant bit
first).
GCI Format
<------------------------ Upstream SC Octet ------------------>
MSB
7
LSB
0
6
5
4
3
2
1
C31
CDB1 CDA1
C32
CDB2 CDA2
MR
MX
|<----------------------- C/I FIELD ------------->|
Upstream Bit Definitions of the C/I field require the programmable I/O ports to be programmed as inputs. Otherwise,
these bits follow the downstream C/I bits for CD1 , CD2 , and C3 .
C
C
C
CDA : Debounced CD1 bit of channel x.
C
C
CDB : The filtered CD2 bit of channel x in non-E1 demultiplexed mode or the filtered CD1B bit in the E1
C
C
C
demultiplexed mode.
C3 –C3 of channel C.
C
C
In GCI mode, C4 and C5 are not available as upstream C/I data but can be obtained by reading the SLIC device I/O
register.
15.4 Monitor Channel
The Monitor Channel (see Figure 29) is used to read and write the QLSLAC device’s coefficient registers, to read
the status of the device and the contents of the internal registers, and to provide supplementary signaling.
Information is transferred on the Monitor Channel using the MR and MX bits of the SC channel, providing a secure
method of data exchange between the upstream and downstream devices.
The Monitor byte is the third byte in the 4 byte GCI channel and is received every 125 µs over the DU or DD pins. A
Monitor command consists of one address byte, one or more command bytes, and is followed by additional bytes of
input data as required. The command may be followed by the QLSLAC device sending data bytes upstream via the
DU pin.
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Data Sheet
Monitor Channel Protocol
2nd Byte
1st Byte
3rd Byte
MX
Transmitter
MX
EOM
MR
Receiver
MR
ACK
1st Byte
ACK
2nd Byte
ACK
3rd Byte
125 µs
Figure 29 - Maximum Speed Monitor Handshake Timing
•
•
An inactive (high) MX and MR pair bit for two or more consecutive frames shows an idle state on the monitor
channel and the end of message (EOM).
Figure 29 shows that transmission is initiated by the transition of the transmitter MX bit from the inactive to
the active state. The transition coincides with the beginning of the first byte sent on the monitor channel. The
receiver acknowledges the first byte by setting MR bit to active and keeping it active for at least one more
frame.
•
•
The same data must be received in two consecutive frames in order to be accepted by the receiver.
The same byte is sent continuously in each of the succeeding frames until either a new byte is transmitted,
the end of message, or an abort.
•
•
Any false MX or MR bit received by the receiver or transmitter leads to a request for abort or an abort,
respectively.
For maximum data transfer speed, the transmitter anticipates the falling edge of the receiver's
acknowledgment, as shown in Figure 29.
Figure 30 and Figure 31 are state diagrams that define the operation of the monitor transmitter and receiver
sections in the QLSLAC device.
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Data Sheet
Idle
MX=1
Initial
state
MR⋅RQT
1st byte
MX=0
MR⋅RQT
MR⋅RQT
nth byte
ACK, MX=1
MR
MR⋅RQT
MR
MR⋅RQT
wait for
ACK, MX=0
MR ... MR- bit received
MX ... MX - bit calculated and expected on the DU line
RQT ... Request for transmission frominternal source
Figure 30 - Monitor Transmitter Mode Diagram
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Data Sheet
Idle
MR = 1
MX • LL
MX
Initial
State
MX
1st Byte
Received
MR = 0
Abort
MR = 1
ABT
Any
State
MX
MX
MX
Byte
Valid
MR = 0
MX • LL
Wait for
LL MR = 0
MX • LL
MX
MX • LL
MX
MX
MX • LL
nth Byte
Received
MR = 1
New Byte
MR = 1
Wait for
LL MR = 0
MX
21108A-033
MR: MR bit transmitted on DU line
MX: MX bit received on DD line
LL: Last look at monitor byte received
ABT: Abort indication from internal source
Figure 31 - Monitor Receiver State Diagram
15.5 Programming with the Monitor Channel
The QLSLAC device uses the monitor channel for the transfer of status or mode information to and from higher
level processors.
The messages transmitted in the monitor channel have different data structures. The first byte of monitor channel
data indicates the address of the device either sending or receiving the data.
All Monitor channel messages to and from the QLSLAC device begin with the following address byte::
D7
1
D6
0
D5
0
D4
A
D3
B
D2
0
D1
0
D0
C
Address
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A = 0; Channel 1 is the source (upstream) or destination (downstream)
A = 1; Channel 2 is the source (upstream) or destination (downstream)
B = 0; Data destination determined by A
B = 1; Both channels, 1 and 2, receive the data
C = 0; Address for channel identification command
C = 1; Address for all other commands
The monitor channel address byte is followed by a command byte. If the command byte specifies a write, then from
1 to 14 additional data bytes may follow (see Table 9). If the control byte specifies a read, additional data bytes may
follow. The QLSLAC device responds to the read command by sending up to 14 data bytes upstream containing the
information requested by the upstream controller. Shown next is the generic byte transmission sequence over the
GCI monitor channel.
GCI Monitor Channel
Downstream
Upstream
ADDRESS
Control byte, write
Data byte 1*
•
Data byte m*
ADDRESS
Control byte, read
Data byte 1
•
Data Byte n
m ≤ 14
n ≤ 14
Table 9 - Generic Byte Transmission Sequence
Note:
* May or may not be present
15.6 Channel Identification Command (CIC)
When the monitor channel address byte is 80H or 90H, a command of 00H is interpreted by the QLSLAC device as
a two byte Channel Identification Command (CIC).
The format for this command is shown next.:
D7
D6
D5
D4
D3
D2
D1
D0
Address Byte
1
0
0
0
0
0
A
0
0
0
0
0
0
0
0
0
Command Byte
A = 0
A = 1
Channel 1 is the destination
Channel 2 is the destination
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Immediately after the last bit of the CIC command is received, the QLSLAC device responds with the 2 byte
channel ID code:
D7
D6
D5
D4
D3
D2
D1
D0
Byte 1
Byte 2
1
0
0
0
A
0
CONF
0
CONF
1
CONF
1
CONF
0
DT
DT
A = 0
A = 1
Channel 1 is the source
Channel 2 is the source
CONF
DT
Configuration value is always 0000 for the QLSLAC device
Device Type value is always 1,0: Analog Transceiver. Other types are defined as:
D7
0
D6
0
Description
U Transceiver
0
1
S Transceiver
Analog Transceiver
Future
1
0
1
1
15.7 General Structure of Other Commands
When the QLSLAC device has completed transmission of the channel ID information, it sends an EOM (MX = 1 for
two successive frames) on the upstream C/I channel. The QLSLAC device also expects an EOM to be received on
the downstream C/I channel before any further message sequences are received.
When the monitor channel address byte is 81h, 89h, 91h, or 99h, the command byte is interpreted by the QLSLAC
device as either a Transfer Operation (TOP), Status Operation (SOP), or a Coefficient Operation (COP).
D7
1
D6
0
D5
0
D4
A
D3
B
D2
0
D1
0
D0
1
Address Byte
A = 0; Channel 1 is the destination
A = 1; Channel 2 is the destination
B = 0; Data destination determined by A
B = 1; Both channels 1 and 2 receive the data
Commands are sent to the QLSLAC device to:
•
•
•
Read the status of the system without changing its operation (Transfer Operation (TOP) command)
Write/read the QLSLAC device operating state (Status Operation (SOP) command)
Write/read filter coefficients (Coefficient Operation (COP) command).
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Data Sheet
16.0 Summary of Monitor Channel Commands (GCI Commands)
Commands
C#
Hex
Description
Channel Information
Command
Channel Identification Command (CIC); Requires unique address byte (80h,
90h)
CIC
00h
Transfer Operation
Commands
TOP 1
73h
Read revision code number
SOP 1
SOP 2
SOP 3
SOP 4
SOP 5
SOP 6
SOP 7
00h
02h
04h
0Eh
Deactivate channel
Software Reset
Hardware Reset
Activate channel
70/71h Write/Read Operating Conditions (Configuration Register 1, CR1)
46/47h Write/Read Chip Configuration (Configuration Register 2, CR2)
60/61h Write/Read Operating Functions (Configuration Register 3, CR3)
Status Operation
Commands
Write/Read SLIC device I/O direction and Status Bits (Configuration Register
4, CR4)
SOP 8
54/55h
SOP 9
4A/4Bh Write/Read Operating Mode (Configuration Register 5, CR5)
SOP 10
53h
Read SLIC device I/O Register
SOP 11 C8/C9h Write/Read Debounce Time Register
SOP 12 E8/E9h Write/Read Ground Key Filter Sampling Interval
SOP 13 4D/4Fh Read Real-Time Data Register
SOP 14 6C/6Dh Write/Read Interrupt Mask Register
COP 1
COP 2
COP 3
COP 4
COP 5
COP 6
COP 7
COP 8
COP 9
50/51h Write/Read AISN & Analog gains
80/81h Write/Read GX Filter Coefficients
82/83h Write/Read GR Filter Coefficients
98/99h Write/Read Z Filter Coefficients (FIR)
86/87h Write/Read B1 Filter Coefficients (FIR)
88/89h Write/Read X Filter Coefficients
8A/8Bh Write/Read R Filter Coefficients
96/97h Write/Read B2 Filter Coefficients (IIR)
9A/9Bh Write/Read Z Filter (IIR)
Coefficient Operation
Commands
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Data Sheet
16.1 TOP (Transfer Operation) Command
The TOP (transfer operation) command, a GCI command, is used when no status modification of the QLSLAC
device is required. The byte transmission sequence for a TOP command is shown in Table 10.
GCI Monitor Channel
Downstream
Upstream
ADDRESS
Control byte, TOP read
TOP Byte 1
•
•
TOP Byte n
n ≤ 14
Table 10 - Byte Transmission Sequence for TOP Command
TOP 1. Read Revision Code Number (RCN)
GCI Command
(73h)
D7
D6
D5
D4
D3
D2
D1
D0
Command
0
1
1
1
0
0
1
1
Output Data
RCN7
RCN6
RCN5
RCN4
RCN3
RCN2
RCN1
RCN0
The revision code of the QLSLAC device will be 14h or higher.
16.2 SOP (Status Operation) Command
To modify or evaluate the QLSLAC device status, the contents of configuration registers CR1–CR5 and the SLIC
device I/O register can be transferred to and from the QLSLAC device. This is done by a SOP (Status Operation)
command, which is a GCI command. The general transmission sequence of the SOP command is shown in Table
11.
GCI Monitor Channel
Downstream
Upstream
ADDRESS
Control byte, SOP write
CR1
•
•
CRm
SOP Read
CR1
•
•
CRn
m ≤ 7
n ≤ 8
Table 11 - General Transmission Sequence of SOP Command
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Data Sheet
16.3 SOP Control Byte Command Format
SOP 1. Deactivate Channel (Standby Mode)
GCI Command
(00h)
D7
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
Command
0
0
In the Deactivated (Standby) mode:
All of the programmed information is retained.
The upstream and downstream Monitor and SC channels remain active.
The B channel for an inactive channel is idle, no data is received or transmitted.
The analog output (VOUT) is disabled and biased at VREF.
The Channel Status (CSTAT bit in the SLIC device I/O and Status Bits register is set to 0.
SOP 2. Software Reset
GCI Command
(02h)
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
1
D0
0
Command
The action of this command is identical to that of the RST pin except it only operates on the addressed channel and
does not reset the ground key filtering interval.
SOP 3. Hardware Reset
GCI Command
(04h)
D7
0
D6
0
D5
0
D4
0
D3
0
D2
1
D1
0
D0
0
Command
The Hardware reset command is equivalent to pulling the RST pin on the device low. This command resets all four
channels of the device. The action of the Hardware reset function is described in Reset States on page 43.
SOP 4. Activate Channel (Operational Mode)
GCI Command
(0Eh)
D7
0
D6
0
D5
0
D4
0
D3
1
D2
1
D1
1
D0
0
Command
This command places the addressed channel of the device in the Active mode. No valid B-Channel data is
transmitted until after the second FSC pulse is received following the execution of the Activate command. The
Channel Status (CSTAT) bit in the SLIC device I/O and Status Bits register is set to 1.
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SOP 5. Write/Read Configuration Register 1 (CR1), Operating Conditions
GCI Command
(70/71h)
Operating Conditions (Configuration Register 1, CR1)
D7
D6
D5
D4
D3
D2
D1
D0
Command
I/O Data
0
1
1
1
0
0
0
R/W
TON
CTP
CRP
HPF
LRG
ATI
ILB
FDL
Configuration register CR1 enables or disables test features and controls feeding states. The reset value of CR1 =
04H
Cutoff Transmit Path
CTP = 0*
CTP = 1
Transmit path connected
Transmit path disconnected
Cutoff Receive Path**
CRP = 0*
CRP = 1
Receive path connected
Receive path cutoff
High Pass Filter
HPF = 0*
HPF = 1
Transmit Highpass filter enabled
Transmit Highpass filter disabled
Lower Receive Gain
LRG = 0*
LRG = 1
6 dB loss not inserted
6 dB loss inserted
Arm Transmit Interrupt
ATI = 0*
ATI = 1
Transmit interrupt not armed
Transmit interrupt armed
Interface Loop Back
ILB = 0*
ILB = 1
Interface (GCI) loopback disabled
Interface (GCI) loopback enabled
Full Digital Loopback
FDL = 0*
FDL = 1
Full Digital Loopback disabled
Full Digital Loopback enabled
1 kHz Receive Tone
TON = 0*
TON = 1
1 kHz receive tone off
1 kHz receive tone on
Power Up and Hardware Reset (RST) Value = 00h
**B Filter is disabled during receive cutoff.
SOP 6. Write/Read Configuration Register 2 (CR2), Chip Configuration
GCI Command
(46/47h)
Chip Configuration (Configuration Register 2, CR2)
D7
D6
D5
D4
D3
D2
D1
D0
Command
I/O Data
0
1
0
0
0
1
1
R/W
INTM
CHP
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
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Interrupt Mode (Global parameter)
INTM = 0
INTM = 1
TTL-compatible output
Open drain output
Chopper Clock Control (Global parameter)
CHP = 0*
CHP = 1
Chopper Clock is 256 kHz (2048/8 kHz)
Chopper Clock is 292.57 kHz (2048/7 kHz)
RSVD:
Reserved for future use. Always write as 0, but 0 is not guaranteed when read.
* Power Up and Hardware Reset (RST) Value = 9Ah
SOP 7. Write/Read Configuration Register 3 (CR3), Operating Functions
GCI Command
(60/61h)
Operating Functions (Configuration Register 3, CR3)
D7
D6
D5
D4
D3
D2
D1
D0
Command
I/O Data
0
1
1
0
0
0
0
R/W
EB
RSVD
A/µ
EGR
EGX
EX
ER
EZ
RSVD:
Reserved for future use. Always write as 0, but 0 is not guaranteed when read.
A-law/µ-law
A/µ = 0*
A/µ = 1
A-law coding
µ-law coding
GR filter
GX filter
X filter
R filter
Z filter
EGR = 0*
EGR = 1
GR filter default coefficients used:
GR filter programmed coefficients used
EGX = 0*
EGX = 1
GX filter default coefficients used
GX filter programmed coefficients used
EX = 0*
EX = 1
X filter default coefficients used
X filter programmed coefficients used
ER = 0*
ER = 1
R filter default coefficients used
R filter programmed coefficients used
EZ = 0*
EZ = 1
Z filter default coefficients used
Z filter programmed coefficients used
B filter
EB = 0*
EB = 1
B filter default coefficients used
B filter programmed coefficients used
*Power Up and Hardware Reset (RST) Value = 00h
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SOP 8. Write/Read Configuration Register 4 (CR4), SLIC Device I/O Direction and Status Bits
GCI Command
(54/55h)
SLIC Device I/O Direction and Status Bits (Configuration Register 4, CR4)
D7
D6
D5
D4
D3
D2
D1
D0
Command
I/O Data
0
1
0
1
0
1
0
R/W
RSVD
CSTAT
CFAIL
IOD5
IOD4
IOD3
IOD2
IOD1
Pins CD1, CD2 and C3 through C5 are set to Input or Output modes individually.
RSVD: Reserved for future use. Always write as 0, but 0 is not guaranteed when read.
Channel Status (Read only, write as 0)
CSTAT = 0
CSTAT = 1
Channel is inactive (Standby mode)
Channel is active
Clock Fail (Read only, write as 0; Global status bit)
CFAIL = 0
CFAIL = 1
The internal clock is synchronized to frame sync
The internal clock is not synchronized to frame sync
The CFAIL bit is universal for the QLSLAC device and is independent of the channel addressed.
IOD1–IOD5
Programmable I/O direction control (CD1, CD2, C3, C4, C5 pins)
*0 = Pin is set as an input port
1 = Pin is set as an output port
*Power Up and Hardware Reset (RST) Value = 00h
SOP 9. Write/Read Configuration Register 5 (CR5), Operating Mode
GCI Command
(4A/4Bh)
Operating Mode (Configuration Register 5, CR5)
D7
0
D6
1
D5
D4
D3
1
D2
0
D1
1
D0
Command
I/O Data
0
0
R/W
RSVD
VMODE
LPM
RSVD
RSVD:
Reserved for future use. Always write as 0, but 0 is not guaranteed when read.
VOUT Mode (Global parameter)
VMODE = 0*
VOUT = VREF through a resistor when channel is inactive
VOUT high impedance when channel is inactive.
VMODE = 1
Low Power Mode (Global parameter)
LPM
LPM reduced the power in the QSLAC device, but it is not needed and not used
in the
QLSLAC device
Power Up and Hardware Reset (RST) Value = 0Fh
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SOP 10. Read SLIC Device Input/Output Register
GCI Command
(53h)
D7
D6
D5
D4
D3
D2
D1
D0
Command
0
1
0
1
0
0
1
1
Output Data
C7
C6
CD1B
C5
C4
C3
CD2
CD1
The logic states present on the CD1, CD2, C3, C4, and C5 pins of the QLSLAC device for the addressed channel
are read using this command, independent of their programmed direction (see SLIC device I/O Direction Register).
CD1B is the multiplexed CD1 bit and is valid only if the E1 multiplexing mode is enabled (EE = 1). If CD1, CD2, C3,
C4, and C5 are programmed as inputs, then the logic states reported are determined by the external driving signal.
In addition, CDA (the debounced state of CD1) and CDB (the debounced state of CD2, non-E1 multiplexed mode)
or CD1B (E1 multiplexed mode), and the logic state present on the C3 pin of the device are sent directly upstream
on the C/I bits of the upstream SC channel. If the CD1, CD2, C3, C4, and C5 pins are programmed as outputs then
the logic states of these pins are controlled directly by the bits present in the C/I portion of the downstream SC
channel and are not sent directly upstream in the SC channel. This command is normally used only to read the bit
status via Command 53h. It is also possible although not recommended, if the CD1, CD2, and C3–C7 pins are
programmed as outputs, to write the output state as Command 52h. The register is programmed upon execution of
Command 52h but the status is overwritten when the next C/I portion of the downstream SC channel is received.
SOP 11. Write/Read Debounce Time Register*
GCI Command
(C8/C9h)
D7
D6
D5
D4
D3
D2
D1
D0
Command
I/O Data
1
1
0
0
1
0
0
R/W
ECH
EE1
E1P
DSH3
DSH2
DSH1
DSH0
RSVD
Enable E1 (Global parameter)
EE1 = 0*
E1 Multiplexing is turned off
E1 Multiplexing is turned on
EE1 = 1
E1 Polarity (Global parameter)
E1P = 0*
E1P = 1
E1 is a high-going pulse
E1 is a low-going pulse
Debounce for hook switch (Global parameter)
DSH = 0–15 Debounce period in ms
DSH contains the debouncing time in ms of the CD1 data (usually hook switch) entering the
CD1B bit of the read SLIC device Input/Output register and the CD1B transmitted on the
C/I bit of the upstream SC channel. The input data on CD1 must remain stable for the
debounce time in order for the state of CD1B to change.
Default = 8 ms
RSVD
Reserved for future use. Always write as 0, but 0 is not guaranteed when read.
Enable Chopper (Global parameter)
ECH = 0*
Chopper clock output is turned off.
Chopper clock output is turned on.
ECH = 1
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Power Up and Hardware Reset (RST) Value = 20h
Note:
* This command applies to all four channels of the device.
SOP 12. Write/Read Ground Key Filter Sampling Interval
GCI Command
(E8/E9h)
R/W = 0: Write
R/W = 1: Read
D7
D6
D5
D4
D3
D2
D1
D0
Command
I/O Data
1
1
1
0
1
0
0
R/W
GK0
RSVD
RSVD
RSVD
RSVD
GK3
GK2
GK1
Filter Ground Key
GK = 0–15
Filter sampling period in ms
GK contains the filter sampling time (in ms) of the CD1B data (usually Ground Key) or CD2 enter-
ing the upstream C/I channel described earlier.
RSVD
Reserved for future use. Always write as 0, but 0 is not guaranteed when read.
Power Up and Hardware Reset (RST) Value = x0h.
SOP 13. Read Real-Time Data Register
GCI Command
(4D/4Fh)
C = 0: Do not clear interrupt
C = 1: Clear interrupt
This register reads real-time data with or without closing the interrupt.
D7
D6
D5
D4
D3
D2
D1
D0
Command
I/O Data
0
1
0
0
1
1
C
1
CDB4
CDA4
CDB3
CDA3
CDB2
CDA2
CDB1
CDA1
Real Time Data
CDA
Debounced data bit 1 on Channel 1
1
1
2
2
3
3
4
4
CDB
CDA
CDB
CDB
CDA
CDB
CDA
Data bit 2 or multiplexed data bit 1 on Channel 1
Debounced data bit 1 on Channel 2
Data bit 2 or multiplexed data bit 1 on Channel 2
Debounced data bit 1 on Channel 3
Data bit 1 on Channel 3
Debounced data bit 1 on Channel 4
Data bit 2 or multiplexed data bit 1 on Channel 4
This data is also available in the C/I field of the upstream SC channel.
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SOP 14. Write/Read Interrupt Mask Register
GCI Command
(6C/6Dh)
R/W = 0: Write
R/W = 1: Read
D7
D6
D5
D4
D3
D2
D1
D0
Command
I/O Data
0
1
1
0
1
1
0
R/W
MCDB4
MCDA4
MCDB3
MCDA3
MCDB2
MCDA2
MCDB1
MCDA1
Mask CD Interrupt
MCDx = 0
CDx bit is NOT MASKED
C
C
MCDx = 1*
CDx bit is MASKED
C
C
x
Bit number (A or B)
C
Channel number (1 through 4)
Masked
A change does not cause the Interrupt Pin to go Low.
*Power Up and Hardware Reset (RST) Value = FFh
16.4 COP (Coefficient Operation) Command
The COP command, which is a GCI command, writes or reads data related to filter coefficients. Filter coefficient
data is used by the voice processors within the QLSLAC device to configure the various filters in the voice channel.
In this case, 1 to 14 coefficient bytes follow the command byte. The QLSLAC device interprets the bytes as canonic
signed digital (CSD) data and sets the coefficients accordingly.
The QLSLAC device responds to the read coefficient command by sending up to 14 CSD bytes upstream. These
bytes contain the coefficients requested by the upstream controller. For diagnostic purposes, various RAM locations
containing data to which the QLSLAC device has access can also be read back by this command.
The generic transmission sequence for the COP command is shown in Table 12.
Downstream
Upstream
ADDRESS
Command byte, COP write
Data1
•
•
Datam
Control byte, COP read
Data1
•
•
Datan
m ≤ 14
n ≤ 14
Table 12 - Generic Transmission Sequence for COP Command
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The following tables show the format of the COP bytes that follow a downstream address byte.
D7
D6
D5
D4
D3
D2
D1
D0
Command
Data
CMD
CMD
CMD
CMD
CMD
CMD
CMD
CMD
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
Data
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
The format in the upstream direction is the same except that the command byte is omitted.
16.5 Details of COP, CSD Data Commands
This section describes in detail each of the monitor channel COP commands. Each of the commands is shown
along with the format of any additional data bytes that follow. For details of the filter coefficients of the form C m ,
xy xy
please refer to the Description of Coefficients section on page 98.
COP 1. Write/Read AISN Coefficients and Analog Gains
GCI Command
(50/51h)
R/W = 0: Write
R/W = 1: Read
D7
D6
D5
D4
D3
D2
D1
D0
Command
I/O Data
0
1
0
1
0
0
0
W/R
DGIN
AX
AR
AISN4
ASIN3
AISN2
AISN1
AISN0
Disable Input Attenuator (GIN)
DGIN = 0*
Input attenuator on
Input attenuator off
DGIN = 1
Transmit analog gain
AX = 0*:
0 dB gain
AX = 1:
6.02 dB gain
Receive Analog Loss
AR = 0*:
0 dB loss
AR = 1:
6.02 dB loss
AISN coefficient
AISN = 0*–31 See below (Default value = 0)
The Analog Impedance Scaling Network (AISN) gain can be varied from −0.9375 •GIN to
+0.9375 •GIN in multiples of 0.0625 •GIN. The gain coefficient is decoded using the following
equation:
hAISN = 0.0625 • GIN [(16 • AISN4 + 8 • AISN3 + 4 • AISN2 + 2 • AISN1 + AISN0) – 16]
where h
is the gain of the AISN. A value of AISN = 10000 turns on the Full Digital Loopbackmode
AISN
* Power Up and Hardware Reset (RST) Value = 00h
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COP 2. Write/Read GX Filter Coefficients
GCI Command
(80/81h)
R/W = 0: Write
R/W = 1: Read
D7
D6
0
D5
D4
0
D3
D2
0
D1
D0
W/R
Command
1
0
0
0
Coefficient Byte 1
Coefficient Byte 2
C40
C20
m40
m20
C30
C10
m30
m10
Cxy = 0 or 1 in the command above corresponds to Cxy = +1 or −1, respectively, in the equation below.
The coefficient for the GX filter is defined as:
HGX = (1 + (C10 • 2–m10(1 + C20 • 2–m20(1 + C30 • 2–m30(1 + C40 • 2–m40)))))
Power Up and Hardware Reset (RST) Value = A9F0h, (H = 1.995, or +6 dB)
GX
Note:
The default value is contained in a ROM register separate from the programmable coefficient RAM. There is a filter enable bit in Operating Func-
tions Register to switch between the default and programmed values.
COP 3. Write/Read GR Filter Coefficients
GCI Command
(82/83h)
R/W = 0: Write
R/W = 1: Read
D7
D6
0
D5
D4
0
D3
D2
0
D1
D0
Command
1
0
0
1
W/R
Coefficient Byte 1
Coefficient Byte 2
C40
C20
m40
m20
C30
C10
m30
m10
Cxy = 0 or 1 in the command above corresponds to Cxy = +1 or −1, respectively, in the equation below.
The coefficient for the GR filter is defined as:
HGR = (C10 • 2–m10(1 + C20 • 2–m20(1 + C30 • 2–m30(1 + C40 • 2–m40))))
Power Up and Hardware Reset (RST) Value = 23A1h, (H = 0.35547, or –8.984 dB)
GR
See note under COP Command 2.
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COP 4. Write/Read Z Filter FIR Coefficients
GCI Command
(98/99h)
R/W = 1: Read
R/W = 0: Write
This command writes and reads only the FIR portion of the Z filter without affecting the IIR.
D7
D6
0
D5
D4
1
D3
D2
0
D1
D0
Command
1
0
1
0
R/W
I/O Data Byte 1
I/O Data Byte 2
I/O Data Byte 3
I/O Data Byte 4
I/O Data Byte 5
I/O Data Byte 6
I/O Data Byte 7
I/O Data Byte 8
I/O Data Byte 9
I/O Data Byte 10
C40
C20
C41
C21
C42
C22
C43
C23
C44
C24
m40
m20
m41
m21
m42
m22
m43
m23
m44
m24
C30
C10
C31
C11
C32
C12
C33
C13
C34
C14
m30
m10
m31
m11
m32
m12
m33
m13
m34
m14
Cxy = 0 or 1 in the command above corresponds to Cxy = +1 or −1, respectively, in the equation below.
The Z-transform equation for the Z filter is defined as:
z5 • z6 • z7 • z–1
Hz(z) = z0 + z1 • z–1 + z2 • z–2 + z3 • z–3 + z4 • z–4
------------------------------------------
+
1 – z7 • z–1
Sample rate = 32 kHz
For i = 0–5 and 7
zi = C1i • 2–m1i{1 + C2i • 2–m2i[1 + C3i • 2–m3i(1 + C4i • 2–m4i)]}
z6 = C16 • 2–m16{1 + C26 • 2–m26
}
Power Up and Hardware Reset (RST) Values = 0190 0190 0190 0190 0190 0190 01 0190 (Hex)
(H (z) = 0)
z
See note under COP Command 2 on page 92.
Note:
Z6 is used for IIR filter scaling only. Its value is typically greater than zero but less than or equal to one. The input to the IIR filter section is first
increased by a gain of 1/Z6, improving dynamic range and avoiding truncation limitations through processing within this filter. The IIR filter output
is then multiplied by Z6 to normalize the overall gain. Z5 is the actual IIR filter gain value defined by the programmed coefficients, but it also in-
cludes the initial 1/Z6 gain. The theoretical effective IIR gain, without the Z6 gain and normalization, is actually Z5/Z6.
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COP 5. Write/Read B1 Filter Coefficients (B-FIR)
GCI Command
(86/87h)
R/W = 1: Read
R/W = 0: Write
D7
D6
0
D5
D4
0
D3
D2
1
D1
D0
R/W
Command
1
0
0
1
I/O Data Byte 1
I/O Data Byte 2
I/O Data Byte 3
I/O Data Byte 4
I/O Data Byte 5
I/O Data Byte 6
I/O Data Byte 7
I/O Data Byte 8
I/O Data Byte 9
I/O Data Byte 10
I/O Data Byte 11
I/O Data Byte 12
I/O Data Byte 13
I/O Data Byte 14
C32
C12
C23
C34
C14
C25
C36
C16
C27
C38
C18
C29
C310
C110
m32
m12
m23
m34
m14
m25
m36
m16
m27
m38
m18
m29
m310
m110
C22
C33
C13
C24
C35
C15
C26
C37
C17
C28
C39
C19
C210
m22
m33
m13
m24
m35
m15
m26
m37
m17
m28
m39
m19
m210
RSVD
Cxy = 0 or 1 in the command above corresponds to Cxy = +1 or −1, respectively, in the equation below.
The Z-transform equation for the B filter is defined as:
B10 • z–10
HB(z) = B2 • z–2 + … + B9 • z–9
------------------------------
+
1 – B11 • z–1
Sample rate = 16 kHz
The coefficients for the FIR B section and the gain of the IIR B section are defined as:
Bi = C1i • 2–m1i[1 + C2i • 2–m2i(1 + C3i • 2–m3i)]
For i = 2 to 10,
The feedback coefficient of the IIR B section is defined as:
B11 = C111 • 2–m111{1 + C211 • 2–m211[1 + C311 • 2–m311(1 + C411 • 2–m411)]}
Refer to Command COP8 for programming the B coefficients.
11
Power Up and Hardware Reset (RST) Values = 09 00 90 09 00 90 09 00 90 09 00 90 09 00 (Hex)
HB(z) = 0
RSVD:
Reserved for future use. Reset to 0. Always write as 0, but 0 is not guaranteed when read.
See note under COP Command 2 on page 92.
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COP 6. Write/Read X Filter Coefficients
GCI Command
(88/89h)
R/W = 1: Read
R/W = 0: Write
D7
D6
0
D5
D4
0
D3
D2
0
D1
D0
W/R
Command
1
0
1
0
Coefficient Byte 1
Coefficient Byte 2
Coefficient Byte 3
Coefficient Byte 4
Coefficient Byte 5
Coefficient Byte 6
Coefficient Byte 7
Coefficient Byte 8
Coefficient Byte 9
Coefficient Byte 10
Coefficient Byte 11
Coefficient Byte 12
C40
C20
C41
C21
C42
C22
C43
C23
C44
C24
C45
C25
m40
m20
m41
m21
m42
m22
m43
m23
m44
m24
m45
m25
C30
C10
C31
C11
C32
C12
C33
C13
C34
C14
C35
C15
m30
m10
m31
m11
m32
m12
m33
m13
m34
m14
m35
m15
Cxy = 0 or 1 in the command above corresponds to Cxy = +1 or −1, respectively, in the equation below.
The Z-transform equation for the X filter is defined as:
Hx(z) = X0 + X1z–1 + X2z–2 + X3z–3 + X4z–4 + X5z–5
Sample rate = 16 kHz
For i = 0 to 5, the coefficients for the X filter are defined as:
Xi = C1i • 2–m1i(1 + C2i • 2–m2i(1 + C3i • 2–m3i(1 + C4i • 2–m4i)))
Power Up and Hardware Reset (RST) Values = 0111 0190 0190 0190 0190 0190h
Hx(z) = 1
See note under COP Command 2 on page 92.
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COP 7. Write/Read R Filter Coefficients
GCI Command
(8A/8Bh)
R/W = 1: Read
R/W = 0: Write
D7
1
D6
0
D5
D4
0
D3
D2
0
D1
D0
W/R
Command
0
1
1
Coefficient Byte 1
Coefficient Byte 2
Coefficient Byte 3
Coefficient Byte 4
Coefficient Byte 5
Coefficient Byte 6
Coefficient Byte 7
Coefficient Byte 8
Coefficient Byte 9
Coefficient Byte 10
Coefficient Byte 11
Coefficient Byte 12
Coefficient Byte 13
Coefficient Byte 14
C46
C26
C40
C20
C41
C21
C42
C22
C43
C23
C44
C24
C45
C25
m46
m26
m40
m20
m41
m21
m42
m22
m43
C23
m44
m24
m45
m25
C36
C16
C30
C10
C31
C11
C32
C12
C33
C13
C34
C14
C35
C15
m36
m16
m30
m10
m31
m11
m32
m12
m33
m13
m34
m14
m35
m15
Cxy = 0 or 1 in the command above corresponds to Cxy = +1 or −1, respectively, in the equation below.
HR = HIIR • HFIR
The Z-transform equation for the IIR filter is defined as:
1 – z–1
-----------------------------------
=
HIIR
–1
⎞
⎠
⎛
1 – R6 • z
⎝
Sample rate = 8 kHz
The coefficient for the IIR filter is defined as:
R6 = C16 • 2–ml6{1 + C26 • 2–m26[1 + C36 • 2–m36(1 + C46 • 2–m46)]}
The Z-transform equation for the FIR filter is defined as:
HFIR(z) = R0 + R1z–1 + R2z–2 + R3z–3 + R4z–4 + R5z–5
Sample rate = 16 kHz
For i = 0 to 5, the coefficients for the R2 filter are defined as:
Ri = C1i • 2–m1i{1 + C2i • 2–m2i[1 + C3i • 2–m3i(1 + C4i • 2–m4i)]}
Power Up and Hardware Reset (RST) Values = 2E01 0111 0190 0190 0190 0190 0190 (Hex)
(HFIR (z) = 1, R6 = 0.9902)
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See note under COP Command 2 on page 92.
COP 8. Write/Read B2 Filter Coefficients (B-IIR)
GCI Command
(96/97h)
R/W = 1: Read
R/W = 0: Write
D7
D6
0
D5
D4
1
D3
D2
1
D1
D0
W/R
Command
1
0
0
1
Coefficient Byte 1
Coefficient Byte 2
C411
C211
m411
m211
C311
C111
m311
m111
This function is described in Write/Read B1 Filter Coefficients on page 94.
Power Up and Hardware Reset (RST) Value = 0190h
(B = 0)
11
COP 9. Write/Read IIR Z Filter Coefficients
GCI Command
(9A/9B)
R/W = 0: Write
R/W = 1: Read
This command writes and reads only the IIR portion of the Z filter without affecting the FIR.
D7
D6
0
D5
D4
1
D3
D2
0
D1
D0
Command
1
0
1
1
R/W
I/O Data Byte 1
I/O Data Byte 2
I/O Data Byte 3
I/O Data Byte 4
I/O Data Byte 5
C45
C25
C26
C47
C27
m45
m25
m26
m47
m27
C35
C15
C16
C37
C17
m35
m15
m16
m37
m17
Cxy = 0 or 1 in the command above corresponds to Cxy = +1 or −1, respectively, in the equation below.
The Z-transform equation for the Z filter is defined as:
z5 • z6 • z7 • z–1
Hz(z) = z0 + z1 • z–1 + z2 • z–2 + z3 • z–3 + z4 • z–4
------------------------------------------
+
1 – z7 • z–1
Sample rate = 32 kHz
For i = 0–5 and 7
zi = C1i • 2–m1i{1 + C2i • 2–m2i[1 + C3i • 2–m3i(1 + C4i • 2–m4i)]}
z6 = C16 • 2–m16{1 + C26 • 2–m26
}
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Power Up and Hardware Reset (RST) Values = 0190 0190 0190 0190 0190 0190 01 0190 (Hex)
(Hz(z) = 0)
See note under COP Command 2 on page 92.
Note:
Z6 is used for IIR filter scaling only. Its value is typically greater than zero but less than or equal to one. The input to the IIR filter section is first
increased by a gain of 1/Z6, improving dynamic range and avoiding truncation limitations through processing within this filter. The IIR filter output
is then multiplied by Z6 to normalize the overall gain. Z5 is the actual IIR filter gain value defined by the programmed coefficients, but it also in-
cludes the initial 1/Z6 gain. The theoretical effective IIR gain, without the Z6 gain and normalization, is actually Z5/Z6.
17.0 Programmable Filters
General Description of CSD Coefficients
The filter functions are performed by a series of multiplications and accumulations. A multiplication occurs by
repeatedly shifting the multiplicand and summing the result with the previous value at that summation node. The
method used in the QLSLAC device is known as Canonic Signed Digit (CSD) multiplication and splits each
coefficient into a series of CSD coefficients.
Each programmable FIR filter section has the following general transfer function:
HF(z) = h0 + h1z–1 + h2z–2 + … + hnz–n
Equation 1
where the number of taps in the filter = n + 1.
The transfer function for the IIR part of Z and B filters:
1
-----------------------------------
HI(z) =
Equation 2
1 – h(n + 1)z–1
The transfer function of the IIR part of the R filter is:
1 – z–1
-----------------------------------
HI(z) =
Equation 3
1 – h(n + 1)z–1
The values of the user-defined coefficients (h ) are assigned via the MPI. Each of the coefficients (h ) is defined in
i
i
the following general equation:
hi = B12–M1 + B22–M2 + … + BN2–MN
Equation 4
where:
Mi = the number of shifts = Mi ≤ Mi + 1
B = sign = ±1
i
N = number of CSD coefficients.
The value of h in Equation 4 represents a decimal number, broken down into a sum of successive values of:
i
–0
–1
–2
–7
1)
2)
±1.0 multiplied by 2 , or 2 , or 2 … 2
…
±1.0 multiplied by 1, or 1/2, or 1/4 … 1/128 …
The limit on the negative powers of 2 is determined by the length of the registers in the ALU.
The coefficient h in Equation 4 is a value made up of N binary 1s in a binary register where the left part represents
i
whole numbers, the right part decimal fractions, and a decimal point separates them. The first binary 1 is shifted M
1
bits to the right of the decimal point; the second binary 1 is shifted M bits to the right of the decimal point; the third
2
binary 1 is shifted M bits to the right of the decimal point, and so on.
3
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When M is 0, the value is a binary 1 in front of the decimal point, that is, no shift. If M is also 0, the result is
1
2
another binary 1 in front of the decimal point, giving a total value of binary 10 in front of the decimal point (i.e., a
decimal value of 2.0). The value of N, therefore, determines the range of values the coefficient h can take (e.g., if N
i
= 3 the maximum and minimum values are ±3, and if N = 4 the values are between ±4).
Detailed Description of QLSLAC Device Coefficients
The CSD coding scheme in the QLSLAC device uses a value called mi, where m1 represents the distance shifted
right of the decimal point for the first binary 1. m2 represents the distance shifted to the right of the previous binary
1, and m3 represents the number of shifts to the right of the second binary 1. Note that the range of values
determined by N is unchanged. Equation 4 is now modified (in the case of N = 4) to:
hi = B12–m1 + B22–m2 + B32–m3 + B42–m4
Equation 5
hi = C1 • 2–m1 + C1 • C2 • 2–(m1 + m2) + C1 • C2 • C3 • 2–(m1 + m2 + m3) + C1 • C2 • C3 • C4 • 2–(m1 + m2 + m3 + m4)
Equation 6
hi = C1 • 2–m1{1 + C2 • 2–m2[1 + C3 • 2–m3(1 + C4 • 2–m4)]}
Equation 7
where:
M = m1
B = C1
1
1
M = m1 + m2
B = C1 •C2
3
2
2
M = m1 + m2 + m3
B = C1 •C2 •C3
3
M = m1 + m2 + m3 + m4 B = C1 •C2 •C3 •C4
4
4
In the QLSLAC device, a coefficient, h , consists of N CSD coefficients, each being made up of 4 bits and formatted
i
as Cxy mxy, where Cxy is 1 bit (MSB) and mxy is 3 bits. Each CSD coefficient is broken down as follows:
Cxy
mxy
is the sign bit (0 = positive, 1 = negative).
is the 3-bit shift code. It is encoded as a binary
number as follows:
000:
001:
010:
011:
100:
101:
110:
111:
y
0 shifts
1 shifts
2 shifts
3 shifts
4 shifts
5 shifts
6 shifts
7 shifts
is the coefficient number (the i in h ).
i
x
is the position of this CSD coefficient within the h coefficient. The most significant binary 1 is represented by
i
x = 1. The
next most significant binary 1 is represented by x = 2, and so on.
Thus, C13 m13 represents the sign and the relative shift position for the first (most significant) binary 1 in the 4th (h )
3
coefficient.
The number of CSD coefficients, N, is limited to 4 in the GR, GX, R, X, and Z filters; 4 in the IIR part of the B filter; 3
in the FIR part of the B filter; and 2 in the post-gain factor of the Z-IIR filter. The GX filter coefficient equation is slightly
different from the other filters.
hiGX = 1 + hi
Equation 8
Please refer to Summary of MPI Commands on page 54 for complete details on programming the coefficients.
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17.1 User Test States and Operating Conditions
The QLSLAC device supports testing by providing test states and special operating conditions as shown in Figure
24 (see Operating Conditions register).
Cutoff Transmit Path (CTP): When CTP = 1, DX and TSC are High impedance and the transmit time slot does not
exist. This state takes precedence over the TSA Loopback (TLB) and Full Digital Loopback (FDL) states.
Cutoff Receive Path (CRP): When CRP = 1, the receive signal is forced to 0 just ahead of the low pass filter (LPF)
block. This state also blocks Full Digital Loopback (FDL), the 1 kHz receive tone, and the B-filter path.
High Pass Filter Disable (HPF): When HPF = 1, all of the High pass and notch filters in the transmit path are
disabled.
Lower Receive Gain (LRG): When LRG = 1, an extra 6.02 dB of loss is inserted into the receive path.
Arm Transmit Interrupt (ATI) and Read Transmit PCM Data (PCM/MPI mode only): The read transmit PCM
data command, Command CDh, can be used to read transmit PCM data through the microprocessor interface. If
the ATI bit is set, an interrupt will be generated whenever new transmit data appears in the channel and will be
cleared when the data is read. When combined with Tone Generation and Loopback states, this allows the
microprocessor to test channel integrity.
Interface Loopback (ILB): When ILB = 1, data from the receive/downstream path is looped back to the
transmit/Upstream path. Any other data in the transmit path is overwritten.
Full Digital Loopback (FDL): When FDL = 1, the VOUT output is turned off and the analog output voltage is routed
to the input of the transmit path, replacing the voltage from VIN. The AISN path is temporarily turned off. This test
mode can also be entered by writing the code 10000 into the AISN register.
1 kHz Receive Tone (TON): When TON = 1, a 1 kHz digital mW is injected into the receive path, replacing any
receive or downstream signal.
17.2 A-Law and µ-Law Companding
Table 13 and Table Table 14 show the companding definitions used for A-law and µ-law PCM encoding.
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Data Sheet
1
2
3
4
5
6
7
8
Character
Signal pre
Inversion of
Even Bits
Quantized
Value (at
Decoder
Decoder
Output
Value No.
Decision
Value
Number
# Intervals
x Interval
Size
Value at
Segment
End Points
Decision
Segment
Number
Value
x
n
n
(See Note 1)
Output)
y
Bit No.
n
1 2 3 4 5 6 7 8
4096
(128)
127
(4096)
3968
1 1 1 1 1 1 1 1
4032
2112
128
113
7
16 x 128
See Note 2
113
112
2176
2048
1 1 1 1 0 0 0 0
2048
1024
See Note 2
6
5
16 x 64
16 x 32
97
96
1088
1024
1 1 1 0 0 0 0 0
1056
528
97
81
See Note 2
81
80
544
1 1 0 1 0 0 0 0
512
512
See Note 2
16 x 16
16 x 8
16 x 4
4
3
65
64
272
256
264
132
66
65
49
33
1 1 0 0 0 0 0 0
256
128
See Note 2
49
48
136
1 0 1 1 0 0 0 0
128
See Note 2
2
1
33
32
68
64
1 0 1 0 0 0 0 0
64
See Note 2
32 x 2
1
0
2
0
1
1
1 0 0 0 0 0 0 0
Table 13 - A-Law: Positive Input Values
Notes:
1. 4096 normalized value units correspond to TMAX = 3.14 dBm0.
2. The character signals are obtained by inverting the even bits of the signals of column 6. Before this inversion, the character signal
corresponding to positive input values between two successive decision values numbered n and n+1 (see column 4) is 128+n, expressed
as a binary number.
xn – 1 + xn
------------------------
3. The value at the decoder output is yn
4. 128 is a virtual decision value.
5. Bit 1 is a 0 for negative input values.
=
, for n = 1,...127, 128.
2
x
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Data Sheet
1
2
3
4
5
6
7
8
Character
Signal pre
Inversion of
Even Bits
Quantized
Value (at
Decoder
Decoder
Output
Value No.
Decision
Value
Number
# Intervals
x Interval
Size
Value at
Segment
End Points
Decision
Segment
Number
Value
x
n
n
(See Note 1)
Output)
y
Bit No.
n
1 2 3 4 5 6 7 8
8159
(128)
127
(8159)
7903
1 0 0 0 0 0 0 0
8031
4191
127
112
8
16 x 256
See Note 2
113
112
4319
4063
1 0 0 0 1 1 1 1
4063
2015
See Note 2
7
6
16 x 128
16 x 64
97
96
2143
2015
1 0 0 1 1 1 1 1
2079
1023
96
80
See Note 2
81
80
1055
991
1 0 1 0 1 1 1 1
991
See Note 2
16 x 32
16 x 16
16 x 8
5
4
65
64
511
1 0 1 1 1 1 1 1
495
231
64
48
479
223
479
See Note 2
49
48
239
223
1 1 0 0 1 1 1 1
See Note 2
3
33
32
103
1 1 0 1 1 1 1 1
99
33
32
16
95
31
95
See Note 2
2
1
16 x 4
17
16
35
31
1 1 1 0 1 1 1 1
See Note 2
15 x 2
1 x 1
2
1
3
1
2
0
1
0
1 1 1 1 1 1 1 0
1 1 1 1 1 1 1 1
0
0
Table 14 - µ-Law: Positive Input Values
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Data Sheet
Notes:
1. 8159 normalized value units correspond to TMAX = 3.17 dBm0.
2. The character signal corresponding to positive input values between two successive decision values numbered n and n+1 (see column 4)
is 255-n, expressed as a binary number.
x
n + 1 + xn
------------------------
, for n = 1, 2,...127.
3. The value at the decoder is y0 = x0 = 0 for n = 0, and yn
4. 128 is a virtual decision value.
=
2
x
5. Bit 1 is a 0 for negative input values.
18.0 APPLICATIONS
The QLSLAC device performs a programmable codec/filter function for four telephone lines. It interfaces to the
telephone lines through a Zarlink SLIC device or a transformer with external buffering. The QLSLAC device
provides latched digital I/O to control and monitor four SLIC devices and provides access to time-critical
information, such as off/on-hook and ring trip, for all four channels via a single read operation or via the upstream
C/I bits in the GCI SC channel. When various country or transmission requirements must be met, the QLSLAC
device enables a single SLIC device design for multiple applications. The line characteristics (such as apparent
impedance, attenuation, and hybrid balance) can be modified by programming each QLSLAC device channel’s
coefficients to meet desired performance. The QLSLAC device may require an external buffer to drive transformer
SLIC devices.
In PCM/MPI mode, connection to a PCM back plane is implemented by means of a simple buffer chip. Several
QLSLAC devices can be tied together in one bus interfacing the back plane through a single buffer. An intelligent bus
interface chip is not required because each QLSLAC device provides its own buffer control (TSCA/TSCB). The
QLSLAC device is controlled through the microprocessor interface, either by a microprocessor on the line card or
by a central processor.
In GCI mode, the QLSLAC device decodes the S0 and S1 inputs and determines the DCL frequency, 2.048 MHz or
4.096 MHz automatically. The QLSLAC device transmits and receives the GCI channel information in accordance
with S0, S1 and DCL, synchronized by Frame Sync. (FSC). Up to four QLSLAC devices can be bussed together
forming one bidirectional 16 channel GCI bus. A simple inexpensive buffer should be used between the GCI bus
and the backplane of the system.
Controlling the SLIC Device
The Le58QL061 QLSLAC device has five TTL-compatible I/O pins (CD1, CD2, C3, C4 and C5) for each channel.
The Le58QL063 device has two additional outputs (C6, C7) per channel. The outputs are programmed using MPI
Command 52h or the downstream C/I bits in the GCI SC channel. The logic states are read back using MPI
Command 53h or GCI Command SOP 10. In GCI mode CD1 (debounced), CD2, and C3 are also present on the
upstream C/I bits in the GCI SC channel. In PCM/MPI mode, CD1 and CD2 for all four channels can be read back
using MPI Command 4D/4Fh. The direction of the I/O pins (input or output) is specified by programming the SLIC
device I/O direction register (MPI Command 54/55h, GCI Command SOP 8).
Calculating Coefficients with WinSLAC Software
The WinSLAC software is a program that models the QLSLAC device, the line conditions, the SLIC device, and the
line card components to obtain the coefficients of the programmable filters of the QLSLAC device and some of the
transmission performance plots.
The following parameters relating to the desired line conditions and the components/circuits used in the line card
are to be provided as input to the program:
1. Line impedance or the balance impedance of the line is specified by the local telephone system.
2. Desired two-wire impedance that is to appear at the line card terminals of the exchange.
3. Tabular data for templates describing the frequency response and attenuation distortion of the design.
4. Relative analog signal levels for both the transmit and receive two-wire signals.
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Data Sheet
5. Component values and SLIC device selection for the analog portion of the line circuits.
6. Two-wire return loss template is usually specified by the local telephone system.
7. Four-wire return loss template is usually specified by the local telephone system.
The output from the WinSLAC program includes the coefficients of the GR, GX, Z, R, X, and B filters as well as
transmission performance plots of two-wire return loss, receive and transmit path frequency responses, and four-
wire return loss.
The software supports the use of the Zarlink SLIC devices or allows entry of a SPICE netlist describing the behavior
of any type of SLIC device circuit.
19.0 Application Circuit
Shared Ring Threshold
+3.3 V
+5.0 V
CTH
CRT
RSR4
RRTH2
VCC
RD
VCCA
RING
BUS
VCCD
DGND
U2
CBPD
DA
U1
Le7920
SLIC
Le58QL061
QLSLAC
AGND
VIN1
RR1
CD
RD
CBPA
RSR1
PCM/MPI
MODE
DB
AGND
VTX
CVTX
CAD
RR
RFA
TIP
RT
AX
MLCK/E1
MCLK/E1
RRX
VOUT1
HPA
PCLK/DCL
FS/FSC
DXA/DU
DRA/DD
PCLK
FS
RSN
RDC
CHP
CVRX
RDC2
U3
RDC1
VBAT
DXA
HPB
BX
RFB
RR
DRA
TSCA
DIO
RING
CDC
TO
TI
CBD
TSCA
DIO/S1
DCLK/S0
CS/PG
RST
INT
2
C1, C2
D0
D1
DET
CD21, C31
C41
C51
3
RYOUT1, RYOUT2
RING RELAY
TEST
DCLK
OUT
TEST
CS
RST
INT
BGND
CBAT
BGND
CD11
IN
VBAT
VBAT
TMG
CAS
K
RR
+
5V
VREF
CAS
RTMG
CFIL
D1
K TI
GCI MODE
MCLK/E1
PCLK/DCL
FS/FSC
DXA/DU
DRA/DD
E1
K TO
DCL
FSC
DU
DD
S1
TIP
SLIC 2
5
DIO/S1
DCLK/S0
RING
S0
CS/PG
TIP
RST
INT
RST
INT
SLIC 3
SLIC 4
5
TSCA
TSCA
RING
TIP
5
ANALOG
GROUND
DIGITAL
GROUND
RING
Grounds are connected on board.
Figure 32 - Le7920 SLIC/QLSLAC Device Application Circuit
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Data Sheet
20.0 Line Card Parts List
The following list defines the parts and part values required to meet target specification limits for one channel.
Item
Quantity
Type
Capacitor
Value
0.1 µF
0.1 µF
0.1 µF
0.1 µF
57.6 kΩ
0.15 µF
178 kΩ
50 Ω
Tol.
20%
20%
20%
20%
1%
Rating
10 V
Comments
Bypass capacitor
Bypass capacitor
Bypass capacitor
Coupling capacitor
CBPA
1
1
1
1
1
1
1
1
1
CBPD
CFIL
CVTX
RRX
CVRX
RT
Capacitor
Capacitor
Capacitor
Resistor
10 V
10 V
10 V
0.01 W
10 V
Capacitor
Resistor
20%
1%
Coupling capacitor
0.01 W
RFA
Fuse resistor
Fuse resistor
See Note
RFB
50 Ω
Note:
For all other components, please refer to the Le7920 Data Sheet, document ID #080146.
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Data Sheet
21.0 Physical Dimensions
21.1 44-Pin TQFP
Notes:
Min
-
0.05
0.95
Nom
-
Max
1.20
0.15
1.05
Symbol
A
A1
A2
D
D1
E
1. All dimensions and toleerances conform to ANSI Y14.5-1982.
2. Datum plane -H- is located at the mold parting line and is coincident
with the bottom of the lead where the lead exits the plastic body.
3. Dimensions “D1” and “E1” do not include mold protrusion. Allowable
protrusion is 0.254mm per side. Dimensions “D1” and “E1” include
-
1.00
12 BSC
10 BSC
12 BSC
10 BSC
0.60
mold mismatch and are determined at Datum plane -H-
.
4. Dimension “B” does not include Dambar protrusion. Allowable Dambar
protrusion shall be 0.08mm total in excess of the “b” dimension at
maximum material condition. Dambar can not be located on the lower
radius or the foot.
E1
L
0.45
0.75
N
44
5. Controlling dimensions: Millimeter.
6. Dimensions “D” and “E” are measured from both innermost and
outermost points.
7. Deviation from lead-tip true position shall be within 0.076mm for pitch
>0.5mm and within 0.04 for pitch ꢀ0.5mm.
e
0.80 BSC
0.37
b
0.30
0.30
0.45
0.40
b1
ccc
ddd
aaa
0.35
0.10
0.20
8. Lead coplanarity shall be within: (Refer to 06-500)
1- 0.10mm for devices with lead pitch of 0.65-0.80mm.
2- 0.076mm for devices with lead pitch of 0.50mm.
Coplanarity is measured per specification 06-500.
9. Half span (center of package to lead tip) shall be
15.30 0.165mm ꢁ.602” .0065”ꢂ.
0.20
JEDEC #: MS-026 (C) ACB
10. “N” is the total number of terminals.
11. The top of package is smaller than the bottom of the package by 0.15mm.
12. This outline conforms to Jedec publication 95 registration MS-026
13. The 160 lead is a compliant depopulation of the 176 lead MS-026
variation BGA.
44-Pin TQFP
Note:
Packages may have mold tooling markings on the surface. These markings have no impact on the form, fit or function of the
device. Markings will vary with the mold tool used in manufacturing.
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Data Sheet
64-Pin LQFP
LQFP 064
Dwg rev. AS; 8/00
LQFP 064
Note:
Packages may have mold tooling markings on the surface. These markings have no impact on the form, fit or function of the
device. Markings will vary with the mold tool used in manufacturing.
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Data Sheet
For more information about all Zarlink products
visit our Web Site at
www.zarlink.com
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable.
However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such
information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or
use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual
property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in
certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink.
This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part
of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other
information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the
capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute
any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and
suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does
not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in
significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request.
Purchase of Zarlink’s I2C components conveys a license under the Philips I2C Patent rights to use these components in an I2C System, provided that the system
conforms to the I2C Standard Specification as defined by Philips.
Zarlink, ZL, the Zarlink Semiconductor logo and the Legerity logo and combinations thereof, VoiceEdge, VoicePort, SLAC, ISLIC, ISLAC and VoicePath are
trademarks of Zarlink Semiconductor Inc.
TECHNICAL DOCUMENTATION - NOT FOR RESALE
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Zarlink Semiconductor Inc.
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