GRM31CR61C106KC31L_技术文档

PIC24FJ128GA010 FAMILY

64/80/100-Pin, General Purpose, 16-Bit Flash Microcontrollers

High-Performance CPU:

Analog Features:

• 10-Bit, Up to 16-Channel Analog-to-Digital Converter

- 500 ksps conversion rate

- Conversion available during Sleep and Idle

• Dual Analog Comparators with Programmable

Input/Output Configuration

• Modified Harvard Architecture

• Up to 16 MIPS Operation @ 32 MHz

• 8 MHz Internal Oscillator with 4x PLL Option and

Multiple Divide Options

• 17-Bit x 17-Bit Single-Cycle Hardware

Multiplier

Peripheral Features:

• 32-Bit by 16-Bit Hardware Divider

• 16 x 16-Bit Working Register Array

• C Compiler Optimized Instruction Set Architecture:

- 76 base instructions

- Flexible addressing modes

• Two Address Generation Units for Separate Read

and Write Addressing of Data Memory

• Two 3-Wire/4-Wire SPI modules, Supporting

4 Frame modes with 8-Level FIFO Buffer

2

• Two I C™ modules Support Multi-Master/Slave

mode and 7-Bit/10-Bit Addressing

• Two UART modules:

- Supports RS-232, RS-485 and LIN/J2602

- On-chip hardware encoder/decoder for IrDA

- Auto-wake-up on Start bit

®

Special Microcontroller Features:

- Auto-Baud Detect

- 4-level FIFO buffer

• Operating Voltage Range of 2.0V to 3.6V

• Flash Program Memory:

• Parallel Master Slave Port (PMP/PSP):

- Supports 8-bit or 16-bit data

- 1000 erase/write cycles

- 20-year data retention minimum

- Supports 16 address lines

• Self-Reprogrammable under Software Control

• Selectable Power Management modes:

- Sleep, Idle and Alternate Clock modes

• Fail-Safe Clock Monitor Operation:

- Detects clock failure and switches to on-chip,

low-power RC oscillator

• Hardware Real-Time Clock/Calendar (RTCC):

- Provides clock, calendar and alarm functions

• Programmable Cyclic Redundancy Check (CRC)

-

User-programmable polynomial

8/16-level FIFO buffer

• Five 16-Bit Timers/Counters with Programmable

Prescaler

• Five 16-Bit Capture Inputs

• Five 16-Bit Compare/PWM Outputs

• High-Current Sink/Source (18 mA/18 mA) on All

I/O Pins

• Configurable, Open-Drain Output on Digital I/O Pins

• Up to 5 External Interrupt Sources

• 5.5V Tolerant Input (digital pins only)

• On-Chip 2.5V Regulator

• JTAG Boundary Scan and Programming Support

• Power-on Reset (POR), Power-up Timer (PWRT)

and Oscillator Start-up Timer (OST)

• Flexible Watchdog Timer (WDT) with On-Chip,

Low-Power RC Oscillator for Reliable Operation

• In-Circuit Serial Programming™ (ICSP™) and

In-Circuit Emulation (ICE) via 2 Pins

Program

Pins Memory

(Bytes)

SRAM

(Bytes)

Timers

16-Bit

10-Bit

A/D (ch)

2

Device

SPI

I C™

PIC24FJ64GA006

PIC24FJ96GA006

PIC24FJ128GA006

PIC24FJ64GA008

PIC24FJ96GA008

PIC24FJ128GA008

PIC24FJ64GA010

PIC24FJ96GA010

PIC24FJ128GA010

64

64K

96K

8K

5

2

16

2

Y

64

128K

64K

80

96K

80

128K

64K

100

96K

128K

 2005-2012 Microchip Technology Inc.

DS39747F-page 1

PIC24FJ128GA010 FAMILY

Pin Diagrams

64-Pin TQFP/QFN⁽¹⁾

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

SOSCO/T1CK/CN0/RC14

SOSCI/CN1/RC13

OC1/RD0

1

PMD5/RE5

PMD6/RE6

2

PMD7/RE7

3

IC4/PMCS1/INT4/RD11

IC3/PMCS2/INT3/RD10

IC2/U1CTS/INT2/RD9

IC1/RTCC/INT1/RD8

Vss

PMA5/SCK2/CN8/RG6

PMA4/SDI2/CN9/RG7

PMA3/SDO2/CN10/RG8

4

5

6

MCLR

PMA2/SS2/CN11/RG9

VSS

7

PIC24FJXXGA006

PIC24FJXXXGA006

8

OSC2/CLKO/RC15

OSC1/CLKI/RC12

VDD

9

VDD

10

11

12

13

14

15

16

C1IN+/AN5/CN7/RB5

C1IN-/AN4/CN6/RB4

SCL1/RG2

C2IN+/AN3/CN5/RB3

SDA1/RG3

U1RTS/BCLK1/SCK1/INT0/RF6

U1RX/SDI1/RF2

U1TX/SDO1/RF3

C2IN-/AN2/SS1/CN4/RB2

PGC1/EMUC1/VREF-/AN1/CN3/RB1

PGD1/EMUD1/PMA6/VREF+/AN0/CN2/RB0

Legend:

Shaded pins indicate pins that are tolerant to up to +5.5 VDC.

Note 1: Bottom pad of QFN package must be connected to VSS.

DS39747F-page 2

 2005-2012 Microchip Technology Inc.

PIC24FJ128GA010 FAMILY

Pin Diagrams (Continued)

80-Pin TQFP

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

SOSCO/T1CK/CN0/RC14

1

PMD5/RE5

PMD6/RE6

SOSCI/CN1/RC13

OC1/RD0

2

PMD7/RE7

3

IC4/PMCS1/RD11

IC3/PMCS2/RD10

IC2/RD9

T2CK/RC1

4

T4CK/RC3

5

PMA5/SCK2/CN8/RG6

PMA4/SDI2/CN9/RG7

PMA3/SDO2/CN10/RG8

MCLR

6

IC1/RTCC/RD8

SDA2/INT4/RA15

SCL2/INT3/RA14

VSS

7

8

9

PMA2/SS2/CN11/RG9

VSS

10

11

12

13

14

15

16

17

18

19

20

PIC24FJXXGA008

PIC24FJXXXGA008

OSC2/CLKO/RC15

OSC1/CLKI/RC12

VDD

TMS/INT1/RE8

TDO/INT2/RE9

SCL1/RG2

C1IN+/AN5/CN7/RB5

C1IN-/AN4/CN6/RB4

SDA1/RG3

SCK1/INT0/RF6

SDI1/RF7

C2IN+/AN3/CN5/RB3

C2IN-/AN2/SS1/CN4/RB2

PGC1/EMUC1/AN1/CN3/RB1

PGD1/EMUD1/AN0/CN2/RB0

SDO1/RF8

U1RX/RF2

U1TX/RF3

Legend: Shaded pins indicate pins that are tolerant to up to +5.5 VDC.

 2005-2012 Microchip Technology Inc.

DS39747F-page 3

PIC24FJ128GA010 FAMILY

Pin Diagrams (Continued))

100-Pin TQFP

VSS

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

1

RG15

VDD

PMD5/RE5

SOSCO/T1CK/CN0/RC14

SOSCI/CN1/RC13

OC1/RD0

IC4/PMCS1/RD11

IC3/PMCS2/RD10

IC2/RD9

IC1/RTCC/RD8

INT4/RA15

INT3/RA14

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

PMD6/RE6

PMD7/RE7

T2CK/RC1

T3CK/RC2

T4CK/RC3

T5CK/RC4

PMA5/SCK2/CN8/RG6

PMA4/SDI2/CN9/RG7

PMA3/SDO2/CN10/RG8

MCLR

PMA2/SS2/CN11/RG9

VSS

OSC2/CLKO/RC15

OSC1/CLKI/RC12

VDD

PIC24FJXXGA010

PIC24FJXXXGA010

TDO/RA5

VDD

TMS/RA0

INT1/RE8

INT2/RE9

TDI/RA4

SDA2/RA3

SCL2/RA2

SCL1/RG2

SDA1/RG3

SCK1/INT0/RF6

SDI1/RF7

SDO1/RF8

U1RX/RF2

U1TX/RF3

C1IN+/AN5/CN7/RB5

C1IN-/AN4/CN6/RB4

C2IN+/AN3/CN5/RB3

C2IN-/AN2/SS1/CN4/RB2

PGC1/EMUC1/AN1/CN3/RB1

PGD1/EMUD1/AN0/CN2/RB0

Legend: Shaded pins indicate pins that are tolerant to up to +5.5 VDC.

DS39747F-page 4

 2005-2012 Microchip Technology Inc.

PIC24FJ128GA010 FAMILY

Table of Contents

1.0 Device Overview .......................................................................................................................................................................... 7

2.0 Guidelines for Getting Started with 16-bit Microcontrollers ........................................................................................................ 19

3.0 CPU............................................................................................................................................................................................ 25

4.0 Memory Organization................................................................................................................................................................. 31

5.0 Flash Program Memory.............................................................................................................................................................. 51

6.0 Resets ........................................................................................................................................................................................ 57

7.0 Interrupt Controller ..................................................................................................................................................................... 63

8.0 Oscillator Configuration.............................................................................................................................................................. 97

9.0 Power-Saving Features............................................................................................................................................................ 105

10.0 I/O Ports ................................................................................................................................................................................... 107

11.0 Timer1 ...................................................................................................................................................................................... 111

12.0 Timer2/3 and Timer4/5 ............................................................................................................................................................ 113

13.0 Input Capture............................................................................................................................................................................ 119

14.0 Output Compare....................................................................................................................................................................... 121

15.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 127

2

16.0 Inter-Integrated Circuit (I C™) ................................................................................................................................................. 137

17.0 Universal Asynchronous Receiver Transmitter (UART)........................................................................................................... 145

18.0 Parallel Master Port (PMP)....................................................................................................................................................... 153

19.0 Real-Time Clock and Calendar (RTCC)................................................................................................................................... 163

20.0 Programmable Cyclic Redundancy Check (CRC) Generator .................................................................................................. 175

21.0 10-bit High-Speed A/D Converter............................................................................................................................................. 179

22.0 Comparator Module.................................................................................................................................................................. 189

23.0 Comparator Voltage Reference................................................................................................................................................ 193

24.0 Special Features ...................................................................................................................................................................... 195

25.0 Instruction Set Summary.......................................................................................................................................................... 205

26.0 Development Support............................................................................................................................................................... 213

27.0 Electrical Characteristics.......................................................................................................................................................... 217

28.0 Packaging Information.............................................................................................................................................................. 231

Appendix A: Revision History............................................................................................................................................................. 245

Index ................................................................................................................................................................................................. 247

The Microchip Web Site..................................................................................................................................................................... 251

Customer Change Notification Service .............................................................................................................................................. 251

Customer Support.............................................................................................................................................................................. 251

Reader Response.............................................................................................................................................................................. 252

Product Identification System ............................................................................................................................................................ 253

 2005-2012 Microchip Technology Inc.

DS39747F-page 5

PIC24FJ128GA010 FAMILY

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip

products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and

enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via

E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We

welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current

devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision

of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

•

Microchip’s Worldwide Web site; http://www.microchip.com

Your local Microchip sales office (see last page)

When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

using.

Customer Notification System

Register on our web site at www.microchip.com to receive the most current information on all of our products.

DS39747F-page 6

 2005-2012 Microchip Technology Inc.

PIC24FJ128GA010 FAMILY

1.1.2

POWER-SAVING TECHNOLOGY

1.0

DEVICE OVERVIEW

All of the devices in the PIC24FJ128GA010 family

incorporate a range of features that can significantly

reduce power consumption during operation. Key

items include:

This document contains device-specific information for

the following devices:

• PIC24FJ64GA006

• PIC24FJ64GA008

• PIC24FJ64GA010

• PIC24FJ96GA006

• PIC24FJ96GA008

• PIC24FJ96GA010

• PIC24FJ128GA006

• PIC24FJ128GA008

• PIC24FJ128GA010

• On-the-Fly Clock Switching: The device clock

can be changed under software control to the

Timer1 source or the internal low-power RC

oscillator during operation, allowing the user to

incorporate power-saving ideas into their software

designs.

• Doze Mode Operation: When timing-sensitive

applications, such as serial communications,

require the uninterrupted operation of peripherals,

the CPU clock speed can be selectively reduced,

allowing incremental power savings without

missing a beat.

This family introduces a new line of Microchip devices:

a 16-bit microcontroller family with a broad peripheral

feature set and enhanced computational performance.

The PIC24FJ128GA010 family offers a new migration

option for those high-performance applications which

may be outgrowing their 8-bit platforms, but don’t

require the numerical processing power of a digital

signal processor.

• Instruction-Based Power-Saving Modes: The

microcontroller can suspend all operations, or

selectively shut down its core while leaving its

peripherals active, with a single instruction in

software.

1.1.3

OSCILLATOR OPTIONS AND

FEATURES

1.1

Core Features

1.1.1

16-BIT ARCHITECTURE

All of the devices in the PIC24FJ128GA010 family offer

five different oscillator options, allowing users a range

of choices in developing application hardware. These

include:

Central to all PIC24F devices is the 16-bit modified

Harvard architecture, first introduced with Microchip’s

dsPIC^®digital signal controllers. The PIC24F CPU core

offers a wide range of enhancements, such as:

• Two Crystal modes using crystals or ceramic

resonators.

• 16-bit data and 24-bit address paths, with the

ability to move information between data and

memory spaces

• Two External Clock modes offering the option of a

divide-by-2 clock output.

• Linear addressing of up to 8 Mbytes (program

space) and 64 Kbytes (data)

• A Fast Internal Oscillator (FRC) with a nominal

8 MHz output, which can also be divided under

software control to provide clock speeds as low as

31 kHz.

• A 16-element working register array with built-in

software stack support

• A 17 x 17 hardware multiplier with support for

integer math

• A Phase Lock Loop (PLL) frequency multiplier,

available to the external oscillator modes and the

FRC oscillator, which allows clock speeds of up to

32 MHz.

• Hardware support for 32 by 16-bit division

• An instruction set that supports multiple

addressing modes and is optimized for high-level

languages such as ‘C’

• A separate internal RC oscillator (LPRC) with a

fixed, 31 kHz output, which provides a low-power

option for timing-insensitive applications.

• Operational performance up to 16 MIPS

The internal oscillator block also provides a stable ref-

erence source for the Fail-Safe Clock Monitor. This

option constantly monitors the main clock source

against a reference signal provided by the internal

oscillator and enables the controller to switch to the

internal oscillator, allowing for continued low-speed

operation or a safe application shutdown.

 2005-2012 Microchip Technology Inc.

DS39747F-page 7

PIC24FJ128GA010 FAMILY

1.1.4

EASY MIGRATION

1.3

Details on Individual Family

Members

Regardless of the memory size, all devices share the

same rich set of peripherals, allowing for a smooth

migration path as applications grow and evolve.

Devices in the PIC24FJ128GA010 family are available

in 64-pin, 80-pin and 100-pin packages. The general

block diagram for all devices is shown in Figure 1-1.

The consistent pinout scheme used throughout the

entire family also aids in migrating to the next larger

device. This is true when moving between devices with

the same pin count, or even jumping from 64-pin to

80-pin to 100-pin devices.

The devices are differentiated from each other in two

ways:

1. Flash program memory (64 Kbytes for

PIC24FJ64GA devices, 96 Kbytes for

PIC24FJ96GA devices and 128 Kbytes for

PIC24FJ128GA devices).

The PIC24F family is pin-compatible with devices in the

dsPIC33 family, and shares some compatibility with the

pinout schema for PIC18 and dsPIC30. This extends

the ability of applications to grow from the relatively

simple, to the powerful and complex, yet still selecting

a Microchip device.

2. Available I/O pins and ports (53 pins on 6 ports for

64-pin devices, 69 pins on 7 ports for 80-pin

devices and 84 pins on 7 ports for 100-pin

devices). Note also that, since interrupt-on-change

inputs are available on every I/O pin for this family

of devices, the number of CN inputs also differs

between package sizes.

1.2

Other Special Features

• Communications: The PIC24FJ128GA010

family incorporates a range of serial communica-

tion peripherals to handle a range of application

requirements. All devices are equipped with two

independent UARTs with built-in IrDA

All other features for devices in this family are identical.

These are summarized in Table 1-1.

A

list of the pin features available on the

PIC24FJ128GA010 family devices, sorted by function,

is shown in Table 1-2. Note that this table shows the pin

location of individual peripheral features and not how

they are multiplexed on the same pin. This information

is provided in the pinout diagrams in the beginning of

the data sheet. Multiplexed features are sorted by the

priority given to a feature, with the highest priority

peripheral being listed first.

encoder/decoders. There are also two indepen-

dent SPI modules, and two independent I²C

modules that support both Master and Slave

modes of operation.

• Parallel Master/Enhanced Parallel Slave Port:

One of the general purpose I/O ports can be

reconfigured for enhanced parallel data communi-

cations. In this mode, the port can be configured

for both master and slave operations, and

supports 8-bit and 16-bit data transfers with up to

16 external address lines in Master modes.

• Real-Time Clock/Calendar: This module

implements a full-featured clock and calendar with

alarm functions in hardware, freeing up timer

resources and program memory space for use of

the core application.

• 10-Bit A/D Converter: This module incorporates

programmable acquisition time, allowing for a

channel to be selected and a conversion to be

initiated without waiting for a sampling period, as

well as faster sampling speeds.

DS39747F-page 8

 2005-2012 Microchip Technology Inc.

PIC24FJ128GA010 FAMILY

TABLE 1-1:

DEVICE FEATURES FOR THE PIC24FJ128GA010 FAMILY

Features

Operating Frequency

DC – 32 MHz

96K

Program Memory (Bytes)

64K

96K

128K

64K

128K

64K

96K

128K

Program Memory (Instructions) 22,016 32,768 44,032 22,016 32,768 44,032 22,016 32,768 44,032

Data Memory (Bytes)

8192

Interrupt Sources

43

(Soft Vectors/NMI Traps)

(39/4)

I/O Ports

Ports B, C, D, E, F, G

53

Ports A, B, C, D, E, F, G

69

Ports A, B, C, D, E, F, G

84

Total I/O Pins

Timers:

Total Number (16-bit)

32-Bit (from paired 16-bit timers)

Input Capture Channels

5

2

5

Output Compare/PWM

Channels

Input Change Notification

Interrupt

19

22

Serial Communications:

UART

2

SPI (3-wire/4-wire)

I²C™

2

Parallel Communications

(PMP/PSP)

Yes

JTAG Boundary Scan

Yes

16

10-Bit Analog-to-Digital Module

(input channels)

Analog Comparators

Resets (and Delays)

2

POR, BOR, RESETInstruction, MCLR, WDT, Illegal Opcode, Configuration Word

Mismatch, REPEATInstruction, Hardware Traps (PWRT, OST, PLL Lock)

Instruction Set

Packages

76 Base Instructions, Multiple Addressing Mode Variations

64-Pin TQFP/QFN

80-Pin TQFP

100-Pin TQFP

 2005-2012 Microchip Technology Inc.

DS39747F-page 9

PIC24FJ128GA010 FAMILY

FIGURE 1-1:

PIC24FJ128GA010 FAMILY GENERAL BLOCK DIAGRAM

Data Bus

Interrupt

PORTA⁽¹⁾

Controller

RA0:RA7,

RA9:RA10,

RA14:15

16

8

Data Latch

Data RAM

PSV & Table

Data Access

Control Block

PCH

PCL

PORTB⁽¹⁾

RB0:RB15

23

Program Counter

Address

Latch

Repeat

Control

Logic

Stack

Control

Logic

16

23

16

Read AGU

Write AGU

Address Latch

Program Memory

Data Latch

PORTC

RC1:RC4,

RC12:RC15

EA MUX

PORTD⁽¹⁾

Address Bus

24

16

RD0:RD15

Inst Latch

Inst Register

PORTE⁽¹⁾

RE0:RE9

Instruction

Decode &

Control

Divide

Support

Control Signals

16 x 16

W Reg Array

17x17

Multiplier

PORTF⁽¹⁾

Power-up

Timer

Timing

OSC2/CLKO

OSC1/CLKI

Generation

RF0:RF8,

RF12:RF13

Oscillator

Start-up Timer

FRC/LPRC

Oscillators

16-Bit ALU

16

Power-on

Reset

Precision

Band Gap

Reference

PORTG⁽¹⁾

Watchdog

Timer

ENVREG

Brown-out

Reset⁽²⁾

RG0:RG9,

RG12:RG15

Voltage

Regulator

VDDCORE/VCAP

Timer1

VDD,VSS

MCLR

10-Bit

A/D

Timer2/3

Comparators

Timer4/5

RTCC

SPI1/2

PMP/PSP

PWM/

OC1-5

CN1-22⁽¹⁾

IC1-5

I2C1/2

UART1/2

Note 1: Not all pins or features are implemented on all device pinout configurations. See Table 1-2 for I/O port pin descriptions.

2: BOR functionality is provided when the on-board voltage regulator is enabled.

DS39747F-page 10

 2005-2012 Microchip Technology Inc.

PIC24FJ128GA010 FAMILY

TABLE 1-2:

PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS

Pin Number

Input

Buffer

Function

I/O

Description

64-Pin

80-Pin

100-Pin

AN0

AN1

16

15

14

13

12

11

17

18

21

22

23

24

27

28

29

30

19

20

35

29

12

11

21

14

13

22

39

40

48

47

16

15

14

13

12

11

4

20

19

18

17

16

15

21

22

27

28

29

30

33

34

35

36

25

26

38

35

16

15

27

18

17

28

49

50

60

59

20

19

18

17

16

15

6

25

24

23

22

21

20

26

27

32

33

34

35

41

42

43

44

30

31

48

39

21

20

32

23

22

33

63

64

74

73

25

24

23

22

21

20

10

11

12

14

44

81

82

83

84

49

I

ANA

—

A/D Analog Inputs.

AN2

I

AN3

I

AN4

I

AN5

I

AN6

I

AN7

I

AN8

I

AN9

I

AN10

AN11

AN12

AN13

AN14

AN15

AVDD

AVSS

BCLK1

BCLK2

C1IN-

C1IN+

C1OUT

C2IN-

C2IN+

C2OUT

CLKI

CLKO

CN0

I

P

O

I

Positive Supply for Analog Modules.

Ground Reference for Analog Modules.

—

®

—

UART1 IrDA Baud Clock.

®

—

UART2 IrDA Baud Clock.

ANA

—

Comparator 1 Negative Input.

Comparator 1 Positive Input.

Comparator 1 Output.

I

O

I

ANA

—

Comparator 2 Negative Input.

Comparator 2 Positive Input.

Comparator 2 Output.

I

O

I

ANA

—

Main Clock Input Connection.

System Clock Output.

O

I

ST

Interrupt-on-Change Inputs.

CN1

I

ST

CN2

I

ST

CN3

I

ST

CN4

I

ST

CN5

I

ST

CN6

I

ST

CN7

I

ST

CN8

I

ST

CN9

5

7

I

ST

CN10

CN11

CN12

CN13

CN14

CN15

CN16

CN17

6

8

I

ST

8

10

36

66

67

68

69

39

I

ST

30

52

53

54

55

31

I

ST

I

ST

I

ST

I

ST

I

ST

I

ST

2

Legend:

TTL = TTL input buffer, ST = Schmitt Trigger input buffer, ANA = Analog level input/output, I C™ = I C/SMBus input buffer

 2005-2012 Microchip Technology Inc.

DS39747F-page 11

PIC24FJ128GA010 FAMILY

TABLE 1-2:

PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Pin Number

Input

Buffer

Function

I/O

Description

Interrupt-on-Change Inputs.

64-Pin

80-Pin

100-Pin

CN18

CN19

CN20

CN21

CVREF

EMUC1

EMUD1

EMUC2

EMUD2

ENVREG

IC1

32

—

23

15

16

17

18

57

42

43

44

45

52

35

42

43

44

45

7

40

65

37

38

29

19

20

21

22

71

54

55

56

57

64

45

13

14

52

53

9

50

80

47

48

34

24

25

26

27

86

68

69

70

71

79

55

18

19

66

67

13

I

ST

ANA

ST

I

O

Comparator Voltage Reference Output.

In-Circuit Emulator Clock Input/Output.

In-Circuit Emulator Data Input/Output.

In-Circuit Emulator Clock Input/Output.

In-Circuit Emulator Data Input/Output.

Enable for On-Chip Voltage Regulator.

Input Capture Inputs.

I/O

I

IC2

IC3

IC4

IC5

INT0

External Interrupt Inputs.

INT1

INT2

INT3

INT4

MCLR

Master Clear (Device Reset) Input. This line is brought

low to cause a Reset.

OC1

OC2

46

49

50

51

52

17

30

39

40

15

16

17

18

58

61

62

63

66

21

36

49

50

19

20

21

22

72

76

77

78

81

26

44

63

64

24

25

26

27

O

—

Output Compare/PWM Outputs.

OC3

O

—

OC4

O

—

OC5

O

—

OCFA

OCFB

OSC1

OSC2

PGC1

PGD1

PGC2

PGD2

I

ST

ANA

ST

Output Compare Fault A Input.

I

Output Compare Fault B Input.

I

Main Oscillator Input Connection.

O

Main Oscillator Output Connection.

I/O

In-Circuit Debugger and ICSP™ Programming Clock.

In-Circuit Debugger and ICSP Programming Data.

In-Circuit Debugger and ICSP™ Programming Clock.

In-Circuit Debugger and ICSP Programming Data.

2

Legend:

TTL = TTL input buffer, ST = Schmitt Trigger input buffer, ANA = Analog level input/output, I C™ = I C/SMBus input buffer

DS39747F-page 12

 2005-2012 Microchip Technology Inc.

PIC24FJ128GA010 FAMILY

TABLE 1-2:

PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Pin Number

80-Pin

36

Input

Buffer

Function

I/O

Description

64-Pin

100-Pin

PMA0

PMA1

30

44

I/O

ST/TTL Parallel Master Port Address Bit 0 Input (Buffered Slave

modes) and Output (Master modes).

29

35

43

ST/TTL Parallel Master Port Address Bit 1 Input (Buffered Slave

modes) and Output (Master modes).

PMA2

PMA3

PMA4

PMA5

PMA6

PMA7

PMA8

PMA9

PMA10

PMA11

PMA12

PMA13

PMBE

PMCS1

PMCS2

PMD0

PMD1

PMD2

PMD3

PMD4

PMD5

PMD6

PMD7

PMRD

PMWR

8

10

8

14

12

11

10

29

28

50

49

42

41

35

34

78

71

70

93

94

98

99

100

3

O

—

Parallel Master Port Address (Demultiplexed Master

modes).

6

5

7

O

4

6

O

16

22

32

31

28

27

24

23

51

45

44

60

61

62

63

64

1

24

23

40

39

34

33

30

29

63

57

56

76

77

78

79

80

1

O

Parallel Master Port Byte Enable Strobe.

I/O

O

ST/TTL Parallel Master Port Chip Select 1 Strobe/Address bit 14.

Parallel Master Port Chip Select 2 Strobe/Address bit 15.

—

I/O

ST/TTL Parallel Master Port Data (Demultiplexed Master mode)

or Address/Data (Multiplexed Master modes).

ST/TTL

2

4

ST/TTL

3

5

ST/TTL

53

52

67

66

82

81

ST/TTL Parallel Master Port Read Strobe.

ST/TTL Parallel Master Port Write Strobe.

2

Legend:

TTL = TTL input buffer, ST = Schmitt Trigger input buffer, ANA = Analog level input/output, I C™ = I C/SMBus input buffer

 2005-2012 Microchip Technology Inc.

DS39747F-page 13

PIC24FJ128GA010 FAMILY

TABLE 1-2:

PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Pin Number

Input

Buffer

Function

I/O

Description

64-Pin

80-Pin

100-Pin

RA0

RA1

—

16

15

14

13

12

11

17

18

21

22

23

24

27

28

29

30

—

39

47

48

40

—

23

24

52

53

20

19

18

17

16

15

21

22

27

28

29

30

33

34

35

36

4

17

38

58

59

60

61

91

92

28

29

66

67

25

24

23

22

21

20

26

27

32

33

34

35

41

42

43

44

6

I/O

ST

PORTA Digital I/O.

RA2

RA3

RA4

RA5

RA6

RA7

RA9

RA10

RA14

RA15

RB0

PORTB Digital I/O.

RB1

RB2

RB3

RB4

RB5

RB6

RB7

RB8

RB9

RB10

RB11

RB12

RB13

RB14

RB15

RC1

RC2

RC3

RC4

RC12

RC13

RC14

RC15

PORTC Digital I/O.

—

5

7

8

—

49

59

60

50

9

63

73

74

64

2

Legend:

TTL = TTL input buffer, ST = Schmitt Trigger input buffer, ANA = Analog level input/output, I C™ = I C/SMBus input buffer

DS39747F-page 14

 2005-2012 Microchip Technology Inc.

PIC24FJ128GA010 FAMILY

TABLE 1-2:

PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Pin Number

Input

Buffer

Function

I/O

Description

64-Pin

80-Pin

100-Pin

RD0

RD1

RD2

RD3

RD4

RD5

RD6

RD7

RD8

RD9

RD10

RD11

RD12

RD13

RD14

RD15

RE0

RE1

RE2

RE3

RE4

RE5

RE6

RE7

RE8

RE9

RF0

46

49

50

51

52

53

54

55

42

43

44

45

—

60

61

62

63

64

1

58

61

62

63

66

67

68

69

54

55

56

57

64

65

37

38

76

77

78

79

80

1

72

76

77

78

81

82

83

84

68

69

70

71

79

80

47

48

93

94

98

99

100

3

I/O

ST

PORTD Digital I/O.

PORTE Digital I/O.

2

4

3

5

—

58

59

34

33

31

32

35

—

13

14

72

73

42

41

39

40

45

44

43

—

18

19

87

88

52

51

49

50

55

54

53

40

39

PORTF Digital I/O.

RF1

RF2

RF3

RF4

RF5

RF6

RF7

RF8

RF12

RF13

2

Legend:

TTL = TTL input buffer, ST = Schmitt Trigger input buffer, ANA = Analog level input/output, I C™ = I C/SMBus input buffer

 2005-2012 Microchip Technology Inc.

DS39747F-page 15

PIC24FJ128GA010 FAMILY

TABLE 1-2:

PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Pin Number

Input

Buffer

Function

I/O

Description

64-Pin

80-Pin

100-Pin

RG0

RG1

—

37

36

4

75

74

47

46

6

90

89

57

56

10

11

12

14

96

97

95

1

I/O

O

ST

—

PORTG Digital I/O.

RG2

RG3

RG6

RG7

5

7

RG8

6

8

RG9

8

10

—

54

45

6

RG12

RG13

RG14

RG15

RTCC

SCK1

SCK2

SCL1

SCL2

SDA1

SDA2

SDI1

SDI2

SDO1

SDO2

SOSCI

SOSCO

SS1

—

42

35

4

68

55

10

57

58

56

59

54

11

53

12

73

74

23

14

74

6

Real-Time Clock Alarm Output.

SPI1 Serial Clock Output.

O

—

I/O

I

ST

SPI2 Serial Clock Output.

2

37

32

36

31

34

5

47

52

46

53

44

7

I C

I2C1 Synchronous Serial Clock Input/Output.

I2C2 Synchronous Serial Clock Input/Output.

I2C1 Data Input/Output.

2

I C

2

I C

2

I C

I2C2 Data Input/Output.

ST

—

SPI1 Serial Data Input.

I

SPI2 Serial Data Input.

33

6

43

8

O

SPI1 Serial Data Output.

O

—

SPI2 Serial Data Output.

47

48

14

8

59

60

18

10

60

4

I

ANA

ST

—

Secondary Oscillator/Timer1 Clock Input.

Secondary Oscillator/Timer1 Clock Output.

Slave Select Input/Frame Select Output (SPI1).

Slave Select Input/Frame Select Output (SPI2).

Timer1 Clock.

O

I/O

I

SS2

T1CK

T2CK

T3CK

T4CK

T5CK

TCK

48

—

27

28

24

23

I

Timer2 External Clock Input.

—

5

7

I

Timer3 External Clock Input.

8

I

Timer4 External Clock Input.

—

33

34

14

13

9

I

Timer5 External Clock Input.

38

60

61

17

I

JTAG Test Clock/Programming Clock Input.

JTAG Test Data/Programming Data Input.

JTAG Test Data Output.

TDI

I

TDO

O

TMS

I

ST

JTAG Test Mode Select Input.

2

Legend:

TTL = TTL input buffer, ST = Schmitt Trigger input buffer, ANA = Analog level input/output, I C™ = I C/SMBus input buffer

DS39747F-page 16

 2005-2012 Microchip Technology Inc.

PIC24FJ128GA010 FAMILY

TABLE 1-2:

PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Pin Number

Input

Buffer

Function

I/O

Description

64-Pin

80-Pin

100-Pin

U1CTS

U1RTS

U1RX

U1TX

43

35

34

33

21

29

31

32

37

38

42

41

27

35

39

40

47

48

52

51

40

39

49

50

I

O

I

ST

—

UART1 Clear-to-Send Input.

UART1 Request-to-Send Output.

UART1 Receive.

ST

DIG

ST

—

O

I

UART1 Transmit Output.

U2CTS

U2RTS

U2RX

U2TX

UART2 Clear-to-Send Input.

UART2 Request-to-Send Output.

UART 2 Receive Input.

O

I

ST

—

O

P

UART2 Transmit Output.

VDD

10, 26, 38 12, 32, 48 2, 16, 37,

46, 62

—

Positive Supply for Peripheral Digital Logic and I/O Pins.

VDDCAP

56

70

85

P

—

External Filter Capacitor Connection (regulator is

enabled).

VDDCORE

56

70

85

Positive Supply for Microcontroller Core Logic (regulator

is disabled).

VREF-

VREF+

VSS

15

16

23

24

28

29

I

ANA

—

A/D and Comparator Reference Voltage (Low) Input.

A/D and Comparator Reference Voltage (High) Input.

Ground Reference for Logic and I/O Pins.

9, 25, 41

11, 31, 51 15, 36, 45,

65, 75

P

2

Legend:

TTL = TTL input buffer, ST = Schmitt Trigger input buffer, ANA = Analog level input/output, I C™ = I C/SMBus input buffer

 2005-2012 Microchip Technology Inc.

DS39747F-page 17

PIC24FJ128GA010 FAMILY

NOTES:

DS39747F-page 18

 2005-2012 Microchip Technology Inc.

PIC24FJ128GA010 FAMILY

FIGURE 2-1:

RECOMMENDED

MINIMUM CONNECTIONS

2.0

2.1

GUIDELINES FOR GETTING

STARTED WITH 16-BIT

MICROCONTROLLERS

(2)

C2

VDD

Basic Connection Requirements

Getting started with the PIC24FJ128GA010 family

family of 16-bit microcontrollers requires attention to a

minimal set of device pin connections before

proceeding with development.

(1)

R1

R2

(EN/DIS)VREG

VCAP/VDDCORE

MCLR

C1

The following pins must always be connected:

C7

PIC24FJXXXX

• All VDD and VSS pins

(see Section 2.2 “Power Supply Pins”)

VDD

VSS

VDD

(2)

C3

C6

• All AVDD and AVSS pins, regardless of whether or

not the analog device features are used

(see Section 2.2 “Power Supply Pins”)

• MCLR pin

(see Section 2.3 “Master Clear (MCLR) Pin”)

(2)

C4

C5

• ENVREG/DISVREG and VCAP/VDDCORE pins

(PIC24F J devices only)

(see Section 2.4 “Voltage Regulator Pins

(ENVREG/DISVREG and VCAP/VDDCORE)”)

Key (all values are recommendations):

C1 through C6: 0.1 F, 20V ceramic

These pins must also be connected if they are being

used in the end application:

C7: 10 F, 6.3V or greater, tantalum or ceramic

R1: 10 kΩ

• PGECx/PGEDx pins used for In-Circuit Serial

Programming™ (ICSP™) and debugging purposes

(see Section 2.5 “ICSP Pins”)

R2: 100Ω to 470Ω

Note 1: See Section 2.4 “Voltage Regulator Pins

(ENVREG/DISVREG and VCAP/VDDCORE)”

for explanation of ENVREG/DISVREG pin

connections.

• OSCI and OSCO pins when an external oscillator

source is used

(see Section 2.6 “External Oscillator Pins”)

2: The example shown is for a PIC24F device

with five VDD/VSS and AVDD/AVSS pairs.

Other devices may have more or less pairs;

adjust the number of decoupling capacitors

appropriately.

Additionally, the following pins may be required:

• VREF+/VREF- pins used when external voltage

reference for analog modules is implemented

Note:

The AVDD and AVSS pins must always be

connected, regardless of whether any of

the analog modules are being used.

The minimum mandatory connections are shown in

Figure 2-1.

 2005-2012 Microchip Technology Inc.

DS39747F-page 19

PIC24FJ128GA010 FAMILY

2.2

Power Supply Pins

2.3

Master Clear (MCLR) Pin

The MCLR pin provides two specific device

functions: device Reset, and device programming

and debugging. If programming and debugging are

2.2.1

DECOUPLING CAPACITORS

The use of decoupling capacitors on every pair of

power supply pins, such as VDD, VSS, AVDD and

AVSS is required.

not required in the end application,

a

direct

connection to VDD may be all that is required. The

addition of other components, to help increase the

application’s resistance to spurious Resets from

Consider the following criteria when using decoupling

capacitors:

voltage sags, may be beneficial.

A

typical

• Value and type of capacitor: A 0.1 F (100 nF),

10-20V capacitor is recommended. The capacitor

should be a low-ESR device with a resonance

frequency in the range of 200 MHz and higher.

Ceramic capacitors are recommended.

configuration is shown in Figure 2-1. Other circuit

designs may be implemented, depending on the

application’s requirements.

During programming and debugging, the resistance

and capacitance that can be added to the pin must

be considered. Device programmers and debuggers

drive the MCLR pin. Consequently, specific voltage

levels (VIH and VIL) and fast signal transitions must

not be adversely affected. Therefore, specific values

of R1 and C1 will need to be adjusted based on the

application and PCB requirements. For example, it is

recommended that the capacitor, C1, be isolated

from the MCLR pin during programming and

debugging operations by using a jumper (Figure 2-2).

The jumper is replaced for normal run-time

operations.

• Placement on the printed circuit board: The

decoupling capacitors should be placed as close

to the pins as possible. It is recommended to

place the capacitors on the same side of the

board as the device. If space is constricted, the

capacitor can be placed on another layer on the

PCB using a via; however, ensure that the trace

length from the pin to the capacitor is no greater

than 0.25 inch (6 mm).

• Handling high-frequency noise: If the board is

experiencing high-frequency noise (upward of

tens of MHz), add a second ceramic type capaci-

tor in parallel to the above described decoupling

capacitor. The value of the second capacitor can

be in the range of 0.01 F to 0.001 F. Place this

second capacitor next to each primary decoupling

capacitor. In high-speed circuit designs, consider

implementing a decade pair of capacitances as

close to the power and ground pins as possible

(e.g., 0.1 F in parallel with 0.001 F).

Any components associated with the MCLR pin

should be placed within 0.25 inch (6 mm) of the pin.

FIGURE 2-2:

EXAMPLE OF MCLR PIN

CONNECTIONS

VDD

• Maximizing performance: On the board layout

from the power supply circuit, run the power and

return traces to the decoupling capacitors first,

and then to the device pins. This ensures that the

decoupling capacitors are first in the power chain.

Equally important is to keep the trace length

between the capacitor and the power pins to a

minimum, thereby reducing PCB trace

R1

R2

MCLR

PIC24FXXXX

JP

C1

inductance.

Note 1: R1  10 k is recommended. A suggested

starting value is 10 k. Ensure that the

MCLR pin VIH and VIL specifications are met.

2.2.2

TANK CAPACITORS

On boards with power traces running longer than six

inches in length, it is suggested to use a tank capacitor

for integrated circuits including microcontrollers to

supply a local power source. The value of the tank

capacitor should be determined based on the trace

resistance that connects the power supply source to

the device, and the maximum current drawn by the

device in the application. In other words, select the tank

capacitor so that it meets the acceptable voltage sag at

the device. Typical values range from 4.7 F to 47 F.

2: R2  470 will limit any current flowing into

MCLR from the external capacitor, C, in the

event of MCLR pin breakdown, due to

Electrostatic Discharge (ESD) or Electrical

Overstress (EOS). Ensure that the MCLR pin

VIH and VIL specifications are met.

DS39747F-page 20

 2005-2012 Microchip Technology Inc.

PIC24FJ128GA010 FAMILY

Designers may use Figure 2-3 to evaluate ESR

equivalence of candidate devices.

2.4

Voltage Regulator Pins

(ENVREG/DISVREG and

VCAP/VDDCORE)

The placement of this capacitor should be close to

VCAP/VDDCORE. It is recommended that the trace

Note:

This section applies only to PIC24F J

devices with an on-chip voltage regulator.

length not exceed 0.25 inch (6 mm). Refer to

Section 27.0 “Electrical Characteristics” for

additional information.

The on-chip voltage regulator enable/disable pin

(ENVREG or DISVREG, depending on the device

family) must always be connected directly to either a

supply voltage or to ground. The particular connection

is determined by whether or not the regulator is to be

used:

When the regulator is disabled, the VCAP/VDDCORE pin

must be tied to a voltage supply at the VDDCORE level.

Refer to Section 27.0 “Electrical Characteristics” for

information on VDD and VDDCORE.

FIGURE 2-3:

FREQUENCY vs. ESR

PERFORMANCE FOR

SUGGESTED VCAP

• For ENVREG, tie to VDD to enable the regulator,

or to ground to disable the regulator

• For DISVREG, tie to ground to enable the

regulator or to VDD to disable the regulator

10

1

Refer to Section 24.2 “On-Chip Voltage Regulator”

for details on connecting and using the on-chip

regulator.

When the regulator is enabled, a low-ESR (< 5Ω)

capacitor is required on the VCAP/VDDCORE pin to

stabilize the voltage regulator output voltage. The

VCAP/VDDCORE pin must not be connected to VDD and

must use a capacitor of 10 µF connected to ground. The

type can be ceramic or tantalum. Suitable examples of

capacitors are shown in Table 2-1. Capacitors with

equivalent specification can be used.

0.1

0.01

0.001

0.01

0.1

1

10

100

1000 10,000

Frequency (MHz)

Note:

Typical data measurement at 25°C, 0V DC bias.

.

TABLE 2-1:

Make

SUITABLE CAPACITOR EQUIVALENTS

Nominal

Part #

Base Tolerance Rated Voltage Temp. Range

Capacitance

TDK

C3216X7R1C106K

C3216X5R1C106K

10 µF

±10%

16V

-55 to 125ºC

-55 to 85ºC

-55 to 125ºC

-55 to 85ºC

-55 to 125ºC

-55 to 85ºC

Panasonic

Murata

ECJ-3YX1C106K

ECJ-4YB1C106K

GRM32DR71C106KA01L

GRM31CR61C106KC31L

Murata

 2005-2012 Microchip Technology Inc.

DS39747F-page 21

PIC24FJ128GA010 FAMILY

2.4.1

CONSIDERATIONS FOR CERAMIC

CAPACITORS

FIGURE 2-4:

DC BIAS VOLTAGE vs.

CAPACITANCE

CHARACTERISTICS

In recent years, large value, low-voltage, surface-mount

ceramic capacitors have become very cost effective in

sizes up to a few tens of microfarad. The low-ESR, small

physical size and other properties make ceramic

capacitors very attractive in many types of applications.

10

0

-10

-20

-30

-40

-50

-60

-70

16V Capacitor

10V Capacitor

Ceramic capacitors are suitable for use with the inter-

nal voltage regulator of this microcontroller. However,

some care is needed in selecting the capacitor to

ensure that it maintains sufficient capacitance over the

intended operating range of the application.

6.3V Capacitor

-80

0

1

2

3

4

5

6

7

8

9

10 11 12

13 14 15

16 17

DC Bias Voltage (VDC)

Typical low-cost, 10 F ceramic capacitors are available

in X5R, X7R and Y5V dielectric ratings (other types are

also available, but are less common). The initial toler-

ance specifications for these types of capacitors are

often specified as ±10% to ±20% (X5R and X7R), or

-20%/+80% (Y5V). However, the effective capacitance

that these capacitors provide in an application circuit will

also vary based on additional factors, such as the

applied DC bias voltage and the temperature. The total

in-circuit tolerance is, therefore, much wider than the

initial tolerance specification.

When selecting a ceramic capacitor to be used with the

internal voltage regulator, it is suggested to select a

high-voltage rating, so that the operating voltage is a

small percentage of the maximum rated capacitor volt-

age. For example, choose a ceramic capacitor rated at

16V for the 2.5V or 1.8V core voltage. Suggested

capacitors are shown in Table 2-1.

2.5

ICSP Pins

The X5R and X7R capacitors typically exhibit satisfac-

tory temperature stability (ex: ±15% over a wide

temperature range, but consult the manufacturer's data

sheets for exact specifications). However, Y5V capaci-

tors typically have extreme temperature tolerance

specifications of +22%/-82%. Due to the extreme tem-

perature tolerance, a 10 F nominal rated Y5V type

capacitor may not deliver enough total capacitance to

meet minimum internal voltage regulator stability and

transient response requirements. Therefore, Y5V

capacitors are not recommended for use with the

internal regulator if the application must operate over a

wide temperature range.

The PGECx and PGEDx pins are used for In-Circuit

Serial Programming (ICSP) and debugging purposes.

It is recommended to keep the trace length between

the ICSP connector and the ICSP pins on the device as

short as possible. If the ICSP connector is expected to

experience an ESD event, a series resistor is recom-

mended, with the value in the range of a few tens of

ohms, not to exceed 100Ω.

Pull-up resistors, series diodes and capacitors on the

PGECx and PGEDx pins are not recommended as they

will interfere with the programmer/debugger communi-

cations to the device. If such discrete components are

an application requirement, they should be removed

from the circuit during programming and debugging.

Alternatively, refer to the AC/DC characteristics and

timing requirements information in the respective

device Flash programming specification for information

on capacitive loading limits and pin input voltage high

(VIH) and input low (VIL) requirements.

In addition to temperature tolerance, the effective

capacitance of large value ceramic capacitors can vary

substantially, based on the amount of DC voltage

applied to the capacitor. This effect can be very signifi-

cant, but is often overlooked or is not always

documented.

Typical DC bias voltage vs. capacitance graph for X7R

type capacitors is shown in Figure 2-4.

For device emulation, ensure that the “Communication

Channel Select” (i.e., PGECx/PGEDx pins),

programmed into the device, matches the physical

connections for the ICSP to the Microchip

debugger/emulator tool.

For more information on available Microchip

development tools connection requirements, refer to

Section 26.0 “Development Support”.

DS39747F-page 22

 2005-2012 Microchip Technology Inc.

PIC24FJ128GA010 FAMILY

FIGURE 2-5:

SUGGESTED

2.6

External Oscillator Pins

PLACEMENT OF THE

OSCILLATOR CIRCUIT

Many microcontrollers have options for at least two

oscillators: a high-frequency primary oscillator and a

low-frequency

secondary

oscillator

(refer to

Single-Sided and In-line Layouts:

Section 8.0 “Oscillator Configuration” for details).

Copper Pour

(tied to ground)

Primary Oscillator

Crystal

The oscillator circuit should be placed on the same

side of the board as the device. Place the oscillator

circuit close to the respective oscillator pins with no

more than 0.5 inch (12 mm) between the circuit

components and the pins. The load capacitors should

be placed next to the oscillator itself, on the same side

of the board.

DEVICE PINS

Primary

OSCI

OSCO

GND

Oscillator

C1

C2

`

Use a grounded copper pour around the oscillator cir-

cuit to isolate it from surrounding circuits. The

grounded copper pour should be routed directly to the

MCU ground. Do not run any signal traces or power

traces inside the ground pour. Also, if using a two-sided

board, avoid any traces on the other side of the board

where the crystal is placed.

SOSCO

SOSC I

Secondary

Oscillator

Crystal

`

Layout suggestions are shown in Figure 2-5. In-line

packages may be handled with a single-sided layout

that completely encompasses the oscillator pins. With

fine-pitch packages, it is not always possible to com-

pletely surround the pins and components. A suitable

solution is to tie the broken guard sections to a mirrored

ground layer. In all cases, the guard trace(s) must be

returned to ground.

Sec Oscillator: C2

Sec Oscillator: C1

Fine-Pitch (Dual-Sided) Layouts:

Top Layer Copper Pour

(tied to ground)

In planning the application’s routing and I/O assign-

ments, ensure that adjacent port pins, and other

signals in close proximity to the oscillator, are benign

(i.e., free of high frequencies, short rise and fall times

and other similar noise).

Bottom Layer

Copper Pour

(tied to ground)

OSCO

For additional information and design guidance on

oscillator circuits, please refer to these Microchip

Application Notes, available at the corporate web site

(www.microchip.com):

C2

Oscillator

Crystal

GND

• AN826, “Crystal Oscillator Basics and Crystal

Selection for rfPIC™ and PICmicro^®Devices”

C1

• AN849, “Basic PICmicro^®Oscillator Design”

OSCI

• AN943, “Practical PICmicro^®Oscillator Analysis

and Design”

• AN949, “Making Your Oscillator Work”

DEVICE PINS

 2005-2012 Microchip Technology Inc.

DS39747F-page 23

PIC24FJ128GA010 FAMILY

If your application needs to use certain A/D pins as

analog input pins during the debug session, the user

application must modify the appropriate bits during

initialization of the A/D module, as follows:

2.7

Configuration of Analog and

Digital Pins During ICSP

Operations

If an ICSP compliant emulator is selected as a debug-

ger, it automatically initializes all of the A/D input pins

(ANx) as “digital” pins. Depending on the particular

device, this is done by setting all bits in the ADnPCFG

register(s), or clearing all bit in the ANSx registers.

• For devices with an ADnPCFG register, clear the

bits corresponding to the pin(s) to be configured

as analog. Do not change any other bits, particu-

larly those corresponding to the PGECx/PGEDx

pair, at any time.

All PIC24F devices will have either one or more

ADnPCFG registers or several ANSx registers (one for

each port); no device will have both. Refer to

Section 21.0 “10-bit High-Speed A/D Converter” for

more specific information.

• For devices with ANSx registers, set the bits

corresponding to the pin(s) to be configured as

analog. Do not change any other bits, particularly

those corresponding to the PGECx/PGEDx pair,

at any time.

The bits in these registers that correspond to the A/D

pins that initialized the emulator must not be changed

by the user application firmware; otherwise,

communication errors will result between the debugger

and the device.

When a Microchip debugger/emulator is used as a

programmer, the user application firmware must

correctly configure the ADnPCFG or ANSx registers.

Automatic initialization of this register is only done

during debugger operation. Failure to correctly

configure the register(s) will result in all A/D pins being

recognized as analog input pins, resulting in the port

value being read as a logic '0', which may affect user

application functionality.

2.8

Unused I/Os

Unused I/O pins should be configured as outputs and

driven to a logic low state. Alternatively, connect a 1 kΩ

to 10 kΩ resistor to VSS on unused pins and drive the

output to logic low.

DS39747F-page 24

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PIC24FJ128GA010 FAMILY

For most instructions, the core is capable of executing

a data (or program data) memory read, a working reg-

3.0

CPU

Note: This data sheet summarizes the features of

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. Refer to Section 2. “CPU”

(DS39703) in the “PIC24F Family Reference

Manual” for more information.

ister (data) read, a data memory write and a program

(instruction) memory read per instruction cycle. As a

result, three parameter instructions can be supported,

allowing trinary operations (that is, A + B = C) to be

executed in a single cycle.

A high-speed, 17-bit by 17-bit multiplier has been

included to significantly enhance the core arithmetic

capability and throughput. The multiplier supports

signed, unsigned and Mixed mode 16-bit by 16-bit or

8-bit by 8-bit integer multiplication. All multiply

instructions execute in a single cycle.

The PIC24F CPU has a 16-bit (data) modified Harvard

architecture with an enhanced instruction set, and a

24-bit instruction word with a variable length opcode

field. The Program Counter (PC) is 23 bits wide and

addresses up to 4M instructions of user program

memory space. A single-cycle instruction prefetch

mechanism is used to help maintain throughput and

provides predictable execution. All instructions execute

in a single cycle, with the exception of instructions that

change the program flow, the double-word move

(MOV.D) instruction and the table instructions.

Overhead-free program loop constructs are supported

using the REPEATinstructions, which are interruptible

at any point.

The 16-bit ALU has been enhanced with integer divide

assist hardware that supports an iterative, non-restoring

divide algorithm. It operates in conjunction with the

REPEATinstruction looping mechanism, and a selection

of iterative divide instructions, to support 32-bit (or

16-bit) divided by 16-bit integer signed and unsigned

division. All divide operations require 19 cycles to

complete but are interruptible at any cycle boundary.

The PIC24F has a vectored exception scheme with up

to 8 sources of non-maskable traps and up to

118 interrupt sources. Each interrupt source can be

assigned to one of seven priority levels.

PIC24F devices have sixteen 16-bit working registers

in the programmer’s model. Each of the working

registers can act as a data, address or address offset

register. The 16th working register (W15) operates as

a Software Stack Pointer for interrupts and calls.

A block diagram of the CPU is shown in Figure 3-1.

The upper 32 Kbytes of the data space memory map

can optionally be mapped into program space at any

16K word boundary defined by the 8-bit Program

Space Visibility Page (PSVPAG) register. The program

to data space mapping feature lets any instruction

access program space as if it were data space.

3.1

Programmer’s Model

The programmer’s model for the PIC24F is shown in

Figure 3-2. All registers in the programmer’s model are

memory mapped and can be manipulated directly by

instructions. A description of each register is provided

in Table 3-1. All registers associated with the

programmer’s model are memory mapped.

The Instruction Set Architecture (ISA) has been signifi-

cantly enhanced beyond that of the PIC18, but

maintains an acceptable level of backward compatibility.

All PIC18 instructions and addressing modes are

supported either directly or through simple macros.

Many of the ISA enhancements have been driven by

compiler efficiency needs.

The core supports Inherent (no operand), Relative,

Literal, Memory Direct and three groups of addressing

modes. All modes support Register Direct and various

Register Indirect modes. Each group offers up to

7 addressing modes. Instructions are associated with

predefined addressing modes depending upon their

functional requirements.

 2005-2012 Microchip Technology Inc.

DS39747F-page 25

PIC24FJ128GA010 FAMILY

FIGURE 3-1:

PIC24F CPU CORE BLOCK DIAGRAM

PSV & Table

Data Access

Control Block

Data Bus

Interrupt

Controller

16

8

Data Latch

Data RAM

23

16

PCL

Program Counter

PCH

23

Address

Latch

Stack

Control

Logic

Loop

Control

Logic

23

16

RAGU

WAGU

Address Latch

Program Memory

Data Latch

EA MUX

16

Address Bus

ROM Latch

24

16

Instruction

Decode &

Control

Instruction Reg

Control Signals

to Various Blocks

Hardware

Multiplier

16 x 16

W Register Array

Divide

16

Support

16-Bit ALU

16

To Peripheral Modules

DS39747F-page 26

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PIC24FJ128GA010 FAMILY

TABLE 3-1:

CPU CORE REGISTERS

Register(s) Name

Description

W0 through W15

PC

Working Register Array

23-Bit Program Counter

SR

ALU STATUS Register

SPLIM

Stack Pointer Limit Value Register

Table Memory Page Address Register

Program Space Visibility Page Address Register

Repeat Loop Counter Register

CPU Control Register

TBLPAG

PSVPAG

RCOUNT

CORCON

FIGURE 3-2:

PROGRAMMER’S MODEL

15

0

W0 (WREG)

Divider Working Registers

Multiplier Registers

W1

W2

W3

W4

W5

W6

W7

Working/Address

Registers

W8

W9

W10

W11

W12

W13

W14

W15

Frame Pointer

Stack Pointer

0

Stack Pointer Limit

Program Counter

0

SPLIM

22

0

PC

7

0

TBLPAG

Data Table Page Address

7

Program Space Visibility

Page Address

PSVPAG

15

RCOUNT

IPL

Repeat Loop Counter

SRL

0

SRH

STATUS Register (SR)

— — — — — — —

DC

RA N OV Z

C

2 1 0

15

0

— — — — — — — — — — — — IPL3 PSV — —

Core Control Register (CORCON)

Registers or bits are shadowed for PUSH.Sand POP.Sinstructions.

 2005-2012 Microchip Technology Inc.

DS39747F-page 27

PIC24FJ128GA010 FAMILY

3.2

CPU Control Registers

REGISTER 3-1:

SR: CPU STATUS REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

DC

bit 15

bit 8

R/W-0⁽¹⁾

IPL2⁽²⁾

bit 7

R/W-0⁽¹⁾

IPL1⁽²⁾

R/W-0⁽¹⁾

IPL0⁽²⁾

R-0

RA

R/W-0

N

R/W-0

OV

R/W-0

Z

R/W-0

C

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-9

bit 8

Unimplemented: Read as ‘0’

DC: ALU Half Carry/Borrow bit

1= A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)

of the result occurred

0= No carry-out from the 4th or 8th low-order bit of the result has occurred

bit 7-5

IPL<2:0>: CPU Interrupt Priority Level Status bits⁽²⁾

111= CPU Interrupt Priority Level is 7 (15); user interrupts are disabled

110= CPU Interrupt Priority Level is 6 (14)

101= CPU Interrupt Priority Level is 5 (13)

100= CPU Interrupt Priority Level is 4 (12)

011= CPU Interrupt Priority Level is 3 (11)

010= CPU Interrupt Priority Level is 2 (10)

001= CPU Interrupt Priority Level is 1 (9)

000= CPU Interrupt Priority Level is 0 (8)

bit 4

bit 3

bit 2

bit 1

bit 0

RA: REPEATLoop Active bit

1= REPEATloop in progress

0= REPEATloop not in progress

N: ALU Negative bit

1= Result was negative

0= Result was non-negative (zero or positive)

OV: ALU Overflow bit

1= Overflow occurred for signed (2’s complement) arithmetic in this arithmetic operation

0= No overflow has occurred

Z: ALU Zero bit

1= An operation, which effects the Z bit, has set it at some time in the past

0= The most recent operation, which effects the Z bit, has cleared it (i.e., a non-zero result)

C: ALU Carry/Borrow bit

1= A carry-out from the Most Significant bit of the result occurred

0= No carry-out from the Most Significant bit of the result occurred

Note 1: The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1.

2: The IPL bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU Interrupt Priority Level.

The value in parentheses indicates the IPL when IPL3 = 1.

DS39747F-page 28

 2005-2012 Microchip Technology Inc.

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REGISTER 3-2:

CORCON: CORE CONTROL REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

U-0

—

U-0

—

U-0

—

R/C-0

IPL3⁽¹⁾

R/W-0

PSV

U-0

—

U-0

—

bit 7

Legend:

C = Clearable bit

W = Writable bit

‘1’ = Bit is set

R = Readable bit

-n = Value at POR

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-4

bit 3

Unimplemented: Read as ‘0’

IPL3: CPU Interrupt Priority Level Status bit⁽¹⁾

1= CPU Interrupt Priority Level is greater than 7

0= CPU Interrupt Priority Level is 7 or less

bit 2

PSV: Program Space Visibility in Data Space Enable bit

1= Program space is visible in data space

0= Program space is not visible in data space

bit 1-0

Unimplemented: Read as ‘0’

Note 1: User interrupts are disabled when IPL3 = 1.

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DS39747F-page 29

PIC24FJ128GA010 FAMILY

3.3.2

DIVIDER

3.3

Arithmetic Logic Unit (ALU)

The divide block supports 32-bit/16-bit and 16-bit/16-bit

signed and unsigned integer divide operation with the

following data sizes:

The PIC24F ALU is 16 bits wide and is capable of addi-

tion, subtraction, bit shifts and logic operations. Unless

otherwise mentioned, arithmetic operations are 2’s

complement in nature. Depending on the operation, the

ALU may affect the values of the Carry (C), Zero (Z),

Negative (N), Overflow (OV) and Digit Carry (DC)

Status bits in the SR register. The C and DC Status bits

operate as Borrow and Digit Borrow bits, respectively,

for subtraction operations.

1. 32-bit signed/16-bit signed divide

2. 32-bit unsigned/16-bit unsigned divide

3. 16-bit signed/16-bit signed divide

4. 16-bit unsigned/16-bit unsigned divide

The quotient for all divide instructions ends up in W0

and the remainder in W1. 16-bit signed and unsigned

DIVinstructions can specify any W register for both the

16-bit divisor (Wn) and any W register (aligned) pair

(W(m+1):Wm) for the 32-bit dividend. The divide algo-

rithm takes one cycle per bit of divisor, so both

32-bit/16-bit and 16-bit/16-bit instructions take the

same number of cycles to execute.

The ALU can perform 8-bit or 16-bit operations,

depending on the mode of the instruction that is used.

Data for the ALU operation can come from the W

register array, or data memory, depending on the

addressing mode of the instruction. Likewise, output

data from the ALU can be written to the W register array

or a data memory location.

The PIC24F CPU incorporates hardware support for

both multiplication and division. This includes a dedi-

cated hardware multiplier and support hardware for

16-bit divisor division.

3.3.3

MULTI-BIT SHIFT SUPPORT

The PIC24F ALU supports both single bit and

single-cycle, multi-bit arithmetic and logic shifts.

Multi-bit shifts are implemented using a shifter block,

capable of performing up to a 15-bit arithmetic right

shift, or up to a 15-bit left shift, in a single cycle. All

multi-bit shift instructions only support Register Direct

Addressing for both the operand source and result

destination.

3.3.1

MULTIPLIER

The ALU contains a high-speed, 17-bit x 17-bit

multiplier. It supports unsigned, signed or mixed sign

operation in several multiplication modes:

1. 16-bit x 16-bit signed

A full summary of instructions that use the shift

operation is provided below in Table 3-2.

2. 16-bit x 16-bit unsigned

3. 16-bit signed x 5-bit (literal) unsigned

4. 16-bit unsigned x 16-bit unsigned

5. 16-bit unsigned x 5-bit (literal) unsigned

6. 16-bit unsigned x 16-bit signed

7. 8-bit unsigned x 8-bit unsigned

TABLE 3-2:

Instruction

INSTRUCTIONS THAT USE THE SINGLE AND MULTI-BIT SHIFT OPERATION

Description

ASR

SL

Arithmetic shift right source register by one or more bits.

Shift left source register by one or more bits.

LSR

Logical shift right source register by one or more bits.

DS39747F-page 30

 2005-2012 Microchip Technology Inc.

PIC24FJ128GA010 FAMILY

either the 23-bit Program Counter (PC) during program

execution, or from table operation or data space

remapping, as described in Section 4.3 “Interfacing

Program and Data Memory Spaces”.

4.0

MEMORY ORGANIZATION

As Harvard architecture devices, PIC24F micro-

controllers feature separate program and data memory

spaces and busses. This architecture also allows the

direct access of program memory from the data space

during code execution.

User access to the program memory space is restricted

to the lower half of the address range (000000h to

7FFFFFh). The exception is the use of TBLRD/TBLWT

operations, which use TBLPAG<7> to permit access to

the Configuration bits and Device ID sections of the

configuration memory space.

4.1

Program Address Space

The

program

address

memory

space

of

PIC24FJ128GA010 family devices is 4M instructions.

The space is addressable by a 24-bit value derived from

Memory maps for the PIC24FJ128GA010 family of

devices are shown in Figure 4-1.

FIGURE 4-1:

PROGRAM SPACE MEMORY MAP FOR PIC24FJ128GA010 FAMILY DEVICES

PIC24FJ64GA

PIC24FJ96GA

PIC24FJ128GA

000000h

000002h

000004h

GOTOInstruction

Reset Address

GOTOInstruction

Reset Address

GOTOInstruction

Reset Address

Interrupt Vector Table

Reserved

Interrupt Vector Table

Reserved

Interrupt Vector Table

Reserved

0000FEh

000100h

000104h

0001FEh

000200h

Alternate Vector Table

User Flash

Program Memory

(22K instructions)

User Flash

Program Memory

(32K instructions)

User Flash

Program Memory

(44K instructions)

Flash Config Words

00ABFEh

00AC00h

00FFFEh

010000h

Flash Config Words

0157FEh

015800h

Unimplemented

(Read ‘0’s)

Unimplemented

(Read ‘0’s)

7FFFFEh

800000h

Reserved

F7FFFEh

F80000h

Device Configuration

Registers

Device Configuration

Registers

Device Configuration

Registers

F8000Eh

F80010h

Reserved

DEVID (2)

FEFFFEh

FF0000h

FFFFFEh

DEVID (2)

Note:

Memory areas are not shown to scale.

 2005-2012 Microchip Technology Inc.

DS39747F-page 31

PIC24FJ128GA010 FAMILY

4.1.1

PROGRAM MEMORY

ORGANIZATION

4.1.3

FLASH CONFIGURATION WORDS

In PIC24FJ128GA010 family devices, the top two words

of on-chip program memory are reserved for configura-

tion information. On device Reset, the configuration

information is copied into the appropriate Configuration

registers. The addresses of the Flash Configuration

Word for devices in the PIC24FJ128GA010 family are

shown in Table 4-1. Their location in the memory map is

shown with the other memory vectors in Figure 4-1.

The program memory space is organized in

word-addressable blocks. Although it is treated as

24 bits wide, it is more appropriate to think of each

address of the program memory as a lower and upper

word, with the upper byte of the upper word being

unimplemented. The lower word always has an even

address, while the upper word has an odd address

(Figure 4-2).

The Configuration Words in program memory are a

compact format. The actual Configuration bits are

mapped in several different registers in the configuration

memory space. Their order in the Flash Configuration

Words do not reflect a corresponding arrangement in the

configuration space. Additional details on the device

Configuration Words are provided in Section 24.1

“Configuration Bits”.

Program memory addresses are always word-aligned

on the lower word, and addresses are incremented or

decremented by two during code execution. This

arrangement also provides compatibility with data

memory space addressing and makes it possible to

access data in the program memory space.

4.1.2

HARD MEMORY VECTORS

TABLE 4-1:

FLASH CONFIGURATION

WORDS FOR

PIC24FJ128GA010 FAMILY

DEVICES

All PIC24F devices reserve the addresses between

00000h and 000200h for hard coded program execu-

tion vectors. A hardware Reset vector is provided to

redirect code execution from the default value of the

PC on device Reset to the actual start of code. A GOTO

instruction is programmed by the user at 000000h, with

the actual address for the start of code at 000002h.

Program

Memory

(Words)

Configuration

Word

Addresses

Device

PIC24F devices also have two Interrupt Vector Tables

(IVT), located from 000004h to 0000FFh, and 000100h

to 0001FFh. These vector tables allow each of the

many device interrupt sources to be handled by sepa-

rate ISRs. A more detailed discussion of the Interrupt

Vector Tables is provided in Section 7.1 “Interrupt

Vector Table”.

PIC24FJ64GA

PIC24FJ96GA

PIC24FJ128GA

22,016

32,768

44,032

00ABFCh:

00ABFEh

00FFFCh:

00FFFEh

0157FCh:

0157FEh

FIGURE 4-2:

PROGRAM MEMORY ORGANIZATION

least significant word

8

msw

Address

PC Address

(lsw Address)

most significant word

23

16

0

000000h

000002h

000004h

000006h

00000000

000001h

000003h

000005h

000007h

00000000

Program Memory

‘Phantom’ Byte’

(read as ‘0’)

Instruction Width

DS39747F-page 32

 2005-2012 Microchip Technology Inc.

PIC24FJ128GA010 FAMILY

memory space (that is, when EA<15> = 0) is used for

implemented memory addresses, while the upper half

4.2

Data Address Space

Note:

This data sheet summarizes the features of

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. Refer to Section 3. “Data Mem-

ory” (DS39717) in the “PIC24F Family

Reference Manual” for more information.

(EA<15> = 1) is reserved for the Program Space Visi-

bility area (see Section 4.3.3 “Reading Data from

Program Memory Using Program Space Visibility”).

PIC24FJ128GA010 family devices implement a total of

8 Kbytes of data memory. Should an EA point to a

location outside of this area, an all zero word or byte will

be returned.

The PIC24F core has a separate, 16-bit wide data mem-

ory space, addressable as a single linear range. The

data space is accessed using two Address Generation

Units (AGUs), one each for read and write operations.

The data space memory map is shown in Figure 4-3.

4.2.1

DATA SPACE WIDTH

The data memory space is organized in

byte-addressable, 16-bit wide blocks. Data is aligned in

data memory and registers as 16-bit words, but all data

space EAs resolve to bytes. The Least Significant Bytes

(LSBs) of each word have even addresses, while the

Most Significant Bytes (MSBs) have odd addresses.

All Effective Addresses (EAs) in the data memory

space are 16 bits wide and point to bytes within the

data space. This gives a data space address range of

64 Kbytes or 32K words. The lower half of the data

FIGURE 4-3:

DATA SPACE MEMORY MAP FOR PIC24FJ128GA010 FAMILY DEVICES

MSB

Address

LSB

Address

MSB

LSB

0000h

0001h

SFR

Space

SFR Space

Data RAM

07FFh

0801h

07FEh

0800h

Near

Data Space

Implemented

Data RAM

1FFFh

2001h

27FFh

2801h

1FFEh

2000h

27FEh

2800h

Unimplemented

Read as ‘0’

7FFFh

8001h

7FFFh

8000h

Program Space

Visibility Area

FFFFh

FFFEh

Note:

Data memory areas are not shown to scale.

 2005-2012 Microchip Technology Inc.

DS39747F-page 33

PIC24FJ128GA010 FAMILY

A Sign-Extend (SE) instruction is provided to allow

users to translate 8-bit signed data to 16-bit signed

values. Alternatively, for 16-bit unsigned data, users

can clear the MSB of any W register by executing a

Zero-Extend (ZE) instruction on the appropriate

address.

4.2.2

DATA MEMORY ORGANIZATION

AND ALIGNMENT

To maintain backward compatibility with PIC^®devices

and improve data space memory usage efficiency, the

PIC24F instruction set supports both word and byte

operations. As a consequence of byte accessibility, all

Effective Address calculations are internally scaled to

step through word-aligned memory. For example, the

core recognizes that Post-Modified Register Indirect

Addressing mode [Ws++] will result in a value of

Ws + 1 for byte operations and Ws + 2 for word

operations.

Although most instructions are capable of operating on

word or byte data sizes, it should be noted that some

instructions operate only on words.

4.2.3

NEAR DATA SPACE

The 8-Kbyte area, between 0000h and 1FFFh, is

referred to as the Near Data Space (NDS). Locations in

this space are directly addressable via a 13-bit abso-

lute address field within all memory direct instructions.

The remainder of the data space is indirectly address-

able. Additionally, the whole data space is addressable

using MOV instructions, which support Memory Direct

Addressing with a 16-bit address field.

Data byte reads will read the complete word which con-

tains the byte, using the LSb of any EA to determine

which byte to select. The selected byte is placed onto

the LSB of the data path. That is, data memory and reg-

isters are organized as two parallel, byte-wide entities

with shared (word) address decode, but separate write

lines. Data byte writes only write to the corresponding

side of the array or register which matches the byte

address.

4.2.4

SFR SPACE

The first 2 Kbytes of the Near Data Space, from 0000h

to 07FFh, are primarily occupied with Special Function

Registers (SFRs). These are used by the PIC24F core

and peripheral modules for controlling the operation of

the device.

All word accesses must be aligned to an even address.

Misaligned word data fetches are not supported, so

care must be taken when mixing byte and word opera-

tions, or translating from 8-bit MCU code. If a

misaligned read or write is attempted, an address error

trap will be generated. If the error occurred on a read,

the instruction underway is completed; if it occurred on

a write, the instruction will be executed but the write will

not occur. In either case, a trap is then executed, allow-

ing the system and/or user to examine the machine

state prior to execution of the address Fault.

SFRs are distributed among the modules that they con-

trol, and are generally grouped together by module.

Much of the SFR space contains unused addresses;

these are read as ‘0’. A diagram of the SFR space,

showing where SFRs are actually implemented, is

shown in Table 4-2. Each implemented area indicates

a 32-byte region where at least one address is imple-

mented as an SFR. A complete listing of implemented

SFRs, including their addresses, is shown in Tables 4-3

through 4-30.

All byte loads into any W register are loaded into the

Least Significant Byte. The Most Significant Byte is not

modified.

TABLE 4-2:

IMPLEMENTED REGIONS OF SFR DATA SPACE

SFR Space Address

xx00

xx20

xx40

xx60

xx80

xxA0

xxC0

xxE0

000h

100h

200h

300h

400h

500h

600h

700h

Core

ICN

—

Interrupts

—

Timers

A/D

Capture

Compare

—

I²C™

UART

SPI

—

I/O

—

PMP

—

RTC/Comp

—

CRC

System

NVM/PMD

—

Legend: — = No implemented SFRs in this block

DS39747F-page 34

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4.2.5

SOFTWARE STACK

4.3

Interfacing Program and Data

Memory Spaces

In addition to its use as a working register, the W15 reg-

ister in PIC24F devices is also used as a Software

Stack Pointer. The pointer always points to the first

available free word and grows from lower to higher

addresses. It predecrements for stack pops and post-

increments for stack pushes, as shown in Figure 4-4.

Note that for a PC push during any CALL instruction,

the MSB of the PC is zero-extended before the push,

ensuring that the MSB is always clear.

The PIC24F architecture uses a 24-bit wide program

space and 16-bit wide data space. The architecture is

also a modified Harvard scheme, meaning that data

can also be present in the program space. To use this

data successfully, it must be accessed in a way that

preserves the alignment of information in both spaces.

Aside from normal execution, the PIC24F architecture

provides two methods by which program space can be

accessed during operation:

Note:

A PC push during exception processing

will concatenate the SRL register to the

MSB of the PC prior to the push.

• Using table instructions to access individual bytes

or words anywhere in the program space

The Stack Pointer Limit register (SPLIM) associated

with the Stack Pointer sets an upper address boundary

for the stack. SPLIM is uninitialized at Reset. As is the

case for the Stack Pointer, SPLIM<0> is forced to ‘0’

because all stack operations must be word-aligned.

Whenever an EA is generated using W15 as a source

or destination pointer, the resulting address is com-

pared with the value in SPLIM. If the contents of the

Stack Pointer (W15) and the SPLIM register are equal

and a push operation is performed, a stack error trap

will not occur. The stack error trap will occur on a

subsequent push operation. Thus, for example, if it is

desirable to cause a stack error trap when the stack

grows beyond address, 2000h, in RAM, initialize the

SPLIM with the value, 1FFEh.

• Remapping a portion of the program space into

the data space (Program Space Visibility)

Table instructions allow an application to read or write

to small areas of the program memory. This makes the

method ideal for accessing data tables that need to be

updated from time to time. It also allows access to all

bytes of the program word. The remapping method

allows an application to access a large block of data on

a read-only basis, which is ideal for look ups from a

large table of static data. It can only access the least

significant word of the program word.

4.3.1

ADDRESSING PROGRAM SPACE

Since the address ranges for the data and program

spaces are 16 and 24 bits, respectively, a method is

needed to create a 23-bit or 24-bit program address

from 16-bit data registers. The solution depends on the

interface method to be used.

Similarly, a Stack Pointer underflow (stack error) trap is

generated when the Stack Pointer address is found to

be less than 0800h. This prevents the stack from

interfering with the Special Function Register (SFR)

space.

For table operations, the 8-bit Table Page register

(TBLPAG) is used to define a 32K word region within

the program space. This is concatenated with a 16-bit

EA to arrive at a full 24-bit program space address. In

this format, the Most Significant bit of TBLPAG is used

to determine if the operation occurs in the user memory

(TBLPAG<7> = 0) or the configuration memory

(TBLPAG<7> = 1).

A write to the SPLIM register should not be immediately

followed by an indirect read operation using W15.

FIGURE 4-4:

CALL STACK FRAME

0000h

15

0

For remapping operations, the 8-bit Program Space

Visibility register (PSVPAG) is used to define a

16K word page in the program space. When the Most

Significant bit of the EA is ‘1’, PSVPAG is concatenated

with the lower 15 bits of the EA to form a 23-bit program

space address. Unlike table operations, this limits

remapping operations strictly to the user memory area.

PC<15:0>

000000000

W15 (before CALL)

PC<22:16>

W15 (after CALL)

Table 4-31 and Figure 4-5 show how the program EA is

created for table operations and remapping accesses

from the data EA. Here, P<23:0> refers to a program

space word, whereas D<15:0> refers to a data space

word.

POP : [--W15]

PUSH: [W15++]

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TABLE 4-31: PROGRAM SPACE ADDRESS CONSTRUCTION

Program Space Address

Access

Space

Access Type

<23>

<22:16>

<15>

PC<22:1>

<14:1>

<0>

Instruction Access

(Code Execution)

User

0

0xx xxxx xxxx xxxx xxxx xxx0

TBLRD/TBLWT

(Byte/Word Read/Write)

TBLPAG<7:0>

0xxx xxxx

Data EA<15:0>

xxxx xxxx xxxx xxxx

Data EA<15:0>

Configuration

TBLPAG<7:0>

1xxx xxxx

xxxx xxxx xxxx xxxx

Data EA<14:0>⁽¹⁾

Program Space Visibility User

(Block Remap/Read)

0

PSVPAG<7:0>

xxxx xxxx

xxx xxxx xxxx xxxx

Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of

the address is PSVPAG<0>.

FIGURE 4-5:

DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION

Program Counter⁽¹⁾

Program Counter

23 Bits

0

1/0

EA

Table Operations⁽²⁾

1/0

TBLPAG

8 Bits

16 Bits

24 Bits

Select

1

0

EA

Program Space Visibility⁽¹⁾

(Remapping)

0

PSVPAG

8 Bits

15 Bits

23 Bits

Byte Select

User/Configuration

Space Select

Note 1: The LSb of program space addresses is always fixed as ‘0’ in order to maintain word alignment of

data in the program and data spaces.

2: Table operations are not required to be word-aligned. Table read operations are permitted in the

configuration memory space.

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2. TBLRDH (Table Read High): In Word mode, it

4.3.2

DATA ACCESS FROM PROGRAM

MEMORY USING TABLE

INSTRUCTIONS

maps the entire upper word of a program address

(P<23:16>) to

a data address. Note that

D<15:8>, the “phantom byte”, will always be ‘0’.

The TBLRDL and TBLWTL instructions offer a direct

method of reading or writing the lower word of any

address within the program space, without going

through data space. The TBLRDHand TBLWTHinstruc-

tions are the only method to read or write the upper 8 bits

of a program space word as data.

In Byte mode, it maps the upper or lower byte of

the program word to D<7:0> of the data

address, as above. Note that the data will

always be ‘0’ when the upper “phantom” byte is

selected (byte select = 1).

In a similar fashion, two table instructions, TBLWTH

and TBLWTL, are used to write individual bytes or

words to a program space address. The details of

their operation are explained in Section 5.0 “Flash

Program Memory”.

The PC is incremented by two for each successive

24-bit program word. This allows program memory

addresses to directly map to data space addresses.

Program memory can thus be regarded as two 16-bit,

word-wide address spaces, residing side by side, each

with the same address range. TBLRDL and TBLWTL

access the space which contains the least significant

data word, and TBLRDHand TBLWTHaccess the space

which contains the upper data byte.

For all table operations, the area of program memory

space to be accessed is determined by the Table Page

register (TBLPAG). TBLPAG covers the entire program

memory space of the device, including user and config-

uration spaces. When TBLPAG<7> = 0, the Table Page

is located in the user memory space. When

TBLPAG<7> = 1, the page is located in configuration

space.

Two table instructions are provided to move byte or

word-sized (16-bit) data to and from program space.

Both function as either byte or word operations.

1. TBLRDL (Table Read Low): In Word mode, it

maps the lower word of the program space

location (P<15:0>) to a data address (D<15:0>).

Note:

Only table read operations will execute in

the configuration memory space, and only

then, in implemented areas such as the

Device ID. Table write operations are not

allowed.

In Byte mode, either the upper or lower byte of

the lower program word is mapped to the lower

byte of a data address. The upper byte is

selected when byte select is ‘1’; the lower byte

is selected when it is ‘0’.

FIGURE 4-6:

ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS

Program Space

TBLPAG

02

Data EA<15:0>

23

15

0

000000h

23

16

8

0

00000000

020000h

030000h

‘Phantom’ Byte

TBLRDH.B(Wn<0> = 0)

TBLRDL.B(Wn<0> = 1)

TBLRDL.B(Wn<0> = 0)

TBLRDL.W

The address for the table operation is determined by the data EA

within the page defined by the TBLPAG register.

Only read operations are shown; write operations are also valid in

the user memory area.

800000h

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24-bit program word are used to contain the data. The

upper 8 bits of any program space locations used as

data should be programmed with ‘1111 1111’ or

‘0000 0000’ to force a NOP. This prevents possible

issues should the area of code ever be accidentally

executed.

4.3.3

READING DATA FROM PROGRAM

MEMORY USING PROGRAM SPACE

VISIBILITY

The upper 32 Kbytes of data space may optionally be

mapped into any 16K word page of the program space.

This provides transparent access of stored constant

data from the data space without the need to use

special instructions (i.e., TBLRDL/H).

Note:

PSV access is temporarily disabled during

table reads/writes.

Program space access through the data space occurs

if the Most Significant bit of the data space EA is ‘1’ and

Program Space Visibility is enabled by setting the PSV

bit in the Core Control register (CORCON<2>). The

location of the program memory space to be mapped

into the data space is determined by the Program

Space Visibility Page register (PSVPAG). This 8-bit

register defines any one of 256 possible pages of

16K words in program space. In effect, PSVPAG func-

tions as the upper 8 bits of the program memory

address, with the 15 bits of the EA functioning as the

lower bits. Note that by incrementing the PC by 2 for

each program memory word, the lower 15 bits of data

space addresses directly map to the lower 15 bits in the

corresponding program space addresses.

For operations that use PSV and are executed outside

a REPEAT loop, the MOV and MOV.D instructions will

require one instruction cycle in addition to the specified

execution time. All other instructions will require two

instruction cycles in addition to the specified execution

time.

For operations that use PSV which are executed inside

a REPEAT loop, there will be some instances that

require two instruction cycles in addition to the

specified execution time of the instruction:

• Execution in the first iteration

• Execution in the last iteration

• Execution prior to exiting the loop due to an

interrupt

Data reads to this area add an additional cycle to the

instruction being executed, since two program memory

fetches are required.

• Execution upon re-entering the loop after an

interrupt is serviced

Any other iteration of the REPEAT loop will allow the

instruction accessing data, using PSV, to execute in a

single cycle.

Although each data space address, 8000h and higher,

maps directly into a corresponding program memory

address (see Figure 4-7), only the lower 16 bits of the

FIGURE 4-7:

PROGRAM SPACE VISIBILITY OPERATION

When CORCON<2> = 1and EA<15> = 1:

Program Space

Data Space

PSVPAG

02

23

15

0

000000h

0000h

Data EA<14:0>

010000h

018000h

The data in the page

designated by PSV-

PAG is mapped into

the upper half of the

data memory

8000h

space....

PSV Area

...while the lower 15

bits of the EA specify

an exact address

within the PSV area.

This corresponds

exactly to the same

lower 15 bits of the

actual program space

address.

FFFFh

800000h

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NOTES:

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controller just before shipping the product. This also

allows the most recent firmware or a custom firmware

to be programmed.

5.0

FLASH PROGRAM MEMORY

Note:

This data sheet summarizes the features of

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. Refer to Section 4. “Program

Memory” (DS39715) in the “PIC24F

Family Reference Manual” for more

information.

RTSP is accomplished using TBLRD (table read) and

TBLWT (table write) instructions. With RTSP, the user

may write program memory data in blocks of 64 instruc-

tions (192 bytes) at a time, and erase program memory

in blocks of 512 instructions (1536 bytes) at a time.

5.1

Table Instructions and Flash

Programming

The PIC24FJ128GA010 family of devices contains

internal Flash program memory for storing and execut-

ing application code. The memory is readable, writable

and erasable during normal operation over the

specified VDD range.

Regardless of the method used, all programming of

Flash memory is done with the table read and table

write instructions. These allow direct read and write

access to the program memory space from the data

memory while the device is in normal operating mode.

The 24-bit target address in the program memory is

formed using the TBLPAG<7:0> bits and the Effective

Address (EA) from a W register specified in the table

instruction, as shown in Figure 5-1.

Flash memory can be programmed in four ways:

1. In-Circuit Serial Programming™ (ICSP™)

2. Run-Time Self-Programming (RTSP)

3. JTAG

4. Enhanced In-Circuit Serial Programming

(Enhanced ICSP)

The TBLRDLand the TBLWTLinstructions are used to

read or write to bits<15:0> of program memory.

TBLRDLand TBLWTLcan access program memory in

both Word and Byte modes.

ICSP allows a PIC24FJ128GA010 family device to be

serially programmed while in the end application circuit.

This is simply done with two lines for Programming

Clock and Programming Data (which are named PGCx

and PGDx, respectively), and three other lines for

power (VDD), ground (VSS) and Master Clear (MCLR).

This allows customers to manufacture boards with

unprogrammed devices and then program the micro-

The TBLRDHand TBLWTHinstructions are used to read

or write to bits<23:16> of program memory. TBLRDH

and TBLWTHcan also access program memory in Word

or Byte mode.

FIGURE 5-1:

ADDRESSING FOR TABLE REGISTERS

24 Bits

Program Counter

Using

Program

Counter

0

Working Reg EA

Using

Table

Instruction

TBLPAG Reg

8 Bits

1/0

16 Bits

User/Configuration

Space Select

Byte

Select

24-Bit EA

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5.2

RTSP Operation

5.4

Enhanced In-Circuit Serial

Programming

The PIC24F Flash program memory array is organized

into rows of 64 instructions or 192 bytes. RTSP allows

the user to erase blocks of eight rows (512 instructions)

at a time and to program one row at a time. It is also

possible to program single words.

Enhanced In-Circuit Serial Programming uses an on-

board bootloader, known as the program executive, to

manage the programming process. Using an SPI data

frame format, the program executive can erase,

program and verify program memory. See the device

programming specification for more information on

Enhanced ICSP

The 8-row erase blocks and single row write blocks are

edge-aligned, from the beginning of program memory,

on boundaries of 1536 bytes and 192 bytes,

respectively.

5.5

Control Registers

When data is written to program memory using TBLWT

instructions, the data is not written directly to memory.

Instead, data written using table writes is stored in

holding latches until the programming sequence is

executed.

There are two SFRs used to read and write the

program Flash memory: NVMCON and NVMKEY.

The NVMCON register (Register 5-1) controls which

blocks are to be erased, which memory type is to be

programmed and the start of the programming cycle.

Any number of TBLWT instructions can be executed

and a write will be successfully performed. However,

64 TBLWTinstructions are required to write the full row

of memory.

NVMKEY is a write-only register that is used for write

protection. To start a programming or erase sequence,

the user must consecutively write 55h and AAh to the

NVMKEY register. Refer to Section 5.6 “Programming

Operations” for further details.

To ensure that no data is corrupted during a write, any

unused addresses should be programmed with

FFFFFFh. This is because the holding latches reset to

an unknown state, so if the addresses are left in the

Reset state, they may overwrite the locations on rows

which were not rewritten.

5.6

Programming Operations

A complete programming sequence is necessary for

programming or erasing the internal Flash in RTSP

mode. During a programming or an erase operation,

the processor stalls (Waits) until the operation is

finished. Setting the WR bit (NVMCON<15>) starts the

operation and the WR bit is automatically cleared when

the operation is finished.

The basic sequence for RTSP programming is to set up

a Table Pointer, then do a series of TBLWTinstructions

to load the buffers. Programming is performed by

setting the control bits in the NVMCON register.

Data can be loaded in any order and the holding regis-

ters can be written to multiple times before performing

a write operation. Subsequent writes, however, will

wipe out any previous writes.

Configuration Word values are stored in the last two

locations of program memory. Performing a page erase

operation on the last page of program memory clears

these values and enables code protection. As a result,

avoid performing page erase operations on the last

page of program memory.

Note:

Writing to a location multiple times without

erasing is not recommended.

All of the table write operations are single-word writes

(2 instruction cycles), because only the buffers are

written.

A

programming cycle is required for

programming each row.

5.3

JTAG Operation

The PIC24F family supports JTAG programming and

boundary scan. Boundary scan can improve the manu-

facturing process by verifying pin to PCB connectivity.

Programming can be performed with industry standard

JTAG programmers supporting Serial Vector Format

(SVF).

DS39747F-page 52

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REGISTER 5-1:

NVMCON: FLASH MEMORY CONTROL REGISTER

R/SO-0⁽¹⁾

WR

R/W-0⁽¹⁾

WREN

R/W-0⁽¹⁾

WRERR

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

R/W-0⁽¹⁾

ERASE

U-0

—

U-0

—

R/W-0⁽¹⁾

NVMOP3⁽²⁾NVMOP2⁽²⁾

R/W-0⁽¹⁾

NVMOP1⁽²⁾NVMOP0⁽²⁾

R/W-0⁽¹⁾

bit 7

bit 0

Legend:

SO = Settable Only bit

W = Writable bit

‘1’ = Bit is set

R = Readable bit

-n = Value at POR

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

WR: Write Control bit

1= Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is

cleared by hardware once operation is complete.

0= Program or erase operation is complete and inactive

bit 14

bit 13

WREN: Write Enable bit

1= Enables Flash program/erase operations

0= Inhibits Flash program/erase operations

WRERR: Write Sequence Error Flag bit

1= An improper program or erase sequence attempt or termination has occurred (bit is set automatically

on any set attempt of the WR bit)

0= The program or erase operation completed normally

bit 12-7

bit 6

Unimplemented: Read as ‘0’

ERASE: Erase/Program Enable bit

1= Performs the erase operation specified by NVMOP<3:0> on the next WR command

0= Performs the program operation specified by NVMOP<3:0> on the next WR command

bit 5-4

bit 3-0

Unimplemented: Read as ‘0’

NVMOP<3:0>: NVM Operation Select bits⁽²⁾

1111= Memory bulk erase operation (ERASE = 1) or no operation (ERASE = 0)⁽³⁾

0011= Memory word program operation (ERASE = 0) or no operation (ERASE = 1)

0010= Memory page erase operation (ERASE = 1) or no operation (ERASE = 0)

0001= Memory row program operation (ERASE = 0) or no operation (ERASE = 1)

Note 1: These bits can only be reset on a POR.

2: All other combinations of NVMOP<3:0> are unimplemented.

3: Available in ICSP™ mode only. Refer to the device programming specifications.

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4. Write the first 64 instructions from data RAM into

the program memory buffers (see Example 5-2).

5.6.1

PROGRAMMING ALGORITHM FOR

FLASH PROGRAM MEMORY

5. Write the program block to Flash memory:

The user can program one row of program Flash memory

at a time. To do this, it is necessary to erase the 8-row

erase block containing the desired row. The general

process is:

a) Set the NVMOP bits to ‘0001’ to configure

for row programming. Clear the ERASE bit

and set the WREN bit.

b) Write 55h to NVMKEY.

c) Write AAh to NVMKEY.

1. Read eight rows of program memory

(512 instructions) and store in data RAM.

d) Set the WR bit. The programming cycle

begins and the CPU stalls for the duration of

the write cycle. When the write to Flash

memory is done, the WR bit is cleared

automatically.

2. Update the program data in RAM with the

desired new data.

3. Erase the block (see Example 5-1):

a) Set the NVMOP bits (NVMCON<3:0>) to

‘0010’ to configure for block erase. Set the

ERASE (NVMCON<6>) and WREN

(NVMCON<14>) bits.

6. Repeat Steps 4 and 5, using the next available

64 instructions from the block in data RAM by

incrementing the value in TBLPAG, until all

512 instructions are written back to Flash

memory.

b) Write the starting address of the block to be

erased into the TBLPAG and W registers.

c) Write 55h to NVMKEY.

d) Write AAh to NVMKEY.

For protection against accidental operations, the write

initiate sequence for NVMKEY must be used to allow

any erase or program operation to proceed. After the

programming command has been executed, the user

must wait for the programming time until programming

is complete. The two instructions following the start of

the programming sequence should be NOPs, as shown

in Example 5-3.

e) Set the WR bit (NVMCON<15>). The erase

cycle begins and the CPU stalls for the dura-

tion of the erase cycle. When the erase is

done, the WR bit is cleared automatically.

EXAMPLE 5-1:

ERASING A PROGRAM MEMORY BLOCK

; Set up NVMCON for block erase operation

MOV

#0x4042, W0

W0, NVMCON

;

; Initialize NVMCON

; Init pointer to row to be ERASED

MOV

#tblpage(PROG_ADDR), W0

W0, TBLPAG

#tbloffset(PROG_ADDR), W0

;

; Initialize PM Page Boundary SFR

; Initialize in-page EA[15:0] pointer

; Set base address of erase block

; Block all interrupts with priority <7

; for next 5 instructions

TBLWTL W0, [W0]

DISI

#5

MOV

BSET

NOP

#0x55, W0

W0, NVMKEY

#0xAA, W1

W1, NVMKEY

NVMCON, #WR

; Write the 55 key

;

; Write the AA key

; Start the erase sequence

; Insert two NOPs after the erase

; command is asserted

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EXAMPLE 5-2:

LOADING THE WRITE BUFFERS

; Set up NVMCON for row programming operations

MOV

#0x4001, W0

W0, NVMCON

;

; Initialize NVMCON

; Set up a pointer to the first program memory location to be written

; program memory selected, and writes enabled

MOV

#0x0000, W0

W0, TBLPAG

#0x6000, W0

;

; Initialize PM Page Boundary SFR

; An example program memory address

; Perform the TBLWT instructions to write the latches

; 0th_program_word

MOV

#LOW_WORD_0, W2

#HIGH_BYTE_0, W3

;

TBLWTL W2, [W0]

TBLWTH W3, [W0++]

; Write PM low word into program latch

; Write PM high byte into program latch

; 1st_program_word

MOV

#LOW_WORD_1, W2

#HIGH_BYTE_1, W3

;

TBLWTL W2, [W0]

TBLWTH W3, [W0++]

; Write PM low word into program latch

; Write PM high byte into program latch

;

2nd_program_word

MOV

#LOW_WORD_2, W2

#HIGH_BYTE_2, W3

;

TBLWTL W2, [W0]

TBLWTH W3, [W0++]

; Write PM low word into program latch

; Write PM high byte into program latch

•

; 63rd_program_word

MOV

#LOW_WORD_31, W2

#HIGH_BYTE_31, W3

;

TBLWTL W2, [W0]

TBLWTH W3, [W0]

; Write PM low word into program latch

; Write PM high byte into program latch

EXAMPLE 5-3:

INITIATING A PROGRAMMING SEQUENCE

DISI

#5

; Block all interrupts with priority <7

; for next 5 instructions

MOV

BSET

BTSC

BRA

#0x55, W0

W0, NVMKEY

#0xAA, W1

W1, NVMKEY

NVMCON, #WR

NVMCON, #15

$-2

; Write the 55 key

;

; Write the AA key

; Start the program/erase sequence

; and wait for it to be

; completed

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PIC24FJ128GA010 FAMILY

instructions write the desired data into the write latches

and specify the lower 16 bits of the program memory

address to write to. To configure the NVMCON register

for a word write, set the NVMOP bits (NVMCON<3:0>)

to ‘0011’. The write is performed by executing the

unlock sequence and setting the WR bit.

5.6.2

PROGRAMMING A SINGLE WORD

OF FLASH PROGRAM MEMORY

If a Flash location has been erased, it can be pro-

grammed using table write instructions to write an

instruction word (24-bit) into the write latch. The

TBLPAG register is loaded with the 8 Most Significant

Bytes of the Flash address. The TBLWTLand TBLWTH

EXAMPLE 5-4:

PROGRAMMING A SINGLE WORD OF FLASH PROGRAM MEMORY

; Setup a pointer to data Program Memory

MOV

#tblpage(PROG_ADDR), W0

W0, TBLPAG

#tbloffset(PROG_ADDR), W0

;

;Initialize PM Page Boundary SFR

;Initialize a register with program memory address

MOV

#LOW_WORD_N, W2

#HIGH_BYTE_N, W3

;

TBLWTL W2, [W0]

TBLWTH W3, [W0++]

; Write PM low word into program latch

; Write PM high byte into program latch

; Setup NVMCON for programming one word to data Program Memory

MOV

#0x4003, W0

W0, NVMCON

;

; Set NVMOP bits to 0011

DISI

#5

; Disable interrupts while the KEY sequence is

written

MOV

BSET

#0x55, W0

W0, NVMKEY

#0xAA, W0

W0, NVMKEY

NVMCON, #WR

; Write the key sequence

; Start the write cycle

DS39747F-page 56

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PIC24FJ128GA010 FAMILY

6.0

RESETS

Note:

Refer to the specific peripheral or CPU

section of this manual for register Reset

states.

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

intended to be a comprehensive refer-

ence source. Refer to Section 7. “Reset”

(DS39712) in the “PIC24F Family

Reference Manual” for more information.

All types of device Reset will set a corresponding status

bit in the RCON register to indicate the type of Reset

(see Register 6-1). A POR will clear all bits except for

the BOR and POR bits (RCON<1:0>), which are set.

The user may set or clear any bit at any time during

code execution. The RCON bits only serve as status

bits. Setting a particular Reset status bit in software will

not cause a device Reset to occur.

The Reset module combines all Reset sources and

controls the device Master Reset Signal, SYSRST. The

following is a list of device Reset sources:

• POR: Power-on Reset

The RCON register also has other bits associated with

the Watchdog Timer and device power-saving states.

The function of these bits is discussed in other sections

of this manual.

• MCLR: Pin Reset

• SWR: RESETInstruction

• WDT: Watchdog Timer Reset

• BOR: Brown-out Reset

Note:

The status bits in the RCON register

should be cleared after they are read so

that the next RCON register value after a

device Reset will be meaningful.

• CM: Configuration Word Mismatch Reset

• TRAPR: Trap Conflict Reset

• IOPUWR: Illegal Opcode Reset

• UWR: Uninitialized W Register Reset

A simplified block diagram of the Reset module is

shown in Figure 6-1.

Any active source of Reset will make the SYSRST sig-

nal active. Many registers associated with the CPU and

peripherals are forced to a known Reset state. Most

registers are unaffected by a Reset; their status is

unknown on POR and unchanged by all other Resets.

FIGURE 6-1:

RESET SYSTEM BLOCK DIAGRAM

RESET

Instruction

Glitch Filter

MCLR

WDT

Module

Sleep or Idle

POR

VDD Rise

Detect

SYSRST

VDD

Brown-out

Reset

BOR

Enable Voltage Regulator

Trap Conflict

Illegal Opcode

Uninitialized W Register

Configuration Word Mismatch Reset

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PIC24FJ128GA010 FAMILY

REGISTER 6-1:

RCON: RESET CONTROL REGISTER⁽¹⁾

R/W-0

TRAPR

bit 15

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

CM

R/W-0

IOPUWR

VREGS

bit 8

R/W-0

EXTR

R/W-0

SWR

R/W-0

SWDTEN⁽²⁾

R/W-0

WDTO

R/W-0

IDLE

R/W-1

BOR

R/W-1

POR

SLEEP

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

bit 14

TRAPR: Trap Reset Flag bit

1= A Trap Conflict Reset has occurred

0= A Trap Conflict Reset has not occurred

IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit

1= An illegal opcode detection, an illegal address mode or uninitialized W register used as an

Address Pointer caused a Reset

0= An illegal opcode or uninitialized W Reset has not occurred

bit 13-10

bit 9

Unimplemented: Read as ‘0’

CM: Configuration Word Mismatch Reset Flag bit

1= A Configuration Word Mismatch Reset has occurred

0= A Configuration Word Mismatch Reset has not occurred

bit 8

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

VREGS: Voltage Regulator Standby Enable bit

1= Regulator remains active during Sleep

0= Regulator goes to standby during Sleep

EXTR: External Reset (MCLR) Pin bit

1= A Master Clear (pin) Reset has occurred

0= A Master Clear (pin) Reset has not occurred

SWR: Software Reset (Instruction) Flag bit

1= A RESETinstruction has been executed

0= A RESETinstruction has not been executed

SWDTEN: Software Enable/Disable of WDT bit⁽²⁾

1= WDT is enabled

0= WDT is disabled

WDTO: Watchdog Timer Time-out Flag bit

1= WDT time-out has occurred

0= WDT time-out has not occurred

SLEEP: Wake From Sleep Flag bit

1= Device has been in Sleep mode

0= Device has not been in Sleep mode

IDLE: Wake-up From Idle Flag bit

1= Device was in Idle mode

0= Device was not in Idle mode

Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not

cause a device Reset.

2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the

SWDTEN bit setting.

DS39747F-page 58

 2005-2012 Microchip Technology Inc.

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REGISTER 6-1:

RCON: RESET CONTROL REGISTER⁽¹⁾(CONTINUED)

bit 1

BOR: Brown-out Reset Flag bit

1= A Brown-out Reset has occurred (note that BOR is also set after a Power-on Reset)

0= A Brown-out Reset has not occurred

bit 0

POR: Power-on Reset Flag bit

1= A Power-on Reset has occurred

0= A Power-on Reset has not occurred

Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not

cause a device Reset.

2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the

SWDTEN bit setting.

TABLE 6-1:

RESET FLAG BIT OPERATION

Setting Event

Flag Bit

Clearing Event

TRAPR (RCON<15>)

IOPUWR (RCON<14>)

EXTR (RCON<7>)

SWR (RCON<6>)

WDTO (RCON<4>)

SLEEP (RCON<3>)

IDLE (RCON<2>)

BOR (RCON<1>)

POR (RCON<0>)

Trap conflict event

POR

Illegal opcode or uninitialized W register access

MCLR Reset

RESETinstruction

WDT time-out

PWRSAVinstruction, POR

PWRSAV #SLEEPinstruction

PWRSAV #IDLEinstruction

POR, BOR

POR

—

POR

—

Note: All Reset flag bits may be set or cleared by the user software.

6.1

Clock Source Selection at Reset

6.2

Device Reset Times

If clock switching is enabled, the system clock source at

device Reset is chosen as shown in Table 6-2. If clock

switching is disabled, the system clock source is always

selected according to the oscillator Configuration bits.

Refer to Section 8.0 “Oscillator Configuration” for

further details.

The Reset times for various types of device Reset are

summarized in Table 6-3. Note that the system Reset

signal, SYSRST, is released after the POR and PWRT

delay times expire.

The time that the device actually begins to execute

code will also depend on the system oscillator delays,

which include the Oscillator Start-up Timer (OST) and

the PLL lock time. The OST and PLL lock times occur

in parallel with the applicable SYSRST delay times.

TABLE 6-2:

OSCILLATOR SELECTION vs.

TYPE OF RESET (CLOCK

SWITCHING ENABLED)

The FSCM delay determines the time at which the

FSCM begins to monitor the system clock source after

the SYSRST signal is released.

Reset Type

Clock Source Determinant

POR

Oscillator Configuration bits

(FNOSC<2:0>)

BOR

MCLR

WDTR

SWR

COSC Control bits

(OSCCON<14:12>)

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TABLE 6-3:

Reset Type

POR

RESET DELAY TIMES FOR VARIOUS DEVICE RESETS

System Clock

Delay

FSCM

Delay

Clock Source

SYSRST Delay

Notes

1, 2, 3

EC, FRC, FRCDIV, LPRC TPOR + TSTARTUP + TRST

—

TFSCM

—

ECPLL, FRCPLL

XT, HS, SOSC

XTPLL, HSPLL

EC, FRC, FRCDIV, LPRC

ECPLL, FRCPLL

XT, HS, SOSC

XTPLL, HSPLL

Any Clock

TPOR + TSTARTUP + TRST

TLOCK

TOST

1, 2, 3, 5, 6

1, 2, 3, 4, 6

TPOR + TSTARTUP + TRST TOST + TLOCK

1, 2, 3, 4, 5, 6

BOR

TSTARTUP + TRST

TRST

—

2, 3

TLOCK

TFSCM

—

2, 3, 5, 6

TOST

2, 3, 4, 6

TOST + TLOCK

2, 3, 4, 5, 6

MCLR

WDT

—

3

Any Clock

TRST

—

Software

Any Clock

TRST

—

Illegal Opcode Any Clock

Uninitialized W Any Clock

TRST

—

TRST

—

Trap Conflict

Any Clock

TRST

—

Note 1: TPOR = Power-on Reset delay (10 s nominal).

2: TSTARTUP = TVREG (10 s nominal) if the on-chip regulator is enabled or TPWRT (64 ms nominal) if an

on-chip regulator is disabled.

3: TRST = Internal state Reset time (20 s nominal).

4: TOST = Oscillator Start-up Timer. A 10-bit counter counts 1024 oscillator periods before releasing the

oscillator clock to the system.

5: TLOCK = PLL lock time.

6: TFSCM = Fail-Safe Clock Monitor delay (100 s nominal).

DS39747F-page 60

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6.2.1

POR AND LONG OSCILLATOR

START-UP TIMES

6.2.2.1

FSCM Delay for Crystal and PLL

Clock Sources

The oscillator start-up circuitry and its associated delay

timers are not linked to the device Reset delays that

occur at power-up. Some crystal circuits (especially

low-frequency crystals) will have a relatively long

start-up time. Therefore, one or more of the following

conditions is possible after SYSRST is released:

When the system clock source is provided by a crystal

oscillator and/or the PLL, a small delay, TFSCM, will

automatically be inserted after the POR and PWRT

delay times. The FSCM will not begin to monitor the

system clock source until this delay expires. The FSCM

delay time is nominally 100 s and provides additional

time for the oscillator and/or PLL to stabilize. In most

cases, the FSCM delay will prevent an oscillator failure

trap at a device Reset when the PWRT is disabled.

• The oscillator circuit has not begun to oscillate.

• The Oscillator Start-up Timer has NOT expired (if

a crystal oscillator is used).

• The PLL has not achieved a lock (if PLL is used).

6.3

Special Function Register Reset

States

The device will not begin to execute code until a valid

clock source has been released to the system. There-

fore, the oscillator and PLL start-up delays must be

considered when the Reset delay time must be known.

Most of the Special Function Registers (SFRs) associ-

ated with the PIC24F CPU and peripherals are reset to a

particular value at a device Reset. The SFRs are

grouped by their peripheral or CPU function and their

Reset values are specified in each section of this manual.

6.2.2

FAIL-SAFE CLOCK MONITOR

(FSCM) AND DEVICE RESETS

The Reset value for each SFR does not depend on the

type of Reset, with the exception of four registers. The

Reset value for the Reset Control register, RCON, will

depend on the type of device Reset. The Reset value for

the Oscillator Control register, OSCCON, will depend on

the type of Reset and the programmed values of the

oscillator Configuration bits in the FOSC Device Config-

uration register (see Table 6-2). The RCFGCAL and

NVMCON registers are only affected by a POR.

If the FSCM is enabled, it will begin to monitor the sys-

tem clock source when SYSRST is released. If a valid

clock source is not available at this time, the device will

automatically switch to the FRC oscillator and the user

can switch to the desired crystal oscillator in the Trap

Service Routine.

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DS39747F-page 61

PIC24FJ128GA010 FAMILY

NOTES:

DS39747F-page 62

 2005-2012 Microchip Technology Inc.

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7.1.1

ALTERNATE INTERRUPT VECTOR

TABLE

7.0

INTERRUPT CONTROLLER

Note: This data sheet summarizes the features

of this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. Refer to Section 8. “Interrupts”

(DS39707) in the “PIC24F Family

Reference Manual” for more information.

The Alternate Interrupt Vector Table (AIVT) is located

after the IVT, as shown in Figure 7-1. Access to the

AIVT is provided by the ALTIVT control bit

(INTCON2<15>). If the ALTIVT bit is set, all interrupt

and exception processes will use the alternate vectors

instead of the default vectors. The alternate vectors are

organized in the same manner as the default vectors.

The PIC24F interrupt controller reduces the numerous

peripheral interrupt request signals to a single interrupt

request signal to the PIC24F CPU. It has the following

features:

The AIVT supports emulation and debugging efforts by

providing a means to switch between an application

and a support environment without requiring the inter-

rupt vectors to be reprogrammed. This feature also

enables switching between applications for evaluation

of different software algorithms at run time. If the AIVT

is not needed, the AIVT should be programmed with

the same addresses used in the IVT.

• Up to 8 processor exceptions and software traps

• 7 user-selectable priority levels

• Interrupt Vector Table (IVT) with up to 118 vectors

• A unique vector for each interrupt or exception

source

• Fixed priority within a specified user priority level

7.2

Reset Sequence

• Alternate Interrupt Vector Table (AIVT) for debug

support

A device Reset is not a true exception because the

interrupt controller is not involved in the Reset process.

The PIC24F device clears its registers in response to a

Reset which forces the PC to zero. The microcontroller

then begins program execution at location, 000000h.

The user programs a GOTO instruction at the Reset

address, which redirects program execution to the

appropriate start-up routine.

• Fixed interrupt entry and return latencies

7.1

Interrupt Vector Table

The Interrupt Vector Table (IVT) is shown in Figure 7-1.

The IVT resides in program memory, starting at location,

000004h. The IVT contains 126 vectors, consisting of

8 non-maskable trap vectors, plus up to 118 sources of

interrupt. In general, each interrupt source has its own

vector. Each interrupt vector contains a 24-bit wide

address. The value programmed into each interrupt vec-

tor location is the starting address of the associated

Interrupt Service Routine (ISR).

Note: Any unimplemented or unused vector

locations in the IVT and AIVT should be

programmed with the address of a default

interrupt handler routine that contains a

RESETinstruction.

Interrupt vectors are prioritized in terms of their natural

priority; this is linked to their position in the vector table.

All other things being equal, lower addresses have a

higher natural priority. For example, the interrupt asso-

ciated with Vector 0 will take priority over interrupts at

any other vector address.

PIC24FJ128GA010 family devices implement non-

maskable traps and unique interrupts. These are

summarized in Table 7-1 and Table 7-2.

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PIC24FJ128GA010 FAMILY

FIGURE 7-1:

PIC24F INTERRUPT VECTOR TABLE

Reset – GOTOInstruction

Reset – GOTOAddress

Reserved

000000h

000002h

000004h

Oscillator Fail Trap Vector

Address Error Trap Vector

Stack Error Trap Vector

Math Error Trap Vector

Reserved

Interrupt Vector 0

Interrupt Vector 1

—

000014h

—

Interrupt Vector 52

Interrupt Vector 53

Interrupt Vector 54

—

00007Ch

00007Eh

000080h

(1)

Interrupt Vector Table (IVT)

—

Interrupt Vector 116

Interrupt Vector 117

Reserved

0000FCh

0000FEh

000100h

000102h

Reserved

Oscillator Fail Trap Vector

Address Error Trap Vector

Stack Error Trap Vector

Math Error Trap Vector

Reserved

Interrupt Vector 0

Interrupt Vector 1

—

000114h

—

(1)

Alternate Interrupt Vector Table (AIVT)

Interrupt Vector 52

Interrupt Vector 53

Interrupt Vector 54

—

00017Ch

00017Eh

000180h

—

Interrupt Vector 116

Interrupt Vector 117

Start of Code

0001FEh

000200h

Note 1: See Table 7-2 for the interrupt vector list.

TABLE 7-1:

TRAP VECTOR DETAILS

IVT Address

Vector Number

AIVT Address

Trap Source

0

1

2

3

4

5

6

7

000004h

000006h

000008h

00000Ah

00000Ch

00000Eh

000010h

000012h

000104h

000106h

000108h

00010Ah

00010Ch

00010Eh

000110h

000112h

Reserved

Oscillator Failure

Address Error

Stack Error

Math Error

Reserved

DS39747F-page 64

 2005-2012 Microchip Technology Inc.

PIC24FJ128GA010 FAMILY

TABLE 7-2:

IMPLEMENTED INTERRUPT VECTORS

Interrupt Bit Locations

Enable

Vector

Number

AIVT

Address

Interrupt Source

IVT Address

Flag

Priority

ADC1 Conversion Done

Comparator Event

CRC Generator

External Interrupt 0

External Interrupt 1

External Interrupt 2

External Interrupt 3

External Interrupt 4

I2C1 Master Event

I2C1 Slave Event

I2C2 Master Event

I2C2 Slave Event

Input Capture 1

Input Capture 2

Input Capture 3

Input Capture 4

Input Capture 5

Input Change Notification

Output Compare 1

Output Compare 2

Output Compare 3

Output Compare 4

Output Compare 5

Parallel Master Port

Real-Time Clock/Calendar

SPI1 Error

13

18

67

0

00002Eh

000038h

00009Ah

000014h

00003Ch

00004Eh

00007Eh

000080h

000036h

000034h

000078h

000076h

000016h

00001Eh

00005Eh

000060h

000062h

00003Ah

000018h

000020h

000046h

000048h

000066h

00006Eh

000090h

000026h

000028h

000054h

000056h

00001Ah

000022h

000024h

00004Ah

00004Ch

000096h

00002Ah

00002Ch

000098h

000050h

000052h

00012Eh

000138h

00019Ah

000114h

00013Ch

00014Eh

00017Eh

000180h

000136h

000134h

000178h

000176h

000116h

00011Eh

00015Eh

000160h

000162h

00013Ah

000118h

000120h

000146h

000148h

000166h

00016Eh

000190h

000126h

000128h

000154h

000156h

00011Ah

000122h

000124h

00014Ah

00014Ch

000196h

00012Ah

00012Ch

000198h

000150h

000152h

IFS0<13>

IFS1<2>

IFS4<3>

IFS0<0>

IFS1<4>

IFS1<13>

IFS3<5>

IFS3<6>

IFS1<1>

IFS1<0>

IFS3<2>

IFS3<1>

IFS0<1>

IFS0<5>

IFS2<5>

IFS2<6>

IFS2<7>

IFS1<3>

IFS0<2>

IFS0<6>

IFS1<9>

IFS1<10>

IFS2<9>

IFS2<13>

IFS3<14>

IFS0<9>

IFS0<10>

IFS2<0>

IFS2<1>

IFS0<3>

IFS0<7>

IFS0<8>

IFS1<11>

IFS1<12>

IFS4<1>

IFS0<11>

IFS0<12>

IFS4<2>

IFS1<14>

IFS1<15>

IEC0<13>

IEC1<2>

IEC4<3>

IEC0<0>

IEC1<4>

IEC1<13>

IEC3<5>

IEC3<6>

IEC1<1>

IEC1<0>

IEC3<2>

IEC3<1>

IEC0<1>

IEC0<5>

IEC2<5>

IEC2<6>

IEC2<7>

IEC1<3>

IEC0<2>

IEC0<6>

IEC1<9>

IEC1<10>

IEC2<9>

IEC2<13>

IEC3<14>

IEC0<9>

IEC0<10>

IEC0<0>

IEC2<1>

IEC0<3>

IEC0<7>

IEC0<8>

IEC1<11>

IEC1<12>

IEC4<1>

IEC0<11>

IEC0<12>

IEC4<2>

IEC1<14>

IEC1<15>

IPC3<6:4>

IPC4<10:8>

IPC16<14:12>

IPC0<2:0>

20

29

53

54

17

16

50

49

1

IPC5<2:0>

IPC7<6:4>

IPC13<6:4>

IPC13<10:8>

IPC4<6:4>

IPC4<2:0>

IPC12<10:8>

IPC12<6:4>

IPC0<6:4>

5

IPC1<6:4>

37

38

39

19

2

IPC9<6:4>

IPC9<10:8>

IPC9<14:12>

IPC4<14:12>

IPC0<10:8>

IPC1<10:8>

IPC6<6:4>

6

25

26

41

45

62

9

IPC6<10:8>

IPC10<6:4>

IPC11<6:4>

IPC15<10:8>

IPC2<6:4>

SPI1 Event

10

32

33

3

IPC2<10:8>

IPC8<2:0>

SPI2 Error

SPI2 Event

IPC8<6:4>

Timer1

IPC0<14:12>

IPC1<14:12>

IPC2<2:0>

Timer2

7

Timer3

8

Timer4

27

28

65

11

12

66

30

31

IPC6<14:12>

IPC7<2:0>

Timer5

UART1 Error

IPC16<6:4>

IPC2<14:12>

IPC3<2:0>

UART1 Receiver

UART1 Transmitter

UART2 Error

IPC16<10:8>

IPC7<10:8>

IPC7<14:12>

UART2 Receiver

UART2 Transmitter

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The interrupt sources are assigned to the IFSx, IECx

and IPCx registers in the same sequence that they are

listed in Table 7-2. For example, the INT0 (External

Interrupt 0) is shown as having a vector number and a

natural order priority of 0. Thus, the INT0IF status bit is

found in IFS0<0>, the enable bit in IEC0<0> and the

priority bits in the first position of IPC0 (IPC0<2:0>).

7.3

Interrupt Control and Status

Registers

The PIC24FJ128GA010 family devices implement a

total of 29 registers for the interrupt controller:

• INTCON1

• INTCON2

Although they are not specifically part of the interrupt

control hardware, two of the CPU control registers con-

tain bits that control interrupt functionality. The CPU

STATUS register (SR) contains the IPL<2:0> bits

(SR<7:5>). These indicate the current CPU Interrupt

Priority Level. The user may change the current CPU

priority level by writing to the IPL bits.

• IFS0 through IFS4

• IEC0 through IEC4

• IPC0 through IPC14, and IPC16

• INTTREG

Global interrupt control functions are controlled from

INTCON1 and INTCON2. INTCON1 contains the Inter-

rupt Nesting Disable (NSTDIS) bit, as well as the

control and status flags for the processor trap sources.

The INTCON2 register controls the external interrupt

request signal behavior and the use of the Alternate

Interrupt Vector Table.

The CORCON register contains the IPL3 bit, which

together with IPL<2:0>, also indicates the current CPU

priority level. IPL3 is a read-only bit so that trap events

cannot be masked by the user software.

The interrupt controller has the Interrupt Controller Test

Register (INTTREG) that displays the status of the

interrupt controller. When an interrupt request occurs,

its associated vector number and the new interrupt pri-

ority level are latched into INTTREG. This information

can be used to determine a specific interrupt source if

a generic ISR is used for multiple vectors, such as

when ISR remapping is used in bootloader applica-

tions. It also could be used to check if another interrupt

is pending while in an ISR.

The IFS registers maintain all of the interrupt request

flags. Each source of interrupt has a status bit which is

set by the respective peripherals, or external signal,

and is cleared via software.

The IEC registers maintain all of the interrupt enable

bits. These control bits are used to individually enable

interrupts from the peripherals or external signals.

The IPC registers are used to set the Interrupt Priority

Level for each source of interrupt. Each user interrupt

source can be assigned to one of eight priority levels.

All Interrupt registers are described in Register 7-1

through Register 7-30, in the following pages.

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REGISTER 7-1:

SR: CPU STATUS REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

DC⁽¹⁾

bit 15

bit 8

R/W-0⁽¹⁾

IPL2^(2,3)

bit 7

R/W-0⁽¹⁾

IPL1^(2,3)

R/W-0⁽¹⁾

IPL0^(2,3)

R-0

RA⁽¹⁾

R/W-0

N⁽¹⁾

R/W-0

OV⁽¹⁾

R/W-0

Z⁽¹⁾

R/W-0

C⁽¹⁾

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-5

IPL<2:0>: CPU Interrupt Priority Level Status bits^(2,3)

111= CPU Interrupt Priority Level is 7 (15); user interrupts are disabled

110= CPU Interrupt Priority Level is 6 (14)

101= CPU Interrupt Priority Level is 5 (13)

100= CPU Interrupt Priority Level is 4 (12)

011= CPU Interrupt Priority Level is 3 (11)

010= CPU Interrupt Priority Level is 2 (10)

001= CPU Interrupt Priority Level is 1 (9)

000= CPU Interrupt Priority Level is 0 (8)

Note 1: See Register 3-1 for the description of the remaining bit(s) that are not dedicated to interrupt control functions.

2: The IPL bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU Interrupt Priority Level. The

value in parentheses indicates the Interrupt Priority Level if IPL3 = 1.

3: The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1.

REGISTER 7-2:

CORCON: CORE CONTROL REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

U-0

—

U-0

—

U-0

—

R/C-0

IPL3⁽²⁾

R/W-0

PSV⁽¹⁾

U-0

—

U-0

—

bit 7

Legend:

C = Clearable bit

W = Writable bit

‘1’ = Bit is set

R = Readable bit

-n = Value at POR

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 3

IPL3: CPU Interrupt Priority Level Status bit⁽²⁾

1= CPU Interrupt Priority Level is greater than 7

0= CPU Interrupt Priority Level is 7 or less

Note 1: See Register 3-2 for the description of the remaining bit(s) that are not dedicated to interrupt control functions.

2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.

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REGISTER 7-3:

INTCON1: INTERRUPT CONTROL REGISTER 1

R/W-0

NSTDIS

bit 15

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 8

bit 0

U-0

—

U-0

—

U-0

—

R/W-0

U-0

—

MATHERR ADDRERR

STKERR

OSCFAIL

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

NSTDIS: Interrupt Nesting Disable bit

1= Interrupt nesting is disabled

0= Interrupt nesting is enabled

bit 14-5

bit 4

Unimplemented: Read as ‘0’

MATHERR: Arithmetic Error Trap Status bit

1= Overflow trap has occurred

0= Overflow trap has not occurred

bit 3

bit 2

bit 1

bit 0

ADDRERR: Address Error Trap Status bit

1= Address error trap has occurred

0= Address error trap has not occurred

STKERR: Stack Error Trap Status bit

1= Stack error trap has occurred

0= Stack error trap has not occurred

OSCFAIL: Oscillator Failure Trap Status bit

1= Oscillator failure trap has occurred

0= Oscillator failure trap has not occurred

Unimplemented: Read as ‘0’

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REGISTER 7-4:

INTCON2: INTERRUPT CONTROL REGISTER 2

R/W-0

ALTIVT

bit 15

R-0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

DISI

bit 8

U-0

—

U-0

—

U-0

—

R/W-0

INT4EP

INT3EP

INT2EP

INT1EP

INT0EP

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

bit 14

ALTIVT: Enable Alternate Interrupt Vector Table bit

1= Use alternate vector table

0= Use standard (default) vector table

DISI: DISIInstruction Status bit

1= DISIinstruction is active

0= DISIis not active

bit 13-5

bit 4

Unimplemented: Read as ‘0’

INT4EP: External Interrupt 4 Edge Detect Polarity Select bit

1= Interrupt on negative edge

0= Interrupt on positive edge

bit 3

bit 2

bit 1

bit 0

INT3EP: External Interrupt 3 Edge Detect Polarity Select bit

1= Interrupt on negative edge

0= Interrupt on positive edge

INT2EP: External Interrupt 2 Edge Detect Polarity Select bit

1= Interrupt on negative edge

0= Interrupt on positive edge

INT1EP: External Interrupt 1 Edge Detect Polarity Select bit

1= Interrupt on negative edge

0= Interrupt on positive edge

INT0EP: External Interrupt 0 Edge Detect Polarity Select bit

1= Interrupt on negative edge

0= Interrupt on positive edge

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REGISTER 7-5:

IFS0: INTERRUPT FLAG STATUS REGISTER 0

U-0

—

U-0

—

R/W-0

AD1IF

R/W-0

SPI1IF

R/W-0

T3IF

U1TXIF

U1RXIF

SPF1IF

bit 15

bit 8

R/W-0

T2IF

R/W-0

OC2IF

R/W-0

IC2IF

U-0

—

R/W-0

T1IF

R/W-0

OC1IF

R/W-0

IC1IF

R/W-0

INT0IF

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-14

bit 13

Unimplemented: Read as ‘0’

AD1IF: A/D Conversion Complete Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 12

bit 11

bit 10

bit 9

U1TXIF: UART1 Transmitter Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

U1RXIF: UART1 Receiver Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

SPI1IF: SPI1 Event Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

SPF1IF: SPI1 Fault Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 8

T3IF: Timer3 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 7

T2IF: Timer2 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 6

OC2IF: Output Compare Channel 2 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 5

IC2IF: Input Capture Channel 2 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 4

bit 3

Unimplemented: Read as ‘0’

T1IF: Timer1 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 2

bit 1

bit 0

OC1IF: Output Compare Channel 1 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

IC1IF: Input Capture Channel 1 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

INT0IF: External Interrupt 0 Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

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REGISTER 7-6:

IFS1: INTERRUPT FLAG STATUS REGISTER 1

R/W-0

U2TXIF

bit 15

R/W-0

INT2IF

R/W-0

T5IF

R/W-0

T4IF

R/W-0

OC4IF

R/W-0

OC3IF

U-0

—

U2RXIF

bit 8

U-0

—

U-0

—

U-0

—

R/W-0

INT1IF

R/W-0

CNIF

R/W-0

CMIF

R/W-0

MI2C1IF

SI2C1IF

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

U2TXIF: UART2 Transmitter Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

U2RXIF: UART2 Receiver Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

INT2IF: External Interrupt 2 Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

T5IF: Timer5 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

T4IF: Timer4 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

OC4IF: Output Compare Channel 4 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

OC3IF: Output Compare Channel 3 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 8-5

bit 4

Unimplemented: Read as ‘0’

INT1IF: External Interrupt 1 Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 3

bit 2

bit 1

bit 0

CNIF: Input Change Notification Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

CMIF: Comparator Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

MI2C1IF: Master I2C1 Event Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

SI2C1IF: Slave I2C1 Event Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

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REGISTER 7-7:

IFS2: INTERRUPT FLAG STATUS REGISTER 2

U-0

—

U-0

—

R/W-0

PMPIF

U-0

—

U-0

—

U-0

—

R/W-0

OC5IF

U-0

—

bit 15

bit 8

R/W-0

IC5IF

R/W-0

IC4IF

R/W-0

IC3IF

U-0

—

U-0

—

U-0

—

R/W-0

SPI2IF

R/W-0

SPF2IF

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-14

bit 13

Unimplemented: Read as ‘0’

PMPIF: Parallel Master Port Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 12-10

bit 9

Unimplemented: Read as ‘0’

OC5IF: Output Compare Channel 5 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 8

bit 7

Unimplemented: Read as ‘0’

IC5IF: Input Capture Channel 5 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 6

bit 5

IC4IF: Input Capture Channel 4 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

IC3IF: Input Capture Channel 3 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 4-2

bit 1

Unimplemented: Read as ‘0’

SPI2IF: SPI2 Event Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 0

SPF2IF: SPI2 Fault Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

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REGISTER 7-8:

IFS3: INTERRUPT FLAG STATUS REGISTER 3

U-0

—

R/W-0

PMPIF

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

R/W-0

INT4IF

R/W-0

INT3IF

U-0

—

U-0

—

R/W-0

U-0

—

MI2C2IF

SI2C2IF

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

bit 14

Unimplemented: Read as ‘0’

RTCIF: Real-Time Clock/Calendar Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 13-7

bit 6

Unimplemented: Read as ‘0’

INT4IF: External Interrupt 4 Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 5

INT3IF: External Interrupt 3 Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 4-3

bit 2

Unimplemented: Read as ‘0’

MI2C2IF: Master I2C2 Event Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 1

bit 0

SI2C2IF: Slave I2C2 Event Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

Unimplemented: Read as ‘0’

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REGISTER 7-9:

IFS4: INTERRUPT FLAG STATUS REGISTER 4

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

CRCIF

R/W-0

U-0

—

U2ERIF

U1ERIF

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-4

bit 3

Unimplemented: Read as ‘0’

CRCIF: CRC Generator Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 2

bit 1

bit 0

U2ERIF: UART2 Error Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

U1ERIF: UART1 Error Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

Unimplemented: Read as ‘0’

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REGISTER 7-10: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0

U-0

—

U-0

—

R/W-0

AD1IE

R/W-0

T3IE

U1TXIE

U1RXIE

SPI1IE

SPF1IE

bit 15

bit 8

R/W-0

T2IE

R/W-0

OC2IE

R/W-0

IC2IE

U-0

—

R/W-0

T1IE

R/W-0

OC1IE

R/W-0

IC1IE

R/W-0

INT0IE

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-14

bit 13

Unimplemented: Read as ‘0’

AD1IE: A/D Conversion Complete Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 12

bit 11

bit 10

bit 9

U1TXIE: UART1 Transmitter Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

U1RXIE: UART1 Receiver Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

SPI1IE: SPI1 Transfer Complete Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

SPF1IE: SPI1 Fault Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 8

T3IE: Timer3 Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 7

T2IE: Timer2 Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 6

OC2IE: Output Compare Channel 2 Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 5

IC2IE: Input Capture Channel 2 Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 4

bit 3

Unimplemented: Read as ‘0’

T1IE: Timer1 Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 2

bit 1

bit 0

OC1IE: Output Compare Channel 1 Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

IC1IE: Input Capture Channel 1 Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

INT0IE: External Interrupt 0 Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

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REGISTER 7-11: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1

R/W-0

T5IE

R/W-0

T4IE

R/W-0

OC4IE

R/W-0

OC3IE

U-0

—

U2TXIE

U2RXIE

INT2IE

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-0

CNIE

R/W-0

CMIE

R/W-0

INT1IE

MI2C1IE

SI2C1IE

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

U2TXIE: UART2 Transmitter Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

U2RXIE: UART2 Receiver Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

INT2IE: External Interrupt 2 Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

T5IE: Timer5 Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

T4IE: Timer4 Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

OC4IE: Output Compare Channel 4 Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

OC3IE: Output Compare Channel 3 Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 8-5

bit 4

Unimplemented: Read as ‘0’

INT1IE: External Interrupt 1 Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 3

bit 2

bit 1

bit 0

CNIE: Input Change Notification Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

CMIE: Comparator Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

MI2C1IE: Master I2C1 Event Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

SI2C1IE: Slave I2C1 Event Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

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REGISTER 7-12: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2

U-0

—

U-0

—

R/W-0

U-0

—

U-0

—

U-0

—

R/W-0

OC5IE

U-0

—

PMPIE

bit 15

bit 8

R/W-0

IC5IE

R/W-0

IC4IE

R/W-0

IC3IE

U-0

—

U-0

—

U-0

—

R/W-0

SPI2IE

SPF2IE

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-14

bit 13

Unimplemented: Read as ‘0’

PMPIE: Parallel Master Port Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 12-10

bit 9

Unimplemented: Read as ‘0’

OC5IE: Output Compare Channel 5 Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 8

bit 7

Unimplemented: Read as ‘0’

IC5IE: Input Capture Channel 5 Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 6

bit 5

IC4IE: Input Capture Channel 4 Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

IC3IE: Input Capture Channel 3 Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 4-2

bit 1

Unimplemented: Read as ‘0’

SPI2IE: SPI2 Event Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 0

SPF2IE: SPI2 Fault Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

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REGISTER 7-13: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3

U-0

—

R/W-0

RTCIE

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

R/W-0

U-0

—

U-0

—

R/W-0

U-0

—

INT4IE

INT3IE

MI2C2IE

SI2C2IE

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

bit 14

Unimplemented: Read as ‘0’

RTCIE: Real-Time Clock/Calendar Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 13-7

bit 6

Unimplemented: Read as ‘0’

INT4IE: External Interrupt 4 Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 5

INT3IE: External Interrupt 3 Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 4-3

bit 2

Unimplemented: Read as ‘0’

MI2C2IE: Master I2C2 Event Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 1

bit 0

SI2C2IE: Slave I2C2 Event Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

Unimplemented: Read as ‘0’

DS39747F-page 78

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REGISTER 7-14: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

U-0

—

CRCIE

U2ERIE

U1ERIE

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-4

bit 3

Unimplemented: Read as ‘0’

CRCIE: CRC Generator Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 2

U2ERIE: UART2 Error Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 1

bit 0

U1ERIE: UART1 Error Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

Unimplemented: Read as ‘0’

 2005-2012 Microchip Technology Inc.

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REGISTER 7-15: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0

U-0

—

R/W-1

T1IP2

R/W-0

T1IP1

R/W-0

T1IP0

U-0

—

R/W-1

R/W-0

OC1IP2

OC1IP1

OC1IP0

bit 15

bit 8

U-0

—

R/W-1

IC1IP2

R/W-0

IC1IP1

R/W-0

IC1IP0

U-0

—

R/W-1

R/W-0

INT0IP2

INT0IP1

INT0IP0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

T1IP<2:0>: Timer1 Interrupt Priority bits

bit 14-12

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8

OC1IP<2:0>: Output Compare Channel 1 Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

IC1IP<2:0>: Input Capture Channel 1 Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 3

Unimplemented: Read as ‘0’

bit 2-0

INT0IP<2:0:> External Interrupt 0 Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

DS39747F-page 80

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REGISTER 7-16: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1

U-0

—

R/W-1

T2IP2

R/W-0

T2IP1

R/W-0

T2IP0

U-0

—

R/W-1

R/W-0

OC2IP2

OC2IP1

OC2IP0

bit 15

bit 8

U-0

—

R/W-1

IC2IP2

R/W-0

IC2IP1

R/W-0

IC2IP0

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

T2IP<2:0>: Timer2 Interrupt Priority bits

bit 14-12

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8

OC2IP<2:0>: Output Compare Channel 2 Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 3-0

Unimplemented: Read as ‘0’

 2005-2012 Microchip Technology Inc.

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REGISTER 7-17: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

U1RXIP2

U1RXIP1

U1RXIP0

SPI1IP2

SPI1IP1

SPI1IP0

bit 15

bit 8

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

T3IP2

R/W-0

T3IP1

R/W-0

T3IP0

SPF1IP2

SPF1IP1

SPF1IP0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

Unimplemented: Read as ‘0’

bit 14-12

U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8

SPI1IP<2:0>: SPI1 Event Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

SPF1IP<2:0>: SPI1 Fault Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 3

Unimplemented: Read as ‘0’

bit 2-0

T3IP<2:0>: Timer3 Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

DS39747F-page 82

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REGISTER 7-18: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

AD1IP2

AD1IP1

AD1IP0

U1TXIP2

U1TXIP1

U1TXIP0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-7

bit 6-4

Unimplemented: Read as ‘0’

AD1IP<2:0>: A/D Conversion Complete Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 3

Unimplemented: Read as ‘0’

bit 2-0

U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

 2005-2012 Microchip Technology Inc.

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REGISTER 7-19: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4

U-0

—

R/W-1

CNIP2

R/W-0

CNIP1

R/W-0

CNIP0

U-0

—

R/W-1

CMIP2

R/W-0

CMIP1

R/W-0

CMIP0

bit 15

bit 8

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

MI2C1IP2

MI2C1IP1

MI2C1IP0

SI2C1IP2

SI2C1IP1

SI2C1IP0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

Unimplemented: Read as ‘0’

bit 14-12

CNIP<2:0>: Input Change Notification Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8

CMIP<2:0>: Comparator Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

MI2C1IP<2:0>: Master I2C1 Event Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 3

Unimplemented: Read as ‘0’

bit 2-0

SI2C1IP<2:0>: Slave I2C1 Event Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

DS39747F-page 84

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REGISTER 7-20: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-1

R/W-0

INT1IP2

INT1IP1

INT1IP0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-3

bit 2-0

Unimplemented: Read as ‘0’

INT1IP<2:0>: External Interrupt 1 Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

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REGISTER 7-21: IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6

U-0

—

R/W-1

T4IP2

R/W-0

T4IP1

R/W-0

T4IP0

U-0

—

R/W-1

R/W-0

OC4IP2

OC4IP1

OC4IP0

bit 15

bit 8

U-0

—

R/W-1

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

OC3IP2

OC3IP1

OC3IP0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

T4IP<2:0>: Timer4 Interrupt Priority bits

bit 14-12

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8

OC4IP<2:0>: Output Compare Channel 4 Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

OC3IP<2:0>: Output Compare Channel 3 Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 3-0

Unimplemented: Read as ‘0’

DS39747F-page 86

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REGISTER 7-22: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

U2TXIP2

U2TXIP1

U2TXIP0

U2RXIP2

U2RXIP1

U2RXIP0

bit 15

bit 8

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

T5IP2

R/W-0

T5IP1

R/W-0

T5IP0

INT2IP2

INT2IP1

INT2IP0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

Unimplemented: Read as ‘0’

bit 14-12

U2TXIP<2:0>: UART2 Transmitter Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8

U2RXIP<2:0>: UART2 Receiver Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

INT2IP<2:0>: External Interrupt 2 Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 3

Unimplemented: Read as ‘0’

bit 2-0

T5IP<2:0>: Timer5 Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

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REGISTER 7-23: IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

SPI2IP2

SPI2IP1

SPI2IP0

SPF2IP2

SPF2IP1

SPF2IP0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-7

bit 6-4

Unimplemented: Read as ‘0’

SPI2IP<2:0>: SPI2 Event Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 3

Unimplemented: Read as ‘0’

bit 2-0

SPF2IP<2:0>: SPI2 Fault Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

DS39747F-page 88

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REGISTER 7-24: IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9

U-0

—

R/W-1

IC5IP2

R/W-0

IC5IP1

R/W-0

IC5IP0

U-0

—

R/W-1

IC4IP2

R/W-0

IC4IP1

R/W-0

IC4IP0

bit 15

bit 8

U-0

—

R/W-1

IC3IP2

R/W-0

IC3IP1

R/W-0

IC3IP0

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

bit 14-12

IC5IP<2:0>: Input Capture Channel 5 Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8

IC4IP<2:0>: Input Capture Channel 4 Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

IC3IP<2:0>: Input Capture Channel 3 Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 3-0

Unimplemented: Read as ‘0’

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REGISTER 7-25: IPC10: INTERRUPT PRIORITY CONTROL REGISTER 10

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

R/W-1

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

OC5IP2

OC5IP1

OC5IP0

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-7

bit 6-4

Unimplemented: Read as ‘0’

OC5IP<2:0>: Output Compare Channel 5 Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 3-0

Unimplemented: Read as ‘0’

REGISTER 7-26: IPC11: INTERRUPT PRIORITY CONTROL REGISTER 11

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

R/W-1

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

PMPIP2

PMPIP1

PMPIP0

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-7

bit 6-4

Unimplemented: Read as ‘0’

PMPIP<2:0>: Parallel Master Port Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 3-0

Unimplemented: Read as ‘0’

DS39747F-page 90

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REGISTER 7-27: IPC12: INTERRUPT PRIORITY CONTROL REGISTER 12

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-1

R/W-0

MI2C2IP2

MI2C2IP1

MI2C2IP0

bit 15

bit 8

U-0

—

R/W-1

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

SI2C2IP2

SI2C2IP1

SI2C2IP0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-11

bit 10-8

Unimplemented: Read as ‘0’

MI2C2IP<2:0>: Master I2C2 Event Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

SI2C2IP<2:0>: Slave I2C2 Event Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 3-0

Unimplemented: Read as ‘0’

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REGISTER 7-28: IPC13: INTERRUPT PRIORITY CONTROL REGISTER 13

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-1

R/W-0

IN4IP1

R/W-0

INT4IP2

INT4IP0

bit 15

bit 8

U-0

—

R/W-1

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

INT3IP2

INT3IP1

INT3IP0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-11

bit 10-8

Unimplemented: Read as ‘0’

INT4IP<2:0>: External Interrupt 4 Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

INT3IP<2:0>: External Interrupt 3 Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 3-0

Unimplemented: Read as ‘0’

DS39747F-page 92

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REGISTER 7-29: IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-1

R/W-0

RTCIP2

RTCIP1

RTCIP0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-11

bit 10-8

Unimplemented: Read as ‘0’

RTCIP<2:0>: Real-Time Clock/Calendar Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 7-0

Unimplemented: Read as ‘0’

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REGISTER 7-30: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

CRCIP2

CRCIP1

CRCIP0

U2ERIP2

U2ERIP1

U2ERIP0

bit 15

bit 8

U-0

—

R/W-1

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

U1ERIP2

U1ERIP1

U1ERIP0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

Unimplemented: Read as ‘0’

bit 14-12

CRCIP2:0>: CRC Generator Error Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8

U2ERIP<2:0>: UART2 Error Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

U1ERIP<2:0>: UART1 Error Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 3-0

Unimplemented: Read as ‘0’

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REGISTER 7-31: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER

R-0

U-0

—

R/W-0

U-0

—

R-0

CPUIRQ

VHOLD

ILR3

ILR2

ILR1

ILR0

bit 15

bit 8

U-0

—

R-0

VECNUM6

VECNUM5

VECNUM4

VECNUM3

VECNUM2

VECNUM1

VECNUM0

bit 0

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

CPUIRQ: Interrupt Request from Interrupt Controller CPU bit

1= An interrupt request has occurred but has not yet been Acknowledged by the CPU; this happens

when the CPU priority is higher than the interrupt priority

0= No interrupt request is unacknowledged

bit 14

bit 13

Unimplemented: Read as ‘0’

VHOLD: Vector Number Capture Configuration bit

1= The VECNUM bits contain the value of the highest priority pending interrupt

0= The VECNUM bits contain the value of the last Acknowledged interrupt (i.e., the last interrupt that

has occurred with higher priority than the CPU, even if other interrupts are pending)

bit 12

Unimplemented: Read as ‘0’

bit 11-8

ILR<3:0>: New CPU Interrupt Priority Level bits

1111= CPU Interrupt Priority Level is 15

•

0001= CPU Interrupt Priority Level is 1

0000= CPU Interrupt Priority Level is 0

bit 7

Unimplemented: Read as ‘0’

bit 6-0

VECNUM<6:0>: Pending Interrupt Vector ID bits (pending vector number is VECNUM + 8)

0111111= Interrupt Vector pending is number 135

•

0000001= Interrupt Vector pending is number 9

0000000= Interrupt Vector pending is number 8

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7.4.3

TRAP SERVICE ROUTINE

7.4

Interrupt Setup Procedures

A Trap Service Routine (TSR) is coded like an ISR,

except that the appropriate trap status flag in the

INTCON1 register must be cleared to avoid re-entry

into the TSR.

7.4.1

INITIALIZATION

To configure an interrupt source:

1. Set the NSTDIS Control bit (INTCON1<15>) if

nested interrupts are not desired.

7.4.4

INTERRUPT DISABLE

2. Select the user-assigned priority level for the

interrupt source by writing the control bits in the

appropriate IPCx Control register. The priority

level will depend on the specific application and

type of interrupt source. If multiple priority levels

are not desired, the IPCx register control bits for

all enabled interrupt sources may be

programmed to the same non-zero value.

All user interrupts can be disabled using the following

procedure:

1. Push the current SR value onto the software

stack using the PUSHinstruction.

2. Force the CPU to Priority Level 7 by inclusive

ORing the value OEh with SRL.

To enable user interrupts, the POPinstruction may be

used to restore the previous SR value.

Note: At a device Reset, the IPC registers are

initialized, such that all user interrupt

sources are assigned to Priority Level 4.

Note that only user interrupts with a priority level of 7 or

less can be disabled. Trap sources (Level 8-15) cannot

be disabled.

3. Clear the interrupt flag status bit associated with

the peripheral in the associated IFSx Status

register.

The DISIinstruction provides a convenient way to dis-

able interrupts of Priority Levels 1-6 for a fixed period of

time. Level 7 interrupt sources are not disabled by the

DISI instruction.

4. Enable the interrupt source by setting the inter-

rupt enable control bit associated with the

source in the appropriate IECx Control register.

7.4.2

INTERRUPT SERVICE ROUTINE

The method that is used to declare an ISR and initialize

the IVT with the correct vector address will depend on

the programming language (i.e., ‘C’ or assembler) and

the language development toolsuite that is used to

develop the application. In general, the user must clear

the interrupt flag in the appropriate IFSx register for the

source of interrupt that the ISR handles. Otherwise, the

ISR will be re-entered immediately after exiting the

routine. If the ISR is coded in assembly language, it

must be terminated using a RETFIE instruction to

unstack the saved PC value, SRL value and old CPU

priority level.

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• On-chip 4x PLL to boost internal operating frequency

on select internal and external oscillator sources

8.0

OSCILLATOR

CONFIGURATION

• Software-controllable switching between various

clock sources

Note:

This data sheet summarizes the features of

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. Refer to Section 6. “Oscillator”

(DS39700) in the “PIC24F Family

Reference Manual” for more information.

• Software-controllable postscaler for selective

clocking of CPU for system power savings

• A Fail-Safe Clock Monitor (FSCM) that detects

clock failure and permits safe application recovery

or shutdown

A simplified diagram of the oscillator system is shown

in Figure 8-1.

The oscillator system for PIC24FJ128GA010 family

devices has the following features:

• A total of four external and internal oscillator options

as clock sources, providing 11 different clock modes

FIGURE 8-1:

PIC24FJ128GA010 FAMILY CLOCK DIAGRAM

PIC24FJ128GA010 Family

Primary Oscillator

CLKO

XT, HS, EC

CLKDIV<14:12>

OSC1

OSC2

XTPLL, HSPLL,

ECPLL, FRCPLL

CPU

8 MHz/

4 MHz

4 x PLL

FRC

Oscillator

FRCDIV

Peripherals

8 MHz

(Nominal)

CLKDIV<10:8>

FRC

LPRC

Oscillator

31 kHz (Nominal)

Secondary Oscillator

SOSC

SOSCO

SOSCI

SOSCEN

Enable

Oscillator

Clock Control Logic

Fail-Safe

Clock

Monitor

WDT, PWRT

Clock Source Option

for Other Modules

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8.1

CPU Clocking Scheme

8.2

Oscillator Configuration

The system clock source can be provided by one of

four sources:

The oscillator source (and operating mode) that is

used at a device Power-on Reset event is selected

using Configuration bit settings. The oscillator Config-

uration bit settings are located in the Configuration

registers in the program memory (refer to

Section 24.1 “Configuration Bits” for further

details). The Primary Oscillator Configuration bits,

POSCMD<1:0> (Configuration Word 2<1:0>), and

the Initial Oscillator Select Configuration bits,

FNOSC<2:0> (Configuration Word 2<10:8>), select

the oscillator source that is used at a Power-on Reset.

The FRC primary oscillator with postscaler (FRCDIV)

is the default (unprogrammed) selection. The second-

ary oscillator, or one of the internal oscillators, may be

chosen by programming these bit locations.

• Primary Oscillator (POSC) on the OSC1 and

OSC2 pins

• Secondary Oscillator (SOSC) on the SOSCI and

SOSCO pins

• Fast Internal RC (FRC) Oscillator

• Low-Power Internal RC (LPRC) Oscillator

The primary oscillator and FRC sources have the

option of using the internal 4x PLL. The frequency of

the FRC clock source can optionally be reduced by the

programmable clock divider. The selected clock source

generates the processor and peripheral clock sources.

The processor clock source is divided by two to pro-

duce the internal instruction cycle clock, FCY. In this

document, the instruction cycle clock is also denoted

by FOSC/2. The internal instruction cycle clock, FOSC/2,

can be provided on the OSC2 I/O pin for some

operating modes of the primary oscillator.

The Configuration bits allow users to choose between

the various clock modes, shown in Table 8-1.

8.2.1

CLOCK SWITCHING MODE

CONFIGURATION BITS

The FCKSM Configuration bits (Configuration Word 2<7:6>)

are used to jointly configure device clock switching and

the Fail-Safe Clock Monitor (FSCM). Clock switching is

enabled only when FCKSM1 is programmed (‘0’). The

FSCM is enabled only when FCKSM<1:0> are both

programmed (‘00’).

TABLE 8-1:

CONFIGURATION BIT VALUES FOR CLOCK SELECTION

Oscillator Mode

Oscillator Source

POSCMD<1:0>

FNOSC<2:0>

Note

1, 2

Fast RC Oscillator with Postscaler

(FRCDIV)

Internal

11

111

(Reserved)

Internal

xx

11

110

101

100

1

Low-Power RC Oscillator (LPRC)

Secondary (Timer1) Oscillator

(SOSC)

Secondary

Primary Oscillator (HS) with PLL

Module (HSPLL)

Primary

10

01

00

011

Primary Oscillator (XT) with PLL

Module (XTPLL)

Primary Oscillator (EC) with PLL

Module (ECPLL)

Primary Oscillator (HS)

Primary Oscillator (XT)

Primary Oscillator (EC)

Primary

Internal

10

01

00

11

010

001

Fast RC Oscillator with PLL Module

(FRCPLL)

1

Fast RC Oscillator (FRC)

Internal

11

000

Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit.

2: This is the default oscillator mode for an unprogrammed (erased) device.

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The Clock Divider register (Register 8-2) controls the

features associated with Doze mode, as well as the

postscaler for the FRC oscillator.

8.3

Control Registers

The operation of the oscillator is controlled by three

Special Function Registers:

The FRC Oscillator Tune register (Register 8-3) allows

the user to fine-tune the FRC oscillator over a range of

approximately ±12%. Each increment may adjust the

FRC frequency by varying amounts and may not be

monotonic. The next closest frequency may be multiple

steps apart.

• OSCCON

• CLKDIV

• OSCTUN

The OSCCON register (Register 8-1) is the main con-

trol register for the oscillator. It controls clock source

switching, and allows the monitoring of clock sources.

REGISTER 8-1:

OSCCON: OSCILLATOR CONTROL REGISTER

U-0

—

R-0

U-0

—

R/W-x⁽¹⁾

NOSC2

R/W-x⁽¹⁾

NOSC1

R/W-x⁽¹⁾

NOSC0

COSC2

COSC1

COSC0

bit 15

bit 8

R/SO-0

CLKLOCK

bit 7

U-0

—

R-0⁽²⁾

LOCK

U-0

—

R/CO-0

CF

U-0

—

R/W-0

SOSCEN

OSWEN

bit 0

Legend:

CO = Clearable Only bit

W = Writable bit

SO = Settable Only bit

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

R = Readable bit

-n = Value at POR

‘1’ = Bit is set

bit 15

Unimplemented: Read as ‘0’

bit 14-12

COSC<2:0>: Current Oscillator Selection bits

111= Fast RC Oscillator with Postscaler (FRCDIV)

110= Reserved

101= Low-Power RC Oscillator (LPRC)

100= Secondary Oscillator (SOSC)

011= Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)

010= Primary Oscillator (XT, HS, EC)

001= Fast RC Oscillator with postscaler and PLL module (FRCPLL)

000= Fast RC Oscillator (FRC)

bit 11

Unimplemented: Read as ‘0’

bit 10-8

NOSC<2:0>: New Oscillator Selection bits⁽¹⁾

111= Fast RC Oscillator with Postscaler (FRCDIV)

110= Reserved

101= Low-Power RC Oscillator (LPRC)

100= Secondary Oscillator (SOSC)

011= Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)

010= Primary Oscillator (XT, HS, EC)

001= Fast RC Oscillator with postscaler and PLL module (FRCPLL)

000= Fast RC Oscillator (FRC)

bit 7

bit 6

CLKLOCK: Clock Selection Lock Enable bit

If FSCM is enabled (FCKSM1 = 1):

1= Clock and PLL selections are locked

0= Clock and PLL selections are not locked and may be modified by setting the OSWEN bit

If FSCM is disabled (FCKSM1 = 0):

Clock and PLL selections are never locked and may be modified by setting the OSWEN bit.

Unimplemented: Read as ‘0’

Note 1: Reset values for these bits are determined by the FNOSC Configuration bits.

2: Also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected.

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REGISTER 8-1:

OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED)

bit 5

LOCK: PLL Lock Status bit⁽²⁾

1= PLL module is in lock or PLL module start-up timer is satisfied

0= PLL module is out of lock, PLL start-up timer is running or PLL is disabled

bit 4

bit 3

Unimplemented: Read as ‘0’

CF: Clock Fail Detect bit

1= FSCM has detected a clock failure

0= No clock failure has been detected

bit 2

bit 1

Unimplemented: Read as ‘0’

SOSCEN: 32 kHz Secondary Oscillator (SOSC) Enable bit

1= Enable secondary oscillator

0= Disable secondary oscillator

bit 0

OSWEN: Oscillator Switch Enable bit

1= Initiate an oscillator switch to clock source specified by NOSC<2:0> bits

0= Oscillator switch is complete

Note 1: Reset values for these bits are determined by the FNOSC Configuration bits.

2: Also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected.

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REGISTER 8-2:

CLKDIV: CLOCK DIVIDER REGISTER

R/W-0

ROI

R/W-0

DOZEN⁽¹⁾

R/W-0

R/W-1

DOZE2

DOZE1

DOZE0

RCDIV2

RCDIV1

RCDIV0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

ROI: Recover on Interrupt bit

1= Interrupts clear the DOZEN bit and reset the CPU peripheral clock ratio to 1:1

0= Interrupts have no effect on the DOZEN bit

bit 14-12

DOZE<2:0>: CPU Peripheral Clock Ratio Select bits

111= 1:128

110= 1:64

101= 1:32

100= 1:16

011= 1:8

010= 1:4

001= 1:2

000= 1:1

bit 11

DOZEN: DOZE Enable bit⁽¹⁾

1= DOZE<2:0> bits specify the CPU peripheral clock ratio

0= CPU peripheral clock ratio set to 1:1

bit 10-8

RCDIV<2:0>: FRC Postscaler Select bits

111= 31.25 kHz (divide-by-256)

110= 125 kHz (divide-by-64)

101= 250 kHz (divide-by-32)

100= 500 kHz (divide-by-16)

011= 1 MHz (divide-by-8)

010= 2 MHz (divide-by-4)

001= 4 MHz (divide-by-2)

000= 8 MHz (divide-by-1)

bit 7-0

Unimplemented: Read as ‘0’

Note 1: This bit is automatically cleared when the ROI bit is set and an interrupt occurs.

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REGISTER 8-3:

OSCTUN: FRC OSCILLATOR TUNE REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

U-0

—

R/W-0

TUN5

R/W-0

TUN4

R/W-0

TUN3

R/W-0

TUN2

R/W-0

TUN1

R/W-0

TUN0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-6

bit 5-0

Unimplemented: Read as ‘0’

TUN<5:0>: FRC Oscillator Tuning bits

011111= Maximum frequency deviation

011110=



000001=

000000= Center frequency, oscillator is running at factory calibrated frequency

111111=



100001=

100000= Minimum frequency deviation

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Once the basic sequence is completed, the system

clock hardware responds automatically as follows:

8.4

Clock Switching Operation

With few limitations, applications are free to switch

between any of the four clock sources (POSC, SOSC,

FRC and LPRC) under software control and at any

time. To limit the possible side effects that could result

from this flexibility, PIC24F devices have a safeguard

lock built into the switching process.

1. The clock switching hardware compares the

COSC status bits with the new value of the

NOSC control bits. If they are the same, then the

clock switch is a redundant operation. In this

case, the OSWEN bit is cleared automatically

and the clock switch is aborted.

Note:

Primary oscillator mode has three

different submodes (XT, HS and EC)

which are determined by the POSCMD

Configuration bits. While an application

can switch to and from primary oscillator

mode in software, it cannot switch

between the different primary submodes

without reprogramming the device.

2. If a valid clock switch has been initiated, the

LOCK (OSCCON<5>) and CF (OSCCON<3>)

status bits are cleared.

3. The new oscillator is turned on by the hardware

if it is not currently running. If a crystal oscillator

must be turned on, the hardware will wait until

the OST expires. If the new source is using the

PLL, then the hardware waits until a PLL lock is

detected (LOCK = 1).

8.4.1

ENABLING CLOCK SWITCHING

4. The hardware waits for ten clock cycles from the

new clock source and then performs the clock

switch.

To enable clock switching, the FCKSM1 Configuration bit

in the Flash Configuration Word 2 register must be pro-

grammed to ‘0’. (Refer to Section 24.1 “Configuration

Bits” for further details.) If the FCKSM1 Configuration bit

is unprogrammed (‘1’), the clock switching function and

Fail-Safe Clock Monitor function are disabled. This is the

default setting.

5. The hardware clears the OSWEN bit to indicate a

successful clock transition. In addition, the NOSC

bit values are transferred to the COSC status bits.

6. The old clock source is turned off at this time

with the exception of LPRC (if WDT or FSCM is

enabled) or SOSC (if SOSCEN remains set).

The NOSC control bits (OSCCON<10:8>) do not

control the clock selection when clock switching is dis-

abled. However, the COSC bits (OSCCON<14:12>)

will reflect the clock source selected by the FNOSC

Configuration bits.

Note 1: The processor will continue to execute

code throughout the clock switching

sequence. Timing-sensitive code should

not be executed during this time.

The OSWEN control bit (OSCCON<0>) has no effect

when clock switching is disabled; it is held at ‘0’ at all

times.

2: Direct clock switches between any

primary oscillator mode with PLL and

FRCPLL mode are not permitted. This

applies to clock switches in either direc-

tion. In these instances, the application

must switch to FRC mode as a transition

clock source between the two PLL

modes.

8.4.2

OSCILLATOR SWITCHING

SEQUENCE

At a minimum, performing a clock switch requires this

basic sequence:

1. If

desired,

read

the

COSC

bits

(OSCCON<14:12>) to determine the current

oscillator source.

2. Perform the unlock sequence to allow a write to

the OSCCON register high byte.

3. Write the appropriate value to the NOSC control

bits (OSCCON<10:8>) for the new oscillator

source.

4. Perform the unlock sequence to allow a write to

the OSCCON register low byte.

5. Set the OSWEN bit to initiate the oscillator

switch.

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A recommended code sequence for a clock switch

includes the following:

EXAMPLE 8-1:

BASIC CODE SEQUENCE

FOR CLOCK SWITCHING

1. Disable interrupts during the OSCCON register

unlock and write sequence.

.global __reset

.include "p24fxxxx.inc"

.text

__reset:

2. Execute the unlock sequence for the OSCCON

high byte by writing 78h and 9Ah to

OSCCON<15:8>

instructions.

in

two

back-to-back

;Place the new oscillator selection in W0

;OSCCONH (high byte) Unlock Sequence

DISI #18

3. Write new oscillator source to the NOSC control

bits in the instruction immediately following the

unlock sequence.

PUSH

MOV

w1

w2

w3

4. Execute the unlock sequence for the OSCCON

low byte by writing 46h and 57h to

OSCCON<7:0> in two back-to-back instructions.

#OSCCONH, w1

#0x78, w2

#0x9A, w3

w2, [w1]

w3, [w1]

MOV

5. Set the OSWEN bit in the instruction immediately

following the unlock sequence.

MOV.b

;Set new oscillator selection

MOV.b WREG, OSCCONH

;OSCCONL (low byte) unlock sequence

6. Continue to execute code that is not

clock-sensitive (optional).

7. Invoke an appropriate amount of software delay

(cycle counting) to allow the selected oscillator

and/or PLL to start and stabilize.

MOV

MOV.b

#OSCCONL, w1

#0x46, w2

#0x57, w3

w2, [w1]

8. Check to see if OSWEN is ‘0’. If it is, the switch

was successful. If OSWEN is still set, then

check the LOCK bit to determine the cause of

the failure.

w3, [w1]

;Start oscillator switch operation

BSET OSCCON, #0

POP

.end

w3

w2

w1

The core sequence for unlocking the OSCCON register

and initiating a clock switch is shown in Example 8-1.

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and code execution, but allows peripheral modules to

continue operation. The assembly syntax of the

9.0

POWER-SAVING FEATURES

Note:

This data sheet summarizes the features of

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. Refer to Section 10. Power-

Saving Features” (DS39698) in the

“PIC24F Family Reference Manual” for

more information.

PWRSAVinstruction is shown in Example 9-1.

Sleep and Idle modes can be exited as a result of an

enabled interrupt, WDT time-out or a device Reset.

When the device exits these modes, it is said to

“wake-up”.

Note: SLEEP_MODE and IDLE_MODE are con-

stants defined in the assembler include

file for the selected device.

The PIC24FJ128GA010 family of devices provides the

ability to manage power consumption by selectively

managing clocking to the CPU and the peripherals. In

general, a lower clock frequency and a reduction in the

number of circuits being clocked constitutes lower

consumed power. All PIC24F devices manage power

consumption in four different ways:

9.2.1

SLEEP MODE

Sleep mode has these features:

• The system clock source is shut down. If an

on-chip oscillator is used, it is turned off.

• The device current consumption will be reduced

to a minimum provided that no I/O pin is sourcing

current.

• Clock Frequency

• Instruction-Based Sleep and Idle modes

• Software-Controlled Doze mode

• Selective Peripheral Control in Software

• The Fail-Safe Clock Monitor does not operate

during Sleep mode since the system clock source

is disabled.

Combinations of these methods can be used to selec-

tively tailor an application’s power consumption, while

still maintaining critical application features, such as

timing-sensitive communications.

• The LPRC clock will continue to run in Sleep

mode if the WDT is enabled.

• The WDT, if enabled, is automatically cleared

prior to entering Sleep mode.

9.1

Clock Frequency and Clock

Switching

• Some device features or peripherals may

continue to operate in Sleep mode. This includes

items, such as the input change notification on the

I/O ports, or peripherals that use an external clock

input. Any peripheral that requires the system

clock source for its operation will be disabled in

Sleep mode.

PIC24F devices allow for a wide range of clock

frequencies to be selected under application control. If

the system clock configuration is not locked, users can

choose low-power or high-precision oscillators by simply

changing the NOSC bits. The process of changing a sys-

tem clock during operation, as well as limitations to the

process, are discussed in more detail in Section 8.0

“Oscillator Configuration”.

The device will wake-up from Sleep mode on any of

these events:

• On any interrupt source that is individually

enabled

9.2

Instruction-Based Power-Saving

Modes

• On any form of device Reset

• On a WDT time-out

PIC24F devices have two special power-saving modes

that are entered through the execution of a special

PWRSAVinstruction. Sleep mode stops clock operation

and halts all code execution; Idle mode halts the CPU

On wake-up from Sleep, the processor will restart with

the same clock source that was active when Sleep

mode was entered.

EXAMPLE 9-1:

PWRSAV INSTRUCTION SYNTAX

PWRSAV#SLEEP_MODE ; Put the device into SLEEP mode

PWRSAV#IDLE_MODE ; Put the device into IDLE mode

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It is also possible to use Doze mode to selectively

reduce power consumption in event driven applica-

tions. This allows clock-sensitive functions, such as

synchronous communications, to continue without

interruption while the CPU idles, waiting for something

to invoke an interrupt routine. Enabling the automatic

return to full-speed CPU operation on interrupts is

enabled by setting the ROI bit (CLKDIV<15>). By

default, interrupt events have no effect on Doze mode

operation.

9.2.2

IDLE MODE

Idle mode has these features:

• The CPU will stop executing instructions.

• The WDT is automatically cleared.

• The system clock source remains active. By

default, all peripheral modules continue to operate

normally from the system clock source, but can

also be selectively disabled (see Section 9.4

“Selective Peripheral Module Control”).

• If the WDT or FSCM is enabled, the LPRC will

also remain active.

9.4

Selective Peripheral Module

Control

The device will wake from Idle mode on any of these

events:

Idle and Doze modes allow users to substantially

reduce power consumption by slowing or stopping the

CPU clock. Even so, peripheral modules still remain

clocked, and thus, consume power. There may be

cases where the application needs what these modes

do not provide: the allocation of power resources to

CPU processing with minimal power consumption from

the peripherals.

• Any interrupt that is individually enabled.

• Any device Reset.

• A WDT time-out.

On wake-up from Idle, the clock is re-applied to the

CPU and instruction execution begins immediately,

starting with the instruction following the PWRSAV

instruction or the first instruction in the ISR.

PIC24F devices address this requirement by allowing

peripheral modules to be selectively disabled, reducing

or eliminating their power consumption. This can be

done with two control bits:

9.2.3

INTERRUPTS COINCIDENT WITH

POWER SAVE INSTRUCTIONS

Any interrupt that coincides with the execution of a

PWRSAVinstruction will be held off until entry into Sleep

or Idle mode has completed. The device will then

wake-up from Sleep or Idle mode.

• The Peripheral Enable bit, generically named

“XXXEN”, located in the module’s main control

SFR.

• The Peripheral Module Disable (PMD) bit, generi-

cally named “XXXMD”, located in one of the PMD

Control registers.

9.3

Doze Mode

Generally, changing clock speed and invoking one of

the power-saving modes are the preferred strategies

for reducing power consumption. There may be cir-

cumstances, however, where this is not practical. For

example, it may be necessary for an application to

maintain uninterrupted synchronous communication,

even while it is doing nothing else. Reducing system

clock speed may introduce communication errors,

Both bits have similar functions in enabling or disabling its

associated module. Setting the PMD bit for a module dis-

ables all clock sources to that module, reducing its power

consumption to an absolute minimum. In this state, the

control and status registers associated with the periph-

eral will also be disabled, so writes to those registers will

have no effect and read values will be invalid. Many

peripheral modules have a corresponding PMD bit.

while using

a

power-saving mode may stop

In contrast, disabling a module by clearing its XXXEN

bit disables its functionality, but leaves its registers

available to be read and written to. Power consumption

is reduced, but not by as much as the PMD bit does.

Most peripheral modules have an enable bit;

exceptions include Capture, Compare and RTCC.

communications completely.

Doze mode is a simple and effective alternative method

to reduce power consumption while the device is still

executing code. In this mode, the system clock contin-

ues to operate from the same source and at the same

speed. Peripheral modules continue to be clocked at the

same speed, while the CPU clock speed is reduced.

Synchronization between the two clock domains is

maintained, allowing the peripherals to access the SFRs

while the CPU executes code at a slower rate.

To achieve more selective power savings, peripheral

modules can also be selectively disabled when the

device enters Idle mode. This is done through the

control bit of the generic name format, “XXXIDL”. By

default, all modules that can operate during Idle mode

will do so. Using the disable on Idle feature allows

further reduction of power consumption during Idle

mode, enhancing power savings for extremely critical

power applications.

Doze mode is enabled by setting the DOZEN bit

(CLKDIV<11>). The ratio between peripheral and core

clock speed is determined by the DOZE<2:0> bits

(CLKDIV<14:12>). There are eight possible

configurations, from 1:1 to 1:128, with 1:1 being the

default.

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When a peripheral is enabled and the peripheral is

actively driving an associated pin, the use of the pin as

10.0 I/O PORTS

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

a general purpose output pin is disabled. The I/O pin

may be read, but the output driver for the parallel port

bit will be disabled. If a peripheral is enabled, but the

peripheral is not actively driving a pin, that pin may be

driven by a port.

intended to be a comprehensive refer-

ence source. Refer to Section 12. “I/O

Ports with Peripheral Pin Select (PPS)”

(DS39711) in the “PIC24F Family

Reference Manual” for more information.

All port pins have three registers directly associated

with their operation as digital I/O. The Data Direction

register (TRISx) determines whether the pin is an input

or an output. If the data direction bit is a ‘1’, then the pin

is an input. All port pins are defined as inputs after a

Reset. Reads from the latch (LATx), read the latch.

Writes to the latch, write the latch. Reads from the port

(PORTx), read the port pins, while writes to the port

pins, write the latch.

All of the device pins (except VDD, VSS, MCLR and

OSC1/CLKI) are shared between the peripherals and

the parallel I/O ports. All I/O input ports feature Schmitt

Trigger inputs for improved noise immunity.

10.1 Parallel I/O (PIO) Ports

A parallel I/O port that shares a pin with a peripheral is,

in general, subservient to the peripheral. The periph-

eral’s output buffer data and control signals are

provided to a pair of multiplexers. The multiplexers

select whether the peripheral or the associated port

has ownership of the output data and control signals of

the I/O pin. The logic also prevents “loop through”, in

which a port’s digital output can drive the input of a

peripheral that shares the same pin. Figure 10-1 shows

how ports are shared with other peripherals and the

associated I/O pin to which they are connected.

Any bit and its associated data and control registers

that are not valid for a particular device will be

disabled. That means the corresponding LATx and

TRISx registers, and the port pin will read as zeros.

When a pin is shared with another peripheral or func-

tion that is defined as an input only, it is nevertheless,

regarded as a dedicated port because there is no

other competing source of outputs. An example is the

INT4 pin.

FIGURE 10-1:

BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE

Peripheral Module

Output Multiplexers

Peripheral Input Data

Peripheral Module Enable

I/O

Peripheral Output Enable

Peripheral Output Data

1

0

Output Enable

Output Data

1

0

PIO Module

Read TRIS

Data Bus

WR TRIS

D

Q

I/O Pin

CK

TRIS Latch

D

Q

WR LAT +

WR PORT

CK

Data Latch

Read LAT

Input Data

Read PORT

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10.1.1

OPEN-DRAIN CONFIGURATION

10.2.2

ANALOG INPUT PINS AND

VOLTAGE CONSIDERATIONS

In addition to the PORT, LAT and TRIS registers for

data control, each port pin can also be individually con-

figured for either digital or open-drain output. This is

controlled by the Open-Drain Control register, ODCx,

associated with each port. Setting any of the bits con-

figures the corresponding pin to act as an open-drain

output.

The voltage tolerance of pins used as device inputs is

dependent on the pin’s input function. Pins that are

used as digital only inputs are able to handle DC volt-

ages up to 5.5V, a level typical for digital logic circuits.

In contrast, pins that also have analog input functions

of any kind can only tolerate voltages up to VDD. On

these pins, voltage excursions beyond VDD are always

to be avoided. Table 10-1 summarizes the input capa-

bilities. Refer to Section 27.1 “DC Characteristics”

for more details.

The open-drain feature allows the generation of

outputs higher than VDD (e.g., 5V) on any desired

digital only pins by using external pull-up resistors. The

maximum open-drain voltage allowed is the same as

the maximum VIH specification.

Note:

For easy identification, the pin diagrams at

the beginning of this data sheet also indi-

cate 5.5V tolerant pins with dark grey

shading.

10.2 Configuring Analog Port Pins

The use of the AD1PCFG and TRIS registers control

the operation of the A/D port pins. The port pins that are

desired as analog inputs must have their correspond-

ing TRIS bit set (input). If the TRIS bit is cleared

(output), the digital output level (VOH or VOL) will be

converted.

TABLE 10-1: INPUT VOLTAGE LEVELS⁽¹⁾

Tolerated

Port or Pin

Description

Input

PORTA<10:9>

PORTB<15:0>

PORTC<15:12>

PORTA<15:14>

PORTA<7:0>

PORTC<4:1>

PORTD<15:0>

PORTE<9:0>

PORTF<13:12>

PORTF<8:0>

PORTG<15:12>

PORTG<9:6>

PORTG<3:0>

VDD

Only VDD input

levels are tolerated.

When reading the PORT register, all pins configured as

analog input channels will read as cleared (a low level).

Pins configured as digital inputs will not convert an

analog input. Analog levels on any pin that is defined as

a digital input (including the ANx pins) may cause the

input buffer to consume current that exceeds the

device specifications.

5.5V

Tolerates input

levels above VDD,

useful for most

standard logic.

10.2.1

I/O PORT WRITE/READ TIMING

One instruction cycle is required between a port

direction change or port write operation and a read

operation of the same port. Typically this instruction

would be a NOP.

Note 1: Not all port pins shown here are imple-

mented on 64-pin and 80-pin devices.

Refer to Section 1.0 “Device Overview”

to confirm which ports are available in

specific devices.

EXAMPLE 10-1:

PORT WRITE/READ EXAMPLE

MOV

NOP

0xFF00, W0

W0, TRISBB

; Configure PORTB<15:8> as inputs

; and PORTB<7:0> as outputs

; Delay 1 cycle

btss PORTB, #13

; Next Instruction

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Each CN pin also has a weak pull-up connected to it.

The pull-ups act as a current source that is connected

10.3 Input Change Notification

The input change notification function of the I/O ports

allows the PIC24FJ128GA010 family of devices to gen-

erate interrupt requests to the processor in response to

a Change-of-State (COS) on selected input pins. This

feature is capable of detecting input Change-of-States,

even in Sleep mode, when the clocks are disabled.

Depending on the device pin count, there are up to

22 external signals (CN0 through CN21) that may be

selected (enabled) for generating an interrupt request

on a Change-of-State.

to the pin and eliminate the need for external resistors

when push button or keypad devices are connected.

The pull-ups are enabled separately using the CNPU1

and CNPU2 registers, which contain the control bits for

each of the CN pins. Setting any of the control bits

enables the weak pull-ups for the corresponding pins.

When the internal pull-up is selected, the pin pulls up to

VDD – 0.7V (typical). Make sure that there is no external

pull-up source when the internal pull-ups are enabled, as

the voltage difference can cause a current path.

There are four control registers associated with the CN

module. The CNEN1 and CNEN2 registers contain the

interrupt enable control bits for each of the CN input

pins. Setting any of these bits enables a CN interrupt

for the corresponding pins.

Note:

Pull-ups on Change Notification (CN) pins

should always be disabled whenever the

port pin is configured as a digital output.

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NOTES:

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Figure 11-1 presents a block diagram of the 16-bit timer

module.

11.0 TIMER1

Note:

This data sheet summarizes the features of

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. Refer to Section 14. “Timers”

(DS39704) in the “PIC24F Family

Reference Manual” for more information.

To configure Timer1 for operation:

1. Set the TON bit (= 1).

2. Select the timer prescaler ratio using the

TCKPS<1:0> bits.

3. Set the Clock and Gating modes using the TCS

and TGATE bits.

The Timer1 module is a 16-bit timer which can serve as

the time counter for the Real-Time Clock (RTC) or

operate as a free-running, interval timer/counter.

Timer1 can operate in three modes:

4. Set or clear the TSYNC bit to configure

synchronous or asynchronous operation.

5. Load the timer period value into the PR1

register.

• 16-Bit Timer

6. If interrupts are required, set the Timer1 Inter-

rupt Enable bit, T1IE. Use the priority bits,

T1IP<2:0>, to set the interrupt priority.

• 16-Bit Synchronous Counter

• 16-Bit Asynchronous Counter

Timer1 also supports these features:

• Timer gate operation

• Selectable prescaler settings

• Timer operation during CPU Idle and Sleep

modes

• Interrupt on 16-bit Period register match or falling

edge of the external gate signal

FIGURE 11-1:

16-BIT TIMER1 MODULE BLOCK DIAGRAM

TCKPS<1:0>

TON

2

SOSCO/

1x

01

00

T1CK

Prescaler

1, 8, 64, 256

Gate

Sync

SOSCEN

SOSCI

TCY

TGATE

TCS

TGATE

1

0

Q

D

Set T1IF

CK

0

Reset

Equal

TMR1

Sync

1

TSYNC

Comparator

PR1

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REGISTER 11-1: T1CON: TIMER1 CONTROL REGISTER

R/W-0

TON

U-0

—

R/W-0

TSIDL

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

R/W-0

U-0

—

R/W-0

TCS

U-0

—

TGATE

TCKPS1

TCKPS0

TSYNC

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

TON: Timer1 On bit

1= Starts 16-bit Timer1

0= Stops 16-bit Timer1

bit 14

bit 13

Unimplemented: Read as ‘0’

TSIDL: Stop in Idle Mode bit

1= Discontinues module operation when device enters Idle mode

0= Continues module operation in Idle mode

bit 12-7

bit 6

Unimplemented: Read as ‘0’

TGATE: Timer1 Gated Time Accumulation Enable bit

When TCS = 1:

This bit is ignored.

When TCS = 0:

1= Gated time accumulation is enabled

0= Gated time accumulation is disabled

bit 5-4

TCKPS<1:0>: Timer1 Input Clock Prescale Select bits

11= 1:256

10= 1:64

01= 1:8

00= 1:1

bit 3

bit 2

Unimplemented: Read as ‘0’

TSYNC: Timer1 External Clock Input Synchronization Select bit

When TCS = 1:

1= Synchronizes external clock input

0= Does not synchronize external clock input

When TCS = 0:

This bit is ignored.

bit 1

bit 0

TCS: Timer1 Clock Source Select bit

1= External clock from pin, T1CK (on the rising edge)

0= Internal clock (FOSC/2)

Unimplemented: Read as ‘0’

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To configure Timer2/3 or Timer4/5 for 32-bit operation:

12.0 TIMER2/3 AND TIMER4/5

1. Set the T32 bit (T2CON<3> or T4CON<3> = 1).

Note:

This data sheet summarizes the features of

2. Select the prescaler ratio for Timer2 or Timer4

using the TCKPS<1:0> bits.

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. Refer to Section 14. “Timers”

(DS39704) in the “PIC24F Family

Reference Manual” for more information.

3. Set the Clock and Gating modes using the TCS

and TGATE bits.

4. Load the timer period value. PR3 (or PR5) will

contain the most significant word of the value,

while PR2 (or PR4) contains the least significant

word.

The Timer2/3 and Timer4/5 modules are 32-bit timers,

which can also be configured as four independent, 16-bit

timers with selectable operating modes.

5. If interrupts are required, set the interrupt enable

bit, T3IE or T5IE. Use the interrupt priority bits,

T3IP<2:0> or T5IP<2:0>, to set the interrupt pri-

ority. Note that while Timer2 or Timer4 controls

the timer, the interrupt appears as a Timer3 or

Timer5 interrupt.

As a 32-bit timer, Timer2/3 and Timer4/5 operate in

three modes:

• Two Independent 16-Bit Timers (Timer2 and

Timer3) with All 16-Bit Operating modes

• Single 32-Bit Timer

6. Set the TON bit (= 1).

• Single 32-Bit Synchronous Counter

The timer value, at any point, is stored in the register

pair: TMR3:TMR2 (or TMR5:TMR4). TMR3 (TMR5)

always contains the most significant word of the count,

while TMR2 (TMR4) contains the least significant word.

They also support these features:

• Timer Gate Operation

• Selectable Prescaler Settings

• Timer Operation During Idle and Sleep modes

• Interrupt on a 32-Bit Period Register Match

• A/D Event Trigger (Timer2/3 only)

To configure any of the timers for individual 16-bit

operation:

1. Clear the T32 bit corresponding to that timer

(T2CON<3> for Timer2 and Timer3 or

T4CON<3> for Timer4 and Timer5).

Individually, all four of the 16-bit timers can function as

synchronous timers or counters. They also offer the

features listed above, except for the A/D Event Trigger;

this is implemented only with Timer3. The operating

modes and enabled features are determined by setting

the appropriate bit(s) in the T2CON, T3CON, T4CON

and T5CON registers. T2CON and T4CON are shown

in generic form in Register 12-1; T3CON and T5CON

are shown in Register 12-2.

2. Select the timer prescaler ratio using the

TCKPS<1:0> bits.

3. Set the Clock and Gating modes using the TCS

and TGATE bits.

4. Load the timer period value into the PRx register.

5. If interrupts are required, set the interrupt enable

bit, TxIE; use the priority bits, TxIP<2:0>, to set

the interrupt priority.

For 32-bit timer/counter operation, Timer2 and Timer4

are the least significant word; Timer3 and Timer4 are

the most significant word of the 32-bit timers.

6. Set the TON bit (TxCON<15> = 1).

Note:

For 32-bit operation, T3CON and T5CON

control bits are ignored. Only T2CON and

T4CON control bits are used for setup and

control. Timer2 and Timer4 clock and gate

inputs are utilized for the 32-bit timer

modules, but an interrupt is generated

with the Timer3 or Timer5 interrupt flags.

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FIGURE 12-1:

TIMER2/3 AND TIMER4/5 (32-BIT) BLOCK DIAGRAM

TCKPS<1:0>

2

TON

T2CK

(T4CK)

1x

01

00

Prescaler

1, 8, 64, 256

Gate

Sync

TCY

TGATE

TCS

1

0

Q

D

Set T3IF (T5IF)

Q

CK

PR3

PR2

(PR5)

(PR4)

A/D Event Trigger*

Equal

MSB

Comparator

LSB

TMR2

(TMR4)

TMR3

(TMR5)

Sync

Reset

16

Read TMR2 (TMR4)

Write TMR2 (TMR4)

16

TMR3HLD

(TMR5HLD)

Data Bus<15:0>

Note: The 32-bit Timer Configuration bit, T32, must be set for 32-bit timer/counter operation. All control bits are

respective to the T2CON and T4CON registers.

*

The A/D Event Trigger is only available on Timer2/3.

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FIGURE 12-2:

TIMER2 AND TIMER4 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM

TCKPS<1:0>

TON

2

T2CK

(T4CK)

1x

01

00

Prescaler

1, 8, 64, 256

Gate

Sync

TGATE

TCS

TCY

TGATE

Q

D

1

0

Set T2IF (T4IF)

Q

CK

Reset

Equal

TMR2 (TMR4)

Sync

Comparator

PR2 (PR4)

FIGURE 12-3:

TIMER3 AND TIMER5 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM

TCKPS<1:0>

2

TON

T3CK

(T5CK)

1x

01

00

Sync

Prescaler

1, 8, 64, 256

TGATE

TCS

TCY

TGATE

Q

D

1

0

Set T3IF (T5IF)

CK

Reset

Equal

TMR3 (TMR5)

A/D Event Trigger*

Comparator

PR3 (PR5)

*

The A/D Event Trigger is available only on Timer2/3.

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REGISTER 12-1: TxCON: TIMER2 AND TIMER4 CONTROL REGISTER

R/W-0

TON

U-0

—

R/W-0

TSIDL

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

R/W-0

T32⁽¹⁾

U-0

—

R/W-0

TCS

U-0

—

TGATE

TCKPS1

TCKPS0

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

TON: Timerx On bit

When TxCON<3> = 1:

1= Starts 32-bit Timerx/y

0= Stops 32-bit Timerx/y

When TxCON<3> = 0:

1= Starts 16-bit Timerx

0= Stops 16-bit Timerx

bit 14

bit 13

Unimplemented: Read as ‘0’

TSIDL: Stop in Idle Mode bit

1= Discontinues module operation when the device enters Idle mode

0= Continues module operation in Idle mode

bit 12-7

bit 6

Unimplemented: Read as ‘0’

TGATE: Timerx Gated Time Accumulation Enable bit

When TCS = 1:

This bit is ignored.

When TCS = 0:

1= Gated time accumulation is enabled

0= Gated time accumulation is disabled

bit 5-4

bit 3

TCKPS<1:0>: Timer2 Input Clock Prescale Select bits

11= 1:256

10= 1:64

01= 1:8

00= 1:1

T32: 32-Bit Timer Mode Select bit⁽¹⁾

1= Timerx and Timery form a single 32-bit timer

0= Timerx and Timery act as two 16-bit timers

bit 2

bit 1

Unimplemented: Read as ‘0’

TCS: Timerx Clock Source Select bit

1= External clock from pin, TxCK (on the rising edge)

0= Internal clock (FOSC/2)

bit 0

Unimplemented: Read as ‘0’

Note 1: In 32-bit mode, the T3CON or T5CON control bits do not affect 32-bit timer operation.

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REGISTER 12-2: TyCON: TIMER3 AND TIMER5 CONTROL REGISTER

R/W-0

TON⁽¹⁾

U-0

—

R/W-0

TSIDL⁽¹⁾

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

R/W-0

TGATE⁽¹⁾

R/W-0

TCKPS1⁽¹⁾TCKPS0⁽¹⁾

R/W-0

U-0

—

U-0

—

R/W-0

TCS⁽¹⁾

U-0

—

bit 7

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

TON: Timery On bit⁽¹⁾

1= Starts 16-bit Timery

0= Stops 16-bit Timery

bit 14

bit 13

Unimplemented: Read as ‘0’

TSIDL: Stop in Idle Mode bit⁽¹⁾

1= Discontinues module operation when the device enters Idle mode

0= Continues module operation in Idle mode

bit 12-7

bit 6

Unimplemented: Read as ‘0’

TGATE: Timery Gated Time Accumulation Enable bit⁽¹⁾

When TCS = 1:

This bit is ignored.

When TCS = 0:

1= Gated time accumulation is enabled

0= Gated time accumulation is disabled

bit 5-4

TCKPS<1:0>: Timery Input Clock Prescale Select bits⁽¹⁾

11= 1:256

10= 1:64

01= 1:8

00= 1:1

bit 3-2

bit 1

Unimplemented: Read as ‘0’

TCS: Timery Clock Source Select bit⁽¹⁾

1= External clock from pin, TyCK (on the rising edge)

0= Internal clock (FOSC/2)

bit 0

Unimplemented: Read as ‘0’

Note 1: When 32-bit operation is enabled (T2CON<3> = 1), these bits have no effect on Timery operation; all timer

functions are set through T2CON.

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NOTES:

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• Capture timer value on every fourth rising edge of

input, applied at the ICx pin

13.0 INPUT CAPTURE

Note:

This data sheet summarizes the features of

this group of PIC24F devices. It is not

• Capture timer value on every 16th rising edge of

input, applied at the ICx pin

intended to be a comprehensive reference

source. Refer to Section 15. “Input Cap-

ture” (DS39701) in the “PIC24F Family

Reference Manual” for more information.

• Capture timer value on every rising and every

falling edge of input, applied at the ICx pin

• Device wake-up from capture pin during CPU

Sleep and Idle modes

The input capture module has multiple operating

modes, which are selected via the ICxCON register.

The operating modes include:

The input capture module has a four-level FIFO buffer.

The number of capture events required to generate a

CPU interrupt can be selected by the user.

• Capture timer value on every falling edge of input,

applied at the ICx pin

• Capture timer value on every rising edge of input,

applied at the ICx pin

FIGURE 13-1:

INPUT CAPTURE BLOCK DIAGRAM

From 16-Bit Timers

TMRy

TMRx

16

ICTMR

(ICxCON<7>)

1

0

Prescaler

Counter

(1, 4, 16)

FIFO

R/W

Logic

Edge Detection Logic

and

Clock Synchronizer

ICx Pin

ICM<2:0> (ICxCON<2:0>)

Mode Select

3

ICOV, ICBNE (ICxCON<4:3>)

ICI<1:0>

ICxBUF

Interrupt

Logic

ICxCON

System Bus

Set Flag ICxIF

(in IFSx Register)

Note: An ‘x’ in a signal, register or bit name denotes the number of the capture channel.

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13.1 Input Capture Registers

REGISTER 13-1: ICxCON: INPUT CAPTURE x CONTROL REGISTER

U-0

—

U-0

—

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

ICSIDL

bit 15

bit 8

R/W-0

ICTMR⁽¹⁾

R/W-0

ICI1

R/W-0

ICI0

R-0, HC

ICOV

R/W-0, HC

ICBNE

R/W-0

ICM2

R/W-0

ICM1

R/W-0

ICM0

bit 7

bit 0

Legend:

HC = Hardware Clearable bit

W = Writable bit

R = Readable bit

-n = Value at POR

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

‘1’ = Bit is set

bit 15-14

bit 13

Unimplemented: Read as ‘0’

ICSIDL: Input Capture x Module Stop in Idle Control bit

1= Input capture module will Halt in CPU Idle mode

0= Input capture module will continue to operate in CPU Idle mode

bit 12-8

bit 7

Unimplemented: Read as ‘0’

ICTMR: Input Capture x Timer Select bit⁽¹⁾

1= TMR2 contents are captured on capture event

0= TMR3 contents are captured on capture event

bit 6-5

ICI<1:0>: Select Number of Captures per Interrupt bits

11= Interrupt on every fourth capture event

10= Interrupt on every third capture event

01= Interrupt on every second capture event

00= Interrupt on every capture event

bit 4

ICOV: Input Capture x Overflow Status Flag bit (read-only)

1= Input capture overflow occurred

0= No input capture overflow occurred

bit 3

ICBNE: Input Capture x Buffer Empty Status bit (read-only)

1= Input capture buffer is not empty, at least one more capture value can be read

0= Input capture buffer is empty

bit 2-0

ICM<2:0>: Input Capture x Mode Select bits

111= Input capture functions as an interrupt pin only when the device is in Sleep or Idle mode (rising

edge detect only, all other control bits are not applicable)

110= Unused (module is disabled)

101= Capture mode, every 16th rising edge

100= Capture mode, every 4th rising edge

011= Capture mode, every rising edge

010= Capture mode, every falling edge

001= Capture mode, every edge (rising and falling); ICI<1:0> does not control interrupt generation

for this mode

000= Input capture module is turned off

Note 1: Timer selections may vary. Refer to the specific device data sheet for details.

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• Dual Compare Match mode generating:

- Single Output Pulse mode

14.0 OUTPUT COMPARE

Note:

This data sheet summarizes the features of

this group of PIC24F devices. It is not

- Continuous Output Pulse mode

• Simple Pulse-Width Modulation mode:

- with Fault protection input

intended to be a comprehensive reference

source. Refer to Section 16. “Output

Compare” (DS39706) in the “PIC24F

Family Reference Manual” for more

information.

- without Fault protection input

14.2 Setup for Single Output Pulse

Generation

14.1 MODES OF OPERATION

When the OCM control bits (OCxCON<2:0>) are set to

‘100’, the selected output compare channel initializes

the OCx pin to the low state and generates a single

output pulse.

Each output compare module has the following modes

of operation:

• Single Compare Match mode

FIGURE 14-1:

OUTPUT COMPARE MODULE BLOCK DIAGRAM

Set Flag bit

(1)

OCxIF

(1)

OCxRS

Output

Logic

(1)

S

R

Q

OCxR

OCx

Output Enable

3

OCM<2:0>

Mode Select

(2)

Comparator

OCFA or OCFB

0

OCTSEL

1

0

1

16

Period Match Signals

from Time Bases

(see Note 3)

TMR Register Inputs

from Time Bases

(see Note 3)

Note 1: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels, 1

through 5.

2: OCFA pin controls OC1-OC4 channels; OCFB pin controls OC5.

3: Each output compare channel can use either Timer2 or Timer3.

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To generate a single output pulse, the following steps

14.3 Setup for Continuous Output

are required (these steps assume the timer source is

initially turned off, but this is not a requirement for the

module operation):

Pulse Generation

When the OCM control bits (OCxCON<2:0>) are set to

‘101’, the selected output compare channel initializes

the OCx pin to the low state, and generates output

pulses on each and every compare match event.

1. Determine the instruction clock cycle time. Take

into account the frequency of the external clock

to the timer source (if one is used) and the timer

prescaler settings.

For the user to configure the module for the generation

of a continuous stream of output pulses, the following

steps are required (these steps assume the timer

source is initially turned off, but this is not a requirement

for the module operation):

2. Calculate time to the rising edge of the output

pulse relative to the TMRy start value (0000h).

3. Calculate the time to the falling edge of the pulse

based on the desired pulse width and the time to

the rising edge of the pulse.

1. Determine the instruction clock cycle time. Take

into account the frequency of the external clock

to the timer source (if one is used) and the timer

prescaler settings.

4. Write the values computed in Steps 2 and 3

above into the Compare register, OCxR, and the

Secondary

Compare

register,

OCxRS,

respectively.

2. Calculate the time to the rising edge of the output

pulse relative to the TMRy start value (0000h).

5. Set the Timer Period register, PRy, to a value

equal to or greater than the value in OCxRS, the

Secondary Compare register.

3. Calculate the time to the falling edge of the pulse,

based on the desired pulse width and the time to

the rising edge of the pulse.

6. Set the OCM bits to ‘100’ and the OCTSEL

(OCxCON<3>) bit to the desired timer source.

The OCx pin state will now be driven low.

4. Write the values computed in Step 2 and 3

above, into the Compare register, OCxR, and

the Secondary Compare register, OCxRS,

respectively.

7. Set the TON (TyCON<15>) bit to ‘1’, which

enables the compare time base to count.

8. Upon the first match between TMRy and OCxR,

the OCx pin will be driven high.

5. Set the Timer Period register, PRy, to a value,

equal to or greater than, the value in OCxRS, the

Secondary Compare register.

9. When the incrementing timer, TMRy, matches the

Secondary Compare register, OCxRS, the

second and trailing edge (high-to-low) of the pulse

is driven onto the OCx pin. No additional pulses

are driven onto the OCx pin and it remains at low.

As a result of the second compare match event,

the OCxIF interrupt flag bit is set which will result

in an interrupt, if it is enabled, by setting the

OCxIE bit. For further information on periph-

eral interrupts, refer to Section 7.0 “Interrupt

Controller”.

6. Set the OCM bits to ‘101’ and the OCTSEL bit to

the desired timer source. The OCx pin state will

now be driven low.

7. Enable the compare time base by setting the TON

(TyCON<15>) bit to ‘1’.

8. Upon the first match between TMRy and OCxR,

the OCx pin will be driven high.

9. When the compare time base, TMRy, matches

the Secondary Compare register, OCxRS, the

second and trailing edge (high-to-low) of the pulse

is driven onto the OCx pin.

10. To initiate another single pulse output, change the

Timer and Compare register settings, if needed,

and then issue a write to set the OCM bits to ‘100’.

Disabling and re-enabling of the timer, and clear-

ing the TMRy register are not required, but may

be advantageous for defining a pulse from a

known event time boundary.

10. As a result of the second compare match event,

the OCxIF interrupt flag bit is set.

11. When the compare time base and the value in its

respective Period register match, the TMRy

register resets to 0x0000and resumes counting.

The output compare module does not have to be dis-

abled after the falling edge of the output pulse. Another

pulse can be initiated by rewriting the value of the

OCxCON register.

12. Steps 8 through 11 are repeated and a continuous

stream of pulses is generated indefinitely. The

OCxIF flag is set on each OCxRS-TMRy compare

match event.

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EQUATION 14-1: CALCULATING THE PWM

PERIOD⁽¹⁾

14.4 Pulse-Width Modulation Mode

The following steps should be taken when configuring

the output compare module for PWM operation:

PWM Period = [(PRy) + 1] • TCY • (Timer Prescale Value)

where:

1. Set the PWM period by writing to the selected

Timer Period register (PRy).

PWM Frequency = 1/[PWM Period]

2. Set the PWM duty cycle by writing to the OCxRS

register.

Note 1: Based on TCY = TOSC * 2; Doze mode and

PLL are disabled.

3. Write the OCxR register with the initial duty

cycle.

Note: A PRy value of N will produce a PWM

period of N + 1 time base count cycles.

For example, a value of 7 written into the

PRy register will yield a period consisting

of 8 time base cycles.

4. Enable interrupts, if required, for the timer and

output compare modules. The output compare

interrupt is required for PWM Fault pin

utilization.

5. Configure the output compare module for one of

two PWM operation modes by writing to the

Output Compare mode bits, OCM<2:0>

(OCxCON<2:0>).

14.4.2

PWM DUTY CYCLE

The PWM duty cycle is specified by writing to the

OCxRS register. The OCxRS register can be written to

at any time, but the duty cycle value is not latched into

OCxR until a match between PRy and TMRy occurs

(i.e., the period is complete). This provides a double

buffer for the PWM duty cycle and is essential for glitch-

less PWM operation. In the PWM mode, OCxR is a

read-only register.

6. Set the TMRy prescale value and enable the

time base by setting TON (TxCON<15>) = 1.

Note: The OCxR register should be initialized

before the output compare module is first

enabled. The OCxR register becomes a

Read-Only Duty Cycle register when the

module is operated in the PWM modes.

The value held in OCxR will become the

PWM duty cycle for the first PWM period.

The contents of the Duty Cycle Buffer

register, OCxRS, will not be transferred

into OCxR until a time base period match

occurs.

Some important boundary parameters of the PWM duty

cycle include:

• If the Duty Cycle register, OCxR, is loaded with

0000h, the OCx pin will remain low (0% duty cycle).

• If OCxR is greater than PRy (Timer Period register),

the pin will remain high (100% duty cycle).

• If OCxR is equal to PRy, the OCx pin will be low

for one time base count value and high for all

other count values.

14.4.1

PWM PERIOD

The PWM period is specified by writing to PRy, the

Timer Period register. The PWM period can be

calculated using Equation 14-1.

See Example 14-1 for PWM mode timing details.

Table 14-1 shows example PWM frequencies and

resolutions for a device operating at 10 MIPS.

EQUATION 14-2: CALCULATION FOR MAXIMUM PWM RESOLUTION⁽¹⁾

FCY

log₁₀

(

)

FPWM • (Timer Prescale Value)

bits

Maximum PWM Resolution (bits) =

log₁₀(2)

Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.

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EXAMPLE 14-1:

PWM PERIOD AND DUTY CYCLE CALCULATIONS⁽¹⁾

1. Find the Period register value for a desired PWM frequency of 52.08 kHz, where FOSC = 8 MHz with PLL (32 MHz device clock

rate) and a Timer2 prescaler setting of 1:1.

TCY = 2/FOSC = 62.5 ns

PWM Period = 1/PWM Frequency = 1/52.08 kHz = 19.2 s

PWM Period = (PR2 + 1) • TCY • (Timer2 Prescale Value)

19.2 s

PR2

= (PR2 + 1) • 62.5 ns • 1

= 306

2. Find the maximum resolution of the duty cycle that can be used with a 52.08 kHz frequency and a 32 MHz device clock rate:

PWM Resolution = log₁₀(FCY/FPWM)/log₁₀2) bits

= (log₁₀(16 MHz/52.08 kHz)/log₁₀2) bits

= 8.3 bits

Note 1: Based on TCY = TOSC * 2; Doze mode and PLL are disabled.

TABLE 14-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 4 MIPS (FCY = 4 MHz)⁽¹⁾

PWM Frequency

7.6 Hz

61 Hz

122 Hz

977 Hz

3.9 kHz

31.3 kHz

125 kHz

Timer Prescaler Ratio

Period Register Value

Resolution (bits)

8

1

FFFFh

16

1

007Fh

7

1

001Fh

5

FFFFh

16

7FFFh

15

0FFFh

12

03FFh

10

Note 1: Based on TCY = TOSC * 2; Doze mode and PLL are disabled.

TABLE 14-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 16 MIPS (FCY = 16 MHz)⁽¹⁾

PWM Frequency

30.5 Hz

244 Hz

488 Hz

3.9 kHz

15.6 kHz

125 kHz

500 kHz

Timer Prescaler Ratio

Period Register Value

Resolution (bits)

8

1

FFFFh

16

1

007Fh

7

1

001Fh

5

FFFFh

16

7FFFh

15

0FFFh

12

03FFh

10

Note 1: Based on TCY = TOSC * 2; Doze mode and PLL are disabled.

DS39747F-page 124

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REGISTER 14-1: OCxCON: OUTPUT COMPARE x CONTROL REGISTER

U-0

—

U-0

—

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

OCSIDL

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R-0, HC

OCFLT⁽¹⁾

R/W-0

OCTSEL⁽¹⁾

R/W-0

OCM2

R/W-0

OCM1

R/W-0

OCM0

bit 7

bit 0

Legend:

HC = Hardware Clearable bit

W = Writable bit

R = Readable bit

-n = Value at POR

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

‘1’ = Bit is set

bit 15-14

bit 13

Unimplemented: Read as ‘0’

OCSIDL: Stop Output Compare x Module Stop in Idle Control bit

1= Output capture x will halt in CPU Idle mode

0= Output capture x will continue to operate in CPU Idle mode

bit 12-5

bit 4

Unimplemented: Read as ‘0’

OCFLT: PWM Fault Condition Status bit⁽¹⁾

1= PWM Fault condition has occurred (cleared in HW only)

0= No PWM Fault condition has occurred (this bit is only used when OCM<2:0> = 111)

bit 3

OCTSEL: Output Compare x Timer Select bit⁽¹⁾

1= Timer3 is the clock source for output Compare x

0= Timer2 is the clock source for output Compare x

bit 2-0

OCM<2:0>: Output Compare x Mode Select bits

111= PWM mode on OCx, Fault pin is enabled⁽²⁾

110= PWM mode on OCx, Fault pin is disabled⁽²⁾

101= Initialize the OCx pin low, generate continuous output pulses on the OCx pin

100= Initialize the OCx pin low, generate single output pulse on the OCx pin

011= Compare event toggles OCx pin

010= Initialize the OCx pin high, a compare event forces the OCx pin low

001= Initialize the OCx pin low, a compare event forces the OCx pin high

000= Output compare channel is disabled

Note 1: Refer to the device data sheet for specific time bases available to the output compare module.

2: The OCFA pin controls the OC1-OC4 channels; OCFB pin controls the OC5 channel.

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NOTES:

DS39747F-page 126

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To set up the SPI module for the Standard Master mode

of operation:

15.0 SERIAL PERIPHERAL

INTERFACE (SPI)

1. If using interrupts:

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

a) Clear the SPIxIF bit in the respective IFSx

register.

intended to be a comprehensive refer-

ence source. Refer to Section 23. “Serial

Peripheral Interface (SPI)” (DS39699) in

the “PIC24F Family Reference Manual”

for more information.

b) Set the SPIxIE bit in the respective IECx

register.

c) Write the SPIxIP bits in the respective IPCx

register to set the interrupt priority.

2. Write the desired settings to the SPIxCON

The Serial Peripheral Interface (SPI) module is a

synchronous serial interface useful for communicating

with other peripheral or microcontroller devices. These

peripheral devices may be serial EEPROMs, shift reg-

isters, display drivers, A/D Converters, etc. The SPI

module is compatible with SPI and SIOP interfaces

from Motorola^®.

register with MSTEN (SPIxCON1<5>) = 1.

3. Clear the SPIROV bit (SPIxSTAT<6>).

4. Enable SPI operation by setting the SPIEN bit

(SPIxSTAT<15>).

5. Write the data to be transmitted to the SPIxBUF

register. Transmission (and reception) will start

as soon as data is written to the SPIxBUF

register.

The module supports operation in two buffer modes. In

Standard mode, data is shifted through a single serial

buffer. In Enhanced Buffer mode, data is shifted

through an 8-level FIFO buffer.

To set up the SPI module for the Standard Slave mode

of operation:

1. Clear the SPIxBUF register.

2. If using interrupts:

Note:

Do not perform read-modify-write opera-

tions (such as bit-oriented instructions) on

the SPIxBUF register, in either Standard

or Enhanced Buffer mode.

a) Clear the SPIxIF bit in the respective IFSx

register.

b) Set the SPIxIE bit in the respective IECx

register.

The module also supports a basic framed SPI protocol

while operating in either Master or Slave modes. A total

of four framed SPI configurations are supported.

c) Write the SPIxIP bits in the respective IPCx

register to set the interrupt priority.

The SPI serial interface consists of four pins:

3. Write the desired settings to the SPIxCON1 and

• SDIx: Serial Data Input

SPIxCON2

registers

with

MSTEN

(SPIxCON1<5>) = 0.

• SDOx: Serial Data Output

• SCKx: Shift Clock Input or Output

4. Clear the SMP bit.

5. If the CKE bit is set, then the SSEN bit

(SPIxCON1<7>) must be set to enable the

SSx pin.

• SSx: Active-Low Slave Select or Frame

Synchronization I/O Pulse

The SPI module can be configured to operate using

2, 3 or 4 pins. In the 3-pin mode, SSx is not used. In the

2-pin mode, both SDOx and SSx are not used.

6. Clear the SPIROV bit (SPIxSTAT<6>).

7. Enable SPI operation by setting the SPIEN bit

(SPIxSTAT<15>).

A block diagram of the module is shown in Figure 15-1

and Figure 15-2.

Note: In this section, the SPI modules are

referred to together as SPIx, or separately

as SPI1 and SPI2. Special Function Reg-

isters will follow a similar notation. For

example, SPIxCON refers to the control

register for the SPI1 or SPI2 module.

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To set up the SPI module for the Enhanced Buffer

Master mode of operation:

To set up the SPI module for the Enhanced Buffer

Slave mode of operation:

1. If using interrupts:

1. Clear the SPIxBUF register.

2. If using interrupts:

a) Clear the SPIxIF bit in the respective IFSx

register.

• Clear the SPIxIF bit in the respective IFSx

register.

b) Set the SPIxIE bit in the respective IECx

register.

• Set the SPIxIE bit in the respective IECx

register.

c) Write the SPIxIP bits in the respective IPCx

register.

• Write the SPIxIP bits in the respective IPCx

register to set the interrupt priority.

2. Write the desired settings to the SPIxCON1

and SPIxCON2 registers with MSTEN

(SPIxCON1<5>) = 1.

3. Write the desired settings to the SPIxCON1

and SPIxCON2 registers with MSTEN

(SPIxCON1<5>) = 0.

3. Clear the SPIROV bit (SPIxSTAT<6>).

4. Select Enhanced Buffer mode by setting the

SPIBEN bit (SPIxCON2<0>).

4. Clear the SMP bit.

5. If the CKE bit is set, then the SSEN bit must be

set, thus enabling the SSx pin.

5. Enable SPI operation by setting the SPIEN bit

(SPIxSTAT<15>).

6. Clear the SPIROV bit (SPIxSTAT<6>).

6. Write the data to be transmitted to the SPIxBUF

register. Transmission (and reception) will start

as soon as data is written to the SPIxBUF

register.

7. Select Enhanced Buffer mode by setting the

SPIBEN bit (SPIxCON2<0>).

8. Enable SPI operation by setting the SPIEN bit

(SPIxSTAT<15>).

FIGURE 15-1:

SPIx MODULE BLOCK DIAGRAM (STANDARD MODE)

SCKx

1:1 to 1:8

Secondary

Prescaler

1:1/4/16/64

Primary

Prescaler

FCY

SSx/FSYNCx

Sync

Control

Select

Edge

Control

Clock

SPIxCON1<1:0>

SPIxCON1<4:2>

Control

Shift

SDOx

SDIx

Enable

Master Clock

bit 0

SPIxSR

Transfer

SPIxBUF

Read SPIxBUF

Write SPIxBUF

16

Internal Data Bus

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FIGURE 15-2:

SPIx MODULE BLOCK DIAGRAM (ENHANCED MODE)

SCKx

1:1/4/16/64

Primary

Prescaler

1:1 to 1:8

Secondary

Prescaler

FCY

SSx/FSYNCx

Sync

Control

Select

Edge

Control

Clock

SPIxCON1<1:0>

SPIxCON1<4:2>

Control

Shift

SDOx

SDIx

Enable

Master Clock

bit 0

SPIxSR

Transfer

8-Level FIFO

Receive Buffer

8-Level FIFO

Transmit Buffer

SPIxBUF

Read SPIxBUF

Write SPIxBUF

16

Internal Data Bus

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REGISTER 15-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER

R/W-0

SPIEN

U-0

—

R/W-0

U-0

—

U-0

—

R-0

SPISIDL

SPIBEC2

SPIBEC1

SPIBEC0

bit 15

bit 8

R/W-0

R/C-0

R/W-0

R-0

SRMPT

SPIROV

SRXMPT

SISEL2

SISEL1

SISEL0

SPITBF

SPIRBF

bit 7

bit 0

Legend:

C = Clearable bit

W = Writable bit

‘1’ = Bit is set

R = Readable bit

-n = Value at POR

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

SPIEN: SPIx Enable bit

1= Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins

0= Disables module

bit 14

bit 13

Unimplemented: Read as ‘0’

SPISIDL: Stop in Idle Mode bit

1= Discontinues module operation when device enters Idle mode

0= Continues module operation in Idle mode

bit 12-11

bit 10-8

Unimplemented: Read as ‘0’

SPIBEC<2:0>: SPIx Buffer Element Count bits

Master mode:

Number of SPI transfers pending.

Slave mode:

Number of SPI transfers unread.

bit 7

bit 6

SRMPT: Shift Register (SPIxSR) Empty bit (valid in Enhanced Buffer mode)

1= SPIx Shift register is empty and ready to send or receive

0= SPIx Shift register is not empty; read as ‘0’

SPIROV: Receive Overflow Flag bit

1= A new byte/word is completely received and discarded; the user software has not read the previous

data in the SPIxBUF register

0= No overflow has occurred

bit 5

SRXMPT: Receive FIFO Empty bit (valid in Enhanced Buffer mode)

1= Receive FIFO is empty

0= Receive FIFO is not empty’

bit 4-2

SISEL<2:0>: SPIx Buffer Interrupt Mode bits (valid in Enhanced Buffer mode)

111= Interrupt when the SPIx transmit buffer is full (SPITBF bit is set)

110= Interrupt when the last bit is shifted into SPIxSR, as a result, the TX FIFO is empty

101= Interrupt when the last bit is shifted out of SPIxSR, now the transmit is complete

100= Interrupt when one data is shifted into the SPIxSR, as a result, the TX FIFO has one open spot

011= Interrupt when the SPIx receive buffer is full (SPIRBF bit is set)

010= Interrupt when the SPIx receive buffer is 3/4 or more full

001= Interrupt when data is available in the receive buffer (SRMPT bit is set)

000= Interrupt when the last data in the receive buffer is read, and as a result, the buffer is empty

(SRXMPT bit set)

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REGISTER 15-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER (CONTINUED)

bit 1

SPITBF: SPIx Transmit Buffer Full Status bit

1= Transmit not yet started, SPIxTXB is full

0= Transmit started, SPIxTXB is empty

In Standard Buffer mode:

Automatically set in hardware when the CPU writes to the SPIxBUF location, loading SPIxTXB.

Automatically cleared in hardware when the SPIx module transfers data from SPIxTXB to SPIxSR.

In Enhanced Buffer mode:

Automatically set in hardware when the CPU writes to the SPIxBUF location, loading the last available

buffer location. Automatically cleared in hardware when a buffer location is available for a CPU write.

bit 0

SPIRBF: SPIx Receive Buffer Full Status bit

1= Receive complete, SPIxRXB is full

0= Receive is not complete, SPIxRXB is empty

In Standard Buffer mode:

Automatically set in hardware when the SPIx transfers data from SPIxSR to SPIxRXB. Automatically

cleared in hardware when the core reads the SPIxBUF location, reading SPIxRXB.

In Enhanced Buffer mode:

Automatically set in hardware when the SPIx transfers data from SPIxSR to the buffer, filling the last

unread buffer location. Automatically cleared in hardware when a buffer location is available for a

transfer from SPIxSR.

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REGISTER 15-2: SPIXCON1: SPIx CONTROL REGISTER 1

U-0

—

U-0

—

U-0

—

R/W-0

SMP

R/W-0

CKE⁽¹⁾

DISSCK

DISSDO

MODE16

bit 15

bit 8

R/W-0

SSEN

R/W-0

CKP

R/W-0

MSTEN

SPRE2

SPRE1

SPRE0

PPRE1

PPRE0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12

Unimplemented: Read as ‘0’

DISSCK: Disable SCKx pin bit (SPI Master modes only)

1= Internal SPI clock is disabled, the pin functions as an I/O

0= Internal SPI clock is enabled

bit 11

bit 10

bit 9

DISSDO: Disable SDOx pin bit

1= SDOx pin is not used by the module; the pin functions as an I/O

0= SDOx pin is controlled by the module

MODE16: Word/Byte Communication Select bit

1= Communication is word-wide (16 bits)

0= Communication is byte-wide (8 bits)

SMP: SPIx Data Input Sample Phase bit

Master mode:

1= Input data is sampled at the end of data output time

0= Input data is sampled at the middle of data output time

Slave mode:

SMP must be cleared when SPIx is used in Slave mode.

bit 8

bit 7

bit 6

bit 5

bit 4-2

CKE: SPIx Clock Edge Select bit⁽¹⁾

1= Serial output data changes on transition from active clock state to Idle clock state (see bit 6)

0= Serial output data changes on transition from Idle clock state to active clock state (see bit 6)

SSEN: Slave Select Enable bit (Slave mode)

1= SSx pin is used for Slave mode

0= SSx pin is not used by module; pin is controlled by port function

CKP: Clock Polarity Select bit

1= Idle state for clock is a high level; active state is a low level

0= Idle state for clock is a low level; active state is a high level

MSTEN: Master Mode Enable bit

1= Master mode

0= Slave mode

SPRE<2:0>: Secondary Prescale bits (Master mode)

111= Secondary prescale 1:1

110= Secondary prescale 2:1

...

000= Secondary prescale 8:1

bit 1-0

PPRE<1:0>: Primary Prescale bits (Master mode)

11= Primary prescale 1:1

10= Primary prescale 4:1

01= Primary prescale 16:1

00= Primary prescale 64:1

Note 1: The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed

SPI modes (FRMEN = 1).

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REGISTER 15-3: SPIxCON2: SPIx CONTROL REGISTER 2

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

FRMEN

SPIFSD

SPIFPOL

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

SPIFE

R/W-0

SPIBEN

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

bit 14

bit 13

FRMEN: Framed SPIx Support bit

1= Framed SPIx support is enabled

0= Framed SPIx support is disabled

SPIFSD: Frame Sync Pulse Direction Control on SSx Pin bit

1= Frame sync pulse input (slave)

0= Frame sync pulse output (master)

SPIFPOL: Frame Sync Pulse Polarity bit (Frame mode only)

1= Frame sync pulse is active-high

0= Frame sync pulse is active-low

bit 12-2

bit 1

Unimplemented: Read as ‘0’

SPIFE: Frame Sync Pulse Edge Select bit

1= Frame sync pulse coincides with the first bit clock

0= Frame sync pulse precedes the first bit clock

bit 0

SPIBEN: Enhanced Buffer Enable bit

1= Enhanced Buffer is enabled

0= Enhanced Buffer is disabled (Legacy mode)

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FIGURE 15-3:

SPI MASTER/SLAVE CONNECTION (STANDARD MODE)

PROCESSOR 1 (SPI Master)

PROCESSOR 2 (SPI Slave)

SDOx

SDIx

Serial Receive Buffer

(SPIxRXB)

Serial Receive Buffer

(SPIxRXB)

SDIx

SDOx

Shift Register

(SPIxSR)

Shift Register

(SPIxSR)

LSb

MSb

LSb

Serial Transmit Buffer

(SPIxTXB)

Serial Clock

SCKx

SSx

SCKx

SPIx Buffer

(SPIxBUF)

SPIx Buffer

(SPIxBUF)

(SSEN (SPIxCON1<7>) = 1and MSTEN (SPIxCON1<5>) = 0)

(MSTEN (SPIxCON1<5> = 1))

Note 1: Using the SSx pin in the Slave mode of operation is optional.

2: User must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory

mapped to SPIxBUF.

FIGURE 15-4:

SPI MASTER/SLAVE CONNECTION (ENHANCED BUFFER MODES)

PROCESSOR 1 (SPI Enhanced Buffer Master)

PROCESSOR 2 (SPI Enhanced Buffer Slave)

SDOx

SDIx

SDOx

Shift Register

(SPIxSR)

Shift Register

(SPIxSR)

LSb

MSb

LSb

8-Level FIFO Buffer

Serial Clock

SPIx Buffer

(SPIxBUF)

SPIx Buffer

(SPIxBUF)

SCKx

SSx

SCKx

SSx

MSTEN (SPIxCON1<5> = 1and

SPIBEN (SPIxCON2<0>) = 1

SSEN (SPIxCON1<7>) = 1and

MSTEN (SPIxCON1<5>) = 0and

SPIBEN (SPIxCON2<0>) = 1

Note 1: Using the SSx pin in Slave mode of operation is optional.

2: User must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory

mapped to SPIxBUF.

DS39747F-page 134

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FIGURE 15-5:

FIGURE 15-6:

FIGURE 15-7:

FIGURE 15-8:

SPI MASTER, FRAME MASTER CONNECTION DIAGRAM

PIC24F

PROCESSOR 2

(SPI Slave, Frame Slave)

SDOx

SDIx

SDOx

Serial Clock

SCKx

SSx

SCKx

SSx

Frame Sync

Pulse

SPI MASTER, FRAME SLAVE CONNECTION DIAGRAM

PIC24F

PROCESSOR 2

SPI Master, Frame Slave)

SDOx

SDIx

SDOx

Serial Clock

SCKx

SSx

SCKx

SSx

Frame Sync

Pulse

SPI SLAVE, FRAME MASTER CONNECTION DIAGRAM

PIC24F

PROCESSOR 2

(SPI Slave, Frame Slave)

SDOx

SDIx

SDOx

Serial Clock

SCKx

SSx

SCKx

SSx

Frame Sync.

Pulse

SPI SLAVE, FRAME SLAVE CONNECTION DIAGRAM

PIC24F

PROCESSOR 2

(SPI Master, Frame Slave)

SDOx

SDIx

SDOx

Serial Clock

SCKx

SSx

SCKx

SSx

Frame Sync

Pulse

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EQUATION 15-1: RELATIONSHIP BETWEEN DEVICE AND SPI CLOCK SPEED⁽¹⁾

FCY

FSCK =

Primary Prescaler * Secondary Prescaler

Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.

TABLE 15-1: SAMPLE SCK FREQUENCIES^(1,2)

Secondary Prescaler Settings

FCY = 16 MHz

1:1

2:1

4:1

6:1

8:1

Primary Prescaler Settings

1:1

4:1

Invalid

4000

1000

250

8000

2000

500

4000

1000

250

63

2667

667

167

42

2000

500

125

31

16:1

64:1

125

FCY = 5 MHz

Primary Prescaler Settings

1:1

4:1

5000

1250

313

78

2500

625

156

39

1250

313

78

833

208

52

625

156

39

16:1

64:1

20

13

10

Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.

2: The SCKx frequencies are shown in kHz.

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16.1 Communicating as a Master in a

Single Master Environment

16.0 INTER-INTEGRATED CIRCUIT

2

(I C™)

The details of sending a message in Master mode

depends on the communications protocol for the device

being communicated with. Typically, the sequence of

events is as follows:

Note:

This data sheet summarizes the features of

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. Refer to Section 24. “Inter-

Integrated Circuit™ (I²C™)” (DS39702)

in the “PIC24F Family Reference Manual”

for more information.

1. Assert a Start condition on SDAx and SCLx.

2. Send the I²C device address byte to the slave

with a write indication.

3. Wait for and verify an Acknowledge from the

slave.

The Inter-Integrated Circuit (I²C) module is a serial

interface useful for communicating with other periph-

eral or microcontroller devices. These peripheral

devices may be serial EEPROMs, display drivers, A/D

Converters, etc.

4. Send the first data byte (sometimes known as

the command) to the slave.

5. Wait for and verify an Acknowledge from the

slave.

The I²C module supports these features:

6. Send the serial memory address low byte to the

slave.

• Independent master and slave logic

• 7-bit and 10-bit device addresses

• General call address, as defined in the I²C protocol

7. Repeat Steps 4 and 5 until all data bytes are

sent.

• Clock stretching to provide delays for the

processor to respond to a slave data request

8. Assert a Repeated Start condition on SDAx and

SCLx.

• Both 100 kHz and 400 kHz bus specifications.

• Configurable address masking

9. Send the device address byte to the slave with

a read indication.

• Multi-Master modes to prevent loss of messages

in arbitration

10. Wait for and verify an Acknowledge from the

slave.

• Bus Repeater mode, allowing the acceptance of

all messages as a slave, regardless of the

address

11. Enable master reception to receive serial

memory data.

12. Generate an ACK or NACK condition at the end

of a received byte of data.

• Automatic SCL

13. Generate a Stop condition on SDAx and SCLx.

A block diagram of the module is shown in Figure 16-1.

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FIGURE 16-1:

I²C™ BLOCK DIAGRAM

Internal

Data Bus

I2CxRCV

Read

Shift

Clock

SCLx

SDAx

I2CxRSR

LSB

Address Match

Write

Read

Match Detect

I2CxMSK

Write

Read

I2CxADD

Start and Stop

Bit Detect

Write

Start and Stop

Bit Generation

I2CxSTAT

I2CxCON

Read

Write

Collision

Detect

Acknowledge

Generation

Read

Clock

Stretching

Write

Read

I2CxTRN

LSB

Shift Clock

Reload

Control

Write

Read

BRG Down Counter

TCY/2

I2CxBRG

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16.2 Setting Baud Rate When

Operating as a Bus Master

16.3 Slave Address Masking

The I2CxMSK register (Register 16-3) designates

address bit positions as “don’t care” for both 7-Bit and

10-Bit Addressing modes. Setting a particular bit loca-

tion (= 1) in the I2CxMSK register causes the slave

module to respond, whether the corresponding

address bit value is a ‘0’ or ‘1’. For example, when

I2CxMSK is set to ‘00100000’, the slave module will

detect both addresses, ‘0000000’ and ‘00100000’.

To compute the Baud Rate Generator reload value, use

the following equation:

EQUATION 16-1:⁽¹⁾

I2CxBRG = (FCY/FSCL – FCY/10,000,000) – 1

Note 1: Based on FCY = FOSC/2; Doze mode and

To enable address masking, the IPMI (Intelligent

Peripheral Management Interface) must be disabled by

clearing the IPMIEN bit (I2CxCON<11>).

PLL are disabled.

TABLE 16-1: I²C™ CLOCK RATES^(1,3,4)

Required

I2CxBRG Value

Actual

System

FSCL

FCY

FSCL

(Decimal)

(Hexadecimal)

100 kHz

400 kHz

1 MHz

16 MHz

8 MHz

4 MHz

16 MHz

8 MHz

4 MHz

2 MHz

16 MHz

8 MHz

4 MHz

157

78

39

37

18

9

9D

4E

27

25

12

9

100 kHz

99 kHz

404 kHz

385 kHz⁽²⁾

1,026 KHz

909 KHz

4

13

6

D

1 MHz

6

1 MHz

3

Note 1: Based on TCY = TOSC * 2; Doze mode and PLL are disabled.

2: This is the closest value to 400 kHz for this value of FCY.

3: FCY = 2 MHz is the minimum input clock frequency to have FSCL = 1 MHz.

4: I2CxBRG cannot have a value of less than 2.

As a result of changes in the I²C protocol, several I²C

addresses are reserved and will not be Acknowledged

in Slave mode.

Address masking does not affect behavior. Refer to

Table 16-2 for a summary of these reserved addresses.

.

TABLE 16-2: RESERVED I²C™ ADDRESSES⁽¹⁾

Slave Address

R/W Bit

Description

0000 000

0000 001

0000 010

0000 011

0000 1xx

1111 1xx

1111 0xx

0

1

x

General Call Address⁽²⁾

Start Byte

CBUS Address

Reserved

HS Mode Master Code

Reserved

10-Bit Slave Upper Byte⁽³⁾

Note 1: The above address bits will not cause an address match, independent of address mask settings.

2: The address will be Acknowledged only if GCEN = 1.

3: A match on this address can only occur on the upper byte in 10-Bit Addressing mode.

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REGISTER 16-1: I2CxCON: I2Cx CONTROL REGISTER

R/W-0

I2CEN

U-0

—

R/W-0

R/W-1, HC

SCLREL

R/W-0

A10M

R/W-0

SMEN

I2CSIDL

IPMIEN

DISSLW

bit 15

bit 8

R/W-0

GCEN

R/W-0

R/W-0, HC R/W-0, HC

ACKEN RCEN

R/W-0, HC

PEN

R/W-0, HC

RSEN

R/W-0, HC

SEN

STREN

ACKDT

bit 7

bit 0

Legend:

HC = Hardware Clearable bit

W = Writable bit

R = Readable bit

-n = Value at POR

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

‘1’ = Bit is set

bit 15

I2CEN: I2Cx Enable bit

1= Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins

0= Disables I2Cx module; all I²C™ pins are controlled by port functions

bit 14

bit 13

Unimplemented: Read as ‘0’

I2CSIDL: Stop in Idle Mode bit

1= Discontinues module operation when the device enters an Idle mode

0= Continues module operation in Idle mode

bit 12

SCLREL: SCLx Release Control bit (when operating as an I²C™ slave)

1= Releases SCLx clock

0= Holds SCLx clock low (clock stretch)

If STREN = 1:

Bit is R/W (i.e., software may write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware is clear

at the beginning of slave transmission. Hardware is clear at the end of slave reception.

If STREN = 0:

Bit is R/S (i.e., software may only write ‘1’ to release clock). Hardware is clear at the beginning of slave

transmission.

bit 11

bit 10

bit 9

IPMIEN: Intelligent Peripheral Management Interface (IPMI) Enable bit

1= IPMI Support mode is enabled; all addresses are Acknowledged

0= IPMI mode is disabled

A10M: 10-Bit Slave Address bit

1= I2CxADD is a 10-bit slave address

0= I2CxADD is a 7-bit slave address

DISSLW: Disable Slew Rate Control bit

1= Slew rate control is disabled

0= Slew rate control is enabled

bit 8

SMEN: SMBus Input Levels bit

1= Enables I/O pin thresholds compliant with the SMBus specification

0= Disables SMBus input thresholds

bit 7

GCEN: General Call Enable bit (when operating as an I²C slave)

1= Enables interrupt when a general call address is received in the I2CxRSR (module is enabled for

reception)

0= General call address is disabled

bit 6

STREN: SCLx Clock Stretch Enable bit (when operating as an I²C slave)

Used in conjunction with the SCLREL bit.

1= Enables software or receives clock stretching

0= Disables software or receives clock stretching

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REGISTER 16-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED)

bit 5

ACKDT: Acknowledge Data bit (When operating as an I²C master; applicable during master receive.)

Value that will be transmitted when the software initiates an Acknowledge sequence.

1= Sends NACK during Acknowledge

0= Sends ACK during Acknowledge

bit 4

ACKEN: Acknowledge Sequence Enable bit

(When operating as an I²C master; applicable during master receive.)

1= Initiates Acknowledge sequence on SDAx and SCLx pins and transmits the ACKDT data bit.

Hardware is clear at the end of the master Acknowledge sequence.

0= Acknowledge sequence is not in progress

bit 3

bit 2

bit 1

bit 0

RCEN: Receive Enable bit (when operating as an I²C master)

1= Enables Receive mode for I²C. Hardware is clear at the end of the eighth bit of the master receive

data byte.

0= Receive sequence is not in progress

PEN: Stop Condition Enable bit (when operating as an I²C master)

1= Initiates Stop condition on SDAx and SCLx pins. Hardware is clear at the end of the master Stop

sequence.

0= Stop condition is not in progress

RSEN: Repeated Start Condition Enable bit (when operating as an I²C master)

1= Initiates Repeated Start condition on SDAx and SCLx pins. Hardware is clear at the end of the

master Repeated Start sequence.

0= Repeated Start condition is not in progress

SEN: Start Condition Enable bit (when operating as an I²C master)

1= Initiates Start condition on SDAx and SCLx pins. Hardware is clear at the end of the master Start

sequence.

0= Start condition is not in progress

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REGISTER 16-2: I2CxSTAT: I2Cx STATUS REGISTER

R-0, HSC

ACKSTAT

R-0, HSC

TRSTAT

U-0

—

U-0

—

U-0

—

R/C-0, HSC R-0, HSC

R-0, HSC

ADD10

BCL

GCSTAT

bit 15

bit 8

R/C-0, HSC R/C-0, HSC

IWCOL I2COV

bit 7

R-0, HSC

D/A

R/C-0, HSC R/C-0, HSC R-0, HSC

R/W

R-0, HSC

RBF

R-0, HSC

TBF

P

S

bit 0

Legend:

HS = Hardware Settable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

C = Clearable bit

R = Readable bit

HSC = Hardware Settable/Clearable bit

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

bit 14

ACKSTAT: Acknowledge Status bit

1= NACK is received from slave

0= ACK is received from slave

Hardware is set or clear at the end of slave Acknowledge.

TRSTAT: Transmit Status bit (When operating as I²C master; applicable to master transmit operation.)

1= Master transmit is in progress (8 bits + ACK)

0= Master transmit is not in progress

Hardware is set at the beginning of master transmission. Hardware is clear at the end of slave Acknowledge.

bit 13-11

bit 10

Unimplemented: Read as ‘0’

BCL: Master Bus Collision Detect bit

1= A bus collision has been detected during master operation

0= No collision

Hardware is set at the detection of a bus collision.

bit 9

bit 8

bit 7

bit 6

bit 5

GCSTAT: General Call Status bit

1= General call address was received

0= General call address was not received

Hardware is set when an address matches a general call address. Hardware is clear at Stop detection.

ADD10: 10-Bit Address Status bit

1= 10-bit address was matched

0= 10-bit address was not matched

Hardware is set at a match of the 2nd byte of a matched 10-bit address. Hardware is clear at Stop detection.

IWCOL: Write Collision Detect bit

1= An attempt to write the I2CxTRN register failed because the I²C module is busy

0= No collision

Hardware is set at an occurrence of a write to I2CxTRN while busy (cleared by software).

I2COV: Receive Overflow Flag bit

1= A byte was received while the I2CxRCV register is still holding the previous byte

0= No overflow

Hardware is set at an attempt to transfer I2CxRSR to I2CxRCV (cleared by software).

D/A: Data/Address bit (when operating as I²C slave)

1= Indicates that the last byte received was data

0= Indicates that the last byte received was device address

Hardware is clear at a device address match. Hardware is set after a transmission finishes or by

reception of a slave byte.

bit 4

P: Stop bit

1= Indicates that a Stop bit has been detected last

0= Stop bit was not detected last

Hardware is set or clear when a Start, Repeated Start or Stop is detected.

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REGISTER 16-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED)

bit 3

bit 2

bit 1

S: Start bit

1= Indicates that a Start (or Repeated Start) bit has been detected last

0= Start bit was not detected last

Hardware is set or clear when Start, Repeated Start or Stop is detected.

R/W: Read/Write bit Information (when operating as I²C slave)

1= Read – indicates data transfer is output from slave

0= Write – indicates data transfer is input to slave

Hardware is set or clear after reception of an I²C device address byte.

RBF: Receive Buffer Full Status bit

1= Receive is complete, I2CxRCV is full

0= Receive is not complete, I2CxRCV is empty

Hardware is set when I2CxRCV is written with the received byte. Hardware is clear when the software reads

I2CxRCV.

bit 0

TBF: Transmit Buffer Full Status bit

1= Transmit is in progress, I2CxTRN is full

0= Transmit is complete, I2CxTRN is empty

Hardware is set when the software writes to I2CxTRN. Hardware is clear at the completion of

data transmission.

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REGISTER 16-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

AMSK9

AMSK8

bit 15

bit 8

R/W-0

AMSK7

AMSK6

AMSK5

AMSK4

AMSK3

AMSK2

AMSK1

AMSK0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-10

bit 9-0

Unimplemented: Read as ‘0’

AMSK<9:0>: Mask for Address Bit x Select bits

1= Enables masking for bit x of incoming message address; bit match is not required in this position

0= Disables masking for bit x; bit match is required in this position

DS39747F-page 144

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• Fully Integrated Baud Rate Generator with 16-Bit

Prescaler

17.0 UNIVERSAL ASYNCHRONOUS

RECEIVER TRANSMITTER

(UART)

• Baud Rates Ranging from 1 Mbps to 15 bps at

16 MIPS

• 4-Deep First-In-First-Out (FIFO) Transmit Data

Buffer

Note:

This data sheet summarizes the features of

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. Refer to Section 21. “UART”

(DS39708) in the “PIC24F Family

Reference Manual” for more information.

• 4-Deep FIFO Receive Data Buffer

• Parity, Framing and Buffer Overrun Error Detection

• Support for 9-bit mode with Address Detect

(9th bit = 1)

• Transmit and Receive Interrupts

The Universal Asynchronous Receiver Transmitter

(UART) module is one of the serial I/O modules available

in the PIC24F device family. The UARTx is a full-duplex,

asynchronous system that can communicate with

peripheral devices, such as personal computers,

LIN/J2602, RS-232 and RS-485 interfaces. The

module also supports a hardware flow control option

with the UxCTS and UxRTS pins, and also includes an

IrDA^®encoder and decoder.

• Loopback mode for Diagnostic Support

• Support for Sync and Break Characters

• Supports Automatic Baud Rate Detection

• IrDA Encoder and Decoder Logic

• 16x Baud Clock Output for IrDA Support

A simplified block diagram of the UARTx is shown in

Figure 17-1. The UARTx module consists of these key

important hardware elements:

The primary features of the UARTx module are:

• Baud Rate Generator

• Full-Duplex, 8 or 9-Bit Data Transmission

Through the UxTX and UxRX Pins

• Asynchronous Transmitter

• Asynchronous Receiver

• Even, Odd or No Parity Options (for 8-bit data)

• One or Two Stop bits

• Hardware Flow Control Option with UxCTS and

UxRTS Pins

FIGURE 17-1:

UARTx SIMPLIFIED BLOCK DIAGRAM

Baud Rate Generator

IrDA^®

BCLKx

Hardware Flow Control

UARTx Receiver

UxRTS

UxCTS

UxRX

UxTX

UARTx Transmitter

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The maximum baud rate (BRGH = 0) possible is

FCY/16 (for UBRGx = 0) and the minimum baud rate

possible is FCY/(16 * 65536).

17.1 UARTx Baud Rate Generator

(BRG)

The UARTx module includes a dedicated, 16-bit Baud

Rate Generator. The UBRGx register controls the

period of a free-running, 16-bit timer. Equation 17-1

shows the formula for computation of the baud rate

with BRGH = 0.

Equation 17-2 shows the formula for computation of

the baud rate with BRGH = 1.

EQUATION 17-2: UARTx BAUD RATE WITH

BRGH = 1⁽¹⁾

EQUATION 17-1: UARTx BAUD RATE WITH

FCY

Baud Rate =

BRGH = 0⁽¹⁾

4 • (UBRGx + 1)

FCY

4 • Baud Rate

Baud Rate =

– 1

UBRGx =

16 • (UBRGx + 1)

FCY

16 • Baud Rate

Note 1: Based on FCY = FOSC/2; Doze mode

– 1

UBRGx =

and PLL are disabled.

Note 1: Based on FCY = FOSC/2; Doze mode

The maximum baud rate (BRGH = 1) possible is FCY/4

(for UBRGx = 0) and the minimum baud rate possible

is FCY/(4 * 65536).

and PLL are disabled.

Example 17-1 shows the calculation of the baud rate

error for the following conditions:

Writing a new value to the UBRGx register causes the

BRG timer to be reset (cleared). This ensures the BRG

does not wait for a timer overflow before generating the

new baud rate.

• FCY = 4 MHz

• Desired Baud Rate = 9600

EXAMPLE 17-1:

BAUD RATE ERROR CALCULATION (BRGH = 0)⁽¹⁾

Desired Baud Rate

=

FCY/(16 (UBRGx + 1))

Solving for UBRGx value:

BRGx

=

((FCY/Desired Baud Rate)/16) – 1

((4000000/9600)/16) – 1

25

Calculated Baud Rate

=

4000000/(16 (25 + 1))

9615

Error

=

(Calculated Baud Rate – Desired Baud Rate)

Desired Baud Rate

=

(9615 – 9600)/9600

0.16%

Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.

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17.2 Transmitting in 8-Bit Data Mode

17.5 Receiving in 8-Bit or 9-Bit Data

Mode

1. Set up the UARTx:

a) Write appropriate values for data, parity and

Stop bits.

1. Set up the UARTx (as described in Section 17.2

“Transmitting in 8-Bit Data Mode”).

b) Write appropriate baud rate value to the

UBRGx register.

2. Enable the UARTx.

3. A receive interrupt will be generated when one

or more data characters have been received, as

per interrupt control bit, URXISELx.

c) Set up transmit and receive interrupt enable

and priority bits.

2. Enable the UARTx.

4. Read the OERR bit to determine if an overrun

error has occurred. The OERR bit must be reset

in software.

3. Set the UTXEN bit (causes a transmit interrupt).

4. Write data byte to lower byte of UTXxREG word.

The value will be immediately transferred to the

Transmit Shift Register (TSR) and the serial bit

stream will start shifting out with the next rising

edge of the baud clock.

5. Read UxRXREG.

The act of reading the UxRXREG character will move

the next character to the top of the receive FIFO,

including a new set of PERR and FERR values.

5. Alternately, the data byte may be transferred

while UTXEN = 0 and then the user may set

UTXEN. This will cause the serial bit stream to

begin immediately because the baud clock will

start from a cleared state.

17.6 Operation of UxCTS and UxRTS

Control Pins

UARTx Clear-to-Send (UxCTS) and Request-to-Send

(UxRTS) are the two hardware controlled pins that are

associated with the UARTx modules. These two pins

allow the UARTx to operate in Simplex and Flow Con-

trol mode. They are implemented to control the

transmission and reception between the Data Terminal

Equipment (DTE). The UEN<1:0> bits in the UxMODE

register configure these pins.

6. A transmit interrupt will be generated as per

interrupt control bit, UTXISELx.

17.3 Transmitting in 9-Bit Data Mode

1. Set up the UARTx (as described in Section 17.2

“Transmitting in 8-Bit Data Mode”).

2. Enable the UARTx.

17.7 Infrared Support

3. Set the UTXEN bit (causes a transmit interrupt).

4. Write UxTXREG as a 16-bit value only.

The UARTx module provides two types of infrared

UARTx support: one is the IrDA clock output to support

the external IrDA encoder and decoder device (legacy

module support), and the other is the full implementation

of the IrDA encoder and decoder.

5. A word write to UxTXREG triggers the transfer

of the 9-bit data to the TSR. Serial bit stream will

start shifting out with the first rising edge of the

baud clock.

6. A transmit interrupt will be generated as per the

setting of control bit, UTXISELx.

17.8 External IrDA Support – IrDA

Clock Output

17.4 Break and Sync Transmit

Sequence

To support the external IrDA encoder and decoder

devices, the BCLKx pin (same as the UxRTS pin) can

be configured to generate the 16x baud clock. With

UEN<1:0> = 11, the BCLKx pin will output the

16x baud clock if the UARTx module is enabled. It can

be used to support the IrDA codec chip.

The following sequence will send a message frame

header, made up of a Break, followed by an auto-baud

Sync byte.

1. Configure the UARTx for the desired mode.

2. Set UTXEN and UTXBRK – sets up the Break

character,

17.9 Built-in IrDA Encoder and Decoder

3. Load the UxTXREG with a dummy character to

initiate transmission (value is ignored).

The UARTx has full implementation of the IrDA

encoder and decoder as part of the UARTx module.

The built-in IrDA encoder and decoder functionality is

enabled using the IREN bit UxMODE<12>. When

enabled (IREN = 1), the receive pin (UxRX) acts as the

input from the infrared receiver. The transmit pin

(UxTX) acts as the output to the infrared transmitter.

4. Write ‘55h’ to UxTXREG – loads the Sync

character into the transmit FIFO.

5. After the Break has been sent, the UTXBRK bit

is reset by hardware. The Sync character now

transmits.

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REGISTER 17-1: UxMODE: UARTx MODE REGISTER

R/W-0

UARTEN

bit 15

U-0

—

R/W-0

USIDL

R/W-0

IREN⁽¹⁾

R/W-0

U-0

—

R/W-0

UEN1

R/W-0

UEN0

RTSMD

bit 8

R/W-0, HC

WAKE

R/W-0

R/W-0, HC

ABAUD

R/W-0

RXINV

R/W-0

BRGH

R/W-0

LPBACK

PDSEL1

PDSEL0

STSEL

bit 7

bit 0

Legend:

HC = Hardware Clearable bit

W = Writable bit

R = Readable bit

-n = Value at POR

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

‘1’ = Bit is set

bit 15

UARTEN: UARTx Enable bit

1= UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0>

0= UARTx is disabled; all UARTx pins are controlled by PORT latches; UARTx power consumption is minimal

bit 14

bit 13

Unimplemented: Read as ‘0’

USIDL: Stop in Idle Mode bit

1= Discontinues module operation when the device enters Idle mode

0= Continues module operation in Idle mode

bit 12

bit 11

IREN: IrDA^®Encoder and Decoder Enable bit⁽¹⁾

1= IrDA encoder and decoder are enabled

0= IrDA encoder and decoder are disabled

RTSMD: Mode Selection for UxRTS Pin bit

1= UxRTS pin is in Simplex mode

0= UxRTS pin is in Flow Control mode

bit 10

Unimplemented: Read as ‘0’

UEN<1:0>: UARTx Enable bits

bit 9-8

11= UxTX, UxRX and BCLKx pins are enabled and used; the UxCTS pin is controlled by PORT latches

10= UxTX, UxRX, UxCTS and UxRTS pins are enabled and used

01= UxTX, UxRX and UxRTS pins are enabled and used; the UxCTS pin is controlled by PORT latches

00= UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLKx pins are controlled by PORT

latches

bit 7

WAKE: Wake-up on Start bit Detect During Sleep Mode Enable bit

1= UARTx will continue to sample the UxRX pin; interrupt is generated on the falling edge, bit cleared in

hardware on the following rising edge

0= No wake-up is enabled

bit 6

bit 5

LPBACK: UARTx Loopback Mode Select bit

1= Enables Loopback mode

0= Loopback mode is disabled

ABAUD: Auto-Baud Enable bit

1= Enables baud rate measurement on the next character – requires reception of a Sync field (55h);

cleared in hardware upon completion

0= Baud rate measurement is disabled or completed

bit 4

RXINV: Receive Polarity Inversion bit

1= UxRX Idle state is ‘0’

0= UxRX Idle state is ‘1’

Note 1: This feature is only available for the 16x BRG mode (BRGH = 0).

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REGISTER 17-1: UxMODE: UARTx MODE REGISTER (CONTINUED)

bit 3

BRGH: High Baud Rate Enable bit

1= BRG generates 4 clocks per bit period (4x Baud Clock, High-Speed mode)

0= BRG generates 16 clocks per bit period (16x Baud Clock, Standard mode)

bit 2-1

PDSEL<1:0>: Parity and Data Selection bits

11= 9-bit data, no parity

10= 8-bit data, odd parity

01= 8-bit data, even parity

00= 8-bit data, no parity

bit 0

STSEL: Stop Bit Selection bit

1= Two Stop bits

0= One Stop bit

Note 1: This feature is only available for the 16x BRG mode (BRGH = 0).

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REGISTER 17-2: UxSTA: UARTx STATUS AND CONTROL REGISTER

R/W-0

UTXISEL1

bit 15

R/W-0

TXINV

R/W-0

U-0

—

R/W-0, HC

UTXBRK

R/W-0

R-0

R-1

UTXISEL0

UTXEN

UTXBF

TRMT

bit 8

R/W-0

R-1

R-0

R/C-0

R-0

URXISEL1 URXISEL0

bit 7

ADDEN

RIDLE

PERR

FERR

OERR

URXDA

bit 0

Legend:

C = Clearable bit

W = Writable bit

‘1’ = Bit is set

HC = Hardware Clearable bit

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

R = Readable bit

-n = Value at POR

bit 15,13

UTXISEL<1:0>: Transmission Interrupt Mode Selection bits

11= Reserved; do not use

10= Interrupt when a character is transferred to the Transmit Shift Register and as a result, the transmit

buffer becomes empty

01= Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit operations

are completed

00= Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at least

one character open in the transmit buffer)

bit 14

TXINV: Transmit Polarity Inversion bit

IREN = 0:

1= TX Idle state is ‘0’

0= TX Idle state is ‘1’

IREN = 1:

1= IrDA^®encoded TX Idle state is ‘1’

0= IrDA encoded TX Idle state is ‘0’

bit 12

bit 11

Unimplemented: Read as ‘0’

UTXBRK: Transmit Break bit

1= Sends Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit;

cleared by hardware upon completion

0= Sync Break transmission is disabled or completed

bit 10

UTXEN: Transmit Enable bit

1= Transmit is enabled, UxTX pin controlled by UARTx

0= Transmit is disabled, any pending transmission is aborted and the buffer is reset. UxTX pin is controlled

by the PORT.

bit 9

UTXBF: Transmit Buffer Full Status bit (read-only)

1= Transmit buffer is full

0= Transmit buffer is not full, at least one more character can be written

bit 8

TRMT: Transmit Shift Register Empty bit (read-only)

1= Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)

0= Transmit Shift Register is not empty, a transmission is in progress or queued

bit 7-6

URXISEL<1:0>: Receive Interrupt Mode Selection bits

11= Interrupt is set on RSR transfer, making the receive buffer full (i.e., has 4 data characters)

10= Interrupt is set on RSR transfer, making the receive buffer 3/4 full (i.e., has 3 data characters)

0x= Interrupt is set when any character is received and transferred from the RSR to the receive buffer;

receive buffer has one or more characters

bit 5

ADDEN: Address Character Detect bit (bit 8 of received data = 1)

1= Address Detect mode is enabled. If 9-bit mode is not selected, this does not take effect.

0= Address Detect mode is disabled

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REGISTER 17-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)

bit 4

bit 3

bit 2

bit 1

RIDLE: Receiver Idle bit (read-only)

1= Receiver is Idle

0= Receiver is active

PERR: Parity Error Status bit (read-only)

1= Parity error has been detected for the current character (character at the top of the receive FIFO)

0= Parity error has not been detected

FERR: Framing Error Status bit (read-only)

1= Framing error has been detected for the current character (character at the top of the receive FIFO)

0= Framing error has not been detected

OERR: Receive Buffer Overrun Error Status bit (clear/read-only)

1= Receive buffer has overflowed

0= Receive buffer has not overflowed (clearing a previously set OERR bit (1 0transition) will reset

the receiver buffer and the RSR to the empty state)

bit 0

URXDA: Receive Buffer Data Available bit (read-only)

1= Receive buffer has data, at least one more character can be read

0= Receive buffer is empty

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NOTES:

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Key features of the PMP module include:

18.0 PARALLEL MASTER PORT

(PMP)

• Up to 16 Programmable Address Lines

• Up to Two Chip Select Lines

Note:

This data sheet summarizes the features of

• Programmable Strobe Options

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. Refer to Section 13. “Parallel

Master Port (PMP)” (DS39713) in the

“PIC24F Family Reference Manual” for

more information.

- Individual Read and Write Strobes or;

- Read/Write Strobe with Enable Strobe

• Address Auto-Increment/Auto-Decrement

• Programmable Address/Data Multiplexing

• Programmable Polarity on Control Signals

• Legacy Parallel Slave Port Support

• Enhanced Parallel Slave Support

- Address Support

The Parallel Master Port (PMP) module is a parallel,

8-bit I/O module, specifically designed to communicate

with a wide variety of parallel devices, such as commu-

nication peripherals, LCDs, external memory devices

and microcontrollers. Because the interface to parallel

peripherals varies significantly, the PMP is highly

configurable.

- 4-Byte Deep Auto-Incrementing Buffer

• Programmable Wait States

• Selectable Input Voltage Levels

FIGURE 18-1:

PMP MODULE OVERVIEW

Address Bus

Data Bus

Control Lines

PMA<0>

PMALL

PIC24F

Parallel Master Port

PMA<1>

PMALH

Up to 16-Bit Address

EEPROM

PMA<13:2>

PMA<14>

PMCS1

PMA<15>

PMCS2

PMBE

FIFO

Buffer

Microcontroller

LCD

PMRD

PMRD/PMWR

PMWR

PMENB

PMD<7:0>

PMA<7:0>

PMA<15:8>

8-Bit Data

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REGISTER 18-1: PMCON: PARALLEL PORT CONTROL REGISTER

R/W-0

U-0

—

R/W-0

PSIDL

R/W-0

PMPEN

ADRMUX1 ADRMUX0

PTBEEN

PTWREN

PTRDEN

bit 15

bit 8

R/W-0

CSF1

R/W-0

CSF0

R/W-0⁽¹⁾

ALP

R/W-0⁽¹⁾

CS2P

R/W-0⁽¹⁾

CS1P

R/W-0

BEP

R/W-0

WRSP

R/W-0

RDSP

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

PMPEN: Parallel Master Port Enable bit

1= PMP is enabled

0= PMP is disabled, no off-chip access is performed

bit 14

bit 13

Unimplemented: Read as ‘0’

PSIDL: Stop in Idle Mode bit

1= Discontinues module operation when device enters Idle mode

0= Continues module operation in Idle mode

bit 12-11

ADRMUX<1:0>: Address/Data Multiplexing Selection bits

11= Reserved

10= All 16 bits of address are multiplexed on PMD<7:0> pins

01= Lower 8 bits of address are multiplexed on PMD<7:0> pins, upper 8 bits are on PMA<15:8>

00= Address and data appear on separate pins

bit 10

bit 9

PTBEEN: Byte Enable Port Enable bit (16-Bit Master mode)

1= PMBE port is enabled

0= PMBE port is disabled

PTWREN: Write Enable Strobe Port Enable bit

1= PMWR/PMENB port is enabled

0= PMWR/PMENB port is disabled

bit 8

PTRDEN: Read/Write Strobe Port Enable bit

1= PMRD/PMWR port is enabled

0= PMRD/PMWR port is disabled

bit 7-6

CSF<1:0>: Chip Select Function bits

11= Reserved

10= PMCS1 and PMCS2 function as chip select

01= PMCS2 functions as chip select, PMCS1 functions as Address Bit 14

00= PMCS1 and PMCS2 function as Address Bits 15 and 14

bit 5

bit 4

bit 3

ALP: Address Latch Polarity bit⁽¹⁾

1= Active-high (PMALL and PMALH)

0= Active-low (PMALL and PMALH)

CS2P: Chip Select 2 Polarity bit⁽¹⁾

1= Active-high (PMCS2)

0= Active-low (PMCS2)

CS1P: Chip Select 1 Polarity bit⁽¹⁾

1= Active-high (PMCS1/PMCS)

0= Active-low (PMCS1/PMCS)

Note 1: These bits have no effect when their corresponding pins are used as address lines.

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REGISTER 18-1: PMCON: PARALLEL PORT CONTROL REGISTER (CONTINUED)

bit 2

BEP: Byte Enable Polarity bit

1= Byte enable is active-high (PMBE)

0= Byte enable is active-low (PMBE)

bit 1

WRSP: Write Strobe Polarity bit

For Slave modes and Master mode 2 (PMMODE<9:8> = 00,01,10):

1= Write strobe is active-high (PMWR)

0= Write strobe is active-low (PMWR)

For Master mode 1 (PMMODE<9:8> = 11):

1= Enable strobe is active-high (PMENB)

0= Enable strobe is active-low (PMENB)

bit 0

RDSP: Read Strobe Polarity bit

For Slave modes and Master mode 2 (PMMODE<9:8> = 00,01,10):

1= Read strobe is active-high (PMRD)

0= Read strobe is active-low (PMRD)

For Master mode 1 (PMMODE<9:8> = 11):

1= Read/write strobe is active-high (PMRD/PMWR)

0= Read/write strobe is active-low (PMRD/PMWR)

Note 1: These bits have no effect when their corresponding pins are used as address lines.

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REGISTER 18-2: PMMODE: PARALLEL PORT MODE REGISTER

R-0

R/W-0

BUSY

IRQM1

IRQM0

INCM1

INCM0

MODE16

MODE1

MODE0

bit 15

bit 8

R/W-0

WAITB1⁽¹⁾

bit 7

R/W-0

WAITB0⁽¹⁾

R/W-0

WAITE1⁽¹⁾

R/W-0

WAITE0⁽¹⁾

WAITM3

WAITM2

WAITM1

WAITM0

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

BUSY: Busy bit (Master mode only)

1= Port is busy (not useful when the processor stall is active)

0= Port is not busy

bit 14-13

IRQM<1:0>: Interrupt Request Mode bits

11= Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode), or

on a read or write operation when PMA<1:0> = 11(Addressable PSP mode only)

10= No interrupt is generated, processor stall activated

01= Interrupt is generated at the end of the read/write cycle

00= No interrupt is generated

bit 12-11

INCM<1:0>: Increment Mode bits

11= PSP read and write buffers auto-increment (Legacy PSP mode only)

10= Decrements ADDR<15,13:0> by 1 every read/write cycle

01= Increments ADDR<15,13:0> by 1 every read/write cycle

00= No increment or decrement of the address

bit 10

MODE16: 8/16-Bit Mode bit

1= 16-bit mode: Data register is 16 bits, a read or write to the Data register invokes two 8-bit transfers

0= 8-bit mode: Data register is 8 bits, a read or write to the Data register invokes one 8-bit transfer

bit 9-8

MODE<1:0>: Parallel Port Mode Select bits

11= Master mode 1 (PMCSx, PMRD/PMWR, PMENB, PMBE, PMA<x:0> and PMD<7:0>)

10= Master mode 2 (PMCSx, PMRD, PMWR, PMBE, PMA<x:0> and PMD<7:0>)

01= Enhanced PSP, control signals (PMRD, PMWR, PMCS, PMD<7:0> and PMA<1:0>)

00= Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS and PMD<7:0>)

bit 7-6

bit 5-2

bit 1-0

WAITB<1:0>: Data Setup to Read/Write Wait State Configuration bits⁽¹⁾

11= Data Wait of 4 TCY; multiplexed address phase of 4 TCY

10= Data Wait of 3 TCY; multiplexed address phase of 3 TCY

01= Data Wait of 2 TCY; multiplexed address phase of 2 TCY

00= Data Wait of 1 TCY; multiplexed address phase of 1 TCY

WAITM<3:0>: Read to Byte Enable Strobe Wait State Configuration bits

1111= Wait of additional 15 TCY

...

0001= Wait of additional 1 TCY

0000= No additional Wait cycles (operation forced into one TCY)

WAITE<1:0>: Data Hold After Strobe Wait State Configuration bits⁽¹⁾

11= Wait of 4 TCY

10= Wait of 3 TCY

01= Wait of 2 TCY

00= Wait of 1 TCY

Note 1: WAITB and WAITE bits are ignored whenever WAITM<3:0> = 0000.

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REGISTER 18-3: PMADDR: PARALLEL PORT ADDRESS REGISTER⁽¹⁾

R/W-0

CS2

R/W-0

CS1

R/W-0

ADDR13

ADDR12

ADDR11

ADDR10

ADDR9

ADDR8

bit 15

bit 8

R/W-0

ADDR7

ADDR6

ADDR5

ADDR4

ADDR3

ADDR2

ADDR1

ADDR0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

CS2: Chip Select 2 bit

1= Chip Select 2 is active

0= Chip Select 2 is inactive (pin functions as PMA<15>)

bit 14

CS1: Chip Select 1 bit

1= Chip Select 1 is active

0= Chip Select 1 is inactive (pin functions as PMA<14>)

bit 13-0

ADDR<13:0>: Parallel Port Destination Address bits

Note 1: PMADDR and PMDOUT1 share the same physical register. The register functions as PMDOUT1 only in

Slave modes and as PMADDR only in Master modes.

REGISTER 18-4: PMAEN: PARALLEL PORT ENABLE REGISTER

R/W-0

PTEN15

bit 15

R/W-0

PTEN14

PTEN13

PTEN12

PTEN11

PTEN10

PTEN9

PTEN8

bit 8

R/W-0

PTEN7

bit 7

R/W-0

PTEN6

PTEN5

PTEN4

PTEN3

PTEN2

PTEN1

PTEN0

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-14

bit 13-2

bit 1-0

PTEN<15:14>: PMCSx Strobe Enable bits

1= PMA15 and PMA14 function as either PMA<15:14> or PMCS2 and PMCS1

0= PMA15 and PMA14 function as port I/O

PTEN<13:2>: PMP Address Port Enable bits

1= PMA<13:2> function as PMP address lines

0= PMA<13:2> function as port I/O

PTEN<1:0>: PMALH/PMALL Strobe Enable bits

1= PMA1 and PMA0 function as either PMA<1:0> or PMALH and PMALL

0= PMA1 and PMA0 pads function as port I/O

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REGISTER 18-5: PMSTAT: PARALLEL PORT STATUS REGISTER

R-0

IBF

R/W-0, HS

IBOV

U-0

—

U-0

—

R-0

IB3F

IB2F

IB1F

IB0F

bit 15

bit 8

R-1

R/W-0, HS

OBUF

U-0

—

U-0

—

R-1

OBE

OB3E

OB2E

OB1E

OB0E

bit 0

bit 7

Legend:

HS = Hardware Settable bit

W = Writable bit

R = Readable bit

-n = Value at POR

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

‘1’ = Bit is set

bit 15

bit 14

IBF: Input Buffer Full Status bit

1= All writable Input Buffer registers are full

0= Some or all of the writable Input Buffer registers are empty

IBOV: Input Buffer Overflow Status bit

1= A write attempt to a full Input Byte register occurred (must be cleared in software)

0= No overflow occurred

bit 13-12

bit 11-8

Unimplemented: Read as ‘0’

IB3F:IB0F: Input Buffer n Status Full bit

1= Input buffer contains data that has not been read (reading the buffer will clear this bit)

0= Input buffer does not contain any unread data

bit 7

bit 6

OBE: Output Buffer Empty Status bit

1= All readable Output Buffer registers are empty

0= Some or all of the readable Output Buffer registers are full

OBUF: Output Buffer Underflow Status bit

1= A read occurred from an empty Output Byte register (must be cleared in software)

0= No underflow occurred

bit 5-4

bit 3-0

Unimplemented: Read as ‘0’

OB3E:OB0E: Output Buffer n Status Empty bit

1= Output buffer is empty (writing data to the buffer will clear this bit)

0= Output buffer contains data that has not been transmitted

DS39747F-page 158

 2005-2012 Microchip Technology Inc.

PIC24FJ128GA010 FAMILY

REGISTER 18-6: PADCFG1: PAD CONFIGURATION CONTROL REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

RTSECSEL⁽¹⁾PMPTTL⁽²⁾

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-2

bit 1

Unimplemented: Read as ‘0’

RTSECSEL: RTCC Seconds Clock Output Select bit⁽¹⁾

1= RTCC Seconds Clock is selected for the RTCC pin

0= RTCC Alarm Pulse is selected for the RTCC pin

bit 0

PMPTTL: PMP Module TTL Input Buffer Select bit⁽²⁾

1= PMP module uses TTL input buffers

0= PMP module uses Schmitt input buffers

Note 1: To enable the actual RTCC output, the RTCOE (RCFGCAL<10>) bit needs to be set.

2: Refer to Table 1-2 for affected PMP inputs.

 2005-2012 Microchip Technology Inc.

DS39747F-page 159

PIC24FJ128GA010 FAMILY

FIGURE 18-2:

LEGACY PARALLEL SLAVE PORT EXAMPLE

Address Bus

Data Bus

Master

PMD<7:0>

PIC24F Slave

PMD<7:0>

Control Lines

PMCS

PMRD

PMWR

PMRD

PMWR

FIGURE 18-3:

ADDRESSABLE PARALLEL SLAVE PORT EXAMPLE

PIC24F Slave

Master

PMA<1:0>

Write

Address

Decode

Read

Address

Decode

PMD<7:0>

PMDOUT1L (0)

PMCS

PMDIN1L (0)

PMDIN1H (1)

PMDIN2L (2)

PMDIN2H (3)

PMCS

PMRD

PMWR

PMDOUT1H (1)

PMDOUT2L (2)

PMDOUT2H (3)

PMRD

PMWR

Address Bus

Data Bus

Control Lines

TABLE 18-1: SLAVE MODE ADDRESS RESOLUTION

PMA<1:0>

Output Register (Buffer)

Input Register (Buffer)

00

01

10

11

PMDOUT1<7:0> (0)

PMDOUT1<15:8> (1)

PMDOUT2<7:0> (2)

PMDOUT2<15:8> (3)

PMDIN1<7:0> (0)

PMDIN1<15:8> (1)

PMDIN2<7:0> (2)

PMDIN2<15:8> (3)

FIGURE 18-4:

MASTER MODE, DEMULTIPLEXED ADDRESSING (SEPARATE READ AND

WRITE STROBES, TWO CHIP SELECTS)

PIC24F

PMA<13:0>

PMD<7:0>

PMCS1

PMCS2

Address Bus

PMRD

Data Bus

Control Lines

PMWR

DS39747F-page 160

 2005-2012 Microchip Technology Inc.

PIC24FJ128GA010 FAMILY

FIGURE 18-5:

MASTER MODE, PARTIALLY MULTIPLEXED ADDRESSING (SEPARATE READ

AND WRITE STROBES, TWO CHIP SELECTS)

PMA<13:8>

PIC24F

PMD<7:0>

PMA<7:0>

PMCS1

PMCS2

PMALL

PMRD

Address Bus

Multiplexed

Data and

Address Bus

Control Lines

PMWR

FIGURE 18-6:

MASTER MODE, FULLY MULTIPLEXED ADDRESSING (SEPARATE READ AND

WRITE STROBES, TWO CHIP SELECTS)

PMD<7:0>

PMA<13:8>

PIC24F

PMCS1

PMCS2

PMALL

PMALH

PMRD

PMWR

Multiplexed

Data and

Address Bus

Control Lines

FIGURE 18-7:

EXAMPLE OF A MULTIPLEXED ADDRESSING APPLICATION

PIC24F

A<7:0>

373

PMD<7:0>

A<15:0>

PMALL

D<7:0>

CE

A<15:8>

373

OE

WR

PMALH

PMCS1

PMRD

PMWR

Address Bus

Data Bus

Control Lines

FIGURE 18-8:

EXAMPLE OF A PARTIALLY MULTIPLEXED ADDRESSING APPLICATION

PIC24F

A<7:0>

373

PMD<7:0>

A<14:0>

PMALL

D<7:0>

A<14:8>

CE

OE

PMA<14:7>

WR

Address Bus

Data Bus

PMCS1

PMRD

PMWR

Control Lines

 2005-2012 Microchip Technology Inc.

DS39747F-page 161

PIC24FJ128GA010 FAMILY

FIGURE 18-9:

EXAMPLE OF AN 8-BIT MULTIPLEXED ADDRESS AND DATA APPLICATION

PIC24F

PMD<7:0>

Parallel Peripheral

AD<7:0>

PMALL

PMCS1

PMRD

ALE

CS

Address Bus

Data Bus

RD

PMWR

WR

Control Lines

FIGURE 18-10:

PARALLEL EEPROM EXAMPLE (UP TO 15-BIT ADDRESS, 8-BIT DATA)

PIC24F

Parallel EEPROM

PMA<n:0>

A<n:0>

PMD<7:0>

D<7:0>

PMCS1

PMRD

PMWR

CE

OE

WR

Address Bus

Data Bus

Control Lines

FIGURE 18-11:

PARALLEL EEPROM EXAMPLE (UP TO 15-BIT ADDRESS, 16-BIT DATA)

PIC24F

Parallel EEPROM

A<n:1>

D<7:0>

PMA<n:0>

PMD<7:0>

PMBE

PMCS1

PMRD

A0

CE

OE

WR

Address Bus

Data Bus

PMWR

Control Lines

FIGURE 18-12:

LCD CONTROL EXAMPLE (BYTE MODE OPERATION)

PIC24F

LCD Controller

PM<7:0>

PMA0

D<7:0>

RS

PMRD/PMWR

PMCS1

R/W

E

Address Bus

Data Bus

Control Lines

DS39747F-page 162

 2005-2012 Microchip Technology Inc.

PIC24FJ128GA010 FAMILY

• Calendar: Weekday, Date, Month and Year

• Alarm Configurable

19.0 REAL-TIME CLOCK AND

CALENDAR (RTCC)

• Year Range: 2000 to 2099

Note:

This data sheet summarizes the features of

• Leap Year Correction

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. Refer to Section 29. “Real-Time

Clock and Calendar (RTCC)” (DS39696)

in the “PIC24F Family Reference Manual”

for more information.

• BCD Format for Compact Firmware

• Optimized for Low-Power Operation

• User Calibration with Auto-Adjust

• Calibration Range: ±2.64 Seconds Error per

Month

• Requirements: External 32.768 kHz Clock Crystal

• Alarm Pulse or Seconds Clock Output on RTCC Pin

The Real-Time Clock and Calendar hardware module

has the following features:

• Time: Hours, Minutes and Seconds

• 24-Hour Format (Military Time)

FIGURE 19-1:

RTCC BLOCK DIAGRAM

CPU Clock Domain

RTCC Clock Domain

32.768 kHz Input

from SOSC Oscillator

RCFGCAL

RTCC Prescalers

0.5s

ALCFGRPT

YEAR

MTHDAY

RTCVAL

RTCC Timer

Alarm

WKDYHR

MINSEC

Event

Comparator

ALMTHDY

Compare Registers

with Masks

ALRMVAL

ALWDHR

ALMINSEC

Repeat Counter

RTCC Interrupt

RTCC Interrupt Logic

Alarm Pulse

RTCC Pin

RTCOE

 2005-2012 Microchip Technology Inc.

DS39747F-page 163

PIC24FJ128GA010 FAMILY

By writing the ALRMVALH byte, the Alarm Pointer

19.1 RTCC Module Registers

value, ALRMPTR<1:0>, decrements by one until it

reaches ‘00’. Once it reaches ‘00’, the ALRMMIN and

ALRMSEC value will be accessible through

ALRMVALH and ALRMVALL until the pointer value is

manually changed.

The RTCC module registers are organized into three

categories:

• RTCC Control Registers

• RTCC Value Registers

• Alarm Value Registers

TABLE 19-2: ALRMVAL REGISTER

MAPPING

19.1.1

REGISTER MAPPING

To limit the register interface, the RTCC Timer and

Alarm Time registers are accessed through corre-

sponding register pointers. The RTCC Value register

window (RTCVALH and RTCVALL) uses the RTCPTR

bits (RCFGCAL<9:8>) to select the desired Timer

register pair (see Table 19-1). By writing the RTCVALH

byte, the RTCC Pointer value, RTCPTR<1:0>, decre-

ments by one until it reaches ‘00’. Once it reaches ‘00’,

the MINUTES and SECONDS value will be accessible

through RTCVALH and RTCVALL until the pointer

value is manually changed.

Alarm Value Register Window

ALRMPTR

<1:0>

ALRMVAL<15:8> ALRMVAL<7:0>

00

01

10

11

ALRMMIN

ALRMWD

ALRMMNTH

—

ALRMSEC

ALRMHR

ALRMDAY

—

Considering that the 16-bit core does not distinguish

between 8-bit and 16-bit read operations, the user must

be aware that when reading either the ALRMVALH or

ALRMVALL bytes it will decrement the ALRMPTR<1:0>

value. The same applies to the RTCVALH or RTCVALL

bytes with the RTCPTR<1:0> being decremented.

TABLE 19-1: RTCVAL REGISTER MAPPING

RTCC Value Register Window

RTCPTR

<1:0>

Note:

This only applies to read operations and

not write operations.

RTCVAL<15:8> RTCVAL<7:0>

00

01

10

11

MINUTES

WEEKDAY

MONTH

—

SECONDS

HOURS

DAY

19.1.2

WRITE LOCK

In order to perform a write to any of the RTCC Timer

registers, the RTCWREN bit (RCFGCAL<13>) must be

set (refer to Example 19-1).

YEAR

The Alarm Value register window (ALRMVALH and

ALRMVALL) uses the ALRMPTR bits

(ALCFGRPT<9:8>) to select the desired Alarm register

pair (see Table 19-2).

EXAMPLE 19-1:

SETTING THE RTCWREN BIT IN MPLAB^®C30

asm volatile("disi #13");

asm volatile("push W1");

asm volatile("push W2");

asm volatile("push W3");

asm volatile("MOV #NVMKEY, W1");

asm volatile("MOV #0x55, W2");

asm volatile("MOV #0xAA, W3");

asm volatile("MOV W2, [W1]");

//move the address of NVMKEY into W1

//start 55/AA sequence

NOP();

//There must be an instruction between the two writes ( either a NOP or a MOV to W)

asm volatile("MOV W3, [W1]");

asm volatile("BSET RCFGCAL, #13");

asm volatile("pop W3");

//set the RTCWREN bit

asm volatile("pop W2");

asm volatile("pop W1");

Note:

To avoid accidental writes to the timer, it is recommended that the RTCWREN bit (RCFGCAL<13>) is kept

clear at any other time. For the RTCWREN bit to be set, there is only 1 instruction cycle time window allowed

between the 55h/AA sequence and the setting of RTCWREN; therefore, it is recommended that the code in

Example 19-1 be followed.

DS39747F-page 164

 2005-2012 Microchip Technology Inc.

PIC24FJ128GA010 FAMILY

19.1.3

RTCC CONTROL REGISTERS

REGISTER 19-1:

RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER⁽¹⁾

R/W-0

RTCEN⁽²⁾

bit 15

U-0

R/W-0

R-0

R/W-0

—

RTCWREN

RTCSYNC HALFSEC⁽³⁾

RTCOE

RTCPTR1

RTCPTR0

bit 8

R/W-0

CAL7

R/W-0

CAL6

R/W-0

CAL5

R/W-0

CAL4

R/W-0

CAL3

R/W-0

CAL2

R/W-0

CAL1

R/W-0

CAL0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

RTCEN: RTCC Enable bit⁽²⁾

1= RTCC module is enabled

0= RTCC module is disabled

bit 14

bit 13

Unimplemented: Read as ‘0’

RTCWREN: RTCC Value Registers Write Enable bit

1= RTCVALH and RTCVALL registers can be written to by the user

0= RTCVALH and RTCVALL registers are locked out from being written to by the user

bit 12

RTCSYNC: RTCC Value Registers Read Synchronization bit

1= RTCVALH, RTCVALL and ALCFGRPT registers can change while reading due to a rollover ripple

resulting in an invalid data read. If the register is read twice and results in the same data, the data can

be assumed to be valid.

0= RTCVALH, RTCVALL or ALCFGRPT registers can be read without concern over a rollover ripple

bit 11

bit 10

bit 9-8

HALFSEC: Half-Second Status bit⁽³⁾

1= Second half period of a second

0= First half period of a second

RTCOE: RTCC Output Enable bit

1= RTCC output is enabled

0= RTCC output is disabled

RTCPTR<1:0>: RTCC Value Register Window Pointer bits

Points to the corresponding RTCC Value registers when reading the RTCVALH and RTCVALL registers;

the RTCPTR<1:0> value decrements on every read or write of RTCVALH until it reaches ‘00’.

RTCVAL<15:8>:

00= MINUTES

01= WEEKDAY

10= MONTH

11= Reserved

RTCVAL<7:0>:

00= SECONDS

01= HOURS

10= DAY

11= YEAR

Note 1: The RCFGCAL Reset value is dependent on the type of Reset.

2: A write to the RTCEN bit is only allowed when RTCWREN = 1.

3: This bit is read-only; it is cleared to ‘0’ on a write to the lower half of the MINSEC register.

 2005-2012 Microchip Technology Inc.

DS39747F-page 165

PIC24FJ128GA010 FAMILY

REGISTER 19-1:

RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER⁽¹⁾

bit 7-0 CAL<7:0>: RTC Drift Calibration bits

01111111= Maximum positive adjustment; adds 508 RTC clock pulses every one minute

...

01111111= Minimum positive adjustment; adds 4 RTC clock pulses every one minute

00000000= No adjustment

11111111= Minimum negative adjustment; subtracts 4 RTC clock pulses every one minute

...

10000000= Maximum negative adjustment; subtracts 512 RTC clock pulses every one minute

Note 1: The RCFGCAL Reset value is dependent on the type of Reset.

2: A write to the RTCEN bit is only allowed when RTCWREN = 1.

3: This bit is read-only; it is cleared to ‘0’ on a write to the lower half of the MINSEC register.

REGISTER 19-2: PADCFG1: PAD CONFIGURATION CONTROL REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

RTSECSEL⁽¹⁾PMPTTL⁽²⁾

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-2

bit 1

Unimplemented: Read as ‘0’

RTSECSEL: RTCC Seconds Clock Output Select bit⁽¹⁾

1= RTCC seconds clock is selected for the RTCC pin

0= RTCC alarm pulse is selected for the RTCC pin

bit 0

PMPTTL: PMP Module TTL Input Buffer Select bit⁽²⁾

1= PMP module uses TTL input buffers

0= PMP module uses Schmitt input buffers

Note 1: To enable the actual RTCC output, the RTCOE (RCFGCAL<10>) bit needs to be set.

2: Refer to Table 1-2 for affected PMP inputs.

DS39747F-page 166

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PIC24FJ128GA010 FAMILY

REGISTER 19-3: ALCFGRPT: ALARM CONFIGURATION REGISTER

R/W-0

ALRMEN

bit 15

R/W-0

CHIME

AMASK3

AMASK2

AMASK1

AMASK0

ALRMPTR1 ALRMPTR0

bit 8

R/W-0

ARPT7

bit 7

R/W-0

ARPT6

ARPT5

ARPT4

ARPT3

ARPT2

ARPT1

ARPT0

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

ALRMEN: Alarm Enable bit

1= Alarm is enabled (cleared automatically after an alarm event whenever ARPT<7:0> = 00 and

CHIME = 0)

0= Alarm is disabled

bit 14

CHIME: Chime Enable bit

1= Chime is enabled; ARPT<7:0> bits are allowed to roll over from 00h to FFh

0= Chime is disabled; ARPT<7:0> bits stop once they reach 00h

bit 13-10

AMASK<3:0>: Alarm Mask Configuration bits

0000= Every half second

0001= Every second

0010= Every 10 seconds

0011= Every minute

0100= Every 10 minutes

0101= Every hour

0110= Once a day

0111= Once a week

1000= Once a month

1001= Once a year (except when configured for February 29th, once every 4 years)

101x= Reserved – do not use

11xx= Reserved – do not use

bit 9-8

ALRMPTR<1:0>: Alarm Value Register Window Pointer bits

Points to the corresponding Alarm Value registers when reading ALRMVALH and ALRMVALL registers;

the ALRMPTR<1:0> value decrements on every read or write of ALRMVALH until it reaches ‘00’.

ALRMVAL<15:8>:

00= ALRMMIN

01= ALRMWD

10= ALRMMNTH

11= Unimplemented

ALRMVAL<7:0>:

00= ALRMSEC

01= ALRMHR

10= ALRMDAY

11= Unimplemented

bit 7-0

ARPT<7:0>: Alarm Repeat Counter Value bits

11111111= Alarm will repeat 255 more times

...

00000000= Alarm will not repeat

The counter decrements on any alarm event. The counter is prevented from rolling over from 00h to FFh

unless CHIME = 1.

 2005-2012 Microchip Technology Inc.

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19.1.4

RTCVAL REGISTER MAPPINGS

REGISTER 19-4: YEAR: YEAR VALUE REGISTER⁽¹⁾

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/W-x

YRTEN3

YRTEN2

YRTEN1

YRTEN0

YRONE3

YRONE2

YRONE1

YRONE0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

bit 7-4

bit 3-0

Unimplemented: Read as ‘0’

YRTEN<3:0:> Binary Coded Decimal Value of Year’s Tens Digit; Contains a value from 0 to 9

YRONE<3:0>: Binary Coded Decimal Value of Year’s Ones Digit; Contains a value from 0 to 9

Note 1: A write to the YEAR register is only allowed when RTCWREN = 1.

REGISTER 19-5: MTHDY: MONTH AND DAY VALUE REGISTER⁽¹⁾

U-0

—

U-0

—

U-0

—

R/W-x

MTHONE0

bit 8

MTHTEN0

MTHONE3

MTHONE2

MTHONE1

bit 15

U-0

—

U-0

—

R/W-x

DAYTEN1

DAYTEN0

DAYONE3

DAYONE2

DAYONE1

DAYONE0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-13

bit 12

Unimplemented: Read as ‘0’

MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit; Contains a value of 0 or 1

bit 11-8

bit 7-6

bit 5-4

bit 3-0

MTHONE<3:0>: Binary Coded Decimal Value of Month’s Ones Digit; Contains a value from 0 to 9

Unimplemented: Read as ‘0’

DAYTEN<1:0>: Binary Coded Decimal Value of Day’s Tens Digit; Contains a value from 0 to 3

DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit; Contains a value from 0 to 9

Note 1: A write to this register is only allowed when RTCWREN = 1.

DS39747F-page 168

 2005-2012 Microchip Technology Inc.

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REGISTER 19-6: WKDYHR: WEEKDAY AND HOURS VALUE REGISTER⁽¹⁾

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-x

WDAY2

WDAY1

WDAY0

bit 15

bit 8

U-0

—

U-0

—

R/W-x

HRTEN1

HRTEN0

HRONE3

HRONE2

HRONE1

HRONE0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-11

bit 10-8

bit 7-6

Unimplemented: Read as ‘0’

WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit; Contains a value from 0 to 6

Unimplemented: Read as ‘0’

bit 5-4

HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit; Contains a value from 0 to 2

HRONE<3:0>: Binary Coded Decimal Value of Hour’s Ones Digit; Contains a value from 0 to 9

bit 3-0

Note 1: A write to this register is only allowed when RTCWREN = 1.

REGISTER 19-7: MINSEC: MINUTES AND SECONDS VALUE REGISTER

U-0

—

R/W-x

MINONE0

bit 8

MINTEN2

MINTEN1

MINTEN0

MINONE3

MINONE2

MINONE1

bit 15

U-0

—

R/W-x

SECTEN2

SECTEN1

SECTEN0

SECONE3

SECONE2

SECONE1

SECONE0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

bit 14-12

bit 11-8

bit 7

MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit; Contains a value from 0 to 5

MINONE<3:0>: Binary Coded Decimal Value of Minute’s Ones Digit; Contains a value from 0 to 9

Unimplemented: Read as ‘0’

bit 6-4

bit 3-0

SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit; Contains a value from 0 to 5

SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit; Contains a value from 0 to 9

 2005-2012 Microchip Technology Inc.

DS39747F-page 169

PIC24FJ128GA010 FAMILY

19.1.5

ALRMVAL REGISTER MAPPINGS

REGISTER 19-8: ALMTHDY: ALARM MONTH AND DAY VALUE REGISTER⁽¹⁾

U-0

—

U-0

—

U-0

—

R/W-x

MTHTEN0

MTHONE3

MTHONE2

MTHONE1

MTHONE0

bit 15

bit 8

U-0

—

U-0

—

R/W-x

DAYTEN1

DAYTEN0

DAYONE3

DAYONE2

DAYONE1

DAYONE0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-13

bit 12

Unimplemented: Read as ‘0’

MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit; Contains a value of 0 or 1

bit 11-8

bit 7-6

bit 5-4

bit 3-0

MTHONE<3:0>: Binary Coded Decimal Value of Month’s Ones Digit; Contains a value from 0 to 9

Unimplemented: Read as ‘0’

DAYTEN<1:0>: Binary Coded Decimal Value of Day’s Tens Digit; Contains a value from 0 to 3

DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit; Contains a value from 0 to 9

Note 1: A write to this register is only allowed when RTCWREN = 1.

REGISTER 19-9: ALWDHR: ALARM WEEKDAY AND HOURS VALUE REGISTER⁽¹⁾

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-x

WDAY0

bit 8

WDAY2

WDAY1

bit 15

U-0

—

U-0

—

R/W-x

HRTEN1

HRTEN0

HRONE3

HRONE2

HRONE1

HRONE0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-11

bit 10-8

bit 7-6

Unimplemented: Read as ‘0’

WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit; Contains a value from 0 to 6

Unimplemented: Read as ‘0’

bit 5-4

HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit; Contains a value from 0 to 2

HRONE<3:0>: Binary Coded Decimal Value of Hour’s Ones Digit; Contains a value from 0 to 9

bit 3-0

Note 1: A write to this register is only allowed when RTCWREN = 1.

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REGISTER 19-10: ALMINSEC: ALARM MINUTES AND SECONDS VALUE REGISTER

U-0

—

R/W-x

MINTEN2

MINTEN1

MINTEN0

MINONE3

MINONE2

MINONE1

MINONE0

bit 15

bit 8

U-0

—

R/W-x

SECTEN2

SECTEN1

SECTEN0

SECONE3

SECONE2

SECONE1

SECONE0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

bit 14-12

bit 11-8

bit 7

MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit; Contains a value from 0 to 5

MINONE<3:0>: Binary Coded Decimal Value of Minute’s Ones Digit; Contains a value from 0 to 9

Unimplemented: Read as ‘0’

bit 6-4

bit 3-0

SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit; Contains a value from 0 to 5

SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit; Contains a value from 0 to 9

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19.2 Calibration

19.3 Alarm

The real-time crystal input can be calibrated using the

periodic auto-adjust feature. When properly calibrated,

the RTCC can provide an error of less than 3 seconds

per month. This is accomplished by finding the number

of error clock pulses and storing the value into the

lower half of the RCFGCAL register. The 8-bit signed

value loaded into the lower half of RCFGCAL is multi-

plied by four and will either be added or subtracted from

the RTCC timer, once every minute. Refer to the steps

below for RTCC calibration:

• Configurable from half second to one year

• Enabled using the ALRMEN bit

(ALCFGRPT<15>, Register 19-3)

• One-time alarm and repeat alarm options are

available

19.3.1

CONFIGURING THE ALARM

The alarm feature is enabled using the ALRMEN bit.

This bit is cleared when an alarm is issued. Writes to

ALRMVALH:ALRMVALL should only take place when

ALRMEN = 0.

1. Using another timer resource on the device, the

user must find the error of the 32.768 kHz

crystal.

As shown in Figure 19-2, the interval selection of the

alarm is configured through the AMASK bits

(ALCFGRPT<13:10>). These bits determine which and

how many digits of the alarm must match the clock value

for the alarm to occur. The alarm can also be configured

to repeat, based on a preconfigured interval. The

amount of times this occurs, once the alarm is enabled,

is stored in the lower half of the ALCFGRPT register.

2. Once the error is known, it must be converted to

the number of error clock pulses per minute.

EQUATION 19-1:

†

(Ideal Frequency – Measured Frequency) * 60 = Clocks per Minute

† Ideal Frequency = 32,768 Hz

When ALCFGRPT

=

00 and the CHIME

(ALCFGRPT<14>) bit = 0, the repeat function is

disabled and only a single alarm will occur. The alarm

can be repeated up to 255 times by loading the lower

half of the ALCFGRPT register with FFh.

3. a) If the oscillator is faster then ideal (negative

result form Step 2), the RCFGCAL register value

needs to be negative. This causes the specified

number of clock pulses to be subtracted from

the timer counter, once every minute.

After each alarm is issued, the ALCFGRPT register is

decremented by one. Once the register has reached

‘00’, the alarm will be issued one last time, after which,

the ALRMEN bit will be cleared automatically and the

alarm will turn off. Indefinite repetition of the alarm can

occur if the CHIME bit = 1. Instead of the alarm being

disabled when the ALCFGRPT register reaches ‘00’, it

will roll over to FF and continue counting indefinitely

when CHIME = 1.

b) If the oscillator is slower then ideal (positive

result from Step 2), the RCFGCAL register value

needs to be positive. This causes the specified

number of clock pulses to be subtracted from

the timer counter, once every minute.

4. Divide the number of error clocks per minute by

4 to get the correct CAL value and load the

RCFGCAL register with the correct value. (Each

1-bit increment in CAL adds or subtracts

4 pulses). Load the RCFGCAL register with the

correct value.

19.3.2

ALARM INTERRUPT

At every alarm event an interrupt is generated. In addi-

tion, an alarm pulse output is provided that operates at

half the frequency of the alarm. This output is

completely synchronous to the RTCC clock and can be

used as a trigger clock to other peripherals.

Writes to the lower half of the RCFGCAL register

should only occur when the timer is turned off or

immediately after the rising edge of the seconds pulse.

Note:

Changing any of the registers, other then

the RCFGCAL and ALCFGRPT registers,

and the CHIME bit while the alarm is

enabled (ALRMEN = 1), can result in a

false alarm event leading to a false alarm

interrupt. To avoid a false alarm event, the

timer and alarm values should only be

changed while the alarm is disabled

(ALRMEN = 0). It is recommended that

the ALCFGRPT register and CHIME bit be

changed when RTCSYNC = 0.

Note:

It is up to the user to include in the error

value, the initial error of the crystal drift

due to temperature and drift due to crystal

aging.

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FIGURE 19-2:

ALARM MASK SETTINGS

Day of

the

Week

Alarm Mask Setting

(AMASK<3:0>)

Month

Day

Hours

Minutes

Seconds

0000– Every half second

0001– Every second

0010– Every 10 seconds

0011– Every minute

0100– Every 10 minutes

0101– Every hour

s

m

0110– Every day

h

0111– Every week

1000– Every month

d

(1)

1001– Every year

m

d

Note 1: Annually, except when configured for February 29.

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NOTES:

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20.2 Overview

20.0 PROGRAMMABLE CYCLIC

REDUNDANCY CHECK (CRC)

GENERATOR

The module implements a software configurable CRC

generator. The terms of the polynomial and its length

can be programmed using the CRCXOR (X<15:1>) bits

and the CRCCON (PLEN<3:0>) bits, respectively.

Note:

This data sheet summarizes the features of

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. Refer to Section 30. “Program-

mable Cyclic Redundancy Check

(CRC)” (DS39714) in the “PIC24F Family

Reference Manual” for more information.

Consider the following equation:

EQUATION 20-1: CRC POLYNOMIAL

x¹⁶+ x¹²+ x⁵+ 1

To program this polynomial into the CRC generator,

the CRC register bits should be set, as shown in

Table 20-1.

The programmable CRC generator offers the following

features:

• User-programmable polynomial CRC equation

• Interrupt output

TABLE 20-1: EXAMPLE CRC SETUP

• Data FIFO

Bit Name

Bit Value

PLEN<3:0>

X<15:1>

1111

20.1 Registers

000100000010000

There are four registers used to control programmable

CRC operation:

Note that for the value of X<15:1>, the 12th bit and the

5th bit are set to ‘1’, as required by the equation. The

0 bit, required by the equation, is always XORed. For a

16-bit polynomial, the 16th bit is also always assumed to

be XORed; therefore, the X<15:1> bits do not have the

0 bit or the 16th bit.

• CRCCON

• CRCXOR

• CRCDAT

• CRCWDAT

The topology of a standard CRC generator is shown in

Figure 20-2.

FIGURE 20-1:

CRC SHIFTER DETAILS

PLEN<3:0>

0

1

2

15

CRC Shift Register

Hold

X2

Hold

X1

X3

X15

0

XOR

OUT

IN

BIT 0

IN

BIT 1

IN

BIT 2

IN

BIT 15

DOUT

1

p_clk

CRC Read Bus

CRC Write Bus

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FIGURE 20-2:

CRC GENERATOR RECONFIGURED FOR x¹⁶+ x¹²+ x⁵+ 1

XOR

D

Q

D

Q

D

Q

D

Q

D

Q

SDOx

BIT 0

BIT 4

BIT 5

BIT 12

BIT 15

p_clk

CRC Read Bus

CRC Write Bus

To continually feed data into the CRC engine, the rec-

ommended mode of operation is to initially “prime” the

FIFO with a sufficient number of words, so no interrupt

is generated before the next word can be written. Once

that is done, start the CRC by setting the CRCGO bit to

‘1’. From that point onward, the VWORD bits should be

polled. If they read less than 8 or 16, another word can

be written into the FIFO.

20.3 User Interface

20.3.1

DATA INTERFACE

To start serial shifting, a ‘1’ must be written to the

CRCGO bit.

The module incorporates a FIFO that is 8-deep when

PLEN<3:0> (CRCCON<3:0>) > 7 and 16-deep other-

wise. The data for which the CRC is to be calculated

must first be written into the FIFO. The smallest data

element that can be written into the FIFO is one byte.

For example, if PLEN = 5, then the size of the data is

PLEN + 1 = 6. The data must be written as follows:

To empty words already written into a FIFO, the

CRCGO bit must be set to ‘1’ and the CRC shifter

allowed to run until the CRCMPT bit is set.

Also, to get the correct CRC reading, it will be

necessary to wait for the CRCMPT bit to go high before

reading the CRCWDAT register.

data[5:0] = crc_input[5:0]

data[7:6] = ‘bxx

If a word is written when the CRCFUL bit is set, the

VWORD Pointer will roll over to 0. The hardware will

then behave as if the FIFO is empty. However, the con-

dition to generate an interrupt will not be met; therefore,

no interrupt will be generated (see Section 20.3.2

“Interrupt Operation”).

Once data is written into the CRCWDAT MSb (as

defined by PLEN), the value of the VWORD<4:0> bits

(CRCCON<12:8>) increment by one. The serial shifter

starts shifting data into the CRC engine when

CRCGO = 1 and VWORD > 0. When the MSb is

shifted out, VWORD decrements by one. The serial

shifter continues shifting until the VWORD reaches 0.

Therefore, for a given value of PLEN, it will take

(PLEN<3:0> + 1)/2 x VWORD number of clock cycles

to complete the CRC calculations.

At least one instruction cycle must pass after a write to

CRCWDAT before a read of the VWORD bits is done.

20.3.2

INTERRUPT OPERATION

When VWORD<4:0> make a transition from a value of

‘1’ to ‘0’, an interrupt will be generated.

When VWORD reaches 8 (or 16), the CRCFUL bit will

be set. When VWORD reaches 0, the CRCMPT bit will

be set.

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REGISTER 20-1: CRCCON: CRC CONTROL REGISTER

U-0

—

U-0

—

R/W-0

CSIDL

R-0

VWORD4

VWORD3

VWORD2

VWORD1

VWORD0

bit 15

bit 8

R-0

CRCFUL

bit 7

R-1

U-0

—

R/W-0

CRCMPT

CRCGO

PLEN3

PLEN2

PLEN1

PLEN0

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-14

bit 13

Unimplemented: Read as ‘0’

CSIDL: CRC Stop in Idle Mode bit

1= Discontinues module operation when the device enters Idle mode

0= Continues module operation in Idle mode

bit 12-8

bit 7

VWORD<4:0>: Pointer Value bits

Indicates the number of valid words in the FIFO. It has a maximum value of 8 when PLEN<3:0> > 7

or 16 when PLEN<3:0> 7.

CRCFUL: FIFO Full bit

1= FIFO is full

0= FIFO is not full

bit 6

CRCMPT: FIFO Empty bit

1= FIFO is empty

0= FIFO is not empty

bit 5

bit 4

Unimplemented: Read as ‘0’

CRCGO: Start CRC bit

1= Starts CRC serial shifter

0= CRC serial shifter is turned off

bit 3-0

PLEN<3:0>: Polynomial Length bits

Denotes the length of the polynomial to be generated minus 1.

20.4.2

IDLE MODE

20.4 Operation in Power Save Modes

To continue full module operation in Idle mode, the

CSIDL bit must be cleared prior to entry into the mode.

20.4.1

SLEEP MODE

If Sleep mode is entered while the module is operating,

the module will be suspended in its current state until

clock execution resumes.

If CSIDL = 1, the module will behave the same way as

it does in Sleep mode. Pending interrupt events will be

passed on, even though the module clocks are not

available.

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NOTES:

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A block diagram of the A/D Converter is shown in

Figure 21-1.

21.0 10-BIT HIGH-SPEED A/D

CONVERTER

To perform an A/D conversion:

Note:

This data sheet summarizes the features of

1. Configure the A/D module:

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. Refer to Section 17. “10-Bit A/D

Converter” (DS39705) in the “PIC24F

Family Reference Manual” for more

information.

a) Select the port pins as analog inputs

(AD1PCFG<15:0>).

b) Select a voltage reference source to match

the expected range on the analog inputs

(AD1CON2<15:13>).

c) Select the analog conversion clock to match

the desired data rate with the processor clock

(AD1CON3<7:0>).

The 10-bit A/D Converter has the following key

features:

• Successive Approximation (SAR) conversion

• Conversion speeds of up to 500 ksps

• Up to 16 analog input pins

d) Select the appropriate sample/conver-

sion sequence (AD1CON1<7:0> and

AD1CON3<12:8>).

e) Select how conversion results are

presented in the buffer (AD1CON1<9:8>).

• External voltage reference input pins

• Automatic Channel Scan mode

f) Select the interrupt rate (AD1CON2<5:2>).

g) Turn on the A/D module (AD1CON1<15>).

2. Configure the A/D interrupt (if required):

a) Clear the AD1IF bit.

• Selectable conversion trigger source

• 16-word conversion result buffer

• Selectable Buffer Fill modes

• Four result alignment options

b) Select the A/D interrupt priority.

• Operation during CPU Sleep and Idle modes

Note:

A/D results should be read with the ADON

bit = 1. If the A/D is disabled before

reading the buffer, it is possible to lose

data.

Depending on the particular device pinout, the 10-bit

A/D Converter can have up to 16 analog input pins,

designated AN0 through AN15. In addition, there are

two analog input pins for external voltage reference

connections. These voltage reference inputs may be

shared with other analog input pins. The actual number

of analog input pins and external voltage reference

input configuration will depend on the device. Refer to

the specific device data sheet for further details.

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Figure 21-1: 10-BIT HIGH-SPEED A/D CONVERTER BLOCK DIAGRAM

Internal Data Bus

16

AVDD

VR+

AVSS

VREF+

VR-

Comparator

VREF-

VINH

VR- VR+

S/H

DAC

VINL

AN0

AN1

AN2

VINH

10-Bit SAR

Conversion Logic

AN3

Data Formatting

AN4

AN5

VINL

AN6

AN7

ADC1BUF0:

ADC1BUFF

AN8

AD1CON1

AD1CON2

AD1CON3

AD1CHS

AN9

VINH

VINL

AN10

AN11

AN12

AN13

AN14

AN15

AD1PCFG

AD1CSSL

Sample Control

Control Logic

Conversion Control

Input MUX Control

Pin Config. Control

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REGISTER 21-1: AD1CON1: A/D CONTROL REGISTER 1

R/W-0

ADON⁽¹⁾

bit 15

U-0

—

R/W-0

U-0

—

U-0

—

U-0

—

R/W-0

ADSIDL

FORM1

FORM0

bit 8

R/W-0

SSRC2

bit 7

R/W-0

U-0

—

U-0

—

R/W-0

ASAM

R/W-0, HCS R/C-0, HCS

SAMP DONE

bit 0

SSRC1

SSRC0

Legend:

C = Clearable bit

W = Writable bit

‘1’ = Bit is set

HCS = Hardware Clearable/Settable bit

U = Unimplemented bit, read as ‘0’

R = Readable bit

-n = Value at POR

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

ADON: A/D Operating Mode bit⁽¹⁾

1= A/D Converter module is operating

0= A/D Converter is off

bit 14

bit 13

Unimplemented: Read as ‘0’

ADSIDL: Stop in Idle Mode bit

1= Discontinues module operation when the device enters Idle mode

0= Continues module operation in Idle mode

bit 12-10

bit 9-8

Unimplemented: Read as ‘0’

FORM<1:0>: Data Output Format bits

11= Signed fractional (sddd dddd dd00 0000)

10= Fractional (dddd dddd dd00 0000)

01= Signed integer (ssss sssd dddd dddd)

00= Integer (0000 00dd dddd dddd)

bit 7-5

SSRC<2:0>: Conversion Trigger Source Select bits

111= Internal counter ends sampling and starts conversion (auto-convert)

110= Reserved

10x= Reserved

011= Reserved

010= Timer3 compare ends sampling and starts conversion

001= Active transition on the INT0 pin ends sampling and starts conversion

000= Clearing the SAMP bit ends sampling and starts conversion

bit 4-3

bit 2

Unimplemented: Read as ‘0’

ASAM: A/D Sample Auto-Start bit

1= Sampling begins immediately after the last conversion completes; SAMP bit is auto-set

0= Sampling begins when the SAMP bit is set

bit 1

bit 0

SAMP: A/D Sample Enable bit

1= A/D Sample-and-Hold amplifier is sampling input

0= A/D Sample-and-Hold amplifier is holding

DONE: A/D Conversion Status bit

1= A/D conversion is done

0= A/D conversion is NOT done

Note 1: The values of the ADC1BUFx registers will not retain their values once the ADON bit is cleared. Read out

the conversion values from the buffer before disabling the module.

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REGISTER 21-2: AD1CON2: A/D CONTROL REGISTER 2

R/W-0

U-0

r

U-0

—

R/W-0

U-0

—

U-0

—

VCFG2

VCFG1

VCFG0

CSCNA

bit 15

bit 8

R-0

U-0

—

R/W-0

SMPI3

R/W-0

SMPI2

R/W-0

SMPI1

R/W-0

SMPI0

R/W-0

BUFM

R/W-0

ALTS

BUFS

bit 7

bit 0

Legend:

r = Reserved bit

W = Writable bit

‘1’ = Bit is set

R = Readable bit

-n = Value at POR

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

VCFG<2:0>: Voltage Reference Configuration bits:

VCFG<2:0>

VR+

VR-

000

001

010

011

1xx

AVDD

External VREF+ pin

AVDD

AVSS

External VREF- pin

AVSS

External VREF+ pin

AVDD

bit 12

bit 11

bit 10

Reserved

Unimplemented: Read as ‘0’

CSCNA: Scan Input Selections for CH0+ S/H Input for MUX A Input Multiplexor Setting bit

1= Scan inputs

0= Do not scan inputs

bit 9-8

bit 7

Unimplemented: Read as ‘0’

BUFS: Buffer Fill Status bit (valid only when BUFM = 1)

1= A/D is currently filling Buffer 08-0F, user should access data in 00-07

0= A/D is currently filling Buffer 00-07, user should access data in 08-0F

bit 6

Unimplemented: Read as ‘0’

bit 5-2

SMPI<3:0>: Sample/Convert Sequences Per Interrupt Selection bits

1111 = Interrupts at the completion of conversion for each 16th sample/convert sequence

1110 = Interrupts at the completion of conversion for each 15th sample/convert sequence

.....

0001 = Interrupts at the completion of conversion for each 2nd sample/convert sequence

0000 = Interrupts at the completion of conversion for each sample/convert sequence

bit 1

bit 0

BUFM: Buffer Mode Select bit

1 = Buffer configured as two 8-word buffers (ADC1BUFx<15:8> and ADC1BUFx<7:0>)

0 = Buffer configured as one 16-word buffer (ADC1BUFx<15:0>)

ALTS: Alternate Input Sample Mode Select bit

1= Uses MUX A input multiplexor settings for the first sample, then alternates between the MUX B and

MUX A input multiplexor settings for all subsequent samples

0= Always uses MUX A input multiplexor settings

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REGISTER 21-3: AD1CON3: A/D CONTROL REGISTER 3

R/W-0

ADRC

U-0

—

U-0

—

R/W-0

SAMC4

SAMC3

SAMC2

SAMC1

SAMC0

bit 15

bit 8

R/W-0

ADCS7

ADCS6

ADCS5

ADCS4

ADCS3

ADCS2

ADCS1

ADCS0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

ADRC: A/D Conversion Clock Source bit

1= A/D internal RC clock

0= Clock is derived from the system clock

bit 14-13

bit 12-8

Unimplemented: Read as ‘0’

SAMC<4:0>: Auto-Sample Time bits

11111= 31 TAD

·····

00001= 1 TAD

00000= 0 TAD (not recommended)

bit 7-0

ADCS<7:0:> A/D Conversion Clock Select bits

11111111

····· = Reserved

01000000

00111111 = 64 * TCY

·····

00000001 = 2 * TCY

00000000 = TCY

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REGISTER 21-4: AD1CHS: A/D INPUT SELECT REGISTER

R/W-0

U-0

—

U-0

—

U-0

—

R/W-0

CH0NB

CH0SB3

CH0SB2

CH0SB1

CH0SB0

bit 15

bit 8

R/W-0

U-0

—

U-0

—

U-0

—

R/W-0

CH0NA

CH0SA3

CH0SA2

CH0SA1

CH0SA0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

CH0NB: Channel 0 Negative Input Select for MUX B Multiplexor Setting bit

1= Channel 0 negative input is AN1

0= Channel 0 negative input is VR-

bit 14-12

bit 11-8

Unimplemented: Read as ‘0’

CH0SB<3:0>: Channel 0 Positive Input Select for MUX B Multiplexor Setting bits

1111= Channel 0 positive input is AN15

1110= Channel 0 positive input is AN14

·····

0001= Channel 0 positive input is AN1

0000= Channel 0 positive input is AN0

bit 7

CH0NA: Channel 0 Negative Input Select for MUX A Multiplexor Setting bit

1= Channel 0 negative input is AN1

0= Channel 0 negative input is VR-

bit 6-4

bit 3-0

Unimplemented: Read as ‘0’

CH0SA<3:0>: Channel 0 Positive Input Select for MUX A Multiplexor Setting bits

1111= Channel 0 positive input is AN15

1110= Channel 0 positive input is AN14

·····

0001= Channel 0 positive input is AN1

0000= Channel 0 positive input is AN0

DS39747F-page 184

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PIC24FJ128GA010 FAMILY

REGISTER 21-5: AD1PCFG: A/D PORT CONFIGURATION REGISTER

R/W-0

PCFG15

bit 15

R/W-0

PCFG14

PCFG13

PCFG12

PCFG11

PCFG10

PCFG9

PCFG8

bit 8

R/W-0

PCFG7

bit 7

R/W-0

PCFG6

PCFG5

PCFG4

PCFG3

PCFG2

PCFG1

PCFG0

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-0

PCFG<15:0>: Analog Input Pin Configuration Control bits

1= Pin for corresponding analog channel is configured in Digital mode; I/O port read is enabled

0= Pin configured in Analog mode; I/O port read is disabled, A/D samples pin voltage

REGISTER 21-6: AD1CSSL: A/D INPUT SCAN SELECT REGISTER

R/W-0

CSSL8

bit 8

CSSL15

CSSL14

CSSL13

CSSL12

CSSL11

CSSL10

CSSL9

bit 15

R/W-0

CSSL7

CSSL6

CSSL5

CSSL4

CSSL3

CSSL2

CSSL1

CSSL0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-0

CSSL<15:0>: A/D Input Pin Scan Selection bits

1= Corresponding analog channel is selected for input scan

0= Analog channel is omitted from input scan

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DS39747F-page 185

PIC24FJ128GA010 FAMILY

EQUATION 21-1: A/D CONVERSION CLOCK PERIOD⁽¹⁾

TAD = TCY(ADCS + 1)

TAD

– 1

ADCS =

TCY

Note 1: Based on TCY = TOSC * 2; Doze mode and PLL are disabled.

FIGURE 21-2:

10-BIT A/D CONVERTER ANALOG INPUT MODEL

VDD

RIC  250

Sampling

RSS  5 k(Typical)

Switch

VT = 0.6V

ANx

RSS

Rs

CHOLD

= DAC Capacitance

= 4.4 pF (Typical)

VA

CPIN

6-11 pF

ILEAKAGE

500 nA

VT = 0.6V

(Typical)

VSS

Legend: CPIN

VT

= Input Capacitance

= Threshold Voltage

ILEAKAGE = Leakage Current at the pin due to

various junctions

RIC

= Interconnect Resistance

RSS

= Sampling Switch Resistance

= Sample/Hold Capacitance (from DAC)

CHOLD

Note: CPIN value depends on the device package and is not tested. The effect of CPIN is negligible if Rs  5 k.

DS39747F-page 186

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PIC24FJ128GA010 FAMILY

FIGURE 21-3:

A/D TRANSFER FUNCTION

Output Code

(Binary (Decimal))

11 1111 1111(1023)

11 1111 1110(1022)

10 0000 0011(515)

10 0000 0010(514)

10 0000 0001(513)

10 0000 0000(512)

01 1111 1111(511)

01 1111 1110(510)

01 1111 1101(509)

00 0000 0001(1)

00 0000 0000(0)

Voltage Level

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PIC24FJ128GA010 FAMILY

NOTES:

DS39747F-page 188

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PIC24FJ128GA010 FAMILY

The analog comparator module contains two

comparators that can be configured in a variety of

22.0 COMPARATOR MODULE

Note:

This data sheet summarizes the features of

ways. The inputs can be selected from the analog

inputs, multiplexed with I/O pins, as well as the on-chip

voltage reference. Block diagrams of the various

comparator configurations are shown in Figure 22-1.

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. Refer to Section 19. “Comparator

Module” (DS39710) in the “PIC24F Family

Reference Manual” for more information.

FIGURE 22-1:

COMPARATOR I/O OPERATING MODES

C1NEG

CMCON<6>

C1EN

C1

C1INV

C1IN+

C1IN-

VIN-

VIN+

C1OUT

C1POS

C1IN+

CVREF

C1OUTEN

C2NEG

C2POS

CMCON<7>

C2EN

C2

C2INV

C2IN+

C2IN-

VIN-

VIN+

C2OUT

C2IN+

CVREF

C2OUTEN

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PIC24FJ128GA010 FAMILY

REGISTER 22-1: CMCON: COMPARATOR CONTROL REGISTER

R/W-0

U-0

—

R/C-0

R/W-0

C2EN

R/W-0

C1EN

R/W-0

CMIDL

C2EVT

C1EVT

C2OUTEN

C1OUTEN

bit 15

bit 8

R-0

R/W-0

C2INV

R/W-0

C1INV

R/W-0

C2OUT

C1OUT

C2NEG

C2POS

C1NEG

C1POS

bit 7

bit 0

Legend:

C = Clearable bit

W = Writable bit

‘1’ = Bit is set

R = Readable bit

-n = Value at POR

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

CMIDL: Stop in Idle Mode bit

1= When the device enters Idle mode, the module does not generate interrupts; module is still enabled

0= Continues normal module operation in Idle mode

bit 14

bit 13

Unimplemented: Read as ‘0’

C2EVT: Comparator 2 Event bit

1= Comparator output changed states

0= Comparator output did not change states

bit 12

bit 11

bit 10

bit 9

C1EVT: Comparator 1 Event bit

1= Comparator output changed states

0= Comparator output did not change states

C2EN: Comparator 2 Enable bit

1= Comparator is enabled

0= Comparator is disabled

C1EN: Comparator 1 Enable bit

1= Comparator is enabled

0= Comparator is disabled

C2OUTEN: Comparator 2 Output Enable bit

1= Comparator output is driven on the output pad

0= Comparator output is not driven on the output pad

bit 8

C1OUTEN: Comparator 1 Output Enable bit

1= Comparator output is driven on the output pad

0= Comparator output is not driven on the output pad

bit 7

C2OUT: Comparator 2 Output bit

When C2INV = 0:

1= C2 VIN+ > C2 VIN-

0= C2 VIN+ < C2 VIN-

When C2INV = 1:

0= C2 VIN+ > C2 VIN-

1= C2 VIN+ < C2 VIN-

bit 6

C1OUT: Comparator 1 Output bit

When C1INV = 0:

1= C1 VIN+ > C1 VIN-

0= C1 VIN+ < C1 VIN-

When C1INV = 1:

0= C1 VIN+ > C1 VIN-

1= C1 VIN+ < C1 VIN-

DS39747F-page 190

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PIC24FJ128GA010 FAMILY

REGISTER 22-1: CMCON: COMPARATOR CONTROL REGISTER (CONTINUED)

bit 5

bit 4

bit 3

C2INV: Comparator 2 Output Inversion bit

1= C2 output is inverted

0= C2 output is not inverted

C1INV: Comparator 1 Output Inversion bit

1= C1 output is inverted

0= C1 output is not inverted

C2NEG: Comparator 2 Negative Input Configure bit

1= C2IN+ is connected to VIN-

0= C2IN- is connected to VIN-

See Figure 22-1 for the Comparator modes.

bit 2

bit 1

bit 0

C2POS: Comparator 2 Positive Input Configure bit

1= C2IN+ is connected to VIN+

0= CVREF is connected to VIN+

See Figure 22-1 for the Comparator modes.

C1NEG: Comparator 1 Negative Input Configure bit

1= C1IN+ is connected to VIN-

0= C1IN- is connected to VIN-

See Figure 22-1 for the Comparator modes.

C1POS: Comparator 1 Positive Input Configure bit

1= C1IN is connected to VIN+

0= CVREF is connected to VIN+

See Figure 22-1 for the Comparator modes.

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PIC24FJ128GA010 FAMILY

NOTES:

DS39747F-page 192

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PIC24FJ128GA010 FAMILY

voltage, each with 16 distinct levels. The range to be

used is selected by the CVRR bit (CVRCON<5>). The

primary difference between the ranges is the size of the

steps selected by the CVREF Selection bits

23.0 COMPARATOR VOLTAGE

REFERENCE

Note:

This data sheet summarizes features of

(CVR<3:0>), with one range offering finer resolution.

PIC24F group of devices and is not

intended to be a comprehensive reference

source. Refer to Section 20. “Comparator

Voltage Reference Module” (DS39709)

in the “PIC24F Family Reference Manual”

for more information.

The comparator reference supply voltage can come

from either VDD and VSS, or the external VREF+ and

VREF-. The voltage source is selected by the CVRSS

bit (CVRCON<4>).

The settling time of the comparator voltage reference

must be considered when changing the CVREF

output.

23.1 Configuring the Comparator

Voltage Reference

CVRR: Comparator VREF Range Selection bit 1 = 0

to 0.625 CVRSRC, with CVRSRC/24 step size.

The voltage reference module is controlled through the

CVRCON register (Register 23-1). The comparator

voltage reference provides two ranges of output

0 = 0.25 CVRSRC to 0.72 CVRSRC, with CVRSRC/32

step size

FIGURE 23-1:

COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM

CVRSS = 1

VREF+

AVDD

8R

CVRSS = 0

CVR<3:0>

R

CVREN

R

16 Steps

CVREF

R

CVRR

VREF-

8R

CVRSS = 1

CVRSS = 0

AVSS

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PIC24FJ128GA010 FAMILY

REGISTER 23-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/W-0

CVRR

R/W-0

CVR3

R/W-0

CVR2

R/W-0

CVR1

R/W-0

CVR0

CVREN

CVROE

CVRSS

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

bit 7

Unimplemented: Read as ‘0’

CVREN: Comparator Voltage Reference Enable bit

1= CVREF circuit is powered on

0= CVREF circuit is powered down

bit 6

CVROE: Comparator VREF Output Enable bit

1= CVREF voltage level is output on the CVREF pin

0= CVREF voltage level is disconnected from the CVREF pin

bit 5

CVRR: Comparator VREF Range Selection bit

1= 0 to 0.625 CVRSRC, with CVRSRC/24 step size

0= 0.25 CVRSRC to 0.72 CVRSRC, with CVRSRC/32 step size

bit 4

CVRSS: Comparator VREF Source Selection bit

1= Comparator reference source: CVRSRC = VREF+ – VREF-

0= Comparator reference source: CVRSRC = AVDD – AVSS

bit 3-0

CVR<3:0>: Comparator VREF Value Selection 0  CVR<3:0>  15 bits

When CVRR = 1:

CVREF = (CVR<3:0>/ 24)  (CVRSRC)

When CVRR = 0:

CVREF = 1/4  (CVRSRC) + (CVR<3:0>/32)  (CVRSRC)

DS39747F-page 194

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PIC24FJ128GA010 FAMILY

24.1.1

CONSIDERATIONS FOR

CONFIGURING PIC24FJ128GA010

FAMILY DEVICES

24.0 SPECIAL FEATURES

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

intended to be a comprehensive refer-

ence source. Refer to Section 32.

In PIC24FJ128GA010 family devices, the configuration

bytes are implemented as volatile memory. This means

that configuration data must be programmed each time

the device is powered up. Configuration data is stored

in the two words at the top of the on-chip program

memory space, known as the Flash Configuration

Words. Their specific locations are shown in

Table 24-1. These are packed representations of the

actual device Configuration bits, whose actual

locations are distributed among five locations in config-

uration space. The configuration data is automatically

loaded from the Flash Configuration Words to the

proper Configuration registers during device Resets.

“High-Level

Device

Integration”

(DS39719) in the “PIC24F Family

Reference Manual” for more information.

PIC24FJ128GA010 devices include several features

intended to maximize application flexibility and reliabil-

ity, and minimize cost through elimination of external

components. These are:

• Flexible Configuration

• Watchdog Timer (WDT)

• Code Protection

Note:

Configuration data is reloaded on all types

of device Resets.

• JTAG Boundary Scan Interface

• In-Circuit Serial Programming™ (ICSP™)

• In-Circuit Emulation

TABLE 24-1: FLASH CONFIGURATION

WORD LOCATIONS

24.1 Configuration Bits

Configuration Word

The Configuration bits can be programmed (read as

‘0’) or left unprogrammed (read as ‘1’) to select various

device configurations. These bits are mapped, starting

at program memory location, F80000h. A complete list

is shown in Table 24-1. A detailed explanation of the

various bit functions is provided in Register 24-1

through Register 24-4.

Addresses

Device

1

2

PIC24FJ64GA

PIC24FJ96GA

PIC24FJ128GA

00ABFEh

00FFFEh

0157FEh

00ABFCh

00FFFCh

0157FCh

Note that address, F80000h, is beyond the user program

memory space. In fact, it belongs to the configuration

memory space (800000h-FFFFFFh), which can only be

accessed using table reads and table writes.

When creating applications for these devices, users

should always specifically allocate the location of the

Flash Configuration Word for configuration data. This is

to make certain that program code is not stored in this

address when the code is compiled.

The Configuration bits are reloaded from the Flash

Configuration Word on any device Reset.

The upper byte of both Flash Configuration Words in

program memory should always be ‘1111 1111’. This

makes them appear to be NOP instructions in the

remote event that their locations are ever executed by

accident. Since Configuration bits are not implemented

in the corresponding locations, writing ‘1’s to these

locations has no effect on device operation.

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REGISTER 24-1: FLASH CONFIGURATION WORD 1

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

bit 23

bit 16

r-x

r

R/PO-1

JTAGEN⁽¹⁾

R/PO-1

GCP

R/PO-1

GWRP

R/PO-1

DEBUG

r-1

r

U-1

—

R/PO-1

ICS

bit 15

bit 8

R/PO-1

FWDTEN

bit 7

R/PO-1

WINDIS

U-1

—

R/PO-1

FWPSA

R/PO-1

WDTPS3

WDTPS2

WDTPS1

WDTPS0

bit 0

Legend:

x = Bit is unknown

r = Reserved

R = Readable bit

PO = Program Once bit

U = Unimplemented bit, read as ‘0’

‘1’ = Bit is set ‘0’ = Bit is cleared

-n = Value when device is unprogrammed

bit 23-16

bit 15

Unimplemented: Read as ‘1’

Reserved: Program as ‘0’. Read value is unknown.

JTAGEN: JTAG Port Enable bit⁽¹⁾

bit 14

1= JTAG port is enabled

0= JTAG port is disabled

bit 13

bit 12

bit 11

GCP: General Segment Program Memory Code Protection bit

1= Code protection is disabled

0= Code protection is enabled for the entire program memory space

GWRP: General Segment Code Flash Write Protection bit

1= Writes to program memory are allowed

0= Writes to program memory are disabled

DEBUG: Background Debugger Enable bit

1= Device resets into Operational mode

0= Device resets into Debug mode

bit 10

bit 9

bit 8

Reserved: Program as ‘1’

Unimplemented: Read as ‘1’

ICS: Emulator Pin Placement Select bit

1= Emulator/debugger uses EMUC2/EMUD2

0= Emulator/debugger uses EMUC1/EMUD1

bit 7

bit 6

FWDTEN: Watchdog Timer Enable bit

1= Watchdog Timer is enabled

0= Watchdog Timer is disabled

WINDIS: Windowed Watchdog Timer Disable bit

1= Standard Watchdog Timer is enabled

0= Windowed Watchdog Timer is enabled; FWDTEN must be ‘1’

bit 5

bit 4

Unimplemented: Read as ‘1’

FWPSA: WDT Prescaler Ratio Select bit

1= Prescaler ratio of 1:128

0= Prescaler ratio of 1:32

Note 1: JTAGEN bit can not be modified using JTAG programming. It can only change using In-Circuit Serial

Programming™ (ICSP™).

DS39747F-page 196

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PIC24FJ128GA010 FAMILY

REGISTER 24-1: FLASH CONFIGURATION WORD 1 (CONTINUED)

bit 3-0 WDTPS<3:0>: Watchdog Timer Postscaler Select bits

1111= 1:32,768

1110= 1:16,384

1101= 1:8,192

1100= 1:4,096

1011= 1:2,048

1010= 1:1,024

1001= 1:512

1000= 1:256

0111= 1:128

0110= 1:64

0101= 1:32

0100= 1:16

0011= 1:8

0010= 1:4

0001= 1:2

0000= 1:1

Note 1: JTAGEN bit can not be modified using JTAG programming. It can only change using In-Circuit Serial

Programming™ (ICSP™).

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PIC24FJ128GA010 FAMILY

REGISTER 24-2: FLASH CONFIGURATION WORD 2

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

bit 23

bit 16

R/PO-1

IESO

U-1

—

U-1

—

U-1

—

U-1

—

R/PO-1

FNOSC2

FNOSC1

FNOSC0

bit 15

bit 8

R/PO-1

FCKSM1

bit 7

R/PO-1

U-1

—

U-1

—

U-1

—

R/PO-1

POSCMD0

bit 0

FCKSM0

OSCIOFCN

POSCMD1

Legend:

x = Bit is unknown

R = Readable bit

PO = Program Once bit

U = Unimplemented bit, read as ‘0’

‘1’ = Bit is set ‘0’ = Bit is cleared

-n = Value when device is unprogrammed

bit 23-16 Unimplemented: Read as ‘1’

bit 15

IESO: Internal External Switchover bit

1= IESO mode (Two-Speed Start-up) is enabled

0= IESO mode (Two-Speed Start-up) is disabled

bit 14-11 Unimplemented: Read as ‘1’

bit 10-8

FNOSC<2:0>: Initial Oscillator Select bits

111= Fast RC Oscillator with Postscaler (FRCDIV)

110= Reserved

101= Low-Power RC Oscillator (LPRC)

100= Secondary Oscillator (SOSC)

011= Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)

010= Primary Oscillator (XT, HS, EC)

001= Fast RC Oscillator with postscaler and PLL module (FRCPLL)

000= Fast RC Oscillator (FRC)

bit 7-6

bit 5

FCKSM<1:0>: Clock Switching and Fail-Safe Clock Monitor Configuration bits

1x= Clock switching and Fail-Safe Clock Monitor are disabled

01= Clock switching is enabled, Fail-Safe Clock Monitor is disabled

00= Clock switching is enabled, Fail-Safe Clock Monitor is enabled

OSCIOFCN: OSC2 Pin Configuration bit

If POSCMD<1:0> = 11 or 00:

1= OSC2/CLKO/RC15 functions as CLKO (FOSC/2)

0= OSC2/CLKO/RC15 functions as port I/O (RC15)

If POSCMD<1:0> = 10 or 01:

OSCIOFCN has no effect on OSC2/CLKO/RC15.

bit 4-2

bit 1-0

Unimplemented: Read as ‘1’

POSCMD<1:0>: Primary Oscillator Configuration bits

11= Primary oscillator is disabled

10= HS Oscillator mode is selected

01= XT Oscillator mode is selected

00= EC Oscillator mode is selected

DS39747F-page 198

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REGISTER 24-3: DEVID: DEVICE ID REGISTER

U

—

bit 23

bit 16

U

R

—

FAMID7

FAMID6

FAMID5

FAMID4

FAMID3

FAMID2

bit 8

bit 15

R

FAMID1

FAMID0

DEV5

DEV4

DEV3

DEV2

DEV1

DEV0

bit 7

bit 0

Legend:

x = Bit is unknown

PO = Program Once bit

‘1’ = Bit is set

R = Readable bit

-n = Value at POR

U = Unimplemented bit, read as ‘1’

‘0’ = Bit is cleared x = Bit is unknown

bit 23-14

bit 13-6

Unimplemented: Read as ‘0’

FAMID<7:0>: Device Family Identifier bits

00010000= PIC24FJ128GA010 family

DEV<5:0>: Individual Device Identifier bits

bit 5-0

000101= PIC24FJ64GA006

000110= PIC24FJ96GA006

000111= PIC24FJ128GA006

001000= PIC24FJ64GA008

001001= PIC24FJ96GA008

001010= PIC24FJ128GA008

001011= PIC24FJ64GA010

001100= PIC24FJ96GA010

001101= PIC24FJ128GA010

 2005-2012 Microchip Technology Inc.

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PIC24FJ128GA010 FAMILY

REGISTER 24-4: DEVREV: DEVICE REVISION REGISTER

U

—

bit 23

bit 16

R-0

r

R-0

r

R-1

r

R-1

r

U

R

—

MAJRV2

bit 8

bit 15

R

U

R

MAJRV1

MAJRV0

—

DOT2

DOT1

DOT0

bit 7

bit 0

Legend:

x = Bit is unknown

r = Reserved

R = Readable bit

-n = Value at POR

PO = Program Once bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘1’

‘0’ = Bit is cleared x = Bit is unknown

bit 23-16

bit 15-12

bit 11-9

bit 8-6

Unimplemented: Read as ‘0’

Reserved: Read as ‘0011’

Unimplemented: Read as ‘0’

MAJRV<2:0>: Major Revision Identifier bits

Unimplemented: Read as ‘0’

bit 5-3

bit 2-0

DOT<2:0>: Minor Revision Identifier bits

DS39747F-page 200

 2005-2012 Microchip Technology Inc.

PIC24FJ128GA010 FAMILY

FIGURE 24-1:

CONNECTIONS FOR THE

ON-CHIP REGULATOR

24.2 On-Chip Voltage Regulator

All of the PIC24FJ128GA010 family devices power

their core digital logic at a nominal 2.5V. This may

create an issue for designs that are required to operate

at a higher typical voltage, such as 3.3V. To simplify

system design, all devices in the PIC24FJ128GA010

family incorporate an on-chip regulator that allows the

device to run its core logic from VDD.

Regulator Enabled (ENVREG tied to VDD):

3.3V

PIC24FJ128GA010

VDD

ENVREG

The regulator is controlled by the ENVREG pin. Tying

VDD to the pin enables the regulator, which in turn,

provides power to the core from the other VDD pins.

When the regulator is enabled, a low-ESR capacitor

(such as tantalum) must be connected to the

VDDCORE/VCAP pin (Figure 24-1). This helps to main-

tain the stability of the regulator. The recommended

value for the filter capacitor, CEFC, is provided in

Section 27.1 “DC Characteristics”.

VDDCORE/VCAP

VSS

CEFC

(10 F typ)

Regulator Disabled (ENVREG tied to ground):

(1)

2.5V

3.3V

If ENVREG is tied to VSS, the regulator is disabled. In

this case, separate power for the core logic, at a nomi-

nal 2.5V, must be supplied to the device on the

VDDCORE/VCAP pin to run the I/O pins at higher voltage

levels, typically 3.3V. Alternatively, the VDDCORE/VCAP

and VDD pins can be tied together to operate at a lower

nominal voltage. Refer to Figure 24-1 for possible

configurations.

PIC24FJ128GA010

VDD

ENVREG

VDDCORE/VCAP

VSS

24.2.1

ON-CHIP REGULATOR AND POR

When the voltage regulator is enabled, it takes approxi-

mately 20 s for it to generate output. During this time,

designated as TSTARTUP, code execution is disabled.

TSTARTUP is applied every time the device resumes

operation after any power-down, including Sleep mode.

Regulator Disabled (VDD tied to VDDCORE):

(1)

2.5V

PIC24FJ128GA010

VDD

If the regulator is disabled, a separate Power-up Timer

(PWRT) is automatically enabled. The PWRT adds a

fixed delay of 64 ms nominal delay at device start-up.

ENVREG

VDDCORE/VCAP

VSS

24.2.2

When

ON-CHIP REGULATOR AND BOR

the on-chip regulator is enabled,

simple

PIC24FJ128GA010 devices also have

a

brown-out capability. If the voltage supplied to the reg-

ulator is inadequate to maintain a regulated level, the

regulator Reset circuitry will generate a Brown-out

Reset. This event is captured by the BOR flag bit

(RCON<0>). The brown-out voltage specifications can

be found in the “PIC24F Family Reference Manual” in

Section 7. “Reset” (DS39712).

Note 1: These are typical operating voltages. Refer

to Section 27.1 “DC Characteristics” for

the full operating ranges of VDD and

VDDCORE.

24.2.3

POWER-UP REQUIREMENTS

The on-chip regulator is designed to meet the power-up

requirements for the device. If the application does not

use the regulator, then strict power-up conditions must

be adhered to. While powering up, VDDCORE must

never exceed VDD by 0.3 volts.

 2005-2012 Microchip Technology Inc.

DS39747F-page 201

PIC24FJ128GA010 FAMILY

• When the device exits Sleep or Idle mode to

resume normal operation

24.3 Watchdog Timer (WDT)

Note:

This data sheet summarizes the features of

• By a CLRWDTinstruction during normal execution

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. Refer to Section 9. “Watchdog

Timer (WDT)” (DS39697) in the “PIC24F

Family Reference Manual” for more

information.

If the WDT is enabled, it will continue to run during

Sleep or Idle modes. When the WDT time-out occurs,

the device will wake-up and code execution will con-

tinue from where the PWRSAVinstruction was executed.

The corresponding SLEEP or IDLE bits (RCON<3:2>)

will need to be cleared in software after the device

wakes up.

For PIC24FJ128GA010 family devices, the WDT is

driven by the LPRC oscillator. When the WDT is

enabled, the clock source is also enabled.

The WDT Flag bit, WDTO (RCON<4>), is not auto-

matically cleared following a WDT time-out. To detect

subsequent WDT events, the flag must be cleared in

software.

The nominal WDT clock source from LPRC is 32 kHz.

This feeds a prescaler that can be configured for either

5-bit (divide-by-32) or 7-bit (divide-by-128) operation.

The prescaler is set by the FWPSA Configuration bit.

With a 32 kHz input, the prescaler yields a nominal

WDT time-out period (TWDT) of 1 ms in 5-bit mode or

4 ms in 7-bit mode.

Note:

The CLRWDT and PWRSAV instructions

clear the prescaler and postscaler counts

when executed.

24.3.1

CONTROL REGISTER

A variable postscaler divides down the WDT prescaler

output and allows for a wide range of time-out periods.

The postscaler is controlled by the WDTPS<3:0> Con-

figuration bits (Flash Configuration Word 1<3:0>),

which allow the selection of a total of 16 settings, from

1:1 to 1:32,768. Using the prescaler and postscaler,

time-out periods, ranging from 1 ms to 131 seconds,

can be achieved.

The WDT is enabled or disabled by the FWDTEN

Configuration bit. When the FWDTEN Configuration bit

is set, the WDT is always enabled.

The WDT can be optionally controlled in software when

the FWDTEN Configuration bit has been programmed

to ‘0’. The WDT is enabled in software by setting the

SWDTEN control bit (RCON<5>). The SWDTEN con-

trol bit is cleared on any device Reset. The software

WDT option allows the user to enable the WDT for crit-

ical code segments and disables the WDT during

non-critical segments for maximum power savings.

The WDT, prescaler and postscaler are reset:

• On any device Reset

• On the completion of a clock switch, whether

invoked by software (i.e., setting the OSWEN bit

after changing the NOSC bits) or by hardware

(i.e., Fail-Safe Clock Monitor)

• When a PWRSAVinstruction is executed (i.e.,

Sleep or Idle mode is entered)

FIGURE 24-2:

WATCHDOG TIMER (WDT) BLOCK DIAGRAM

SWDTEN

FWDTEN

LPRC Control

Wake from Sleep

FWPSA

WDTPS<3:0>

Prescaler

(5-bit/7-bit)

WDT

Counter

Postscaler

WDT Overflow

1:1 to 1:32.768

LPRC Input

Reset

32 kHz

1 ms/4 ms

All Device Resets

Transition to

New Clock Source

Exit Sleep or

Idle Mode

CLRWDTInstr.

PWRSAVInstr.

Sleep or Idle Mode

DS39747F-page 202

 2005-2012 Microchip Technology Inc.

PIC24FJ128GA010 FAMILY

24.4 JTAG Interface

24.6

In-Circuit Serial Programming

Note:

This data sheet summarizes the features of

Note:

This data sheet summarizes the features of

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. Refer to Section 33. “Program-

ming and Diagnostics” (DS39716) in the

“PIC24F Family Reference Manual” for

more information.

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. Refer to Section 33. “Program-

ming and Diagnostics” (DS39716) in the

“PIC24F Family Reference Manual” for

more information.

PIC24FJ128GA010 family devices implement a JTAG

interface, which supports boundary scan device testing

as well as In-Circuit Serial Programming™ (ICSP™).

PIC24FJ128GA010 family microcontrollers can be

serially programmed while in the end application circuit.

This is simply done with two lines for clock (PGCx) and

data (PGDx), and three other lines for power, ground

and the programming voltage. This allows customers to

manufacture boards with unprogrammed devices and

then program the microcontroller just before shipping

the product. This also allows the most recent firmware

or a custom firmware to be programmed.

Refer to the Microchip web site (www.microchip.com)

for JTAG support files and additional information.

24.5 Program Verification and

Code Protection

Note:

This data sheet summarizes the features of

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. Refer to Section 33. “Program-

ming and Diagnostics” (DS39716) in the

“PIC24F Family Reference Manual” for

more information.

24.7 In-Circuit Debugger

When MPLAB^®ICD 2 is selected as a debugger, the

In-Circuit Debugging functionality is enabled. This

function allows simple debugging functions when used

with MPLAB IDE. Debugging functionality is controlled

through the EMUCx (Emulation/Debug Clock) and

EMUDx (Emulation/Debug Data) pins.

For all devices in the PIC24FJ128GA010 family, the

on-chip program memory space is treated as a single

block. Code protection for this block is controlled by

one Configuration bit, GCP (Flash Configuration

Word 1<13>. This bit inhibits external reads and writes

to the program memory space. It has no direct effect in

normal execution mode.

To use the In-Circuit Debugger function of the device, the

design must implement ICSP connections to MCLR,

VDD, VSS, PGCx, PGDx and the EMUDx/EMUCx pin

pair. In addition, when the feature is enabled, some of the

resources are not available for general use. These

resources include the first 80 bytes of data RAM and two

I/O pins.

Write protection is controlled by the GWRP bit (Flash

Configuration Word 1<12>. When GWRP is pro-

grammed to ‘0’, internal write and erase operations to

the program memory are blocked.

24.5.1

CONFIGURATION REGISTER

PROTECTION

The Configuration registers are protected against

inadvertent or unwanted changes, or reads in two

ways. The primary protection method is the same as

that of the shadow registers, which contain a compli-

mentary value that is constantly compared with the

actual value. To safeguard against unpredictable

events, Configuration bit changes resulting from indi-

vidual cell level disruptions (such as ESD events) will

cause a parity error and trigger a device Configuration

Word Mismatch Reset.

The data for the Configuration registers is derived from

the Flash Configuration Words in program memory. As

a consequence, when the GCP bit is set, the source

data for the device configuration is also protected.

 2005-2012 Microchip Technology Inc.

DS39747F-page 203

PIC24FJ128GA010 FAMILY

NOTES:

DS39747F-page 204

 2005-2012 Microchip Technology Inc.

PIC24FJ128GA010 FAMILY

The literal instructions that involve data movement may

use some of the following operands:

25.0 INSTRUCTION SET SUMMARY

The PIC24F instruction set adds many enhancements

to the previous PIC^®MCU instruction sets, while main-

taining an easy migration from previous PIC MCU

instruction sets. Most instructions are a single program

memory word. Only three instructions require two

program memory locations.

• A literal value to be loaded into a W register or file

register (specified by the value of ‘k’)

• The W register or file register where the literal

value is to be loaded (specified by ‘Wb’ or ‘f’)

However, literal instructions that involve arithmetic or

logical operations use some of the following operands:

Each single-word instruction is a 24-bit word divided

into an 8-bit opcode, which specifies the instruction

type and one or more operands, which further specify

the operation of the instruction. The instruction set is

highly orthogonal and is grouped into four basic

categories:

• The first source operand which is a register, ‘Wb’,

without any address modifier

• The second source operand which is a literal

value

• The destination of the result (only if not the same

as the first source operand) which is typically a

register, ‘Wd’, with or without an address modifier

• Word or byte-oriented operations

• Bit-oriented operations

• Literal operations

The control instructions may use some of the following

operands:

• Control operations

• A program memory address

Table 25-1 shows the general symbols used in

describing the instructions. The PIC24F instruction set

summary in Table 25-2 lists all the instructions, along

with the status flags affected by each instruction.

• The mode of the table read and table write

instructions

All instructions are a single word, except for certain

double-word instructions, which were made double-

word instructions so that all of the required information

is available in these 48 bits. In the second word, the

8 MSbs are ‘0’s. If this second word is executed as an

instruction (by itself), it will execute as a NOP.

Most word or byte-oriented W register instructions

(including barrel shift instructions) have three

operands:

• The first source operand which is typically a

register ‘Wb’ without any address modifier

Most single-word instructions are executed in a single

instruction cycle, unless a conditional test is true or the

Program Counter (PC) is changed as a result of the

instruction. In these cases, the execution takes two

instruction cycles, with the additional instruction

cycle(s) executed as a NOP. Notable exceptions are the

BRA (unconditional/computed branch), indirect CALL/

GOTO, all table reads and writes, and RETURN/RETFIE

instructions, which are single-word instructions but take

two or three cycles.

• The second source operand which is typically a

register ‘Ws’ with or without an address modifier

• The destination of the result which is typically a

register ‘Wd’ with or without an address modifier

However, word or byte-oriented file register instructions

have two operands:

• The file register specified by the value, ‘f’

• The destination, which could either be the file

register ‘f’ or the W0 register, which is denoted as

‘WREG’

Certain instructions that involve skipping over the sub-

sequent instruction require either two or three cycles if

the skip is performed, depending on whether the

instruction being skipped is a single-word or two-word

instruction. Moreover, double-word moves require two

cycles. The double-word instructions execute in two

instruction cycles.

Most bit-oriented instructions (including simple rotate/

shift instructions) have two operands:

• The W register (with or without an address

modifier) or file register (specified by the value of

‘Ws’ or ‘f’)

• The bit in the W register or file register

(specified by a literal value or indirectly by the

contents of register, ‘Wb’)

 2005-2012 Microchip Technology Inc.

DS39747F-page 205

PIC24FJ128GA010 FAMILY

TABLE 25-1: SYMBOLS USED IN OPCODE DESCRIPTIONS

Field

Description

#text

(text)

[text]

{ }

Means literal defined by “text”

Means “content of text”

Means “the location addressed by text”

Optional field or operation

<n:m>

.b

Register bit field

Byte mode selection

.d

Double-Word mode selection

.S

Shadow register select

.w

Word mode selection (default)

bit4

4-bit bit selection field (used in word addressed instructions) {0...15}

MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero

Absolute address, label or expression (resolved by the linker)

File register address {0000h...1FFFh}

1-bit unsigned literal {0,1}

C, DC, N, OV, Z

Expr

f

lit1

lit4

4-bit unsigned literal {0...15}

lit5

5-bit unsigned literal {0...31}

lit8

8-bit unsigned literal {0...255}

lit10

lit14

lit16

lit23

None

PC

10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode

14-bit unsigned literal {0...16384}

16-bit unsigned literal {0...65535}

23-bit unsigned literal {0...8388608}; LSB must be ‘0’

Field does not require an entry, may be blank

Program Counter

Slit10

Slit16

Slit6

Wb

10-bit signed literal {-512...511}

16-bit signed literal {-32768...32767}

6-bit signed literal {-16...16}

Base W register {W0..W15}

Wd

Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }

Wdo

Destination W register 

{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }

Wm,Wn

Wn

Dividend, Divisor working register pair (Direct Addressing)

One of 16 working registers {W0..W15}

Wnd

Wns

One of 16 destination working registers {W0..W15}

One of 16 source working registers {W0..W15}

W0 (working register used in file register instructions)

Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }

WREG

Ws

Wso

Source W register 

{ Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }

DS39747F-page 206

 2005-2012 Microchip Technology Inc.

PIC24FJ128GA010 FAMILY

TABLE 25-2: INSTRUCTION SET OVERVIEW

Assembly

Mnemonic

# of

Status Flags

Affected

Assembly Syntax

Description

Words Cycles

ADD

ADDC

AND

ASR

ADD

ADDC

AND

ASR

BCLR

BRA

BSET

BSW.C

BSW.Z

BTG

BTSC

f

f = f + WREG

1

C, DC, N, OV, Z

N, Z

f,WREG

WREG = f + WREG

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

f

Wd = lit10 + Wd

1

Wd = Wb + Ws

1

Wd = Wb + lit5

1

f = f + WREG + (C)

1

f,WREG

WREG = f + WREG + (C)

Wd = lit10 + Wd + (C)

Wd = Wb + Ws + (C)

Wd = Wb + lit5 + (C)

f = f .AND. WREG

1

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

f

1

f,WREG

WREG = f .AND. WREG

Wd = lit10 .AND. Wd

Wd = Wb .AND. Ws

1

N, Z

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

f

1

N, Z

1

N, Z

Wd = Wb .AND. lit5

1

N, Z

f = Arithmetic Right Shift f

WREG = Arithmetic Right Shift f

Wd = Arithmetic Right Shift Ws

Wnd = Arithmetic Right Shift Wb by Wns

Wnd = Arithmetic Right Shift Wb by lit5

Bit Clear f

1

C, N, OV, Z

N, Z

f,WREG

1

Ws,Wd

1

Wb,Wns,Wnd

Wb,#lit5,Wnd

f,#bit4

Ws,#bit4

C,Expr

1

N, Z

BCLR

BRA

1

None

Bit Clear Ws

1

None

Branch if Carry

1 (2)

2

None

GE,Expr

GEU,Expr

GT,Expr

GTU,Expr

LE,Expr

LEU,Expr

LT,Expr

LTU,Expr

N,Expr

Branch if Greater than or Equal

Branch if Unsigned Greater than or Equal

Branch if Greater than

Branch if Unsigned Greater than

Branch if Less than or Equal

Branch if Unsigned Less than or Equal

Branch if Less than

None

Branch if Unsigned Less than

Branch if Negative

None

NC,Expr

NN,Expr

NOV,Expr

NZ,Expr

OV,Expr

Expr

Branch if Not Carry

None

Branch if Not Negative

Branch if Not Overflow

Branch if Not Zero

None

Branch if Overflow

None

Branch Unconditionally

Branch if Zero

None

Z,Expr

1 (2)

2

None

Wn

Computed Branch

None

BSET

BSW

f,#bit4

Ws,#bit4

Ws,Wb

Bit Set f

1

None

Bit Set Ws

1

None

Write C bit to Ws<Wb>

Write Z bit to Ws<Wb>

Bit Toggle f

1

None

Ws,Wb

1

None

BTG

f,#bit4

Ws,#bit4

f,#bit4

1

None

Bit Toggle Ws

1

None

BTSC

Bit Test f, Skip if Clear

1

None

(2 or 3)

BTSC

Ws,#bit4

Bit Test Ws, Skip if Clear

1

None

(2 or 3)

 2005-2012 Microchip Technology Inc.

DS39747F-page 207

PIC24FJ128GA010 FAMILY

TABLE 25-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Assembly

Mnemonic

# of

Status Flags

Affected

Assembly Syntax

f,#bit4

Description

Bit Test f, Skip if Set

Words Cycles

BTSS

1

None

(2 or 3)

Ws,#bit4

Bit Test Ws, Skip if Set

1

None

(2 or 3)

BTST

f,#bit4

Ws,#bit4

Ws,Wb

Bit Test f

1

2

1

2

1

Z

BTST.C

BTST.Z

BTST.C

BTST.Z

BTSTS

Bit Test Ws to C

C

Bit Test Ws to Z

Z

Bit Test Ws<Wb> to C

Bit Test Ws<Wb> to Z

Bit Test then Set f

Bit Test Ws to C, then Set

Bit Test Ws to Z, then Set

Call Subroutine

C

Ws,Wb

Z

BTSTS

f,#bit4

Z

BTSTS.C Ws,#bit4

BTSTS.Z Ws,#bit4

C

Z

CALL

CLR

CALL

CLR

lit23

Wn

None

Call Indirect Subroutine

f = 0x0000

None

f

None

CLR

WREG

Ws

WREG = 0x0000

Ws = 0x0000

None

CLR

None

CLRWDT

COM

CLRWDT

Clear Watchdog Timer

WDTO, Sleep

COM

CP

f

f = f

1

N, Z

f,WREG

Ws,Wd

f

WREG = f

N, Z

Wd = Ws

N, Z

CP

Compare f with WREG

Compare Wb with lit5

Compare Wb with Ws (Wb – Ws)

Compare f with 0x0000

Compare Ws with 0x0000

Compare f with WREG, with Borrow

Compare Wb with lit5, with Borrow

C, DC, N, OV, Z

CP

Wb,#lit5

Wb,Ws

f

CP

CP0

CPB

CP0

CPB

Ws

f

Wb,#lit5

Wb,Ws

Compare Wb with Ws, with Borrow

(Wb – Ws – C)

CPSEQ

CPSGT

CPSLT

CPSNE

CPSEQ

CPSGT

CPSLT

CPSNE

Wb,Wn

Compare Wb with Wn, Skip if =

Compare Wb with Wn, Skip if >

Compare Wb with Wn, Skip if <

Compare Wb with Wn, Skip if 

1

None

(2 or 3)

1

(2 or 3)

1

(2 or 3)

1

(2 or 3)

DAW

DEC

DAW.B

DEC

Wn

Wn = Decimal Adjust Wn

f = f –1

1

C

f

C, DC, N, OV, Z

None

DEC

f,WREG

Ws,Wd

f

WREG = f –1

1

DEC

Wd = Ws – 1

1

DEC2

f = f – 2

1

DEC2

f,WREG

Ws,Wd

#lit14

Wm,Wn

Wns,Wnd

Ws,Wnd

WREG = f – 2

1

DEC2

Wd = Ws – 2

1

DISI

DIV

DISI

Disable Interrupts for k Instruction Cycles

Signed 16/16-Bit Integer Divide

Signed 32/16-Bit Integer Divide

Unsigned 16/16-Bit Integer Divide

Unsigned 32/16-Bit Integer Divide

Swap Wns with Wnd

1

DIV.SW

DIV.SD

DIV.UW

DIV.UD

EXCH

18

1

N, Z, C, OV

None

EXCH

FF1L

FF1R

FF1L

Find First One from Left (MSb) Side

Find First One from Right (LSb) Side

1

C

FF1R

1

C

DS39747F-page 208

 2005-2012 Microchip Technology Inc.

PIC24FJ128GA010 FAMILY

TABLE 25-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Assembly

Mnemonic

# of

Status Flags

Affected

Assembly Syntax

Description

Words Cycles

GOTO

INC

Expr

Go to Address

Go to Indirect

f = f + 1

2

1

2

1

2

1

None

Wn

None

INC

f

C, DC, N, OV, Z

N, Z

INC

f,WREG

WREG = f + 1

Wd = Ws + 1

f = f + 2

INC

Ws,Wd

INC2

IOR

INC2

IOR

f

f,WREG

WREG = f + 2

Wd = Ws + 2

f = f .IOR. WREG

Ws,Wd

f

IOR

f,WREG

WREG = f .IOR. WREG

N, Z

IOR

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

#lit14

Wd = lit10 .IOR. Wd

N, Z

IOR

Wd = Wb .IOR. Ws

N, Z

IOR

Wd = Wb .IOR. lit5

N, Z

LNK

LSR

LNK

Link Frame Pointer

None

LSR

f

f = Logical Right Shift f

C, N, OV, Z

N, Z

LSR

f,WREG

WREG = Logical Right Shift f

Wd = Logical Right Shift Ws

Wnd = Logical Right Shift Wb by Wns

Wnd = Logical Right Shift Wb by lit5

Move f to Wn

LSR

Ws,Wd

LSR

Wb,Wns,Wnd

Wb,#lit5,Wnd

f,Wn

LSR

N, Z

MOV

None

MOV

[Wns+Slit10],Wnd

f

Move [Wns+Slit10] to Wnd

Move f to f

None

MOV

N, Z

MOV

f,WREG

Move f to WREG

N, Z

MOV

#lit16,Wn

#lit8,Wn

Wn,f

Move 16-Bit Literal to Wn

None

MOV.b

MOV

Move 8-Bit Literal to Wn

None

Move Wn to f

None

MOV

Wns,[Wns+Slit10]

Wso,Wdo

WREG,f

Move Wns to [Wns+Slit10]

Move Ws to Wd

MOV

None

N, Z

MOV

Move WREG to f

MOV.D

MUL.SS

MUL.SU

MUL.US

MUL.UU

MUL.SU

MUL.UU

MUL

Wns,Wd

Move Double from W(ns):W(ns+1) to Wd

Move Double from Ws to W(nd+1):W(nd)

{Wnd+1, Wnd} = Signed(Wb) * Signed(Ws)

{Wnd+1, Wnd} = Signed(Wb) * Unsigned(Ws)

{Wnd+1, Wnd} = Unsigned(Wb) * Signed(Ws)

{Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(Ws)

{Wnd+1, Wnd} = Signed(Wb) * Unsigned(lit5)

{Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(lit5)

W3:W2 = f * WREG

None

Ws,Wnd

MUL

Wb,Ws,Wnd

Wb,#lit5,Wnd

f

NEG

f

f = f + 1

1

2

1

2

1

C, DC, N, OV, Z

None

NEG

f,WREG

Ws,Wd

WREG = f + 1

NEG

Wd = Ws + 1

NOP

POP

NOP

No Operation

NOPR

POP

No Operation

None

f

Pop f from Top-of-Stack (TOS)

Pop from Top-of-Stack (TOS) to Wdo

Pop from Top-of-Stack (TOS) to W(nd):W(nd+1)

Pop Shadow Registers

Push f to Top-of-Stack (TOS)

Push Wso to Top-of-Stack (TOS)

Push W(ns):W(ns+1) to Top-of-Stack (TOS)

Push Shadow Registers

None

POP

Wdo

Wnd

None

POP.D

POP.S

PUSH

PUSH.D

PUSH.S

None

All

PUSH

f

None

Wso

Wns

None

 2005-2012 Microchip Technology Inc.

DS39747F-page 209

PIC24FJ128GA010 FAMILY

TABLE 25-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Assembly

Mnemonic

# of

Status Flags

Affected

Assembly Syntax

Description

Words Cycles

PWRSAV

RCALL

PWRSAV

RCALL

REPEAT

RESET

RETFIE

RETLW

RETURN

RLC

#lit1

Expr

Wn

Go into Sleep or Idle mode

Relative Call

1

2

WDTO, Sleep

None

Computed Call

2

None

REPEAT

#lit14

Wn

Repeat Next Instruction lit14 + 1 times

Repeat Next Instruction (Wn) + 1 times

Software Device Reset

Return from Interrupt

1

None

1

None

RESET

RETFIE

RETLW

RETURN

RLC

1

None

3 (2)

1

None

#lit10,Wn

Return with Literal in Wn

Return from Subroutine

f = Rotate Left through Carry f

WREG = Rotate Left through Carry f

Wd = Rotate Left through Carry Ws

f = Rotate Left (No Carry) f

WREG = Rotate Left (No Carry) f

Wd = Rotate Left (No Carry) Ws

f = Rotate Right through Carry f

WREG = Rotate Right through Carry f

Wd = Rotate Right through Carry Ws

f = Rotate Right (No Carry) f

WREG = Rotate Right (No Carry) f

Wd = Rotate Right (No Carry) Ws

Wnd = Sign-Extended Ws

f = FFFFh

None

f

C, N, Z

RLC

f,WREG

Ws,Wd

f

1

C, N, Z

RLC

1

C, N, Z

RLNC

RRC

RLNC

RRC

1

N, Z

f,WREG

Ws,Wd

f

1

N, Z

1

N, Z

1

C, N, Z

RRC

f,WREG

Ws,Wd

f

1

C, N, Z

RRC

1

C, N, Z

RRNC

SE

1

N, Z

f,WREG

Ws,Wd

Ws,Wnd

f

1

N, Z

1

N, Z

SE

1

C, N, Z

SETM

SL

1

None

WREG

WREG = FFFFh

1

None

Ws

Ws = FFFFh

1

None

SL

f

f = Left Shift f

1

C, N, OV, Z

N, Z

SL

f,WREG

Ws,Wd

Wb,Wns,Wnd

Wb,#lit5,Wnd

f

WREG = Left Shift f

1

SL

Wd = Left Shift Ws

1

SL

Wnd = Left Shift Wb by Wns

Wnd = Left Shift Wb by lit5

f = f – WREG

1

SL

1

N, Z

SUB

1

C, DC, N, OV, Z

SUB

f,WREG

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

f

WREG = f – WREG

1

SUB

Wn = Wn – lit10

1

SUB

Wd = Wb – Ws

1

SUB

Wd = Wb – lit5

1

SUBB

f = f – WREG – (C)

1

f,WREG

WREG = f – WREG – (C)

1

SUBB

SUBR

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

f

Wn = Wn – lit10 – (C)

Wd = Wb – Ws – (C)

Wd = Wb – lit5 – (C)

f = WREG – f

1

C, DC, N, OV, Z

SUBR

f,WREG

WREG = WREG – f

Wd = Ws – Wb

Wb,Ws,Wd

Wb,#lit5,Wd

Wd = lit5 – Wb

SUBBR

f

f = WREG – f – (C)

1

C, DC, N, OV, Z

f,WREG

WREG = WREG – f – (C)

SUBBR

SWAP.b

SWAP

Wb,Ws,Wd

Wb,#lit5,Wd

Wn

Wd = Ws – Wb – (C)

1

2

C, DC, N, OV, Z

None

Wd = lit5 – Wb – (C)

SWAP

Wn = Nibble Swap Wn

Wn = Byte Swap Wn

Wn

None

TBLRDH

Ws,Wd

Read Prog<23:16> to Wd<7:0>

None

DS39747F-page 210

 2005-2012 Microchip Technology Inc.

PIC24FJ128GA010 FAMILY

TABLE 25-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Assembly

Mnemonic

# of

Status Flags

Affected

Assembly Syntax

Description

Words Cycles

TBLRDL

TBLWTH

TBLWTL

ULNK

TBLRDL

TBLWTH

TBLWTL

ULNK

XOR

Ws,Wd

Read Prog<15:0> to Wd

1

2

1

None

Write Ws<7:0> to Prog<23:16>

Write Ws to Prog<15:0>

Unlink Frame Pointer

f = f .XOR. WREG

None

N, Z

XOR

f

XOR

f,WREG

WREG = f .XOR. WREG

Wd = lit10 .XOR. Wd

Wd = Wb .XOR. Ws

N, Z

XOR

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

Ws,Wnd

N, Z

XOR

N, Z

XOR

Wd = Wb .XOR. lit5

N, Z

ZE

Wnd = Zero-Extend Ws

C, Z, N

 2005-2012 Microchip Technology Inc.

DS39747F-page 211

PIC24FJ128GA010 FAMILY

NOTES:

DS39747F-page 212

 2005-2012 Microchip Technology Inc.

PIC24FJ128GA010 FAMILY

26.1 MPLAB Integrated Development

Environment Software

26.0 DEVELOPMENT SUPPORT

The PIC^®microcontrollers and dsPIC^®digital signal

controllers are supported with a full range of software

and hardware development tools:

The MPLAB IDE software brings an ease of software

development previously unseen in the 8/16/32-bit

microcontroller market. The MPLAB IDE is a Windows^®

operating system-based application that contains:

• Integrated Development Environment

- MPLAB^®IDE Software

• A single graphical interface to all debugging tools

- Simulator

• Compilers/Assemblers/Linkers

- MPLAB C Compiler for Various Device

Families

- Programmer (sold separately)

- HI-TECH C^®for Various Device Families

- MPASM^TMAssembler

- MPLINK^TMObject Linker/

MPLIB^TMObject Librarian

- In-Circuit Emulator (sold separately)

- In-Circuit Debugger (sold separately)

• A full-featured editor with color-coded context

• A multiple project manager

- MPLAB Assembler/Linker/Librarian for

Various Device Families

• Customizable data windows with direct edit of

contents

• Simulators

• High-level source code debugging

• Mouse over variable inspection

- MPLAB SIM Software Simulator

• Emulators

• Drag and drop variables from source to watch

windows

- MPLAB REAL ICE™ In-Circuit Emulator

• In-Circuit Debuggers

• Extensive on-line help

• Integration of select third party tools, such as

IAR C Compilers

- MPLAB ICD 3

- PICkit™ 3 Debug Express

• Device Programmers

- PICkit™ 2 Programmer

- MPLAB PM3 Device Programmer

The MPLAB IDE allows you to:

• Edit your source files (either C or assembly)

• One-touch compile or assemble, and download to

emulator and simulator tools (automatically

updates all project information)

• Low-Cost Demonstration/Development Boards,

Evaluation Kits, and Starter Kits

• Debug using:

- Source files (C or assembly)

- Mixed C and assembly

- Machine code

MPLAB IDE supports multiple debugging tools in a

single development paradigm, from the cost-effective

simulators, through low-cost in-circuit debuggers, to

full-featured emulators. This eliminates the learning

curve when upgrading to tools with increased flexibility

and power.

 2005-2012 Microchip Technology Inc.

DS39747F-page 213

PIC24FJ128GA010 FAMILY

26.2 MPLAB C Compilers for Various

Device Families

26.5 MPLINK Object Linker/

MPLIB Object Librarian

The MPLAB C Compiler code development systems

are complete ANSI C compilers for Microchip’s PIC18,

PIC24 and PIC32 families of microcontrollers and the

dsPIC30 and dsPIC33 families of digital signal control-

lers. These compilers provide powerful integration

capabilities, superior code optimization and ease of

use.

The MPLINK Object Linker combines relocatable

objects created by the MPASM Assembler and the

MPLAB C18 C Compiler. It can link relocatable objects

from precompiled libraries, using directives from a

linker script.

The MPLIB Object Librarian manages the creation and

modification of library files of precompiled code. When

a routine from a library is called from a source file, only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

For easy source level debugging, the compilers provide

symbol information that is optimized to the MPLAB IDE

debugger.

26.3 HI-TECH C for Various Device

Families

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

The HI-TECH C Compiler code development systems

are complete ANSI C compilers for Microchip’s PIC

family of microcontrollers and the dsPIC family of digital

signal controllers. These compilers provide powerful

integration capabilities, omniscient code generation

and ease of use.

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, replacement, deletion and extraction

26.6 MPLAB Assembler, Linker and

Librarian for Various Device

Families

For easy source level debugging, the compilers provide

symbol information that is optimized to the MPLAB IDE

debugger.

The compilers include a macro assembler, linker, pre-

processor, and one-step driver, and can run on multiple

platforms.

MPLAB Assembler produces relocatable machine

code from symbolic assembly language for PIC24,

PIC32 and dsPIC devices. MPLAB C Compiler uses

the assembler to produce its object file. The assembler

generates relocatable object files that can then be

archived or linked with other relocatable object files and

archives to create an executable file. Notable features

of the assembler include:

26.4 MPASM Assembler

The MPASM Assembler is a full-featured, universal

macro assembler for PIC10/12/16/18 MCUs.

The MPASM Assembler generates relocatable object

files for the MPLINK Object Linker, Intel^®standard HEX

files, MAP files to detail memory usage and symbol

reference, absolute LST files that contain source lines

and generated machine code and COFF files for

debugging.

• Support for the entire device instruction set

• Support for fixed-point and floating-point data

• Command line interface

• Rich directive set

• Flexible macro language

The MPASM Assembler features include:

• Integration into MPLAB IDE projects

• MPLAB IDE compatibility

• User-defined macros to streamline

assembly code

• Conditional assembly for multi-purpose

source files

• Directives that allow complete control over the

assembly process

DS39747F-page 214

 2005-2012 Microchip Technology Inc.

PIC24FJ128GA010 FAMILY

26.7 MPLAB SIM Software Simulator

26.9 MPLAB ICD 3 In-Circuit Debugger

System

The MPLAB SIM Software Simulator allows code

development in a PC-hosted environment by simulat-

ing the PIC MCUs and dsPIC^®DSCs on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a comprehensive stimulus controller. Registers can be

logged to files for further run-time analysis. The trace

buffer and logic analyzer display extend the power of

the simulator to record and track program execution,

actions on I/O, most peripherals and internal registers.

MPLAB ICD 3 In-Circuit Debugger System is Micro-

chip's most cost effective high-speed hardware

debugger/programmer for Microchip Flash Digital Sig-

nal Controller (DSC) and microcontroller (MCU)

devices. It debugs and programs PIC^®Flash microcon-

trollers and dsPIC^®DSCs with the powerful, yet easy-

to-use graphical user interface of MPLAB Integrated

Development Environment (IDE).

The MPLAB ICD 3 In-Circuit Debugger probe is con-

nected to the design engineer’s PC using a high-speed

USB 2.0 interface and is connected to the target with a

connector compatible with the MPLAB ICD 2 or MPLAB

REAL ICE systems (RJ-11). MPLAB ICD 3 supports all

MPLAB ICD 2 headers.

The MPLAB SIM Software Simulator fully supports

symbolic debugging using the MPLAB C Compilers,

and the MPASM and MPLAB Assemblers. The soft-

ware simulator offers the flexibility to develop and

debug code outside of the hardware laboratory envi-

ronment, making it an excellent, economical software

development tool.

26.10 PICkit 3 In-Circuit Debugger/

Programmer and

26.8 MPLAB REAL ICE In-Circuit

Emulator System

PICkit 3 Debug Express

The MPLAB PICkit 3 allows debugging and program-

ming of PIC^®and dsPIC^®Flash microcontrollers at a

most affordable price point using the powerful graphical

user interface of the MPLAB Integrated Development

Environment (IDE). The MPLAB PICkit 3 is connected

to the design engineer's PC using a full speed USB

interface and can be connected to the target via an

Microchip debug (RJ-11) connector (compatible with

MPLAB ICD 3 and MPLAB REAL ICE). The connector

uses two device I/O pins and the reset line to imple-

ment in-circuit debugging and In-Circuit Serial

Programming™.

MPLAB REAL ICE In-Circuit Emulator System is

Microchip’s next generation high-speed emulator for

Microchip Flash DSC and MCU devices. It debugs and

programs PIC^®Flash MCUs and dsPIC^®Flash DSCs

with the easy-to-use, powerful graphical user interface of

the MPLAB Integrated Development Environment (IDE),

included with each kit.

The emulator is connected to the design engineer’s PC

using a high-speed USB 2.0 interface and is connected

to the target with either a connector compatible with in-

circuit debugger systems (RJ11) or with the new high-

speed, noise tolerant, Low-Voltage Differential Signal

(LVDS) interconnection (CAT5).

The PICkit 3 Debug Express include the PICkit 3, demo

board and microcontroller, hookup cables and CDROM

with user’s guide, lessons, tutorial, compiler and

MPLAB IDE software.

The emulator is field upgradable through future firmware

downloads in MPLAB IDE. In upcoming releases of

MPLAB IDE, new devices will be supported, and new

features will be added. MPLAB REAL ICE offers

significant advantages over competitive emulators

including low-cost, full-speed emulation, run-time

variable watches, trace analysis, complex breakpoints, a

ruggedized probe interface and long (up to three meters)

interconnection cables.

 2005-2012 Microchip Technology Inc.

DS39747F-page 215

PIC24FJ128GA010 FAMILY

26.11 PICkit 2 Development

Programmer/Debugger and

PICkit 2 Debug Express

26.13 Demonstration/Development

Boards, Evaluation Kits, and

Starter Kits

The PICkit™ 2 Development Programmer/Debugger is

a low-cost development tool with an easy to use inter-

face for programming and debugging Microchip’s Flash

families of microcontrollers. The full featured

Windows^®programming interface supports baseline

A wide variety of demonstration, development and

evaluation boards for various PIC MCUs and dsPIC

DSCs allows quick application development on fully func-

tional systems. Most boards include prototyping areas for

adding custom circuitry and provide application firmware

and source code for examination and modification.

(PIC10F,

PIC12F5xx,

PIC16F5xx),

midrange

(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,

dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit

microcontrollers, and many Microchip Serial EEPROM

products. With Microchip’s powerful MPLAB Integrated

The boards support a variety of features, including LEDs,

temperature sensors, switches, speakers, RS-232

interfaces, LCD displays, potentiometers and additional

EEPROM memory.

Development Environment (IDE) the PICkit™

2

enables in-circuit debugging on most PIC^®microcon-

trollers. In-Circuit-Debugging runs, halts and single

steps the program while the PIC microcontroller is

embedded in the application. When halted at a break-

point, the file registers can be examined and modified.

The demonstration and development boards can be

used in teaching environments, for prototyping custom

circuits and for learning about various microcontroller

applications.

In addition to the PICDEM™ and dsPICDEM™ demon-

stration/development board series of circuits, Microchip

has a line of evaluation kits and demonstration software

The PICkit 2 Debug Express include the PICkit 2, demo

board and microcontroller, hookup cables and CDROM

with user’s guide, lessons, tutorial, compiler and

MPLAB IDE software.

®

for analog filter design, KEELOQ security ICs, CAN,

IrDA^®, PowerSmart battery management, SEEVAL^®

evaluation system, Sigma-Delta A/D, flow rate sensing,

plus many more.

26.12 MPLAB PM3 Device Programmer

Also available are starter kits that contain everything

needed to experience the specified device. This usually

includes a single application and debug capability, all

on one board.

The MPLAB PM3 Device Programmer is a universal,

CE compliant device programmer with programmable

voltage verification at VDDMIN and VDDMAX for

maximum reliability. It features a large LCD display

(128 x 64) for menus and error messages and a modu-

lar, detachable socket assembly to support various

package types. The ICSP™ cable assembly is included

as a standard item. In Stand-Alone mode, the MPLAB

PM3 Device Programmer can read, verify and program

PIC devices without a PC connection. It can also set

code protection in this mode. The MPLAB PM3

connects to the host PC via an RS-232 or USB cable.

The MPLAB PM3 has high-speed communications and

optimized algorithms for quick programming of large

memory devices and incorporates an MMC card for file

storage and data applications.

Check the Microchip web page (www.microchip.com)

for the complete list of demonstration, development

and evaluation kits.

DS39747F-page 216

 2005-2012 Microchip Technology Inc.

PIC24FJ128GA010 FAMILY

27.0 ELECTRICAL CHARACTERISTICS

This section provides an overview of the PIC24FJ128GA010 electrical characteristics. Additional information will be

provided in future revisions of this document as it becomes available.

Absolute maximum ratings for the PIC24FJ128GA010 are listed below. Exposure to these maximum rating conditions

for extended periods may affect device reliability. Functional operation of the device at these, or any other conditions

above the parameters indicated in the operation listings of this specification, is not implied.

(†)

Absolute Maximum Ratings

Ambient temperature under bias...............................................................................................................-40°C to +85°C

Storage temperature .............................................................................................................................. -65°C to +150°C

Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V

Voltage on any combined analog and digital pin and MCLR, with respect to VSS ......................... -0.3V to (VDD + 0.3V)

Voltage on any digital only pin with respect to VSS .................................................................................. -0.3V to +6.0V

Voltage on VDDCORE with respect to VSS ................................................................................................. -0.3V to +2.8V

Maximum current out of VSS pin ...........................................................................................................................300 mA

Maximum current into VDD pin (Note 1)................................................................................................................250 mA

Maximum output current sunk by any I/O pin..........................................................................................................25 mA

Maximum output current sourced by any I/O pin ....................................................................................................25 mA

Maximum current sunk by all ports .......................................................................................................................200 mA

Maximum current sourced by all ports (Note 1)....................................................................................................200 mA

Note 1: Maximum allowable current is a function of device maximum power dissipation (see Table 27-2).

†NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those, or any other conditions above those

indicated in the operation listings of this specification, is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

FIGURE 27-1:

FREQUENCY/VOLTAGE GRAPH

3.00V

2.75V

2.50V

2.75V

2.25V

2.00V

16 MHz

32 MHz

Frequency

Note 1: When the voltage regulator is disabled, VDD and VDDCORE must be maintained so that VDDCORE  VDD 3.6V.

 2005-2012 Microchip Technology Inc.

DS39747F-page 217

PIC24FJ128GA010 FAMILY

27.1 DC Characteristics

TABLE 27-1: OPERATING MIPS vs. VOLTAGE

Max MIPS

PIC24FJ128GA010 Family

16

VDD Range

(in Volts)

Temp Range

(in °C)

2.0-3.6V

-40°C to +85°C

TABLE 27-2: THERMAL OPERATING CONDITIONS

Rating

Symbol

Min

Typ

Max

Unit

PIC24FJ128GA010 Family:

Operating Junction Temperature Range

Operating Ambient Temperature Range

TJ

TA

-40

—

+125

+85

°C

Power Dissipation:

Internal Chip Power Dissipation:

PINT = VDD x (IDD –  IOH)

PD

PINT + PI/O

W

I/O Pin Power Dissipation:

PI/O =  ({VDD – VOH} x IOH) +  (VOL x IOL)

Maximum Allowed Power Dissipation

PDMAX

(TJ – TA)/JA

TABLE 27-3: THERMAL PACKAGING CHARACTERISTICS

Characteristic

Symbol

Typ

Max

Unit

Notes

^JA

JA

^JA

Package Thermal Resistance, 14x14x1 mm TQFP

Package Thermal Resistance, 12x12x1 mm TQFP

Package Thermal Resistance, 10x10x1 mm TQFP

50

—

°C/W (Note 1)

69.4

76.6

Note 1: Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations.

TABLE 27-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS

Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

DC CHARACTERISTICS

Operating temperature

-40°C  TA  +85°C for Industrial

Param

No.

Sym

Characteristic

Min

Typ⁽¹⁾

Max

Units

Conditions

Operating Voltage

DC10 Supply Voltage

VDD

VBOR

VDDCORE

2.0

—

3.6

2.75

—

V

Regulator is enabled

Regulator is disabled

VDD

VDDCORE

DC12 VDR

RAM Data Retention

Voltage⁽²⁾

1.5

DC16 VPOR

VDD Start Voltage

to Ensure Internal

Power-on Reset Signal

—

0.05

1.9

—

VSS

—

V

DC17 SVDD

DC18 VBOR

VDD Rise Rate

to Ensure Internal

Power-on Reset Signal

V/ms 0-3.3V in 0.1s

0-2.5V in 60 ms

Brown-out Reset

Voltage⁽³⁾

2.2

2.5

V

Regulator must be enabled

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

2: This is the limit to which VDD can be lowered without losing RAM data.

3: Device will operate normally until Brown-out reset occurs even though VDD may be below VDDMIN.

DS39747F-page 218

 2005-2012 Microchip Technology Inc.

PIC24FJ128GA010 FAMILY

TABLE 27-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD)

Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for Industrial

DC CHARACTERISTICS

Parameter

Typical⁽¹⁾

No.

Max

Units

Conditions

Operating Current (IDD)⁽²⁾

DC20

1.6

6.0

20

4.0

12

mA

A

-40°C

+25°C

+85°C

-40°C

+25°C

+85°C

-40°C

+25°C

+85°C

-40°C

+25°C

+85°C

-40°C

+25°C

+85°C

-40°C

+25°C

+85°C

-40°C

+25°C

+85°C

-40°C

+25°C

+85°C

DC20a

DC20b

DC20d

DC20e

DC20f

DC23

2.5V⁽³⁾

3.6V⁽⁴⁾

2.5V⁽³⁾

3.6V⁽⁴⁾

2.5V⁽³⁾

3.6V⁽⁴⁾

2.5V⁽³⁾

3.6V⁽⁴⁾

1 MIPS

DC23a

DC23b

DC23d

DC23e

DC23f

DC24

12

4 MIPS

12

32

DC24a

DC24b

DC24d

DC24e

DC24f

DC31

20

32

20

32

16 MIPS

20

32

20

32

20

32

70

150

200

400

150

200

400

DC31a

DC31b

DC31d

DC31e

DC31f

100

200

70

A

LPRC (31 kHz)

A

100

200

A

Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance

only and are not tested.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O

pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have

an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSC1

driven with external square wave from rail-to-rail. All I/O pins are configured as inputs and pulled to VDD.

MCLR = VDD; WDT and FSCM are disabled. CPU, SRAM, program memory and data memory are

operational. No peripheral modules are operating and PMD bits are set.

3: On-chip voltage regulator is disabled (ENVREG tied to VSS).

4: On-chip voltage regulator is enabled (ENVREG tied to VDD).

 2005-2012 Microchip Technology Inc.

DS39747F-page 219

PIC24FJ128GA010 FAMILY

TABLE 27-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)

Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for Industrial

DC CHARACTERISTICS

Parameter

Typical⁽¹⁾

No.

Max

Units

Conditions

Idle Current (IIDLE): Core Off, Clock On Base Current⁽²⁾

DC40

0.7

2.1

6.8

70

2

mA

A

-40°C

+25°C

+85°C

-40°C

+25°C

+85°C

-40°C

+25°C

+85°C

-40°C

+25°C

+85°C

-40°C

+25°C

+85°C

-40°C

+25°C

+85°C

-40°C

+25°C

+85°C

-40°C

+25°C

+85°C

DC40a

DC40b

DC40d

DC40e

DC40f

DC43

2.5V⁽³⁾

3.6V⁽⁴⁾

2.5V⁽³⁾

3.6V⁽⁴⁾

2.5V⁽³⁾

3.6V⁽⁴⁾

2.5V⁽³⁾

3.6V⁽⁴⁾

2

1 MIPS

2

4

DC43a

DC43b

DC43d

DC43e

DC43f

DC47

4

4 MIPS

4

8

DC47a

DC47b

DC47c

DC47d

DC47e

DC51

8

16 MIPS

8

150

200

400

150

200

400

DC51a

DC51b

DC51d

DC51e

DC51f

100

150

70

A

LPRC (31 kHz)

A

100

150

A

Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance

only and are not tested.

2: Base IIDLE current is measured with core off, clock on, PMD bits set and all modules turned off.

3: On-chip voltage regulator is disabled (ENVREG tied to VSS).

4: On-chip voltage regulator is enabled (ENVREG tied to VDD).

DS39747F-page 220

 2005-2012 Microchip Technology Inc.

PIC24FJ128GA010 FAMILY

TABLE 27-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)

Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for Industrial

DC CHARACTERISTICS

Parameter

Typical⁽¹⁾

No.

Max

Units

Conditions

Power-Down Current (IPD)⁽²⁾

DC60

3

25

45

A

-40°C

+25°C

+85°C

-40°C

+25°C

+85°C

DC60a

DC60b

DC60f

DC60g

DC60h

2.0V⁽³⁾

3.6V⁽⁴⁾

100

20

27

120

600

40

Base Power-Down Current⁽⁵⁾

60

600

Module Differential Current

DC61

10

8

25

15

A

-40°C

+25°C

+85°C

-40°C

+25°C

+85°C

-40°C

+25°C

+85°C

-40°C

+25°C

+85°C

DC61a

DC61b

DC61f

DC61g

DC61h

DC62

2.0V⁽³⁾

3.6V⁽⁴⁾

2.0V⁽³⁾

3.6V⁽⁴⁾

(5)

Watchdog Timer Current: IWDT

DC62a

DC62b

DC62f

DC62g

DC62h

8

RTCC + Timer1 w/32 kHz Crystal:

(5)

IRTCC

8

Note 1: Data in the Typical column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance

only and are not tested.

2: Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and

pulled high. WDT, etc., are all switched off. Unused PMD bits are set. VREGS bit is clear.

3: On-chip voltage regulator is disabled (ENVREG tied to VSS).

4: On-chip voltage regulator is enabled (ENVREG tied to VDD).

5: The  current is the additional current consumed when the module is enabled. This current should be

added to the base IPD current.

 2005-2012 Microchip Technology Inc.

DS39747F-page 221

PIC24FJ128GA010 FAMILY

TABLE 27-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS

Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for Industrial

DC CHARACTERISTICS

Param

No.

Sym

Characteristic

Min

Typ⁽¹⁾

Max

Units

Conditions

VIL

Input Low Voltage⁽⁴⁾

I/O Pins with ST Buffer

I/O Pins with TTL Buffer

MCLR

DI10

VSS

—

0.2 VDD

0.15 VDD

0.2 VDD

0.3 VDD

0.8

V

DI11

DI15

DI16

DI17

DI18

DI19

OSC1 (XT mode)

OSC1 (HS mode)

I/O Pins with I²C™ Buffer

I/O Pins with SMBus Buffer

Input High Voltage⁽⁴⁾

SMBus enabled

VIH

DI20

DI21

I/O Pins with ST Buffer:

with Analog Functions

Digital Only

0.8 VDD

—

VDD

5.5

V

I/O Pins with TTL Buffer:

with Analog Functions,

Digital Only

0.25 VDD + 0.8

—

VDD

5.5

V

DI25

DI26

DI27

DI28

MCLR

0.8 VDD

0.7 VDD

—

VDD

V

OSC1 (XT mode)

OSC1 (HS mode)

I/O Pins with I²C Buffer:

with Analog Functions

Digital Only

0.7 VDD

—

VDD

5.5

V

DI29

I/O Pins with SMBus Buffer:

with Analog Functions

Digital Only

2.1

VDD

5.5

V

2.5V  VPIN  VDD

VDD = 3.3V, VPIN = VSS

VDD = 2.0V

DI30

DI31

ICNPU CNxx Pull-up Current

50

—

250

—

400

30

A

IPU

Maximum Load Current

for Digital High Detection

w/Internal Pull-up

—

100

VDD = 3.3V

IIL

Input Leakage Current^(2,3)

DI50

DI51

I/O Ports:

with Analog Functions

Digital Only

Pin at high-impedance

VSS  VPIN  VDD

VSS  VPIN  5.5V

—

50

1000

nA

Analog Input Pins

—

50

1000

nA

VSS  VPIN  VDD,

Pin at high-impedance

DI55

DI56

MCLR

OSC1

—

50

1000

nA

VSS VPIN VDD

VSS VPIN VDD,

XT and HS modes

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltages.

3: Negative current is defined as current sourced by the pin.

4: Refer to Table 1-2 for I/O pins buffer types.

DS39747F-page 222

 2005-2012 Microchip Technology Inc.

PIC24FJ128GA010 FAMILY

TABLE 27-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS

Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for Industrial

DC CHARACTERISTICS

Param

No.

Sym

Characteristic

Min

Typ⁽¹⁾Max

Units

Conditions

VOL

Output Low Voltage

DO10

DO16

I/O Ports

—

0.4

V

IOL = 8.5 mA, VDD = 3.6V

IOL = 6.0 mA, VDD = 2.0V

IOL = 8.5 mA, VDD = 3.6V

IOL = 6.0 mA, VDD = 2.0V

OSC2/CLKO

VOH

Output High Voltage

DO20

I/O Ports

3.0

2.4

1.65

1.4

2.4

1.4

—

V

IOH = -3.0 mA, VDD = 3.6V

IOH = -6.0 mA, VDD = 3.6V

IOH = -1.0 mA, VDD = 2.0V

IOH = -3.0 mA, VDD = 2.0V

IOH = -6.0 mA, VDD = 3.6V

IOH = -3.0 mA, VDD = 2.0V

DO26

OSC2/CLKO

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

 2005-2012 Microchip Technology Inc.

DS39747F-page 223

PIC24FJ128GA010 FAMILY

TABLE 27-10: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  TA  +85°C for Industrial

DC CHARACTERISTICS

Param. Symbol

Characteristic

Min.

Typ⁽¹⁾

Max.

Units

Conditions

IICL

IICH

Input Low Injection Current

Input High Injection Current

DI60a

DI60b

All pins except VDD, VSS,

AVDD, AVSS, MCLR, VCAP,

RB11, SOSCI, SOSCO, D+,

D-, VUSB and VBUS

0

—

-5^(2,5)

mA

All pins except VDD, VSS,

AVDD, AVSS, MCLR, VCAP,

0

—

+5^(3,4,5)mA RB11, SOSCI, SOSCO, D+,

D-, VUSB and VBUS, and all

5V tolerant pins⁽⁴⁾

IICT

Total Input Injection Current

DI60c

(sum of all I/O and control

pins)

-20⁽⁶⁾

+20⁽⁶⁾

mA Absolute instantaneous sum

of all ± input injection cur-

rents from all I/O pins

( | IICL + | IICH | )  IICT

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.

2: Characterized but not tested.

3: Non-5V tolerant pins VIH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V. Characterized but not

tested.

4: Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V.

5: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts.

6: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted

provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not

exceed the specified limit. Characterized but not tested.

DS39747F-page 224

 2005-2012 Microchip Technology Inc.

PIC24FJ128GA010 FAMILY

TABLE 27-11: DC CHARACTERISTICS: PROGRAM MEMORY

Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for Industrial

DC CHARACTERISTICS

Param

No.

Sym

Characteristic

Min

Typ⁽¹⁾

Max

Units

Conditions

Program Flash Memory

Cell Endurance

D130

D131

EP

VPR

100

1K

—

E/W -40C to +85C

VDD for Read

VMIN

3.6

V

VMIN = Minimum operating

voltage

D132B VPEW VDD for Self-Timed

Erase/Write

2.25

—

3.6

V

D133A TIW

Self-Timed Write Cycle Time

—

3

—

ms

D134

TRETD Characteristic Retention

20

—

Year Provided no other specifications

are violated

D135

IDDP

Supply Current During

Programming

—

10

—

mA

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.

TABLE 27-12: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS

Operating Conditions: -40°C < TA < +85°C (unless otherwise stated)

Param

No.

Sym

Characteristics

Min Typ Max Units

Comments

VRGOUT Regulator Output Voltage

External Filter Capacitor Value

—

2.5

10

—

V

CEFC

4.7

F Series resistance < 3 Ohm recommended;

< 5 Ohm required.

TVREG Voltage Regulator Start-up Time

TPWRT Power-up Timer Period

—

500

64

—

1

s ENVREG = VDD

ms ENVREG = VSS

ms

TBG

Band Gap Reference Start-up Time

—

 2005-2012 Microchip Technology Inc.

DS39747F-page 225

PIC24FJ128GA010 FAMILY

TABLE 27-13: COMPARATOR SPECIFICATIONS

Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated)

Param

No.

Symbol

Characteristic

Min

Typ

Max

Units

Comments

D300

D301

D302

VIOFF

VICM

Input Offset Voltage*

—

0

10

—

30

VDD

—

mV

V

Input Common Mode Voltage*

CMRR

Common Mode Rejection

Ratio*

55

dB

300

301

TRESP

Response Time*⁽¹⁾

—

150

—

400

10

ns

TMC2OV Comparator Mode Change to

Output Valid*

s

*

Parameters are characterized but not tested.

Note 1: Response time is measured with one comparator input at (VDD – 1.5)/2, while the other input transitions

from VSS to VDD.

TABLE 27-14: COMPARATOR VOLTAGE REFERENCE SPECIFICATIONS

Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated)

Param

No.

Symbol

Characteristic

Min

Typ

Max

Units

Comments

VRD310 CVRES

VRD311 CVRAA

VRD312 CVRUR

Resolution

VDD/24

—

2k

—

VDD/32

AVDD – 1.5

—

LSb



Absolute Accuracy

Unit Resistor Value (R)

Settling Time⁽¹⁾

—

VR310

TSET

—

10

s

Note 1: Settling time measured while CVRR = 1and CVR<3:0> bits transition from ‘0000’ to ‘1111’.

DS39747F-page 226

 2005-2012 Microchip Technology Inc.

PIC24FJ128GA010 FAMILY

27.2 AC Characteristics and Timing Parameters

The information contained in this section defines the PIC24FJ128GA010 AC characteristics and timing parameters.

TABLE 27-15: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC

Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C  TA  +85°C for Industrial

Operating voltage VDD range as described in Section 27.1 “DC Characteristics”.

FIGURE 27-2:

LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS

Load Condition 1 – for all pins except OSC2

VDD/2

Load Condition 2 – for OSC2

CL

RL

VSS

CL

RL = 464

CL = 50 pF for all pins except OSC2

15 pF for OSC2 output

VSS

TABLE 27-16: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS

Param

Symbol

Characteristic

Min

Typ⁽¹⁾Max Units

Conditions

No.

DO50 COSC2

OSC2/CLKO Pin

—

15

pF In XT and HS modes when

external clock is used to drive

OSC1

DO56 CIO

DO58 CB

All I/O Pins and OSC2

SCLx, SDAx

—

50

pF EC mode

pF In I²C™ mode

400

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

 2005-2012 Microchip Technology Inc.

DS39747F-page 227

PIC24FJ128GA010 FAMILY

FIGURE 27-3:

EXTERNAL CLOCK TIMING

Q4

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Q1

Q3

Q2

OSC1

CLKO

OS20

OS25

OS30 OS30

OS31 OS31

OS40

OS41

TABLE 27-17: EXTERNAL CLOCK TIMING REQUIREMENTS

Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for Industrial

AC CHARACTERISTICS

Param

No.

Sym

Characteristic

Min

Typ⁽¹⁾

Max

Units

Conditions

OS10

FOSC External CLKI Frequency

(external clocks allowed

only in EC mode)

DC

3

—

32

8

MHz EC mode

MHz ECPLL mode

Oscillator Frequency

3.5

10

—

10

8

32

33

MHz XT mode

MHz XTPLL mode

MHz HS mode

31

kHz

SOSC

OS20 TOSC TOSC = 1/FOSC

—

See Parameter OS10

for FOSC value

OS25 TCY

Instruction Cycle Time⁽²⁾

62.5

—

DC

—

ns

OS30 TosL, External Clock in (OSC1)

TosH High or Low Time

0.45 x TOSC

EC mode

OS31 TosR, External Clock in (OSC1)

TosF Rise or Fall Time

—

20

ns

OS40 TckR CLKO Rise Time⁽³⁾

OS41 TckF CLKO Fall Time⁽³⁾

—

6

10

ns

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

2: Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values are

based on characterization data for that particular oscillator type under standard operating conditions with

the device executing code. Exceeding these specified limits may result in an unstable oscillator operation

and/or higher than expected current consumption. All devices are tested to operate at “Min.” values with an

external clock applied to the OSC1/CLKI pin. When an external clock input is used, the “Max.” cycle time

limit is “DC” (no clock) for all devices.

3: Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin. CLKO is low for the

Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY).

DS39747F-page 228

 2005-2012 Microchip Technology Inc.

PIC24FJ128GA010 FAMILY

TABLE 27-18: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.0V TO 3.6V)

Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for Industrial

AC CHARACTERISTICS

Param

No.

Sym

Characteristic⁽¹⁾

Min

Typ⁽²⁾

Max

Units

Conditions

OS50 FPLLI PLL Input Frequency

Range

3

—

8

32

2

MHz ECPLL, HSPLL, XTPLL

modes

OS51 FSYS PLL Output Frequency

Range

12

—

-2

—

1

MHz

ms

%

OS52 TLOCK PLL Start-up Time

(Lock Time)

OS53 DCLK CLKO Stability (Jitter)

+2

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

TABLE 27-19: INTERNAL RC OSCILLATOR SPECIFICATIONS

AC CHARACTERISTICS

Industrial

Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C  TA +85°C for Industrial

Param

No.

Sym

Characteristic⁽¹⁾

Min

Typ

Max

Units

Conditions

—

15

—

µs

TFRC FRC Start-up Time

TLPRC LPRC Start-up Time

500

Note 1: These parameters are characterized but not tested in manufacturing.

TABLE 27-20: INTERNAL RC OSCILLATOR ACCURACY

Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for Industrial

AC CHARACTERISTICS

Param

No.

Characteristic

Min

Typ

Max

Units

Conditions

Internal FRC Accuracy @ 8 MHz⁽¹⁾

F20

FRC

-2

-5

—

+2

+5

%

+25°C

VDD = 3.0 - 3.6V

-40°C  TA +85°C

F21

LPRC @ 31 kHz⁽¹⁾

-15

+15

Note 1: Change of LPRC frequency as VDD changes.

 2005-2012 Microchip Technology Inc.

DS39747F-page 229

PIC24FJ128GA010 FAMILY

FIGURE 27-4:

CLKO AND I/O TIMING CHARACTERISTICS

I/O Pin

(Input)

DI35

DI40

I/O Pin

(Output)

New Value

Old Value

DO31

DO32

Note: Refer to Figure 27-2 for load conditions.

TABLE 27-21: CLKO AND I/O TIMING REQUIREMENTS

Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for Industrial

AC CHARACTERISTICS

Param

No.

Sym

Characteristic

Min

Typ⁽¹⁾

Max

Units

Conditions

DO31 TIOR Port Output Rise Time

DO32 TIOF Port Output Fall Time

—

20

10

—

25

—

ns

DI35

TINP

INTx Pin High or Low

Time (output)

DI40

TRBP CNx High or Low Time

(input)

2

—

TCY

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.

DS39747F-page 230

 2005-2012 Microchip Technology Inc.

PIC24FJ128GA010 FAMILY

TABLE 27-22: A/D MODULE SPECIFICATIONS

AC CHARACTERISTICS

Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C  TA  +85°C

Param Symbol

No.

Characteristic

Min. Typ

Max.

Units

Conditions

Device Supply

AD01 AVDD

AD02 AVSS

Module VDD Supply

Module VSS Supply

Greater of

VDD – 0.3

or 2.0

—

Lesser of

VDD + 0.3

or 3.6

V

VSS – 0.3

—

VSS + 0.3

Reference Inputs

AD05 VREFH

AD06 VREFL

AD07 VREF

Reference Voltage High

Reference Voltage Low

AVSS + 1.7

AVSS

—

AVDD

V

AVDD – 1.7

AVDD + 0.3

Absolute Reference

Voltage

AVSS – 0.3

AD08 IVREF

AD09 ZVREF

Reference Voltage Input

Current

—

1.25

—

mA

Reference Input

Impedance

10K



Analog Input

(2)

AD10 VINH-VINL Full-Scale Input Span

VREFL

AVSS – 0.3

—

VREFH

AVDD + 0.3

±0.610

V

AD11 VIN

AD12

Absolute Input Voltage

Leakage Current

—

±0.001

A

VINL = AVSS = VREFL = 0V,

AVDD = VREFH = 5V,

Source Impedance = 2.5 k

AD14 VINL

AD17 RIN

Absolute VINL Input Voltage AVSS – 0.3

AVDD/2

2.5K

V

Recommended

—

Impedance of Analog Voltage

A/D Accuracy

10 data bits

+1

AD20a Nr

Resolution

bits

(2)

AD21a INL

Integral Nonlinearity

—

<±2

<±1

±3

LSb VINL = AVSS = VREFL = 0V,

AVDD = VREFH = 3V

(2)

AD22a DNL

AD23a GERR

AD24a EOFF

Differential Nonlinearity

+0.5

+1

LSb VINL = AVSS = VREFL = 0V,

AVDD = VREFH = 3V

(2)

Gain Error

LSb VINL = AVSS = VREFL = 0V,

AVDD = VREFH = 3V

(2)

Offset Error

+1

±2

LSb VINL = AVSS = VREFL = 0V,

AVDD = VREFH = 3V

(1)

AD25a

—

Monotonicity

—

Guaranteed

Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.

2: Measurements are taken with external VREF+ and VREF- used as the A/D voltage reference.

 2005-2012 Microchip Technology Inc.

DS39747F-page 231

PIC24FJ128GA010 FAMILY

TABLE 27-23: A/D CONVERSION TIMING REQUIREMENTS⁽¹⁾

Standard Operating Conditions: 2.0V to 3.6V (unless

otherwise stated)

Operating temperature

AC CHARACTERISTICS

-40°C  TA  +85°C for Industrial

Param

No.

Sym

Characteristic

Min

75

Typ

Max

Units

Conditions

AD50

TAD

A/D Clock Period

—

ns

TCY = 75 ns, ADxCON3

is in default state

AD51

tRC

A/D Internal RC Oscillator

Period

—

250

—

ns

Conversion Rate

AD55 tCONV Conversion Time

AD56 FCNV Throughput Rate

AD57 tSAMP Sample Time

—

12

—

1

—

500

—

TAD

ksps

TAD

AVDD > 2.7V

Clock Parameters

AD61

tPSS

Sample Start Delay from

Setting Sample bit (SAMP)

2

—

3

TAD

Note 1: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity

performance, especially at elevated temperatures.

DS39747F-page 232

 2005-2012 Microchip Technology Inc.

PIC24FJ128GA010 FAMILY

28.0 PACKAGING INFORMATION

28.1 Package Marking Information

64-Lead TQFP (10x10x1 mm)

Example

XXXXXXXXXX

YYWWNNN

PIC24FJ128

GA006-I/

PT

e

3

1110017

80-Lead TQFP (12x12x1 mm)

Example

XXXXXXXXXXXX

YYWWNNN

PIC24FJ128GA

008-I/PT

1110017

e

3

100-Lead TQFP (12x12x1 mm)

Example

XXXXXXXXXXXX

YYWWNNN

PIC24FJ128GA

010-I/PT

e

3

1110017

100-Lead TQFP (14x14x1 mm)

Example

XXXXXXXXXXXX

YYWWNNN

PIC24FJ128GA

010-I/PF

1110017

e

3

Legend: XX...X Customer-specific information

Y

YY

WW

NNN

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

)

e3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

 2005-2012 Microchip Technology Inc.

DS39747F-page 233

PIC24FJ128GA010 FAMILY

64-Lead QFN (9x9x0.9 mm)

Example

XXXXXXXXXXX

YYWWNNN

PIC24FJ128

GA010-I/MR

e

3

1150017

DS39747F-page 234

 2005-2012 Microchip Technology Inc.

PIC24FJ128GA010 FAMILY

28.2 Package Details

The following sections give the technical details of the packages.

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇꢎꢏꢌꢐꢇꢑꢒꢅꢆꢇꢓꢉꢅꢋꢔꢅꢍꢕꢇꢖꢈꢎꢗꢇMꢇꢘꢙꢚꢘꢙꢚꢘꢇꢛꢛꢇꢜ ꢆ!"ꢇ#$ꢙꢙꢇꢛꢛꢇ%ꢎꢑꢓꢈ&

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D1

E

e

E1

N

b

1 2 3

NOTE 1

c

NOTE 2

α

A

φ

A2

A1

β

L

L1

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1ꢗ+2 1ꢆ!ꢃꢌꢅꢑꢃ'ꢈꢄ!ꢃꢋꢄꢁꢅꢘꢍꢈꢋꢉꢈ&ꢃꢌꢆꢇꢇꢊꢅꢈ$ꢆꢌ&ꢅ ꢆꢇ"ꢈꢅ!ꢍꢋ*ꢄꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ!ꢁ

ꢙ.32 ꢙꢈ%ꢈꢉꢈꢄꢌꢈꢅꢑꢃ'ꢈꢄ!ꢃꢋꢄ(ꢅ"!"ꢆꢇꢇꢊꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ(ꢅ%ꢋꢉꢅꢃꢄ%ꢋꢉ'ꢆ&ꢃꢋꢄꢅꢏ"ꢉꢏꢋ!ꢈ!ꢅꢋꢄꢇꢊꢁ

ꢒꢃꢌꢉꢋꢌꢍꢃꢏ ꢘꢈꢌꢍꢄꢋꢇꢋꢕꢊ ꢑꢉꢆ*ꢃꢄꢕ +ꢓꢔꢞꢓ@/1

 2005-2012 Microchip Technology Inc.

DS39747F-page 235

PIC24FJ128GA010 FAMILY

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS39747F-page 236

 2005-2012 Microchip Technology Inc.

PIC24FJ128GA010 FAMILY

80-Lead Plastic Thin Quad Flatpack (PT) – 12x12x1 mm Body, 2.00 mm Footprint [TQFP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

D1

E

e

E1

N

b

NOTE 1

12 3

α

NOTE 2

A

c

φ

A2

β

A1

L1

L

Units

MILLIMETERS

Dimension Limits

MIN

NOM

80

0.50 BSC

–

1.00

–

MAX

Number of Leads

Lead Pitch

Overall Height

Molded Package Thickness

Standoff

Foot Length

N

e

A

A2

A1

L

–

1.20

1.05

0.15

0.75

0.95

0.05

0.45

0.60

Footprint

Foot Angle

L1

φ

1.00 REF

3.5°

0°

7°

Overall Width

Overall Length

E

D

E1

D1

c

14.00 BSC

12.00 BSC

–

Molded Package Width

Molded Package Length

Lead Thickness

Lead Width

Mold Draft Angle Top

Mold Draft Angle Bottom

0.09

0.17

11°

0.20

0.27

13°

b

α

0.22

12°

β

11°

13°

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Chamfers at corners are optional; size may vary.

3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-092B

 2005-2012 Microchip Technology Inc.

DS39747F-page 237

PIC24FJ128GA010 FAMILY

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS39747F-page 238

 2005-2012 Microchip Technology Inc.

PIC24FJ128GA010 FAMILY

100-Lead Plastic Thin Quad Flatpack (PT) – 12x12x1 mm Body, 2.00 mm Footprint [TQFP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

D1

e

E

E1

N

b

123

NOTE 2

NOTE 1

c

α

A

φ

L

A1

β

A2

L1

Units

Dimension Limits

MILLIMETERS

NOM

MIN

MAX

Number of Leads

Lead Pitch

Overall Height

N

e

A

100

0.40 BSC

–

1.20

1.05

0.15

0.75

Molded Package Thickness

Standoff

Foot Length

A2

A1

L

0.95

0.05

0.45

1.00

–

0.60

Footprint

Foot Angle

L1

φ

1.00 REF

3.5°

0°

7°

Overall Width

E

D

E1

D1

c

14.00 BSC

12.00 BSC

–

Overall Length

Molded Package Width

Molded Package Length

Lead Thickness

Lead Width

0.09

0.13

11°

0.20

0.23

13°

b

α

0.18

12°

Mold Draft Angle Top

Mold Draft Angle Bottom

β

11°

13°

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Chamfers at corners are optional; size may vary.

3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-100B

 2005-2012 Microchip Technology Inc.

DS39747F-page 239

PIC24FJ128GA010 FAMILY

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS39747F-page 240

 2005-2012 Microchip Technology Inc.

PIC24FJ128GA010 FAMILY

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D

D1

e

E1

E

b

N

α

NOTE 1

1 23

NOTE 2

A

φ

c

A2

A1

β

L1

L

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8

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)

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ꢔꢁ ꢑꢃ'ꢈꢄ!ꢃꢋꢄꢃꢄꢕꢅꢆꢄ#ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢃꢄꢕꢅꢏꢈꢉꢅꢖꢗꢒ.ꢅ0ꢀꢔꢁ/ꢒꢁ

1ꢗ+2 1ꢆ!ꢃꢌꢅꢑꢃ'ꢈꢄ!ꢃꢋꢄꢁꢅꢘꢍꢈꢋꢉꢈ&ꢃꢌꢆꢇꢇꢊꢅꢈ$ꢆꢌ&ꢅ ꢆꢇ"ꢈꢅ!ꢍꢋ*ꢄꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ!ꢁ

ꢙ.32 ꢙꢈ%ꢈꢉꢈꢄꢌꢈꢅꢑꢃ'ꢈꢄ!ꢃꢋꢄ(ꢅ"!"ꢆꢇꢇꢊꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ(ꢅ%ꢋꢉꢅꢃꢄ%ꢋꢉ'ꢆ&ꢃꢋꢄꢅꢏ"ꢉꢏꢋ!ꢈ!ꢅꢋꢄꢇꢊꢁ

ꢒꢃꢌꢉꢋꢌꢍꢃꢏ ꢘꢈꢌꢍꢄꢋꢇꢋꢕꢊ ꢑꢉꢆ*ꢃꢄꢕ +ꢓꢔꢞꢀꢀꢓ1

 2005-2012 Microchip Technology Inc.

DS39747F-page 241

PIC24FJ128GA010 FAMILY

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS39747F-page 242

 2005-2012 Microchip Technology Inc.

PIC24FJ128GA010 FAMILY

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2005-2012 Microchip Technology Inc.

DS39747F-page 243

PIC24FJ128GA010 FAMILY

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS39747F-page 244

 2005-2012 Microchip Technology Inc.

PIC24FJ128GA010 FAMILY

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2005-2012 Microchip Technology Inc.

DS39747F-page 245

PIC24FJ128GA010 FAMILY

NOTES:

DS39747F-page 246

 2005-2012 Microchip Technology Inc.

PIC24FJ128GA010 FAMILY

APPENDIX A: REVISION HISTORY

Revision A (September 2005)

Original data sheet for PIC24FJ128GA010 family

devices.

Revision B (March 2006)

Update of electrical specifications.

Revision C (June 2006)

Update of electrical specifications.

Revision D (September 2007)

Minor changes in the overall data sheet

Revision E (October 2009)

Updated to remove Preliminary status.

Revision F (January 2012)

Added Section 2.0 “Guidelines for Getting Started

with 16-bit Microcontrollers”. In Section 28.0

“Packaging Information”, Land Patterns of all the

packaging have been added. Minor edits to text

throughout the document.

 2005-2012 Microchip Technology Inc.

DS39747F-page 247

PIC24FJ128GA010 FAMILY

NOTES:

DS39747F-page 248

 2005-2012 Microchip Technology Inc.

PIC24FJ128GA010 FAMILY

INDEX

A

C

A/D

C Compilers

Conversion Timing Requirements............................. 232

Module Specifications............................................... 231

MPLAB C18.............................................................. 214

Clock Switching

AC

Enabling.................................................................... 103

Operation.................................................................. 103

Oscillator Sequence ................................................. 103

Characteristics .......................................................... 227

Load Conditions........................................................ 227

Temperature and Voltage Specifications.................. 227

Code Examples

Alternate Interrupt Vector Table (AIVT) .............................. 63

Arithmetic Logic Unit (ALU)................................................. 30

Assembler

Basic Code Sequence for Clock Switching .............. 104

Erasing a Program Memory Block.............................. 54

Initiating a Programming Sequence ........................... 55

Loading Write Buffers................................................. 55

Port Write/Read........................................................ 108

Programming a Single Word of Flash

MPASM Assembler................................................... 214

B

Block Diagrams

Program Memory................................................ 56

PWRSAV Instruction Syntax .................................... 105

Comparator Module.......................................................... 189

Comparator Voltage Reference........................................ 193

Configuring ............................................................... 193

Configuration Bits ............................................................. 195

Configuration Register Protection..................................... 203

Core Features....................................................................... 7

16-Bit Architecture........................................................ 7

Easy Migration.............................................................. 8

Oscillator Options, Features......................................... 7

PIC24FJ128GA010 Family Devices............................. 9

Power-Saving Technology............................................ 7

CPU .................................................................................... 25

Control Registers........................................................ 28

Programmer’s Model .................................................. 27

CPU Clocking Scheme ....................................................... 98

CRC

Example Setup ......................................................... 175

Operation in Power Save Modes.............................. 177

Overview................................................................... 175

Registers .................................................................. 175

User Interface........................................................... 176

Customer Change Notification Service............................. 253

Customer Notification Service .......................................... 253

Customer Support............................................................. 253

CVRR

10-Bit High-Speed A/D Converter............................. 180

16-Bit Timer1 Module................................................ 111

8-Bit Multiplexed Address and Data Application....... 162

Accessing Program Memory with

Table Instructions ............................................... 48

Addressable Parallel Slave Port ............................... 160

Comparator I/O Operating Modes............................. 189

Comparator Voltage Reference ................................ 193

Connections for On-Chip Voltage Regulator............. 201

Device Clock............................................................... 97

2

I C............................................................................. 138

Input Capture ............................................................ 119

LCD Control, Byte Mode........................................... 162

Legacy Parallel Slave Port........................................ 160

Master Mode, Demultiplexed Addressing ................. 160

Master Mode, Fully Multiplexed Addressing ............. 161

Master Mode, Partially Multiplexed Addressing........ 161

Multiplexed Addressing Application .......................... 161

Output Compare Module........................................... 121

Parallel EEPROM (Up to 15-Bit Address, 16-Bit Data)...

162

Parallel EEPROM (Up to 15-Bit Address, 8-Bit Data).....

162

Partially Multiplexed Addressing Application ............ 161

PIC24F CPU Core ...................................................... 26

PIC24FJ128GA010 Family (General)......................... 10

PMP Module ............................................................. 153

Program Space Visibility Operation ............................ 49

Reset System.............................................................. 57

RTCC........................................................................ 163

Shared Port Structure ............................................... 107

SPI Master, Frame Master Connection..................... 135

SPI Master, Frame Slave Connection....................... 135

SPI Master/Slave Connection (Enhanced

Buffer Modes) ................................................... 134

SPI Master/Slave Connection (Standard Mode)....... 134

SPI Slave, Frame Master Connection....................... 135

SPI Slave, Frame Slave Connection......................... 135

SPIx Module (Enhanced Mode)................................ 129

SPIx Module (Standard Mode).................................. 128

Timer2 and Timer4 (16-Bit Synchronous)................. 115

Timer2/3 and Timer4/5 (32-Bit)................................. 114

Timer3 and Timer5 (16-Bit Synchronous)................. 115

UARTx ...................................................................... 145

Watchdog Timer (WDT)............................................ 202

CVrsrc....................................................................... 193

D

Data Memory

Address Space ........................................................... 33

Width .................................................................. 33

Memory Map for PIC24F128GA010

Family Devices ................................................... 33

Near Data Space........................................................ 34

Organization and Alignment ....................................... 34

SFR Space ................................................................. 34

Software Stack ........................................................... 46

 2005-2012 Microchip Technology Inc.

DS39747F-page 249

PIC24FJ128GA010 FAMILY

DC Characteristics ............................................................218

Comparator Voltage Reference

In-Circuit Debugger........................................................... 203

In-Circuit Serial Programming (ICSP)............................... 203

Input Capture.................................................................... 119

Registers .................................................................. 120

Instruction Set

Specifications....................................................226

I/O Pin Input Specifications............................... 222, 224

I/O Pin Output Specifications....................................223

Idle Current (IIDLE) ....................................................220

Operating Current (IDD).............................................219

Operating MIPS vs. Voltage......................................218

Power-Down Current (IPD) ........................................221

Program Memory ......................................................225

Temperature and Voltage Specifications..................218

Thermal Operating Conditions..................................218

Thermal Packaging ...................................................218

Development Support .......................................................213

Overview................................................................... 207

Summary .................................................................. 205

2

Inter-Integrated Circuit (I C) ............................................. 137

Internal RC Oscillator

Use with WDT........................................................... 202

Internet Address ............................................................... 253

Interrupt

Setup Procedures

Initialization......................................................... 96

Interrupt Control and Status Registers ............................... 66

IECx............................................................................ 66

IFSx ............................................................................ 66

INTCON1, INTCON2 .................................................. 66

IPCx............................................................................ 66

Interrupt Controller.............................................................. 63

Interrupt Vector Table (IVT)................................................ 63

Interrupts

E

Electrical Characteristics...................................................217

Absolute Maximum Ratings ......................................217

ENVREG Pin.....................................................................201

Equations

A/D Conversion Clock Period ...................................186

Calculating the PWM Period .....................................123

Calculation for Maximum PWM Resolution...............123

CRC Polynomial........................................................175

Relationship Between Device and SPI

Setup Procedure,

Interrupt Disable ................................................. 96

Setup Procedures....................................................... 96

Interrupt Service Routine (ISR) .......................... 96

Trap Service Routine (TSR) ............................... 96

Clock Speed......................................................136

UARTx Baud Rate with BRGH = 0............................146

UARTx Baud Rate with BRGH = 1............................146

Errata ....................................................................................6

Examples

M

Memory Organization ......................................................... 31

Microchip Internet Web Site.............................................. 253

MPLAB ASM30 Assembler, Linker, Librarian................... 214

MPLAB Integrated Development

Baud Rate Error Calculation (BRGH = 0) .................146

PWM Period and Duty Cycle Calculations................124

Setting RTCWREN Bit in MPLAB C30......................164

Environment Software .............................................. 213

MPLAB PM3 Device Programmer .................................... 216

MPLAB REAL ICE In-Circuit Emulator System ................ 215

MPLINK Object Linker/MPLIB Object Librarian................ 214

F

Flash Configuration Words.......................................... 32, 195

Flash Program Memory.......................................................51

Control Registers ........................................................52

Enhanced ICSP ..........................................................52

JTAG Operation ..........................................................52

Operations ..................................................................52

Programming a Single Word.......................................56

Programming Algorithm ..............................................54

RTSP Operation..........................................................52

Table Instructions........................................................51

FSCM

O

On-Chip Voltage Regulator............................................... 201

Brown-out Reset (BOR)............................................ 201

Power-on Reset (POR)............................................. 201

Power-up Requirements........................................... 201

Oscillator Configuration ...................................................... 97

Clock Switching Mode Configuration Bits................... 98

Control Registers........................................................ 99

CLKDIV............................................................... 99

OSCCON............................................................ 99

OSCTUN ............................................................ 99

Output Compare ............................................................... 121

Continuous Output Pulse Generation Setup............. 122

Modes of Operation .................................................. 121

Pulse-Width Modulation.................................... 123

Pulse-Width Modulation

and Device Resets......................................................61

Delay for Crystal and PLL Clock Sources...................61

I

I/O Ports............................................................................107

Configuring Analog Pins ...........................................108

Voltage Considerations.....................................108

Input Change Notification..........................................109

Open-Drain Configuration .........................................108

Parallel I/O (PIO).......................................................107

Write/Read Timing ....................................................108

Duty Cycle ........................................................ 123

PWM Period ..................................................... 123

Single Output Pulse Generation Setup..................... 121

2

I C

Clock Rates...............................................................139

Communicating as Master in a Single

Master Environment..........................................137

Setting Baud Rate When Operating as

Bus Master........................................................139

Slave Address Masking ............................................139

Implemented Interrupt Vectors (table).................................65

DS39747F-page 250

 2005-2012 Microchip Technology Inc.

PIC24FJ128GA010 FAMILY

SPI2............................................................................ 40

System........................................................................ 45

Timer .......................................................................... 37

UART1........................................................................ 40

UART2........................................................................ 40

P

Packaging ......................................................................... 233

Details....................................................................... 235

Marking ..................................................................... 233

Parallel Master Port (PMP) ............................................... 153

PIC24FJ128GA010 Family

Registers

AD1CHS (A/D Input Select)...................................... 184

AD1CON1 (A/D Control 1)........................................ 181

AD1CON2 (A/D Control 2)........................................ 182

AD1CON3 (A/D Control 3)........................................ 183

AD1CSSL (A/D Input Scan Select)........................... 185

AD1PCFG (A/D Port Configuration) ......................... 185

ALCFGRPT (Alarm Configuration) ........................... 167

ALMINSEC (Alarm Minutes and

Seconds Value)................................................ 171

ALMTHDY (Alarm Month and Day Value)................ 170

ALWDHR (Alarm Weekday and Hours Value) ......... 170

CLKDIV (Clock Divider)............................................ 101

CMCON (Comparator Control)................................. 190

CORCON (Core Control)...................................... 29, 67

CRCCON (CRC Control).......................................... 177

CVRCON (Comparator Voltage

Pinout Descriptions..................................................... 11

Pin Diagrams ........................................................................ 2

POR and Long Oscillator Start-up Times............................ 61

Power-Saving Features .................................................... 105

Clock Switching, Clock Frequency............................ 105

Doze Modes.............................................................. 106

Instruction-Based Modes .......................................... 105

Idle .................................................................... 106

Sleep................................................................. 105

Interrupts, Coincident with Power-Save

Instructions ....................................................... 106

Selective Peripheral Control ..................................... 106

Program Address Space..................................................... 31

Memory Map for PIC24FJ128GA010

Family Devices ................................................... 31

Program and Data Memory Spaces

Reference Control)........................................... 194

DEVID (Device ID).................................................... 199

DEVREV (Device Revision)...................................... 200

Flash Configuration Word 1...................................... 196

Flash Configuration Word 2...................................... 198

I2CxCON (I2Cx Control)........................................... 140

I2CxMSK (I2Cx Slave Mode Address Mask)............ 144

I2CxSTAT (I2Cx Status)........................................... 142

ICxCON (Input Capture x Control)............................ 120

IEC0 (Interrupt Enable Control 0)............................... 75

IEC1 (Interrupt Enable Control 1)............................... 76

IEC2 (Interrupt Enable Control 2)............................... 77

IEC3 (Interrupt Enable Control 3)............................... 78

IEC4 (Interrupt Enable Control 4)............................... 79

IFS0 (Interrupt Flag Status 0)..................................... 70

IFS1 (Interrupt Flag Status 1)..................................... 71

IFS2 (Interrupt Flag Status 2)..................................... 72

IFS3 (Interrupt Flag Status 3)..................................... 73

IFS4 (Interrupt Flag Status 4)..................................... 74

INTCON1 (Interrupt Control 1) ................................... 68

INTCON2 (Interrupt Control 2) ................................... 69

INTTREG (Interrupt Control and Status) .................... 95

IPC0 (Interrupt Priority Control 0)............................... 80

IPC1 (Interrupt Priority Control 1)............................... 81

IPC10 (Interrupt Priority Control 10)........................... 90

IPC11 (Interrupt Priority Control 11)........................... 90

IPC12 (Interrupt Priority Control 12)........................... 91

IPC13 (Interrupt Priority Control 13)........................... 92

IPC15 (Interrupt Priority Control 15)........................... 93

IPC16 (Interrupt Priority Control 16)........................... 94

IPC2 (Interrupt Priority Control 2)............................... 82

IPC3 (Interrupt Priority Control 3)............................... 83

IPC4 (Interrupt Priority Control 4)............................... 84

IPC5 (Interrupt Priority Control 5)............................... 85

IPC6 (Interrupt Priority Control 6)............................... 86

IPC7 (Interrupt Priority Control 7)............................... 87

IPC8 (Interrupt Priority Control 8)............................... 88

IPC9 (Interrupt Priority Control 9)............................... 89

MINSEC (Minutes and Seconds Value) ................... 169

MTHDY (Month and Day Value)............................... 168

NVMCON (Flash Memory Control)............................. 53

OCxCON Output Compare x Control) ...................... 125

OSCCON (Oscillator Control)..................................... 99

Interfacing ................................................................... 46

Program Memory

Data Access Using Table Instructions ........................ 48

Hard Memory Vectors................................................. 32

Interrupt Vector ........................................................... 32

Organization................................................................ 32

Reading Data Using Program Space Visibility............ 49

Reset Vector ............................................................... 32

Table Instructions

TBLRDH ............................................................. 48

TBLRDL .............................................................. 48

Program Space

Address Construction.................................................. 47

Addressing.................................................................. 46

Data Access from, Address Generation...................... 47

Program Verification and Code Protection........................ 203

Programmer’s Model........................................................... 25

R

Reader Response............................................................. 254

Register Maps

A/D.............................................................................. 41

CRC ............................................................................ 45

Dual Comparator......................................................... 44

I2C1 ............................................................................ 39

I2C2 ............................................................................ 39

ICN.............................................................................. 37

Input Capture .............................................................. 38

Interrupt Controller...................................................... 36

NVM............................................................................ 45

Output Compare ......................................................... 38

Pad Configuration ....................................................... 43

Parallel Master/Slave Port .......................................... 44

PMD............................................................................ 45

PORTA........................................................................ 41

PORTB........................................................................ 42

PORTC ....................................................................... 42

PORTD ....................................................................... 42

PORTE........................................................................ 43

PORTF........................................................................ 43

PORTG ....................................................................... 43

Real-Time Clock and Calendar (RTCC) ..................... 44

SPI1 ............................................................................ 40

 2005-2012 Microchip Technology Inc.

DS39747F-page 251

PIC24FJ128GA010 FAMILY

OSCTUN (FRC Oscillator Tune)...............................102

PADCFG1 (Pad Configuration Control) ....................166

T

Table of Contents ................................................................. 5

PMADDR (Parallel Port Address) .............................157

PMAEN (Parallel Port Enable) ..................................157

PMCON (Parallel Port Control) .................................154

PMMODE (Parallel Port Mode).................................156

PMSTAT (Parallel Port Status) .................................158

RCFGCAL (RTCC Calibration

and Configuration) ............................................165

RCON (Reset Control)................................................58

SPIxCON1 (SPIx Control 1)......................................132

SPIxCON2 (SPIx Control 2)......................................133

SPIxSTAT (SPIx Status and Control) .......................130

SR (CPU STATUS)...............................................28, 67

T1CON (Timer1 Control)...........................................112

TxCON (Timer2/4 Control)........................................116

TyCON (Timer3/5 Control)........................................117

UxMODE (UARTx Mode)..........................................148

UxSTA (UARTx Status and Control).........................150

WKDYHR (Weekday and Hours Value)....................169

YEAR (Year Value)...................................................168

Timer1 Module.................................................................. 111

Timer2/3 Module............................................................... 113

Timer4/5 Module............................................................... 113

Timing Diagrams

CLKO and I/O ........................................................... 230

External Clock........................................................... 228

Timing Requirements

Capacitive Loading on Output Pin ............................ 227

CLKO and I/O ........................................................... 230

External Clock........................................................... 228

Timing Specifications

Internal RC Oscillator................................................ 229

Internal RC Oscillator Accuracy................................ 229

PLL Clock ................................................................. 229

U

UARTx

Baud Rate Generator (BRG) .................................... 146

Break and Sync Transmit Sequence ........................ 147

Infrared Support........................................................ 147

IrDA

Built-in Encoder and Decoder........................... 147

External Support, Clock Output........................ 147

Operation of UxCTS and UxRTS Control Pins ......... 147

Receiving in

Registers Map

CPU Core....................................................................35

Reset Sequence..................................................................63

Resets.................................................................................57

Clock Source Selection...............................................59

Device Times ..............................................................59

Revision History ................................................................247

RTCC

8-Bit or 9-Bit Data Mode................................... 147

Transmitting

Alarm.........................................................................172

Configuring........................................................172

Interrupt.............................................................172

ALRMVAL Register Mappings ..................................170

Calibration.................................................................172

Control Registers ......................................................165

Module Registers......................................................164

Mapping ............................................................164

RTCVAL Register Mapping.......................................168

8-Bit Data Mode................................................ 147

Transmitting in

9-Bit Data Mode................................................ 147

Universal Asynchronous Receiver Transmitter (UART) ... 145

V

VDDCORE/VCAP Pin ........................................................... 201

W

Watchdog Timer (WDT).................................................... 202

Control Register........................................................ 202

Programming Considerations ................................... 202

WWW Address ................................................................. 253

WWW, On-Line Support ....................................................... 6

S

Serial Peripheral Interface (SPI) .......................................127

Software Simulator (MPLAB SIM).....................................215

Software Stack Pointer, Frame Pointer

CALL Stack Frame......................................................46

Special Features ...............................................................195

Code Protection ........................................................195

Flexible Configuration ...............................................195

In-Circuit Emulation...................................................195

In-Circuit Serial Programming (ICSP).......................195

JTAG Boundary Scan Interface ................................195

Watchdog Timer (WDT)............................................195

Special Function Register Reset States..............................61

Symbols Used in Opcode Descriptions.............................206

DS39747F-page 252

 2005-2012 Microchip Technology Inc.

PIC24FJ128GA010 FAMILY

THE MICROCHIP WEB SITE

CUSTOMER SUPPORT

Microchip provides online support via our WWW site at

www.microchip.com. This web site is used as a means

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following

information:

Users of Microchip products can receive assistance

through several channels:

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application notes and sample programs, design

resources, user’s guides and hardware support

documents, latest software releases and archived

software

• Development Systems Information Line

Customers

should

contact

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representative or field application engineer (FAE) for

support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

• General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

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Technical support is available through the web site

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Microchip’s customer notification service helps keep

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will receive e-mail notification whenever there are

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specified product family or development tool of interest.

To register, access the Microchip web site at

www.microchip.com. Under “Support”, click on

“Customer Change Notification” and follow the

registration instructions.

 2005-2012 Microchip Technology Inc.

DS39747F-page 253

PIC24FJ128GA010 FAMILY

READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip

product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our

documentation can better serve you, please FAX your comments to the Technical Publications Manager at

(480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

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Telephone: (_______) _________ - _________

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Literature Number: DS39747F

Application (optional):

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Y

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Device: PIC24FJ128GA010 family

Questions:

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

DS39747F-page 254

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PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Examples:

PIC 24 FJ 128 GA0 10 T - I / PT - XXX

a)

b)

PIC24FJ128GA008-I/PT 301:

General purpose PIC24F, 96 Kbyte program

memory, 80-pin, Industrial temp.,

Microchip Trademark

Architecture

TQFP package, QTP pattern #301.

PIC24FJ128GA010-I/PT:

Flash Memory Family

General purpose PIC24F, 128 Kbyte program

memory, 100-pin, Industrial temp.,

TQFP package.

Program Memory Size (KB)

Product Group

Pin Count

Tape and Reel Flag (if applicable)

Temperature Range

Package

Pattern

Architecture

24 = 16-bit modified Harvard without DSP

Flash Memory Family FJ = Flash program memory

Product Group

Pin Count

GA0 = General purpose microcontrollers

06 = 64-pin

08 = 80-pin

10 = 100-pin

Temperature Range

Package

I

= -40C to +85C (Industrial)

PT = 64-Lead, 80-Lead, 100-Lead (12x12x1 mm)

TQFP (Thin Quad Flatpack)

PF = 100-Lead (14x14x1 mm) TQFP (Thin Quad Flatpack)

MR = 64-lead (9x9x0.9 mm) QFN (Quad Flatpack, No Lead)

Pattern

Three-digit QTP, SQTP, Code or Special Requirements

(blank otherwise)

ES = Engineering Sample

 2005-2012 Microchip Technology Inc.

DS39747F-page 255

PIC24FJ128GA010 FAMILY

NOTES:

DS39747F-page 256

 2005-2012 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

32

PIC logo, rfPIC and UNI/O are registered trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MXDEV, MXLAB, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, chipKIT,

chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,

dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,

FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,

Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,

MPLINK, mTouch, Omniscient Code Generation, PICC,

PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,

rfLAB, Select Mode, Total Endurance, TSHARC,

UniWinDriver, WiperLock and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

ISBN:978-1-61341-955-7

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

 2005-2012 Microchip Technology Inc.

DS39747F-page 257

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Fax: 86-10-8528-2104

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

Boston

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Korea - Daegu

Tel: 82-53-744-4301

Fax: 82-53-744-4302

China - Chongqing

Tel: 86-23-8980-9588

Fax: 86-23-8980-9500

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

Korea - Seoul

China - Hangzhou

Tel: 86-571-2819-3187

Fax: 86-571-2819-3189

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

Cleveland

Independence, OH

Tel: 216-447-0464

Fax: 216-447-0643

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

China - Nanjing

Tel: 86-25-8473-2460

Fax: 86-25-8473-2470

Malaysia - Penang

Tel: 60-4-227-8870

Fax: 60-4-227-4068

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Detroit

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Indianapolis

Noblesville, IN

Tel: 317-773-8323

Fax: 317-773-5453

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Taiwan - Hsin Chu

Tel: 886-3-5778-366

Fax: 886-3-5770-955

Los Angeles

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-330-9305

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Santa Clara

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

China - Xian

Tel: 86-29-8833-7252

Fax: 86-29-8833-7256

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Toronto

Mississauga, Ontario,

Canada

China - Xiamen

Tel: 905-673-0699

Fax: 905-673-6509

Tel: 86-592-2388138

Fax: 86-592-2388130

China - Zhuhai

Tel: 86-756-3210040

Fax: 86-756-3210049

11/29/11

DS39747F-page 258

 2005-2012 Microchip Technology Inc.


型号：	GRM31CR61C106KC31L
厂家：	MICROCHIP
描述：	64/80/100-Pin, General Purpose, 16-Bit Flash Microcontrollers 八十〇分之六十四/ 100-引脚，通用16位闪存微控制器闪存微控制器电容器 PC
文件：	总258页 (文件大小：2294K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

GRM31CR61C106KC31L [MICROCHIP]

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