DSPIC33FJ256MC510 [MICROCHIP]
Flash Programming Specification; 闪存编程规范
| 型号： | DSPIC33FJ256MC510 |
| 厂家： | 
MICROCHIP |
| 描述： | Flash Programming Specification |
| 文件： | 总80页 (文件大小：943K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
dsPIC33F/PIC24H
dsPIC33F/PIC24H Flash Programming Specification
• PIC24HJ128GP306
1.0
DEVICE OVERVIEW
• PIC24HJ128GP310
This document defines the programming specification
for the dsPIC33F 16-bit Digital Signal Controller (DSC)
and PIC24H 16-bit Microcontroller (MCU) families. This
programming specification is required only for those
developing programming support for the dsPIC33F/
PIC24H family. Customers only using one of these
devices should use development tools that already
provide support for device programming.
• PIC24HJ128GP506
• PIC24HJ128GP510
• PIC24HJ256GP206
• PIC24HJ256GP210
• PIC24HJ256GP610
• dsPIC33FJ12GP201
• dsPIC33FJ12GP202
• dsPIC33FJ12MC201
• dsPIC33FJ12MC202
• PIC24HJ12GP201
• PIC24HJ12GP202
This document includes programming specifications
for the following devices:
• dsPIC33FJ64GP206
• dsPIC33FJ64GP306
• dsPIC33FJ64GP310
• dsPIC33FJ64GP706
• dsPIC33FJ64GP708
• dsPIC33FJ64GP710
• dsPIC33FJ128GP206
• dsPIC33FJ128GP306
• dsPIC33FJ128GP310
• dsPIC33FJ128GP706
• dsPIC33FJ128GP708
• dsPIC33FJ128GP710
• dsPIC33FJ256GP506
• dsPIC33FJ256GP510
• dsPIC33FJ256GP710
• dsPIC33FJ64MC506
• dsPIC33FJ64MC508
• dsPIC33FJ64MC510
• dsPIC33FJ64MC706
• dsPIC33FJ64MC710
• dsPIC33FJ128MC506
• dsPIC33FJ128MC510
• dsPIC33FJ128MC706
• dsPIC33FJ128MC708
• dsPIC33FJ128MC710
• dsPIC33FJ256MC510
• dsPIC33FJ256MC710
• PIC24HJ64GP206
2.0
PROGRAMMING OVERVIEW
OF THE dsPIC33F/PIC24H
There are two methods of programming the dsPIC33F/
PIC24H family of devices discussed in this
programming specification. They are:
• In-Circuit Serial Programming™ (ICSP™)
programming capability
• Enhanced In-Circuit Serial Programming
The ICSP programming method is the most direct
method to program the device; however, it is also the
slower of the two methods. It provides native, low-level
programming capability to erase, program and verify
the chip.
The Enhanced ICSP protocol uses a faster method that
takes advantage of the programming executive, as
illustrated in Figure 2-1. The programming executive
provides all the necessary functionality to erase, pro-
gram and verify the chip through a small command set.
The command set allows the programmer to program
the dsPIC33F/PIC24H Programming Specification
devices without having to deal with the low-level
programming protocols of the chip.
• PIC24HJ64GP210
• PIC24HJ64GP506
• PIC24HJ64GP510
• PIC24HJ128GP206
• PIC24HJ128GP210
© 2007 Microchip Technology Inc.
Preliminary
DS70152D-page 1
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
FIGURE 2-1:
PROGRAMMING SYSTEM
OVERVIEW FOR
FIGURE 2-2:
CONNECTIONS FOR THE
ON-CHIP REGULATOR
ENHANCED ICSP™
3.3V
dsPIC33F/PIC24H
dsPIC33F/PIC24H
Programming
Executive
Programmer
VDD
VDDCORE
VSS
CF
On-Chip Memory
Note 1: These are typical operating voltages. Refer
to Section TABLE 8-1: “AC/DC Charac-
teristics and Timing Requirements” for
the full operating ranges of VDD and
This specification is divided into major sections that
describe the programming methods independently.
Section 3.0 “Device Programming
– Enhanced
ICSP” describes the Enhanced ICSP method.
Section 5.0 “Device Programming – ICSP” describes
the ICSP method.
2.2
Program Memory Write/Erase
Requirements
2.1
Power Requirements
The program Flash memory on the dsPIC33F/PIC24H
has a specific write/erase requirement that must be
adhered to for proper device operation. The rule is that
any given word in memory must not be written without
first erasing the page in which it is located. Thus, the
easiest way to conform to this rule is to write all the data
in a programming block within one write cycle. The pro-
gramming methods specified in this document comply
with this requirement.
All devices in the dsPIC33F/PIC24H family are dual volt-
age supply designs: one supply for the core and another
for the peripherals and I/O pins. A regulator is provided
on-chip to alleviate the need for two external voltage
supplies.
All of the dsPIC33F/PIC24H devices power their core
digital logic at a nominal 2.5V. To simplify system
design, all devices in the dsPIC33F/PIC24H Program-
ming Specification family incorporate an on-chip regu-
lator that allows the device to run its core logic from
VDD.
Note:
A program memory word can be pro-
grammed twice before an erase, but only
if (a) the same data is used in both pro-
gram operations or (b) bits containing ‘1’
are set to ‘0’ but no ‘0’ is set to ‘1’.
The regulator provides power to the core from the other
VDD pins. A low-ESR capacitor (such as tantalum) must
be connected to the VDDCORE pin (Figure 2-2). This
helps to maintain the stability of the regulator. The
specifications for core voltage and capacitance are
listed in Section TABLE 8-1: “AC/DC Characteristics
and Timing Requirements”.
DS70152D-page 2
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
2.3
Pin Diagrams
The pin diagrams for the dsPIC33F/PIC24H device
family are shown in the following figures. The pins that
are required for programming are listed in Table 2-1.
The MCLR, PGC1, PGD1, PGC2, PGD2, PGC3 and
PGD3 pins are shown in bold letters in the figures.
Refer to the appropriate device data sheet for complete
pin descriptions.
TABLE 2-1:
Pin Name
PIN DESCRIPTIONS (PINS USED DURING PROGRAMMING)
During Programming
Pin Description
Pin Name
Pin Type
MCLR
MCLR
VDD
P
P
Programming Enable
(1)
VDD and AVDD
Power Supply
(1)
VSS and AVSS
VDDCORE
PGC1
VSS
P
Ground
VDDCORE
PGC1
PGD1
PGC2
PGD2
PGC3
PGD3
P
Regulated Power Supply for Core
Primary Programming Pin Pair: Serial Clock
Primary Programming Pin Pair: Serial Data
Secondary Programming Pin Pair: Serial Clock
Secondary Programming Pin Pair: Serial Data
Tertiary Programming Pin Pair: Serial Clock
Tertiary Programming Pin Pair: Serial Data
I
PGD1
I/O
I
PGC2
PGD2
I/O
I
PGC3
PGD3
I/O
Legend: I = Input, O = Output, P = Power
Note 1: All power supply and ground pins must be connected, including analog supplies (AVDD) and ground
(AVSS).
© 2007 Microchip Technology Inc.
Preliminary
DS70152D-page 3
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
Pin Diagrams
64-Pin TQFP
COFS/RG15
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
SCK2/CN8/RG6
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14
PGD2/EMUD2/SOSCI/T4CK/CN1/RC13
OC1/RD0
2
3
4
IC4/INT4/RD11
SDI2/CN9/RG7
5
IC3/INT3/RD10
SDO2/CN10/RG8
6
IC2/U1CTS/INT2/RD9
IC1/INT1/RD8
MCLR
7
SS2/T5CK/CN11/RG9
VSS
8
VSS
dsPIC33FJ64GP206
dsPIC33FJ128GP206
9
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
VDD
10
11
12
13
14
15
16
AN5/IC8/CN7/RB5
AN4/IC7/CN6/RB4
AN3/CN5/RB3
SCL1/RG2
SDA1/RG3
AN2/SS1/LVDIN/CN4/RB2
PGC3/EMUC3/AN1/VREF-/CN3/RB1
PGD3/EMUD3/AN0/VREF+/CN2/RB0
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
DS70152D-page 4
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
Pin Diagrams (Continued)
64-Pin TQFP
COFS/RG15
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
SCK2/CN8/RG6
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14
PGD2/EMUD2/SOSCI/T4CK/CN1/RC13
OC1/RD0
2
3
4
IC4/INT4/RD11
SDI2/CN9/RG7
5
IC3/INT3/RD10
SDO2/CN10/RG8
6
IC2/U1CTS/INT2/RD9
IC1/INT1/RD8
MCLR
7
SS2/T5CK/CN11/RG9
VSS
8
VSS
dsPIC33FJ64GP306
dsPIC33FJ128GP306
9
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
VDD
10
11
12
13
14
15
16
AN5/IC8/CN7/RB5
AN4/IC7/CN6/RB4
AN3/CN5/RB3
SCL1/RG2
SDA1/RG3
AN2/SS1/LVDIN/CN4/RB2
PGC3/EMUC3/AN1/VREF-/CN3/RB1
PGD3/EMUD3/AN0/VREF+/CN2/RB0
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
© 2007 Microchip Technology Inc.
Preliminary
DS70152D-page 5
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
Pin Diagrams (Continued)
64-Pin TQFP
COFS/RG15
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
SCK2/CN8/RG6
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14
PGD2/EMUD2/SOSCI/T4CK/CN1/RC13
OC1/RD0
2
3
4
IC4/INT4/RD11
SDI2/CN9/RG7
5
IC3/INT3/RD10
SDO2/CN10/RG8
6
IC2/U1CTS/INT2/RD9
IC1/INT1/RD8
MCLR
7
SS2/T5CK/CN11/RG9
VSS
8
VSS
dsPIC33FJ256GP506
9
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
VDD
10
11
12
13
14
15
16
AN5/IC8/CN7/RB5
AN4/IC7/CN6/RB4
AN3/CN5/RB3
SCL1/RG2
SDA1/RG3
AN2/SS1/LVDIN/CN4/RB2
PGC3/EMUC3/AN1/VREF-/CN3/RB1
PGD3/EMUD3/AN0/VREF+/CN2/RB0
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
DS70152D-page 6
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
Pin Diagrams (Continued)
64-Pin TQFP
COFS/RG15
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
SCK2/CN8/RG6
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14
PGD2/EMUD2/SOSCI/T4CK/CN1/RC13
OC1/RD0
2
3
4
IC4/INT4/RD11
SDI2/CN9/RG7
5
IC3/INT3/RD10
SDO2/CN10/RG8
6
IC2/U1CTS/INT2/RD9
IC1/INT1/RD8
MCLR
7
dsPIC33FJ64GP706
dsPIC33FJ128GP706
SS2/T5CK/CN11/RG9
VSS
8
VSS
9
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
VDD
10
11
12
13
14
15
16
AN5/IC8/CN7/RB5
AN4/IC7/CN6/RB4
AN3/CN5/RB3
SCL1/RG2
SDA1/RG3
AN2/SS1/LVDIN/CN4/RB2
PGC3/EMUC3/AN1/VREF-/CN3/RB1
PGD3/EMUD3/AN0/VREF+/CN2/RB0
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
© 2007 Microchip Technology Inc.
Preliminary
DS70152D-page 7
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
Pin Diagrams (Continued)
80-Pin TQFP
PGC2/EMUC2/SOSCO/T1CK/
CN0/RC14
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
COFS/RG15
PGD2/EMUD2/SOSCI/CN1/RC13
AN16/T2CK/T7CK/RC1
2
3
OC1/RD0
AN17/T3CK/T6CK/RC2
AN18/T4CK/T9CK/RC3
AN19/T5CK/T8CK/RC4
SCK2/CN8/RG6
IC4/RD11
4
IC3/RD10
5
IC2/RD9
6
IC1/RD8
SDI2/CN9/RG7
7
SDA2/INT4/RA3
SCL2/INT3/RA2
VSS
SDO2/CN10/RG8
MCLR
8
9
SS2/CN11/RG9
VSS
10
11
12
dsPIC33FJ64GP708
dsPIC33FJ128GP708
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
VDD
TMS/AN20/INT1/RA12
TDO/AN21/INT2/RA13
AN5/CN7/RB5
AN4/CN6/RB4
AN3/CN5/RB3
13
14
15
16
17
18
19
20
SCL1/RG2
SDA1/RG3
SCK1/INT0/RF6
SDI1/RF7
SDO1/RF8
U1RX/RF2
U1TX/RF3
AN2/SS1/LVDIN/CN4/RB2
PGC3/EMUC3/AN1/CN3/RB1
PGD3/EMUD3/AN0/CN2/RB0
DS70152D-page 8
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
Pin Diagrams (Continued)
100-Pin TQFP
V
SS
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
COFS/RG15
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14
VDD
2
3
PGD2/EMUD2/SOSCI/CN1/RC13
AN29/RE5
AN30/RE6
OC1/RD0
IC4/RD11
IC3/RD10
IC2/RD9
4
AN31/RE7
5
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
AN18/T4CK/T9CK/RC3
AN19/T5CK/T8CK/RC4
6
7
IC1/RD8
8
INT4/RA15
9
INT3/RA14
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
10
11
12
V
SS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
13
14
15
16
17
18
19
20
21
22
23
24
25
dsPIC33FJ64GP310
dsPIC33FJ128GP310
VDD
SS2/CN11/RG9
TDO/RA5
VSS
TDI/RA4
VDD
TMS/RA0
SDA2/RA3
SCL2/RA2
SCL1/RG2
SDA1/RG3
SCK1/INT0/RF6
SDI1/RF7
AN20/INT1/RA12
AN21/INT2/RA13
AN5/CN7/RB5
AN4/CN6/RB4
AN3/CN5/RB3
AN2/SS1/LVDIN/CN4/RB2
PGC3/EMUC3/AN1/CN3/RB1
PGD3/EMUD3/AN0/CN2/RB0
SDO1/RF8
U1RX/RF2
U1TX/RF3
© 2007 Microchip Technology Inc.
Preliminary
DS70152D-page 9
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
Pin Diagrams (Continued)
100-Pin TQFP
V
SS
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
COFS/RG15
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14
VDD
2
3
PGD2/EMUD2/SOSCI/CN1/RC13
AN29/RE5
AN30/RE6
OC1/RD0
IC4/RD11
IC3/RD10
IC2/RD9
4
AN31/RE7
5
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
AN18/T4CK/T9CK/RC3
AN19/T5CK/T8CK/RC4
6
7
IC1/RD8
8
INT4/RA15
9
INT3/RA14
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
10
11
12
V
SS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
13
14
15
16
17
18
19
20
21
22
23
24
25
dsPIC33FJ256GP510
VDD
SS2/CN11/RG9
TDO/RA5
VSS
VDD
TDI/RA4
TMS/RA0
SDA2/RA3
SCL2/RA2
SCL1/RG2
SDA1/RG3
SCK1/INT0/RF6
SDI1/RF7
AN20/INT1/RA12
AN21/INT2/RA13
AN5/CN7/RB5
AN4/CN6/RB4
AN3/CN5/RB3
AN2/SS1/LVDIN/CN4/RB2
PGC3/EMUC3/AN1/CN3/RB1
PGD3/EMUD3/AN0/CN2/RB0
SDO1/RF8
U1RX/RF2
U1TX/RF3
DS70152D-page 10
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
Pin Diagrams (Continued)
100-Pin TQFP
V
SS
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
COFS/RG15
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14
VDD
2
3
PGD2/EMUD2/SOSCI/CN1/RC13
AN29/RE5
AN30/RE6
OC1/RD0
IC4/RD11
IC3/RD10
IC2/RD9
4
AN31/RE7
5
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
AN18/T4CK/T9CK/RC3
AN19/T5CK/T8CK/RC4
6
7
IC1/RD8
8
INT4/RA15
9
INT3/RA14
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
10
11
12
V
SS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
13
14
15
16
17
18
19
20
21
22
23
24
25
dsPIC33FJ64GP710
dsPIC33FJ128GP710
dsPIC33FJ256GP710
VDD
SS2/CN11/RG9
TDO/RA5
VSS
VDD
TDI/RA4
TMS/RA0
SDA2/RA3
SCL2/RA2
SCL1/RG2
SDA1/RG3
SCK1/INT0/RF6
AN20/INT1/RA12
AN21/INT2/RA13
AN5/CN7/RB5
AN4/CN6/RB4
AN3/CN5/RB3
SDI1/RF7
SDO1/RF8
U1RX/RF2
U1TX/RF3
AN2/SS1/LVDIN/CN4/RB2
PGC3/EMUC3/AN1/CN3/RB1
PGD3/EMUD3/AN0/CN2/RB0
© 2007 Microchip Technology Inc.
Preliminary
DS70152D-page 11
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
Pin Diagrams (Continued)
64-Pin TQFP
PWM3H/RE5
PWM4L/RE6
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14
PGD2/EMUD2/SOSCI/T4CK/CN1/RC13
OC1/RD0
2
PWM4H/RE7
3
SCK2/CN8/RG6
4
IC4/INT4/RD11
SDI2/CN9/RG7
5
IC3/INT3/RD10
SDO2/CN10/RG8
6
IC2/U1CTS/FLTB/INT2/RD9
IC1/FLTA/INT1/RD8
VSS
MCLR
7
SS2/T5CK/CN11/RG9
VSS
8
dsPIC33FJ64MC506
9
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
VDD
10
11
12
13
14
15
16
AN5/QEB/IC8/CN7/RB5
AN4/QEA/IC7/CN6/RB4
AN3/INDX/CN5/RB3
AN2/SS1/LVDIN/CN4/RB2
PGC3/EMUC3/AN1/VREF-/CN3/RB1
PGD3/EMUD3/AN0/VREF+/CN2/RB0
SCL1/RG2
SDA1/RG3
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
DS70152D-page 12
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
Pin Diagrams (Continued)
64-Pin TQFP
PWM3H/RE5
PWM4L/RE6
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14
PGD2/EMUD2/SOSCI/T4CK/CN1/RC13
OC1/RD0
2
PWM4H/RE7
3
SCK2/CN8/RG6
4
IC4/INT4/RD11
SDI2/CN9/RG7
5
IC3/INT3/RD10
SDO2/CN10/RG8
6
IC2/U1CTS/FLTB/INT2/RD9
IC1/FLTA/INT1/RD8
VSS
MCLR
7
SS2/T5CK/CN11/RG9
VSS
8
dsPIC33FJ128MC506
dsPIC33FJ64MC506
dsPIC33FJ128MC706
9
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
VDD
10
11
12
13
14
15
16
AN5/QEB/IC8/CN7/RB5
AN4/QEA/IC7/CN6/RB4
AN3/INDX/CN5/RB3
AN2/SS1/LVDIN/CN4/RB2
PGC3/EMUC3/AN1/VREF-/CN3/RB1
PGD3/EMUD3/AN0/VREF+/CN2/RB0
SCL1/RG2
SDA1/RG3
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
© 2007 Microchip Technology Inc.
Preliminary
DS70152D-page 13
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
Pin Diagrams (Continued)
80-Pin TQFP
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
PWM3H/RE5
PWM4L/RE6
PGD2/EMUD2/SOSCI/CN1/RC13
2
3
OC1/RD0
IC4/RD11
IC3/RD10
IC2/RD9
IC1/RD8
INT4/RA3
INT3/RA2
VSS
PWM4H/RE7
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
SCK2/CN8/RG6
4
5
6
SDI2/CN9/RG7
7
SDO2/CN10/RG8
MCLR
8
9
SS2/CN11/RG9
VSS
10
11
12
dsPIC33FJ64MC508
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
TMS/FLTA/INT1/RE8
TDO/FLTB/INT2/RE9
AN5/QEB/CN7/RB5
AN4/QEA/CN6/RB4
AN3/INDX/CN5/RB3
VDD
13
14
15
16
17
18
19
20
SCL1/RG2
SDA1/RG3
SCK1/INT0/RF6
SDI1/RF7
SDO1/RF8
U1RX/RF2
U1TX/RF3
AN2/SS1/LVDIN/CN4/RB2
PGC3/EMUC3/AN1/CN3/RB1
PGD3/EMUD3/AN0/CN2/RB0
DS70152D-page 14
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
Pin Diagrams (Continued)
80-Pin TQFP
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14
PGD2/EMUD2/SOSCI/CN1/RC13
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
PWM3H/RE5
PWM4L/RE6
2
3
OC1/RD0
IC4/RD11
IC3/RD10
IC2/RD9
PWM4H/RE7
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
SCK2/CN8/RG6
4
5
6
IC1/RD8
SDI2/CN9/RG7
7
SDA2/INT4/RA3
SCL2/INT3/RA2
VSS
SDO2/CN10/RG8
MCLR
8
9
SS2/CN11/RG9
VSS
10
11
12
dsPIC33FJ128MC708
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
VDD
TMS/FLTA/INT1/RE8
TDO/FLTB/INT2/RE9
AN5/QEB/CN7/RB5
AN4/QEA/CN6/RB4
AN3/INDX/CN5/RB3
13
14
15
16
17
18
19
20
SCL1/RG2
SDA1/RG3
SCK1/INT0/RF6
SDI1/RF7
AN2/SS1/LVDIN/CN4/RB2
PGC3/EMUC3/AN1/CN3/RB1
PGD3/EMUD3/AN0/CN2/RB0
SDO1/RF8
U1RX/RF2
U1TX/RF3
© 2007 Microchip Technology Inc.
Preliminary
DS70152D-page 15
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
Pin Diagrams (Continued)
100-Pin TQFP
V
SS
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
COFS/RG15
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14
VDD
2
3
PGD2/EMUD2/SOSCI/CN1/RC13
PWM3H/RE5
PWM4L/RE6
OC1/RD0
IC4/RD11
IC3/RD10
IC2/RD9
4
PWM4H/RE7
5
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
AN18/T4CK/T9CK/RC3
AN19/T5CK/T8CK/RC4
6
7
IC1/RD8
8
INT4/RA15
9
INT3/RA14
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
10
11
12
V
SS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
13
14
15
16
17
18
19
20
21
22
23
24
25
dsPIC33FJ64MC510
VDD
SS2/CN11/RG9
TDO/RA5
VSS
VDD
TDI/RA4
RA3
TMS/RA0
RA2
AN20/FLTA/INT1/RE8
AN21/FLTB/INT2/RE9
SCL1/RG2
SDA1/RG3
SCK1/INT0/RF6
SDI1/RF7
AN5/QEB/CN7/RB5
AN4/QEA/CN6/RB4
AN3/INDX/CN5/RB3
AN2/SS1/LVDIN/CN4/RB2
PGC3/EMUC3/AN1/CN3/RB1
PGD3/EMUD3/AN0/CN2/RB0
SDO1/RF8
U1RX/RF2
U1TX/RF3
DS70152D-page 16
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
Pin Diagrams (Continued)
100-Pin TQFP
V
SS
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
COFS/RG15
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14
VDD
2
3
PGD2/EMUD2/SOSCI/CN1/RC13
PWM3H/RE5
PWM4L/RE6
OC1/RD0
IC4/RD11
IC3/RD10
IC2/RD9
4
PWM4H/RE7
5
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
AN18/T4CK/T9CK/RC3
AN19/T5CK/T8CK/RC4
6
7
IC1/RD8
8
INT4/RA15
9
INT3/RA14
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
10
11
12
V
SS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
13
14
15
16
17
18
19
20
21
22
23
24
25
dsPIC33FJ128MC510
dsPIC33FJ256MC510
VDD
SS2/CN11/RG9
TDO/RA5
VSS
VDD
TDI/RA4
TMS/RA0
SDA2/RA3
SCL2/RA2
AN20/FLTA/INT1/RE8
AN21/FLTB/INT2/RE9
SCL1/RG2
SDA1/RG3
SCK1/INT0/RF6
SDI1/RF7
AN5/QEB/CN7/RB5
AN4/QEA/CN6/RB4
AN3/INDX/CN5/RB3
AN2/SS1/LVDIN/CN4/RB2
PGC3/EMUC3/AN1/CN3/RB1
PGD3/EMUD3/AN0/CN2/RB0
SDO1/RF8
U1RX/RF2
U1TX/RF3
© 2007 Microchip Technology Inc.
Preliminary
DS70152D-page 17
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
Pin Diagrams (Continued)
100-Pin TQFP
V
SS
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
COFS/RG15
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14
VDD
2
3
PGD2/EMUD2/SOSCI/CN1/RC13
PWM3H/RE5
PWM4L/RE6
OC1/RD0
IC4/RD11
IC3/RD10
IC2/RD9
4
PWM4H/RE7
5
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
AN18/T4CK/T9CK/RC3
AN19/T5CK/T8CK/RC4
6
7
IC1/RD8
8
INT4/RA15
9
INT3/RA14
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
10
11
12
V
SS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
dsPIC33FJ64MC710
dsPIC33FJ128MC710
dsPIC33FJ256MC710
13
14
15
16
17
18
19
20
21
22
23
24
25
VDD
SS2/CN11/RG9
TDO/RA5
VSS
VDD
TDI/RA4
TMS/RA0
SDA2/RA3
SCL2/RA2
AN20/FLTA/INT1/RE8
AN21/FLTB/INT2/RE9
SCL1/RG2
SDA1/RG3
SCK1/INT0/RF6
SDI1/RF7
AN5/QEB/CN7/RB5
AN4/QEA/CN6/RB4
AN3/INDX/CN5/RB3
AN2/SS1/LVDIN/CN4/RB2
PGC3/EMUC3/AN1/CN3/RB1
PGD3/EMUD3/AN0/CN2/RB0
SDO1/RF8
U1RX/RF2
U1TX/RF3
DS70152D-page 18
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
Pin Diagrams (Continued)
64-Pin TQFP
RG15
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
SCK2/CN8/RG6
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14
PGD2/EMUD2/SOSCI/T4CK/CN1/RC13
OC1/RD0
2
3
4
IC4/INT4/RD11
SDI2/CN9/RG7
5
IC3/INT3/RD10
SDO2/CN10/RG8
MCLR
6
IC2/U1CTS/INT2/RD9
IC1/INT1/RD8
7
SS2/T5CK/CN11/RG9
VSS
8
VSS
PIC24HJ64GP206
PIC24HJ128GP206
PIC24HJ256GP206
9
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
VDD
10
11
12
13
14
15
16
AN5/IC8/CN7/RB5
AN4/IC7/CN6/RB4
AN3/CN5/RB3
SCL1/RG2
SDA1/RG3
AN2/SS1/CN4/RB2
PGC3/EMUC3/AN1/VREF-/CN3/RB1
PGD3/EMUD3/AN0/VREF+/CN2/RB0
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
Note:
The PIC24HJ64GP206 device does not have the SCL2 and SDA2 pins.
© 2007 Microchip Technology Inc.
Preliminary
DS70152D-page 19
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
Pin Diagrams (Continued)
64-Pin TQFP
RG15
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
SCK2/CN8/RG6
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14
PGD2/EMUD2/SOSCI/T4CK/CN1/RC13
OC1/RD0
2
3
4
IC4/INT4/RD11
SDI2/CN9/RG7
5
IC3/INT3/RD10
SDO2/CN10/RG8
MCLR
6
IC2/U1CTS/INT2/RD9
IC1/INT1/RD8
7
PIC24HJ128GP306
SS2/T5CK/CN11/RG9
VSS
8
VSS
9
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
VDD
10
11
12
13
14
15
16
AN5/IC8/CN7/RB5
AN4/IC7/CN6/RB4
AN3/CN5/RB3
SCL1/RG2
SDA1/RG3
AN2/SS1/CN4/RB2
PGC3/EMUC3/AN1/VREF-/CN3/RB1
PGD3/EMUD3/AN0/VREF+/CN2/RB0
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
DS70152D-page 20
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
Pin Diagrams (Continued)
64-Pin TQFP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14
PGD2/EMUD2/SOSCI/T4CK/CN1/RC13
OC1/RD0
COFS/RG15
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
SCK2/CN8/RG6
1
2
3
4
IC4/INT4/RD11
SDI2/CN9/RG7
5
IC3/INT3/RD10
SDO2/CN10/RG8
MCLR
6
IC2/U1CTS/INT2/RD9
IC1/INT1/RD8
7
SS2/T5CK/CN11/RG9
VSS
8
VSS
PIC24HJ64GP506
PIC24HJ128GP506
9
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
VDD
10
11
12
13
14
15
16
AN5/IC8/CN7/RB5
AN4/IC7/CN6/RB4
AN3/CN5/RB3
SCL1/RG2
SDA1/RG3
AN2/SS1/CN4/RB2
PGC3/EMUC3/AN1/VREF-/CN3/RB1
PGD3/EMUD3/AN0/VREF+/CN2/RB0
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
© 2007 Microchip Technology Inc.
Preliminary
DS70152D-page 21
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
Pin Diagrams (Continued)
100-Pin TQFP
V
SS
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
RG15
1
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14
VDD
2
PGD2/EMUD2/SOSCI/CN1/RC13
OC1/RD0
AN29/RE5
AN30/RE6
3
4
IC4/RD11
AN31/RE7
5
IC3/RD10
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
AN18/T4CK/T9CK/RC3
AN19/T5CK/T8CK/RC4
SCK2/CN8/RG6
SDI2/CN9/RG7
6
IC2/RD9
7
IC1/RD8
8
INT4/RA15
9
INT3/RA14
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VSS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
SDO2/CN10/RG8
MCLR
PIC24HJ64GP210
PIC24HJ128GP210
PIC24HJ128GP310
PIC24HJ256GP210
SS2/CN11/RG9
VDD
VSS
TDO/RA5
VDD
TDI/RA4
TMS/RA0
AN20/INT1/RA12
SDA2/RA3
SCL2/RA2
SCL1/RG2
SDA1/RG3
SCK1/INT0/RF6
SDI1/RF7
AN21/INT2/RA13
AN5/CN7/RB5
AN4/CN6/RB4
AN3/CN5/RB3
AN2/SS1/CN4/RB2
PGC3/EMUC3/AN1/CN3/RB1
PGD3/EMUD3/AN0/CN2/RB0
SDO1/RF8
U1RX/RF2
U1TX/RF3
DS70152D-page 22
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
Pin Diagrams (Continued)
100-Pin TQFP
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
V
SS
1
RG15
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14
VDD
2
PGD2/EMUD2/SOSCI/CN1/RC13
OC1/RD0
3
AN29/RE5
AN30/RE6
4
IC4/RD11
AN31/RE7
5
IC3/RD10
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
AN18/T4CK/T9CK/RC3
AN19/T5CK/T8CK/RC4
6
IC2/RD9
7
IC1/RD8
8
INT4/RA15
9
INT3/RA14
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
VSS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
PIC24HJ64GP510
PIC24HJ128GP510
SS2/CN11/RG9
VDD
VSS
TDO/RA5
VDD
TDI/RA4
TMS/RA0
AN20/INT1/RA12
SDA2/RA3
SCL2/RA2
SCL1/RG2
SDA1/RG3
SCK1/INT0/RF6
SDI1/RF7
AN21/INT2/RA13
AN5/CN7/RB5
AN4/CN6/RB4
AN3/CN5/RB3
AN2/SS1/CN4/RB2
PGC3/EMUC3/AN1/CN3/RB1
PGD3/EMUD3/AN0/CN2/RB0
SDO1/RF8
U1RX/RF2
U1TX/RF3
© 2007 Microchip Technology Inc.
Preliminary
DS70152D-page 23
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
Pin Diagrams (Continued)
100-Pin TQFP
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VSS
1
RG15
PGC2/EMUC2/SOSCO/T1CK/CN0/RC14
VDD
2
PGD2/EMUD2/SOSCI/CN1/RC13
AN29/RE5
AN30/RE6
3
OC1/RD0
IC4/RD11
IC3/RD10
IC2/RD9
4
AN31/RE7
5
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
AN18/T4CK/T9CK/RC3
AN19/T5CK/T8CK/RC4
SCK2/CN8/RG6
6
7
IC1/RD8
8
INT4/RA15
9
INT3/RA14
10
11
12
VSS
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
PIC24HJ256GP610
13
14
15
16
17
18
19
20
21
22
23
24
25
SS2/CN11/RG9
VDD
VSS
TDO/RA5
VDD
TDI/RA4
TMS/RA0
AN20/INT1/RA12
SDA2/RA3
SCL2/RA2
SCL1/RG2
SDA1/RG3
SCK1/INT0/RF6
SDI1/RF7
AN21/INT2/RA13
AN5/CN7/RB5
AN4/CN6/RB4
AN3/CN5/RB3
AN2/SS1/CN4/RB2
PGC3/EMUC3/AN1/CN3/RB1
PGD3/EMUD3/AN0/CN2/RB0
SDO1/RF8
U1RX/RF2
U1TX/RF3
DS70152D-page 24
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
Pin Diagrams (Continued)
18-PIN SDIP
18-PIN SOIC
DD
V
MCLR
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
PGD2/EMUD2/AN0/VREF+/CN2/RA0
SS
V
AN6/RP15/CN11/RB15
AN7/RP14/CN12/RB14
PGC2/EMUC2/AN1/VREF-/CN3/RA1
PGD1/EMUD1/AN2/RP0/CN4/RB0
PGC1/EMUC1/AN3/RP1/CN5/RB1
OSCI/CLKI/CN30/RA2
V
DDCORE
SS
V
SCL1/RP9/CN21/RB9
OSCO/CLKO/CN29/RA3
PGD3/EMUD3/SOSCI/RP4/CN1/RB4
PGC3/EMUC3/SOSCO/T1CK/CN0/RA4
SDA1/RP8/CN22/RB8
INT0/RP7/CN23/RB7
© 2007 Microchip Technology Inc.
Preliminary
DS70152D-page 25
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
Pin Diagrams (Continued)
20-PIN SDIP
20-PIN SSOP
DD
V
MCLR
PGD2/EMUD2/AN0/VREF+/CN2/RA0
PGC2/EMC2/AN1/VREF-/CN3/RA1
PGD1/EMUD1/AN2/RP0/CN4/RB0
PGC1/EMUC1/AN3/RP1/CN5/RB1
20
19
18
17
16
15
14
13
12
11
1
2
PWM1L1/RP15/CN11/RB15
PWM1H1/RP14/CN12/RB14
PWM1L2/RP13/CN13/RB13
PWM1H2/RP12/CN14/RB12
3
4
5
VSS
6
V
DDCORE
OSCI/CLKI/CN30/RA2
OSCO/CLKO/CN29/RA3
7
PWM2L1/SDA1/RP9/CN21/RB9
PWM2H1/SCL1/RP8/CN22/RB8
INT0/RP7/CN23/RB7
8
PGD3/EMUD3/SOSCI/RP4/CN1/RB4
PGC3/EMUC3/SOSCO/T1CK/CN0/RA4
9
10
Pin Diagrams (Continued)
28-PIN SDIP
28-PIN SOIC
MCLR
1
28
PGD2/EMUD2/AN0/VREF+/CN2/RA0
2
27
26
25
24
23
22
21
20
19
18
17
16
15
AN6/RP15/CN11/RB15
AN7/RP14/CN12/RB14
AN8/RP13/CN13/RB13
AN9/RP12/CN14/RB12
TMS/RP11/CN15/RB11
TDI/RP10/CN16/RB10
PGC2/EMUC2/AN1/VREF-/CN3/RA1
PGD1/EMUD1/AN2/RP0/CN4/RB0
3
4
PGC1/EMUC1/AN3/RP1/CN5/RB1
AN4/RP2/CN6/RB2
5
6
AN5/RP3/CN7/RB3
7
8
OSCO/CLK1/CN30/RA2
OSCI/CLKI/CN29/RA3
9
10
11
12
13
14
PGD3/EMUD3/SOSC/RP4/CN1/RB4
TDO/SDA1/RP9/CN21/RB9
TCK/SCL1/RP8/CN22/RB8
PGC3/EMUC3/SOSCO/T1CK/CN0/RA4
INT0/RP7/CN23/RB7
ASDA1/RP5/CN27/RB5
ASCL1/RP6/CN24/RB6
DS70152D-page 26
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
Pin Diagrams (Continued)
28-PIN SDIP
28-PIN SOIC
MCLR
PGD2/EMUD2/AN0/VREF+/CN2/RA0
PGC2/EMUC2/AN1/VREF-/CN3/RA1
PGD1/EMUD1/AN2/RP0/CN4/RB0
PGC1/EMUC1/AN3/RP1/CN5/RB1
AN4/RP2/CN6/RB2
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AV
DD
AV
2
PWM1L1/RP15/CN11/RB15
PWM1H1/RP14/CN12/RB14
PWM1L2/RP13/CN13/RB13
PWM1H2/RP12/CN14/RB12
TMS/PWM1L3/RP11/CN15/RB11
TDI/PWM1H3/RP10/CN16/RB10
DDCORE
3
4
5
6
AN5/RP3/CN7/RB3
7
8
OSCI/CLKI/CN30/RA2
9
Vss
10
11
12
13
14
OSCO/CLKO/CN29/RA3
PGD3/EMUD3/SOSCI/RP4/CN1/RB4
PGC3/EMUC3/SOSCO/T1CK/CN0/RA4
TDO/PWM2L1/SDA1/RP9/CN21/RB9
TCK/PWM2H1/SCL1/RP8/CN22/RB8
INT0/RP7/CN23/RB7
V
DD
ASCL1/RP6/CN24/RB6
ASDA1/RP5/CN27/RB5
© 2007 Microchip Technology Inc.
Preliminary
DS70152D-page 27
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
Pin Diagrams (Continued)
28-Pin QFN 6*6mm
28 27
26
25 24
23
22
PGD1/EMUD1/AN2/RP0/CN4/RB0
PGC1/EMUC1/AN3/RP1/CN5/RB1
1
2
3
4
5
6
7
AN8/RP13/CN13/RB13
AN9/RP12/CN14/RB12
21
20
19
18
17
16
15
AN4/RP2/CN6/RB2
AN5/RP3/CN7/RB3
TMS/RP11/CN15/RB11
TDI/RP10/CN16/RB10
dsPIC33FJ12GP202
PIC24HJ12GP202
V
SS
V
DDCORE
SS
OSCI/CLKI/CN30/RA2
OSCO/CLKO/CN29/RA3
V
TDO/SDA1/RP9/CN21/RB9
8
9
10
11
12
13
14
DS70152D-page 28
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
Pin Diagrams (Continued)
28-Pin QFN 6*6mm
28 27
26
25 24
23
22
PGD1
/
EMUD1/AN2/RP0/CN4/RB0
EMUC1/AN3/RP1/CN5/RB1
AN4/RP2/CN6/RB2
PWM1L2/RP13/CN13/RB13
PWM1H2/RP12/CN14/RB12
1
2
3
4
5
6
7
21
20
19
18
17
16
15
PGC1
/
TMS/PWM1L3/RP11/CN15/RB11
TDI/PWM1H3/RP10/CN16/RB10
dsPIC33FJ12MC202
AN5/RP3/CN7/RB3
V
SS
V
DDCORE
OSCI/CLKI/CN30/RA2
VSS
TDO/PWM2L1/SDA1/RP9/CN21/RB9
OSCO/CLKO/CN29/RA3
8
9
10
11
12
13
14
© 2007 Microchip Technology Inc.
Preliminary
DS70152D-page 29
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
gramming and the debug executive is used for in-circuit
debugging. This region of memory can not be used to
store user code.
2.4
Memory Map
The program memory map extends from 0x0 to
0xFFFFFE. Code storage is located at the base of the
memory map and supports up to 88K instructions
(about 256 Kbytes). Table 2-2 shows the program
memory size and number of erase and program blocks
present in each device variant. Each erase block, or
page, contains 512 instructions and each program
block, or row, contains 64 instructions.
Locations 0xF80000 through 0xF80017 are reserved
for the device Configuration registers.
Locations 0xFF0000 and 0xFF0002 are reserved for
the Device ID Word registers. These bits can be used
by the programmer to identify what device type is being
programmed. They are described in Section 7.0
“Device ID”. The Device ID registers read out
normally, even after code protection is applied.
Locations 0x800000 through 0x800FFE are reserved
for executive code memory. This region stores the
programming executive and the debugging executive.
The programming executive is used for device pro-
Figure 2-3 shows the memory map for the dsPIC33F/
PIC24H family variants.
TABLE 2-2:
CODE MEMORY SIZE
User Memory Address
Limit
(Instruction Words)
Executive Memory Address
Limit (Instruction Words)
dsPIC33F/PIC24H Device
Write Blocks
Erase Blocks
dsPIC33FJ64GP206
dsPIC33FJ64GP306
dsPIC33FJ64GP310
dsPIC33FJ64GP706
dsPIC33FJ64GP708
dsPIC33FJ64GP710
dsPIC33FJ128GP206
dsPIC33FJ128GP306
dsPIC33FJ128GP310
dsPIC33FJ128GP706
dsPIC33FJ128GP708
dsPIC33FJ128GP710
dsPIC33FJ256GP506
dsPIC33FJ256GP510
dsPIC33FJ256GP710
dsPIC33FJ64MC506
dsPIC33FJ64MC508
dsPIC33FJ64MC510
dsPIC33FJ64MC706
dsPIC33FJ64MC710
dsPIC33FJ128MC506
dsPIC33FJ128MC510
dsPIC33FJ128MC706
dsPIC33FJ128MC708
dsPIC33FJ128MC710
dsPIC33FJ256MC510
dsPIC33FJ256MC710
PIC24HJ64GP206
0x00ABFE (22K)
0x00ABFE (22K)
0x00ABFE (22K)
0x00ABFE (22K)
0x00ABFE (22K)
0x00ABFE (22K)
0x0157FE (44K)
0x0157FE (44K)
0x0157FE (44K)
0x0157FE (44K)
0x0157FE (44K)
0x0157FE (44K)
0x02ABFE (88K)
0x02ABFE (88K)
0x02ABFE (88K)
0x00ABFE (22K)
0x00ABFE (22K)
0x00ABFE (22K)
0x00ABFE (22K)
0x00ABFE (22K)
0x0157FE (44K)
0x0157FE (44K)
0x0157FE (44K)
0x0157FE (44K)
0x0157FE (44K)
0x02ABFE (88K)
0x02ABFE (88K)
0x00ABFE (22K)
0x00ABFE (22K)
0x00ABFE (22K)
0x00ABFE (22K)
0x0157FE (44K)
0x0157FE (44K)
344
344
344
344
344
344
688
688
688
688
688
688
1368
1368
1368
344
344
344
344
344
688
688
688
688
688
1368
1368
344
344
344
344
688
688
43
43
43
43
43
43
86
86
86
86
86
86
171
171
171
43
43
43
43
43
86
86
86
86
86
171
171
43
43
43
43
86
86
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
PIC24HJ64GP210
PIC24HJ64GP506
PIC24HJ64GP510
PIC24HJ128GP206
PIC24HJ128GP210
DS70152D-page 30
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
TABLE 2-2:
CODE MEMORY SIZE (CONTINUED)
0x0157FE (44K)
0x0157FE (44K)
0x0157FE (44K)
0x0157FE (44K)
0x02ABFE (88K)
0x02ABFE (88K)
0x02ABFE (88K)
0x001FFE (4K)
PIC24HJ128GP306
PIC24HJ128GP310
PIC24HJ128GP506
PIC24HJ128GP510
PIC24HJ256GP206
PIC24HJ256GP210
PIC24HJ256GP610
dsPIC33FJ12GP201
dsPIC33FJ12GP202
dsPIC33FJ12MC201
dsPIC33FJ12MC202
PIC24HJ12GP201
PIC24HJ12GP202
688
688
688
688
1368
1368
1368
64
86
86
86
86
171
171
171
8
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x8007FE (1K)
0x8007FE (1K)
0x8007FE (1K)
0x8007FE (1K)
0x8007FE (1K)
0x8007FE (1K)
0x001FFE (4K)
64
8
0x001FFE (4K)
64
8
0x001FFE (4K)
64
8
0x001FFE (4K)
64
8
0x001FFE (4K)
64
8
© 2007 Microchip Technology Inc.
Preliminary
DS70152D-page 31
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
FIGURE 2-3:
PROGRAM MEMORY MAP
0x000000
User Flash
Code Memory
(87552 x 24-bit)
0x02ABFE
0x02AC00
Reserved
0x7FFFFE
0x800000
Executive Code Memory
(2048 x 24-bit)
0x800FFE
0x801000
Reserved
0xF7FFFE
0xF80000
0xF80017
0xF80018
Configuration Registers
(12 x 8-bit)
Reserved
0xFEFFFE
0xFF0000
0xFF0002
0xFF0004
0xFFFFFE
Device ID
(2 x 16-bit)
Reserved
Note:
The address boundaries for user Flash and Executive code memory are device dependent.
DS70152D-page 32
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
3.1
Overview of the Programming
Process
3.0
DEVICE PROGRAMMING –
ENHANCED ICSP
Figure 3-1 shows the high-level overview of the
programming process. After entering Enhanced ICSP
mode, the programming executive is verified. Next, the
device is erased. Then, the code memory is pro-
grammed, followed by the nonvolatile device Configu-
ration registers. Code memory (including the
Configuration registers) is then verified to ensure that
programming was successful.
This section discusses programming the device
through Enhanced ICSP and the programming execu-
tive. The programming executive resides in executive
memory (separate from code memory) and is executed
when Enhanced ICSP Programming mode is entered.
The programming executive provides the mechanism
for the programmer (host device) to program and verify
the dsPIC33F/PIC24H Programming Specification
family devices using a simple command set and com-
munication protocol. There are several basic functions
provided by the programming executive:
After the programming executive has been verified
in memory (or loaded if not present), the dsPIC33F/
PIC24H Programming Specification can be pro-
grammed using the command set shown in Table 3-1.
• Read Memory
• Erase Memory
FIGURE 3-1:
HIGH-LEVEL ENHANCED
ICSP™ PROGRAMMING
FLOW
• Program Memory
• Blank Check
• Read Executive Firmware Revision
The programming executive performs the low-level
tasks required for erasing, programming and verifying
a device. This allows the programmer to program the
device by issuing the appropriate commands and data.
Table 3-1 summarizes the commands. A detailed
description for each command is provided in
Section 4.2 “Programming Executive Commands”.
Start
Enter Enhanced ICSP™
Perform Bulk
Erase
TABLE 3-1:
Command
COMMAND SET SUMMARY
Description
Program Memory
Verify Program
SCHECK
READC
Sanity check
Read Configuration registers or Device
ID registers
READP
PROGC
Read code memory
Program a Configuration register and
verify
Program Configuration Bits
Verify Configuration Bits
PROGP
PROGW
Program one row of code memory and
verify
Program one word of code memory
and verify
Exit Enhanced ICSP
Done
QBLANK
QVER
Query if the code memory is blank
Query the software version
The programming executive uses the device’s data
RAM for variable storage and program execution. After
the programming executive has run, no assumptions
should be made about the contents of data RAM.
© 2007 Microchip Technology Inc.
Preliminary
DS70152D-page 33
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
3.2
Confirming the Presence of the
Programming Executive
3.3
Entering Enhanced ICSP Mode
As shown in Figure 3-3, entering Enhanced ICSP
Program/Verify mode requires three steps:
Before programming can begin, the programmer must
confirm that the programming executive is stored in
executive memory. The procedure for this task is
shown in Figure 3-2.
1. The MCLR pin is briefly driven high then low.
2. A 32-bit key sequence is clocked into PGD.
3. MCLR is then driven high within a specified
period of time and held.
First, ICSP mode is entered. Then, the unique Applica-
tion ID Word stored in executive memory is read. If the
programming executive is resident, the Application ID
Word is 0xBB, which means programming can resume
as normal. However, if the Application ID Word is not
0xBB, the programming executive must be programmed
to executive code memory using the method described in
Section 6.0 “Programming the Programming Exec-
utive to Memory”.
The programming voltage applied to MCLR is VIH,
which is essentially VDD in the case of dsPIC33F/
PIC24H devices. There is no minimum time require-
ment for holding at VIH. After VIH is removed, an inter-
val of at least P18 must elapse before presenting the
key sequence on PGD.
The key sequence is a specific 32-bit pattern,
‘0100 1101 0100 0011 0100 1000 0101 0000’
(more easily remembered as 0x4D434850 in hexa-
decimal format). The device will enter Program/Verify
mode only if the key sequence is valid. The Most
Significant bit (MSb) of the most significant nibble must
be shifted in first.
Section 5.0 “Device Programming – ICSP” describes
the ICSP programming method. Section 5.11 “Reading
the Application ID Word” describes the procedure for
reading the Application ID Word in ICSP mode.
FIGURE 3-2:
CONFIRMING PRESENCE
OF PROGRAMMING
EXECUTIVE
Once the key sequence is complete, VIH must be
applied to MCLR and held at that level for as long as
Program/Verify mode is to be maintained. An interval
time of at least P19 and P7 must elapse before present-
ing data on PGD. Signals appearing on PGD before P7
has elapsed will not be interpreted as valid.
Start
On successful entry, the program memory can be
accessed and programmed in serial fashion. While in
the Program/Verify mode, all unused I/Os are placed in
the high-impedance state.
Enter ICSP™ Mode
Read the
Application ID
from Address
0x807F0
Is
No
Application ID
0xBB?
Yes
Prog. Executive is
Resident in Memory
Prog. Executive must
be Programmed
Finish
DS70152D-page 34
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
FIGURE 3-3:
ENTERING ENHANCED ICSP™ MODE
P6
P19
P7
P14
VIH
VIH
MCLR
VDD
Program/Verify Entry Code = 0x4D434850
0
1
0
0
1
0
0
0
0
...
PGD
b31 b30 b29 b28 b27
b3
b2
b1
b0
PGC
P1A
P1B
P18
3.4
Blank Check
3.5
3.5.1
Code Memory Programming
The term “Blank Check” implies verifying that the
device has been successfully erased and has no
programmed memory locations. A blank or erased
memory location is always read as a ‘1’.
PROGRAMMING METHODOLOGY
Code memory is programmed with the PROGP
command. PROGPprograms one row of code memory
starting from the memory address specified in the
command. The number of PROGPcommands required
to program a device depends on the number of write
blocks that must be programmed in the device.
The Device ID registers (0xFF0000:0xFF0002) can be
ignored by the Blank Check since this region stores
device information that cannot be erased. The device
Configuration registers are also ignored by the Blank
Check. Additionally, all unimplemented memory space
should be ignored from the Blank Check.
A flowchart for programming code memory is shown in
Figure 3-4. In this example, all 88K instruction words of
a dsPIC33F/PIC24H device are programmed. First, the
number of commands to send (called ‘RemainingC-
mds’ in the flowchart) is set to 1368 and the destination
address (called ‘BaseAddress’) is set to ‘0’. Next, one
write block in the device is programmed with a PROGP
command. Each PROGP command contains data for
one row of code memory of the dsPIC33F/PIC24H.
After the first command is processed successfully,
‘RemainingCmds’ is decremented by ‘1’ and compared
with ‘0’. Since there are more PROGP commands to
send, ‘BaseAddress’ is incremented by 0x80 to point to
the next row of memory.
The QBLANKcommand is used for the Blank Check. It
determines if the code memory is erased by testing
these memory regions. A ‘BLANK’ or ‘NOT BLANK’
response is returned. If it is determined that the device
is not blank, it must be erased before attempting to
program the chip.
On the second PROGP command, the second row is
programmed. This process is repeated until the entire
device is programmed..
Note:
If a bootloader needs to be programmed,
the bootloader code must not be pro-
grammed into the first page of code mem-
ory. For example, if a bootloader located at
address 0x200 attempts to erase the first
page, it would inadvertently erase itself.
Instead, program the bootloader into the
second page, e.g. 0x400.
© 2007 Microchip Technology Inc.
Preliminary
DS70152D-page 35
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
FIGURE 3-4:
FLOWCHART FOR
PROGRAMMING CODE
MEMORY
3.5.2
PROGRAMMING VERIFICATION
After code memory is programmed, the contents of
memory can be verified to ensure that programming
was successful. Verification requires code memory to
be read back and compared against the copy held in
the programmer’s buffer.
Start
The READPcommand can be used to read back all the
BaseAddress = 0x0
RemainingCmds = 1368
programmed code memory.
Alternatively, you can have the programmer perform
the verification after the entire device is programmed,
using a checksum computation.
Send PROGP
Command to Program
BaseAddress
3.5.3
CHECKSUM COMPUTATION
Only the Configuration registers are included in the
checksum computation. The Device ID and Unit ID are
not included in the checksum computation.
Is
No
PROGPresponse
PASS?
Table 3-2 shows how this 16-bit computation can be
made for each dsPIC33F and PIC24H device. Compu-
tations for read code protection are shown both
enabled and disabled. The checksum values shown
here assume that the Configuration registers are also
erased. However, when code protection is enabled,
the value of the FGS register is assumed to be 0x5.
Yes
RemainingCmds =
RemainingCmds – 1
BaseAddress =
BaseAddress + 0x80
Is
RemainingCmds
‘0’?
No
Yes
Failure
Report Error
Finish
DS70152D-page 36
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
TABLE 3-2:
CHECKSUM COMPUTATION
Read Code
Value with
0xAAAAAA at 0x0
and Last
Erased
Value
Device
Checksum Computation
Protection
Code Address
dsPIC33FJ64GP206
dsPIC33FJ64GP306
dsPIC33FJ64GP310
dsPIC33FJ64GP706
dsPIC33FJ64GP708
dsPIC33FJ64GP710
Disabled
CFGB + SUM(0:00ABFF)
CFGB
0x03BC
0x05BA
0x03BC
0x05BA
0x03BC
0x05BA
0x03BC
0x05BA
0x03BC
0x05BA
0x03BC
0x05BA
0x01BC
0x05BA
0x01BC
0x05BA
0x01BC
0x05BA
0x01BC
0x05BA
0x01BC
0x05BA
0x01BC
0x05BA
0x03BC
0x05BA
0x03BC
0x05BA
0x03BC
0x05BA
0x01BE
0x05BA
0x01BE
0x05BA
0x01BE
0x05BA
0x01BE
0x05BA
0x01BE
0x05BA
0x01BE
0x05BA
0xFFBE
0x05BA
0xFFBE
0x05BA
0xFFBE
0x05BA
0xFFBE
0x05BA
0xFFBE
0x05BA
0xFFBE
0x05BA
0x01BE
0x05BA
0x01BE
0x05BA
0x01BE
0x05BA
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
CFGB + SUM(0:00ABFF)
CFGB
CFGB + SUM(0:00ABFF)
CFGB
CFGB + SUM(0:00ABFF)
CFGB
CFGB + SUM(0:00ABFF)
CFGB
CFGB + SUM(0:00ABFF)
CFGB
dsPIC33FJ128GP206 Disabled
Enabled
CFGB + SUM(0:0157FF)
CFGB
dsPIC33FJ128GP306 Disabled
Enabled
CFGB + SUM(0:0157FF)
CFGB
dsPIC33FJ128GP310 Disabled
Enabled
CFGB + SUM(0:0157FF)
CFGB
dsPIC33FJ128GP706 Disabled
Enabled
CFGB + SUM(0:0157FF)
CFGB
dsPIC33FJ128GP708 Disabled
Enabled
CFGB + SUM(0:0157FF)
CFGB
dsPIC33FJ128GP710 Disabled
Enabled
CFGB + SUM(0:0157FF)
CFGB
dsPIC33FJ256GP506 Disabled
Enabled
CFGB + SUM(0:02ABFF)
CFGB
dsPIC33FJ256GP510 Disabled
Enabled
CFGB + SUM(0:02ABFF)
CFGB
dsPIC33FJ256GP710 Disabled
Enabled
CFGB + SUM(0:02ABFF)
CFGB
Item Description:
SUM(a:b) = Byte sum of locations a to b inclusive (all 3 bytes of code memory)
CFGB = Configuration Block (masked)
= Byte sum of ((FBS & 0xCF) + (FSS & 0xFF) + (FGS & 0x07) + (FOSCSEL & 0xA7) + (FOSC & 0xE7) +
(FWDT & 0xDF) + (FPOR & 0xE7) + (FICD & 0xE3))
(for dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202)
= Byte sum of ((FBS & 0xCF) + (FSS & 0xCF) + (FGS & 0x07) + (FOSCSEL & 0xA7) + (FOSC & 0xC7) +
(FWDT & 0xDF) + (FPOR & 0xE7) + (FICD & 0xE3))
(for all other devices)
© 2007 Microchip Technology Inc.
Preliminary
DS70152D-page 37
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
TABLE 3-2:
CHECKSUM COMPUTATION (CONTINUED)
Value with
0xAAAAAA at 0x0
and Last
Read Code
Erased
Value
Device
Checksum Computation
Protection
Code Address
dsPIC33FJ64MC506 Disabled
Enabled
CFGB + SUM(0:00ABFF)
CFGB
0x03BC
0x05BA
0x03BC
0x05BA
0x03BC
0x05BA
0x03BC
0x05BA
0x03BC
0x05BA
0x01BC
0x05BA
0x01BC
0x05BA
0x01BC
0x05BA
0x01BC
0x05BA
0x01BC
0x05BA
0x03BC
0x05BA
0x03BC
0x05BA
0x03BC
0x05BA
0x03BC
0x05BA
0x03BC
0x05BA
0x01BE
0x05BA
0x01BE
0x05BA
0x01BE
0x05BA
0x01BE
0x05BA
0x01BE
0x05BA
0xFFBE
0x05BA
0xFFBE
0x05BA
0xFFBE
0x05BA
0xFFBE
0x05BA
0xFFBE
0x05BA
0x01BE
0x05BA
0x01BE
0x05BA
0x01BE
0x05BA
0x01BE
0x05BA
0x01BE
0x05BA
dsPIC33FJ64MC508 Disabled
Enabled
CFGB + SUM(0:00ABFF)
CFGB
dsPIC33FJ64MC510 Disabled
Enabled
CFGB + SUM(0:00ABFF)
CFGB
dsPIC33FJ64MC706 Disabled
Enabled
CFGB + SUM(0:00ABFF)
CFGB
dsPIC33FJ64MC710 Disabled
Enabled
CFGB + SUM(0:00ABFF)
CFGB
dsPIC33FJ128MC506 Disabled
Enabled
CFGB + SUM(0:0157FF)
CFGB
dsPIC33FJ128MC510 Disabled
Enabled
CFGB + SUM(0:0157FF)
CFGB
dsPIC33FJ128MC706 Disabled
Enabled
CFGB + SUM(0:0157FF)
CFGB
dsPIC33FJ128MC708 Disabled
Enabled
CFGB + SUM(0:0157FF)
CFGB
dsPIC33FJ128MC710 Disabled
Enabled
CFGB + SUM(0:0157FF)
CFGB
dsPIC33FJ256MC510 Disabled
Enabled
CFGB + SUM(0:02ABFF)
CFGB
dsPIC33FJ256MC710 Disabled
Enabled
CFGB + SUM(0:02ABFF)
CFGB
PIC24HJ64GP206
PIC24HJ64GP210
PIC24HJ64GP506
Item Description:
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
CFGB + SUM(0:00ABFF)
CFGB
CFGB + SUM(0:00ABFF)
CFGB
CFGB + SUM(0:00ABFF)
CFGB
SUM(a:b) = Byte sum of locations a to b inclusive (all 3 bytes of code memory)
CFGB = Configuration Block (masked)
= Byte sum of ((FBS & 0xCF) + (FSS & 0xFF) + (FGS & 0x07) + (FOSCSEL & 0xA7) + (FOSC & 0xE7) +
(FWDT & 0xDF) + (FPOR & 0xE7) + (FICD & 0xE3))
(for dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202)
= Byte sum of ((FBS & 0xCF) + (FSS & 0xCF) + (FGS & 0x07) + (FOSCSEL & 0xA7) + (FOSC & 0xC7) +
(FWDT & 0xDF) + (FPOR & 0xE7) + (FICD & 0xE3))
(for all other devices)
DS70152D-page 38
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
TABLE 3-2:
CHECKSUM COMPUTATION (CONTINUED)
Value with
0xAAAAAA at 0x0
and Last
Read Code
Erased
Value
Device
Checksum Computation
Protection
Code Address
PIC24HJ64GP510
PIC24HJ128GP206
PIC24HJ128GP210
PIC24HJ128GP306
PIC24HJ128GP310
PIC24HJ128GP506
PIC24HJ128GP510
PIC24HJ256GP206
PIC24HJ256GP210
PIC24HJ256GP610
dsPIC33FJ12GP201
dsPIC33FJ12GP202
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
CFGB + SUM(0:00ABFF)
CFGB
0x03BC
0x05BA
0x01BC
0x05BA
0x01BC
0x05BA
0x01BC
0x05BA
0x01BC
0x05BA
0x01BC
0x05BA
0x01BC
0x05BA
0x03BC
0x05BA
0x03BC
0x05BA
0x03BC
0x05BA
0xD60C
0x060A
0xD60C
0x060A
0xD60C
0x060A
0xD60C
0x060A
0xD60C
0x060A
0xD60C
0x060A
0x01BE
0x05BA
0xFFBE
0x05BA
0xFFBE
0x05BA
0xFFBE
0x05BA
0xFFBE
0x05BA
0xFFBE
0x05BA
0xFFBE
0x05BA
0x01BE
0x05BA
0x01BE
0x05BA
0x01BE
0x05BA
0xD40E
0x060A
0xD40E
0x060A
0xD40E
0x060A
0xD40E
0x060A
0xD40E
0x060A
0xD40E
0x060A
CFGB + SUM(0:0157FF)
CFGB
CFGB + SUM(0:0157FF)
CFGB
CFGB + SUM(0:0157FF)
CFGB
CFGB + SUM(0:0157FF)
CFGB
CFGB + SUM(0:0157FF)
CFGB
CFGB + SUM(0:0157FF)
CFGB
CFGB + SUM(0:02ABFF)
CFGB
CFGB + SUM(0:02ABFF)
CFGB
CFGB + SUM(0:02ABFF)
CFGB
CFGB + SUM(0:001FFF)
CFGB
CFGB + SUM(0:001FFF)
CFGB
dsPIC33FJ12MC201 Disabled
Enabled
CFGB + SUM(0:001FFF)
CFGB
dsPIC33FJ12MC202 Disabled
Enabled
CFGB + SUM(0:001FFF)
CFGB
PIC24HJ12GP201
PIC24HJ12GP202
Item Description:
Disabled
Enabled
Disabled
Enabled
CFGB + SUM(0:001FFF)
CFGB
CFGB + SUM(0:001FFF)
CFGB
SUM(a:b) = Byte sum of locations a to b inclusive (all 3 bytes of code memory)
CFGB = Configuration Block (masked)
= Byte sum of ((FBS & 0xCF) + (FSS & 0xFF) + (FGS & 0x07) + (FOSCSEL & 0xA7) + (FOSC & 0xE7) +
(FWDT & 0xDF) + (FPOR & 0xE7) + (FICD & 0xE3))
(for dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202)
= Byte sum of ((FBS & 0xCF) + (FSS & 0xCF) + (FGS & 0x07) + (FOSCSEL & 0xA7) + (FOSC & 0xC7) +
(FWDT & 0xDF) + (FPOR & 0xE7) + (FICD & 0xE3))
(for all other devices)
© 2007 Microchip Technology Inc.
Preliminary
DS70152D-page 39
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
3.6
Configuration Bits Programming
3.6.1
OVERVIEW
The dsPIC33F/PIC24H has Configuration bits stored
in twelve 8-bit Configuration registers, aligned on even
configuration memory address boundaries. These bits
can be set or cleared to select various device configu-
rations. There are three types of Configuration bits:
system operation bits, code-protect bits and unit ID bits.
The system operation bits determine the power-on set-
tings for system level components, such as oscillator
and Watchdog Timer. The code-protect bits prevent
program memory from being read and written.
The register descriptions for the FBS, FSS, FGS,
FOSCSEL, FOSC, FWDT, FPOR and FICD
Configuration registers are shown in Table 3-3.
The Configuration register map is shown in Table 3-4..
Note:
If any of the code-protect bits in FBS, FSS
or FGS is clear, then the entire device
must be erased before it can be
reprogrammed.
DS70152D-page 40
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
TABLE 3-3:
dsPIC33F/PIC24H CONFIGURATION BITS DESCRIPTION
Bit Field
Register
Description
RBS<1:0>
FBS
Boot Segment Data RAM Code Protection
11= No RAM is reserved for Boot Segment
10= Small-sized Boot RAM
[128 bytes of RAM are reserved for Boot Segment]
01= Medium-sized Boot RAM
[256 bytes of RAM are reserved for Boot Segment]
00= Large-sized Boot RAM
[1024 bytes of RAM are reserved for Boot Segment]
[Note: This bit is Reserved in dsPIC33FJ12GP201/202,
dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202.]
BSS<2:0>
FBS
Boot Segment Program Memory Code Protection
111= No Boot Segment
110= Standard security, Small-sized Boot Program Flash
[Boot Segment ends at 0x0003FF in dsPIC33FJ12GP201/202,
dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202.
Boot Segment ends at 0x0007FF in other all other devices.]
101= Standard security, Medium-sized Boot Program Flash
[Boot Segment ends at 0x0007FF in dsPIC33FJ12GP201/202,
dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202.
Boot Segment ends at 0x001FFF in all other devices.]
100= Standard security, Large-sized Boot Program Flash
[Boot Segment ends at 0x000FFF in dsPIC33FJ12GP201/202,
dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202.
Boot Segment ends at 0x003FFF in all other devices.]
011= No Boot Segment
010= High security, Small-sized Boot Program Flash
[Reserved in dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202 and
PIC24HJ12GP201/202.
Boot Segment ends at 0x0007FF in all other devices.]
001= High security, Medium-sized Boot Program Flash
[Reserved in dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202 and
PIC24HJ12GP201/202.
Boot Segment ends at 0x001FFF in all other devices.]
000= High security, Large-sized Boot Program Flash
[Reserved in dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202 and
PIC24HJ12GP201/202.
Boot Segment ends at 0x003FFF in all other devices.]
BWRP
FBS
Boot Segment Program Memory Write Protection
1= Boot Segment program memory is not write-protected
0= Boot program memory is write-protected
© 2007 Microchip Technology Inc.
Preliminary
DS70152D-page 41
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
TABLE 3-3:
Bit Field
RSS<1:0>
dsPIC33F/PIC24H CONFIGURATION BITS DESCRIPTION (CONTINUED)
Register
Description
FSS
Secure Segment Data RAM Code Protection
11= No Data RAM is reserved for Secure Segment
10= Small-sized Secure RAM
[(256 – N) bytes of RAM are reserved for Secure Segment in all other
devices.]
01= Medium-sized Secure RAM
[(2048 – N) bytes of RAM are reserved for Secure Segment in all other
devices.]
00= Large-sized Secure RAM
[(4096 – N) bytes of RAM are reserved for Secure Segment in all other
devices.]
where N = Number of bytes of RAM reserved for Boot Sector.
Note 1: This bit is Reserved in dsPIC33FJ12GP201/202,
dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202.]
2: If the defined Boot Segment size is greater than or equal to
the defined Secure Segment, then the Secure Segment size
selection has no effect and the Secure Segment is disabled.
SSS<2:0>
FSS
Secure Segment Program Memory Code Protection
111= No Secure Segment
110= Standard security, Small-sized Secure Program Flash
[Secure Segment ends at 0x001FFF for dsPIC33FJ64GPxxx/
dsPIC33FJ64MCxxx/PIC24HJ64GPxxx devices, and at 0x003FFF in
other devices.]
101= Standard security, Medium-sized Secure Program Flash
[Secure Segment ends at 0x003FFF for dsPIC33FJ64GPxxx/
dsPIC33FJ64MCxxx/PIC24HJ64GPxxx devices, and at 0x007FFF in
other devices.]
100= Standard security, Large-sized Secure Program Flash
[Secure Segment ends at 0x007FFF for dsPIC33FJ64GPxxx/
dsPIC33FJ64MCxxx/PIC24HJ64GPxxx devices, and at 0x00FFFF in
other devices.]
011= No Secure Segment
010= High security, Small-sized Secure Program Flash
[Secure Segment ends at 0x001FFF for dsPIC33FJ64GPxxx/
dsPIC33FJ64MCxxx/PIC24HJ64GPxxx devices, and at 0x003FFF in
other devices.]
001= High security, Medium-sized Secure Program Flash
[Secure Segment ends at 0x003FFF for dsPIC33FJ64GPxxx/
dsPIC33FJ64MCxxx/PIC24HJ64GPxxx devices, and at 0x007FFF in
other devices.]
000= High security, Large-sized Secure Program Flash
[Secure Segment ends at 0x007FFF for dsPIC33FJ64GPxxx/
dsPIC33FJ64MCxxx/PIC24HJ64GPxxx devices, and at 0x00FFFF in
other devices.]
[Note: This bit is Reserved in dsPIC33FJ12GP201/202,
dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202.]
SWRP
FSS
Secure Segment Program Memory Write Protection
1= Secure Segment program memory is not write-protected
0= Secure program memory is write-protected
[Note: This bit is Reserved in dsPIC33FJ12GP201/202,
dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202.]
DS70152D-page 42
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
TABLE 3-3:
dsPIC33F/PIC24H CONFIGURATION BITS DESCRIPTION (CONTINUED)
Bit Field
Register
Description
GSS<1:0>
FGS
General Segment Code-Protect bit
11= Code protection is disabled
10= Standard security code protection is enabled
0x= Reserved in dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202
and PIC24HJ12GP201/202. In all other devices, high security code
protection is enabled.
GWRP
IESO
FGS
General Segment Write-Protect bit
1= General Segment program memory is not write-protected
0= General Segment program memory is write-protected
FOSCSEL
Two-speed Oscillator Start-Up Enable bit
1= Start up device with FRC, then automatically switch to the
user-selected oscillator source when ready
0= Start up device with user-selected oscillator source
TEMP
FOSCSEL
FOSCSEL
Temperature Protection Enable bit
1= Temperature protection disabled
0= Temperature protection enabled
FNOSC<2:0>
Initial Oscillator Source Selection bits
111= Internal Fast RC (FRC) oscillator
110= Reserved
101= LPRC oscillator
100= Secondary (LP) oscillator
011= Primary (XT, HS, EC) oscillator with PLL
010= Primary (XT, HS, EC) oscillator
001= Internal Fast RC (FRC) oscillator with PLL
000= Reserved
FCKSM<1:0>
IOL1WAY
FOSC
FOSC
Clock Switching Mode bits
1x= Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01= Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00= Clock switching is enabled, Fail-Safe Clock Monitor is enabled
Peripheral Pin Select Configuration
1= Allow only one reconfiguration
0= Allow multiple reconfigurations
[Note: This bit is only present in the dsPIC33FJ12GP201/202,
dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202 devices.]
OSCIOFNC
FOSC
FOSC
OSC2 Pin Function bit (except in XT and HS modes)
1= OSC2 is clock output
0= OSC2 is general purpose digital I/O pin
POSCMD<1:0>
Primary Oscillator Mode Select bits
11= Primary oscillator disabled
10= HS crystal oscillator mode
01= XT crystal oscillator mode
00= EC (external clock) mode
FWDTEN
FWDT
Watchdog Enable bit
1= Watchdog always enabled (LPRC oscillator cannot be disabled.
Clearing the SWDTEN bit in the RCON register will have no effect)
0= Watchdog enabled/disabled by user software (LPRC can be
disabled by clearing the SWDTEN bit in the RCON register)
WINDIS
FWDT
FWDT
Watchdog Timer Window Enable bit
1 = Watchdog Timer in Non-Window mode
0 = Watchdog Timer in Window mode
WDTPRE
Watchdog Timer Prescaler bit
1= 1:128
0= 1:32
© 2007 Microchip Technology Inc.
Preliminary
DS70152D-page 43
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
TABLE 3-3:
Bit Field
WDTPOST
dsPIC33F/PIC24H CONFIGURATION BITS DESCRIPTION (CONTINUED)
Register
Description
FWDT
Watchdog Timer Postscaler bits
1111= 1:32,768
1110= 1:16,384
.
.
.
0001= 1:2
0000= 1:1
PWMPIN
FPOR
Motor Control PWM Module Pin mode
1= PWM module pins controlled by PORT register at device Reset
(tri-stated)
0= PWM module pins controlled by PWM module at device Reset
(configured as output pins)
HPOL
LPOL
FPOR
FPOR
FPOR
Motor Control PWM High-side Polarity bit
1= PWM module high-side output pins have active-high output polarity
0= PWM module high-side output pins have active-low output polarity
Motor Control PWM Low-side Polarity bit
1= PWM module low-side output pins have active-high output polarity
0= PWM module low-side output pins have active-low output polarity
ALTI2C
Alternate I2C™ pins
1 = I2C mapped to SDA1/SCL1 pins
0 = I2C mapped to ASDA1/SACL1 pins
[Note: This bit is only present in the dsPIC33FJ12GP201/202,
dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202 devices.]
FPWRT<2:0>
FPOR
Power-on Reset Timer Value Select bits
111= PWRT = 128 ms
110= PWRT = 64 ms
101= PWRT = 32 ms
100= PWRT = 16 ms
011= PWRT = 8 ms
010= PWRT = 4 ms
001= PWRT = 2 ms
000= PWRT Disabled
BKBUG
COE
FICD
FICD
FICD
FICD
Background Debug Enable bit
1= Device will reset in User mode
0= Device will reset in Debug mode
Debugger/Emulator Enable bit
1= Device will reset in Operational mode
0= Device will reset in Clip-On Emulation mode
JTAGEN
ICS<1:0>
JTAG Enable bit
1= JTAG enabled
0= JTAG disabled
ICD Communication Channel Select bits
11= Communicate on PGC1/EMUC1 and PGD1/EMUD1
10= Communicate on PGC2/EMUC2 and PGD2/EMUD2
01= Communicate on PGC3/EMUC3 and PGD3/EMUD3
00= Reserved, do not use
—
All
Unimplemented (read as ‘0’, write as ‘0’)
DS70152D-page 44
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
TABLE 3-4:
dsPIC33F/PIC24H DEVICE CONFIGURATION REGISTER MAP
Address
Name
Bit 7
RBS<1:0>(3)
RSS<1:0>(3)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
BSS<2:0>
SSS<2:0>(3)
Bit 1
Bit 0
BWRP
SWRP(3)
GWRP
0xF80000
0xF80002
0xF80004
FBS
FSS
FGS
—
—
—
GSS<1:0>
FNOSC<2:0>
0xF80006 FOSCSEL
IESO
—
TEMP
IOL1WAY(2)
—
—
0xF80008
0xF8000A
0xF8000C
0xF8000E
0xF80010
0xF80012
0xF80014
0xF80016
FOSC
FWDT
FPOR
FICD
FCKSM<1:0>
OSCIOFNC POSCMD<1:0>
WDTPOST<3:0>
FPWRT<2:0>
FWDTEN WINDIS
PWMPIN(1) HPOL(1)
-
WDTPRE
ALTI2C(2)
LPOL(1)
JTAGEN
—
—
BKBUG
COE
ICS<1:0>
FUID0
FUID1
FUID2
FUID3
User Unit ID Byte 0
User Unit ID Byte 1
User Unit ID Byte 2
User Unit ID Byte 3
Note 1: On the dsPIC33F General Purpose Family devices (dsPIC33FJXXXGPXXX) and PIC24H devices, these
bits are reserved (read as ‘1’ and must be programmed as ‘1’).
2: These bits are only present in the dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202 and
PIC24HJ12GP201/202 devices. In all other devices, they are unimplemented (read as ‘0’).
3: In the dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202 devices, these bits
are reserved (read as ‘1’ and must be programmed as ‘1’).
3.6.2
PROGRAMMING METHODOLOGY
3.6.4
CODEGUARD SECURITY
CONFIGURATION BITS
Configuration bits may be programmed a single byte at
a time using the PROGC command. This command
specifies the configuration data and Configuration
register address. When Configuration bits are
programmed, any unimplemented bits must be
programmed with a ‘0’ and any reserved bits must be
programmed with a ‘1’.
The FBS, FSS and FGS Configuration registers are
special Configuration registers that control the size and
level of code protection for the Boot Segment, Secure
Segment and General Segment, respectively. For each
segment, two main forms of code protection are
provided. One form prevents code memory from being
written (write protection), while the other prevents code
memory from being read (read protection).
Twelve PROGCcommands are required to program all
the Configuration bits. A flowchart for Configuration bit
programming is shown in Figure 3-5.
BWRP, SWRP and GWRP bits control write protection
and BSS<2:0>, SSS<2:0> and GSS<1:0> bits controls
read protection. The Chip Erase ERASEB command
sets all the code protection bits to ‘1’, which allows the
device to be programmed.
Note:
If the General Code Segment Code-
Protect bit (GCP) is programmed to ‘0’,
code memory is code-protected and
can not be read. Code memory must
be verified before enabling read protec-
tion. See Section 3.6.4 “CodeGuard
Security Configuration Bits” for more
information about code-protect Configura-
tion bits.
When write protection is enabled, any programming
operation to code memory will fail. When read protec-
tion is enabled, any read from code memory will cause
a ‘0x0’ to be read, regardless of the actual contents of
code memory. Since the programming executive
always verifies what it programs, attempting to program
code memory with read protection enabled will also
result in failure.
3.6.3
PROGRAMMING VERIFICATION
After the Configuration bits are programmed, the
contents of memory should be verified to ensure that
the programming was successful. Verification requires
the Configuration bits to be read back and compared
against the copy held in the programmer’s buffer. The
READC command reads back the programmed
Configuration bits and verifies that the programming
was successful.
It is imperative that all code protection bits are ‘1’ while
the device is being programmed and verified. Only after
the device is programmed and verified should any of
the above bits be programmed to ‘0’.
Any unimplemented Configuration bits are read-only
and read as ‘0’. The reserved bits are read-only and
read as ‘1’.
© 2007 Microchip Technology Inc.
Preliminary
DS70152D-page 45
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
In addition to code memory protection, a part of Data
RAM can be configured to be accessible only by code
resident in the Boot Segment and/or Secure Segment.
The sizes of these “reserved” sections are user-config-
urable, using the RBS<1:0> and RSS<1:0> bits.
3.6.5
USER UNIT ID
The dsPIC33F/PIC24H devices provide four 8-bit Con-
figuration registers (FUID0 through FUID3) for the user
to store product-specific information, such as unit serial
numbers and other product manufacturing data.
Note:
All bits in the FBS, FSS and FGS Configu-
ration registers can only be programmed
to a value of ‘0’. the ERASEBcommand is
the only way to reprogram code-protect
bits from ON (‘0’) to OFF (‘1’).
FIGURE 3-5:
CONFIGURATION BIT PROGRAMMING FLOW
Start
ConfigAddress = 0xF80000
Send PROGC
Command
Is
No
PROGCresponse
PASS?
Yes
Is
No
ConfigAddress =
ConfigAddress + 2
ConfigAddress
0xF80018?
Yes
Failure
Report Error
Finish
FIGURE 3-6:
EXITING ENHANCED
ICSP™ MODE
3.7
Exiting Enhanced ICSP Mode
Exiting Program/Verify mode is done by removing VIH
from MCLR, as shown in Figure 3-6. The only require-
ment for exit is that an interval P16 should elapse
between the last clock and program signals on PGC
and PGD before removing VIH.
P16
P17
VIH
MCLR
VDD
VIH
PGD
PGC
PGD = Input
DS70152D-page 46
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
After the programming executive has processed the
4.0
4.1
THE PROGRAMMING
command, it brings PGD low for 15 μsec to indicate to
EXECUTIVE
the programmer that the response is available to be
clocked out. The programmer can begin to clock out
Programming Executive
Communication
the response 23 μsec after PGD is brought low and it
must provide the necessary amount of clock pulses to
receive the entire response from the programming
executive.
The programmer and programming executive have a
master-slave relationship, where the programmer is
the master programming device and the programming
executive is the slave.
After the entire response is clocked out, the program-
mer should terminate the clock on PGC until it is time
to send another command to the programming
executive. This protocol is shown in Figure 4-2.
All communication is initiated by the programmer in the
form of a command. Only one command at a time can
be sent to the programming executive. In turn, the
programming executive only sends one response to
the programmer after receiving and processing a
command. The programming executive command set
is described in Section 4.2 “Programming Executive
Commands”. The response set is described in
Section 4.3 “Programming Executive Responses”.
4.1.2
SPI RATE
In Enhanced ICSP mode, the dsPIC33F/PIC24H family
devices operate from the Fast Internal RC oscillator,
which has a nominal frequency of 7.3728 MHz. This
oscillator frequency yields an effective system clock
frequency of 1.8432 MHz. To ensure that the program-
mer does not clock too fast, it is recommended that a
7.35 MHz clock be provided by the programmer.
4.1.1
COMMUNICATION INTERFACE
AND PROTOCOL
4.1.3
TIME OUTS
The ICSP/Enhanced ICSP interface is a 2 wire SPI
implemented using the PGC and PGD pins. The PGC
pin is used as a clock input pin and the clock source
must be provided by the programmer. The PGD pin is
used for sending command data to and receiving
response data from the programming executive. All
serial data is transmitted on the falling edge of PGC
and latched on the rising edge of PGC. All data trans-
missions are sent to the Most Significant bit (MSb) first
using 16-bit mode (see Figure 4-1).
The programming executive uses no Watchdog or time
out for transmitting responses to the programmer. If the
programmer does not follow the flow control
mechanism using PGC as described in Section 4.1.1
“Communication Interface and Protocol”, it is
possible that the programming executive will behave
unexpectedly while trying to send a response to the
programmer. Since the programming executive has no
time out, it is imperative that the programmer correctly
follow the described communication protocol.
As a safety measure, the programmer should use the
command time outs identified in Table 4-1. If the
command time out expires, the programmer should
reset the programming executive and start
programming the device again.
FIGURE 4-1:
PROGRAMMING
EXECUTIVE SERIAL
TIMING
P1
12 13
14
6
11
1
2
3
4
5
15
16
PGC
PGD
P1A
P3
P1B
P2
...
MSb 14 13 12 11
5
4
3
2
1
LSb
Since a 2 wire SPI is used, and data transmissions are
bidirectional, a simple protocol is used to control the
direction of PGD. When the programmer completes a
command transmission, it releases the PGD line and
allows the programming executive to drive this line
high. The programming executive keeps the PGD line
high to indicate that it is processing the command.
© 2007 Microchip Technology Inc.
Preliminary
DS70152D-page 47
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
FIGURE 4-2:
PROGRAMMING EXECUTIVE – PROGRAMMER COMMUNICATION PROTOCOL
Programming Executive
Processes Command
Host Transmits
Last Command Word
Host Clocks Out Response
1
2
15 16
1
2
15 16
1
2
15 16
PGC
PGD
MSB X X X LSB
1
0
MSB X X X LSB
MSB X X X LSB
P8
P9a
P9b
8ns
23 µs
PGC = Input (Idle)
PGD = Output
PGC = Input
PGD = Input
PGC = Input
PGD = Output
4.2.2
PACKED DATA FORMAT
4.2
Programming Executive
Commands
When 24-bit instruction words are transferred across
the 16-bit SPI interface, they are packed to conserve
space using the format shown in Figure 4-4. This
format minimizes traffic over the SPI and provides the
programming executive with data that is properly
aligned for performing table write operations.
The programming executive command set is shown in
Table 4-1. This table contains the opcode, mnemonic,
length, time out and description for each command.
Functional details on each command are provided in
the command descriptions (Section 4.2.4 “Command
Descriptions”).
FIGURE 4-4:
PACKED INSTRUCTION
WORD FORMAT
4.2.1
COMMAND FORMAT
All programming executive commands have a general
format consisting of a 16-bit header and any required
data for the command (see Figure 4-3). The 16-bit
header consists of a 4-bit opcode field, which is used to
identify the command, followed by a 12-bit command
length field.
15
8
7
0
LSW1
MSB2
MSB1
LSW2
LSWx: Least Significant 16 bits of instruction word
MSBx: Most Significant Byte of instruction word
FIGURE 4-3:
COMMAND FORMAT
15
12
11
0
Note:
When the number of instruction words
transferred is odd, MSB2 is zero and
LSW2 can not be transmitted.
Opcode
Length
Command Data First Word (if required)
•
4.2.3
PROGRAMMING EXECUTIVE
ERROR HANDLING
•
Command Data Last Word (if required)
The programming executive will “NACK” all
unsupported commands. Additionally, due to the
memory constraints of the programming executive, no
checking is performed on the data contained in the
programmer command. It is the responsibility of the
programmer to command the programming executive
with valid command arguments or the programming
operation may fail. Additional information on error
handling is provided in Section 5.3.1.3 “QE_Code
Field”.
The command opcode must match one of those in the
command set. Any command that is received which
does not match the list in Table 4-1 will return a “NACK”
response (see Section 5.3.1.1 “Opcode Field”).
The command length is represented in 16-bit words
since the SPI operates in 16-bit mode. The program-
ming executive uses the command length field to
determine the number of words to read from the SPI
port. If the value of this field is incorrect, the command
will not be properly received by the programming
executive.
DS70152D-page 48
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
TABLE 4-1:
PROGRAMMING EXECUTIVE COMMAND SET
Length
Opcode Mnemonic
Time Out
Description
(16-bit words)
0x0
0x1
SCHECK
READC
1
3
1 msec
1 msec
Sanity check.
Read an 8-bit word from the specified Configuration register or
Device ID register.
0x2
READP
4
1 msec/row Read ‘N’ 24-bit instruction words of code memory starting from
the specified address.
0x3
0x4
0x5
RESERVED
PROGC
N/A
4
N/A
This command is reserved. It will return a NACK.
5 msec
5 msec
Write an 8-bit word to the specified Configuration register.
PROGP
99
Program one row of code memory at the specified address,
then verify.
0x6
PROGW
5
5 msec
Program one instruction word of code memory at the specified
address, then verify.
0x7
0x8
0x9
0xA
0xB
0xC
0xD
RESERVED
RESERVED
RESERVED
QBLANK
N/A
N/A
N/A
2
N/A
N/A
This command is reserved. It will return a NACK.
This command is reserved. It will return a NACK.
This command is reserved. It will return a NACK.
Query if the code memory is blank.
N/A
TBD
1 msec
N/A
QVER
1
Query the programming executive software version.
This command is reserved. It will return a NACK.
This command is reserved. It will return a NACK.
RESERVED
RESERVED
N/A
N/A
N/A
Legend: TBD = To Be Determined
Note:
One row of code memory consists of (64) 24-bit words. Refer to Table 2-2 for device-specific information.
4.2.4
COMMAND DESCRIPTIONS
All commands supported by the programming executive
are described in Section 5.2.5 “SCHECK Command”
through Section 4.2.12 “QVER Command”.
4.2.5
15
SCHECKCOMMAND
12 11
0
Opcode
Length
Field
Description
Opcode
Length
0x0
0x1
The SCHECK command instructs the programming
executive to do nothing but generate a response. This
command is used as a “Sanity Check” to verify that the
programming executive is operational.
Expected Response (2 words):
0x1000
0x0002
Note:
This instruction is not required for
programming, but is provided for
development purposes only.
© 2007 Microchip Technology Inc.
Preliminary
DS70152D-page 49
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
4.2.6
15
READCCOMMAND
4.2.7
15
READPCOMMAND
12 11
8 7
0
12 11
8 7
0
Opcode
Length
Addr_MSB
Opcode
Length
Addr_MSB
N
N
Addr_LS
Reserved
Addr_LS
Field
Description
Field
Description
Opcode
Length
N
0x1
0x3
Opcode
Length
N
0x2
0x4
Number of 8-bit Configuration registers
or Device ID registers to read (max of
256)
Number of 24-bit instructions to read
(max of 32768)
Addr_MSB MSB of 24-bit source address
Reserved
Addr_MSB
Addr_LS
0x0
Addr_LS
Least Significant 16 bits of 24-bit
source address
MSB of 24-bit source address
Least Significant 16 bits of 24-bit
source address
The READCcommand instructs the programming exec-
utive to read N Configuration registers or Device ID
registers, starting from the 24-bit address specified by
Addr_MSB and Addr_LS. This command can only be
used to read 8-bit or 16-bit data.
The READPcommand instructs the programming exec-
utive to read N 24-bit words of code memory, starting
from the 24-bit address specified by Addr_MSB and
Addr_LS. This command can only be used to read 24-
bit data. All data returned in the response to this com-
mand uses the packed data format described in
Section 4.2.2 “Packed Data Format”.
When this command is used to read Configuration
registers, the upper byte in every data word returned by
the programming executive is 0x00 and the lower byte
contains the Configuration register value.
Expected Response (2 + 3 * N/2 words for N even):
0x1200
2 + 3 * N/2
Expected Response (4 + 3 * (N – 1)/2 words
for N odd):
0x1100
Least significant program memory word 1
2 + N
...
Configuration register or Device ID Register 1
Least significant data word N
...
Expected Response (4 + 3 * (N – 1)/2 words
for N odd):
Configuration register or Device ID Register N
0x1200
4 + 3 * (N – 1)/2
Least significant program memory word 1
...
Note:
Reading unimplemented memory will
cause the programming executive to
reset. Please ensure that only memory
locations present on a particular device
are accessed.
MSB of program memory word N (zero padded)
Note:
Reading unimplemented memory will
cause the programming executive to
reset. Please ensure that only memory
locations present on a particular device
are accessed.
DS70152D-page 50
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
4.2.8
15
PROGCCOMMAND
12 11 8 7
4.2.9
15
PROGPCOMMAND
12 11 8 7
0
0
Opcode
Length
Addr_MSB
Opcode
Length
Addr_MSB
Reserved
Reserved
Addr_LS
Data
Addr_LS
D_1
D_2
...
Field
Description
D_N
Opcode
Length
0x4
0x4
Field
Description
Reserved
0x0
Addr_MSB MSB of 24-bit destination address
Opcode
Length
0x5
Addr_LS
Data
Least Significant 16 bits of 24-bit
destination address
0x63
Reserved
Addr_MSB MSB of 24-bit destination address
0x0
8-bit data word
The PROGCcommand instructs the programming exec-
utive to program a single Configuration register, located
at the specified memory address.
Addr_LS
Least Significant 16 bits of 24-bit
destination address
D_1
D_2
...
16-bit data word 1
After the specified data word has been programmed to
code memory, the programming executive verifies the
programmed data against the data in the command.
16-bit data word 2
16-bit data word 3 through 95
16-bit data word 96
D_96
Expected Response (2 words):
The PROGPcommand instructs the programming exec-
utive to program one row of code memory
(64 instruction words) to the specified memory
address. Programming begins with the row address
specified in the command. The destination address
should be a multiple of 0x80.
0x1400
0x0002
The data to program to memory, located in command
words D_1 through D_96, must be arranged using the
packed instruction word format shown in Figure 4-4.
After all data has been programmed to code memory,
the programming executive verifies the programmed
data against the data in the command.
Expected Response (2 words):
0x1500
0x0002
Note:
Refer to Table 2-2 for code memory size
information.
© 2007 Microchip Technology Inc.
Preliminary
DS70152D-page 51
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
4.2.10
15
PROGWCOMMAND
12 11 8 7
4.2.11
15
QBLANKCOMMAND
0
12 11
0
Opcode
Length
Opcode
Length
Reserved
Addr_MSB
PSize
Addr_LS
Data_LS
Field
Description
Reserved
Data_MSB
Opcode
Length
PSize
0xA
0x2
Field
Description
Length of program memory to check
(in 24-bit words) +1, up to a max of
49152
Opcode
Length
0x6
0x5
The QBLANKcommand queries the programming exec-
utive to determine if the contents of code memory are
blank (contains all ‘1’s). The size of code memory to
check must be specified in the command.
Reserved
0x0
Addr_MSB MSB of 24-bit destination address
Addr_LS
Least Significant 16 bits of 24-bit
destination address
The Blank Check for code memory begins at 0x0 and
advances toward larger addresses for the specified
number of instruction words.
Data_MSB MSB of 24-bit data
Data_LS Least Significant 16 bits of 24-bit
data
QBLANK returns a QE_Code of 0xF0 if the specified
code memory and code-protect bits are blank;
otherwise, QBLANK returns a QE_Code of 0x0F.
The PROGWcommand instructs the programming exec-
utive to program one word of code memory (3 bytes) to
the specified memory address.
Expected Response (2 words for blank device):
After the word has been programmed to code memory,
the programming executive verifies the programmed
data against the data in the command.
0x1AF0
0x0002
Expected Response (2 words for non-blank device):
Expected Response (2 words):
0x1A0F
0x0002
0x1600
0x0002
Note:
The QBLANK command does not check
the system operation Configuration bits
since these bits are not set to ‘1’ when a
Chip Erase is performed.
DS70152D-page 52
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
4.2.12
15
QVERCOMMAND
4.3.1
RESPONSE FORMAT
All programming executive responses have a general
format consisting of a two-word header and any
required data for the command.
12 11
0
Opcode
Length
Field
Opcode
Length
Description
15
12 11
8
7
0
0xB
0x1
Opcode
Last_Cmd
Length
QE_Code
The QVER command queries the version of the
programming executive software stored in test
memory. The “version.revision” information is returned
in the response’s QE_Code using a single byte with the
following format: main version in upper nibble and
revision in the lower nibble (i.e., 0x23 means
version 2.3 of programming executive software).
D_1 (if applicable)
...
D_N (if applicable)
Expected Response (2 words):
Field
Description
Response opcode.
0x1BMN (where “MN” stands for version M.N)
0x0002
Opcode
Last_Cmd
Programmer command that
generated the response.
4.3
Programming Executive
Responses
QE_Code
Length
Query code or error code.
The programming executive sends a response to the
programmer for each command that it receives. The
response indicates if the command was processed
correctly. It includes any required response data or
error data.
Response length in 16-bit words
(includes 2 header words).
D_1
D_N
First 16-bit data word (if applicable).
Last 16-bit data word (if applicable).
The programming executive response set is shown in
Table 4-2. This table contains the opcode, mnemonic
and description for each response. The response format
is described in Section 4.3.1 “Response Format”.
4.3.1.1
Opcode Field
The opcode is a 4-bit field in the first word of the
response. The opcode indicates how the command
was processed (see Table 4-2). If the command was
processed successfully, the response opcode is PASS.
If there was an error in processing the command, the
response opcode is FAIL and the QE_Code indicates
the reason for the failure. If the command sent to
the programming executive is not identified, the
programming executive returns a NACK response.
TABLE 4-2:
PROGRAMMING EXECUTIVE
RESPONSE OPCODES
Opcode Mnemonic
Description
0x1
PASS
Command successfully
processed.
4.3.1.2
Last_Cmd Field
0x2
0x3
FAIL
Command unsuccessfully
processed.
The Last_Cmd is a 4-bit field in the first word of
the response and indicates the command that the
programming executive processed. Since the program-
ming executive can only process one command at a
time, this field is technically not required. However, it
can be used to verify that the programming executive
correctly received the command that the programmer
transmitted.
NACK
Command not known.
© 2007 Microchip Technology Inc.
Preliminary
DS70152D-page 53
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
4.3.1.3
QE_Code Field
TABLE 4-4:
QE_Code FOR NON-QUERY
COMMANDS
The QE_Code is a byte in the first word of the
response. This byte is used to return data for query
commands and error codes for all other commands.
QE_Code
Description
0x0
0x1
0x2
No error.
When the programming executive processes one of the
two query commands (QBLANKor QVER), the returned
opcode is always PASS and the QE_Code holds the
query response data. The format of the QE_Code for
both queries is shown in Table 4-3.
Verify failed.
Other error.
4.3.1.4
Response Length
The response length indicates the length of the
programming executive’s response in 16-bit words.
This field includes the 2 words of the response header.
TABLE 4-3:
Query
QE_Code FOR QUERIES
QE_Code
With the exception of the response for the READP
command, the length of each response is only 2 words.
QBLANK 0x0F = Code memory is NOT blank
0xF0 = Code memory is blank
The response to the READPcommand uses the packed
instruction word format described in Section 4.2.2
“Packed Data Format”. When reading an odd number
of program memory words (N odd), the response to the
READPcommand is (3 * (N + 1) / 2 + 2) words. When
reading an even number of program memory words
(N even), the response to the READPcommand is (3 *
N / 2 + 2) words.
QVER
0xMN, where programming executive
software version = M.N
(i.e., 0x32 means software version 3.2).
When the programming executive processes any
command other than a Query, the QE_Code repre-
sents an error code. Supported error codes are shown
in Table 4-4. If a command is successfully processed,
the returned QE_Code is set to 0x0, which indicates
that there was no error in the command processing. If
the verify of the programming for the PROGPor PROGC
command fails, the QE_Code is set to 0x1. For all other
programming executive errors, the QE_Code is 0x2.
DS70152D-page 54
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
FIGURE 5-1:
HIGH-LEVEL ICSP™
PROGRAMMING FLOW
5.0
DEVICE PROGRAMMING –
ICSP
ICSP mode is a special programming protocol that
allows you to read and write to dsPIC33F/PIC24H
device family memory. The ICSP mode is the most
direct method used to program the device; note, how-
ever, that Enhanced ICSP is faster. ICSP mode also
has the ability to read the contents of executive mem-
ory to determine if the programming executive is
present. This capability is accomplished by applying
control codes and instructions serially to the device
using pins PGC and PGD.
Start
Enter ICSP™
Perform Bulk
Erase
Program Memory
Verify Program
In ICSP mode, the system clock is taken from the PGC
pin, regardless of the device’s oscillator Configuration
bits. All instructions are shifted serially into an internal
buffer, then loaded into the instruction register and
executed. No program fetching occurs from internal
memory. Instructions are fed in 24 bits at a time. PGD
is used to shift data in, and PGC is used as both the
serial shift clock and the CPU execution clock.
Program Configuration Bits
Verify Configuration Bits
Note:
During ICSP operation, the operating
frequency of PGC must not exceed
5 MHz.
Exit ICSP
Done
5.1
Overview of the Programming
Process
Figure 5-1 shows the high-level overview of the
programming process. After entering ICSP mode, the
first action is to Bulk Erase the device. Next, the code
memory is programmed, followed by the device Con-
figuration registers. Code memory (including the
Configuration registers) is then verified to ensure that
programming was successful. Then, program the
code-protect Configuration bits, if required.
5.2
ICSP Operation
Upon entry into ICSP mode, the CPU is Idle. Execution
of the CPU is governed by an internal state machine. A
4-bit control code is clocked in using PGC and PGD and
this control code is used to command the CPU (see
Table 5-1).
The SIX control code is used to send instructions to the
CPU for execution and the REGOUT control code is
used to read data out of the device via the VISI register.
TABLE 5-1:
CPU CONTROL CODES IN
ICSP™ MODE
4-Bit
Control Code
Mnemonic
Description
0000b
SIX
Shift in 24-bit instruction
and execute.
0001b
REGOUT Shift out the VISI
register.
0010b-1111b N/A
Reserved.
© 2007 Microchip Technology Inc.
Preliminary
DS70152D-page 55
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
5.2.1
SIX SERIAL INSTRUCTION
EXECUTION
5.2.2
REGOUT SERIAL INSTRUCTION
EXECUTION
The SIX control code allows execution of dsPIC33F/
PIC24H Programming Specification assembly instruc-
tions. When the SIX code is received, the CPU is sus-
pended for 24 clock cycles, as the instruction is then
clocked into the internal buffer. Once the instruction is
shifted in, the state machine allows it to be executed over
the next four clock cycles. While the received instruction
is executed, the state machine simultaneously shifts in
the next 4-bit command (see Figure 5-2).
The REGOUT control code allows for data to be
extracted from the device in ICSP mode. It is used to
clock the contents of the VISI register out of the device
over the PGD pin. After the REGOUT control code is
received, the CPU is held Idle for 8 cycles. After these
eight cycles, an additional 16 cycles are required to clock
the data out (see Figure 5-3).
The REGOUT code is unique because the PGD pin is
an input when the control code is transmitted to the
device. However, after the control code is processed,
the PGD pin becomes an output as the VISI register is
shifted out.
Note 1: Coming out of Reset, the first 4-bit control
code is always forced to SIX and a forced
NOPinstruction is executed by the CPU.
Five additional PGC clocks are needed
on start-up, thereby resulting in a 9-bit
SIX command instead of the normal 4-bit
SIX command. After the forced SIX is
clocked in, ICSP operation resumes as
normal (the next 24 clock cycles load the
first instruction word to the CPU).
Note:
Data is transmitted on the falling edge and
latched on the rising edge of PGC. For all
data transmissions, the Least Significant
bit (LSb) is transmitted first.
2: TBLRDH, TBLRDL, TBLWTH and TBLWTL
instructions must be followed by a NOP
instruction.
FIGURE 5-2:
SIX SERIAL EXECUTION
P1
4
1
2
3
4
5
6
7
8
9
17
1
2
3
5
6
7
8
18 19 20 21 22 23 24
1
2
3
4
PGC
P4a
P4
P1A
P3
P1B
P2
PGD
LSB X
X
X
X
X
X
X
X
X
X
X
X
X
X MSB
0
0
0
0
0
0
0
0
0
0
0
0
0
Execute PC – 1,
Fetch SIX Control Code
24-Bit Instruction Fetch
Execute 24-Bit Instruction,
Fetch Next Control Code
Only for
Program
Memory Entry
PGD = Input
FIGURE 5-3:
REGOUT SERIAL EXECUTION
6
11 12 13 14
15
1
2
3
4
1
2
7
8
1
2
3
4
5
1
2
3
4
16
PGC
P4
P4a
P5
...
1
4
14
13
MSb
2
PGD
3
10
11 12
1
LSb
0
0
0
0
0
0
0
Execute Previous Instruction,
Fetch REGOUT Control Code
CPU Held in Idle
No Execution Takes Place,
Fetch Next Control Code
Shift Out VISI Register<15:0>
PGD = Output
PGD = Input
PGD = Input
DS70152D-page 56
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
The key sequence is a specific 32-bit pattern,
‘0100 1101 0100 0011 0100 1000 0101 0001’
(more easily remembered as 0x4D434851 in hexa-
decimal). The device will enter Program/Verify mode only
if the sequence is valid. The Most Significant bit (MSb) of
the most significant nibble must be shifted in first.
5.3
Entering ICSP Mode
As shown in Figure 5-4, entering ICSP Program/Verify
mode requires three steps:
1. MCLR is briefly driven high then low.
2. A 32-bit key sequence is clocked into PGD.
Once the key sequence is complete, VIH must be
applied to MCLR and held at that level for as long as
Program/Verify mode is to be maintained. An interval of
at least time P19 and P7 must elapse before presenting
data on PGD. Signals appearing on PGD before P7
has elapsed will not be interpreted as valid.
3. MCLR is then driven high within a specified
period of time and held.
The programming voltage applied to MCLR is VIH,
which is essentially VDD in the case of dsPIC33F/
PIC24H devices. There is no minimum time require-
ment for holding at VIH. After VIH is removed, an inter-
val of at least P18 must elapse before presenting the
key sequence on PGD.
On successful entry, the program memory can be
accessed and programmed in serial fashion. While
in ICSP mode, all unused I/Os are placed in the
high-impedance state.
FIGURE 5-4:
ENTERING ICSP™ MODE
P6
P19
P7
P14
VIH
VIH
MCLR
VDD
Program/Verify Entry Code = 0x4D434851
0
1
0
0
1
0
0
0
1
...
PGD
b31 b30 b29 b28 b27
b3
b2
b1
b0
PGC
P1A
P1B
P18
TABLE 5-2:
NVMCON ERASE
OPERATIONS
5.4
Flash Memory Programming in
ICSP Mode
NVMCON
Value
Erase Operation
5.4.1
PROGRAMMING OPERATIONS
Flash memory write and erase operations are controlled
by the NVMCON register. Programming is performed by
setting NVMCON to select the type of erase operation
(Table 5-2) or write operation (Table 5-3) and initiating
the programming by setting the WR control bit
(NVMCON<15>).
0x404F
Erase all code memory, executive memory
and Configuration registers (does not
erase Unit ID or Device ID registers).
0x404D
0x404C
Erase General Segment and FGS
Configuration register.
Erase Secure Segment and FSS
Configuration register. This operation will
also erase the General Segment and FGS
Configuration register.
In ICSP mode, all programming operations are self-
timed. There is an internal delay between the user set-
ting the WR control bit and the automatic clearing of the
WR control bit when the programming operation is
complete. Please refer to Section TABLE 8-1: “AC/
DC Characteristics and Timing Requirements” for
information about the delays associated with various
programming operations.
0x4042
0x4040
Erase a page of code memory or
executive memory.
Erase a Configuration register byte.
© 2007 Microchip Technology Inc.
Preliminary
DS70152D-page 57
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
If a Segment Erase operation is required, Step 3 must
be modified with the appropriate NVMCON value as
per Table 5-2.
TABLE 5-3:
NVMCON WRITE
OPERATIONS
NVMCON
Value
Write Operation
The ability to individually erase various segments is a
critical component of the CodeGuard™ Security fea-
tures on dsPIC33F/PIC24H devices. An individual
code segment may be erased without affecting other
segments. In addition, the Configuration register corre-
sponding to the erased code segment also gets
erased. For example, the user might want to erase the
code in the General Segment without erasing a Boot
Loader located in Boot Segment.
0x4001
Program 1 row (64 instruction words)
of code memory or executive memory.
0x4000
0x4003
Write a Configuration register byte.
Program a code memory word.
5.4.2
STARTING AND STOPPING A
PROGRAMMING CYCLE
The Secure Segment Erase command is used to erase
the Secure Segment and the FSS Configuration regis-
ter. The General Segment Erase command is used to
erase the General Segment and the FGS Configuration
register. This command is only effective if a Boot
Segment or Secure Segment has been enabled.
The WR bit (NVMCON<15>) is used to start an erase or
write cycle. Setting the WR bit initiates the programming
cycle.
All erase and write cycles are self-timed. The WR bit
should be polled to determine if the erase or write cycle
has been completed. Starting a programming cycle is
performed as follows:
Note 1: The Boot Segment and FBS Configura-
tion register can only be erased using a
Bulk Erase.
BSET
NVMCON, #WR
2: A Secure Segment Erase operation also
erases the General Segment and FGS
Configuration register. This is true even if
Secure Segment is present on a device
but not enabled.
5.5
Erasing Program Memory
The procedure for erasing program memory (all of code
memory, data memory, executive memory and code-
protect bits) consists of setting NVMCON to 0x404F
and then executing the programming cycle. For seg-
ment erase operations, the NVMCON value should be
modified suitably, according to Table 5-2.
Before performing any segment erase operation, the
programmer must first determine if the dsPIC33F/
PIC24H device has defined a Boot Segment or Secure
Segment, and ensure that a segment does not get
overwritten by operations on any other segment. Also,
a Bulk Erase should not be performed if a Boot
Figure 5-5 shows the ICSP programming process for
Bulk Erasing program memory. This process includes
the ICSP command code, which must be transmitted
(for each instruction) Least Significant bit first, using the
PGC and PGD pins (see Figure 5-2).
Segment or Secure Segment has been defined.
The BSS bit field in the FBS configuration register can
be read to determine whether a Boot Segment has
been defined. If a Boot Segment has already been
defined (and probably already been programmed), the
user must be warned about this fact. Similarly, the SSS
bit field in the FSS configuration register can be read to
determine whether a Secure Segment has been
defined. If a Secure Segment has already been defined
(and probably already been programmed), the user
must be warned about this fact.
Note:
Program memory must be erased before
writing any data to program memory.
FIGURE 5-5:
BULK ERASE FLOW
Start
Write 0x404F to NVMCON SFR
A Bulk Erase operation is the recommended mecha-
nism to allow a user to overwrite the Boot Segment (if
one chooses to do so).
Set the WR bit to Initiate Erase
Delay P11 + P10 Time
In general, the segments and CodeGuard Security-
related configuration registers should be programmed
in the following order:
• FBS and Boot Segment
• FSS and Secure Segment
• FGS and General Segment
Done
DS70152D-page 58
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
TABLE 5-4:
SERIAL INSTRUCTION EXECUTION FOR BULK ERASING CODE MEMORY
Command
(Binary)
Data
(Hex)
Description
Step 1: Exit the Reset vector.
0000
0000
0000
0000
000000
000000
040200
000000
NOP
NOP
GOTO
NOP
0x200
Step 2: Set the NVMCON to erase all program memory.
0000
0000
2404FA
883B0A
MOV
MOV
#0x404F, W10
W10, NVMCON
Step 3: Initiate the erase cycle.
0000
0000
0000
A8E761
000000
000000
BSET
NOP
NOP
NVMCON, #WR
Step 4: Wait for Bulk Erase operation to complete and make sure WR bit is clear.
-
-
Externally time ‘P11’ msec (see Section TABLE 8-1: “AC/DC
Characteristics and Timing Requirements”) to allow suffi-
cient time for the Bulk Erase operation to complete.
0000
0000
0000
0001
807600
887840
000000
<VISI>
MOV
MOV
NOP
NVMCON, W0
W0, VISI
Clock out contents of VISI register. Repeat until the WR bit
is clear.
code memory is programmed 64 instruction words at a
time, Steps 4 and 5 are repeated 16 times to load all the
write latches (Step 6).
5.6
Writing Code Memory
The procedure for writing code memory is similar to the
procedure for writing the Configuration registers,
except that 64 instruction words are programmed at a
time. To facilitate this operation, working registers,
W0:W5, are used as temporary holding registers for the
data to be programmed.
After the write latches are loaded, programming is
initiated by writing to the NVMCON register in Steps 7
and 8. In Step 9, the internal PC is reset to 0x200. This is
a precautionary measure to prevent the PC from incre-
menting into unimplemented memory when large
devices are being programmed. Lastly, in Step 10, Steps
3-9 are repeated until all of code memory is programmed.
Table 5-5 shows the ICSP programming details, includ-
ing the serial pattern with the ICSP command code,
which must be transmitted Least Significant bit first
using the PGC and PGD pins (see Figure 5-2). In Step
1, the Reset vector is exited. In Step 2, the NVMCON
register is initialized for programming of code memory.
In Step 3, the 24-bit starting destination address for
programming is loaded into the TBLPAG register and
W7 register. The upper byte of the starting destination
address is stored in TBLPAG and the lower 16 bits of
the destination address are stored in W7.
FIGURE 5-6:
PACKED INSTRUCTION
WORDS IN W0:W5
15
8
7
0
W0
LSW0
W1
W2
W3
W4
W5
MSB1
MSB3
MSB0
MSB2
LSW1
LSW2
To minimize the programming time, the same packed
instruction format that the programming executive uses
is utilized (Figure 4-4). In Step 4, four packed instruc-
tion words are stored in working registers, W0:W5,
using the MOVinstruction and the read pointer, W6, is
initialized. The contents of W0:W5 holding the packed
instruction word data are shown in Figure 5-6. In Step
5, eight TBLWTinstructions are used to copy the data
from W0:W5 to the write latches of code memory. Since
LSW3
© 2007 Microchip Technology Inc.
Preliminary
DS70152D-page 59
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
TABLE 5-5:
SERIAL INSTRUCTION EXECUTION FOR WRITING CODE MEMORY
Command
(Binary)
Data
(Hex)
Description
Step 1: Exit the Reset vector.
0000
0000
0000
0000
000000
000000
040200
000000
NOP
NOP
GOTO
NOP
0x200
Step 2: Set the NVMCON to program 64 instruction words.
0000
0000
24001A
883B0A
MOV
MOV
#0x4001, W10
W10, NVMCON
Step 3: Initialize the write pointer (W7) for TBLWTinstruction.
0000
0000
0000
200xx0
880190
2xxxx7
MOV
MOV
MOV
#<DestinationAddress23:16>, W0
W0, TBLPAG
#<DestinationAddress15:0>, W7
Step 4: Initialize the read pointer (W6) and load W0:W5 with the next 4 instruction words to program.
0000
0000
0000
0000
0000
0000
2xxxx0
2xxxx1
2xxxx2
2xxxx3
2xxxx4
2xxxx5
MOV
MOV
MOV
MOV
MOV
MOV
#<LSW0>, W0
#<MSB1:MSB0>, W1
#<LSW1>, W2
#<LSW2>, W3
#<MSB3:MSB2>, W4
#<LSW3>, W5
Step 5: Set the read pointer (W6) and load the (next set of) write latches.
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
EB0300
000000
BB0BB6
000000
000000
BBDBB6
000000
000000
BBEBB6
000000
000000
BB1BB6
000000
000000
BB0BB6
000000
000000
BBDBB6
000000
000000
BBEBB6
000000
000000
BB1BB6
000000
000000
CLR
NOP
W6
TBLWTL [W6++], [W7]
NOP
NOP
TBLWTH.B[W6++], [W7++]
NOP
NOP
TBLWTH.B[W6++], [++W7]
NOP
NOP
TBLWTL [W6++], [W7++]
NOP
NOP
TBLWTL [W6++], [W7]
NOP
NOP
TBLWTH.B[W6++], [W7++]
NOP
NOP
TBLWTH.B[W6++], [++W7]
NOP
NOP
TBLWTL [W6++], [W7++]
NOP
NOP
Step 6: Repeat steps 4-5 sixteen times to load the write latches for 64 instructions.
Step 7: Initiate the write cycle.
0000
0000
0000
A8E761
000000
000000
BSET
NOP
NOP
NVMCON, #WR
Step 8: Wait for Row Program operation to complete and make sure WR bit is clear.
DS70152D-page 60
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
TABLE 5-5:
SERIAL INSTRUCTION EXECUTION FOR WRITING CODE MEMORY (CONTINUED)
Command
(Binary)
Data
(Hex)
Description
-
-
Externally time ‘P13’ msec (see Section TABLE 8-1: “AC/DC
Characteristics and Timing Requirements”) to allow suffi-
cient time for the Row Program operation to complete.
0000
0000
0000
0001
807600
887840
000000
<VISI>
MOV
MOV
NOP
NVMCON, W0
W0, VISI
Clock out contents of VISI register. Repeat until the WR bit
is clear.
Step 9: Reset device internal PC.
0000
0000
040200
000000
GOTO
NOP
0x200
Step 10: Repeat steps 3-9 until all code memory is programmed.
FIGURE 5-7:
PROGRAM CODE MEMORY FLOW
Start
N = 1
LoopCount = 0
Configure
Device for
Writes
Load 2 Bytes
to Write
Buffer at <Addr>
N = N + 1
All
bytes
No
written?
Yes
N = 1
LoopCount =
LoopCount + 1
Start Write Sequence
and Poll for WR bit
to be cleared
All
locations
done?
No
Yes
Done
© 2007 Microchip Technology Inc.
Preliminary
DS70152D-page 61
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
TABLE 5-6:
DEFAULT CONFIGURATION
REGISTER VALUES FOR
dsPIC33FJ12GP201/202,
dsPIC33FJ12MC201/202 AND
PIC24HJ12GP201/202
5.7
Writing Configuration Memory
The 8-bit Configuration registers are programmable, one
register at a time. The default programming values rec-
ommended for the Configuration registers are shown in
Table 5-6 and Table 5-7. The recommended default
FOSCSEL value is 0x07, which selects the FRC clock
oscillator setting.
Address
Name
Default Value
0xF80000
0xF80002
0xF80004
0xF80006
0xF80008
0xF8000A
0xF8000C
0xF8000E
0xF80010
0xF80012
0xF80014
0xF80016
FBS
FSS
0xCF
0xFF
0x07
0xA7
0xE7
0xDF
0xF7
0xE3
0xFF
0xFF
0xFF
0xFF
The FBS, FSS and FGS Configuration registers are
special since they enable code protection for the
device. For security purposes, once any bit in these
registers is programmed to ‘0’ (to enable code protec-
tion), it can only be set back to ‘1’ by performing a Bulk
Erase as described in Section 5.5 “Erasing Program
Memory”. Programming any of these bits from a ‘0’ to
‘1’ is not possible, but they may be programmed from a
‘1’ to a ‘0’ to enable code protection.
FGS
FOSCSEL
FOSC
FWDT
FPOR
FICD
Table 5-8 shows the ICSP programming details for clear-
ing the Configuration registers. In Step 1, the Reset vec-
tor is exited. In Step 2, the write pointer (W7) is loaded
with 0x0000, which is the original destination address (in
TBLPAG, 0xF8 of program memory). In Step 3, the
NVMCON is set to program one Configuration register.
In Step 4, the TBLPAG register is initialized to 0xF8 for
writing to the Configuration registers. In Step 5, the value
to write to each Configuration register is loaded to W0.
In Step 6, the Configuration register data is written to the
write latch using the TBLWTLinstruction. In Steps 7 and
8, the programming cycle is initiated. In Step 9, the inter-
nal PC is set to 0x200 as a safety measure to prevent the
PC from incrementing into unimplemented memory.
Lastly, Steps 4-9 are repeated until all twelve
Configuration registers are written.
FUID0
FUID1
FUID2
FUID3
TABLE 5-7:
DEFAULT CONFIGURATION
REGISTER VALUES FOR ALL
OTHER DEVICES
Address
Name
Default Value
0xF80000
0xF80002
0xF80004
0xF80006
0xF80008
0xF8000A
0xF8000C
0xF8000E
0xF80010
0xF80012
0xF80014
0xF80016
FBS
FSS
0xCF
0xCF
0x07
0xA7
0xC7
0xDF
0xE7
0xE3
0xFF
0xFF
0xFF
0xFF
FGS
FOSCSEL
FOSC
FWDT
FPOR
FICD
FUID0
FUID1
FUID2
FUID3
DS70152D-page 62
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
TABLE 5-8:
SERIAL INSTRUCTION EXECUTION FOR WRITING CONFIGURATION REGISTERS
Command
(Binary)
Data
(Hex)
Description
Step 1: Exit the Reset vector.
0000
0000
0000
0000
000000
000000
040200
000000
NOP
NOP
GOTO
NOP
0x200
Step 2: Initialize the write pointer (W7) for the TBLWTinstruction.
0000 200007 MOV #0x0000, W7
Step 3: Set the NVMCON register to program one Configuration register.
0000
0000
24000A
883B0A
MOV
MOV
#0x4000, W10
W10, NVMCON
Step 4: Initialize the TBLPAG register.
0000
0000
200F80
880190
MOV
MOV
#0xF8, W0
W0, TBLPAG
Step 5: Load the Configuration register data to W6.
0000 2xxxx0 MOV #<CONFIG_VALUE>, W0
Step 6: Write the Configuration register data to the write latch and increment the write pointer.
0000
0000
0000
BB1B96
000000
000000
TBLWTL W0, [W7++]
NOP
NOP
Step 7: Initiate the write cycle.
0000
0000
0000
A8E761
000000
000000
BSET
NOP
NOP
NVMCON, #WR
Step 8: Wait for the Configuration Register Write operation to complete and make sure WR bit is clear.
-
-
Externally time ‘P20’ msec (see Section TABLE 8-1: “AC/DC
Characteristics and Timing Requirements”) to allow suffi-
cient time for the Configuration Register Write operation to
complete.
0000
0000
0000
0001
807600
887840
000000
<VISI>
MOV, NVMCON, W0
MOV
NOP
W0, VISI
Clock out contents of VISI register. Repeat until the WR bit
is clear.
Step 9: Reset device internal PC.
0000
0000
040200
000000
GOTO
NOP
0x200
Step 10: Repeat steps 5-9 until all twelve Configuration registers are written.
© 2007 Microchip Technology Inc.
Preliminary
DS70152D-page 63
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
To minimize the reading time, the packed instruction
5.8
Reading Code Memory
word format that was utilized for writing is also used for
reading (see Figure 5-6). In Step 3, the write pointer,
W7, is initialized. In Step 4, two instruction words are
read from code memory and clocked out of the device,
through the VISI register, using the REGOUTcommand.
Step 4 is repeated until the desired amount of code
memory is read.
Reading from code memory is performed by executing
a series of TBLRDinstructions and clocking out the data
using the REGOUTcommand.
Table 5-9 shows the ICSP programming details for
reading code memory. In Step 1, the Reset vector is
exited. In Step 2, the 24-bit starting source address for
reading is loaded into the TBLPAG register and W6
register. The upper byte of the starting source address
is stored in TBLPAG and the lower 16 bits of the source
address are stored in W6.
TABLE 5-9:
SERIAL INSTRUCTION EXECUTION FOR READING CODE MEMORY
Command
(Binary)
Data
(Hex)
Description
Step 1: Exit Reset vector.
0000
0000
0000
0000
000000
000000
040200
000000
NOP
NOP
GOTO
NOP
0x200
Step 2: Initialize TBLPAG and the read pointer (W6) for TBLRDinstruction.
0000
0000
0000
200xx0
880190
2xxxx6
MOV
MOV
MOV
#<SourceAddress23:16>, W0
W0, TBLPAG
#<SourceAddress15:0>, W6
Step 3: Initialize the write pointer (W7) to point to the VISI register.
0000
0000
207847
000000
MOV
NOP
#VISI, W7
Step 4: Read and clock out the contents of the next two locations of code memory, through the VISI register, using
the REGOUTcommand.
0000
0000
0000
0001
0000
0000
0000
0001
BA1B96
000000
000000
<VISI>
BA9BB6
000000
000000
<VISI>
TBLRDL [W6], [W7]
NOP
NOP
Clock out contents of VISI register
TBLRDH [W6++], [W7]
NOP
NOP
Clock out contents of VISI register
Step 5: Repeat step 4 until all desired code memory is read.
Step 6: Reset device internal PC.
0000
0000
040200
000000
GOTO
NOP
0x200
DS70152D-page 64
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
Table 5-10 shows the ICSP programming details for
reading all of configuration memory. Note that the
5.9
Reading Configuration Memory
The procedure for reading configuration memory is
similar to the procedure for reading code memory,
except that 16-bit data words are read (with the upper
byte read being all ‘0’s) instead of 24-bit words. Since
there are twelve Configuration registers, they are read
one register at a time.
TBLPAG register is hard coded to 0xF8 (the upper byte
address of configuration memory) and the read pointer,
W6, is initialized to 0x0000.
TABLE 5-10: SERIAL INSTRUCTION EXECUTION FOR READING ALL CONFIGURATION MEMORY
Command
(Binary)
Data
(Hex)
Description
Step 1: Exit Reset vector.
0000
0000
0000
0000
000000
000000
040200
000000
NOP
NOP
GOTO
NOP
0x200
Step 2: Initialize TBLPAG, the read pointer (W6) and the write pointer (W7) for TBLRDinstruction.
0000
0000
0000
0000
0000
200F80
880190
EB0300
207847
000000
MOV
MOV
CLR
MOV
NOP
#0xF8, W0
W0, TBLPAG
W6
#VISI, W7
Step 3: Read the Configuration register and write it to the VISI register (located at 0x784) and clock out the
VISI register using the REGOUTcommand.
0000
0000
0000
0001
BA0BB6
000000
000000
<VISI>
TBLRDL [W6++], [W7]
NOP
NOP
Clock out contents of VISI register
Step 4: Repeat step 3 twelve times to read all the Configuration registers.
Step 5: Reset device internal PC.
0000
0000
040200
000000
GOTO
NOP
0x200
© 2007 Microchip Technology Inc.
Preliminary
DS70152D-page 65
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
5.10 Verify Code Memory and
Configuration Word
5.11 Reading the Application ID Word
The Application ID Word is stored at address 0x8007F0
in executive code memory. To read this memory
location, you must use the SIX control code to move
this program memory location to the VISI register.
Then, the REGOUT control code must be used to clock
the contents of the VISI register out of the device. The
corresponding control and instruction codes that must
be serially transmitted to the device to perform this
operation are shown in Table 5-11.
The verify step involves reading back the code memory
space and comparing it against the copy held in the
programmer’s buffer. The Configuration registers are
verified with the rest of the code.
The verify process is shown in the flowchart in
Figure 5-8. Memory reads occur a single byte at a time,
so two bytes must be read to compare against the word
in the programmer’s buffer. Refer to Section 5.8
“Reading Code Memory” for implementation details
of reading code memory.
After the programmer has clocked out the Application
ID Word, it must be inspected. If the application ID has
the value 0xBB, the programming executive is resident
in memory and the device can be programmed using
the mechanism described in Section 3.0 “Device
Programming – Enhanced ICSP”. However, if the
application ID has any other value, the programming
executive is not resident in memory; it must be loaded
to memory before the device can be programmed. The
procedure for loading the programming executive to
memory is described in Section 6.0 “Programming
the Programming Executive to Memory”.
Note:
Because the Configuration registers
include the device code protection bit,
code memory should be verified immedi-
ately after writing if code protection is
enabled. This is because the device will
not be readable or verifiable if a device
Reset occurs after the code-protect bit in
the FGS Configuration register has been
cleared.
FIGURE 5-8:
VERIFY CODE
MEMORY FLOW
5.12 Exiting ICSP Mode
Exiting Program/Verify mode is done by removing VIH
from MCLR, as shown in Figure 5-9. The only require-
ment for exit is that an interval P16 should elapse
between the last clock and program signals on PGC
and PGD before removing VIH.
Start
Set TBLPTR = 0
FIGURE 5-9:
EXITING ICSP™ MODE
P16
P17
VIH
Read Low Byte
MCLR
with Post-Increment
VDD
Read High Byte
with Post-Increment
VIH
PGD
PGC
Does
Word = Expect
Data?
Failure,
Report
Error
No
PGD = Input
Yes
All
No
code memory
verified?
Yes
Done
DS70152D-page 66
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
TABLE 5-11: SERIAL INSTRUCTION EXECUTION FOR READING THE APPLICATION ID WORD
Command
(Binary)
Data
(Hex)
Description
Step 1: Exit Reset vector.
0000
0000
0000
0000
000000
000000
040200
000000
NOP
NOP
GOTO
NOP
0x200
Step 2: Initialize TBLPAG and the read pointer (W0) for TBLRDinstruction.
0000
0000
0000
0000
0000
0000
0000
0000
200800
880190
205FE0
207841
000000
BA0890
000000
000000
MOV
MOV
MOV
MOV
NOP
#0x80, W0
W0, TBLPAG
#0x5BE, W0
#VISI, W1
TBLRDL [W0], [W1]
NOP
NOP
Step 3: Output the VISI register using the REGOUTcommand.
0001
<VISI>
Clock out contents of the VISI register
© 2007 Microchip Technology Inc.
Preliminary
DS70152D-page 67
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
Storing the programming executive to executive
6.0
PROGRAMMING THE
PROGRAMMING EXECUTIVE
TO MEMORY
memory is similar to normal programming of code
memory. Namely, the executive memory must first be
erased, and then the programming executive must be
programmed 64 words at a time. This control flow is
summarized in Table 6-1.
6.1
Overview
If it is determined that the programming executive is not
present in executive memory (as described in
Section 3.2 “Confirming the Presence of the Pro-
gramming Executive”), it must be programmed into
executive memory using ICSP, as described in
Section 5.0 “Device Programming – ICSP”.
TABLE 6-1:
PROGRAMMING THE PROGRAMMING EXECUTIVE
Command
(Binary)
Data
(Hex)
Description
Step 1: Exit Reset vector and erase executive memory.
0000
0000
0000
0000
000000
000000
040200
000000
NOP
NOP
GOTO
NOP
0x200
Step 2: Initialize the NVMCON to erase a page of executive memory.
0000
0000
24072A
883B0A
MOV
MOV
#0x4042, W10
W10, NVMCON
Step 3: Initiate the erase cycle, wait for erase to complete and make sure WR bit is clear.
0000
0000
0000
-
A8E761
000000
000000
-
BSET
NOP
NOP
NVMCON, #15
Externally time ‘P12’ msec (see Section TABLE 8-1: “AC/DC
Characteristics and Timing Requirements”) to allow suffi-
cient time for the Page Erase operation to complete.
0000
0000
0000
0001
807600
887840
000000
<VISI>
MOV
MOV
NOP
NVMCON, W0
W0, VISI
Clock out contents of VISI register. Repeat until the WR bit
is clear.
Step 4: Repeat Step 3 four times to erase all four pages of executive memory.
Step 5: Initialize the NVMCON to program 64 instruction words.
0000
0000
24001A
883B0A
MOV
MOV
#0x4001, W10
W10, NVMCON
Step 6: Initialize TBLPAG and the write pointer (W7).
0000
0000
0000
0000
200800
880190
EB0380
000000
MOV
MOV
CLR
NOP
#0x80, W0
W0, TBLPAG
W7
DS70152D-page 68
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
TABLE 6-1:
PROGRAMMING THE PROGRAMMING EXECUTIVE (CONTINUED)
Command
(Binary)
Data
(Hex)
Description
Step 7: Load W0:W5 with the next 4 words of packed programming executive code and initialize W6 for
programming. Programming starts from the base of executive memory (0x800000) using W6 as a read
pointer and W7 as a write pointer.
0000
0000
0000
0000
0000
0000
2<LSW0>0
2<MSB1:MSB0>1 MOV
2<LSW1>2
2<LSW2>3
2<MSB3:MSB2>4 MOV
2<LSW3>5 MOV
MOV
#<LSW0>, W0
#<MSB1:MSB0>, W1
#<LSW1>, W2
#<LSW2>, W3
#<MSB3:MSB2>, W4
#<LSW3>, W5
MOV
MOV
Step 8: Set the read pointer (W6) and load the (next four write) latches.
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
EB0300
000000
BB0BB6
000000
000000
BBDBB6
000000
000000
BBEBB6
000000
000000
BB1BB6
000000
000000
BB0BB6
000000
000000
BBDBB6
000000
000000
BBEBB6
000000
000000
BB1BB6
000000
000000
CLR
NOP
W6
TBLWTL [W6++], [W7]
NOP
NOP
TBLWTH.B[W6++], [W7++]
NOP
NOP
TBLWTH.B[W6++], [++W7]
NOP
NOP
TBLWTL [W6++], [W7++]
NOP
NOP
TBLWTL [W6++], [W7]
NOP
NOP
TBLWTH.B[W6++], [W7++]
NOP
NOP
TBLWTH.B[W6++], [++W7]
NOP
NOP
TBLWTL [W6++], [W7++]
NOP
NOP
Step 9: Repeat Steps 7-8 sixteen times to load the write latches for the 64 instructions.
Step 10: Initiate the programming cycle.
0000
0000
0000
A8E761
000000
000000
BSET
NOP
NOP
NVMCON, #15
Step 11: Wait for the Row Program operation to complete.
-
-
Externally time ‘P13’ msec (see Section TABLE 8-1: “AC/DC
Characteristics and Timing Requirements”) to allow suffi-
cient time for the Page Erase operation to complete.
0000
0000
0000
0001
807600
887840
000000
<VISI>
MOV
MOV
NOP
NVMCON, W0
W0, VISI
Clock out contents of VISI register. Repeat until the WR bit
is clear.
© 2007 Microchip Technology Inc.
Preliminary
DS70152D-page 69
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
TABLE 6-1:
PROGRAMMING THE PROGRAMMING EXECUTIVE (CONTINUED)
Command
(Binary)
Data
(Hex)
Description
Step 12: Reset the device internal PC.
0000
0000
040200
000000
GOTO
NOP
0x200
Step 13: Repeat Steps 7-12 until all 32 rows of executive memory have been programmed.
DS70152D-page 70
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
Reading the contents of executive memory can be
performed using the same technique described in
6.2
Programming Verification
After the programming executive has been
programmed to executive memory using ICSP, it must
be verified. Verification is performed by reading out the
contents of executive memory and comparing it with
the image of the programming executive stored in the
programmer.
Section 5.8 “Reading Code Memory”. A procedure
for reading executive memory is shown in Table 6-2.
Note that in Step 2, the TBLPAG register is set to 0x80,
such that executive memory may be read.
TABLE 6-2:
READING EXECUTIVE MEMORY
Command
(Binary)
Data
(Hex)
Description
Step 1: Exit the Reset vector.
0000
0000
0000
0000
000000
000000
040200
000000
NOP
NOP
GOTO
NOP
0x200
Step 2: Initialize TBLPAG and the read pointer (W6) for TBLRDinstruction.
0000
0000
0000
200800
880190
EB0300
MOV
MOV
CLR
#0x80, W0
W0, TBLPAG
W6
Step 3: Initialize the write pointer (W7) to point to the VISI register.
0000 207847 MOV #VISI, W7
Step 4: Read and clock out the contents of the next two locations of executive memory through the VISI register
using the REGOUTcommand.
0000
0000
0000
0000
0001
0000
0000
0000
0001
000000
BA1B96
000000
000000
<VISI>
BA9BB6
000000
000000
<VISI>
NOP
TBLRDL [W6], [W7]
NOP
NOP
Clock out contents of VISI register
TBLRDH [W6++], [W7]
NOP
NOP
Clock out contents of VISI register
Step 5: Reset the device internal PC.
0000
0000
040200
000000
GOTO
NOP
0x200
Step 6: Repeat Steps 4-5 until all 2048 instruction words of executive memory are read.
© 2007 Microchip Technology Inc.
Preliminary
DS70152D-page 71
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
TABLE 7-1:
DEVICE IDs
7.0
DEVICE ID
Device
DEVID
DEVREV
The device ID region of memory can be used to
determine mask, variant and manufacturing
information about the chip. The device ID region is
2 x 16-bits and it can be read using the READC
command. This region of memory is read-only and can
also be read when code protection is enabled.
dsPIC33FJ64GP206
dsPIC33FJ64GP306
dsPIC33FJ64GP310
dsPIC33FJ64GP706
dsPIC33FJ64GP708
dsPIC33FJ64GP710
dsPIC33FJ128GP206
dsPIC33FJ128GP306
dsPIC33FJ128GP310
dsPIC33FJ128GP706
dsPIC33FJ128GP708
dsPIC33FJ128GP710
dsPIC33FJ256GP506
dsPIC33FJ256GP510
dsPIC33FJ256GP710
dsPIC33FJ64MC506
dsPIC33FJ64MC508
dsPIC33FJ64MC510
dsPIC33FJ64MC706
dsPIC33FJ64MC710
dsPIC33FJ128MC506
dsPIC33FJ128MC510
dsPIC33FJ128MC706
dsPIC33FJ128MC708
dsPIC33FJ128MC710
dsPIC33FJ256MC510
dsPIC33FJ256MC710
PIC24HJ64GP206
0xC1
0xCD
0xCF
0xD5
0xD6
0xD7
0xD9
0xE5
0xE7
0xED
0xEE
0xEF
0xF5
0xF7
0xFF
0x89
0x8A
0x8B
0x91
0x97
0xA1
0xA3
0xA9
0xAE
0xAF
0xB7
0xBF
0x41
0x47
0x49
0x4B
0x5D
0x5F
0x65
0x67
0x61
0x63
0x71
0x3000
0x3000
0x3000
0x3000
0x3000
0x3000
0x3000
0x3000
0x3000
0x3000
0x3000
0x3000
0x3000
0x3000
0x3000
0x3000
0x3000
0x3000
0x3000
0x3000
0x3000
0x3000
0x3000
0x3000
0x3000
0x3000
0x3000
0x3000
0x3000
0x3000
0x3000
0x3000
0x3000
0x3000
0x3000
0x3000
0x3000
0x3000
0x3000
0x3000
0x3000
0x3000
0x3000
0x3000
0x3000
0x3000
Table 7-1 shows the device ID for each device, Table 7-2
shows the Device ID registers and Table 7-3 describes
the bit field of each register.
PIC24HJ64GP210
PIC24HJ64GP506
PIC24HJ64GP510
PIC24HJ128GP206
PIC24HJ128GP210
PIC24HJ128GP306
PIC24HJ128GP310
PIC24HJ128GP506
PIC24HJ128GP510
PIC24HJ256GP206
PIC24HJ256GP210
PIC24HJ256GP610
dsPIC33FJ12GP201
dsPIC33FJ12GP202
dsPIC33FJ12MC201
dsPIC33FJ12MC202
PIC24HJ12GP201
0x73
0x7B
0x802
0x803
0x800
0x801
0x80A
0x80B
PIC24HJ12GP202
DS70152D-page 72
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
TABLE 7-2:
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION DEVICE ID REGISTERS
Bit
Address
Name
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0xFF0000
0xFF0002
DEVID
MASK<9:0>
PROC<3:0>
VARIANT<5:0>
DOT<5:0>
DEVREV
REV<5:0>
TABLE 7-3:
DEVICE ID BITS DESCRIPTION
Register
Bit Field
Description
MASK<9:0>
VARIANT<5:0>
PROC<3:0>
REV<5:0>
DEVID
Encodes the MASKSET ID of the device.
DEVID
Encodes the VARIANT derived from MASKSET of the device.
Encodes the process of the device.
DEVREV
DEVREV
DEVREV
Encodes the major revision number of the device.
Encodes the minor revision number of the device.
DOT<5:0>
© 2007 Microchip Technology Inc.
Preliminary
DS70152D-page 73
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
8.0
AC/DC CHARACTERISTICS
AND TIMING REQUIREMENTS
Table 8-1 lists AC/DC characteristics and timing
requirements.
TABLE 8-1:
AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS
Standard Operating Conditions
Operating Temperature: –40°C-85°C. Programming at 25°C is recommended.
Param
No.
Symbol
Characteristic
Min
Max
Units
Conditions
(1)
D111 VDD
D112 IPP
D113 IDDP
D031 VIL
D041 VIH
D080 VOL
D090 VOH
D012 CIO
D013 CF
Supply Voltage During Programming
Programming Current on MCLR
Supply Current During Programming
Input Low Voltage
VDDCORE
3.60
5
V
μA
mA
V
Normal programming
—
—
2
VSS
0.8 VDD
—
0.2 VDD
VDD
0.6
—
Input High Voltage
V
Output Low Voltage
V
IOL = 8.5 mA @ 3.6V
IOH = -3.0 mA @ 3.6V
Output High Voltage
VDD – 0.7
—
V
Capacitive Loading on I/O pin (PGD)
Filter Capacitor Value on VCAP
Serial Clock (PGC) Period
50
pF To meet AC specifications
1
10
μF Required for controller core
P1
TPGC
136
40
—
ns
ns
ns
ns
ns
ns
P1A
P1B
P2
TPGCL
TPGCH
TSET1
THLD1
TDLY1
Serial Clock (PGC) Low Time
Serial Clock (PGC) High Time
Input Data Setup Time to Serial Clock ↓
Input Data Hold Time from PGC ↓
—
40
—
15
—
P3
15
—
P4
Delay between 4-bit Command and
Command Operand
40
—
P4A
P5
TDLY1A Delay between Command Operand and
Next 4-bit Command
40
20
—
—
ns
ns
TDLY2
Delay between Last PGC ↓ of Command
to First PGC ↑ of Read of Data Word
P6
P7
P8
TSET2
THLD2
TDLY3
VDD ↑ Setup Time to MCLR ↑
100
25
—
—
—
ns
ms
μs
Input Data Hold Time from MCLR ↑
Delay between Last PGC ↓ of Command
Byte to PGD ↑ by Programming Executive
12
P9a
P9b
TDLY4
TDLY5
Programming Executive Command
Processing Time
10
15
—
μs
μs
Delay between PGD ↓ by Programming
Executive to PGD Released by
Programming Executive
23
P10
P11
P12
P13
P14
P15
P16
P17
TDLY6
TDLY7
TDLY8
TDLY9
TR
PGC Low Time After Programming
Bulk Erase Time
400
200
20
1.5
—
—
—
ns
ms
ms
ms
μs
ns
s
Page Erase Time
—
Row Programming Time
MCLR Rise Time to Enter ICSP mode
Data Out Valid from PGC ↑
—
1.0
—
TVALID
10
0
TDLY10 Delay between Last PGC ↓ and MCLR ↓
THLD3 MCLR ↓ to VDD ↓
—
—
100
ns
Note 1: VDD must also be supplied to the AVDD pins during programming. AVDD and AVSS should always be
within ±0.3V of VDD and VSS, respectively.
DS70152D-page 74
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
TABLE 8-1:
AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS (CONTINUED)
Standard Operating Conditions
Operating Temperature: –40°C-85°C. Programming at 25°C is recommended.
Param
No.
Symbol
Characteristic
Min
Max
Units
Conditions
P18
TKEY1
Delay from First MCLR ↓ to First PGC ↑ for
Key Sequence on PGD
40
—
ns
P19
P20
TKEY2
Delay from Last PGC ↓ for Key Sequence
on PGD to Second MCLR ↑
25
—
ns
TDLY11 Maximum Wait Time for Configuration
Register Programming
25
ms
Note 1: VDD must also be supplied to the AVDD pins during programming. AVDD and AVSS should always be
within ±0.3V of VDD and VSS, respectively.
© 2007 Microchip Technology Inc.
Preliminary
DS70152D-page 75
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
NOTES:
DS70152D-page 76
Preliminary
© 2007 Microchip Technology Inc.
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
APPENDIX A: REVISION HISTORY
Revision C (June 2006)
• Added code protection Configuration register
descriptions
• Added information about Unit ID
• Added ERASES, ERASEGand ERASEC
programming executive commands
• Added checksum computation equation
Revision D (March 2007)
• Added information specific to the
dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/
202 and PIC24HJ12GP201/202 devices in sev-
eral sections, including pinout diagrams, program
memory sizes and Device ID values
• Added specific checksum computations for all
dsPIC33F and PIC24H devices
• Updated ICSP bulk/page erase and row/byte pro-
gram code examples to show externally timed
operation (waiting for specific delay periods)
• Added the P20 timing characteristic
• Updated timing characteristics and references to
the timing characteristics
• Updated the ICSP code examples
© 2007 Microchip Technology Inc.
Preliminary
DS70152D-page 77
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
NOTES:
DS70152D-page 78
Preliminary
© 2007 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,
PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and
SmartShunt are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
AmpLab, FilterLab, Linear Active Thermistor, Migratable
Memory, MXDEV, MXLAB, PS logo, SEEVAL, SmartSensor
and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,
MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
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rfPICDEM, Select Mode, Smart Serial, SmartTel, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
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SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2007, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona, Gresham, Oregon and Mountain View, California. The
Company’s quality system processes and procedures are for its PIC®
MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial
EEPROMs, microperipherals, nonvolatile memory and analog
products. In addition, Microchip’s quality system for the design and
manufacture of development systems is ISO 9001:2000 certified.
© 2007 Microchip Technology Inc.
Preliminary
DS70152D-page 79
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Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
China - Shunde
Tel: 86-757-2839-5507
Fax: 86-757-2839-5571
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
China - Xian
Tel: 86-29-8833-7250
Fax: 86-29-8833-7256
12/08/06
DS70152D-page 80
Preliminary
© 2007 Microchip Technology Inc.
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