DSPIC33FJ12MC201TISO [MICROCHIP]
High-Performance, 16-bit Digital Signal Controllers; 高性能16位数字信号控制器型号: | DSPIC33FJ12MC201TISO |
厂家: | MICROCHIP |
描述: | High-Performance, 16-bit Digital Signal Controllers |
文件: | 总304页 (文件大小:4721K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
dsPIC33FJ12MC201/202
Data Sheet
High-Performance,
16-bit Digital Signal Controllers
© 2007-2011 Microchip Technology Inc.
DS70265E
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, chipKIT,
chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,
FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,
Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,
MPLINK, mTouch, Omniscient Code Generation, PICC,
PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,
rfLAB, Select Mode, Total Endurance, TSHARC,
UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2007-2011, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-61341-368-5
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS70265E-page 2
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
High-Performance, 16-bit Digital Signal Controllers
Operating Range:
Interrupt Controller:
• Up to 40 MIPS operation (at 3.0-3.6V):
• 5-cycle latency
- Industrial temperature range (-40°C to +85°C)
- Extended temperature range (-40°C to +125°C)
• Up to 26 available interrupt sources
• Up to three external interrupts
• Seven programmable priority levels
• Four processor exceptions
High-Performance DSC CPU:
• Modified Harvard architecture
• C compiler optimized instruction set
• 16-bit-wide data path
Digital I/O:
• Peripheral pin Select functionality
• 24-bit-wide instructions
• Up to 21 programmable digital I/O pins
• Wake-up/Interrupt-on-Change for up to 21 pins
• Output pins can drive from 3.0V to 3.6V
• Linear program memory addressing up to 4M
instruction words
• Linear data memory addressing up to 64 Kbytes
• 83 base instructions: mostly one word/one cycle
• Up to 5V output with open drain configurations on
5V tolerant pins
• Two 40-bit accumulators with rounding and
saturation options
• 4 mA sink on all I/O pins
• Flexible and powerful addressing modes:
- Indirect
On-Chip Flash and SRAM:
• Flash program memory (12 Kbytes)
• Data SRAM (1024 bytes)
- Modulo
- Bit-Reversed
• Boot and General Security for program Flash
• Software stack
• 16 x 16 fractional/integer multiply operations
• 32/16 and 16/16 divide operations
• Single-cycle multiply and accumulate:
- Accumulator write back for DSP operations
- Dual data fetch
System Management:
• Flexible clock options:
- External, crystal, resonator, internal RC
- Fully integrated Phase-Locked Loop (PLL)
- Extremely low-jitter PLL
• Up to ±16-bit shifts for up to 40-bit data
• Power-up Timer
• Oscillator Start-up Timer/Stabilizer
• Watchdog Timer with its own RC oscillator
• Fail-Safe Clock Monitor
Timers/Capture/Compare/PWM:
• Timer/Counters, up to three 16-bit timers
- Can pair up to make one 32-bit timer
• Reset by multiple sources
- One timer runs as Real-Time Clock with
external 32.768 kHz oscillator
Power Management:
- Programmable prescaler
• On-chip 2.5V voltage regulator
• Input Capture (up to four channels):
- Capture on up, down, or both edges
- 16-bit capture input functions
• Switch between clock sources in real time
• Idle, Sleep, and Doze modes with fast wake-up
- 4-deep FIFO on each capture
• Output Compare (up to two channels):
- Single or Dual 16-bit Compare mode
- 16-bit Glitchless PWM mode
© 2007-2011 Microchip Technology Inc.
DS70265E-page 3
dsPIC33FJ12MC201/202
Motor Control Peripherals:
CMOS Flash Technology:
• 6-channel 16-bit Motor Control PWM:
- Three duty cycle generators
• Low-power, high-speed Flash technology
• Fully static design
- Independent or Complementary mode
- Programmable dead time and output polarity
- Edge-aligned or center-aligned
- Manual output override control
- One Fault input
• 3.3V (±10%) operating voltage
• Industrial and Extended temperature
• Low power consumption
Communication Modules:
- Trigger for ADC conversions
• 4-wire SPI:
- PWM frequency for 16-bit resolution
(@ 40 MIPS) = 1220 Hz for Edge-Aligned
mode, 610 Hz for Center-Aligned mode
- Framing supports I/O interface to simple
codecs
- Supports 8-bit and 16-bit data
- PWM frequency for 11-bit resolution
(@ 40 MIPS) = 39.1 kHz for Edge-Aligned
mode, 19.55 kHz for Center-Aligned mode
- Supports all serial clock formats and
sampling modes
• I2C™:
• 2-channel 16-bit Motor Control PWM:
- One duty cycle generator
- Full Multi-Master Slave mode support
- 7-bit and 10-bit addressing
- Bus collision detection and arbitration
- Integrated signal conditioning
- Slave address masking
- Independent or Complementary mode
- Programmable dead time and output polarity
- Edge-aligned or center-aligned
- Manual output override control
- One Fault input
• UART:
- Interrupt on address bit detect
- Interrupt on UART error
- Trigger for ADC conversions
- PWM frequency for 16-bit resolution
(@ 40 MIPS) = 1220 Hz for Edge-Aligned
mode, 610 Hz for Center-Aligned mode
- Wake-up on Start bit from Sleep mode
- 4-character TX and RX FIFO buffers
- LIN bus support
- PWM frequency for 11-bit resolution
(@ 40 MIPS) = 39.1 kHz for Edge-Aligned
mode, 19.55 kHz for Center-Aligned mode
- IrDA® encoding and decoding in hardware
- High-Speed Baud mode
• Quadrature Encoder Interface module:
- Phase A, Phase B, and index pulse input
- 16-bit up/down position counter
- Hardware Flow Control with CTS and RTS
Packaging:
- Count direction status
• 20-pin PDIP/SOIC/SSOP
- Position Measurement (x2 and x4) mode
- Programmable digital noise filters on inputs
- Alternate 16-bit Timer/Counter mode
- Interrupt on position counter rollover/underflow
• 28-pin SPDIP/SOIC/SSOP/QFN
Note:
See Table 1 for the exact peripheral
features per device.
Analog-to-Digital Converters (ADCs):
• 10-bit, 1.1 Msps or 12-bit, 500 Ksps conversion:
- Two and four simultaneous samples (10-bit ADC)
- Up to six input channels with auto-scanning
- Conversion start can be manual or
synchronized with one of four trigger sources
- Conversion possible in Sleep mode
- ±2 LSb max integral nonlinearity
- ±1 LSb max differential nonlinearity
DS70265E-page 4
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
dsPIC33FJ12MC201/202 PRODUCT
FAMILIES
The device names, pin counts, memory sizes, and
peripheral availability of each device are listed in
Table 1. The following pages show their pinout
diagrams.
TABLE 1:
dsPIC33FJ12MC201/202 CONTROLLER FAMILIES
Remappable Peripherals
Device
Pins
(1)
(1)
(2)
10
16
dsPIC33FJ12MC201 20
dsPIC33FJ12MC202 28
12
12
1
1
3
3
4
4
2
2
4ch
2ch
1
1
1
1
1
1
1ADC,
4 ch
1
1
15 PDIP
SOIC
3
3
(2)
SSOP
(2)
(2)
6ch
2ch
1ADC.
6 ch
21 SPDIP
SOIC
SSOP
QFN
Note 1: Only two out of three timers are remappable.
2: Only PWM fault inputs are remappable.
3: Only two out of three interrupts are remappable.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 5
dsPIC33FJ12MC201/202
Pin Diagrams
= Pins are up to 5V tolerant
20-PIN PDIP, SOIC, SSOP
VDD
VSS
MCLR
1
20
19
18
17
16
15
14
13
12
11
PGED2/AN0/VREF+/CN2/RA0
2
(1)
PGEC2/AN1/VREF-/CN3/RA1
3
PWM1L1/RP15 /CN11/RB15
(1)
(1)
PGED1/AN2/RP0 /CN4/RB0
4
PWM1H1/RP14 /CN12/RB14
(1)
(1)
PGEC1/AN3/RP1 /CN5/RB1
5
PWM1L2/RP13 /CN13/RB13
(1)
PWM1H2/RP12 /CN14/RB12
SS
V
6
VCAP
OSC1/CLKI/CN30/RA2
OSC2/CLKO/CN29/RA3
7
(1)
PWM2L1/SDA1/RP9 /CN21/RB9
8
(1)
(1)
PGED3/SOSCI/RP4 /CN1/RB4
PWM2H1/SCL1/RP8 /CN22/RB8
9
(1)
PGEC3/SOSCO/T1CK/CN0/RA4
INT0/RP7 /CN23/RB7
10
= Pins are up to 5V tolerant
28-PIN SPDIP, SOIC, SSOP
MCLR
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AVDD
AVSS
PGED2/AN0/VREF+/CN2/RA0
2
(1)
PGEC2/AN1/VREF-/CN3/RA1
PWM1L1/RP15 /CN11/RB15
3
(1)
(1)
PGED1/AN2/RP0 /CN4/RB0
PWM1H1/RP14 /CN12/RB14
4
(1)
(1)
PGEC1/AN3/RP1 /CN5/RB1
PWM1L2/RP13 /CN13/RB13
5
(1)
(1)
PWM1H2/RP12 /CN14/RB12
AN4/RP2 /CN6/RB2
6
(1)
(1)
TMS/PWM1L3/RP11 /CN15/RB11
AN5/RP3 /CN7/RB3
7
(1)
VSS
OSC1/CLKI/CN30/RA2
OSC2/CLKO/CN29/RA3
TDI/PWM1H3/RP10 /CN16/RB10
8
VCAP
VSS
9
10
11
12
13
14
(1)
(1)
PGED3/SOSCI/RP4 /CN1/RB4
TDO/PWM2L1/SDA1/RP9 /CN21/RB9
(1)
PGEC3/SOSCO/T1CK/CN0/RA4
TCK/PWM2H1/SCL1/RP8 /CN22/RB8
(1)
VDD
INT0/RP7 /CN23/RB7
(1)
(1)
ASCL1/RP6 /CN24/RB6
ASDA1/RP5 /CN27/RB5
Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available
peripherals.
DS70265E-page 6
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
Pin Diagrams (Continued)
(2)
28-Pin QFN
= Pins are up to 5V tolerant
28 27 26 25
24 23 22
(1)
(1)
PGED1/AN2/RP0 /CN4/RB0
PWM1L2/RP13 /CN13/RB13
1
2
3
4
5
6
7
21
20
19
18
17
16
15
(1)
(1)
PGEC1/AN3/RP1 /CN5/RB1
PWM1H2/RP12 /CN14/RB12
(1)
(1)
AN4/RP2 /CN6/RB2
TMS/PWM1L3/RP11 /CN15/RB11
(1)
(1)
dsPIC33FJ12MC202
AN5/RP3 /CN7/RB3
TDI/PWM1H3/RP10 /CN16/RB10
VSS
VCAP
VSS
OSC1/CLKI/CN30/RA2
OSC2/CLKO/CN29/RA3
(1)
TDO/PWM2L1/SDA1/RP9 /CN21/RB9
8
9
10
11 12 13 14
Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available
peripherals.
2: The metal plane at the bottom of the device is not connected to any pins and is recommended to
be connected to VSS externally.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 7
dsPIC33FJ12MC201/202
Table of Contents
dsPIC33FJ12MC201/202 Product Families........................................................................................................................................... 5
1.0 Device Overview .......................................................................................................................................................................... 9
2.0 Guidelines for Getting Started with 16-bit Digital Signal Controllers .......................................................................................... 15
3.0 CPU............................................................................................................................................................................................ 19
4.0 Memory Organization................................................................................................................................................................. 31
5.0 Flash Program Memory.............................................................................................................................................................. 57
6.0 Resets ....................................................................................................................................................................................... 63
7.0 Interrupt Controller ..................................................................................................................................................................... 71
8.0 Oscillator Configuration............................................................................................................................................................ 103
9.0 Power-Saving Features............................................................................................................................................................ 113
10.0 I/O Ports ................................................................................................................................................................................... 119
11.0 Timer1 ...................................................................................................................................................................................... 141
12.0 Timer2/3 Feature ..................................................................................................................................................................... 143
13.0 Input Capture............................................................................................................................................................................ 149
14.0 Output Compare....................................................................................................................................................................... 151
15.0 Motor Control PWM Module..................................................................................................................................................... 155
16.0 Quadrature Encoder Interface (QEI) Module ........................................................................................................................... 169
17.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 173
18.0 Inter-Integrated Circuit™ (I2C™).............................................................................................................................................. 179
19.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 187
20.0 10-bit/12-bit Analog-to-Digital Converter (ADC)....................................................................................................................... 193
21.0 Special Features ...................................................................................................................................................................... 205
22.0 Instruction Set Summary.......................................................................................................................................................... 211
23.0 Development Support............................................................................................................................................................... 219
24.0 Electrical Characteristics.......................................................................................................................................................... 223
25.0 Packaging Information.............................................................................................................................................................. 271
Appendix A: Revision History............................................................................................................................................................. 287
Index ................................................................................................................................................................................................. 297
The Microchip Web Site..................................................................................................................................................................... 301
Customer Change Notification Service .............................................................................................................................................. 301
Customer Support.............................................................................................................................................................................. 301
Reader Response .............................................................................................................................................................................. 302
Product Identification System............................................................................................................................................................. 303
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department
via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150.
We welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
•
•
Microchip’s Worldwide Web site; http://www.microchip.com
Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
Customer Notification System
Register on our web site at www.microchip.com to receive the most current information on all of our products.
DS70265E-page 8
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
1.0
DEVICE OVERVIEW
Note 1: This data sheet summarizes the features
of the dsPIC33FJ12MC201/202 devices.
It is not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to the
“dsPIC33F/PIC24H Family Reference
Manual”. Please see the Microchip web
site (www.microchip.com) for the latest
dsPIC33F/PIC24H Family Reference
Manual sections.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
This document contains device specific information for
the dsPIC33FJ12MC201/202 Digital Signal Controller
(DSC) Devices. The dsPIC33F devices contain
extensive Digital Signal Processor (DSP) functionality
with a high-performance, 16-bit microcontroller (MCU)
architecture.
Figure 1-1 shows a general block diagram of the core
and peripheral modules in the dsPIC33FJ12MC201/
202 family of devices. Table 1-1 lists the functions of
the various pins shown in the pinout diagrams.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 9
dsPIC33FJ12MC201/202
FIGURE 1-1:
dsPIC33FJ12MC201/202 BLOCK DIAGRAM
PSV and Table
Data Access
Control Block
Y Data Bus
X Data Bus
Interrupt
Controller
PORTA
PORTB
16
16
16
8
16
Data Latch
Data Latch
X RAM
23
PCH PCL
Program Counter
Y RAM
PCU
23
Address
Latch
Address
Latch
Loop
Control
Logic
Stack
Control
Logic
16
23
16
16
Remappable
Pins
Address Generator Units
Address Latch
Program Memory
Data Latch
EA MUX
ROM Latch
24
16
16
Instruction
Decode and
Control
Instruction Reg
16
Control Signals
to Various Blocks
DSP Engine
16 x 16
W Register Array
Power-up
Timer
Timing
Generation
OSC2/CLKO
OSC1/CLKI
Divide Support
16
Oscillator
Start-up Timer
FRC/LPRC
Oscillators
Power-on
Reset
16-bit ALU
Precision
Band Gap
Reference
Watchdog
Timer
16
Brown-out
Reset
Voltage
Regulator
VCAP
VDD, VSS
MCLR
OC/
PWM1-2
PWM
2 Ch
Timers
1-3
UART1
ADC1
PWM
6 Ch
SPI1
IC1,2,7,8
QEI
CNx
I2C1
Note:
Not all pins or features are implemented on all device pinout configurations. See “Pin Diagrams” for the specific pins and features
present on each device.
DS70265E-page 10
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
TABLE 1-1:
Pin Name
AN0-AN5
PINOUT I/O DESCRIPTIONS
Pin
Type
Buffer
Type
PPS
Description
I
Analog
No Analog input channels.
CLKI
CLKO
I
O
ST/CMOS No External clock source input. Always associated with OSC1 pin function.
—
No Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in RC and EC modes. Always associated
with OSC2 pin function.
OSC1
OSC2
I
ST/CMOS No Oscillator crystal input. ST buffer when configured in RC mode; CMOS
otherwise.
I/O
—
No
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in RC and EC modes.
SOSCI
SOSCO
I
O
ST/CMOS No 32.768 kHz low-power oscillator crystal input; CMOS otherwise.
—
No 32.768 kHz low-power oscillator crystal output.
CN0-CN7
CN11-CN16
CN21-CN24
CN27
I
ST
No Change notification inputs.
No Can be software programmed for internal weak pull-ups on all inputs.
No
No
No
CN29-CN30
IC1-IC2
IC7-IC8
I
I
ST
ST
Yes Capture inputs 1/2.
Yes Capture inputs 7/8.
OCFA
OC1-OC2
I
O
ST
—
Yes Compare Fault A input (for Compare Channels 1 and 2).
Yes Compare outputs 1 through 2.
INT0
INT1
INT2
I
I
I
ST
ST
ST
No External interrupt 0.
Yes External interrupt 1.
Yes External interrupt 2.
RA0-RA4
I/O
I/O
ST
ST
No PORTA is a bidirectional I/O port.
No PORTB is a bidirectional I/O port.
RB0-RB15
T1CK
T2CK
T3CK
I
I
I
ST
ST
ST
No Timer1 external clock input.
Yes Timer2 external clock input.
Yes Timer3 external clock input.
I
O
I
ST
—
ST
—
Yes UART1 clear to send.
Yes UART1 ready to send.
Yes UART1 receive.
U1CTS
U1RTS
U1RX
U1TX
O
Yes UART1 transmit.
SCK1
SDI1
SDO1
I/O
I
O
ST
ST
—
Yes Synchronous serial clock input/output for SPI1.
Yes SPI1 data in.
Yes SPI1 data out.
I/O
ST
Yes SPI1 slave synchronization or frame pulse I/O.
SS1
SCL1
SDA1
ASCL1
ASDA1
I/O
I/O
I/O
I/O
ST
ST
ST
ST
No Synchronous serial clock input/output for I2C1.
No Synchronous serial data input/output for I2C1.
No Alternate synchronous serial clock input/output for I2C1.
No Alternate synchronous serial data input/output for I2C1.
TMS
TCK
TDI
I
I
I
ST
ST
ST
—
No JTAG Test mode select pin.
No JTAG test clock input pin.
No JTAG test data input pin.
No JTAG test data output pin.
TDO
O
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
PPS = Peripheral Pin Select
Analog = Analog input
O = Output
P = Power
I = Input
© 2007-2011 Microchip Technology Inc.
DS70265E-page 11
dsPIC33FJ12MC201/202
TABLE 1-1:
Pin Name
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin
Buffer
Type
PPS
Description
Type
INDX
QEA
I
I
ST
ST
Yes Quadrature Encoder Index Pulse input.
Yes Quadrature Encoder Phase A input in QEI mode.
Auxiliary Timer External Clock/Gate input in Timer mode.
Yes Quadrature Encoder Phase A input in QEI mode.
Auxiliary Timer External Clock/Gate input in Timer mode.
Yes Position Up/Down Counter Direction State.
QEB
I
ST
UPDN
O
CMOS
I
ST
—
—
—
—
—
—
ST
—
—
Yes PWM1 Fault A input.
No PWM1 Low output 1
No PWM1 High output 1
No PWM1 Low output 2
No PWM1 High output 2
No PWM1 Low output 3
No PWM1 High output 3
Yes PWM2 Fault A input.
No PWM2 Low output 1
No PWM2 High output 1
FLTA1
O
O
O
O
O
O
I
PWM1L1
PWM1H1
PWM1L2
PWM1H2
PWM1L3
PWM1H3
FLTA2
PWM2L1
PWM2H1
O
O
PGED1
PGEC1
PGED2
PGEC2
PGED3
PGEC3
I/O
ST
ST
ST
ST
ST
ST
No Data I/O pin for programming/debugging communication channel 1.
No Clock input pin for programming/debugging communication channel 1.
No Data I/O pin for programming/debugging communication channel 2.
No Clock input pin for programming/debugging communication channel 2.
No Data I/O pin for programming/debugging communication channel 3.
No Clock input pin for programming/debugging communication channel 3.
I
I/O
I
I/O
I
MCLR
AVDD
AVSS
VDD
I/P
P
P
P
P
P
I
ST
P
No Master Clear (Reset) input. This pin is an active-low Reset to the device.
No Positive supply for analog modules. This pin must be connected at all times.
No Ground reference for analog modules.
P
—
No Positive supply for peripheral logic and I/O pins.
No CPU logic filter capacitor connection.
VCAP
VSS
—
—
No Ground reference for logic and I/O pins.
VREF+
VREF-
Analog
Analog
No Analog voltage reference (high) input.
I
No Analog voltage reference (low) input.
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
PPS = Peripheral Pin Select
Analog = Analog input
O = Output
P = Power
I = Input
DS70265E-page 12
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
1.1
Referenced Sources
This device data sheet is based on the following
individual chapters of the “dsPIC33F/PIC24H Family
Reference Manual”. These documents should be
considered as the general reference for the operation
of a particular module or device feature.
Note 1: To access the documents listed below,
browse to the documentation section of
the dsPIC33FJ12MC202 product page of
the
Microchip
web
site
(www.microchip.com) or select a family
reference manual section from the
following list.
In addition to parameters, features, and
other documentation, the resulting page
provides links to the related family
reference manual sections.
• Section 1. “Introduction” (DS70197)
• Section 2. “CPU” (DS70204)
• Section 3. “Data Memory” (DS70202)
• Section 4. “Program Memory” (DS70202)
• Section 5. “Flash Programming” (DS70191)
• Section 6. “Interrupts” (DS70184)
• Section 7. “Oscillator” (DS70186)
• Section 8. “Reset” (DS70192)
• Section 9. “Watchdog Timer and Power-Saving Modes” (DS70196)
• Section 10. “I/O Ports” (DS70193)
• Section 11. “Timers” (DS70205)
• Section 12. “Input Capture” (DS70198)
• Section 13. “Output Compare” (DS70209)
• Section 14. “Motor Control PWM” (DS70187)
• Section 15. “Quadrature Encoder Interface (QEI)” (DS70208)
• Section 16. “Analog-to-Digital Converter (ADC)” (DS70183)
• Section 17. “UART” (DS70188)
• Section 18. “Serial Peripheral Interface (SPI)” (DS70206)
• Section 19. “Inter-Integrated Circuit™ (I2C™)” (DS70195)
• Section 23. “CodeGuard Security” (DS70199)
• Section 25. “Device Configuration” (DS70194)
© 2007-2011 Microchip Technology Inc.
DS70265E-page 13
dsPIC33FJ12MC201/202
NOTES:
DS70265E-page 14
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
2.2
Decoupling Capacitors
2.0
GUIDELINES FOR GETTING
STARTED WITH 16-BIT
DIGITAL SIGNAL
The use of decoupling capacitors on every pair of
power supply pins, such as VDD, VSS, AVDD, and
AVSS is required.
CONTROLLERS
Consider the following criteria when using decoupling
capacitors:
Note:
This data sheet summarizes the features
of the dsPIC33FJ12MC201/202 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the “dsPIC33F Family
Reference Manual”, which is available
• Value and type of capacitor: Recommendation
of 0.1 µF (100 nF), 10-20V. This capacitor should
be a low-ESR and have resonance frequency in
the range of 20 MHz and higher. It is
recommended that ceramic capacitors be used.
• Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is within
one-quarter inch (6 mm) in length.
from
the
Microchip
web
site
(www.microchip.com).
2.1
Basic Connection Requirements
Getting started with the dsPIC33FJ12MC201/202
family of 16-bit Digital Signal Controllers (DSC)
requires attention to a minimal set of device pin
connections before proceeding with development. The
following is a list of pin names, which must always be
connected:
• Handling high frequency noise: If the board is
experiencing high frequency noise, upward of
tens of MHz, add a second ceramic-type capacitor
in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 µF to 0.001 µF. Place this
second capacitor next to the primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible.
For example, 0.1 µF in parallel with 0.001 µF.
• All VDD and VSS pins
(see Section 2.2 “Decoupling Capacitors”)
• All AVDD and AVSS pins (regardless if ADC module
is not used)
(see Section 2.2 “Decoupling Capacitors”)
• VCAP
(see Section 2.3 “CPU Logic Filter Capacitor
Connection (VCAP)”)
• MCLR pin
(see Section 2.4 “Master Clear (MCLR) Pin”)
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum thereby reducing PCB track inductance.
• PGECx/PGEDx pins used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes
(see Section 2.5 “ICSP Pins”)
• OSC1 and OSC2 pins when external oscillator
source is used
(see Section 2.6 “External Oscillator Pins”)
Additionally, the following pins may be required:
• VREF+/VREF- pins used when external voltage
reference for ADC module is implemented
Note:
The AVDD and AVSS pins must be
connected independent of the ADC
voltage reference source.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 15
dsPIC33FJ12MC201/202
FIGURE 2-1:
RECOMMENDED
MINIMUM CONNECTION
2.4
Master Clear (MCLR) Pin
The MCLR pin provides for two specific device
functions:
10 µF
0.1 µF
Ceramic
• Device Reset
Tantalum
MCLR
VDD
• Device programming and debugging
During device programming and debugging, the
resistance and capacitance that can be added to the
pin must be considered. Device programmers and
debuggers drive the MCLR pin. Consequently,
specific voltage levels (VIH and VIL) and fast signal
transitions must not be adversely affected. Therefore,
specific values of R and C will need to be adjusted
based on the application and PCB requirements.
R
R1
C
dsPIC33F
VDD
VSS
VDD
For example, as shown in Figure 2-2, it is
recommended that the capacitor C, be isolated from
the MCLR pin during programming and debugging
operations.
VSS
0.1 µF
Ceramic
0.1 µF
Ceramic
0.1 µF
0.1 µF
Ceramic
Ceramic
Place the components shown in Figure 2-2 within
one-quarter inch (6 mm) from the MCLR pin.
10 Ω
FIGURE 2-2:
EXAMPLE OF MCLR PIN
CONNECTIONS
2.2.1
TANK CAPACITORS
On boards with power traces running longer than six
inches in length, it is suggested to use a tank capacitor
for integrated circuits including DSCs to supply a local
power source. The value of the tank capacitor should
be determined based on the trace resistance that con-
nects the power supply source to the device, and the
maximum current drawn by the device in the applica-
tion. In other words, select the tank capacitor so that it
meets the acceptable voltage sag at the device. Typical
values range from 4.7 µF to 47 µF.
VDD
R
R1
MCLR
dsPIC33F
JP
C
2.3
CPU Logic Filter Capacitor
Connection (VCAP)
Note 1: R ≤ 10 kΩ is recommended. A suggested
starting value is 10 kΩ. Ensure that the MCLR
pin VIH and VIL specifications are met.
A low-ESR (< 5 Ohms) capacitor is required on the
VCAP pin, which is used to stabilize the voltage
regulator output voltage. The VCAP pin must not be
connected to VDD, and must have a capacitor between
4.7 µF and 10 µF, 16V connected to ground. The type
can be ceramic or tantalum. Refer to Section 24.0
2: R1 ≤ 470Ω will limit any current flowing into
MCLR from the external capacitor C, in the
event of MCLR pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR pin
VIH and VIL specifications are met.
“Electrical
Characteristics”
for
additional
information.
The placement of this capacitor should be close to the
VCAP. It is recommended that the trace length not
exceed one-quarter inch (6 mm). Refer to Section 21.2
“On-Chip Voltage Regulator” for details.
DS70265E-page 16
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
2.5
ICSP Pins
2.6
External Oscillator Pins
The PGECx and PGEDx pins are used for In-Circuit
Serial Programming™ (ICSP™) and debugging pur-
poses. It is recommended to keep the trace length
between the ICSP connector and the ICSP pins on the
device as short as possible. If the ICSP connector is
expected to experience an ESD event, a series resistor
is recommended, with the value in the range of a few
tens of Ohms, not to exceed 100 Ohms.
Many DSCs have options for at least two oscillators: a
high-frequency primary oscillator and a low-frequency
secondary oscillator (refer to Section 8.0 “Oscillator
Configuration” for details).
The oscillator circuit should be placed on the same
side of the board as the device. Also, place the
oscillator circuit close to the respective oscillator pins,
not exceeding one-half inch (12 mm) distance
between them. The load capacitors should be placed
next to the oscillator itself, on the same side of the
board. Use a grounded copper pour around the
oscillator circuit to isolate them from surrounding
circuits. The grounded copper pour should be routed
directly to the MCU ground. Do not run any signal
traces or power traces inside the ground pour. Also, if
using a two-sided board, avoid any traces on the
other side of the board where the crystal is placed. A
suggested layout is shown in Figure 2-3.
Pull-up resistors, series diodes, and capacitors on the
PGECx and PGEDx pins are not recommended as they
will interfere with the programmer/debugger communi-
cations to the device. If such discrete components are
an application requirement, they should be removed
from the circuit during programming and debugging.
Alternately, refer to the AC/DC characteristics and tim-
ing requirements information in the respective device
Flash programming specification for information on
capacitive loading limits and pin input voltage high (VIH)
and input low (VIL) requirements.
FIGURE 2-3:
SUGGESTED PLACEMENT
OF THE OSCILLATOR
CIRCUIT
Ensure that the “Communication Channel Select” (i.e.,
PGECx/PGEDx pins) programmed into the device
matches the physical connections for the ICSP to
MPLAB® ICD 2, MPLAB ICD 3, or MPLAB REAL
ICE™.
Main Oscillator
Guard Ring
For more information on ICD 2, ICD 3, and REAL ICE
connection requirements, refer to the following
documents that are available on the Microchip web
site.
• “MPLAB® ICD 2 In-Circuit Debugger User’s
Guide” DS51331
• “Using MPLAB® ICD 2” (poster) DS51265
• “MPLAB® ICD 2 Design Advisory” DS51566
• “Using MPLAB® ICD 3” (poster) DS51765
• “MPLAB® ICD 3 Design Advisory” DS51764
13
14
15
16
17
18
19
20
Guard Trace
Secondary
Oscillator
• “MPLAB® REAL ICE™ In-Circuit Debugger
User’s Guide” DS51616
• “Using MPLAB® REAL ICE™” (poster) DS51749
© 2007-2011 Microchip Technology Inc.
DS70265E-page 17
dsPIC33FJ12MC201/202
2.7
Oscillator Value Conditions on
Device Start-up
2.9
Unused I/Os
Unused I/O pins should be configured as outputs and
driven to a logic-low state.
If the PLL of the target device is enabled and
configured for the device start-up oscillator, the
maximum oscillator source frequency must be limited
to 4 MHz < FIN < 8 MHz to comply with device PLL
start-up conditions. This means that if the external
oscillator frequency is outside this range, the
application must start-up in the FRC mode first. The
default PLL settings after a POR with an oscillator
frequency outside this range will violate the device
operating speed.
Alternately, connect a 1k to 10k resistor between VSS
and unused pins and drive the output to logic low.
Once the device powers up, the application firmware
can initialize the PLL SFRs, CLKDIV, and PLLDBF to a
suitable value, and then perform a clock switch to the
Oscillator + PLL clock source. Note that clock switching
must be enabled in the device Configuration word.
2.8
Configuration of Analog and
Digital Pins During ICSP
Operations
If MPLAB ICD 2, MPLAB ICD 3, or MPLAB REAL ICE
in-circuit emulator is selected as a debugger, it
automatically initializes all of the A/D input pins (ANx)
as “digital” pins, by setting all bits in the AD1PCFGL
register.
The bits in the register that correspond to the A/D pins
that are initialized by MPLAB ICD 2, MPLAB ICD 3, or
MPLAB REAL ICE in-circuit emulator, must not be
cleared by the user application firmware; otherwise,
communication errors will result between the debugger
and the device.
If your application needs to use certain A/D pins as
analog input pins during the debug session, the user
application must clear the corresponding bits in the
AD1PCFGL register during initialization of the ADC
module.
When MPLAB ICD 2, MPLAB ICD 3, or MPLAB REAL
ICE in-circuit emulator is used as a programmer, the
user application firmware must correctly configure the
AD1PCFGL register. Automatic initialization of this
register is only done during debugger operation.
Failure to correctly configure the register(s) will result in
all A/D pins being recognized as analog input pins,
resulting in the port value being read as a logic ‘0’,
which may affect user application functionality.
DS70265E-page 18
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
3.1
Data Addressing Overview
3.0
CPU
The data space can be addressed as 32K words or
64 Kbytes and is split into two blocks, referred to as X
and Y data memory. Each memory block has its own
independent Address Generation Unit (AGU). The
MCU class of instructions operates solely through the
X memory AGU, which accesses the entire memory
map as one linear data space. Certain DSP instructions
operate through the X and Y AGUs to support dual
operand reads, which splits the data address space
into two parts. The X and Y data space boundary is
device-specific.
Note 1: This data sheet summarizes the features
of the dsPIC33FJ12MC201/202 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 2. “CPU”
(DS70204) of the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microchip website
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Overhead-free circular buffers (Modulo Addressing
mode) are supported in both X and Y address spaces.
The Modulo Addressing removes the software
boundary checking overhead for DSP algorithms.
Furthermore, the X AGU circular addressing can be
used with any of the MCU class of instructions. The X
AGU also supports Bit-Reversed Addressing to greatly
simplify input or output data reordering for radix-2 FFT
algorithms.
The dsPIC33FJ12MC201/202 CPU module has a 16-
bit (data) modified Harvard architecture with an
enhanced instruction set, including significant support
for DSP. The CPU has a 24-bit instruction word with a
variable length opcode field. The Program Counter
(PC) is 23 bits wide and addresses up to 4M x 24 bits
of user program memory space. The actual amount of
program memory implemented varies by device. A
single-cycle instruction prefetch mechanism is used to
help maintain throughput and provides predictable
execution. All instructions execute in a single cycle,
with the exception of instructions that change the
program flow, the double-word move (MOV.D)
instruction and the table instructions. Overhead-free
program loop constructs are supported using the DO
and REPEAT instructions, both of which are
interruptible at any point.
The upper 32 Kbytes of the data space memory map
can optionally be mapped into program space at any
16K program word boundary defined by the 8-bit
Program Space Visibility Page (PSVPAG) register. The
program-to-data-space mapping feature lets any
instruction access program space as if it were data
space.
3.2
DSP Engine Overview
The DSP engine features a high-speed 17-bit by 17-bit
multiplier, 40-bit ALU, two 40-bit saturating
a
accumulators, and a 40-bit bidirectional barrel shifter.
The barrel shifter is capable of shifting a 40-bit value up
to 16 bits right or left, in a single cycle. The DSP instruc-
tions operate seamlessly with all other instructions and
have been designed for optimal real-time performance.
The MAC instruction and other associated instructions
can concurrently fetch two data operands from mem-
ory, while multiplying two W registers and accumulating
and optionally saturating the result in the same cycle.
This instruction functionality requires that the RAM data
space be split for these instructions and linear for all
others. Data space partitioning is achieved in a trans-
parent and flexible manner through dedicating certain
working registers to each address space.
The dsPIC33FJ12MC201/202 devices have sixteen,
16-bit working registers in the programmer’s model.
Each of the working registers can serve as a data,
address, or address offset register. The 16th working
register (W15) operates as a software Stack Pointer
(SP) for interrupts and calls.
There are two classes of instruction in the
dsPIC33FJ12MC201/202 devices: MCU and DSP.
These two instruction classes are seamlessly
integrated into a single CPU. The instruction set
includes many addressing modes and is designed for
optimum C compiler efficiency. For most instructions,
dsPIC33FJ12MC201/202 devices are capable of exe-
cuting a data (or program data) memory read, a work-
ing register (data) read, a data memory write, and a
program (instruction) memory read per instruction
cycle. As a result, three parameter instructions can be
supported, allowing A + B = C operations to be
executed in a single cycle.
3.3
Special MCU Features
The dsPIC33FJ12MC201/202 features a 17-bit by 17-
bit single-cycle multiplier that is shared by both the
MCU ALU and DSP engine. The multiplier can perform
signed, unsigned and mixed-sign multiplication. Using
a 17-bit by 17-bit multiplier for 16-bit by 16-bit
multiplication not only allows you to perform mixed-sign
multiplication, it also achieves accurate results for
special operations, such as (-1.0) x (-1.0).
A block diagram of the CPU is shown in Figure 3-1, and
the programmer’s model for the dsPIC33FJ12MC201/
202 is shown in Figure 3-2.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 19
dsPIC33FJ12MC201/202
The dsPIC33FJ12MC201/202 supports 16/16 and 32/
16 divide operations, both fractional and integer. All
divide instructions are iterative operations. They must
be executed within a REPEATloop, resulting in a total
execution time of 19 instruction cycles. The divide
operation can be interrupted during any of those
19 cycles without loss of data.
A 40-bit barrel shifter is used to perform up to a 16-bit
left or right shift in a single cycle. The barrel shifter can
be used by both MCU and DSP instructions.
FIGURE 3-1:
dsPIC33FJ12MC201/202 CPU CORE BLOCK DIAGRAM
PSV and Table
Data Access
Control Block
Y Data Bus
X Data Bus
Interrupt
Controller
16
Data Latch
16
16
8
16
Data Latch
23
16
PCH PCL
Program Counter
PCU
X RAM
Y RAM
23
Address
Latch
Address
Latch
Loop
Control
Logic
Stack
Control
Logic
23
16
16
Address Generator Units
Address Latch
Program Memory
Data Latch
EA MUX
ROM Latch
24
16
16
Instruction
Decode and
Control
Instruction Reg
Control Signals
to Various Blocks
16
DSP Engine
16 x 16
W Register Array
Divide Support
16
16-bit ALU
16
To Peripheral Modules
DS70265E-page 20
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
FIGURE 3-2:
dsPIC33FJ12MC201/202 PROGRAMMER’S MODEL
D15
D0
W0/WREG
W1
PUSH.SShadow
DOShadow
W2
W3
Legend
W4
DSP Operand
Registers
W5
W6
W7
Working Registers
W8
W9
DSP Address
Registers
W10
W11
W12/DSP Offset
W13/DSP Write Back
W14/Frame Pointer
W15/Stack Pointer
SPLIM
Stack Pointer Limit Register
AD15
AD39
ACCA
AD31
AD0
DSP
Accumulators
ACCB
PC22
PC0
0
Program Counter
0
7
TBLPAG
Data Table Page Address
7
0
PSVPAG
Program Space Visibility Page Address
15
0
0
RCOUNT
REPEATLoop Counter
DOLoop Counter
15
DCOUNT
22
0
DOSTART
DOEND
DOLoop Start Address
DOLoop End Address
22
15
0
Core Configuration Register
CORCON
OA OB SA SB OAB SAB DA DC
SRH
IPL0 RA
N
OV
Z
C
IPL2 IPL1
STATUS Register
SRL
© 2007-2011 Microchip Technology Inc.
DS70265E-page 21
dsPIC33FJ12MC201/202
3.4
CPU Control Registers
REGISTER 3-1:
SR: CPU STATUS REGISTER
R-0
OA
R-0
OB
R/C-0
SA(1)
R/C-0
SB(1)
R-0
R/C-0
SAB
R -0
DA
R/W-0
DC
OAB
bit 15
bit 8
R/W-0(2)
R/W-0(3)
IPL<2:0>(2)
R/W-0(3)
R-0
RA
R/W-0
N
R/W-0
OV
R/W-0
Z
R/W-0
C
bit 7
bit 0
Legend:
C = Clear only bit
S = Set only bit
‘1’ = Bit is set
R = Readable bit
W = Writable bit
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n = Value at POR
x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
OA: Accumulator A Overflow Status bit
1= Accumulator A overflowed
0= Accumulator A has not overflowed
OB: Accumulator B Overflow Status bit
1= Accumulator B overflowed
0= Accumulator B has not overflowed
SA: Accumulator A Saturation ‘Sticky’ Status bit(1)
1= Accumulator A is saturated or has been saturated at some time
0= Accumulator A is not saturated
SB: Accumulator B Saturation ‘Sticky’ Status bit(1)
1= Accumulator B is saturated or has been saturated at some time
0= Accumulator B is not saturated
OAB: OA || OB Combined Accumulator Overflow Status bit
1= Accumulators A or B have overflowed
0= Neither Accumulators A or B have overflowed
SAB: SA || SB Combined Accumulator ‘Sticky’ Status bit
1= Accumulators A or B are saturated or have been saturated at some time in the past
0= Neither Accumulator A or B are saturated
This bit may be read or cleared (not set). Clearing this bit will clear SA and SB.
bit 9
bit 8
DA: DOLoop Active bit
1= DOloop in progress
0= DOloop not in progress
DC: MCU ALU Half Carry/Borrow bit
1= A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)
of the result occurred
0= No carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized
data) of the result occurred
Note 1: This bit can be read or cleared (not set).
2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
3: The IPL<2:0> Status bits are read-only when NSTDIS = 1(INTCON1<15>).
DS70265E-page 22
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
REGISTER 3-1:
SR: CPU STATUS REGISTER (CONTINUED)
bit 7-5
IPL<2:0>: CPU Interrupt Priority Level Status bits(2)
111= CPU Interrupt Priority Level is 7 (15), user interrupts disabled
110= CPU Interrupt Priority Level is 6 (14)
101= CPU Interrupt Priority Level is 5 (13)
100= CPU Interrupt Priority Level is 4 (12)
011= CPU Interrupt Priority Level is 3 (11)
010= CPU Interrupt Priority Level is 2 (10)
001= CPU Interrupt Priority Level is 1 (9)
000= CPU Interrupt Priority Level is 0 (8)
bit 4
bit 3
bit 2
RA: REPEATLoop Active bit
1= REPEATloop in progress
0= REPEATloop not in progress
N: MCU ALU Negative bit
1= Result was negative
0= Result was non-negative (zero or positive)
OV: MCU ALU Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of a magnitude that
causes the sign bit to change state.
1= Overflow occurred for signed arithmetic (in this arithmetic operation)
0= No overflow occurred
bit 1
bit 0
Z: MCU ALU Zero bit
1= An operation that affects the Z bit has set it at some time in the past
0= The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result)
C: MCU ALU Carry/Borrow bit
1= A carry-out from the Most Significant bit of the result occurred
0= No carry-out from the Most Significant bit of the result occurred
Note 1: This bit can be read or cleared (not set).
2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
3: The IPL<2:0> Status bits are read-only when NSTDIS = 1(INTCON1<15>).
© 2007-2011 Microchip Technology Inc.
DS70265E-page 23
dsPIC33FJ12MC201/202
REGISTER 3-2:
CORCON: CORE CONTROL REGISTER
U-0
—
U-0
—
U-0
—
R/W-0
US
R/W-0
EDT(1)
R-0
R-0
R-0
DL<2:0>
bit 15
bit 8
R/W-0
SATA
R/W-0
SATB
R/W-1
R/W-0
R/C-0
IPL3(2)
R/W-0
PSV
R/W-0
RND
R/W-0
IF
SATDW
ACCSAT
bit 7
bit 0
Legend:
C = Clear only bit
W = Writable bit
‘x = Bit is unknown
R = Readable bit
0’ = Bit is cleared
-n = Value at POR
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
bit 15-13
bit 12
Unimplemented: Read as ‘0’
US: DSP Multiply Unsigned/Signed Control bit
1= DSP engine multiplies are unsigned
0= DSP engine multiplies are signed
bit 11
EDT: Early DOLoop Termination Control bit(1)
1= Terminate executing DOloop at end of current loop iteration
0= No effect
bit 10-8
DL<2:0>: DOLoop Nesting Level Status bits
111= 7 DOloops active
•
•
•
001= 1 DOloop active
000= 0 DOloops active
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SATA: ACCA Saturation Enable bit
1= Accumulator A saturation enabled
0= Accumulator A saturation disabled
SATB: ACCB Saturation Enable bit
1= Accumulator B saturation enabled
0= Accumulator B saturation disabled
SATDW: Data Space Write from DSP Engine Saturation Enable bit
1= Data space write saturation enabled
0= Data space write saturation disabled
ACCSAT: Accumulator Saturation Mode Select bit
1= 9.31 saturation (super saturation)
0= 1.31 saturation (normal saturation)
IPL3: CPU Interrupt Priority Level Status bit 3(2)
1= CPU interrupt priority level is greater than 7
0= CPU interrupt priority level is 7 or less
PSV: Program Space Visibility in Data Space Enable bit
1= Program space visible in data space
0= Program space not visible in data space
RND: Rounding Mode Select bit
1= Biased (conventional) rounding enabled
0= Unbiased (convergent) rounding enabled
IF: Integer or Fractional Multiplier Mode Select bit
1= Integer mode enabled for DSP multiply ops
0= Fractional mode enabled for DSP multiply ops
Note 1: This bit will always read as ‘0’.
2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level.
DS70265E-page 24
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
3.5
Arithmetic Logic Unit (ALU)
3.6
DSP Engine
The dsPIC33FJ12MC201/202 ALU is 16 bits wide and
is capable of addition, subtraction, bit shifts, and logic
operations. Unless otherwise mentioned, arithmetic
operations are 2’s complement in nature. Depending
on the operation, the ALU can affect the values of the
Carry (C), Zero (Z), Negative (N), Overflow (OV), and
Digit Carry (DC) Status bits in the SR register. The C
and DC Status bits operate as Borrow and Digit Borrow
bits, respectively, for subtraction operations.
The DSP engine consists of a high-speed 17-bit x
17-bit multiplier, a barrel shifter and a 40-bit adder/
subtracter (with two target accumulators, round and
saturation logic).
The dsPIC33FJ12MC201/202 is a single-cycle instruc-
tion flow architecture; therefore, concurrent operation
of the DSP engine with MCU instruction flow is not pos-
sible. However, some MCU ALU and DSP engine
resources can be used concurrently by the same
instruction (e.g., ED, EDAC).
The ALU can perform 8-bit or 16-bit operations,
depending on the mode of the instruction that is used.
Data for the ALU operation can come from the W
register array or data memory, depending on the
addressing mode of the instruction. Likewise, output
data from the ALU can be written to the W register array
or a data memory location.
The DSP engine can also perform inherent accumula-
tor-to-accumulator operations that require no additional
data. These instructions are ADD, SUB, and NEG.
The DSP engine has options selected through bits in
the CPU Core Control register (CORCON), as listed
below:
Refer to the “16-bit MCU and DSC Programmer’s Ref-
erence Manual” (DS70157) for information on the SR
bits affected by each instruction.
• Fractional or integer DSP multiply (IF)
• Signed or unsigned DSP multiply (US)
• Conventional or convergent rounding (RND)
• Automatic saturation on/off for ACCA (SATA)
• Automatic saturation on/off for ACCB (SATB)
• Automatic saturation on/off for writes to data
memory (SATDW)
The dsPIC33FJ12MC201/202 CPU incorporates hard-
ware support for both multiplication and division. This
includes a dedicated hardware multiplier and support
hardware for 16-bit-divisor division.
• Accumulator Saturation mode selection (ACC-
SAT)
3.5.1
MULTIPLIER
Using the high-speed 17-bit x 17-bit multiplier of the
DSP engine, the ALU supports unsigned, signed or
mixed-sign operation in several MCU multiplication
modes:
A block diagram of the DSP engine is shown in
Figure 3-3.
TABLE 3-1:
DSP INSTRUCTIONS
SUMMARY
• 16-bit x 16-bit signed
• 16-bit x 16-bit unsigned
Algebraic
Operation
ACC Write
• 16-bit signed x 5-bit (literal) unsigned
• 16-bit unsigned x 16-bit unsigned
• 16-bit unsigned x 5-bit (literal) unsigned
• 16-bit unsigned x 16-bit signed
• 8-bit unsigned x 8-bit unsigned
Instruction
Back
CLR
A = 0
A = (x – y)2
A = A + (x – y)2
A = A + (x * y)
A = A + x2
Yes
No
ED
EDAC
MAC
No
3.5.2
DIVIDER
Yes
No
MAC
The divide block supports 32-bit/16-bit and 16-bit/16-bit
signed and unsigned integer divide operations with the
following data sizes:
MOVSAC
MPY
No change in A
A = x * y
Yes
No
A = x 2
No
1. 32-bit signed/16-bit signed divide
2. 32-bit unsigned/16-bit unsigned divide
3. 16-bit signed/16-bit signed divide
4. 16-bit unsigned/16-bit unsigned divide
MPY
MPY.N
MSC
A = – x * y
No
A = A – x * y
Yes
The quotient for all divide instructions ends up in W0
and the remainder in W1. 16-bit signed and unsigned
DIV instructions can specify any W register for both
the 16-bit divisor (Wn) and any W register (aligned)
pair (W(m + 1):Wm) for the 32-bit dividend. The divide
algorithm takes one cycle per bit of divisor, so both
32-bit/16-bit and 16-bit/16-bit instructions take the
same number of cycles to execute.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 25
dsPIC33FJ12MC201/202
FIGURE 3-3:
DSP ENGINE BLOCK DIAGRAM
S
a
40
40-bit Accumulator A
40-bit Accumulator B
t
16
40
Round
Logic
u
r
a
t
Carry/Borrow Out
Saturate
e
Adder
Carry/Borrow In
Negate
40
40
40
Barrel
Shifter
16
40
Sign-Extend
32
16
Zero Backfill
32
33
17-bit
Multiplier/Scaler
16
16
To/From W Array
DS70265E-page 26
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
3.6.1
MULTIPLIER
3.6.2.1
Adder/Subtracter, Overflow and
Saturation
The 17-bit x 17-bit multiplier is capable of signed or
unsigned operation and can multiplex its output using a
scaler to support either 1.31 fractional (Q31) or 32-bit
integer results. Unsigned operands are zero-extended
into the 17th bit of the multiplier input value. Signed
operands are sign-extended into the 17th bit of the
multiplier input value. The output of the 17-bit x 17-bit
multiplier/scaler is a 33-bit value that is sign-extended
to 40 bits. Integer data is inherently represented as a
signed 2’s complement value, where the Most Signifi-
cant bit (MSb) is defined as a sign bit. The range of an
N-bit 2’s complement integer is -2N-1 to 2N-1 – 1.
The adder/subtracter is a 40-bit adder with an optional
zero input into one side, and either true or complement
data into the other input.
• In the case of addition, the Carry/Borrow input is
active-high and the other input is true data (not
complemented).
• In the case of subtraction, the Carry/Borrow input
is active-low and the other input is complemented.
The adder/subtracter generates Overflow Status bits,
SA/SB and OA/OB, which are latched and reflected in
the STATUS register:
• For a 16-bit integer, the data range is -32768
(0x8000) to 32767 (0x7FFF) including 0.
• Overflow from bit 39: this is a catastrophic
overflow in which the sign of the accumulator is
destroyed.
• For a 32-bit integer, the data range is
-2,147,483,648 (0x8000 0000) to 2,147,483,647
(0x7FFF FFFF).
• Overflow into guard bits 32 through 39: this is a
recoverable overflow. This bit is set whenever all
the guard bits are not identical to each other.
When the multiplier is configured for fractional
multiplication, the data is represented as a 2’s
complement fraction, where the MSb is defined as a
sign bit and the radix point is implied to lie just after the
sign bit (QX format). The range of an N-bit 2’s
complement fraction with this implied radix point is -1.0
to (1 – 21-N). For a 16-bit fraction, the Q15 data range
is -1.0 (0x8000) to 0.999969482 (0x7FFF) including 0
and has a precision of 3.01518x10-5. In Fractional
mode, the 16 x 16 multiply operation generates a 1.31
The adder has an additional saturation block that
controls accumulator data saturation, if selected. It
uses the result of the adder, the Overflow Status bits
described
previously
and
the
SAT<A:B>
(CORCON<7:6>) and ACCSAT (CORCON<4>) mode
control bits to determine when and to what value, to
saturate.
Six STATUS register bits support saturation and
overflow:
product that has a precision of 4.65661 x 10-10
.
The same multiplier is used to support the MCU
multiply instructions, which include integer 16-bit
signed, unsigned and mixed sign multiply operations.
• OA: ACCA overflowed into guard bits
• OB: ACCB overflowed into guard bits
• SA: ACCA saturated (bit 31 overflow and
saturation)
or
The MUL instruction can be directed to use byte- or
word-sized operands. Byte operands will direct a 16-bit
result, and word operands will direct a 32-bit result to
the specified register(s) in the W array.
ACCA overflowed into guard bits and
saturated (bit 39 overflow and saturation)
• SB: ACCB saturated (bit 31 overflow and
saturation)
3.6.2
DATA ACCUMULATORS AND
ADDER/SUBTRACTER
or
The data accumulator consists of a 40-bit adder/
subtracter with automatic sign extension logic. It can
select one of two accumulators (A or B) as its pre-
ACCB overflowed into guard bits and
saturated (bit 39 overflow and saturation)
• OAB: Logical OR of OA and OB
• SAB: Logical OR of SA and SB
accumulation
source
and
post-accumulation
destination. For the ADDand LACinstructions, the data
to be accumulated or loaded can be optionally scaled
using the barrel shifter prior to accumulation.
The OA and OB bits are modified each time data
passes through the adder/subtracter. When set, they
indicate that the most recent operation has overflowed
into the accumulator guard bits (bits 32 through 39).
The OA and OB bits can also optionally generate an
arithmetic warning trap when OA and OB are set and
the corresponding Overflow Trap Flag Enable bits
(OVATE, OVBTE) in the INTCON1 register are set
(refer to Section 7.0 “Interrupt Controller”). This
allows the user application to take immediate action; for
example, to correct system gain.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 27
dsPIC33FJ12MC201/202
The SA and SB bits are modified each time data
passes through the adder/subtracter, but can only be
cleared by the user application. When set, they indicate
that the accumulator has overflowed its maximum
range (bit 31 for 32-bit saturation or bit 39 for 40-bit
saturation) and will be saturated (if saturation is
enabled). When saturation is not enabled, SA and SB
default to bit 39 overflow, and therefore, indicate that a
catastrophic overflow has occurred. If the COVTE bit in
the INTCON1 register is set, the SA and SB bits will
generate an arithmetic warning trap when saturation is
disabled.
3.6.3
ACCUMULATOR ‘WRITE BACK’
The MAC class of instructions (with the exception of
MPY, MPY.N, ED,and EDAC) can optionally write a
rounded version of the high word (bits 31 through 16)
of the accumulator which is not targeted by the instruc-
tion into data space memory. The write is performed
across the X bus into combined X and Y address
space. The following addressing modes are supported:
• W13, Register Direct:
The rounded contents of the non-target
accumulator are written into W13 as a
1.15 fraction.
The Overflow and Saturation Status bits can optionally
be viewed in the STATUS Register (SR) as the logical
OR of OA and OB (in bit OAB) and the logical OR of SA
and SB (in bit SAB). Programmers can check one bit in
the STATUS register to determine whether either
accumulator has overflowed, or one bit to determine
whether either accumulator has saturated. This is
useful for complex number arithmetic, which typically
uses both accumulators.
• [W13] + = 2, Register Indirect with Post-Increment:
The rounded contents of the non-target accumu-
lator are written into the address pointed to by
W13 as a 1.15 fraction. W13 is then incremented
by 2 (for a word write).
The device supports three Saturation and Overflow
modes:
• Bit 39 Overflow and Saturation:
When bit 39 overflow and saturation occurs, the
saturation logic loads the maximally positive 9.31
value (0x7FFFFFFFFF) or maximally negative 9.31
value (0x8000000000) into the target accumulator.
The SA or SB bit is set and remains set until
cleared by the user application. This condition is
referred to as ‘super saturation’ and provides pro-
tection against erroneous data or unexpected algo-
rithm problems (such as gain calculations).
• Bit 31 Overflow and Saturation:
When bit 31 overflow and saturation occurs, the
saturation logic then loads the maximally positive
1.31 value (0x007FFFFFFF) or maximally nega-
tive 1.31 value (0x0080000000) into the target
accumulator. The SA or SB bit is set and remains
set until cleared by the user application. When
this Saturation mode is in effect, the guard bits are
not used, so the OA, OB or OAB bits are never
set.
• Bit 39 Catastrophic Overflow:
The bit 39 Overflow Status bit from the adder is
used to set the SA or SB bit, which remains set
until cleared by the user application. No saturation
operation is performed, and the accumulator is
allowed to overflow, destroying its sign. If the
COVTE bit in the INTCON1 register is set, a
catastrophic overflow can initiate a trap exception.
DS70265E-page 28
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
3.6.3.1
Round Logic
3.6.3.2
Data Space Write Saturation
The round logic is a combinational block that performs
a conventional (biased) or convergent (unbiased)
round function during an accumulator write (store). The
Round mode is determined by the state of the RND bit
in the CORCON register. It generates a 16-bit, 1.15
data value that is passed to the data space write
saturation logic. If rounding is not indicated by the
instruction, a truncated 1.15 data value is stored and
the least significant word (lsw) is simply discarded.
In addition to adder/subtracter saturation, writes to data
space can also be saturated, but without affecting the
contents of the source accumulator. The data space
write saturation logic block accepts a 16-bit, 1.15
fractional value from the round logic block as its input,
together with overflow status from the original source
(accumulator) and the 16-bit round adder. These inputs
are combined and used to select the appropriate 1.15
fractional value as output to write to data space
memory.
Conventional rounding will zero-extend bit 15 of the
accumulator and will add it to the ACCxH word (bits 16
through 31 of the accumulator).
If the SATDW bit in the CORCON register is set, data
(after rounding or truncation) is tested for overflow and
adjusted accordingly:
• If the ACCxL word (bits 0 through 15 of the accu-
mulator) is between 0x8000 and 0xFFFF (0x8000
included), ACCxH is incremented.
• For input data greater than 0x007FFF, data
written to memory is forced to the maximum
positive 1.15 value, 0x7FFF.
• If ACCxL is between 0x0000 and 0x7FFF, ACCxH
is left unchanged.
• For input data less than 0xFF8000, data written to
memory is forced to the maximum negative 1.15
value, 0x8000.
A consequence of this algorithm is that over a succes-
sion of random rounding operations, the value tends to
be biased slightly positive.
The MSb of the source (bit 39) is used to determine the
sign of the operand being tested.
Convergent (or unbiased) rounding operates in the
same manner as conventional rounding, except when
ACCxL equals 0x8000. In this case, the Least
Significant bit (LSb), bit 16 of the accumulator, of
ACCxH is examined:
If the SATDW bit in the CORCON register is not set, the
input data is always passed through unmodified under
all conditions.
3.6.4
BARREL SHIFTER
• If it is ‘1’, ACCxH is incremented.
• If it is ‘0’, ACCxH is not modified.
The barrel shifter can perform up to 16-bit arithmetic or
logic right shifts, or up to 16-bit left shifts, in a single
cycle. The source can be either of the two DSP
accumulators or the X bus (to support multi-bit shifts of
register or memory data).
Assuming that bit 16 is effectively random in nature,
this scheme removes any rounding bias that may
accumulate.
The SAC and SAC.R instructions store either a
truncated (SAC), or rounded (SAC.R) version of the
contents of the target accumulator to data memory via
The shifter requires a signed binary value to determine
both the magnitude (number of bits) and direction of the
shift operation. A positive value shifts the operand right.
A negative value shifts the operand left. A value of ‘0’
does not modify the operand.
the
X
bus, subject to data saturation (see
Section 3.6.3.2 “Data Space Write Saturation”). For
the MAC class of instructions, the accumulator write-
back operation functions in the same manner,
addressing combined MCU (X and Y) data space
though the X bus. For this class of instructions, the data
is always subject to rounding.
The barrel shifter is 40 bits wide, thereby obtaining a
40-bit result for DSP shift operations and a 16-bit result
for MCU shift operations. Data from the X bus is
presented to the barrel shifter between bit positions 16
and 31 for right shifts, and between bit positions 0 and
16 for left shifts.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 29
dsPIC33FJ12MC201/202
NOTES:
DS70265E-page 30
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
4.1
Program Address Space
4.0
MEMORY ORGANIZATION
The program address memory space of the
dsPIC33FJ12MC201/202 devices is 4M instructions.
The space is addressable by a 24-bit value derived
either from the 23-bit Program Counter (PC) during
program execution, or from table operation or data
space remapping as described in Section 4.6
“Interfacing Program and Data Memory Spaces”.
Note:
This data sheet summarizes the features
of the dsPIC33FJ12MC201/202 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 4. “Program
Memory” (DS70202) of the “dsPIC33F/
PIC24H Family Reference Manual”, which
is available from the Microchip website
(www.microchip.com).
User application access to the program memory space
is restricted to the lower half of the address range
(0x000000 to 0x7FFFFF). The exception is the use of
TBLRD/TBLWT operations, which use TBLPAG<7> to
permit access to the Configuration bits and Device ID
sections of the configuration memory space.
The dsPIC33FJ12MC201/202 architecture features
separate program and data memory spaces and
buses. This architecture also allows the direct access
of program memory from the data space during code
execution.
The memory map for the dsPIC33FJ12MC201/202
family of devices is shown in Figure 4-1.
FIGURE 4-1:
PROGRAM MEMORY MAP FOR dsPIC33FJ12MC201/202 DEVICES
dsPIC33FJ12MC201/202
0x000000
0x000002
0x000004
0x0000FE
0x000100
0x000104
0x0001FE
0x000200
GOTOInstruction
Reset Address
Interrupt Vector Table
Reserved
Alternate Vector Table
User Program
Flash Memory
(4K instructions)
0x001FFE
0x002000
Unimplemented
(Read ‘0’s)
0x7FFFFE
0x800000
Reserved
0xF7FFFE
0xF80000
0xF80017
0xF80018
Device Configuration
Registers
Reserved
DEVID (2)
0xFEFFFE
0xFF0000
0xFFFFFE
© 2007-2011 Microchip Technology Inc.
DS70265E-page 31
dsPIC33FJ12MC201/202
4.1.1
PROGRAM MEMORY
ORGANIZATION
4.1.2
INTERRUPT AND TRAP VECTORS
All dsPIC33FJ12MC201/202 devices reserve the
addresses between 0x00000 and 0x000200 for hard-
coded program execution vectors. A hardware Reset
vector is provided to redirect code execution from the
default value of the PC on device Reset to the actual
start of code. A GOTOinstruction is programmed by the
user application at 0x000000, with the actual address
for the start of code at 0x000002.
The program memory space is organized in word-
addressable blocks. Although it is treated as 24 bits
wide, it is more appropriate to think of each address of
the program memory as a lower and upper word, with
the upper byte of the upper word being unimplemented.
The lower word always has an even address, while the
upper word has an odd address (Figure 4-2).
dsPIC33FJ12MC201/202 devices also have two
interrupt vector tables, located from 0x000004 to
0x0000FF and 0x000100 to 0x0001FF. These vector
tables allow each of the device interrupt sources to be
handled by separate Interrupt Service Routines (ISRs).
A more detailed discussion of the interrupt vector
tables is provided in Section 7.1 “Interrupt Vector
Table”.
Program memory addresses are always word-aligned
on the lower word, and addresses are incremented or
decremented by two during code execution. This
arrangement provides compatibility with data memory
space addressing and makes data in the program
memory space accessible.
FIGURE 4-2:
PROGRAM MEMORY ORGANIZATION
least significant word (lsw)
PC Address
most significant word (msw)
msw
Address
(lsw Address)
23
16
8
0
0x000001
0x000003
0x000005
0x000007
0x000000
0x000002
0x000004
0x000006
00000000
00000000
00000000
00000000
Program Memory
‘Phantom’ Byte
(read as ‘0’)
Instruction Width
DS70265E-page 32
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported, so
care must be taken when mixing byte and word
operations, or translating from 8-bit MCU code. If a
misaligned read or write is attempted, an address error
trap is generated. If the error occurred on a read, the
instruction in progress is completed. If the error
occurred on a write, the instruction is executed but the
write does not occur. In either case, a trap is then exe-
cuted, allowing the system and/or user application to
examine the machine state prior to execution of the
address Fault.
4.2
Data Address Space
The dsPIC33FJ12MC201/202 CPU has a separate 16-
bit-wide data memory space. The data space is
accessed using separate Address Generation Units
(AGUs) for read and write operations. The data
memory maps is shown in Figure 4-3.
All Effective Addresses (EAs) in the data memory space
are 16 bits wide and point to bytes within the data space.
This arrangement gives a data space address range of
64 Kbytes or 32K words. The lower half of the data
memory space (that is, when EA<15> = 0) is used for
implemented memory addresses, while the upper half
(EA<15> = 1) is reserved for the Program Space
Visibility area (see Section 4.6.3 “Reading Data from
Program Memory Using Program Space Visibility”).
All byte loads into any W register are loaded into the
LSB. The MSB is not modified.
A sign-extend instruction (SE) is provided to allow user
applications to translate 8-bit signed data to 16-bit
signed values. Alternately, for 16-bit unsigned data,
user applications can clear the MSB of any W register
by executing a zero-extend (ZE) instruction on the
appropriate address.
Microchip dsPIC33FJ12MC201/202 devices imple-
ment up to 1 Kbyte of data memory. Should an EA point
to a location outside of this area, an all-zero word or
byte will be returned.
4.2.1
DATA SPACE WIDTH
4.2.3
SFR SPACE
The data memory space is organized in byte
addressable, 16-bit wide blocks. Data is aligned in data
memory and registers as 16-bit words, but all data
space EAs resolve to bytes. The Least Significant
Bytes (LSBs) of each word have even addresses, while
the Most Significant Bytes (MSBs) have odd
addresses.
The first 2 Kbytes of the Near Data Space, from 0x0000
to 0x07FF, is primarily occupied by Special Function
Registers (SFRs). These are used by the
dsPIC33FJ12MC201/202 core and peripheral modules
for controlling the operation of the device.
SFRs are distributed among the modules that they
control, and are generally grouped together by module.
Much of the SFR space contains unused addresses;
these are read as ‘0’.
4.2.2
DATA MEMORY ORGANIZATION
AND ALIGNMENT
To maintain backward compatibility with PIC® MCU
devices and improve data space memory usage
efficiency, the dsPIC33FJ12MC201/202 instruction set
Note:
The actual set of peripheral features and
interrupts varies by the device. Refer to
the corresponding device tables and pin-
out
diagrams
for
device-specific
supports both word and byte operations. As
a
information.
consequence of byte accessibility, all effective address
calculations are internally scaled to step through word-
aligned memory. For example, the core recognizes that
Post-Modified Register Indirect Addressing mode
[Ws++] will result in a value of Ws + 1 for byte
operations and Ws + 2 for word operations.
4.2.4
NEAR DATA SPACE
The 8-Kbyte area between 0x0000 and 0x1FFF is
referred to as the near data space. Locations in this
space are directly addressable via a 13-bit absolute
address field within all memory direct instructions.
Additionally, the whole data space is addressable using
MOVclass of instructions, which support Memory Direct
Addressing mode with a 16-bit address field, or by
using Indirect Addressing mode with a working register
as an address pointer.
Data byte reads will read the complete word that
contains the byte, using the LSB of any EA to
determine which byte to select. The selected byte is
placed onto the LSB of the data path. That is, data
memory and registers are organized as two parallel
byte-wide entities with shared (word) address decoding
but separate write lines. Data byte writes only write to
the corresponding side of the array or register that
matches the byte address.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 33
dsPIC33FJ12MC201/202
FIGURE 4-3:
DATA MEMORY MAP FOR dsPIC33FJ12MC201/202 DEVICES WITH 1 KB RAM
MSB
Address
LSB
Address
16 bits
MSb
LSb
0x0000
0x0001
2 Kbyte
SFR Space
SFR Space
0x07FE
0x0800
0x07FF
0x0801
X Data RAM (X)
Y Data RAM (Y)
8 Kbyte
Near Data
Space
0x09FF
0x0A01
0x09FE
0x0A00
1 Kbyte
SRAM Space
0x0BFF
0x0C01
0x0BFE
0x0C00
0x1FFE
0x2000
0x1FFF
0x2001
0x8001
0x8000
X Data
Optionally
Mapped
Unimplemented (X)
into Program
Memory
0xFFFF
0xFFFE
DS70265E-page 34
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
The Y data space is used in concert with the X data
space by the MAC class of instructions (CLR, ED,
EDAC, MAC, MOVSAC, MPY, MPY.N, and MSC) to provide
two concurrent data read paths.
4.2.5
X AND Y DATA SPACES
The core has two data spaces, X and Y. These data
spaces can be considered either separate (for some
DSP instructions), or as one unified linear address
range (for MCU instructions). The data spaces are
accessed using two Address Generation Units (AGUs)
and separate data paths. This feature allows certain
instructions to concurrently fetch two words from RAM,
thereby enabling efficient execution of DSP algorithms
such as Finite Impulse Response (FIR) filtering and
fast Fourier transform (FFT).
Both the X and Y data spaces support Modulo
Addressing mode for all instructions, subject to
addressing mode restrictions. Bit-Reversed Addressing
mode is only supported for writes to X data space.
All data memory writes, including in DSP instructions,
view data space as combined X and Y address space.
The boundary between the X and Y data spaces is
device-dependent and is not user-programmable.
The X data space is used by all instructions and
supports all addressing modes. X data space has
separate read and write data buses. The X read data
bus is the read data path for all instructions that view
data space as combined X and Y address space. It is
also the X data prefetch path for the dual operand DSP
instructions (MACclass).
All effective addresses are 16 bits wide and point to
bytes within the data space. Therefore, the data space
address range is 64 Kbytes, or 32K words, although the
implemented memory locations vary by device.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 35
TABLE 4-1:
CPU CORE REGISTERS MAP
SFR
Addr
All
Resets
SFR Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WREG0
WREG1
WREG2
WREG3
WREG4
WREG5
WREG6
WREG7
WREG8
WREG9
WREG10
WREG11
WREG12
WREG13
WREG14
WREG15
SPLIM
0000
0002
0004
0006
0008
000A
000C
000E
0010
0012
0014
0016
0018
001A
001C
001E
0020
0022
0024
0026
0028
002A
002C
002E
0030
0032
0034
0036
0038
003A
003C
003E
0040
0042
0044
0046
Working Register 0
Working Register 1
Working Register 2
Working Register 3
Working Register 4
Working Register 5
Working Register 6
Working Register 7
Working Register 8
Working Register 9
Working Register 10
Working Register 11
Working Register 12
Working Register 13
Working Register 14
Working Register 15
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0800
xxxx
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
xxxx
xxxx
xxxx
00xx
xxxx
00xx
0000
0020
0000
Stack Pointer Limit Register
ACCAL
Accumulator A Low Word Register
Accumulator A High Word Register
Accumulator A Upper Word Register
Accumulator B Low Word Register
Accumulator B High Word Register
Accumulator B Upper Word Register
Program Counter Low Word Register
ACCAH
ACCAU
ACCBL
ACCBH
ACCBU
PCL
PCH
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Program Counter High Byte Register
Table Page Address Pointer Register
TBLPAG
PSVPAG
RCOUNT
DCOUNT
DOSTARTL
DOSTARTH
DOENDL
DOENDH
SR
Program Memory Visibility Page Address Pointer Register
Repeat Loop Counter Register
DCOUNT<15:0>
DOSTARTL<15:1>
0
0
—
—
—
—
—
—
—
—
DOENDL<15:1>
—
—
—
DOSTARTH<5:0>
DOENDH
—
OA
—
—
OB
—
—
SA
—
—
SB
US
—
—
—
—
—
—
OAB
EDT
SAB
DA
DC
IPL2
SATA
IPL1
SATB
IPL0
RA
N
OV
Z
C
CORCON
MODCON
DL<2:0>
SATDW ACCSAT
IPL3
PSV
RND
IF
XMODEN YMODEN
—
BWM<3:0>
YWM<3:0>
XWM<3:0>
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-1:
CPU CORE REGISTERS MAP (CONTINUED)
SFR
Addr
All
Resets
SFR Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
XMODSRT
XMODEND
YMODSRT
YMODEND
XBREV
0048
004A
004C
004E
0050
0052
XS<15:1>
XE<15:1>
YS<15:1>
YE<15:1>
0
1
0
1
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
BREN
—
XB<14:0>
DISICNT
—
Disable Interrupts Counter Register
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-2:
CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ12MC202
SFR
Name
Addr
SFR
All
Resets
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CNEN1
CNEN2
CNPU1
CNPU2
Legend:
0060
0062
0068
006A
CN15IE
—
CN14IE
CN30IE
CN13IE
CN29IE
CN12IE
—
CN11IE
CN27IE
—
—
—
—
—
—
—
—
—
CN24IE
—
CN7IE
CN6IE
CN5IE
CN4IE
—
CN3IE
—
CN2IE
—
CN1IE
—
CN0IE
0000
0000
0000
CN23IE
CN22IE
CN21IE
CN16IE
CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE
CN30PUE CN29PUE CN27PUE
CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE
—
—
CN24PUE CN23PUE CN22PUE CN21PUE
—
—
—
—
CN16PUE 0000
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-3:
CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ12MC201
SFR
Name
Addr
SFR
All
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Resets
CNEN1
0060
—
—
—
—
—
—
—
—
—
—
—
—
CN14IE
CN30IE
CN13IE
CN29IE
CN12IE
—
CN11IE
—
CN5IE
CN4IE
—
CN3IE
—
CN2IE
—
CN1IE
—
CN0IE
—
0000
0000
0000
0000
CNEN2
CNPU1
CNPU2
Legend:
00C2
0068
006A
CN23IE
—
CN22IE
—
CN21IE
—
—
—
—
—
—
CN14PUE CN13PUE CN12PUE CN11PUE
CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE
—
—
—
—
—
—
—
CN30PUE CN29PUE
CN23PUE CN22PUE CN21PUE
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-4:
INTERRUPT CONTROLLER REGISTER MAP
SFR
Name
SFR
Addr
All
Resets
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR
—
MATHERR ADDRERR STKERR OSCFAIL
—
0000
INTCON2 0082 ALTIVT
DISI
—
—
—
U1TXIF
—
—
U1RXIF
—
—
—
—
T3IF
—
—
T2IF
IC8IF
—
—
OC2IF
IC7IF
—
—
—
—
—
T1IF
CNIF
—
INT2EP
OC1IF
—
INT1EP INT0EP 0000
IC1IF INT0IF 0000
MI2C1IF SI2C1IF 0000
IFS0
IFS1
IFS3
IFS4
IEC0
IEC1
IEC3
IEC4
IPC0
IPC1
IPC2
IPC3
IPC4
IPC5
IPC7
IPC14
IPC15
IPC16
IPC18
0084
0086
—
—
AD1IF
SPI1IF SPI1EIF
IC2IF
—
INT2IF
—
—
—
—
INT1IF
—
008A FLTA1IF
—
—
—
—
QEIIF PWM1IF
FLTA2IF PWM2IF
SPI1IE SPI1EIE
—
—
—
—
—
0000
0000
0000
008C
0094
0096
—
—
—
—
—
—
—
—
—
—
—
—
—
—
U1EIF
IC1IE
—
AD1IE
U1TXIE
—
U1RXIE
—
T3IE
—
T2IE
IC8IE
—
OC2IE
IC7IE
—
IC2IE
—
T1IE
CNIE
—
OC1IE
—
INT0IE
—
INT2IE
—
—
—
INT1IE
—
MI2C1IE SI2C1IE 0000
009A FLTA1IE
—
—
—
—
QEIIE PWM1IE
FLTA2IE PWM2IE
OC1IP<2:0>
—
—
—
—
—
—
0000
0000
4444
4440
4444
0044
4044
4404
0040
0440
4000
0040
0440
0000
009C
00A4
00A6
00A8
00AA
00AC
00AE
00B2
00C0
00C2
00C4
00C8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
U1EIE
T1IP<2:0>
—
—
IC1IP<2:0>
IC2IP<2:0>
SPI1EIP<2:0>
AD1IP<2:0>
MI2C1IP<2:0>
—
—
INT0IP<2:0>
T2IP<2:0>
—
OC2IP<2:0>
—
—
—
—
—
U1RXIP<2:0>
—
SPI1IP<2:0>
—
—
T3IP<2:0>
—
—
—
—
—
—
—
—
—
—
—
U1TXIP<2:0>
CNIP<2:0>
—
—
IC7IP<2:0>
—
—
—
SI2C1IP<2:0>
IC8IP<2:0>
—
—
—
—
—
—
—
INT1IP<2:0>
—
—
—
—
—
—
—
—
—
INT2IP<2:0>
PWM1IP<2:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
QEIIP<2:0>
—
—
—
FLTA1IP<2:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
U1EIP<2:0>
PWM2IP<2:0>
—
—
FLTA2IP<2:0>
—
—
INTTREG 00E0
Legend:
ILR<3:0>
—
VECNUM<6:0>
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-5:
TIMER REGISTER MAP
SFR
Name
Addr
SFR
All
Resets
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TMR1
PR1
0100
0102
0104
0106
Timer1 Register
Period Register 1
0000
FFFF
0000
0000
xxxx
0000
FFFF
FFFF
0000
0000
T1CON
TMR2
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS<1:0>
—
TSYNC
TCS
—
Timer2 Register
TMR3HLD 0108
Timer3 Holding Register (for 32-bit timer operations only)
Timer3 Register
TMR3
PR2
010A
010C
010E
0110
0112
Period Register 2
PR3
Period Register 3
T2CON
T3CON
Legend:
TON
TON
—
—
TSIDL
TSIDL
—
—
—
—
—
—
—
—
—
—
—
—
TGATE
TGATE
TCKPS<1:0>
TCKPS<1:0>
T32
—
—
—
TCS
TCS
—
—
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-6:
INPUT CAPTURE REGISTER MAP
SFR
Addr
All
Resets
SFR Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IC1BUF
IC1CON
IC2BUF
IC2CON
IC7BUF
IC7CON
IC8BUF
IC8CON
Legend:
0140
0142
0144
0146
0158
015A
015C
015E
Input 1 Capture Register
ICTMR
Input 2 Capture Register
ICTMR
Input 7 Capture Register
ICTMR
Input 8Capture Register
ICTMR
xxxx
0000
xxxx
0000
xxxx
0000
xxxx
0000
—
—
—
—
—
—
—
—
ICSIDL
ICSIDL
ICSIDL
ICSIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ICI<1:0>
ICOV
ICOV
ICOV
ICOV
ICBNE
ICBNE
ICBNE
ICBNE
ICM<2:0>
ICM<2:0>
ICM<2:0>
ICM<2:0>
—
ICI<1:0>
ICI<1:0>
ICI<1:0>
—
—
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-7:
OUTPUT COMPARE REGISTER MAP
SFR
Addr
All
Resets
SFR Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OC1RS
OC1R
0180
0182
0184
0186
0188
018A
Output Compare 1 Secondary Register
Output Compare 1 Register
xxxx
xxxx
0000
xxxx
xxxx
0000
OC1CON
OC2RS
OC2R
—
—
—
—
OCSIDL
OCSIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
OCFLT
OCFLT
OCTSEL
OCTSEL
OCM<2:0>
OCM<2:0>
Output Compare 2 Secondary Register
Output Compare 2 Register
OC2CON
—
—
—
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-8:
6-OUTPUT PWM1 REGISTER MAP FOR dsPIC33FJ12MC202
SFR Name Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 1111 1111
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
1111 1111 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
P1TCON
P1TMR
01C0
01C2
01C4
PTEN
PTDIR
—
—
PTSIDL
—
—
—
—
—
PTOPS<3:0>
PTCKPS<1:0>
PTMOD<1:0>
PWM Timer Count Value Register
PWM Time Base Period Register
PWM Special Event Compare Register
P1TPER
P1SECMP
01C6 SEVTDIR
PWM1CON1 01C8
PWM1CON2 01CA
P1DTCON1 01CC
P1DTCON2 01CE
P1FLTACON 01D0
P1OVDCON 01D4
—
—
—
—
—
—
—
—
—
PMOD3 PMOD2 PMOD1
SEVOPS<3:0>
—
—
PEN3H PEN2H PEN1H
—
—
PEN3L
IUE
PEN2L
PEN1L
UDIS
—
—
—
OSYNC
DTBPS<1:0>
DTB<5:0>
DTAPS<1:0>
DTA<5:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DTS3A
—
DTS3I
—
DTS2A
—
DTS2I
DTS1A
FAEN2
DTS1I
FAOV3H FAOV3L FAOV2H FAOV2L FAOV1H FAOV1L FLTAM
POVD3H POVD3L POVD2H POVD2L POVD1H POVD1L
FAEN3
FAEN1
—
POUT3H POUT3L POUT2H POUT2L POUT1H POUT1L
P1DC1
P1DC2
P1DC3
01D6
01D8
01DA
PWM Duty Cycle 1 Register
PWM Duty Cycle 2 Register
PWM Duty Cycle 3 Register
Legend: u= uninitialized bit, — = unimplemented, read as ‘0’
TABLE 4-9:
4-OUTPUT PWM1 REGISTER MAP FOR dsPIC33FJ12MC201
SFR Name Addr.
Bit 15
Bit 14 Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 1111 1111
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
1111 1111 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
P1TCON
P1TMR
01C0
01C2
01C4
PTEN
PTDIR
—
—
PTSIDL
—
—
—
—
—
PTOPS<3:0>
PTCKPS<1:0>
PTMOD<1:0>
PWM Timer Count Value Register
PWM Time Base Period Register
PWM Special Event Compare Register
P1TPER
P1SECMP
01C6 SEVTDIR
PWM1CON1 01C8
PWM1CON2 01CA
P1DTCON1 01CC
P1DTCON2 01CE
P1FLTACON 01D0
P1OVDCON 01D4
—
—
—
—
—
—
—
—
—
—
PMOD2 PMOD1
—
—
—
—
PEN2H
—
PEN1H
—
—
—
—
PEN2L
PEN1L
UDIS
SEVOPS<3:0>
DTB<5:0>
IUE
OSYNC
DTBPS<1:0>
DTAPS<1:0>
DTA<5:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DTS2A
—
DTS2I
—
DTS1A
FAEN2
DTS1I
FAOV2H FAOV2L FAOV1H FAOV1L FLTAM
POVD2H POVD2L POVD1H POVD1L
FAEN1
—
POUT2H POUT2L POUT1H POUT1L
P1DC1
P1DC2
01D6
01D8
PWM Duty Cycle 1 Register
PWM Duty Cycle 2 Register
Legend: u= uninitialized bit, — = unimplemented, read as ‘0’
TABLE 4-10: 2-OUTPUT PWM2 REGISTER MAP
SFR Name Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
P2TCON
P2TMR
05C0
05C2
05C4
PTEN
PTDIR
—
—
PTSIDL
—
—
—
—
—
PTOPS<3:0>
PTCKPS<1:0>
PTMOD<1:0>
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
PWM Timer Count Value Register
PWM Time Base Period Register
P2TPER
P2SECMP
05C6 SEVTDIR
PWM Special Event Compare Register
PWM2CON1 05C8
PWM2CON2 05CA
P2DTCON1 05CC
P2DTCON2 05CE
P2FLTACON 05D0
P2OVDCON 05D4
—
—
—
—
—
—
—
—
—
—
—
PMOD1
—
—
—
—
—
—
PEN1H
—
—
—
—
—
PEN1L 0000 0000 1111 1111
UDIS 0000 0000 0000 0000
0000 0000 0000 0000
SEVOPS<3:0>
DTB<5:0>
IUE
OSYNC
DTBPS<1:0>
DTAPS<1:0>
DTA<5:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DTS1A
—
DTS1I 0000 0000 0000 0000
FAEN1 0000 0000 0000 0000
FAOV1H FAOV1L FLTAM
POVD1H POVD1L
PWM Duty Cycle 1 Register
—
POUT1H POUT1L 1111 1111 0000 0000
P2DC1
05D6
0000 0000 0000 0000
Legend: u = uninitialized bit, — = unimplemented, read as ‘0’
TABLE 4-11: QEI1 REGISTER MAP
SFR
Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
—
—
QEI1CON
01E0 CNTERR
QEISIDL INDX UPDN
QEIM<2:0>
SWPAB PCDOUT TQGATE
QECK<2:0>
TQCKPS<1:0>
—
POSRES TQCS UPDN_SRC 0000 0000 0000 0000
DFLT1CON 01E2
—
—
—
—
IMV<1:0> CEID QEOUT
—
—
—
0000 0000 0000 0000
0000 0000 0000 0000
1111 1111 1111 1111
POS1CNT
MAX1CNT
01E4
01E6
Position Counter<15:0>
Maximum Count<15:0>
Legend: u= uninitialized bit, — = unimplemented, read as ‘0’
TABLE 4-12: I2C1 REGISTER MAP
SFR
Addr
All
Resets
SFR Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
I2C1RCV
I2C1TRN
I2C1BRG
I2C1CON
I2C1STAT
I2C1ADD
I2C1MSK
Legend:
0200
0202
0204
0206
0208
020A
020C
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Receive Register
Transmit Register
0000
00FF
0000
1000
0000
0000
0000
—
—
—
—
—
Baud Rate Generator Register
I2CEN
ACKSTAT
—
—
I2CSIDL SCLREL
IPMIEN
—
A10M
BCL
—
DISSLW
GCSTAT
SMEN
GCEN
STREN
I2COV
ACKDT
D_A
ACKEN
P
RCEN
S
PEN
R_W
RSEN
RBF
SEN
TBF
TRSTAT
—
—
—
—
—
—
—
ADD10
IWCOL
—
Address Register
—
—
—
—
Address Mask Register
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-13: UART1 REGISTER MAP
SFR
Addr
All
Resets
SFR Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
U1MODE
U1STA
0220
0222
0224
0226
0228
UARTEN
—
USIDL
IREN
—
RTSMD
—
UEN1
UTXBF
—
UEN0
TRMT
WAKE
LPBACK
ABAUD URXINV
ADDEN RIDLE
BRGH
PERR
PDSEL<1:0>
STSEL
0000
0110
xxxx
0000
0000
UTXISEL1 UTXINV UTXISEL0
UTXBRK UTXEN
URXISEL<1:0>
FERR
OERR
URXDA
U1TXREG
U1RXREG
U1BRG
—
—
—
—
—
—
—
—
—
—
—
UART Transmit Register
UART Receive Register
—
—
Baud Rate Generator Prescaler
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-14: SPI1 REGISTER MAP
SFR
Name
SFR
Addr
All
Resets
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SPI1STAT
SPI1CON1
SPI1CON2
SPI1BUF
Legend:
0240
0242
0244
0248
SPIEN
—
—
—
SPISIDL
—
—
—
—
—
SMP
—
—
CKE
—
—
SSEN
—
SPIROV
CKP
—
MSTEN
—
—
—
SPRE<2:0>
—
—
SPITBF
SPIRBF
0000
0000
0000
0000
DISSCK DISSDO MODE16
PPRE<1:0>
FRMEN
SPIFSD
FRMPOL
—
—
—
—
—
—
FRMDLY
—
SPI1 Transmit and Receive Buffer Register
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-15: ADC1 REGISTER MAP FOR dsPIC33FJ12MC202
All
Resets
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADC1BUF0
ADC1BUF1
ADC1BUF2
ADC1BUF3
ADC1BUF4
ADC1BUF5
ADC1BUF6
ADC1BUF7
ADC1BUF8
ADC1BUF9
ADC1BUFA
ADC1BUFB
ADC1BUFC
ADC1BUFD
ADC1BUFE
ADC1BUFF
AD1CON1
AD1CON2
AD1CON3
AD1CHS123
AD1CHS0
0300
0302
0304
0306
0308
030A
030C
030E
0310
0312
0314
0316
0318
031A
031C
031E
0320
0322
0324
0326
ADC Data Buffer 0
ADC Data Buffer 1
ADC Data Buffer 2
ADC Data Buffer 3
ADC Data Buffer 4
ADC Data Buffer 5
ADC Data Buffer 6
ADC Data Buffer 7
ADC Data Buffer 8
ADC Data Buffer 9
ADC Data Buffer 10
ADC Data Buffer 11
ADC Data Buffer 12
ADC Data Buffer 13
ADC Data Buffer 14
ADC Data Buffer 15
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
0000
0000
0000
ADON
—
ADSIDL
—
—
—
—
AD12B
CSCNA
FORM<1:0>
CHPS<1:0>
SSRC<2:0>
—
—
SIMSAM
ASAM
SAMP
BUFM
DONE
ALTS
VCFG<2:0>
BUFS
SMPI<3:0>
ADCS<7:0>
ADRC
—
—
—
—
—
—
—
—
—
—
—
SAMC<4:0>
—
—
CH123NB<1:0>
CH0SB<4:0>
CH123SB
—
CH0NA
—
—
—
—
—
—
—
—
—
CH123NA<1:0>
CH0SA<4:0>
PCFG2 PCFG1
CSS2 CSS1
CH123SA 0000
0328 CH0NB
0000
AD1PCFGL
AD1CSSL
032C
0330
—
—
—
—
—
—
—
—
—
—
—
PCFG5
CSS5
PCFG4
CSS4
PCFG3
CSS3
PCFG0
CSS0
0000
0000
—
—
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-16: ADC1 REGISTER MAP FOR dsPIC33FJ12MC201
All
Resets
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0300
0302
0304
0306
0308
030A
030C
030E
0310
0312
0314
0316
0318
031A
031C
031E
0320
0322
0324
0326
ADC1BUF0
ADC1BUF1
ADC1BUF2
ADC1BUF3
ADC1BUF4
ADC1BUF5
ADC1BUF6
ADC1BUF7
ADC1BUF8
ADC1BUF9
ADC1BUFA
ADC1BUFB
ADC1BUFC
ADC1BUFD
ADC1BUFE
ADC1BUFF
AD1CON1
AD1CON2
AD1CON3
AD1CHS123
AD1CHS0
ADC Data Buffer 0
ADC Data Buffer 1
ADC Data Buffer 2
ADC Data Buffer 3
ADC Data Buffer 4
ADC Data Buffer 5
ADC Data Buffer 6
ADC Data Buffer 7
ADC Data Buffer 8
ADC Data Buffer 9
ADC Data Buffer 10
ADC Data Buffer 11
ADC Data Buffer 12
ADC Data Buffer 13
ADC Data Buffer 14
ADC Data Buffer 15
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
0000
0000
0000
ADON
—
ADSIDL
—
—
—
—
AD12B
CSCNA
FORM<1:0>
CHPS<1:0>
SSRC<2:0>
—
—
SIMSAM
ASAM
SAMP
BUFM
DONE
ALTS
VCFG<2:0>
BUFS
SMPI<3:0>
ADCS<7:0>
ADRC
—
—
—
—
—
—
—
—
—
—
—
SAMC<4:0>
—
—
CH123NB<1:0>
CH0SB<4:0>
CH123SB
—
CH0NA
—
—
—
—
—
—
—
—
—
—
—
CH123NA<1:0>
CH0SA<4:0>
PCFG2 PCFG1
CSS2 CSS1
CH123SA 0000
0328 CH0NB
0000
AD1PCFGL
AD1CSSL
032C
0330
—
—
—
—
—
—
—
—
—
—
—
—
—
PCFG3
CSS3
PCFG0
CSS0
0000
0000
—
—
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-17: PERIPHERAL PIN SELECT INPUT REGISTER MAP
File
Name
All
Resets
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RPINR0
RPINR1
RPINR3
RPINR7
RPINR10
RPINR11
RPINR12
RPINR13
RPINR14
RPINR15
RPINR18
RPINR20
RPINR21
Legend:
1F00
001F
1F1F
1F1F
1F1F
001F
001F
001F
1F1F
001F
1F1F
1F1F
001F
0680
0682
0686
068E
0694
0696
0698
069A
069C
069E
06A4
06A8
06AA
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
INT1R<4:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
T3CKR<4:0>
IC2R<4:0>
IC8R<4:0>
—
—
—
INT2R<4:0>
T2CKR<4:0>
IC1R<4:0>
IC7R<4:0>
—
—
—
—
—
—
—
—
—
—
—
—
OCFAR<4:0>
FLTA1R<4:0>
FLTA2R<4:0>
QEA1R<4:0>
INDX1R<4:0>
U1RXR<4:0>
SDI1R<4:0>
SS1R<4:0>
—
—
QEB1R<4:0>
—
—
—
—
—
U1CTSR<4:0>
SCK1R<4:0>
—
—
—
—
—
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-18: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ12MC202
File
Name
All
Resets
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RPOR0
RPOR1
RPOR2
RPOR3
RPOR4
RPOR5
RPOR6
RPOR7
Legend:
0000
0000
0000
0000
0000
0000
0000
0000
06C0
06C2
06C4
06C6
06C8
06CA
06CC
06CE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RP1R<4:0>
RP3R<4:0>
RP5R<4:0>
RP7R<4:0>
RP9R<4:0>
RP11R<4:0>
RP13R<4:0>
RP15R<4:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RP0R<4:0>
RP2R<4:0>
RP4R<4:0>
RP6R<4:0>
RP8R<4:0>
RP10R<4:0>
RP12R<4:0>
RP14R<4:0>
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-19: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ12MC201
File
Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All Resets
RPOR0
RPOR2
RPOR3
RPOR4
RPOR6
RPOR7
Legend:
0000
0000
0000
0000
0000
0000
06C0
06C4
06C6
06C8
06CC
06CE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RP1R<4:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RP0R<4:0>
RP4R<4:0>
—
—
—
—
—
RP7R<4:0>
RP9R<4:0>
RP13R<4:0>
RP15R<4:0>
—
—
—
—
RP8R<4:0>
RP12R<4:0>
RP14R<4:0>
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-20: PORTA REGISTER MAP
File
Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All Resets
—
—
—
—
—
—
—
—
—
—
—
TRISA
02C0
02C2
02C4
02C6
TRISA4
RA4
TRISA3
RA3
TRISA2
RA2
TRISA1
RA1
TRISA0
RA0
001F
xxxx
xxxx
0000
PORTA
LATA
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LATA4
ODCA4
LATA3
ODCA3
LATA2
ODCA2
LATA1
ODCA1
LATA0
ODCA0
ODCA
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-21: PORTB REGISTER MAP FOR dsPIC33FJ12MC202
File
Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All Resets
TRISB
02C8
02CA
02CC
02CE
TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9
TRISB8
RB8
TRISB7
RB7
TRISB6
RB6
TRISB5
RB5
TRISB4
RB4
TRISB3
RB3
TRISB2
RB2
TRISB1
RB1
TRISB0
RB0
FFFF
xxxx
xxxx
0000
PORTB
LATB
RB15
RB14
RB13
RB12
RB11
RB10
RB9
LATB15
ODCB15
LATB14
ODCB14
LATB13
ODCB13
LATB12
ODCB12
LATB11
ODCB11
LATB10
ODCB10
LATB9
ODCB9
LATB8
ODCB8
LATB7
ODCB7
LATB6
ODCB6
LATB5
ODCB5
LATB4
ODCB4
LATB3
ODCB3
LATB2
ODCB2
LATB1
ODCB1
LATB0
ODCB0
ODCB
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-22: PORTB REGISTER MAP FOR dsPIC33FJ12MC201
File Name Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All Resets
TRISB
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
F393
xxxx
xxxx
0000
02C8 TRISB15 TRISB14 TRISB13 TRISB12
TRISB9 TRISB8 TRISB7
TRISB4
RB4
TRISB1 TRISB0
PORTB
LATB
02CA
02CC
RB15
RB14
RB13
RB12
RB9
RB8
RB7
RB1
RB0
LATB15
LATB14
LATB13
LATB12
LATB9
LATB8
LATB7
LATB4
ODCB4
LATB1
LATB0
ODCB
Legend:
02CE ODCB15 ODCB14 ODCB13 ODCB12
ODCB9 ODCB8 ODCB7
ODCB1 ODCB0
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal
TABLE 4-23: SYSTEM CONTROL REGISTER MAP
All
Resets
File Name Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
RCON
0740
0742
0744
0746
0748
TRAPR IOPUWR
—
COSC<2:0>
DOZE<2:0>
—
—
—
—
—
CM
NOSC<2:0>
FRCDIV<2:0>
—
VREGS
EXTR
SWR
SWDTEN
LOCK
—
WDTO
—
SLEEP
CF
IDLE
—
BOR
POR
xxxx
(2)
OSCCON
CLKDIV
PLLFBD
OSCTUN
—
CLKLOCK IOLOCK
PLLPOST<1:0>
LPOSCEN OSWEN
0300
ROI
DOZEN
—
PLLPRE<4:0>
3040
0030
0000
—
—
—
—
—
—
—
—
PLLDIV<8:0>
—
—
—
—
—
—
TUN<5:0>
Legend:
Note 1:
2:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
RCON register Reset values dependent on type of Reset.
OSCCON register Reset values dependent on the FOSC Configuration bits and by type of Reset.
TABLE 4-24: NVM REGISTER MAP
All
Resets
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
ERASE
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
NVMCON
NVMKEY
0760
0766
WR
—
WREN
—
WRERR
—
—
—
—
—
—
—
—
—
—
—
—
—
—
NVMOP<3:0>
0000
NVMKEY<7:0>
0000
Legend:
Note 1:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.
TABLE 4-25: PMD REGISTER MAP
All
Resets
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
—
IC8MD
—
—
IC7MD
—
—
IC1MD
—
—
—
—
—
—
—
—
—
—
OC2MD
—
PMD1
0770
0772
0774
T3MD
—
T2MD
—
T1MD
—
QEIMD PWM1MD
I2C1MD
U1MD
—
SPI1MD
AD1MD
OC1MD
—
0000
0000
0000
PMD2
—
—
IC2MD
—
—
—
—
—
PMD3
—
—
—
—
PWM2MD
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33FJ12MC201/202
4.2.6
SOFTWARE STACK
4.2.7
DATA RAM PROTECTION FEATURE
The dsPIC33F product family supports Data RAM
protection features that enable segments of RAM to be
protected when used in conjunction with Boot and
Secure Code Segment Security. BSRAM (Secure RAM
segment for BS) is accessible only from the Boot
Segment Flash code, when enabled. SSRAM (Secure
RAM segment for RAM) is accessible only from the
Secure Segment Flash code, when enabled. See
Table 4-1 for an overview of the BSRAM and SSRAM
SFRs.
In addition to its use as a working register, the W15
register in the dsPIC33FJ12MC201/202 devices is also
used as a software Stack Pointer. The Stack Pointer
always points to the first available free word and grows
from lower to higher addresses. It pre-decrements for
stack pops and post-increments for stack pushes, as
shown in Figure 4-4. For a PC push during any CALL
instruction, the MSb of the PC is zero-extended before
the push, ensuring that the MSb is always clear.
Note:
A PC push during exception processing
concatenates the SRL register to the MSb
of the PC prior to the push.
4.3
Instruction Addressing Modes
The addressing modes shown in Table 4-26 form the
basis of the addressing modes that are optimized to
support the specific features of individual instructions.
The addressing modes provided in the MAC class of
instructions differ from those provided in other
instruction types.
The Stack Pointer Limit register (SPLIM) associated
with the Stack Pointer sets an upper address boundary
for the stack. SPLIM is uninitialized at Reset. As is the
case for the Stack Pointer, SPLIM<0> is forced to ‘0’
because all stack operations must be word aligned.
Whenever an EA is generated using W15 as a source
or destination pointer, the resulting address is
compared with the value in SPLIM. If the contents of
the Stack Pointer (W15) and the SPLIM register are
equal and a push operation is performed, a stack error
trap will not occur. However, the stack error trap will
occur on a subsequent push operation. For example, to
cause a stack error trap when the stack grows beyond
address 0x0C00 in RAM, initialize the SPLIM with the
value 0x0BFE.
4.3.1
FILE REGISTER INSTRUCTIONS
Most file register instructions use a 13-bit address field
(f) to directly address data present in the first 8192
bytes of data memory (near data space). Most file
register instructions employ a working register, W0,
which is denoted as WREG in these instructions. The
destination is typically either the same file register or
WREG (with the exception of the MUL instruction),
which writes the result to a register or register pair. The
MOV instruction allows additional flexibility and can
access the entire data space.
Similarly, a Stack Pointer underflow (stack error) trap is
generated when the Stack Pointer address is found to
be less than 0x0800. This prevents the stack from
interfering with the SFR space.
4.3.2
MCU INSTRUCTIONS
A write to the SPLIM register should not be immediately
followed by an indirect read operation using W15.
The three-operand MCU instructions are of the form:
Operand 3 = Operand 1 <function> Operand 2
where Operand 1 is always a working register (that is,
the addressing mode can only be register direct), which
is referred to as Wb. Operand 2 can be a W register,
fetched from data memory, or a 5-bit literal. The result
location can be either a W register or a data memory
location. The following addressing modes are
supported by MCU instructions:
FIGURE 4-4:
CALL STACK FRAME
0x0000
15
0
• Register Direct
PC<15:0>
000000000
W15 (before CALL)
• Register Indirect
PC<22:16>
<Free Word>
• Register Indirect Post-Modified
• Register Indirect Pre-Modified
• 5-bit or 10-bit Literal
W15 (after CALL)
POP : [--W15]
PUSH: [W15++]
Note:
Not all instructions support all the
addressing modes given above.
Individual instructions can support
different subsets of these addressing
modes.
DS70265E-page 48
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
TABLE 4-26: FUNDAMENTAL ADDRESSING MODES SUPPORTED
Addressing Mode
File Register Direct
Description
The address of the file register is specified explicitly.
The contents of a register are accessed directly.
The contents of Wn forms the Effective Address (EA).
Register Direct
Register Indirect
Register Indirect Post-Modified
The contents of Wn forms the EA. Wn is post-modified (incremented
or decremented) by a constant value.
Register Indirect Pre-Modified
Wn is pre-modified (incremented or decremented) by a signed constant value
to form the EA.
Register Indirect with Register Offset The sum of Wn and Wb forms the EA.
(Register Indexed)
Register Indirect with Literal Offset
The sum of Wn and a literal forms the EA.
4.3.3
MOVE AND ACCUMULATOR
INSTRUCTIONS
4.3.4
MACINSTRUCTIONS
The dual source operand DSP instructions (CLR, ED,
EDAC, MAC, MPY, MPY.N, MOVSAC, and MSC), also
referred to as MAC instructions, use a simplified set of
addressing modes to allow the user application to
effectively manipulate the data pointers through register
indirect tables.
Move instructions and the DSP accumulator class of
instructions provide a greater degree of addressing
flexibility than other instructions. In addition to the
addressing modes supported by most MCU
instructions, move and accumulator instructions also
support Register Indirect with Register Offset
Addressing mode, also referred to as Register Indexed
mode.
The two-source operand prefetch registers must be
members of the set {W8, W9, W10, W11}. For data
reads, W8 and W9 are always directed to the X RAGU,
and W10 and W11 are always directed to the Y AGU.
The effective addresses generated (before and after
modification) must, therefore, be valid addresses within
X data space for W8 and W9 and Y data space for W10
and W11.
Note:
For the MOV instructions, the addressing
mode specified in the instruction can differ
for the source and destination EA.
However, the 4-bit Wb (Register Offset)
field is shared by both source and
destination (but typically only used by
one).
Note:
Register Indirect with Register Offset
Addressing mode is available only for W9
(in X space) and W11 (in Y space).
In summary, the following addressing modes are
supported by move and accumulator instructions:
In summary, the following addressing modes are
supported by the MACclass of instructions:
• Register Direct
• Register Indirect
• Register Indirect
• Register Indirect Post-modified
• Register Indirect Pre-modified
• Register Indirect with Register Offset (Indexed)
• Register Indirect with Literal Offset
• 8-bit Literal
• Register Indirect Post-Modified by 2
• Register Indirect Post-Modified by 4
• Register Indirect Post-Modified by 6
• Register Indirect with Register Offset (Indexed)
4.3.5
OTHER INSTRUCTIONS
• 16-bit Literal
In addition to the addressing modes outlined previously,
some instructions use literal constants of various sizes.
For example, BRA(branch) instructions use 16-bit signed
literals to specify the branch destination directly, whereas
the DISIinstruction uses a 14-bit unsigned literal field. In
some instructions, such as ADD Acc, the source of an
operand or result is implied by the opcode itself. Certain
operations, such as NOP, do not have any operands.
Note:
Not all instructions support all the
addressing modes given above. Individual
instructions may support different subsets
of these addressing modes.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 49
dsPIC33FJ12MC201/202
4.4.1
START AND END ADDRESS
4.4
Modulo Addressing
The Modulo Addressing scheme requires that a
starting and ending address be specified and loaded
into the 16-bit Modulo Buffer Address registers:
XMODSRT, XMODEND, YMODSRT, and YMODEND
(see Table 4-1).
Modulo Addressing mode is a method of providing an
automated means to support circular data buffers using
hardware. The objective is to remove the need for
software to perform data address boundary checks
when executing tightly looped code, as is typical in
many DSP algorithms.
Note:
Y space Modulo Addressing EA calcula-
tions assume word-sized data (LSb of
every EA is always clear).
Modulo Addressing can operate in either data or program
space (since the data pointer mechanism is essentially
the same for both). One circular buffer can be supported
in each of the X (which also provides the pointers into
program space) and Y data spaces. Modulo Addressing
can operate on any W register pointer. However, it is not
advisable to use W14 or W15 for Modulo Addressing
since these two registers are used as the Stack Frame
Pointer and Stack Pointer, respectively.
The length of a circular buffer is not directly specified. It
is determined by the difference between the
corresponding start and end addresses. The maximum
possible length of the circular buffer is 32K words
(64 Kbytes).
4.4.2
W ADDRESS REGISTER
SELECTION
In general, any particular circular buffer can be config-
ured to operate in only one direction as there are
certain restrictions on the buffer start address (for incre-
menting buffers), or end address (for decrementing
buffers), based upon the direction of the circular buffer.
The Modulo and Bit-Reversed Addressing Control
register, MODCON<15:0>, contains enable flags as well
as a W register field to specify the W Address registers.
The XWM and YWM fields select the registers that will
operate with Modulo Addressing:
The only exception to the usage restrictions is for
buffers that have a power-of-two length. As these
buffers satisfy the start and end address criteria, they
can operate in a bidirectional mode (that is, address
boundary checks are performed on both the lower and
upper address boundaries).
• If XWM = 15, X RAGU and X WAGU Modulo
Addressing is disabled.
• If YWM = 15, Y AGU Modulo Addressing is
disabled.
FIGURE 4-5:
MODULO ADDRESSING OPERATION EXAMPLE
MOV
MOV
MOV
MOV
MOV
MOV
#0x1100, W0
Byte
Address
W0, XMODSRT
#0x1163, W0
W0, MODEND
#0x8001, W0
W0, MODCON
;set modulo start address
;set modulo end address
;enable W1, X AGU for modulo
;W0 holds buffer fill value
;point W1 to buffer
0x1100
MOV
MOV
#0x0000, W0
#0x1110, W1
DO
MOV
AGAIN, #0x31
W0, [W1++]
;fill the 50 buffer locations
;fill the next location
0x1163
AGAIN: INC W0, W0
;increment the fill value
Start Addr = 0x1100
End Addr = 0x1163
Length = 0x0032 words
DS70265E-page 50
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
4.4.3
MODULO ADDRESSING
APPLICABILITY
4.5.1
BIT-REVERSED ADDRESSING
IMPLEMENTATION
Modulo Addressing can be applied to the Effective
Address (EA) calculation associated with any W
register. Address boundaries check for addresses
equal to:
Bit-Reversed Addressing mode is enabled in any of
these situations:
• BWM bits (W register selection) in the MODCON
register are any value other than ‘15’ (the stack
cannot be accessed using Bit-Reversed
Addressing)
• The upper boundary addresses for incrementing
buffers
• The lower boundary addresses for decrementing
buffers
• The BREN bit is set in the XBREV register
• The addressing mode used is Register Indirect
with Pre-Increment or Post-Increment
If the length of a bit-reversed buffer is M = 2N bytes,
the last ‘N’ bits of the data buffer start address must
be zeros.
It is important to realize that the address boundaries
check for addresses less than or greater than the upper
(for incrementing buffers) and lower (for decrementing
buffers) boundary addresses (not just equal to).
Address changes can, therefore, jump beyond
boundaries and still be adjusted correctly.
XB<14:0> is the Bit-Reversed Address modifier, or
‘pivot point,’ which is typically a constant. In the case of
an FFT computation, its value is equal to half of the FFT
data buffer size.
Note:
The modulo corrected effective address is
written back to the register only when Pre-
Modify or Post-Modify Addressing mode is
used to compute the effective address.
When an address offset (such as [W7 +
W2]) is used, Modulo Address correction
is performed, but the contents of the
register remain unchanged.
Note:
All bit-reversed EA calculations assume
word-sized data (LSb of every EA is
always clear). The XB value is scaled
accordingly to generate compatible (byte)
addresses.
When enabled, Bit-Reversed Addressing is executed
only for Register Indirect with Pre-Increment or Post-
Increment Addressing, and word-sized data writes. It
will not function for any other addressing mode or for
byte-sized data, and normal addresses are generated
instead. When Bit-Reversed Addressing is active, the
W Address Pointer is always added to the address
modifier (XB), and the offset associated with the
Register Indirect Addressing mode is ignored. In
addition, as word-sized data is a requirement, the LSb
of the EA is ignored (and always clear).
4.5
Bit-Reversed Addressing
Bit-Reversed Addressing mode is intended to simplify
data reordering for radix-2 FFT algorithms. It is
supported by the X AGU for data writes only.
The modifier, which can be a constant value or register
contents, is regarded as having its bit order reversed. The
address source and destination are kept in normal order.
Thus, the only operand requiring reversal is the modifier.
Note:
Modulo Addressing and Bit-Reversed
Addressing should not be enabled
together. If an application attempts to do
so, Bit-Reversed Addressing will assume
priority, when active, for the X WAGU, and
X WAGU, Modulo Addressing will be
disabled. However, Modulo Addressing will
continue to function in the X RAGU.
If Bit-Reversed Addressing has already been enabled
by setting the BREN (XBREV<15>) bit, a write to the
XBREV register should not be immediately followed by
an indirect read operation using the W register that has
been designated as the bit-reversed pointer.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 51
dsPIC33FJ12MC201/202
FIGURE 4-6:
BIT-REVERSED ADDRESS EXAMPLE
Sequential Address
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1
0
Bit Locations Swapped Left-to-Right
Around Center of Binary Value
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1 b2 b3 b4
0
Bit-Reversed Address
Pivot Point
XB = 0x0008 for a 16-Word, Bit-Reversed Buffer
TABLE 4-27: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY)
Normal Address Bit-Reversed Address
A3
A2
A1
A0
Decimal
A3
A2
A1
A0
Decimal
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
8
2
4
3
12
2
4
5
10
6
6
7
14
1
8
9
9
10
11
12
13
14
15
5
13
3
11
7
15
DS70265E-page 52
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
4.6.1
ADDRESSING PROGRAM SPACE
4.6
Interfacing Program and Data
Memory Spaces
Since the address ranges for the data and program
spaces are 16 and 24 bits, respectively, a method is
needed to create a 23-bit or 24-bit program address
from 16-bit data registers. The solution depends on the
interface method to be used.
The dsPIC33FJ12MC201/202 architecture uses a 24-
bit-wide program space and a 16-bit-wide data space.
The architecture is also a modified Harvard scheme,
meaning that data can also be present in the program
space. To use this data successfully, it must be
accessed in a way that preserves the alignment of
information in both spaces.
For table operations, the 8-bit Table Page register
(TBLPAG) is used to define a 32K word region within
the program space. This is concatenated with a 16-bit
EA to arrive at a full 24-bit program space address. In
this format, the MSb of TBLPAG is used to determine if
the operation occurs in the user memory (TBLPAG<7>
= 0) or the configuration memory (TBLPAG<7> = 1).
Aside from normal execution, the dsPIC33FJ12MC201/
202 architecture provides two methods by which
program space can be accessed during operation:
• Using table instructions to access individual
bytes, or words, anywhere in the program space
For remapping operations, the 8-bit Program Space
Visibility register (PSVPAG) is used to define a
16K word page in the program space. When the MSb
of the EA is ‘1’, PSVPAG is concatenated with the lower
15 bits of the EA to form a 23-bit program space
address. Unlike table operations, this limits remapping
operations strictly to the user memory area.
• Remapping a portion of the program space into
the data space (Program Space Visibility)
Table instructions allow an application to read or write
to small areas of the program memory. This capability
makes the method ideal for accessing data tables that
need to be updated periodically. It also allows access
to all bytes of the program word. The remapping
method allows an application to access a large block of
data on a read-only basis, which is ideal for lookups
from a large table of static data. The application can
only access the lsw of the program word.
Table 4-28 and Figure 4-7 show how the program EA is
created for table operations and remapping accesses
from the data EA.
TABLE 4-28: PROGRAM SPACE ADDRESS CONSTRUCTION
Program Space Address
Access
Space
Access Type
<23>
<22:16>
<15>
<14:1>
<0>
Instruction Access
(Code Execution)
User
User
0
PC<22:1>
0
0xx xxxx xxxx xxxx xxxx xxx0
TBLRD/TBLWT
(Byte/Word Read/Write)
TBLPAG<7:0>
0xxx xxxx
Data EA<15:0>
xxxx xxxx xxxx xxxx
Data EA<15:0>
Configuration
TBLPAG<7:0>
1xxx xxxx
xxxx xxxx xxxx xxxx
Program Space Visibility User
(Block Remap/Read)
0
PSVPAG<7:0>
xxxx xxxx
Data EA<14:0>(1)
0
xxx xxxx xxxx xxxx
Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of
the address is PSVPAG<0>.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 53
dsPIC33FJ12MC201/202
FIGURE 4-7:
DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
Program Counter(1)
Program Counter
23 bits
0
0
1/0
EA
Table Operations(2)
1/0
TBLPAG
8 bits
16 bits
24 bits
Select
1
0
EA
Program Space Visibility(1)
(Remapping)
0
PSVPAG
8 bits
15 bits
23 bits
Byte Select
User/Configuration
Space Select
Note 1: The Least Significant bit of program space addresses is always fixed as ‘0’ to
maintain word alignment of data in the program and data spaces.
2: Table operations are not required to be word aligned. Table read operations are permitted
in the configuration memory space.
DS70265E-page 54
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
• TBLRDH (Table Read High):
4.6.2
DATA ACCESS FROM PROGRAM
MEMORY USING TABLE
INSTRUCTIONS
- In Word mode, this instruction maps the entire
upper word of a program address (P<23:16>)
to a data address. Note that D<15:8>, the
‘phantom byte’, will always be ‘0’.
The TBLRDL and TBLWTL instructions offer a direct
method of reading or writing the lower word of any
address within the program space without going
through data space. The TBLRDH and TBLWTH
instructions are the only method to read or write the
upper 8 bits of a program space word as data.
- In Byte mode, this instruction maps the upper
or lower byte of the program word to D<7:0>
of the data address, in the TBLRDL instruc-
tion. The data is always ‘0’ when the upper
‘phantom’ byte is selected (Byte Select = 1).
The PC is incremented by two for each successive
24-bit program word. This allows program memory
addresses to directly map to data space addresses.
Program memory can thus be regarded as two 16-bit-
wide word address spaces, residing side by side, each
with the same address range. TBLRDL and TBLWTL
access the space that contains the least significant
data word. TBLRDHand TBLWTHaccess the space that
contains the upper data byte.
In a similar fashion, two table instructions, TBLWTH
and TBLWTL, are used to write individual bytes or
words to a program space address. The details of
their operation are explained in Section 5.0 “Flash
Program Memory”.
For all table operations, the area of program memory
space to be accessed is determined by the Table Page
register (TBLPAG). TBLPAG covers the entire program
memory space of the device, including user and
configuration spaces. When TBLPAG<7> = 0, the table
page is located in the user memory space. When
TBLPAG<7> = 1, the page is located in configuration
space.
Two table instructions are provided to move byte or
word-sized (16-bit) data to and from program space.
Both function as either byte or word operations.
• TBLRDL(Table Read Low):
- In Word mode, this instruction maps the
lower word of the program space location
(P<15:0>) to a data address (D<15:0>).
- In Byte mode, either the upper or lower byte
of the lower program word is mapped to the
lower byte of a data address. The upper byte
is selected when Byte Select is ‘1’; the lower
byte is selected when it is ‘0’.
FIGURE 4-8:
ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS
Program Space
TBLPAG
02
23
15
0
0x000000
23
16
8
0
00000000
00000000
00000000
0x020000
0x030000
00000000
‘Phantom’ Byte
TBLRDH.B (Wn<0> = 0)
TBLRDL.B (Wn<0> = 1)
TBLRDL.B (Wn<0> = 0)
TBLRDL.W
The address for the table operation is determined by the data EA
within the page defined by the TBLPAG register.
Only read operations are shown; write operations are also valid in
the user memory area.
0x800000
© 2007-2011 Microchip Technology Inc.
DS70265E-page 55
dsPIC33FJ12MC201/202
24-bit program word are used to contain the data. The
upper 8 bits of any program space location used as
data should be programmed with ‘1111 1111’ or
‘0000 0000’ to force a NOP. This prevents possible
issues should the area of code ever be accidentally
executed.
4.6.3
READING DATA FROM PROGRAM
MEMORY USING PROGRAM SPACE
VISIBILITY
The upper 32 Kbytes of data space may optionally be
mapped into any 16K word page of the program space.
This option provides transparent access to stored
constant data from the data space without the need to
use special instructions (such as TBLRDL and
TBLRDH).
Note:
PSV access is temporarily disabled during
table reads/writes.
For operations that use PSV and are executed outside
a REPEAT loop, the MOV and MOV.D instructions
require one instruction cycle in addition to the specified
execution time. All other instructions require two
instruction cycles in addition to the specified execution
time.
Program space access through the data space occurs
if the MSb of the data space EA is ‘1’ and program
space visibility is enabled by setting the PSV bit in the
Core Control register (CORCON<2>). The location of
the program memory space to be mapped into the data
space is determined by the Program Space Visibility
Page register (PSVPAG). This 8-bit register defines
any one of 256 possible pages of 16K words in
program space. In effect, PSVPAG functions as the
upper 8 bits of the program memory address, with the
15 bits of the EA functioning as the lower bits. By
incrementing the PC by 2 for each program memory
word, the lower 15 bits of data space addresses directly
map to the lower 15 bits in the corresponding program
space addresses.
For operations that use PSV, and are executed inside
a REPEATloop, these instances require two instruction
cycles in addition to the specified execution time of the
instruction:
• Execution in the first iteration
• Execution in the last iteration
• Execution prior to exiting the loop due to an
interrupt
• Execution upon re-entering the loop after an
interrupt is serviced
Data reads to this area add a cycle to the instruction
being executed, since two program memory fetches
are required.
Any other iteration of the REPEAT loop will allow the
instruction using PSV to access data, to execute in a
single cycle.
Although each data space address 0x8000 and higher
maps directly into a corresponding program memory
address (see Figure 4-9), only the lower 16 bits of the
FIGURE 4-9:
PROGRAM SPACE VISIBILITY OPERATION
When CORCON<2> = 1and EA<15> = 1:
Program Space
Data Space
PSVPAG
02
23
15
0
0x000000
0x0000
Data EA<14:0>
0x010000
0x018000
The data in the page
designated by
PSVPAG is mapped
into the upper half of
the data memory
space...
0x8000
PSV Area
...whilethelower15bits
of the EA specify an
exact address within
the PSV area. This
corresponds exactly to
the same lower 15 bits
of the actual program
space address.
0xFFFF
0x800000
DS70265E-page 56
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
unprogrammed devices, and then program the digital
signal controller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed.
5.0
FLASH PROGRAM MEMORY
Note 1: This data sheet summarizes the features
of the dsPIC33FJ12MC201/202 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 5. “Flash Pro-
RTSP is accomplished using TBLRD (table read) and
TBLWT (table write) instructions. With RTSP, the user
application can write program memory data either in
blocks or ‘rows’ of 64 instructions (192 bytes) or a sin-
gle program memory word, and erase program mem-
ory in blocks or ‘pages’ of 512 instructions (1536
bytes).
gramming”
(DS70191)
of
the
“dsPIC33F/PIC24H Family Reference
Manual”, which is available from the
Microchip website (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
5.1
Table Instructions and Flash
Programming
Regardless of the method used, all programming of
Flash memory is done with the table-read and table-
write instructions. These allow direct read and write
access to the program memory space from the data
memory while the device is in normal operating mode.
The 24-bit target address in the program memory is
formed using bits <7:0> of the TBLPAG register and the
Effective Address (EA) from a W register specified in
the table instruction, as shown in Figure 5-1.
The dsPIC33FJ12MC201/202 devices contain internal
Flash program memory for storing and executing
application code. The memory is readable, writable,
and erasable during normal operation over the entire
VDD range.
Flash memory can be programmed in two ways:
The TBLRDLand the TBLWTLinstructions are used to
read or write to bits <15:0> of program memory.
TBLRDLand TBLWTLcan access program memory in
both Word and Byte modes.
• In-Circuit Serial Programming™ (ICSP™)
programming capability
• Run-Time Self-Programming (RTSP)
The TBLRDHand TBLWTHinstructions are used to read
or write to bits <23:16> of program memory. TBLRDH
and TBLWTHcan also access program memory in Word
or Byte mode.
ICSP allows a dsPIC33FJ12MC201/202 device to be
serially programmed while in the end application circuit.
This is done with two lines for programming clock and
programming data (one of the alternate programming
pin pairs: PGECx/PGEDx), and three other lines for
power (VDD), ground (VSS) and Master Clear (MCLR).
This allows users to manufacture boards with
FIGURE 5-1:
ADDRESSING FOR TABLE REGISTERS
24 bits
Program Counter
Using
Program Counter
0
0
Working Reg EA
Using
Table Instruction
1/0
TBLPAG Reg
8 bits
16 bits
User/Configuration
Space Select
Byte
Select
24-bit EA
© 2007-2011 Microchip Technology Inc.
DS70265E-page 57
dsPIC33FJ12MC201/202
For example, if the device is operating at +125°C, the
FRC accuracy will be ±5%. If the TUN<5:0> bits (see
Register 8-4) are set to ‘b111111, the minimum row
write time is equal to Equation 5-2.
5.2
RTSP Operation
The dsPIC33FJ12MC201/202 Flash program memory
array is organized into rows of 64 instructions or 192
bytes. RTSP allows the user application to erase a
page of memory, which consists of eight rows (512
instructions); and to program one row or one word.
Table 24-12 shows typical erase and programming
times. The 8-row erase pages and single row write
rows are edge-aligned from the beginning of program
memory, on boundaries of 1536 bytes and 192 bytes,
respectively.
EQUATION 5-2:
MINIMUM ROW WRITE
TIME
11064 Cycles
7.37 MHz × (1 + 0.05) × (1 – 0.00375)
------------------------------------------------------------------------------------------------
= 1.435ms
TRW
=
The program memory implements holding buffers that
can contain 64 instructions of programming data. Prior
to the actual programming operation, the write data
must be loaded into the buffers sequentially. The
instruction words loaded must always be from a group
of 64 boundary.
The maximum row write time is equal to Equation 5-3.
EQUATION 5-3:
MAXIMUM ROW WRITE
TIME
11064 Cycles
7.37 MHz × (1 – 0.05) × (1 – 0.00375)
-----------------------------------------------------------------------------------------------
= 1.586ms
TRW
=
The basic sequence for RTSP programming is to set up
a Table Pointer, then do a series of TBLWTinstructions
to load the buffers. Programming is performed by
setting the control bits in the NVMCON register. A total
of 64 TBLWTL and TBLWTH instructions are required
to load the instructions.
Setting the WR bit (NVMCON<15>) starts the
operation, and the WR bit is automatically cleared
when the operation is finished.
All of the table write operations are single-word writes
(two instruction cycles) because only the buffers are
5.4
Control Registers
written.
A
programming cycle is required for
Two SFRs are used to read and write the program
Flash memory: NVMCON and NVMKEY.
programming each row.
The NVMCON register (Register 5-1) controls which
blocks are to be erased, which memory type is to be
programmed, and the start of the programming cycle.
5.3
Programming Operations
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode. The processor stalls (waits) until the operation is
finished.
NVMKEY is a write-only register that is used for write
protection. To start a programming or erase sequence,
the user application must consecutively write 0x55 and
0xAA to the NVMKEY register. Refer to Section 5.3
“Programming Operations” for further details.
The programming time depends on the FRC accuracy
(see Table 24-18) and the value of the FRC Oscillator
Tuning register (see Register 8-4). Use the following
formula to calculate the minimum and maximum values
for the Row Write Time, Page Erase Time, and Word
Write Cycle Time parameters (see Table 24-12).
EQUATION 5-1:
PROGRAMMING TIME
T
---------------------------------------------------------------------------------------------------------------------------
7.37 MHz × (FRC Accuracy)% × (FRC Tuning)%
DS70265E-page 58
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
REGISTER 5-1:
NVMCON: FLASH MEMORY CONTROL REGISTER
R/SO-0(1)
WR
R/W-0(1)
WREN
R/W-0(1)
WRERR
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0(1)
bit 0
U-0
—
R/W-0(1)
ERASE
U-0
—
U-0
—
R/W-0(1)
R/W-0(1)
R/W-0(1)
NVMOP<3:0>(2)
bit 7
Legend:
SO = Settable only bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
WR: Write Control bit
1= Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is
cleared by hardware once operation is complete
0= Program or erase operation is complete and inactive
bit 14
bit 13
WREN: Write Enable bit
1= Enable Flash program/erase operations
0= Inhibit Flash program/erase operations
WRERR: Write Sequence Error Flag bit
1= An improper program or erase sequence attempt or termination has occurred (bit is set
automatically on any set attempt of the WR bit)
0= The program or erase operation completed normally
bit 12-7
bit 6
Unimplemented: Read as ‘0’
ERASE: Erase/Program Enable bit
1= Perform the erase operation specified by NVMOP<3:0> on the next WR command
0= Perform the program operation specified by NVMOP<3:0> on the next WR command
bit 5-4
bit 3-0
Unimplemented: Read as ‘0’
NVMOP<3:0>: NVM Operation Select bits(2)
If ERASE = 1:
1111= Memory bulk erase operation
1101= Erase General Segment
1100= Erase Secure Segment
0011= No operation
0010= Memory page erase operation
0001= No operation
0000= Erase a single Configuration register byte
If ERASE = 0:
1111= No operation
1101= No operation
1100= No operation
0011= Memory word program operation
0010= No operation
0001= Memory row program operation
0000= Program a single Configuration register byte
Note 1: These bits can only be reset on POR.
2: All other combinations of NVMOP<3:0> are unimplemented.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 59
dsPIC33FJ12MC201/202
REGISTER 5-2:
NVMKEY: NONVOLATILE MEMORY KEY REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
W-0
bit 7
W-0
W-0
W-0
W-0
W-0
W-0
W-0
NVMKEY<7:0>
Legend:
SO = Settable only bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7-0
Unimplemented: Read as ‘0’
NVMKEY<7:0>: Key Register (write-only) bits
DS70265E-page 60
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
5. Write the program block to Flash memory:
5.4.1
PROGRAMMING ALGORITHM FOR
FLASH PROGRAM MEMORY
a) Set the NVMOP bits to ‘0001’ to configure
for row programming. Clear the ERASE bit
and set the WREN bit.
Programmers can program one row of program Flash
memory at a time. To do this, it is necessary to erase
the 8-row erase page that contains the desired row.
The general process is:
b) Write 0x55 to NVMKEY.
c) Write 0xAA to NVMKEY.
d) Set the WR bit. The programming cycle
begins and the CPU stalls for the duration of
the write cycle. When the write to Flash mem-
ory is done, the WR bit is cleared
automatically.
1. Read eight rows of program memory
(512 instructions) and store in data RAM.
2. Update the program data in RAM with the
desired new data.
3. Erase the block (see Example 5-1):
6. Repeat steps 4 and 5, using the next available
64 instructions from the block in data RAM by
incrementing the value in TBLPAG, until all
512 instructions are written back to Flash memory.
a) Set the NVMOP bits (NVMCON<3:0>) to
‘0010’ to configure for block erase. Set the
ERASE (NVMCON<6>) and WREN
(NVMCON<14>) bits.
For protection against accidental operations, the write
initiate sequence for NVMKEY must be used to allow
any erase or program operation to proceed. After the
programming command has been executed, the user
application must wait for the programming time until
programming is complete. The two instructions
following the start of the programming sequence
should be NOPs, as shown in Example 5-3.
b) Write the starting address of the page to be
erased into the TBLPAG and W registers.
c) Write 0x55 to NVMKEY.
d) Write 0xAA to NVMKEY.
e) Set the WR bit (NVMCON<15>). The erase
cycle begins and the CPU stalls for the dura-
tion of the erase cycle. When the erase is
done, the WR bit is cleared automatically.
4. Write the first 64 instructions from data RAM into
the program memory buffers (see Example 5-2).
EXAMPLE 5-1:
ERASING A PROGRAM MEMORY PAGE
; Set up NVMCON for block erase operation
MOV
MOV
#0x4042, W0
W0, NVMCON
;
; Initialize NVMCON
; Init pointer to row to be ERASED
MOV
MOV
MOV
#tblpage(PROG_ADDR), W0
W0, TBLPAG
#tbloffset(PROG_ADDR), W0
;
; Initialize PM Page Boundary SFR
; Initialize in-page EA[15:0] pointer
; Set base address of erase block
; Block all interrupts with priority <7
; for next 5 instructions
TBLWTL W0, [W0]
DISI
#5
MOV
MOV
MOV
MOV
BSET
NOP
NOP
#0x55, W0
W0, NVMKEY
#0xAA, W1
W1, NVMKEY
NVMCON, #WR
; Write the 55 key
;
; Write the AA key
; Start the erase sequence
; Insert two NOPs after the erase
; command is asserted
© 2007-2011 Microchip Technology Inc.
DS70265E-page 61
dsPIC33FJ12MC201/202
EXAMPLE 5-2:
LOADING THE WRITE BUFFERS
; Set up NVMCON for row programming operations
MOV
MOV
#0x4001, W0
W0, NVMCON
;
; Initialize NVMCON
; Set up a pointer to the first program memory location to be written
; program memory selected, and writes enabled
MOV
MOV
MOV
#0x0000, W0
W0, TBLPAG
#0x6000, W0
;
; Initialize PM Page Boundary SFR
; An example program memory address
; Perform the TBLWT instructions to write the latches
; 0th_program_word
MOV
MOV
#LOW_WORD_0, W2
#HIGH_BYTE_0, W3
;
;
TBLWTL W2, [W0]
TBLWTH W3, [W0++]
; Write PM low word into program latch
; Write PM high byte into program latch
; 1st_program_word
MOV
MOV
#LOW_WORD_1, W2
#HIGH_BYTE_1, W3
;
;
TBLWTL W2, [W0]
TBLWTH W3, [W0++]
; Write PM low word into program latch
; Write PM high byte into program latch
;
2nd_program_word
MOV
MOV
#LOW_WORD_2, W2
#HIGH_BYTE_2, W3
;
;
TBLWTL W2, [W0]
TBLWTH W3, [W0++]
; Write PM low word into program latch
; Write PM high byte into program latch
•
•
•
; 63rd_program_word
MOV
MOV
#LOW_WORD_31, W2
#HIGH_BYTE_31, W3
;
;
TBLWTL W2, [W0]
TBLWTH W3, [W0++]
; Write PM low word into program latch
; Write PM high byte into program latch
EXAMPLE 5-3:
INITIATING A PROGRAMMING SEQUENCE
DISI
#5
; Block all interrupts with priority <7
; for next 5 instructions
MOV
MOV
MOV
MOV
BSET
NOP
NOP
#0x55, W0
W0, NVMKEY
#0xAA, W1
W1, NVMKEY
NVMCON, #WR
; Write the 55 key
;
; Write the AA key
; Start the erase sequence
; Insert two NOPs after the
; erase command is asserted
DS70265E-page 62
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
A simplified block diagram of the Reset module is
shown in Figure 6-1.
6.0
RESETS
Note 1: This data sheet summarizes the features
of the dsPIC33FJ12MC201/202 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 8. “Reset”
(DS70192) of the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microchip website
(www.microchip.com).
Any active source of Reset will make the SYSRST
signal active. On system Reset, some of the registers
associated with the CPU and peripherals are forced to
a known Reset state, and some are unaffected.
Note:
Refer to the specific peripheral section or
Section 3.0 “CPU” of this manual for
register Reset states.
All types of device Reset set a corresponding status bit
in the RCON register to indicate the type of Reset (see
Register 6-1).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
All bits that are set, with the exception of the POR bit
(RCON<0>), are cleared during a POR event. The user
application can set or clear any bit at any time during
code execution. The RCON bits only serve as status
bits. Setting a particular Reset status bit in software
does not cause a device Reset to occur.
The Reset module combines all Reset sources and
controls the device Master Reset Signal, SYSRST. The
following is a list of device Reset sources:
The RCON register also has other bits associated with
the Watchdog Timer and device power-saving states.
The function of these bits is discussed in other sections
of this data sheet.
• POR: Power-on Reset
• BOR: Brown-out Reset
• MCLR: Master Clear Pin Reset
• SWR: RESETInstruction
Note:
The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset is meaningful.
• WDTO: Watchdog Timer Reset
• CM: Configuration Mismatch Reset
• TRAPR: Trap Conflict Reset
• IOPUWR: Illegal Condition Device Reset
- Illegal Opcode Reset
- Uninitialized W Register Reset
- Security Reset
FIGURE 6-1:
RESET SYSTEM BLOCK DIAGRAM
RESETInstruction
Glitch Filter
MCLR
WDT
Module
Sleep or Idle
BOR
Internal
Regulator
SYSRST
VDD
POR
VDD Rise
Detect
Trap Conflict
Illegal Opcode
Uninitialized W Register
Configuration Mismatch
© 2007-2011 Microchip Technology Inc.
DS70265E-page 63
dsPIC33FJ12MC201/202
(1)
REGISTER 6-1:
RCON: RESET CONTROL REGISTER
R/W-0
TRAPR
bit 15
R/W-0
U-0
—
U-0
—
U-0
U-0
—
R/W-0
CM
R/W-0
IOPUWR
—
VREGS
bit 8
R/W-0
EXTR
R/W-0
SWR
R/W-0
SWDTEN(2)
R/W-0
WDTO
R/W-0
R/W-0
IDLE
R/W-1
BOR
R/W-1
POR
SLEEP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
bit 14
TRAPR: Trap Reset Flag bit
1= A Trap Conflict Reset has occurred
0= A Trap Conflict Reset has not occurred
IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit
1= An illegal opcode detection, an illegal address mode or uninitialized W register used as an
Address Pointer caused a Reset
0= An illegal opcode or uninitialized W Reset has not occurred
bit 13-10
bit 9
Unimplemented: Read as ‘0’
CM: Configuration Mismatch Flag bit
1= A configuration mismatch Reset has occurred
0= A configuration mismatch Reset has not occurred
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
VREGS: Voltage Regulator Standby During Sleep bit
1= Voltage regulator is active during Sleep
0= Voltage regulator goes into Standby mode during Sleep
EXTR: External Reset (MCLR) Pin bit
1= A Master Clear (pin) Reset has occurred
0= A Master Clear (pin) Reset has not occurred
SWR: Software Reset (Instruction) Flag bit
1= A RESETinstruction has been executed
0= A RESETinstruction has not been executed
SWDTEN: Software Enable/Disable of WDT bit(2)
1= WDT is enabled
0= WDT is disabled
WDTO: Watchdog Timer Time-out Flag bit
1= WDT time-out has occurred
0= WDT time-out has not occurred
SLEEP: Wake-up from Sleep Flag bit
1= Device has been in Sleep mode
0= Device has not been in Sleep mode
IDLE: Wake-up from Idle Flag bit
1= Device was in Idle mode
0= Device was not in Idle mode
Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
DS70265E-page 64
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
(1)
REGISTER 6-1:
RCON: RESET CONTROL REGISTER (CONTINUED)
bit 1
BOR: Brown-out Reset Flag bit
1= A Brown-out Reset has occurred
0= A Brown-out Reset has not occurred
bit 0
POR: Power-on Reset Flag bit
1= A Power-on Reset has occurred
0= A Power-on Reset has not occurred
Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 65
dsPIC33FJ12MC201/202
The device is kept in a Reset state until the system
power supplies have stabilized at appropriate levels
and the oscillator clock is ready. The sequence in
which this occurs is detailed below and is shown in
Figure 6-2.
6.1
System Reset
The dsPIC33FJ12MC201/202 family of devices have
two types of Reset:
• Cold Reset
• Warm Reset
A cold Reset is the result of a POR or a BOR. On a cold
Reset, the FNOSC configuration bits in the FOSC
device configuration register selects the device clock
source.
A warm Reset is the result of all other Reset sources,
including the RESET instruction. On warm Reset, the
device will continue to operate from the current clock
source as indicated by the Current Oscillator Selection
(COSC<2:0>) bits in the Oscillator Control
(OSCCON<14:12>) register.
TABLE 6-1:
OSCILLATOR DELAY
Oscillator
Oscillator Startup
Timer
Oscillator Mode
PLL Lock Time
Total Delay
Startup Delay
FRC, FRCDIV16,
FRCDIVN
TOSCD
—
—
TOSCD
FRCPLL
XT
TOSCD
TOSCD
TOSCD
—
—
TOST
TOST
—
TLOCK
—
TOSCD + TLOCK
TOSCD + TOST
TOSCD + TOST
—
HS
—
EC
—
XTPLL
HSPLL
ECPLL
SOSC
LPRC
TOSCD
TOSCD
—
TOST
TOST
—
TLOCK
TLOCK
TLOCK
—
TOSCD + TOST + TLOCK
TOSCD + TOST + TLOCK
TLOCK
TOSCD
TOSCD
TOST
—
TOSCD + TOST
TOSCD
—
Note 1: TOSCD = Oscillator Start-up Delay (1.1 μs max for FRC, 70 μs max for LPRC). Crystal Oscillator start-up
times vary with crystal characteristics, load capacitance, etc.
2: TOST = Oscillator Start-up Timer Delay (1024 oscillator clock period). For example, TOST = 102.4 μs for a
10 MHz crystal and TOST = 32 ms for a 32 kHz crystal.
3: TLOCK = PLL lock time (1.5 ms nominal), if PLL is enabled.
DS70265E-page 66
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
FIGURE 6-2:
SYSTEM RESET TIMING
VBOR
Vbor
VPOR
TPOR
VDD
1
POR
BOR
TBOR
2
3
TPWRT
SYSRST
4
Oscillator Clock
TLOCK
TOSCD
TOST
6
TFSCM
FSCM
5
Reset
Device Status
Run
Time
1.
2.
3.
POR: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is active until VDD crosses the
VPOR threshold and the delay TPOR has elapsed.
BOR: The on-chip voltage regulator has a BOR circuit that keeps the device in Reset until VDD crosses the VBOR threshold and the
delay TBOR has elapsed. The delay TBOR ensures the voltage regulator output becomes stable.
PWRT Timer: The programmable power-up timer continues to hold the processor in Reset for a specific period of time (TPWRT)
after a BOR. The delay TPWRT ensures that the system power supplies have stabilized at the appropriate level for full-speed oper-
ation. After the delay TPWRT has elapsed, the SYSRST becomes inactive, which in turn enables the selected oscillator to start gen-
erating clock cycles.
4.
5.
6.
Oscillator Delay: The total delay for the clock to be ready for various clock source selections are given in Table 6-1. Refer to
Section 8.0 “Oscillator Configuration” for more information.
When the oscillator clock is ready, the processor begins execution from location 0x000000. The user application programs a GOTO
instruction at the Reset address, which redirects program execution to the appropriate start-up routine.
The Fail-safe clock monitor (FSCM), if enabled, begins to monitor the system clock when the system clock is ready and the delay
TFSCM elapsed.
TABLE 6-2:
Symbol
OSCILLATOR PARAMETERS
Note: When the device exits the Reset condi-
tion (begins normal operation), the
device operating parameters (voltage,
frequency, temperature, etc.) must be
within their operating ranges, other-
wise the device may not function cor-
rectly. The user application must
ensure that the delay between the time
power is first applied, and the time
SYSRST becomes inactive, is long
enough to get all operating parameters
within specification.
Parameter
Value
VPOR
TPOR
VBOR
TBOR
TPWRT
POR threshold
1.8V nominal
POR extension time 30 μs maximum
BOR threshold 2.5V nominal
BOR extension time 100 μs maximum
Programmable
0-128 ms nominal
power-up time delay
TFSCM
Fail-safe Clock
Monitor Delay
900 μs maximum
© 2007-2011 Microchip Technology Inc.
DS70265E-page 67
dsPIC33FJ12MC201/202
6.2
POR
6.3
BOR and PWRT
A POR circuit ensures the device is reset from power-
on. The POR circuit is active until VDD crosses the
VPOR threshold and the delay TPOR has elapsed. The
delay TPOR ensures the internal device bias circuits
become stable.
The on-chip regulator has a BOR circuit that resets the
device when the VDD is too low (VDD < VBOR) for proper
device operation. The BOR circuit keeps the device in
Reset until VDD crosses the VBOR threshold and the
delay TBOR has elapsed. The delay TBOR ensures the
voltage regulator output becomes stable.
The device supply voltage characteristics must meet
the specified starting voltage and rise rate
requirements to generate the POR. Refer to
Section 24.0 “Electrical Characteristics” for details.
The BOR status (BOR) bit in the Reset Control
(RCON<1>) register is set to indicate the Brown-out
Reset.
The POR status (POR) bit in the Reset Control
(RCON<0>) register is set to indicate the Power-on
Reset.
The device will not run at full speed after a BOR as the
VDD should rise to acceptable levels for full-speed
operation. The PWRT provides power-up time delay
(TPWRT) to ensure that the system power supplies have
stabilized at the appropriate levels for full-speed
operation before the SYSRST is released.
The power-up timer delay (TPWRT) is programmed by
the
Power-on
Reset
Timer
Value
Select
(FPWRT<2:0>) bits in the POR Configuration
(FPOR<2:0>) register, which provides eight settings
(from 0 ms to 128 ms). Refer to Section 21.0 “Special
Features” for further details.
Figure 6-3 shows the typical brown-out scenarios. The
Reset delay (TBOR + TPWRT) is initiated each time VDD
rises above the VBOR trip point.
FIGURE 6-3:
BROWN-OUT SITUATIONS
VDD
VBOR
TBOR + TPWRT
SYSRST
VDD
VBOR
TBOR + TPWRT
SYSRST
VDD dips before PWRTexpires
VDD
VBOR
TBOR + TPWRT
SYSRST
DS70265E-page 68
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
6.4
External Reset (EXTR)
6.7
Trap Conflict Reset
The external Reset is generated by driving the MCLR
pin low. The MCLR pin is a Schmitt trigger input with an
additional glitch filter. Reset pulses that are longer than
the minimum pulse width will generate a Reset. Refer
to Section 24.0 “Electrical Characteristics” for
minimum pulse width specifications. The External
Reset (MCLR) Pin (EXTR) bit in the Reset Control
(RCON) register is set to indicate the MCLR Reset.
If a lower-priority hard trap occurs while a higher-prior-
ity trap is being processed, a hard trap conflict Reset
occurs. The hard traps include exceptions of priority
level 13 through level 15, inclusive. The address error
(level 13) and oscillator error (level 14) traps fall into
this category.
The Trap Reset Flag (TRAPR) bit in the Reset Control
(RCON<15>) register is set to indicate the Trap Conflict
Reset. Refer to Section 7.0 “Interrupt Controller” for
more information on trap conflict Resets.
6.4.1
EXTERNAL SUPERVISORY CIRCUIT
Many systems have external supervisory circuits that
generate Reset signals to Reset multiple devices in the
system. This external Reset signal can be directly con-
nected to the MCLR pin to Reset the device when the
rest of system is Reset.
6.8
Configuration Mismatch Reset
To maintain the integrity of the peripheral pin select
control registers, they are constantly monitored with
shadow registers in hardware. If an unexpected
change in any of the registers occur (such as cell dis-
turbances caused by ESD or other external events), a
configuration mismatch Reset occurs.
6.4.2
INTERNAL SUPERVISORY CIRCUIT
When using the internal power supervisory circuit to
Reset the device, the external Reset pin (MCLR)
should be tied directly or resistively to VDD. In this case,
the MCLR pin will not be used to generate a Reset. The
external Reset pin (MCLR) does not have an internal
pull-up and must not be left unconnected.
The Configuration Mismatch Flag (CM) bit in the
Reset Control (RCON<9>) register is set to indicate
the configuration mismatch Reset. Refer to
Section 10.0 “I/O Ports” for more information on the
configuration mismatch Reset.
Note:
The configuration mismatch feature and
associated Reset flag is not available on
all devices.
6.5
Software RESET Instruction (SWR)
Whenever the RESET instruction is executed, the
device will assert SYSRST, placing the device in a
special Reset state. This Reset state will not re-
initialize the clock. The clock source in effect prior to the
RESETinstruction will remain. SYSRST is released at
the next instruction cycle, and the Reset vector fetch
will commence.
6.9
Illegal Condition Device Reset
An illegal condition device Reset occurs due to the
following sources:
• Illegal Opcode Reset
• Uninitialized W Register Reset
• Security Reset
The Software Reset (Instruction) Flag (SWR) bit in the
Reset Control (RCON<6>) register is set to indicate
the software Reset.
The Illegal Opcode or Uninitialized W Access Reset
Flag (IOPUWR) bit in the Reset Control (RCON<14>)
register is set to indicate the illegal condition device
Reset.
6.6
Watchdog Time-out Reset (WDTO)
Whenever a Watchdog Time-out occurs, the device
will asynchronously assert SYSRST. The clock source
will remain unchanged. A WDT time-out during Sleep
or Idle mode will wake-up the processor, but will not
reset the processor.
The Watchdog Timer Time-out Flag (WDTO) bit in the
Reset Control (RCON<4>) register is set to indicate
the Watchdog Reset. Refer to Section 21.4
“Watchdog Timer (WDT)” for more information on
Watchdog Reset.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 69
dsPIC33FJ12MC201/202
6.9.1
ILLEGAL OPCODE RESET
6.10 Using the RCON Status Bits
A device Reset is generated if the device attempts to
execute an illegal opcode value that is fetched from
program memory.
The user application can read the Reset Control
(RCON) register after any device Reset to determine
the cause of the Reset.
The illegal opcode Reset function can prevent the
device from executing program memory sections that
are used to store constant data. To take advantage of
the illegal opcode Reset, use only the lower 16 bits of
each program memory section to store the data values.
The upper 8 bits should be programmed with 3Fh,
which is an illegal opcode value.
Note: The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset will be meaningful.
Table 6-3 provides a summary of Reset flag bit
operation.
6.9.2
UNINITIALIZED W REGISTER
RESET
Any attempts to use the uninitialized W register as an
address pointer will Reset the device. The W register
array (with the exception of W15) is cleared during all
Resets and is considered uninitialized until written to.
6.9.3
SECURITY RESET
If a Program Flow Change (PFC) or Vector Flow
Change (VFC) targets a restricted location in a
protected segment (Boot and Secure Segment), that
operation will cause a security Reset.
The PFC occurs when the Program Counter is
reloaded as a result of a Call, Jump, Computed Jump,
Return, Return from Subroutine, or other form of
branch instruction.
The VFC occurs when the Program Counter is
reloaded with an Interrupt or Trap vector.
Refer to Section 21.8 “Code Protection and
CodeGuard™ Security” for more information on
Security Reset.
TABLE 6-3:
RESET FLAG BIT OPERATION
Flag Bit
Set by:
Cleared by:
TRAPR (RCON<15>)
IOPWR (RCON<14>)
Trap conflict event
POR, BOR
POR, BOR
Illegal opcode or uninitialized
W register access or Security Reset
CM (RCON<9>)
Configuration Mismatch
MCLR Reset
POR, BOR
POR
EXTR (RCON<7>)
SWR (RCON<6>)
WDTO (RCON<4>)
RESETinstruction
WDT Time-out
POR, BOR
PWRSAVinstruction,
CLRWDTinstruction, POR, BOR
SLEEP (RCON<3>)
IDLE (RCON<2>)
BOR (RCON<1>)
POR (RCON<0>)
PWRSAV #SLEEPinstruction
PWRSAV #IDLEinstruction
POR, BOR
POR, BOR
POR, BOR
—
—
POR
Note: All Reset flag bits can be set or cleared by user software.
DS70265E-page 70
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
7.1.1
ALTERNATE INTERRUPT VECTOR
TABLE
7.0
INTERRUPT CONTROLLER
Note 1: This data sheet summarizes the features
of the dsPIC33FJ12MC201/202 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 6. “Interrupts”
(DS70184) of the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available on the Microchip website
(www.microchip.com).
The Alternate Interrupt Vector Table (AIVT) is located
after the IVT, as shown in Figure 7-1. Access to the
AIVT is provided by the ALTIVT control bit
(INTCON2<15>). If the ALTIVT bit is set, all interrupt
and exception processes use the alternate vectors
instead of the default vectors. The alternate vectors are
organized in the same manner as the default vectors.
The AIVT supports debugging by providing a way to
switch between an application and
a
support
environment without requiring the interrupt vectors to
be reprogrammed. This feature also enables switching
between applications to facilitate evaluation of different
software algorithms at run time. If the AIVT is not
needed, the AIVT should be programmed with the
same addresses used in the IVT.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The dsPIC33FJ12MC201/202 interrupt controller
reduces the numerous peripheral interrupt request
signals to a single interrupt request signal to the
dsPIC33FJ12MC201/202 CPU. It has the following
features:
7.2
Reset Sequence
A device Reset is not a true exception because the
interrupt controller is not involved in the Reset process.
The dsPIC33FJ12MC201/202 device clears its regis-
ters in response to a Reset, forcing the PC to zero. The
digital signal controller then begins program execution
at location 0x000000. A GOTOinstruction at the Reset
address can redirect program execution to the
appropriate start-up routine.
• Up to eight processor exceptions and software traps
• Seven user-selectable priority levels
• Interrupt Vector Table (IVT) with up to 118 vectors
• A unique vector for each interrupt or exception
source
Note: Any unimplemented or unused vector
locations in the IVT and AIVT should be
programmed with the address of a default
interrupt handler routine that contains a
RESETinstruction.
• Fixed priority within a specified user priority level
• Alternate Interrupt Vector Table (AIVT) for debug
support
• Fixed interrupt entry and return latencies
7.1
Interrupt Vector Table
The Interrupt Vector Table (IVT) is shown in Figure 7-1.
The IVT resides in program memory, starting at location
000004h. The IVT contains 126 vectors consisting of
eight non-maskable trap vectors, plus up to 118
sources of interrupt. In general, each interrupt source
has its own vector. Each interrupt vector contains a 24-
bit-wide address. The value programmed into each
interrupt vector location is the starting address of the
associated Interrupt Service Routine (ISR).
Interrupt vectors are prioritized in terms of their natural
priority. This priority is linked to their position in the
vector table. Lower addresses generally have a higher
natural priority. For example, the interrupt associated
with vector 0 will take priority over interrupts at any
other vector address.
dsPIC33FJ12MC201/202 devices implement up to 26
unique interrupts and 4 nonmaskable traps. These are
summarized in Table 7-1 and Table 7-2.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 71
dsPIC33FJ12MC201/202
FIGURE 7-1:
dsPIC33FJ12MC201/202 INTERRUPT VECTOR TABLE
Reset – GOTOInstruction
Reset – GOTOAddress
Reserved
0x000000
0x000002
0x000004
Oscillator Fail Trap Vector
Address Error Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
Reserved
Reserved
Reserved
Interrupt Vector 0
Interrupt Vector 1
~
0x000014
~
~
Interrupt Vector 52
Interrupt Vector 53
Interrupt Vector 54
~
0x00007C
0x00007E
0x000080
Interrupt Vector Table (IVT)(1)
~
~
Interrupt Vector 116
Interrupt Vector 117
Reserved
0x0000FC
0x0000FE
0x000100
0x000102
Reserved
Reserved
Oscillator Fail Trap Vector
Address Error Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
Reserved
Reserved
Reserved
Interrupt Vector 0
Interrupt Vector 1
~
0x000114
~
~
Alternate Interrupt Vector Table (AIVT)(1)
Interrupt Vector 52
Interrupt Vector 53
Interrupt Vector 54
~
0x00017C
0x00017E
0x000180
~
~
Interrupt Vector 116
Interrupt Vector 117
Start of Code
0x0001FE
0x000200
Note 1: See Table 7-1 for the list of implemented interrupt vectors.
DS70265E-page 72
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
TABLE 7-1:
INTERRUPT VECTORS
Interrupt
Vector
Number
Request(IRQ)
Number
IVT Address
AIVT Address
Interrupt Source
INT0 – External Interrupt 0
8
0
0x000014
0x000016
0x000018
0x00001A
0x00001C
0x00001E
0x000020
0x000022
0x000024
0x000026
0x000028
0x00002A
0x00002C
0x00002E
0x000030
0x000032
0x000034
0x000036
0x000038
0x00003A
0x00003C
0x00003E
0x000040
0x000042
0x000044
0x000046
0x000048
0x00004A
0x00004C
0x00004E
0x000050
0x000052
0x000054
0x000056
0x000058
0x00005A
0x00005C
0x00005E
0x000060
0x000062
0x000064
0x000066
0x000068
0x00006A
0x00006C
0x00006E
0x000114
0x000116
0x000118
0x00011A
0x00011C
0x00011E
0x000120
0x000122
0x000124
0x000126
0x000128
0x00012A
0x00012C
0x00012E
0x000130
0x000132
0x000134
0x000136
0x000138
0x00013A
0x00013C
0x00013E
0x000140
0x000142
0x000144
0x000146
0x000148
0x00014A
0x00014C
0x00014E
0x000150
0x000152
0x000154
0x000156
0x000158
0x00015A
0x00015C
0x00015E
0x000160
0x000162
0x000164
0x000166
0x000168
0x00016A
0x00016C
0x00016E
9
1
IC1 – Input Capture 1
OC1 – Output Compare 1
T1 – Timer1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
2
3
4
Reserved
5
IC2 – Input Capture 2
OC2 – Output Compare 2
T2 – Timer2
6
7
8
T3 – Timer3
9
SPI1E – SPI1 Error
SPI1 – SPI1 Transfer Done
U1RX – UART1 Receiver
U1TX – UART1 Transmitter
ADC1 – ADC1
Reserved
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
Reserved
SI2C1 – I2C1 Slave Events
MI2C1 – I2C1 Master Events
Reserved
Change Notification Interrupt
INT1 – External Interrupt 1
Reserved
IC7 – Input Capture 7
IC8 – Input Capture 8
Reserved
Reserved
Reserved
Reserved
Reserved
INT2 – External Interrupt 2
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
© 2007-2011 Microchip Technology Inc.
DS70265E-page 73
dsPIC33FJ12MC201/202
TABLE 7-1:
INTERRUPT VECTORS (CONTINUED)
Interrupt
Vector
Number
Request(IRQ)
Number
IVT Address
AIVT Address
Interrupt Source
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83-125
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75-117
0x000070
0x000072
0x000074
0x000076
0x000078
0x00007A
0x00007C
0x00007E
0x000080
0x000082
0x000084
0x000086
0x000088
0x00008A
0x00008C
0x00008E
0x000090
0x000092
0x000094
0x000096
0x000098
0x00009A
0x00009C
0x00009E
0x0000A0
0x0000A2
0x0000A4
0x0000A6
0x0000A8
0x000170
0x000172
0x000174
0x000176
0x000178
0x00017A
0x00017C
0x00017E
0x000180
0x000182
0x000184
0x000186
0x000188
0x00018A
0x00018C
0x00018E
0x000190
0x000192
0x000194
0x000196
0x000198
0x00019A
0x00019C
0x00019E
0x0001A0
0x0001A2
0x0001A4
0x0001A6
0x0001A8
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PWM1 – PWM1 Period Match
QEI – Position Counter Compare
Reserved
Reserved
Reserved
Reserved
FLTA1 – PWM1 Fault A
Reserved
U1E – UART1 Error
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PWM2 – PWM2 Period Match
FLTA2 – PWM2 Fault A
Reserved
0x0000AA-
0x0000FE
0x0001AA-
0x0001FE
TABLE 7-2:
TRAP VECTORS
Vector Number
IVT Address
AIVT Address
Trap Source
0
1
2
3
4
5
6
7
0x000004
0x000006
0x000008
0x00000A
0x00000C
0x00000E
0x000010
0x000012
0x000104
0x000106
0x000108
0x00010A
0x00010C
0x00010E
0x000110
0x000112
Reserved
Oscillator Failure
Address Error
Stack Error
Math Error
Reserved
Reserved
Reserved
DS70265E-page 74
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
7.3.4
IPCx
7.3
Interrupt Control and Status
Registers
The IPC registers are used to set the interrupt priority
level for each source of interrupt. Each user interrupt
source can be assigned to one of eight priority levels.
The dsPIC33FJ12MC201/202 devices implement a
total of 22 registers for the interrupt controller:
• INTCON1
• INTCON2
• IFSx
7.3.5
INTTREG
The INTTREG register contains the associated
interrupt vector number and the new CPU interrupt
priority level, which are latched into vector number
(VECNUM<6:0>) and interrupt level (ILR<3:0>) bit
fields in the INTTREG register. The new interrupt
priority level is the priority of the pending interrupt.
• IECx
• IPCx
• INTTREG
7.3.1
INTCON1 AND INTCON2
The interrupt sources are assigned to the IFSx, IECx
and IPCx registers in the same sequence that they are
listed in Table 7-1. For example, the INT0 (External
Interrupt 0) is shown as having vector number 8 and a
natural order priority of 0. Thus, the INT0IF bit is found
in IFS0<0>, the INT0IE bit in IEC0<0>, and the INT0IP
bits in the first positions of IPC0 (IPC0<2:0>).
Global interrupt control functions are controlled from
INTCON1 and INTCON2. INTCON1 contains the
Interrupt Nesting Disable (NSTDIS) bit as well as the
control and status flags for the processor trap sources.
The INTCON2 register controls the external interrupt
request signal behavior and the use of the Alternate
Interrupt Vector Table.
7.3.6
STATUS/CONTROL REGISTERS
7.3.2
IFSx
Although they are not specifically part of the interrupt
control hardware, two of the CPU Control registers
contain bits that control interrupt functionality.
The IFS registers maintain all of the interrupt request
flags. Each source of interrupt has a status bit, which is
set by the respective peripherals or external signal and
is cleared via software.
• The CPU STATUS register, SR, contains the
IPL<2:0> bits (SR<7:5>). These bits indicate the
current CPU interrupt priority level. The user
application can change the current CPU priority
level by writing to the IPL bits.
7.3.3
IECx
The IEC registers maintain all of the interrupt enable
bits. These control bits are used to individually enable
interrupts from the peripherals or external signals.
• The CORCON register contains the IPL3 bit
which, together with IPL<2:0>, also indicates the
current CPU priority level. IPL3 is a read-only bit
so that trap events cannot be masked by the user
software.
All Interrupt registers are described in Register 7-1
through Register 7-24 in the following pages.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 75
dsPIC33FJ12MC201/202
(1)
REGISTER 7-1:
SR: CPU STATUS REGISTER
R-0
OA
R-0
OB
R/C-0
SA
R/C-0
SB
R-0
R/C-0
SAB
R -0
DA
R/W-0
DC
OAB
bit 15
bit 8
R/W-0(3)
IPL2(2)
bit 7
R/W-0(3)
IPL1(2)
R/W-0(3)
IPL0(2)
R-0
RA
R/W-0
N
R/W-0
OV
R/W-0
Z
R/W-0
C
bit 0
Legend:
C = Clear only bit
S = Set only bit
‘1’ = Bit is set
R = Readable bit
W = Writable bit
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n = Value at POR
x = Bit is unknown
bit 7-5
IPL<2:0>: CPU Interrupt Priority Level Status bits(1)
111= CPU Interrupt Priority Level is 7 (15), user interrupts disabled
110= CPU Interrupt Priority Level is 6 (14)
101= CPU Interrupt Priority Level is 5 (13)
100= CPU Interrupt Priority Level is 4 (12)
011= CPU Interrupt Priority Level is 3 (11)
010= CPU Interrupt Priority Level is 2 (10)
001= CPU Interrupt Priority Level is 1 (9)
000= CPU Interrupt Priority Level is 0 (8)
Note 1: For complete register details, see Register 3-1: “SR: CPU Status Register”.
2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
3: The IPL<2:0> Status bits are read-only when NSTDIS (INTCON1<15>) = 1.
(1)
REGISTER 7-2:
CORCON: CORE CONTROL REGISTER
U-0
—
U-0
—
U-0
—
R/W-0
US
R/W-0
EDT
R-0
R-0
R-0
DL<2:0>
bit 15
bit 8
R/W-0
SATA
R/W-0
SATB
R/W-1
R/W-0
R/C-0
IPL3(2)
R/W-0
PSV
R/W-0
RND
R/W-0
IF
SATDW
ACCSAT
bit 7
bit 0
Legend:
C = Clear only bit
W = Writable bit
‘x = Bit is unknown
R = Readable bit
0’ = Bit is cleared
-n = Value at POR
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
bit 3
IPL3: CPU Interrupt Priority Level Status bit 3(2)
1= CPU interrupt priority level is greater than 7
0= CPU interrupt priority level is 7 or less
Note 1: For complete register details, see Register 3-2: “CORCON: Core Control Register”.
2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.
DS70265E-page 76
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
REGISTER 7-3:
INTCON1: INTERRUPT CONTROL REGISTER 1
R/W-0
NSTDIS
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
OVAERR
OVBERR
COVAERR COVBERR
OVATE
OVBTE
COVTE
bit 8
R/W-0
SFTACERR
bit 7
R/W-0
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
DIV0ERR
MATHERR ADDRERR
STKERR
OSCFAIL
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
NSTDIS: Interrupt Nesting Disable bit
1= Interrupt nesting is disabled
0= Interrupt nesting is enabled
OVAERR: Accumulator A Overflow Trap Flag bit
1= Trap was caused by overflow of Accumulator A
0= Trap was not caused by overflow of Accumulator A
OVBERR: Accumulator B Overflow Trap Flag bit
1= Trap was caused by overflow of Accumulator B
0= Trap was not caused by overflow of Accumulator B
COVAERR: Accumulator A Catastrophic Overflow Trap Flag bit
1= Trap was caused by catastrophic overflow of Accumulator A
0= Trap was not caused by catastrophic overflow of Accumulator A
COVBERR: Accumulator B Catastrophic Overflow Trap Flag bit
1= Trap was caused by catastrophic overflow of Accumulator B
0= Trap was not caused by catastrophic overflow of Accumulator B
OVATE: Accumulator A Overflow Trap Enable bit
1= Trap overflow of Accumulator A
0= Trap disabled
OVBTE: Accumulator B Overflow Trap Enable bit
1= Trap overflow of Accumulator B
0= Trap disabled
bit 8
COVTE: Catastrophic Overflow Trap Enable bit
1= Trap on catastrophic overflow of Accumulator A or B enabled
0= Trap disabled
bit 7
SFTACERR: Shift Accumulator Error Status bit
1= Math error trap was caused by an invalid accumulator shift
0= Math error trap was not caused by an invalid accumulator shift
bit 6
DIV0ERR: Arithmetic Error Status bit
1= Math error trap was caused by a divide by zero
0= Math error trap was not caused by a divide by zero
bit 5
bit 4
Unimplemented: Read as ‘0’
MATHERR: Arithmetic Error Status bit
1= Math error trap has occurred
0= Math error trap has not occurred
bit 3
ADDRERR: Address Error Trap Status bit
1= Address error trap has occurred
0= Address error trap has not occurred
© 2007-2011 Microchip Technology Inc.
DS70265E-page 77
dsPIC33FJ12MC201/202
REGISTER 7-3:
INTCON1: INTERRUPT CONTROL REGISTER 1 (CONTINUED)
bit 2
bit 1
bit 0
STKERR: Stack Error Trap Status bit
1= Stack error trap has occurred
0= Stack error trap has not occurred
OSCFAIL: Oscillator Failure Trap Status bit
1= Oscillator failure trap has occurred
0= Oscillator failure trap has not occurred
Unimplemented: Read as ‘0’
DS70265E-page 78
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
REGISTER 7-4:
INTCON2: INTERRUPT CONTROL REGISTER 2
R/W-0
ALTIVT
bit 15
R-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
DISI
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
INT2EP
INT1EP
INT0EP
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
ALTIVT: Enable Alternate Interrupt Vector Table bit
1= Use alternate vector table
0= Use standard (default) vector table
DISI: DISIInstruction Status bit
1= DISIinstruction is active
0= DISIinstruction is not active
bit 13-3
bit 2
Unimplemented: Read as ‘0’
INT2EP: External Interrupt 2 Edge Detect Polarity Select bit
1= Interrupt on negative edge
0= Interrupt on positive edge
bit 1
bit 0
INT1EP: External Interrupt 1 Edge Detect Polarity Select bit
1= Interrupt on negative edge
0= Interrupt on positive edge
INT0EP: External Interrupt 0 Edge Detect Polarity Select bit
1= Interrupt on negative edge
0= Interrupt on positive edge
© 2007-2011 Microchip Technology Inc.
DS70265E-page 79
dsPIC33FJ12MC201/202
REGISTER 7-5:
IFS0: INTERRUPT FLAG STATUS REGISTER 0
U-0
—
U-0
—
R/W-0
AD1IF
R/W-0
R/W-0
R/W-0
SPI1IF
R/W-0
R/W-0
T3IF
U1TXIF
U1RXIF
SPI1EIF
bit 15
bit 8
R/W-0
T2IF
R/W-0
OC2IF
R/W-0
IC2IF
U-0
—
R/W-0
T1IF
R/W-0
OC1IF
R/W-0
IC1IF
R/W-0
INT0IF
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13
Unimplemented: Read as ‘0’
AD1IF: ADC1 Conversion Complete Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 12
bit 11
bit 10
bit 9
U1TXIF: UART1 Transmitter Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
U1RXIF: UART1 Receiver Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
SPI1IF: SPI1 Event Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
SPI1EIF: SPI1 Fault Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 8
T3IF: Timer3 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 7
T2IF: Timer2 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 6
OC2IF: Output Compare Channel 2 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 5
IC2IF: Input Capture Channel 2 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 4
bit 3
Unimplemented: Read as ‘0’
T1IF: Timer1 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 2
OC1IF: Output Compare Channel 1 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
DS70265E-page 80
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
REGISTER 7-5:
IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED)
bit 1
IC1IF: Input Capture Channel 1 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 0
INT0IF: External Interrupt 0 Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
© 2007-2011 Microchip Technology Inc.
DS70265E-page 81
dsPIC33FJ12MC201/202
REGISTER 7-6:
IFS1: INTERRUPT FLAG STATUS REGISTER 1
U-0
—
U-0
—
R/W-0
INT2IF
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0
IC8IF
R/W-0
IC7IF
U-0
—
R/W-0
INT1IF
R/W-0
CNIF
U-0
—
R/W-0
R/W-0
MI2C1IF
SI2C1IF
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13
Unimplemented: Read as ‘0’
INT2IF: External Interrupt 2 Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 12-8
bit 7
Unimplemented: Read as ‘0’
IC8IF: Input Capture Channel 8 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 6
IC7IF: Input Capture Channel 7 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 5
bit 4
Unimplemented: Read as ‘0’
INT1IF: External Interrupt 1 Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 3
CNIF: Input Change Notification Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 2
bit 1
Unimplemented: Read as ‘0’
MI2C1IF: I2C1 Master Events Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 0
SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
DS70265E-page 82
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
REGISTER 7-7:
IFS3: INTERRUPT FLAG STATUS REGISTER 3
R/W-0
FLTA1IF
bit 15
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
QEIIF
R/W-0
U-0
—
PWM1IF
bit 8
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
FLTA1IF: PWM1 Fault A Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 14-11
bit 10
Unimplemented: Read as ‘0’
QEIIF: QEI Event Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 9
PWM1IF: PWM1 Error Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 8-0
Unimplemented: Read as ‘0’
© 2007-2011 Microchip Technology Inc.
DS70265E-page 83
dsPIC33FJ12MC201/202
REGISTER 7-8:
IFS4: INTERRUPT FLAG STATUS REGISTER 4
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
U-0
—
FLTA2IF
PWM2IF
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
U1EIF
U-0
—
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-11
bit 10
Unimplemented: Read as ‘0’
FLTA2IF: PWM2 Fault A Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 9
PWM2IF: PWM2 Error Interrupt Enable bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 8-2
bit 1
Unimplemented: Read as ‘0’
U1EIF: UART1 Error Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 0
Unimplemented: Read as ‘0’
DS70265E-page 84
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
REGISTER 7-9:
IEC0: INTERRUPT ENABLE CONTROL REGISTER 0
U-0
—
U-0
—
R/W-0
AD1IE
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T3IE
U1TXIE
U1RXIE
SPI1IE
SPI1EIE
bit 15
bit 8
R/W-0
T2IE
R/W-0
OC2IE
R/W-0
IC2IE
U-0
—
R/W-0
T1IE
R/W-0
OC1IE
R/W-0
IC1IE
R/W-0
INT0IE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13
Unimplemented: Read as ‘0’
AD1IE: ADC1 Conversion Complete Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 12
bit 11
bit 10
bit 9
U1TXIE: UART1 Transmitter Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
U1RXIE: UART1 Receiver Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
SPI1IE: SPI1 Event Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
SPI1EIE: SPI1 Event Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 8
T3IE: Timer3 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 7
T2IE: Timer2 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 6
OC2IE: Output Compare Channel 2 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 5
IC2IE: Input Capture Channel 2 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 4
bit 3
Unimplemented: Read as ‘0’
T1IE: Timer1 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 2
OC1IE: Output Compare Channel 1 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
© 2007-2011 Microchip Technology Inc.
DS70265E-page 85
dsPIC33FJ12MC201/202
REGISTER 7-9:
IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED)
bit 1
IC1IE: Input Capture Channel 1 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 0
INT0IE: External Interrupt 0 Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
DS70265E-page 86
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
REGISTER 7-10: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1
U-0
—
U-0
—
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
INT2IE
bit 15
bit 8
R/W-0
IC8IE
R/W-0
IC7IE
U-0
—
R/W-0
R/W-0
CNIE
U-0
—
R/W-0
R/W-0
INT1IE
MI2C1IE
SI2C1IE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13
Unimplemented: Read as ‘0’
INT2IE: External Interrupt 2 Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 12-8
bit 7
Unimplemented: Read as ‘0’
IC8IE: Input Capture Channel 8 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 6
IC7IE: Input Capture Channel 7 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 5
bit 4
Unimplemented: Read as ‘0’
INT1IE: External Interrupt 1 Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 3
CNIE: Input Change Notification Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 2
bit 1
Unimplemented: Read as ‘0’
MI2C1IE: I2C1 Master Events Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 0
SI2C1IE: I2C1 Slave Events Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
© 2007-2011 Microchip Technology Inc.
DS70265E-page 87
dsPIC33FJ12MC201/202
REGISTER 7-11: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
QEIIE
R/W-0
U-0
—
FLTA1IE
PWM1IE
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
FLTA1IE: PWM1 Fault A Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 14-11
bit 10
Unimplemented: Read as ‘0’
QEIIE: QEI Event Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 9
PWM1IE: PWM1 Error Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 8-0
Unimplemented: Read as ‘0’
DS70265E-page 88
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
REGISTER 7-12: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
U-0
—
FLA2IE
PWM2IE
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
U1EIE
U-0
—
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-11
bit 10
Unimplemented: Read as ‘0’
FLA2IE: PWM2 Fault A Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 9
PWM2IE: PWM2 Error Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 8-2
bit 1
Unimplemented: Read as ‘0’
U1EIE: UART1 Error Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 0
Unimplemented: Read as ‘0’
© 2007-2011 Microchip Technology Inc.
DS70265E-page 89
dsPIC33FJ12MC201/202
REGISTER 7-13: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
R/W-0
bit 0
T1IP<2:0>
OC1IP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
IC1IP<2:0>
INT0IP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
T1IP<2:0>: Timer1 Interrupt Priority bits
bit 14-12
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
OC1IP<2:0>: Output Compare Channel 1 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
IC1IP<2:0>: Input Capture Channel 1 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
INT0IP<2:0>: External Interrupt 0 Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
DS70265E-page 90
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
REGISTER 7-14: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
T2IP<2:0>
OC2IP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
U-1
—
U-0
—
U-0
—
IC2IP<2:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
T2IP<2:0>: Timer2 Interrupt Priority bits
bit 14-12
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
OC2IP<2:0>: Output Compare Channel 2 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
© 2007-2011 Microchip Technology Inc.
DS70265E-page 91
dsPIC33FJ12MC201/202
REGISTER 7-15: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
R/W-0
bit 0
U1RXIP<2:0>
SPI1IP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
SPI1EIP<2:0>
T3IP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
SPI1IP<2:0>: SPI1 Event Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
SPI1EIP<2:0>: SPI1 Error Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
T3IP<2:0>: Timer3 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
DS70265E-page 92
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
REGISTER 7-16: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
—
R/W-0
—
R/W-0
—
bit 15
bit 8
R/W-0
bit 0
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
AD1IP<2:0>
U1TXIP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-7
bit 6-4
Unimplemented: Read as ‘0’
AD1IP<2:0>: ADC1 Conversion Complete Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
© 2007-2011 Microchip Technology Inc.
DS70265E-page 93
dsPIC33FJ12MC201/202
REGISTER 7-17: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
CNIP<2:0>
bit 15
bit 8
R/W-0
bit 0
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
MI2C1IP<2:0>
SI2C1IP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
CNIP<2:0>: Change Notification Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11-7
bit 6-4
Unimplemented: Read as ‘0’
MI2C1IP<2:0>: I2C1 Master Events Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
SI2C1IP<2:0>: I2C1 Slave Events Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
DS70265E-page 94
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
REGISTER 7-18: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
R/W-0
bit 0
IC8IP<2:0>
IC7IP<2:0>
bit 15
U-0
—
U-1
—
U-0
—
U-0
—
U-0
—
R/W-1
R/W-0
INT1IP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
IC8IP<2:0>: Input Capture Channel 8 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
IC7IP<2:0>: Input Capture Channel 7 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7-3
bit 2-0
Unimplemented: Read as ‘0’
INT1IP<2:0>: External Interrupt 1 Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
© 2007-2011 Microchip Technology Inc.
DS70265E-page 95
dsPIC33FJ12MC201/202
REGISTER 7-19: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7
U-0
—
U-1
—
U-0
—
U-0
—
U-0
—
U-1
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
INT2IP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-7
bit 6-4
Unimplemented: Read as ‘0’
INT2IP<2:0>: External Interrupt 2 Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
DS70265E-page 96
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
REGISTER 7-20: IPC14: INTERRUPT PRIORITY CONTROL REGISTER 14
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
QEIIP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
PWM1IP<2:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-12
bit 10-8
Unimplemented: Read as ‘0’
QEIIP<2:0>: QEI Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
PWM1IP<2:0>: PWM1 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
© 2007-2011 Microchip Technology Inc.
DS70265E-page 97
dsPIC33FJ12MC201/202
REGISTER 7-21: IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
FLTA1IP<2:0>
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
FLTA1IP<2:0>: PWM1 Fault A Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11-0
Unimplemented: Read as ‘0’
REGISTER 7-22: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U1EIP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-7
bit 6-4
Unimplemented: Read as ‘0’
U1EIP<2:0>: UART1 Error Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
DS70265E-page 98
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
REGISTER 7-23: IPC18: INTERRUPT PRIORITY CONTROL REGISTER 18
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
bit 8
FLTA2IP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
PWM2IP<2:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-11
bit 8-10
Unimplemented: Read as ‘0’
FLTA2IP<2:0>: PWM2 Fault A Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 6-4
PWM2IP<2:0>: PWM2 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
© 2007-2011 Microchip Technology Inc.
DS70265E-page 99
dsPIC33FJ12MC201/202
REGISTER 7-24: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
R-0
R-0
R-0
R-0
R-0
R-0
ILR<3:0>
bit 15
bit 8
bit 0
U-0
—
R-0
R-0
R-0
R-0
R-0
VECNUM<6:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-12
bit 11-8
Unimplemented: Read as ‘0’
ILR<3:0>: New CPU Interrupt Priority Level bits
1111= CPU Interrupt Priority Level is 15
•
•
•
0001= CPU Interrupt Priority Level is 1
0000= CPU Interrupt Priority Level is 0
bit 7
Unimplemented: Read as ‘0’
bit 6-0
VECNUM<6:0>: Vector Number of Pending Interrupt bits
0111111= Interrupt Vector pending is number 135
•
•
•
0000001= Interrupt Vector pending is number 9
0000000= Interrupt Vector pending is number 8
DS70265E-page 100
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
7.4.3
TRAP SERVICE ROUTINE (TSR)
7.4
Interrupt Setup Procedures
A Trap Service Routine (TSR) is coded like an ISR,
except that the appropriate trap status flag in the
INTCON1 register must be cleared to avoid re-entry
into the TSR.
7.4.1
INITIALIZATION
To configure an interrupt source at initialization:
1. Set the NSTDIS bit (INTCON1<15>) if nested
interrupts are not desired.
7.4.4
INTERRUPT DISABLE
2. Select the user-assigned priority level for the
interrupt source by writing the control bits into
the appropriate IPCx register. The priority level
will depend on the specific application and type
of interrupt source. If multiple priority levels are
not desired, the IPCx register control bits for all
enabled interrupt sources can be programmed
to the same non-zero value.
All user interrupts can be disabled using this
procedure:
1. Push the current SR value onto the software
stack using the PUSHinstruction.
2. Force the CPU to priority level 7 by inclusive
ORing the value OEh with SRL.
To enable user interrupts, the POP instruction can be
used to restore the previous SR value.
Note: At a device Reset, the IPCx registers
are initialized such that all user inter-
rupt sources are assigned to priority
level 4.
Note:
Only user interrupts with a priority level of
7 or lower can be disabled. Trap sources
(level 8-level 15) cannot be disabled.
3. Clear the interrupt flag status bit associated with
the peripheral in the associated IFSx register.
The DISI instruction provides a convenient way to
disable interrupts of priority levels 1-6 for a fixed period
of time. Level 7 interrupt sources are not disabled by
the DISI instruction.
4. Enable the interrupt source by setting the inter-
rupt enable control bit associated with the
source in the appropriate IECx register.
7.4.2
INTERRUPT SERVICE ROUTINE
(ISR)
The method used to declare an Interrupt Service
Routine (ISR) and initialize the IVT with the correct
vector address depends on the programming language
(C or assembler) and the language development tool
suite used to develop the application.
In general, the user application must clear the interrupt
flag in the appropriate IFSx register for the source of
interrupt that the ISR handles. Otherwise, program will
re-enter the ISR immediately after exiting the routine. If
the ISR is coded in assembly language, it must be
terminated using a RETFIEinstruction to unstack the
saved PC value, SRL value and old CPU priority level.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 101
dsPIC33FJ12MC201/202
NOTES:
DS70265E-page 102
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
The dsPIC33FJ12MC201/202 oscillator system
provides:
8.0
OSCILLATOR
CONFIGURATION
• External and internal oscillator options as clock
sources
• An on-chip Phase-Locked Loop (PLL) to scale the
internal operating frequency to the required
system clock frequency
• An internal FRC oscillator that can also be used
with the PLL, thereby allowing full-speed opera-
tion without any external clock generation hard-
ware
• Clock switching between various clock sources
• Programmable clock postscaler for system power
savings
• A Fail-Safe Clock Monitor (FSCM) that detects
clock failure and takes fail-safe measures
• A Clock Control register (OSCCON)
• Nonvolatile Configuration bits for main oscillator
selection
Note 1: This data sheet summarizes the features
of the dsPIC33FJ12MC201/202 family of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to Section 7. “Oscillator”
(DS70186) of the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microchip website
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
A simplified diagram of the oscillator system is shown
in Figure 8-1.
FIGURE 8-1:
dsPIC33FJ12MC201/202 OSCILLATOR SYSTEM DIAGRAM
Primary Oscillator
OSC1
DOZE<2:0>
XT, HS, EC
S2
(2)
R
XTPLL, HSPLL,
ECPLL, FRCPLL
S3
S1
FCY
FP
(1)
S1/S3
PLL
OSC2
POSCMD<1:0>
÷ 2
FRC
Oscillator
FRCDIVN
FOSC
S7
FRCDIV<2:0>
TUN<5:0>
FRCDIV16
FRC
S6
S0
÷ 16
LPRC
SOSC
LPRC
Oscillator
S5
Secondary Oscillator
SOSCO
SOSCI
S4
LPOSCEN
Clock Switch
Reset
Clock Fail
S7
WDT, PWRT,
NOSC<2:0> FNOSC<2:0>
FSCM
Timer 1
Note 1: See Figure 8-2 for PLL details.
2: If the Oscillator is used with XT or HS modes, an extended parallel resistor with the value of 1 MΩ must be connected.
3: The term FP refers to the clock source for all peripherals, while FCY refers to the clock source for the CPU. Throughout this document,
FCY and FP are used interchangeably, except in the case of Doze mode. FP and FCY will be different when Doze mode is used with
a Doze ratio of 1:2 or lower.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 103
dsPIC33FJ12MC201/202
8.1.1.5
FRC
8.1
CPU Clocking System
The clock signals generated by the FRC and primary
oscillators can be optionally applied to an on-chip
Phase-Locked Loop (PLL) to provide a wide range of
output frequencies for device operation. PLL
configuration is described in Section 8.1.3 “PLL
Configuration”.
The dsPIC33FJ12MC201/202 devices provide seven
system clock options:
• Fast RC (FRC) Oscillator
• FRC Oscillator with PLL
• Primary (XT, HS or EC) Oscillator
• Primary Oscillator with PLL
• Secondary (LP) Oscillator
• Low-Power RC (LPRC) Oscillator
• FRC Oscillator with postscaler
The FRC frequency depends on the FRC accuracy
(see Table 24-18) and the value of the FRC Oscillator
Tuning register (see Register 8-4).
8.1.2
SYSTEM CLOCK SELECTION
8.1.1
SYSTEM CLOCK SOURCES
Fast RC
The oscillator source used at a device Power-on
Reset event is selected using Configuration bit
settings. The oscillator Configuration bit settings are
located in the Configuration registers in the program
memory. (Refer to Section 21.1 “Configuration
Bits” for further details.) The Initial Oscillator
8.1.1.1
The Fast RC (FRC) internal oscillator runs at a nominal
frequency of 7.37 MHz. User software can tune the
FRC frequency. User software can optionally specify a
factor (ranging from 1:2 to 1:256) by which the FRC
clock frequency is divided. This factor is selected using
the FRCDIV<2:0> (CLKDIV<10:8>) bits.
Selection
(FOSCSEL<2:0>), and the Primary Oscillator Mode
Select Configuration bits, POSCMD<1:0>
Configuration
bits,
FNOSC<2:0>
(FOSC<1:0>), select the oscillator source that is used
at a Power-on Reset. The FRC primary oscillator is
the default (unprogrammed) selection.
8.1.1.2
Primary
The primary oscillator can use one of the following as
its clock source:
The Configuration bits allow users to choose among 12
different clock modes, shown in Table 8-1.
• XT (Crystal): Crystals and ceramic resonators in
the range of 3 MHz to 10 MHz. The crystal is
connected to the OSC1 and OSC2 pins.
The output of the oscillator (or the output of the PLL if
a PLL mode has been selected) FOSC is divided by 2 to
generate the device instruction clock (FCY) and the
peripheral clock time base (FP). FCY defines the
operating speed of the device, and speeds up to 40
MHz are supported by the dsPIC33FJ12MC201/202
architecture.
• HS (High-Speed Crystal): Crystals in the range of
10 MHz to 40 MHz. The crystal is connected to
the OSC1 and OSC2 pins.
• EC (External Clock): The external clock signal is
directly applied to the OSC1 pin.
Instruction execution speed or device operating
frequency, FCY, is given by:
8.1.1.3
Secondary
The secondary (LP) oscillator is designed for low power
and uses a 32.768 kHz crystal or ceramic resonator.
The LP oscillator uses the SOSCI and SOSCO pins.
EQUATION 8-1:
DEVICE OPERATING
FREQUENCY
FOSC
2
FCY = -------------
8.1.1.4
Low-Power RC
The Low-Power RC (LPRC) internal oscIllator runs at a
nominal frequency of 32.768 kHz. It is also used as a
reference clock by the Watchdog Timer (WDT) and
Fail-Safe Clock Monitor (FSCM).
DS70265E-page 104
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
For example, suppose a 10 MHz crystal is being used
with the selected oscillator mode of XT with PLL.
8.1.3
PLL CONFIGURATION
The primary oscillator and internal FRC oscillator can
optionally use an on-chip PLL to obtain higher speeds
of operation. The PLL provides significant flexibility in
selecting the device operating speed. A block diagram
of the PLL is shown in Figure 8-2.
• If PLLPRE<4:0> = 0, then N1 = 2. This yields a
VCO input of 10/2 = 5 MHz, which is within the
acceptable range of 0.8-8 MHz.
• If PLLDIV<8:0> = 0x1E, then
M = 32. This yields a VCO output of 5 x 32 = 160
MHz, which is within the 100-200 MHz ranged
needed.
The output of the primary oscillator or FRC, denoted as
‘FIN’, is divided down by a prescale factor (N1) of 2, 3,
... or 33 before being provided to the PLL’s Voltage
Controlled Oscillator (VCO). The input to the VCO must
be selected in the range of 0.8 MHz to 8 MHz. The
prescale factor ‘N1’ is selected using the
PLLPRE<4:0> bits (CLKDIV<4:0>).
• If PLLPOST<1:0> = 0, then N2 = 2. This provides
a Fosc of 160/2 = 80 MHz. The resultant device
operating speed is 80/2 = 40 MIPS.
EQUATION 8-3:
XT WITH PLL MODE
EXAMPLE
The PLL Feedback Divisor, selected using the
PLLDIV<8:0> bits (PLLFBD<8:0>), provides a factor ‘M,’
by which the input to the VCO is multiplied. This factor
must be selected such that the resulting VCO output
frequency is in the range of 100 MHz to 200 MHz.
1 10000000 ⋅ 32
FOSC
⎛
⎞
⎠
-- ------------------------------------
FCY = ------------- =
= 40 MIPS
⎝
2
2 ⋅ 2
2
The VCO output is further divided by a postscale factor
‘N2.’ This factor is selected using the PLLPOST<1:0>
bits (CLKDIV<7:6>). ‘N2’ can be either 2, 4, or 8, and
must be selected such that the PLL output frequency
(FOSC) is in the range of 12.5 MHz to 80 MHz, which
generates device operating speeds of 6.25 to 40 MIPS.
For output ‘FIN’ on a primary oscillator, or FRC oscilla-
tor, the PLL output ‘FOSC’ is given by Equation 8-2.
EQUATION 8-2:
FOSC CALCULATION
M
⎛
⎝
⎞
⎠
---------------------
FOSC = FIN ⋅
N1 ⋅ N2
FIGURE 8-2:
dsPIC33FJ12MC201/202 PLL BLOCK DIAGRAM
FVCO
0.8-8.0 MHz
Here(1)
12.5-80 MHz
Here(1)
100-200 MHz
Here(1)
Source (Crystal, External Clock
or Internal RC)
FOSC
PLLPRE
VCO
PLLPOST
N2
X
PLLDIV
N1
Divide by
2-33
Divide by
2, 4, 8
M
Divide by
2-513
Note 1: This frequency range must be satisfied at all times.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 105
dsPIC33FJ12MC201/202
TABLE 8-1:
CONFIGURATION BIT VALUES FOR CLOCK SELECTION
Oscillator
Source
Oscillator Mode
POSCMD<1:0>
FNOSC<2:0>
Note
Fast RC Oscillator with Divide-by-N (FRCDIVN)
Fast RC Oscillator with Divide-by-16 (FRCDIV16)
Low-Power RC Oscillator (LPRC)
Secondary (Timer1) Oscillator (SOSC)
Primary Oscillator (HS) with PLL (HSPLL)
Primary Oscillator (XT) with PLL (XTPLL)
Primary Oscillator (EC) with PLL (ECPLL)
Primary Oscillator (HS)
Internal
Internal
Internal
Secondary
Primary
Primary
Primary
Primary
Primary
Primary
Internal
Internal
xx
xx
xx
xx
10
01
00
10
01
00
xx
xx
111
110
101
100
011
011
011
010
010
010
001
000
1, 2
1
1
1
—
—
1
—
—
1
Primary Oscillator (XT)
Primary Oscillator (EC)
Fast RC Oscillator with PLL (FRCPLL)
Fast RC Oscillator (FRC)
1
1
Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit.
2: This is the default oscillator mode for an unprogrammed (erased) device.
DS70265E-page 106
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
(1,3)
REGISTER 8-1:
OSCCON: OSCILLATOR CONTROL REGISTER
U-0
—
R-0
R-0
R-0
U-0
—
R/W-y
R/W-y
NOSC<2:0>(2)
R/W-y
bit 8
COSC<2:0>
bit 15
R/W-0
CLKLOCK
bit 7
R/W-0
R-0
U-0
—
R/C-0
CF
U-0
—
R/W-0
R/W-0
IOLOCK
LOCK
LPOSCEN
OSWEN
bit 0
Legend:
y = Value set from Configuration bits on POR
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
COSC<2:0>: Current Oscillator Selection bits (read-only)
111= Fast RC oscillator (FRC) with Divide-by-n
110= Fast RC oscillator (FRC) with Divide-by-16
101= Low-Power RC oscillator (LPRC)
100= Secondary oscillator (SOSC)
011= Primary oscillator (XT, HS, EC) with PLL
010= Primary oscillator (XT, HS, EC)
001= Fast RC oscillator (FRC) with Divide-by-n plus PLL
000= Fast RC oscillator (FRC)
bit 11
Unimplemented: Read as ‘0’
bit 10-8
NOSC<2:0>: New Oscillator Selection bits (2)
111= Fast RC oscillator (FRC) with Divide-by-n
110= Fast RC oscillator (FRC) with Divide-by-16
101= Low-Power RC oscillator (LPRC)
100= Secondary oscillator (SOSC)
011= Primary oscillator (XT, HS, EC) with PLL
010= Primary oscillator (XT, HS, EC)
001= Fast RC oscillator (FRC) with Divide-by-n plus PLL
000= Fast RC oscillator (FRC)
bit 7
CLKLOCK: Clock Lock Enable bit
If clock switching is enabled and FSCM is disabled, (FOSC<FCKSM> = 0b01)
1= Clock switching is disabled, system clock source is locked
0= Clock switching is enabled, system clock source can be modified by clock switching
bit 6
bit 5
bit 4
IOLOCK: Peripheral Pin Select Lock bit
1= Peripherial pin select is locked, write to peripheral pin select registers not allowed
0= Peripherial pin select is not locked, write to peripheral pin select registers allowed
LOCK: PLL Lock Status bit (read-only)
1= Indicates that PLL is in lock, or PLL start-up timer is satisfied
0= Indicates that PLL is out of lock, start-up timer is in progress or PLL is disabled
Unimplemented: Read as ‘0’
Note 1: Writes to this register require an unlock sequence. Refer to Section 7. “Oscillator” (DS70186) in the
“dsPIC33F/PIC24H Family Reference Manual” (available from the Microchip web site) for details.
2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted.
This applies to clock switches in either direction. In these instances, the application must switch to FRC
mode as a transition clock source between the two PLL modes.
3: This register is reset only on a Power-on Reset (POR).
© 2007-2011 Microchip Technology Inc.
DS70265E-page 107
dsPIC33FJ12MC201/202
(1,3)
REGISTER 8-1:
OSCCON: OSCILLATOR CONTROL REGISTER
(CONTINUED)
bit 3
CF: Clock Fail Detect bit (read/clear by application)
1= FSCM has detected clock failure
0= FSCM has not detected clock failure
bit 2
bit 1
Unimplemented: Read as ‘0’
LPOSCEN: Secondary (LP) Oscillator Enable bit
1= Enable secondary oscillator
0= Disable secondary oscillator
bit 0
OSWEN: Oscillator Switch Enable bit
1= Request oscillator switch to selection specified by NOSC<2:0> bits
0= Oscillator switch is complete
Note 1: Writes to this register require an unlock sequence. Refer to Section 7. “Oscillator” (DS70186) in the
“dsPIC33F/PIC24H Family Reference Manual” (available from the Microchip web site) for details.
2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted.
This applies to clock switches in either direction. In these instances, the application must switch to FRC
mode as a transition clock source between the two PLL modes.
3: This register is reset only on a Power-on Reset (POR).
DS70265E-page 108
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
(2)
REGISTER 8-2:
CLKDIV: CLOCK DIVISOR REGISTER
R/W-0
ROI
R/W-0
R/W-1
R/W-1
R/W-0
DOZEN(1)
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
DOZE<2:0>
FRCDIV<2:0>
bit 15
R/W-0
R/W-1
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
PLLPOST<1:0>
PLLPRE<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
ROI: Recover on Interrupt bit
1= Interrupts will clear the DOZEN bit and the processor clock/peripheral clock ratio is set to 1:1
0= Interrupts have no effect on the DOZEN bit
bit 14-12
DOZE<2:0>: Processor Clock Reduction Select bits
111= FCY/128
110= FCY/64
101= FCY/32
100= FCY/16
011= FCY/8 (default)
010= FCY/4
001= FCY/2
000= FCY/1
bit 11
DOZEN: DOZE Mode Enable bit(1)
1= DOZE<2:0> field specifies the ratio between the peripheral clocks and the processor clocks
0= Processor clock/peripheral clock ratio forced to 1:1
bit 10-8
FRCDIV<2:0>: Internal Fast RC Oscillator Postscaler bits
111= FRC divide by 256
110= FRC divide by 64
101= FRC divide by 32
100= FRC divide by 16
011= FRC divide by 8
010= FRC divide by 4
001= FRC divide by 2
000= FRC divide by 1 (default)
bit 7-6
PLLPOST<1:0>: PLL VCO Output Divider Select bits (also denoted as ‘N2’, PLL postscaler)
11= Output/8
10= Reserved
01= Output/4 (default)
00= Output/2
bit 5
Unimplemented: Read as ‘0’
bit 4-0
PLLPRE<4:0>: PLL Phase Detector Input Divider bits (also denoted as ‘N1’, PLL prescaler)
00000= Input/2 (default)
00001= Input/3
•
•
•
11111= Input/33
Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs.
2: This register is reset only on a Power-on Reset (POR).
© 2007-2011 Microchip Technology Inc.
DS70265E-page 109
dsPIC33FJ12MC201/202
(1)
REGISTER 8-3:
PLLFBD: PLL FEEDBACK DIVISOR REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
U-0
—
R/W-0(1)
PLLDIV<8>
bit 8
—
bit 15
R/W-0
bit 7
R/W-0
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
bit 0
PLLDIV<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-9
bit 8-0
Unimplemented: Read as ‘0’
PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier)
000000000= 2
000000001= 3
000000010= 4
•
•
•
000110000= 50 (default)
•
•
•
111111111= 513
Note 1: This register is reset only on a Power-on Reset (POR).
DS70265E-page 110
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
(2)
REGISTER 8-4:
OSCTUN: FRC OSCILLATOR TUNING REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0
bit 0
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TUN<5:0>(1)
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-6
bit 5-0
Unimplemented: Read as ‘0’
TUN<5:0>: FRC Oscillator Tuning bits(1)
011111= Center frequency +11.625% (8.23 MHz)
011110= Center frequency +11.25% (8.20 MHz)
•
•
•
000001= Center frequency +0.375% (7.40 MHz)
000000= Center frequency (7.37 MHz nominal)
111111= Center frequency -0.375% (7.345 MHz)
•
•
•
100001= Center frequency -11.625% (6.52 MHz)
100000= Center frequency -12% (6.49 MHz)
Note 1: OSCTUN functionality has been provided to help customers compensate for temperature effects on the
FRC frequency over a wide range of temperatures. The tuning step size is an approximation and is neither
characterized nor tested.
2: This register is reset only on a Power-on Reset (POR).
© 2007-2011 Microchip Technology Inc.
DS70265E-page 111
dsPIC33FJ12MC201/202
2. If a valid clock switch has been initiated, the
LOCK (OSCCON<5>) and the CF
(OSCCON<3>) status bits are cleared.
8.2
Clock Switching Operation
Applications are free to switch among any of the four
clock sources (Primary, LP, FRC, and LPRC) under
software control at any time. To limit the possible side
effects of this flexibility, dsPIC33FJ12MC201/202
devices have a safeguard lock built into the switch
process.
3. The new oscillator is turned on by the hardware
if it is not currently running. If a crystal oscillator
must be turned on, the hardware waits until the
Oscillator Start-up Timer (OST) expires. If the
new source is using the PLL, the hardware waits
until a PLL lock is detected (LOCK = 1).
Note:
Primary Oscillator mode has three different
submodes (XT, HS, and EC), which are
determined by the POSCMD<1:0> Config-
uration bits. While an application can
switch to and from Primary Oscillator
mode in software, it cannot switch among
the different primary submodes without
reprogramming the device.
4. The hardware waits for 10 clock cycles from the
new clock source and then performs the clock
switch.
5. The hardware clears the OSWEN bit to indicate a
successful clock transition. In addition, the NOSC
bit values are transferred to the COSC status bits.
6. The old clock source is turned off at this time,
with the exception of LPRC (if WDT or FSCM
are enabled) or LP (if LPOSCEN remains set).
8.2.1
ENABLING CLOCK SWITCHING
To enable clock switching, the FCKSM1 Configuration
bit in the Configuration register must be programmed to
‘0’. (Refer to Section 21.1 “Configuration Bits” for
further details.) If the FCKSM1 Configuration bit is
unprogrammed (‘1’), the clock switching function and
Fail-Safe Clock Monitor function are disabled. This is
the default setting.
Note 1: The processor continues to execute code
throughout the clock switching sequence.
Timing-sensitive code should not be
executed during this time.
2: Direct clock switches between any pri-
mary oscillator mode with PLL and
FRCPLL mode are not permitted. This
applies to clock switches in either direc-
tion. In these instances, the application
must switch to FRC mode as a transition
clock source between the two PLL modes.
The NOSC control bits (OSCCON<10:8>) do not
control the clock selection when clock switching is
disabled. However, the COSC bits (OSCCON<14:12>)
reflect the clock source selected by the FNOSC
Configuration bits.
3: Refer to Section 7. “Oscillator”
(DS70186) in the “dsPIC33F/PIC24H
Family Reference Manual” for details.
The OSWEN control bit (OSCCON<0>) has no effect
when clock switching is disabled. It is held at ‘0’ at all
times.
8.2.2
OSCILLATOR SWITCHING SEQUENCE
clock switch requires this basic
8.3
Fail-Safe Clock Monitor (FSCM)
Performing
sequence:
a
The Fail-Safe Clock Monitor allows the device to
continue to operate even in the event of an oscillator
failure. The FSCM function is enabled by programming.
If the FSCM function is enabled, the LPRC internal
oscillator runs at all times (except during Sleep mode)
and is not subject to control by the Watchdog Timer.
1. If
desired,
read
the
COSC
bits
(OSCCON<14:12>) to determine the current
oscillator source.
2. Perform the unlock sequence to allow a write to
the OSCCON register high byte.
In the event of an oscillator failure, the FSCM
generates a clock failure trap event and switches the
system clock over to the FRC oscillator. Then the
application program can either attempt to restart the
oscillator or execute a controlled shutdown. The trap
can be treated as a warm Reset by simply loading the
Reset address into the oscillator fail trap vector.
3. Write the appropriate value to the NOSC control
bits (OSCCON<10:8>) for the new oscillator
source.
4. Perform the unlock sequence to allow a write to
the OSCCON register low byte.
5. Set the OSWEN bit (OSCCON<0>) to initiate
the oscillator switch.
If the PLL multiplier is used to scale the system clock,
the internal FRC is also multiplied by the same factor
on clock failure. Essentially, the device switches to
FRC with PLL on a clock failure.
Once the basic sequence is completed, the system
clock hardware responds automatically as follows:
1. The clock switching hardware compares the
COSC status bits with the new value of the
NOSC control bits. If they are the same, the
clock switch is a redundant operation. In this
case, the OSWEN bit is cleared automatically
and the clock switch is aborted.
DS70265E-page 112
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
9.2
Instruction-Based Power-Saving
Modes
9.0
POWER-SAVING FEATURES
Note 1: This data sheet summarizes the features
of the dsPIC33FJ12MC201/202 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 9. “Watchdog
Timer and Power-Saving Modes”
(DS70196) of the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microchip website
(www.microchip.com).
dsPIC33FJ12MC201/202 devices have two special
power-saving modes that are entered through the
execution of a special PWRSAVinstruction. Sleep mode
stops clock operation and halts all code execution. Idle
mode halts the CPU and code execution, but allows
peripheral modules to continue operation. The
assembler syntax of the PWRSAVinstruction is shown in
Example 9-1.
Note: SLEEP_MODE and IDLE_MODE are
constants defined in the assembler
include file for the selected device.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Sleep and Idle modes can be exited as a result of an
enabled interrupt, WDT time-out or a device Reset. When
the device exits these modes, it is said to wake-up.
9.2.1
SLEEP MODE
The dsPIC33FJ12MC201/202 devices provide the
ability to manage power consumption by selectively
managing clocking to the CPU and the peripherals. In
general, a lower clock frequency and a reduction in the
number of circuits being clocked constitutes lower
consumed power. dsPIC33FJ12MC201/202 devices
can manage power consumption in four different ways:
The following occur in Sleep mode:
• The system clock source is shut down. If an
on-chip oscillator is used, it is turned off.
• The device current consumption is reduced to a
minimum, provided that no I/O pin is sourcing
current
• The Fail-Safe Clock Monitor does not operate,
since the system clock source is disabled
• Clock frequency
• Instruction-based Sleep and Idle modes
• Software-controlled Doze mode
• Selective peripheral control in software
• The LPRC clock continues to run in Sleep mode if
the WDT is enabled
• The WDT, if enabled, is automatically cleared
prior to entering Sleep mode
Combinations of these methods can be used to selec-
tively tailor an application’s power consumption while
still maintaining critical application features, such as
timing-sensitive communications.
• Some device features or peripherals may continue
to operate. This includes items such as the input
change notification on the I/O ports, or peripherals
that use an external clock input.
9.1
Clock Frequency and Clock
Switching
• Any peripheral that requires the system clock
source for its operation is disabled
The device will wake-up from Sleep mode on any of the
these events:
dsPIC33FJ12MC201/202 devices allow a wide range
of clock frequencies to be selected under application
control. If the system clock configuration is not locked,
users can choose low-power or high-precision
oscillators by simply changing the NOSC bits
(OSCCON<10:8>). The process of changing a system
clock during operation, as well as limitations to the
process, are discussed in more detail in Section 8.0
“Oscillator Configuration”.
• Any interrupt source that is individually enabled
• Any form of device Reset
• A WDT time-out
On wake-up from Sleep mode, the processor restarts
with the same clock source that was active when Sleep
mode was entered.
EXAMPLE 9-1:
PWRSAV INSTRUCTION SYNTAX
PWRSAV #SLEEP_MODE
PWRSAV #IDLE_MODE
; Put the device into Sleep mode
; Put the device into Idle mode
© 2007-2011 Microchip Technology Inc.
DS70265E-page 113
dsPIC33FJ12MC201/202
Doze mode is enabled by setting the DOZEN bit
(CLKDIV<11>). The ratio between peripheral and core
clock speed is determined by the DOZE<2:0> bits
(CLKDIV<14:12>). There are eight possible
configurations, from 1:1 to 1:128, with 1:1 being the
default setting.
9.2.2
IDLE MODE
The following occur in Idle mode:
• The CPU stops executing instructions
• The WDT is automatically cleared
• The system clock source remains active. By
default, all peripheral modules continue to operate
normally from the system clock source, but can
also be selectively disabled (see Section 9.4
“Peripheral Module Disable”).
Programs can use Doze mode to selectively reduce
power consumption in event-driven applications. This
allows clock-sensitive functions, such as synchronous
communications, to continue without interruption while
the CPU idles, waiting for something to invoke an
interrupt routine. An automatic return to full-speed CPU
operation on interrupts can be enabled by setting the
ROI bit (CLKDIV<15>). By default, interrupt events
have no effect on Doze mode operation.
• If the WDT or FSCM is enabled, the LPRC also
remains active.
The device will wake from Idle mode on any of these
events:
• Any interrupt that is individually enabled
• Any device Reset
For example, suppose the device is operating at
20 MIPS and the UART module has been configured
for 500 kbps based on this device operating speed. If
the device is placed in Doze mode with a clock
frequency ratio of 1:4, the UART module continues to
communicate at the required bit rate of 500 kbps, but
the CPU now starts executing instructions at a
frequency of 5 MIPS.
• A WDT time-out
On wake-up from Idle mode, the clock is reapplied to
the CPU and instruction execution will begin (2-4 clock
cycles later), starting with the instruction following the
PWRSAVinstruction, or the first instruction in the ISR.
9.2.3
INTERRUPTS COINCIDENT WITH
POWER-SAVE INSTRUCTIONS
9.4
Peripheral Module Disable
Any interrupt that coincides with the execution of a
PWRSAVinstruction is held off until entry into Sleep or
Idle mode has completed. The device then wakes up
from Sleep or Idle mode.
The Peripheral Module Disable (PMD) registers
provide a method to disable a peripheral module by
stopping all clock sources supplied to that module.
When a peripheral is disabled using the appropriate
PMD control bit, the peripheral is in a minimum power
consumption state. The control and status registers
associated with the peripheral are also disabled, so
writes to those registers will have no effect and read
values will be invalid.
9.3
Doze Mode
The preferred strategies for reducing power
consumption are changing clock speed and invoking
one of the power-saving modes. In some
circumstances, this may not be practical. For example,
it may be necessary for an application to maintain
uninterrupted synchronous communication, even while
it is doing nothing else. Reducing system clock speed
can introduce communication errors, while using a
power-saving mode can stop communications
completely.
A peripheral module is enabled only if both the
associated bit in the PMD register is cleared and the
peripheral is supported by the specific dsPIC® DSC
variant. If the peripheral is present in the device, it is
enabled in the PMD register by default.
Note:
If a PMD bit is set, the corresponding
module is disabled after a delay of one
instruction cycle. Similarly, if a PMD bit is
cleared, the corresponding module is
enabled after a delay of one instruction
cycle (assuming the module control regis-
ters are already configured to enable
module operation).
Doze mode is a simple and effective alternative method
to reduce power consumption while the device is still
executing code. In this mode, the system clock
continues to operate from the same source and at the
same speed. Peripheral modules continue to be
clocked at the same speed, while the CPU clock speed
is reduced. Synchronization between the two clock
domains is maintained, allowing the peripherals to
access the SFRs while the CPU executes code at a
slower rate.
DS70265E-page 114
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
REGISTER 9-1:
PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1
U-0
—
U-0
—
R/W-0
T3MD
R/W-0
T2MD
R/W-0
T1MD
R/W-0
R/W-0
U-0
—
QEIMD
PWM1MD
bit 15
bit 8
R/W-0
I2C1MD
bit 7
U-0
—
R/W-0
U1MD
U-0
—
R/W-0
U-0
—
U-0
—
R/W-0
AD1MD(1)
SPI1MD
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13
Unimplemented: Read as ‘0’
T3MD: Timer3 Module Disable bit
1= Timer3 module is disabled
0= Timer3 module is enabled
bit 12
bit 11
bit 10
bit 9
T2MD: Timer2 Module Disable bit
1= Timer2 module is disabled
0= Timer2 module is enabled
T1MD: Timer1 Module Disable bit
1= Timer1 module is disabled
0= Timer1 module is enabled
QEIMD: QEI Module Disable bit
1= QEI module is disabled
0= QEI module is enabled
PWM1MD: PWM1 Module Disable bit
1= PWM1 module is disabled
0= PWM1 module is enabled
bit 18
bit 7
Unimplemented: Read as ‘0’
I2C1MD: I2C1 Module Disable bit
1= I2C1 module is disabled
0= I2C1 module is enabled
bit 6
bit 5
Unimplemented: Read as ‘0’
U1MD: UART1 Module Disable bit
1= UART1 module is disabled
0= UART1 module is enabled
bit 4
bit 3
Unimplemented: Read as ‘0’
SPI1MD: SPI1 Module Disable bit
1= SPI1 module is disabled
0= SPI1 module is enabled
bit 2-1
bit 0
Unimplemented: Read as ‘0’
AD1MD: ADC1 Module Disable bit(1)
1= ADC1 module is disabled
0= ADC1 module is enabled
Note 1: PCFGx bits have no effect if the ADC module is disabled by setting this bit. When the bit is set, all port
pins that have been multiplexed with ANx will be in Digital mode.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 115
dsPIC33FJ12MC201/202
REGISTER 9-2:
R/W-0
PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
IC8MD
IC7MD
IC2MD
IC1MD
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
OC2MD
OC1MD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
bit 14
IC8MD: Input Capture 8 Module Disable bit
1= Input Capture 8 module is disabled
0= Input Capture 8 module is enabled
IC7MD: Input Capture 2 Module Disable bit
1= Input Capture 7 module is disabled
0= Input Capture 7 module is enabled
bit 13-10
bit 9
Unimplemented: Read as ‘0’
IC2MD: Input Capture 2 Module Disable bit
1= Input Capture 2 module is disabled
0= Input Capture 2 module is enabled
bit 8
IC1MD: Input Capture 1 Module Disable bit
1= Input Capture 1 module is disabled
0= Input Capture 1 module is enabled
bit 7-2
bit 1
Unimplemented: Read as ‘0’
OC2MD: Output Compare 2 Module Disable bit
1= Output Compare 2 module is disabled
0= Output Compare 2 module is enabled
bit 0
OC1MD: Output Compare 1 Module Disable bit
1= Output Compare 1 module is disabled
0= Output Compare 1 module is enabled
DS70265E-page 116
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
REGISTER 9-3:
PMD3: PERIPHERAL MODULE DISABLE CONTROL REGISTER 3
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
PWM2MD
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-5
bit 4
Unimplemented: Read as ‘0’
PWM2MD: PWM2 Module Disable bit
1= PWM2 module is disabled
0= PWM2 module is enabled
bit 3-0
Unimplemented: Read as ‘0’
© 2007-2011 Microchip Technology Inc.
DS70265E-page 117
dsPIC33FJ12MC201/202
NOTES:
DS70265E-page 118
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
the I/O pin. The logic also prevents “loop through,” in
which a port’s digital output can drive the input of a
peripheral that shares the same pin. Figure 10-1 shows
how ports are shared with other peripherals and the
associated I/O pin to which they are connected.
10.0 I/O PORTS
Note 1: This data sheet summarizes the features
of the dsPIC33FJ12MC201/202 family of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to Section 10. “I/O Ports”
(DS70193) of the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microchip website
(www.microchip.com).
When a peripheral is enabled and the peripheral is
actively driving an associated pin, the use of the pin as
a general purpose output pin is disabled. The I/O pin
can be read, but the output driver for the parallel port bit
is disabled. If a peripheral is enabled, but the peripheral
is not actively driving a pin, that pin can be driven by a
port.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
All port pins have three registers directly associated
with their operation as digital I/O. The data direction
register (TRISx) determines whether the pin is an input
or an output. If the data direction bit is a ‘1’, the pin is
an input. All port pins are defined as inputs after a
Reset. Reads from the latch (LATx) read the latch.
Writes to the latch write the latch. Reads from the port
(PORTx) read the port pins, while writes to the port pins
write the latch.
All of the device pins (except VDD, VSS, MCLR, and
OSC1/CLKI) are shared among the peripherals and the
parallel I/O ports. All I/O input ports feature Schmitt
Trigger inputs for improved noise immunity.
Any bit and its associated data and control registers
that are not valid for a particular device will be
disabled. This means the corresponding LATx and
TRISx registers and the port pin will read as zeros.
10.1 Parallel I/O (PIO) Ports
Generally a parallel I/O port that shares a pin with a
peripheral is subservient to the peripheral. The
peripheral’s output buffer data and control signals are
provided to a pair of multiplexers. The multiplexers
select whether the peripheral or the associated port
has ownership of the output data and control signals of
When a pin is shared with another peripheral or
function that is defined as an input only, it is
nevertheless regarded as a dedicated port because
there is no other competing source of outputs.
FIGURE 10-1:
BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE
Peripheral Module
Output Multiplexers
Peripheral Input Data
Peripheral Module Enable
I/O
Peripheral Output Enable
Peripheral Output Data
1
Output Enable
0
PIO Module
1
Output Data
Read TRIS
0
Data Bus
WR TRIS
D
Q
I/O Pin
CK
TRIS Latch
D
Q
WR LAT +
WR Port
CK
Data Latch
Read LAT
Read Port
Input Data
© 2007-2011 Microchip Technology Inc.
DS70265E-page 119
dsPIC33FJ12MC201/202
10.1.1
OPEN-DRAIN CONFIGURATION
10.3 Input Change Notification
In addition to the PORT, LAT, and TRIS registers for
data control, some port pins can also be individually
configured for either digital or open-drain output. This
is controlled by the Open-Drain Control register,
ODCx, associated with each port. Setting any of the
bits configures the corresponding pin to act as an
open-drain output.
The input change notification function of the I/O ports
allows the dsPIC33FJ12MC201/202 devices to gener-
ate interrupt requests to the processor in response to a
change-of-state on selected input pins. This feature
can detect input change-of-states even in Sleep mode,
when the clocks are disabled. Depending on the device
pin count, up to 21 external signals (CNx pin) can be
selected (enabled) for generating an interrupt request
on a change-of-state.
The open-drain feature allows the generation of
outputs higher than VDD (e.g., 5V) on any 5V-tolerant
pins by using external pull-up resistors. The maximum
open-drain voltage allowed is the same as the
maximum VIH specification.
Four control registers are associated with the CN mod-
ule. The CNEN1 and CNEN2 registers contain the
interrupt enable control bits for each of the CN input
pins. Setting any of these bits enables a CN interrupt
for the corresponding pins.
See “Pin Diagrams” for the available pins and their
functionality.
Each CN pin also has a weak pull-up connected to it.
The pull-ups act as a current source connected to the
pin, and eliminate the need for external resistors when
push-button or keypad devices are connected. The
pull-ups are enabled separately using the CNPU1 and
CNPU2 registers, which contain the control bits for
each of the CN pins. Setting any of the control bits
enables the weak pull-ups for the corresponding pins.
10.2 Configuring Analog Port Pins
The AD1PCFG and TRIS registers control the opera-
tion of the analog-to-digital (A/D) port pins. The port
pins that are to function as analog inputs must have
their corresponding TRIS bit set (input). If the TRIS bit
is cleared (output), the digital output level (VOH or VOL)
will be converted.
Note:
Pull-ups on change notification pins
should always be disabled when the port
pin is configured as a digital output.
The AD1PCFGL register has a default value of 0x0000;
therefore, all pins that share ANx functions are analog
(not digital) by default.
When the PORT register is read, all pins configured as
analog input channels will read as cleared (a low level).
Pins configured as digital inputs will not convert an
analog input. Analog levels on any pin defined as a
digital input (including the ANx pins) can cause the
input buffer to consume current that exceeds the
device specifications.
10.2.1
I/O PORT WRITE/READ TIMING
One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically this instruction
would be an NOP. An demonstration is shown in
Example 10-1.
EXAMPLE 10-1:
PORT WRITE/READ EXAMPLE
MOV
MOV
NOP
0xFF00, W0
W0, TRISBB
; Configure PORTB<15:8> as inputs
; and PORTB<7:0> as outputs
; Delay 1 cycle
btss PORTB, #13
; Next Instruction
DS70265E-page 120
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
10.4.2.1
Input Mapping
10.4 Peripheral Pin Select
The inputs of the peripheral pin select options are
mapped on the basis of the peripheral. A control
register associated with a peripheral dictates the pin it
will be mapped to. The RPINRx registers are used to
configure peripheral input mapping (see Register 10-1
through Register 10-13). Each register contains sets
of 5-bit fields, with each set associated with one of the
Peripheral pin select configuration enables peripheral
set selection and placement on a wide range of I/O
pins. By increasing the pinout options available on a
particular device, programmers can better tailor the
microcontroller to their entire application, rather than
trimming the application to fit the device.
The peripheral pin select configuration feature oper-
ates over a fixed subset of digital I/O pins. Program-
mers can independently map the input and/or output
of most digital peripherals to any one of these I/O
pins. Peripheral pin select is performed in software,
and generally does not require the device to be
reprogrammed. Hardware safeguards are included
that prevent accidental or spurious changes to the
peripheral mapping, once it has been established.
remappable peripherals. Programming
a
given
peripheral’s bit field with an appropriate 5-bit value
maps the RPn pin with that value to that peripheral.
For any given device, the valid range of values for any
bit field corresponds to the maximum number of
peripheral pin selections supported by the device.
Figure 10-2 Illustrates remappable pin selection for
U1RX input.
Note:
For input mapping only, the Peripheral Pin
Select (PPS) functionality does not have
priority over the TRISx settings. There-
fore, when configuring the RPx pin for
input, the corresponding bit in the TRISx
register must also be configured for input
(i.e., set to ‘1’).
10.4.1
AVAILABLE PINS
The peripheral pin select feature is used with a range
of up to 16 pins. The number of available pins depends
on the particular device and its pin count. Pins that
support the peripheral pin select feature include the
designation “RPn” in their full pin designation, where
“RP” designates a remappable peripheral and “n” is the
remappable pin number.
FIGURE 10-2:
REMAPPABLE MUX
INPUT FOR U1RX
10.4.2
CONTROLLING PERIPHERAL PIN
SELECT
U1RXR<4:0>
Peripheral pin select features are controlled through
two sets of special function registers: one to map
peripheral inputs, and one to map outputs. Because
they are separately controlled, a particular peripheral’s
input and output (if the peripheral has both) can be
placed on any selectable function pin without
constraint.
0
RP0
RP1
RP2
1
U1RX input
to peripheral
The association of a peripheral to a peripheral select-
able pin is handled in two different ways, depending on
whether an input or output is being mapped.
2
15
RP15
© 2007-2011 Microchip Technology Inc.
DS70265E-page 121
dsPIC33FJ12MC201/202
(1)
TABLE 10-1: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION)
Configuration
Bits
Input Name
Function Name
Register
External Interrupt 1
INT1
INT2
T2CK
T3CK
IC1
RPINR0
RPINR1
INT1R<4:0>
INT2R<4:0>
T2CKR<4:0>
T3CKR<4:0>
IC1R<4:0>
External Interrupt 2
Timer2 External Clock
Timer3 External Clock
Input Capture 1
RPINR3
RPINR3
RPINR7
Input Capture 2
IC2
RPINR7
IC2R<4:0>
Input Capture 7
IC7
RPINR10
RPINR10
RPINR11
RPINR12
RPINR13
RPINR14
RPINR14
RPINR15
RPINR18
RPINR18
RPINR20
RPINR20
RPINR21
IC7R<4:0>
Input Capture 8
IC8
IC8R<4:0>
Output Compare Fault A
PWM1 Fault
OCFA
FLTA1
FLTA2
QEA
QEB
INDX
U1RX
U1CTS
SDI1
SCK1
SS1
OCFAR<4:0>
FLTA1R<4:0>
FLTA2R<4:0>
QEA1R<4:0>
QEB1R<4:0>
INDX1R<4:0>
U1RXR<4:0>
U1CTSR<4:0>
SDI1R<4:0>
SCK1R<4:0>
SS1R<4:0>
PWM2 Fault
QEI1 Phase A
QEI1 Phase B
QEI1 Index
UART1 Receive
UART1 Clear To Send
SPI1 Data Input
SPI1 Clock Input
SPI1 Slave Select Input
Note 1: Unless otherwise noted, all inputs use the Schmitt input buffers.
10.4.2.2 Output Mapping FIGURE 10-3:
MULTIPLEXING OF
REMAPPABLE OUTPUT
FOR RPn
In contrast to inputs, the outputs of the peripheral pin
select options are mapped on the basis of the pin. In
this case, a control register associated with a particular
pin dictates the peripheral output to be mapped. The
RPORx registers are used to control output mapping.
Like the RPINRx registers, each register contains sets
of 5-bit fields, with each set associated with one RPn
pin (see Register 10-14 through Register 10-21). The
value of the bit field corresponds to one of the periph-
erals, and that peripheral’s output is mapped to the pin
(see Table 10-2 and Figure 10-3).
RPnR<4:0>
default
U1TX Output enable
0
3
4
U1RTS Output enable
Output enable
The list of peripherals for output mapping also includes
a null value of ‘00000’ because of the mapping
technique. This permits any given pin to remain
unconnected from the output of any of the pin
selectable peripherals.
OC2 Output enable
UPDN Output enable
19
26
default
0
3
4
U1TX Output
U1RTS Output
RPn
Output Data
OC2 Output
19
26
UPDN Output
DS70265E-page 122
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
TABLE 10-2: OUTPUT SELECTION FOR REMAPPABLE PIN (RPn)
Function
RPnR<4:0>
Output Name
RPn tied to default port pin
NULL
U1TX
00000
00011
00100
00111
01000
01001
10010
10011
11010
RPn tied to UART1 Transmit
U1RTS
SDO1
RPn tied to UART1 Ready To Send
RPn tied to SPI1 Data Output
SCK1OUT
SS1OUT
OC1
RPn tied to SPI1 Clock Output
RPn tied to SPI1 Slave Select Output
RPn tied to Output Compare 1
RPn tied to Output Compare 2
RPn tied to QEI direction (UPDN) status
OC2
UPDN
10.4.3
CONTROLLING CONFIGURATION
CHANGES
10.4.3.2
Continuous State Monitoring
In addition to being protected from direct writes, the
contents of the RPINRx and RPORx registers are
constantly monitored in hardware by shadow registers.
If an unexpected change in any of the registers occurs
(such as cell disturbances caused by ESD or other
external events), a configuration mismatch Reset will
be triggered.
Because peripheral remapping can be changed during
run time, some restrictions on peripheral remapping
are needed to prevent accidental configuration
changes. dsPIC33FJ12MC201/202 devices include
three features to prevent alterations to the peripheral
map:
• Control register lock sequence
• Continuous state monitoring
• Configuration bit pin select lock
10.4.3.3
Configuration Bit Pin Select Lock
As an additional level of safety, the device can be
configured to prevent more than one write session to
the RPINRx and RPORx registers. The IOL1WAY
(FOSC<IOL1WAY>) configuration bit blocks the
IOLOCK bit from being cleared after it has been set
once. If IOLOCK remains set, the register unlock
procedure will not execute, and the peripheral pin
select control registers cannot be written to. The only
way to clear the bit and re-enable peripheral remapping
is to perform a device Reset.
10.4.3.1
Control Register Lock
Under normal operation, writes to the RPINRx and
RPORx registers are not allowed. Attempted writes
appear to execute normally, but the contents of the
registers remain unchanged. To change these
registers, they must be unlocked in hardware. The
register lock is controlled by the IOLOCK bit
(OSCCON<6>). Setting IOLOCK prevents writes to the
control registers; clearing IOLOCK allows writes.
In the default (unprogrammed) state, IOL1WAY is set,
restricting users to one write session. Programming
IOL1WAY allows user applications unlimited access
(with the proper use of the unlock sequence) to the
peripheral pin select registers.
To set or clear IOLOCK, a specific command sequence
must be executed:
1. Write 0x46 to OSCCON<7:0>.
2. Write 0x57 to OSCCON<7:0>.
10.5 Peripheral Pin Select Registers
3. Clear (or set) IOLOCK as a single operation.
The dsPIC33FJ12MC201/202 family of devices
implement 21 registers for remappable peripheral
configuration:
Note:
MPLAB® C30 provides built-in
language functions for unlocking the
OSCCON register:
C
• Input Remappable Peripheral Registers (13)
• Output Remappable Peripheral Registers (8)
__builtin_write_OSCCONL(value)
__builtin_write_OSCCONH(value)
See MPLAB IDE Help for more
information.
Note:
Input and Output Register values can only
be changed if OSCCON<IOLOCK> = 0.
See Section 10.4.3.1 “Control Register
Lock” for a specific command sequence.
Unlike the similar sequence with the oscillator’s LOCK
bit, IOLOCK remains in one state until changed. This
allows all of the peripheral pin selects to be configured
with a single unlock sequence followed by an update to
all control registers, then locked with a second lock
sequence.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 123
dsPIC33FJ12MC201/202
REGISTER 10-1: RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
bit 8
INT1R<4:0>
bit 15
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
INT1R<4:0>: Assign External Interrupt 1 (INTR1) to the corresponding RPn pin
11111= Input tied VSS
01111= Input tied to RP15
.
.
.
00001= Input tied to RP1
00000= Input tied to RP0
bit 7-0
Unimplemented: Read as ‘0’
DS70265E-page 124
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
REGISTER 10-2: RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-1
bit 0
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
INT2R<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-5
bit 4-0
Unimplemented: Read as ‘0’
INT2R<4:0>: Assign External Interrupt 2 (INTR2) to the corresponding RPn pin
11111= Input tied VSS
01111= Input tied to RP15
.
.
.
00001= Input tied to RP1
00000= Input tied to RP0
© 2007-2011 Microchip Technology Inc.
DS70265E-page 125
dsPIC33FJ12MC201/202
REGISTER 10-3: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
bit 8
R/W-1
bit 0
T3CKR<4:0>
bit 15
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
T2CKR<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
T3CKR<4:0>: Assign Timer3 External Clock (T3CK) to the corresponding RPn pin
11111= Input tied VSS
01111= Input tied to RP15
.
.
.
00001= Input tied to RP1
00000= Input tied to RP0
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
T2CKR<4:0>: Assign Timer2 External Clock (T2CK) to the corresponding RPn pin
11111= Input tied VSS
01111= Input tied to RP15
.
.
.
00001= Input tied to RP1
00000= Input tied to RP0
DS70265E-page 126
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
REGISTER 10-4: RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
bit 8
R/W-1
bit 0
IC2R<4:0>
bit 15
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
IC1R<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
IC2R<4:0>: Assign Input Capture 2 (IC2) to the corresponding RPn pin
11111= Input tied VSS
01111= Input tied to RP15
.
.
.
00001= Input tied to RP1
00000= Input tied to RP0
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
IC1R<4:0>: Assign Input Capture 1 (IC1) to the corresponding RPn pin
11111= Input tied VSS
01111= Input tied to RP15
.
.
.
00001= Input tied to RP1
00000= Input tied to RP0
© 2007-2011 Microchip Technology Inc.
DS70265E-page 127
dsPIC33FJ12MC201/202
REGISTER 10-5: RPINR10: PERIPHERAL PIN SELECT INPUT REGISTER 10
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
bit 8
R/W-1
bit 0
IC8R<4:0>
bit 15
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
IC7R<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
IC8R<4:0>: Assign Input Capture 8 (IC8) to the corresponding pin RPn pin
11111= Input tied VSS
01111= Input tied to RP15
.
.
.
00001= Input tied to RP1
00000= Input tied to RP0
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
IC7R<4:0>: Assign Input Capture 7 (IC7) to the corresponding pin RPn pin
11111= Input tied VSS
01111= Input tied to RP15
.
.
.
00001= Input tied to RP1
00000= Input tied to RP0
DS70265E-page 128
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
REGISTER 10-6: RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-1
bit 0
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
OCFAR<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-5
bit 4-0
Unimplemented: Read as ‘0’
OCFAR<4:0>: Assign Output Capture A (OCFA) to the corresponding RPn pin
11111= Input tied VSS
01111= Input tied to RP15
.
.
.
00001= Input tied to RP1
00000= Input tied to RP0
REGISTER 10-7: RPINR12: PERIPHERAL PIN SELECT INPUT REGISTER 12
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-1
bit 0
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
FLTA1R<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-5
bit 4-0
Unimplemented: Read as ‘0’
FLTA1R<4:0>: Assign PWM1 Fault (FLTA1) to the corresponding RPn pin
11111= Input tied VSS
01111= Input tied to RP15
.
.
.
00001= Input tied to RP1
00000= Input tied to RP0
© 2007-2011 Microchip Technology Inc.
DS70265E-page 129
dsPIC33FJ12MC201/202
REGISTER 10-8: RPINR13: PERIPHERAL PIN SELECT INPUT REGISTER 13
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-1
bit 0
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
FLTA2R<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-5
bit 4-0
Unimplemented: Read as ‘0’
FLTA2R<4:0>: Assign PWM2 Fault (FLTA2) to the corresponding RPn pin
11111= Input tied VSS
01111= Input tied to RP15
.
.
.
00001= Input tied to RP1
00000= Input tied to RP0
DS70265E-page 130
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
REGISTER 10-9: RPINR14: PERIPHERAL PIN SELECT INPUT REGISTER 14
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
bit 8
R/W-1
bit 0
QEB1R<4:0>
bit 15
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
QEA1R<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
QEB1R<4:0>: Assign B (QEB) to the corresponding pin
11111= Input tied VSS
01111= Input tied to RP15
.
.
.
00001= Input tied to RP1
00000= Input tied to RP0
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
QEA1R<4:0>: Assign A (QEA) to the corresponding pin
11111= Input tied VSS
01111= Input tied to RP15
.
.
.
00001= Input tied to RP1
00000= Input tied to RP0
© 2007-2011 Microchip Technology Inc.
DS70265E-page 131
dsPIC33FJ12MC201/202
REGISTER 10-10: RPINR15: PERIPHERAL PIN SELECT INPUT REGISTER 15
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-1
bit 0
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
INDX1R<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-5
bit 4-0
Unimplemented: Read as ‘0’
INDX1R<4:0>: Assign QEI1 INDEX (INDX1) to the corresponding RPn pin
11111= Input tied VSS
01111= Input tied to RP15
.
.
.
00001= Input tied to RP1
00000= Input tied to RP0
DS70265E-page 132
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
REGISTER 10-11: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
bit 8
R/W-1
bit 0
U1CTSR<4:0>
bit 15
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
U1RXR<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
U1CTSR<4:0>: Assign UART1 Clear to Send (U1CTS) to the corresponding RPn pin
11111= Input tied VSS
01111= Input tied to RP15
.
.
.
00001= Input tied to RP1
00000= Input tied to RP0
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
U1RXR<4:0>: Assign UART1 Receive (U1RX) to the corresponding RPn pin
11111= Input tied VSS
01111= Input tied to RP15
.
.
.
00001= Input tied to RP1
00000= Input tied to RP0
© 2007-2011 Microchip Technology Inc.
DS70265E-page 133
dsPIC33FJ12MC201/202
REGISTER 10-12: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
bit 8
R/W-1
bit 0
SCK1R<4:0>
bit 15
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
SDI1R<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
SCK1R<4:0>: Assign SPI1 Clock Input (SCK1IN) to the corresponding RPn pin
11111= Input tied VSS
01111= Input tied to RP15
.
.
.
00001= Input tied to RP1
00000= Input tied to RP0
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
SDI1R<4:0>: Assign SPI1 Data Input (SDI1) to the corresponding RPn pin
11111= Input tied VSS
01111= Input tied to RP15
.
.
.
00001= Input tied to RP1
00000= Input tied to RP0
DS70265E-page 134
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
REGISTER 10-13: RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-1
bit 0
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
SS1R<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-5
bit 4-0
Unimplemented: Read as ‘0’
SS1R<4:0>: Assign SPI1 Slave Select Input (SS1IN) to the corresponding RPn pin
11111= Input tied VSS
01111= Input tied to RP15
.
.
.
00001= Input tied to RP1
00000= Input tied to RP0
© 2007-2011 Microchip Technology Inc.
DS70265E-page 135
dsPIC33FJ12MC201/202
REGISTER 10-14: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
RP1R<4:0>
bit 15
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
RP0R<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
RP1R<4:0>: Peripheral Output Function is Assigned to RP1 Output Pin bits (see Table 10-2 for
peripheral function numbers)
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
RP0R<4:0>: Peripheral Output Function is Assigned to RP0 Output Pin bits (see Table 10-2 for
peripheral function numbers)
REGISTER 10-15: RPOR1: PERIPHERAL PIN SELECT OUTPUT REGISTER 1
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
RP3R<4:0>
bit 15
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
RP2R<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
RP3R<4:0>: Peripheral Output Function is Assigned to RP3 Output Pin bits (see Table 10-2 for
peripheral function numbers)
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
RP2R<4:0>: Peripheral Output Function is Assigned to RP2 Output Pin bits (see Table 10-2 for
peripheral function numbers)
DS70265E-page 136
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
REGISTER 10-16: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTER 2
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
RP5R<4:0>
bit 15
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
RP4R<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
RP5R<4:0>: Peripheral Output Function is Assigned to RP5 Output Pin bits (see Table 10-2 for
peripheral function numbers)
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
RP4R<4:0>: Peripheral Output Function is Assigned to RP4 Output Pin bits (see Table 10-2 for
peripheral function numbers)
REGISTER 10-17: RPOR3: PERIPHERAL PIN SELECT OUTPUT REGISTER 3
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
RP7R<4:0>
bit 15
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
RP6R<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
RP7R<4:0>: Peripheral Output Function is Assigned to RP7 Output Pin bits (see Table 10-2 for
peripheral function numbers)
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
RP6R<4:0>: Peripheral Output Function is Assigned to RP6 Output Pin bits (see Table 10-2 for
peripheral function numbers)
© 2007-2011 Microchip Technology Inc.
DS70265E-page 137
dsPIC33FJ12MC201/202
REGISTER 10-18: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
RP9R<4:0>
bit 15
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
RP8R<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
RP9R<4:0>: Peripheral Output Function is Assigned to RP9 Output Pin bits (see Table 10-2 for
peripheral function numbers)
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
RP8R<4:0>: Peripheral Output Function is Assigned to RP8 Output Pin bits (see Table 10-2 for
peripheral function numbers)
REGISTER 10-19: RPOR5: PERIPHERAL PIN SELECT OUTPUT REGISTER 5
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
RP11R<4:0>
bit 15
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
RP10R<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
RP11R<4:0>: Peripheral Output Function is Assigned to RP11 Output Pin bits (see Table 10-2 for
peripheral function numbers)
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
RP10R<4:0>: Peripheral Output Function is Assigned to RP10 Output Pin bits (see Table 10-2 for
peripheral function numbers)
DS70265E-page 138
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
REGISTER 10-20: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
RP13R<4:0>
bit 15
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
RP12R<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
RP13R<4:0>: Peripheral Output Function is Assigned to RP13 Output Pin bits (see Table 10-2 for
peripheral function numbers)
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
RP12R<4:0>: Peripheral Output Function is Assigned to RP12 Output Pin bits (see Table 10-2 for
peripheral function numbers)
REGISTER 10-21: RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTER 7
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
RP15R<4:0>
bit 15
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
RP14R<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
RP15R<4:0>: Peripheral Output Function is Assigned to RP15 Output Pin bits (see Table 10-2 for
peripheral function numbers)
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
RP14R<4:0>: Peripheral Output Function is Assigned to RP14 Output Pin bits (see Table 10-2 for
peripheral function numbers)
© 2007-2011 Microchip Technology Inc.
DS70265E-page 139
dsPIC33FJ12MC201/202
NOTES:
DS70265E-page 140
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
Timer1 also supports these features:
11.0 TIMER1
• Timer gate operation
Note 1: This data sheet summarizes the features
of the dsPIC33FJ12MC201/202 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 11. “Timers”
(DS70205) of the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microchip website
(www.microchip.com).
• Selectable prescaler settings
• Timer operation during CPU Idle and Sleep
modes
• Interrupt on 16-bit Period register match or falling
edge of external gate signal
Figure 11-1 presents a block diagram of the 16-bit timer
module.
To configure Timer1 for operation:
1. Set the TON bit (= 1) in the T1CON register.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
2. Select the timer prescaler ratio using the
TCKPS<1:0> bits in the T1CON register.
3. Set the Clock and Gating modes using the TCS
and TGATE bits in the T1CON register.
4. Set or clear the TSYNC bit in T1CON to select
synchronous or asynchronous operation.
The Timer1 module is a 16-bit timer, which can serve
as the time counter for the real-time clock, or operate
as a free-running interval timer/counter. Timer1 can
operate in three modes:
5. Load the timer period value into the PR1
register.
6. If interrupts are required, set the interrupt enable
bit, T1IE. Use the priority bits, T1IP<2:0>, to set
the interrupt priority.
• 16-bit Timer
• 16-bit Synchronous Counter
• 16-bit Asynchronous Counter
FIGURE 11-1:
16-BIT TIMER1 MODULE BLOCK DIAGRAM
TCKPS<1:0>
TON
2
SOSCO/
1x
01
00
T1CK
Prescaler
1, 8, 64, 256
Gate
Sync
SOSCEN
SOSCI
TCY
TGATE
TCS
TGATE
1
0
Q
Q
D
Set T1IF
CK
0
Reset
Equal
TMR1
1
Sync
TSYNC
Comparator
PR1
© 2007-2011 Microchip Technology Inc.
DS70265E-page 141
dsPIC33FJ12MC201/202
REGISTER 11-1: T1CON: TIMER1 CONTROL REGISTER
R/W-0
TON
U-0
—
R/W-0
TSIDL
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0
R/W-0
TCS
U-0
—
TGATE
TCKPS<1:0>
TSYNC
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
TON: Timer1 On bit
1= Starts 16-bit Timer1
0= Stops 16-bit Timer1
bit 14
bit 13
Unimplemented: Read as ‘0’
TSIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12-7
bit 6
Unimplemented: Read as ‘0’
TGATE: Timer1 Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1= Gated time accumulation enabled
0= Gated time accumulation disabled
bit 5-4
TCKPS<1:0>: Timer1 Input Clock Prescale Select bits
11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
bit 3
bit 2
Unimplemented: Read as ‘0’
TSYNC: Timer1 External Clock Input Synchronization Select bit
When TCS = 1:
1= Synchronize external clock input
0= Do not synchronize external clock input
When TCS = 0:
This bit is ignored.
bit 1
bit 0
TCS: Timer1 Clock Source Select bit
1= External clock from pin T1CK (on the rising edge)
0= Internal clock (FCY)
Unimplemented: Read as ‘0’
DS70265E-page 142
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
12.1 32-bit Operation
12.0 TIMER2/3 FEATURE
To configure the Timer2/3 feature timers for 32-bit
operation:
Note 1: This data sheet summarizes the features
of the dsPIC33FJ12MC201/202 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 11. “Timers”
(DS70205) of the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microchip website
(www.microchip.com).
1. Set the T32 control bit.
2. Select the prescaler ratio for Timer2 using the
TCKPS<1:0> bits.
3. Set the Clock and Gating modes using the
corresponding TCS and TGATE bits.
4. Load the timer period value. PR3 contains the
msw of the value, while PR2 contains the least
significant word.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
5. If interrupts are required, set the interrupt enable
bit, T3IE. Use the priority bits, T3IP<2:0>, to set
the interrupt priority. While Timer2 controls the
timer, the interrupt appears as
interrupt.
a Timer3
6. Set the corresponding TON bit.
The Timer2/3 feature has three 2-bit timers that can
also be configured as two independent 16-bit timers
with selectable operating modes.
The timer value at any point is stored in the register
pair, TMR3:TMR2, which always contains the msw of
the count, while TMR2 contains the least significant
word.
As a 32-bit timer, the Timer2/3 feature permits
operation in three modes:
12.2 16-bit Operation
• Two Independent 16-bit timers (e.g., Timer2 and
Timer3) with all 16-bit operating modes (except
Asynchronous Counter mode)
To configure any of the timers for individual 16-bit
operation:
• Single 32-bit timer (Timer2/3)
1. Clear the T32 bit corresponding to that timer.
• Single 32-bit synchronous counter (Timer2/3)
2. Select the timer prescaler ratio using the
TCKPS<1:0> bits.
The Timer2/3 feature also supports:
• Timer gate operation
3. Set the Clock and Gating modes using the TCS
and TGATE bits.
• Selectable prescaler settings
4. Load the timer period value into the PRx
register.
• Timer operation during Idle and Sleep modes
• Interrupt on a 32-bit period register match
5. If interrupts are required, set the interrupt enable
bit, TxIE. Use the priority bits, TxIP<2:0>, to set
the interrupt priority.
• Time base for Input Capture and Output Compare
modules (Timer2 and Timer3 only)
• ADC1 event trigger (Timer2/3 only)
6. Set the TON bit.
Individually, all eight of the 16-bit timers can function as
synchronous timers or counters. They also offer the
features listed above, except for the event trigger. The
operating modes and enabled features are determined
by setting the appropriate bit(s) in the T2CON, T3CON
registers. T2CON registers are shown in generic form
in Register 12-1. T3CON registers are shown in
Register 12-2.
For 32-bit timer/counter operation, Timer2 is the least
significant word, and Timer3 is the msw of the 32-bit
timers.
Note:
For 32-bit operation, T3CON control bits
are ignored. Only T2CON control bits are
used for setup and control. Timer2 clock
and gate inputs are used for the 32-bit
timer modules, but an interrupt is
generated with the Timer3 interrupt flags.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 143
dsPIC33FJ12MC201/202
(1)
FIGURE 12-1:
TIMER2/3 (32-BIT) BLOCK DIAGRAM
TCKPS<1:0>
2
TON
1x
01
00
T2CK
Gate
Sync
Prescaler
1, 8, 64, 256
TCY
TGATE
TCS
TGATE
1
0
Q
Q
D
Set T3IF
CK
PR2
PR3
ADC Event Trigger(2)
Equal
Reset
Comparator
MSb
LSb
TMR3
TMR2
Sync
16
Read TMR2
Write TMR2
16
16
TMR3HLD
16
Data Bus<15:0>
Note 1: The 32-bit timer control bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective
to the T2CON register.
2: The ADC event trigger is available only on Timer2/3.
DS70265E-page 144
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
FIGURE 12-2:
TIMER2 (16-BIT) BLOCK DIAGRAM
TCKPS<1:0>
2
TON
T2CK
1x
01
00
Prescaler
1, 8, 64, 256
Gate
Sync
TGATE
TCS
TGATE
TCY
1
0
Q
D
Set T2IF
Q
CK
Reset
Equal
Sync
TMR2
Comparator
PR2
© 2007-2011 Microchip Technology Inc.
DS70265E-page 145
dsPIC33FJ12MC201/202
REGISTER 12-1: T2CON CONTROL REGISTER
R/W-0
TON
U-0
—
R/W-0
TSIDL
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
T32
U-0
—
R/W-0
TCS
U-0
—
TGATE
TCKPS<1:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
TON: Timer2 On bit
When T32 = 1:
1= Starts 32-bit Timer2/3
0= Stops 32-bit Timer2/3
When T32 = 0:
1= Starts 16-bit Timer2
0= Stops 16-bit Timer2
bit 14
bit 13
Unimplemented: Read as ‘0’
TSIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12-7
bit 6
Unimplemented: Read as ‘0’
TGATE: Timer2 Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1= Gated time accumulation enabled
0= Gated time accumulation disabled
bit 5-4
bit 3
TCKPS<1:0>: Timer2 Input Clock Prescale Select bits
11= 1:256
10= 1:64
01= 1:8
00= 1:1
T32: 32-bit Timer Mode Select bit
1= Timer2 and Timer3 form a single 32-bit timer
0= Timer2 and Timer3 act as two 16-bit timers
bit 2
bit 1
Unimplemented: Read as ‘0’
TCS: Timer2 Clock Source Select bit
1= External clock from pin T2CK (on the rising edge)
0= Internal clock (FCY)
bit 0
Unimplemented: Read as ‘0’
DS70265E-page 146
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
REGISTER 12-2: T3CON CONTROL REGISTER
R/W-0
TON(2)
U-0
—
R/W-0
TSIDL(1)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
R/W-0
TGATE(2)
R/W-0
TCKPS<1:0>(2)
R/W-0
U-0
—
U-0
—
R/W-0
TCS(2)
U-0
—
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
TON: Timer3 On bit(2)
1= Starts 16-bit Timer3
0= Stops 16-bit Timer3
bit 14
bit 13
Unimplemented: Read as ‘0’
TSIDL: Stop in Idle Mode bit(1)
1= Discontinue timer operation when device enters Idle mode
0= Continue timer operation in Idle mode
bit 12-7
bit 6
Unimplemented: Read as ‘0’
TGATE: Timer3 Gated Time Accumulation Enable bit(2)
When TCS = 1:
This bit is ignored.
When TCS = 0:
1= Gated time accumulation enabled
0= Gated time accumulation disabled
bit 5-4
TCKPS<1:0>: Timer3 Input Clock Prescale Select bits(2)
11= 1:256 prescale value
10= 1:64 prescale value
01= 1:8 prescale value
00= 1:1 prescale value
bit 3-2
bit 1
Unimplemented: Read as ‘0’
TCS: Timer3 Clock Source Select bit(2)
1= External clock from T3CK pin
0= Internal clock (FOSC/2)
bit 0
Unimplemented: Read as ‘0’
Note 1: When 32-bit timer operation is enabled (T32 = 1) in the Timer Control register (T2CON<3>), the TSIDL bit
must be cleared to operate the 32-bit timer in Idle mode.
2: When the 32-bit timer operation is enabled (T32 = 1) in the Timer Control register (T2CON<3>), these bits
have no effect.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 147
dsPIC33FJ12MC201/202
NOTES:
DS70265E-page 148
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
1. Simple Capture Event modes:
13.0 INPUT CAPTURE
- Capture timer value on every falling edge of
input at ICx pin
Note 1: This data sheet summarizes the features
of the dsPIC33FJ12MC201/202 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 12. “Input Cap-
ture” (DS70198) of the “dsPIC33F/
PIC24H Family Reference Manual”,
which is available from the Microchip
website (www.microchip.com).
- Capture timer value on every rising edge of
input at ICx pin
2. Capture timer value on every edge (rising and
falling)
3. Prescaler Capture Event modes:
- Capture timer value on every 4th rising edge
of input at ICx pin
- Capture timer value on every 16th rising
edge of input at ICx pin
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Each Input Capture channel can select one of two
16-bit timers (Timer2 or Timer3) for the time base.
The selected timer can use either an internal or
external clock.
The Input Capture module is useful in applications
requiring frequency (period) and pulse measurement.
The dsPIC33FJ12MC201/202 devices support up to
eight input capture channels.
Other operational features include:
• Device wake-up from capture pin during CPU
Sleep and Idle modes
• Interrupt on Input Capture event
The Input Capture module captures the 16-bit value of
the selected Time Base register when an event occurs
at the ICx pin. The events that cause a capture event
are listed below in three categories:
• 4-word FIFO buffer for capture values
- Interrupt optionally generated after 1, 2, 3, or
4 buffer locations are filled
• Use of Input Capture to provide additional
sources of external interrupts
FIGURE 13-1:
INPUT CAPTURE BLOCK DIAGRAM
From 16-bit Timers
TMR2 TMR3
16
16
ICTMR
(ICxCON<7>)
1
0
Edge Detection Logic
and
Clock Synchronizer
FIFO
R/W
Logic
Prescaler
Counter
(1, 4, 16)
ICx Pin
ICM<2:0> (ICxCON<2:0>)
3
Mode Select
ICOV, ICBNE (ICxCON<4:3>)
ICxBUF
ICxI<1:0>
Interrupt
Logic
ICxCON
System Bus
Set Flag ICxIF
(in IFSn Register)
Note: An ‘x’ in a signal, register or bit name denotes the number of the capture channel.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 149
dsPIC33FJ12MC201/202
13.1 Input Capture Registers
REGISTER 13-1: ICxCON: INPUT CAPTURE x CONTROL REGISTER
U-0
—
U-0
—
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
ICSIDL
bit 15
bit 8
R/W-0
bit 0
R/W-0
R/W-0
R/W-0
R-0, HC
ICOV
R-0, HC
ICBNE
R/W-0
R/W-0
ICTMR
ICI<1:0>
ICM<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13
Unimplemented: Read as ‘0’
ICSIDL: Input Capture Module Stop in Idle Control bit
1= Input capture module will halt in CPU Idle mode
0= Input capture module will continue to operate in CPU Idle mode
bit 12-8
bit 7
Unimplemented: Read as ‘0’
ICTMR: Input Capture Timer Select bits
1= TMR2 contents are captured on capture event
0= TMR3 contents are captured on capture event
bit 6-5
ICI<1:0>: Select Number of Captures per Interrupt bits
11= Interrupt on every fourth capture event
10= Interrupt on every third capture event
01= Interrupt on every second capture event
00= Interrupt on every capture event
bit 4
ICOV: Input Capture Overflow Status Flag bit (read-only)
1= Input capture overflow occurred
0= No input capture overflow occurred
bit 3
ICBNE: Input Capture Buffer Empty Status bit (read-only)
1= Input capture buffer is not empty, at least one more capture value can be read
0= Input capture buffer is empty
bit 2-0
ICM<2:0>: Input Capture Mode Select bits
111= Input capture functions as interrupt pin only when device is in Sleep or Idle mode
(Rising edge detect only, all other control bits are not applicable.)
110= Unused (module disabled)
101= Capture mode, every 16th rising edge
100= Capture mode, every 4th rising edge
011= Capture mode, every rising edge
010= Capture mode, every falling edge
001= Capture mode, every edge (rising and falling)
(ICI<1:0> bits do not control interrupt generation for this mode.)
000= Input capture module turned off
DS70265E-page 150
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
The Output Compare module can select either Timer2
or Timer3 for its time base. The module compares the
value of the timer with the value of one or two compare
registers depending on the operating mode selected.
The state of the output pin changes when the timer
value matches the compare register value. The Output
Compare module generates either a single output
pulse or a sequence of output pulses, by changing the
state of the output pin on the compare match events.
The Output Compare module can also generate
interrupts on compare match events.
14.0 OUTPUT COMPARE
Note 1: This data sheet summarizes the features
of the dsPIC33FJ12MC201/202 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 13. “Output
Compare” (DS70209) of the “dsPIC33F/
PIC24H Family Reference Manual”,
which is available on the Microchip web-
site (www.microchip.com).
The Output Compare module has multiple operating
modes:
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
• Active-Low One-Shot mode
• Active-High One-Shot mode
• Toggle mode
• Delayed One-Shot mode
• Continuous Pulse mode
• PWM mode without fault protection
• PWM mode with fault protection
FIGURE 14-1:
OUTPUT COMPARE MODULE BLOCK DIAGRAM
Set Flag bit
OCxIF
OCxRS
OCxR
Output
Logic
S
R
Q
OCx
3
Output
Enable
Logic
Output
Enable
OCM<2:0>
Mode Select
Comparator
OCFA
0
1
0
OCTSEL
1
16
16
TMR2
Rollover
TMR3
Rollover
TMR3
TMR2
© 2007-2011 Microchip Technology Inc.
DS70265E-page 151
dsPIC33FJ12MC201/202
14.1 Output Compare Modes
Configure the Output Compare modes by setting the
appropriate Output Compare Mode (OCM<2:0>) bits in
the Output Compare Control (OCxCON<2:0>) register.
Table 14-1 lists the different bit settings for the Output
Compare modes. Figure 14-2 illustrates the output
compare operation for various modes. The user
application must disable the associated timer when
writing to the output compare control registers to avoid
malfunctions.
Note:
See Section 13. “Output Compare” in
the “dsPIC33F/PIC24H Family Reference
Manual” (DS70209) for OCxR and
OCxRS register restrictions.
TABLE 14-1: OUTPUT COMPARE MODES
OCM<2:0>
Mode
Module Disabled
OCx Pin Initial State
OCx Interrupt Generation
000
001
010
011
100
101
110
Controlled by GPIO register
—
Active-Low One-Shot
Active-High One-Shot
Toggle Mode
0
1
OCx Rising edge
OCx Falling edge
Current output is maintained OCx Rising and Falling edge
Delayed One-Shot
Continuous Pulse mode
0
0
OCx Falling edge
OCx Falling edge
No interrupt
PWM mode without fault
protection
0, if OCxR is zero
1, if OCxR is non-zero
111
PWM mode with fault protection 0, if OCxR is zero
1, if OCxR is non-zero
OCFA Falling edge for OC1 to OC4
DS70265E-page 152
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
FIGURE 14-2:
OUTPUT COMPARE OPERATION
Output Compare
Mode enabled
Timer is reset on
period match
OCxRS
OCxR
TMRy
Active-Low One-Shot
(OCM = 001)
Active-High One-Shot
(OCM = 010)
Toggle Mode
(OCM = 011)
Delayed One-Shot
(OCM = 100)
Continuous Pulse Mode
(OCM = 101)
PWM Mode
(OCM = 110or 111)
© 2007-2011 Microchip Technology Inc.
DS70265E-page 153
dsPIC33FJ12MC201/202
REGISTER 14-1: OCxCON: OUTPUT COMPARE x CONTROL REGISTER
U-0
—
U-0
—
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
OCSIDL
bit 15
bit 8
R/W-0
bit 0
U-0
—
U-0
—
U-0
—
R-0 HC
OCFLT
R/W-0
R/W-0
R/W-0
OCTSEL
OCM<2:0>
bit 7
Legend:
HC = Cleared in Hardware
W = Writable bit
HS = Set in Hardware
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
R = Readable bit
-n = Value at POR
‘1’ = Bit is set
bit 15-14
bit 13
Unimplemented: Read as ‘0’
OCSIDL: Stop Output Compare in Idle Mode Control bit
1= Output Compare x will halt in CPU Idle mode
0= Output Compare x will continue to operate in CPU Idle mode
bit 12-5
bit 4
Unimplemented: Read as ‘0’
OCFLT: PWM Fault Condition Status bit
1= PWM Fault condition has occurred (cleared in hardware only)
0= No PWM Fault condition has occurred
(This bit is only used when OCM<2:0> = 111.)
bit 3
OCTSEL: Output Compare Timer Select bit
1= Timer3 is the clock source for Compare x
0= Timer2 is the clock source for Compare x
bit 2-0
OCM<2:0>: Output Compare Mode Select bits
111= PWM mode on OCx, Fault pin enabled
110= PWM mode on OCx, Fault pin disabled
101= Initialize OCx pin low, generate continuous output pulses on OCx pin
100= Initialize OCx pin low, generate single output pulse on OCx pin
011= Compare event toggles OCx pin
010= Initialize OCx pin high, compare event forces OCx pin low
001= Initialize OCx pin low, compare event forces OCx pin high
000= Output compare channel is disabled
DS70265E-page 154
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
15.1 PWM1: 6-Channel PWM Module
15.0 MOTOR CONTROL PWM
MODULE
This module simplifies the task of generating multiple
synchronized PWM outputs. The following power and
motion control applications are supported by the PWM
module:
Note 1: This data sheet summarizes the features
of the dsPIC33FJ12MC201/202 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 14. “Motor Con-
trol PWM” (DS70187) of the “dsPIC33F/
PIC24H Family Reference Manual”,
which is available on the Microchip web-
site (www.microchip.com).
• 3-Phase AC Induction Motor
• Switched Reluctance (SR) Motor
• Brushless DC (BLDC) Motor
• Uninterruptible Power Supply (UPS)
This module contains three duty cycle generators,
numbered 1 through 3. The module has six PWM
output pins, numbered PWM1H1/PWM1L1 through
PWM1H3/PWM1L3. The six I/O pins are grouped into
high/low numbered pairs, denoted by the suffix H or L,
respectively. For complementary loads, the low PWM
pins are always the complement of the corresponding
high I/O pin.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
15.2 PWM2: 2-Channel PWM Module
The dsPIC33FJ12MC201/202 device supports up to
two dedicated Pulse Width Modulation (PWM)
modules. The PWM1 module is a 6-channel PWM
generator, and the PWM2 module is a 2-channel PWM
generator.
This module provides an additional pair of
complimentary PWM outputs that can be used for:
• Independent PFC correction in a motor system
• Induction cooking
The PWM module has the following features:
This module contains a duty cycle generator that
provides two PWM outputs, numbered PWM2H1/
PWM2L1.
• Up to 16-bit resolution
• On-the-fly PWM frequency changes
• Edge-Aligned and Center-Aligned Output modes
• Single Pulse Generation mode
• Interrupt support for asymmetrical updates in
Center-Aligned mode
• Output override control for Electrically
Commutative Motor (ECM) operation or BLDC
• Special Event comparator for scheduling other
peripheral events
• Fault pins to optionally drive each of the PWM
output pins to a defined state
• Duty cycle updates configurable to be immediate
or synchronized to the PWM time base
© 2007-2011 Microchip Technology Inc.
DS70265E-page 155
dsPIC33FJ12MC201/202
FIGURE 15-1:
6-CHANNEL PWM MODULE BLOCK DIAGRAM (PWM1)
PWM1CON1
PWM1CON2
PWM Enable and Mode SFRs
P1DTCON1
P1DTCON2
P1FLTACON
P1OVDCON
Dead-Time Control SFRs
Fault Pin Control SFRs
PWM Manual
Control SFR
PWM Generator 3
P1DC3 Buffer
P1DC3
PWM1H3
PWM1L3
Comparator
Channel 3 Dead-Time
Generator and
Override Logic
PWM
Generator 2
PWM1H2
PWM1L2
P1TMR
Comparator
P1TPER
Channel 2 Dead-Time
Generator and
Output
Driver
Block
Override Logic
PWM
Generator 1
PWM1H1
PWM1L1
Channel 1 Dead-Time
Generator and
Override Logic
P1TPER Buffer
P1TCON
FLTA1
Special Event
Postscaler
Comparator
Special Event Trigger
SEVTDIR
PTDIR
P1SECMP
PWM Time Base
Note:
Details of PWM Generator 1 and 2 not shown for clarity.
DS70265E-page 156
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
FIGURE 15-2:
2-CHANNEL PWM MODULE BLOCK DIAGRAM (PWM2)
PWM2CON1
PWM Enable and Mode SFRs
PWM2CON2
P2DTCON1
P2DTCON2
P2FLTACON
P2OVDCON
Dead-Time Control SFRs
Fault Pin Control SFRs
PWM Manual
Control SFR
PWM Generator 1
P2DC1Buffer
P2DC1
PWM2H1
PWM2L1
Comparator
Channel 1 Dead-Time
Generator and
Override Logic
P2TMR
Comparator
P2TPER
Output
Driver
Block
P2TPER Buffer
P2TCON
FLTA2
Special Event
Postscaler
Comparator
Special Event Trigger
SEVTDIR
PTDIR
P2SECMP
PWM Time Base
© 2007-2011 Microchip Technology Inc.
DS70265E-page 157
dsPIC33FJ12MC201/202
REGISTER 15-1: PxTCON: PWM TIME BASE CONTROL REGISTER
R/W-0
PTEN
U-0
—
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
PTSIDL
bit 15
R/W-0
bit 7
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTOPS<3:0>
PTCKPS<1:0>
PTMOD<1:0>
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
PTEN: PWM Time Base Timer Enable bit
1= PWM time base is on
0= PWM time base is off
bit 14
bit 13
Unimplemented: Read as ‘0’
PTSIDL: PWM Time Base Stop in Idle Mode bit
1= PWM time base halts in CPU Idle mode
0= PWM time base runs in CPU Idle mode
bit 12-8
bit 7-4
Unimplemented: Read as ‘0’
PTOPS<3:0>: PWM Time Base Output Postscale Select bits
1111= 1:16 postscale
•
•
•
0001= 1:2 postscale
0000= 1:1 postscale
bit 3-2
bit 1-0
PTCKPS<1:0>: PWM Time Base Input Clock Prescale Select bits
11= PWM time base input clock period is 64 TCY (1:64 prescale)
10= PWM time base input clock period is 16 TCY (1:16 prescale)
01= PWM time base input clock period is 4 TCY (1:4 prescale)
00= PWM time base input clock period is TCY (1:1 prescale)
PTMOD<1:0>: PWM Time Base Mode Select bits
11= PWM time base operates in a Continuous Up/Down Count mode with interrupts for double
PWM updates
10= PWM time base operates in a Continuous Up/Down Count mode
01= PWM time base operates in Single Pulse mode
00= PWM time base operates in a Free-Running mode
DS70265E-page 158
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
REGISTER 15-2: PxTMR: PWM TIMER COUNT VALUE REGISTER
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
PTDIR
PTMR<14:8>
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTMR<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
PTDIR: PWM Time Base Count Direction Status bit (read-only)
1= PWM time base is counting down
0= PWM time base is counting up
bit 14-0
PTMR <14:0>: PWM Time Base Register Count Value bits
REGISTER 15-3: PxTPER: PWM TIME BASE PERIOD REGISTER
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
PTPER<14:8>
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTPER<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
PTPER<14:0>: PWM Time Base Period Value bits
bit 14-0
© 2007-2011 Microchip Technology Inc.
DS70265E-page 159
dsPIC33FJ12MC201/202
REGISTER 15-4: PxSECMP: SPECIAL EVENT COMPARE REGISTER
R/W-0
SEVTDIR(1)
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
SEVTCMP<14:8>(2)
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
SEVTCMP<7:0>(2)
R/W-0
R/W-0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
SEVTDIR: Special Event Trigger Time Base Direction bit(1)
1= A Special Event Trigger will occur when the PWM time base is counting down
0= A Special Event Trigger will occur when the PWM time base is counting up
bit 14-0
SEVTCMP<14:0>: Special Event Compare Value bits(2)
Note 1: SEVTDIR is compared with PTDIR (PXTMR<15>) to generate the Special Event Trigger.
2: PxSECMP<14:0> is compared with PXTMR<14:0> to generate the Special Event Trigger.
DS70265E-page 160
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
(2)
REGISTER 15-5: PWMxCON1: PWM CONTROL REGISTER 1
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
PMOD3
PMOD2
PMOD1
bit 15
bit 8
U-0
—
R/W-1
PEN3H(1)
R/W-1
PEN2H(1)
R/W-1
PEN1H(1)
U-0
—
R/W-1
PEN3L(1)
R/W-1
PEN2L(1)
R/W-1
PEN1L(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-11
bit 10-8
Unimplemented: Read as ‘0’
PMOD4:PMOD1: PWM I/O Pair Mode bits
1= PWM I/O pin pair is in the Independent PWM Output mode
0= PWM I/O pin pair is in the Complementary Output mode
bit 7
Unimplemented: Read as ‘0’
bit 6-4
PEN3H:PEN1H: PWMxH I/O Enable bits(1)
1= PWMxH pin is enabled for PWM output
0= PWMxH pin disabled, I/O pin becomes general purpose I/O
bit 3
Unimplemented: Read as ‘0’
bit 2-0
PEN3L:PEN1L: PWMxL I/O Enable bits(1)
1= PWMxL pin is enabled for PWM output
0= PWMxL pin disabled, I/O pin becomes general purpose I/O
Note 1: Reset condition of the PENxH and PENxL bits depends on the value of the PWMPIN Configuration bit in
the FPOR Configuration register.
2: PWM2 supports only one PWM I/O pin pair. PWM1 on dsPIC33FJ12MC201 devices supports only two
PWM I/O pin pairs.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 161
dsPIC33FJ12MC201/202
REGISTER 15-6: PWMxCON2: PWM CONTROL REGISTER 2
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
SEVOPS<3:0>
bit 15
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
IUE
R/W-0
R/W-0
UDIS
OSYNC
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-12
bit 11-8
Unimplemented: Read as ‘0’
SEVOPS<3:0>: PWM Special Event Trigger Output Postscale Select bits
1111= 1:16 postscale
•
•
•
0001= 1:2 postscale
0000= 1:1 postscale
bit 7-3
bit 2
Unimplemented: Read as ‘0’
IUE: Immediate Update Enable bit
1= Updates to the active PxDC registers are immediate
0= Updates to the active PxDC registers are synchronized to the PWM time base
bit 1
bit 0
OSYNC: Output Override Synchronization bit
1= Output overrides via the PxOVDCON register are synchronized to the PWM time base
0= Output overrides via the PxOVDCON register occur on next TCY boundary
UDIS: PWM Update Disable bit
1= Updates from Duty Cycle and Period Buffer registers are disabled
0= Updates from Duty Cycle and Period Buffer registers are enabled
DS70265E-page 162
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
REGISTER 15-7: PxDTCON1: DEAD-TIME CONTROL REGISTER 1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DTB<5:0>
R/W-0
R/W-0
bit 8
R/W-0
bit 0
DTBPS<1:0>
bit 15
R/W-0
DTAPS<1:0>
R/W-0
R/W-0
R/W-0
R/W-0 R/W-0
DTA<5:0>
R/W-0
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
DTBPS<1:0>: Dead-Time Unit B Prescale Select bits
11= Clock period for Dead-Time Unit B is 8 TCY
10= Clock period for Dead-Time Unit B is 4 TCY
01= Clock period for Dead-Time Unit B is 2 TCY
00= Clock period for Dead-Time Unit B is TCY
bit 13-8
bit 7-6
DTB<5:0>: Unsigned 6-bit Dead-Time Value for Dead-Time Unit B bits
DTAPS<1:0>: Dead-Time Unit A Prescale Select bits
11= Clock period for Dead-Time Unit A is 8 TCY
10= Clock period for Dead-Time Unit A is 4 TCY
01= Clock period for Dead-Time Unit A is 2 TCY
00= Clock period for Dead-Time Unit A is TCY
bit 5-0
DTA<5:0>: Unsigned 6-bit Dead-Time Value for Dead-Time Unit A bits
© 2007-2011 Microchip Technology Inc.
DS70265E-page 163
dsPIC33FJ12MC201/202
(1)
REGISTER 15-8: PxDTCON2: DEAD-TIME CONTROL REGISTER 2
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
R/W-0
R/W-0
DTS3I
R/W-0
R/W-0
DTS2I
R/W-0
R/W-0
DTS1I
DTS3A
DTS2A
DTS1A
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-6
bit 5
Unimplemented: Read as ‘0’
DTS3A: Dead-Time Select for PWM3 Signal Going Active bit
1= Dead time provided from Unit B
0= Dead time provided from Unit A
bit 4
bit 3
bit 2
bit 1
bit 0
DTS3I: Dead-Time Select for PWM3 Signal Going Inactive bit
1= Dead time provided from Unit B
0= Dead time provided from Unit A
DTS2A: Dead-Time Select for PWM2 Signal Going Active bit
1= Dead time provided from Unit B
0= Dead time provided from Unit A
DTS2I: Dead-Time Select for PWM2 Signal Going Inactive bit
1= Dead time provided from Unit B
0= Dead time provided from Unit A
DTS1A: Dead-Time Select for PWM1 Signal Going Active bit
1= Dead time provided from Unit B
0= Dead time provided from Unit A
DTS1I: Dead-Time Select for PWM1 Signal Going Inactive bit
1= Dead time provided from Unit B
0= Dead time provided from Unit A
Note 1: PWM2 supports only one PWM I/O pin pair.
DS70265E-page 164
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
(1)
REGISTER 15-9: PxFLTACON: FAULT A CONTROL REGISTER
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FAOV3H
FAOV3L
FAOV2H
FAOV2L
FAOV1H
FAOV1L
bit 15
bit 8
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
FLTAM
FAEN3
FAEN2
FAEN1
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
Unimplemented: Read as ‘0’
FAOVxH<3:1>:FAOVxL<3:1>: Fault Input A PWM Override Value bits
1= The PWM output pin is driven active on an external Fault input event
0= The PWM output pin is driven inactive on an external Fault input event
bit 7
FLTAM: Fault A Mode bit
1= The Fault A input pin functions in the Cycle-by-Cycle mode
0= The Fault A input pin latches all control pins to the programmed states in PxFLTACON<13:8>
bit 6-3
bit 2
Unimplemented: Read as ‘0’
FAEN3: Fault Input A Enable bit
1= PWMxH3/PWMxL3 pin pair is controlled by Fault Input A
0= PWMxH3/PWMxL3 pin pair is not controlled by Fault Input A
bit 1
bit 0
FAEN2: Fault Input A Enable bit
1= PWMxH2/PWMxL2 pin pair is controlled by Fault Input A
0= PWMxH2/PWMxL2 pin pair is not controlled by Fault Input A
FAEN1: Fault Input A Enable bit
1= PWMxH1/PWMxL1 pin pair is controlled by Fault Input A
0= PWMxH1/PWMxL1 pin pair is not controlled by Fault Input A
Note 1: PWM2 supports only one PWM I/O pin pair.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 165
dsPIC33FJ12MC201/202
(1)
REGISTER 15-10: PxOVDCON: OVERRIDE CONTROL REGISTER
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
POVD3H
POVD3L
POVD2H
POVD2L
POVD1H
POVD1L
bit 15
bit 8
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
POUT3H
POUT3L
POUT2H
POUT2L
POUT1H
POUT1L
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
Unimplemented: Read as ‘0’
POVDxH<3:1>:POVDxL<3:1>: PWM Output Override bits
1= Output on PWMx I/O pin is controlled by the PWM generator
0= Output on PWMx I/O pin is controlled by the value in the corresponding POUTxH:POUTxL bit
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
POUTxH<3:1>:POUTxL<3:1>: PWM Manual Output bits
1= PWMx I/O pin is driven active when the corresponding POVDxH:POVDxL bit is cleared
0= PWMx I/O pin is driven inactive when the corresponding POVDxH:POVDxL bit is cleared
Note 1: PWM2 supports only one PWM I/O pin pair.
DS70265E-page 166
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
REGISTER 15-11: PxDC1: PWM DUTY CYCLE REGISTER 1
R/W-0
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
PDC1<15:8>
R/W-0
R/W-0
R/W-0
PDC1<7:0>
R/W-0
R/W-0
R/W-0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
PDC1<15:0>: PWM Duty Cycle 1 Value bits
REGISTER 15-12: P1DC2: PWM DUTY CYCLE REGISTER 2
R/W-0
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
PDC2<15:8>
R/W-0
PDC2<7:0>
R/W-0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
PDC2<15:0>: PWM Duty Cycle 2 Value bits
REGISTER 15-13: P1DC3: PWM DUTY CYCLE REGISTER 3
R/W-0
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
PDC3<15:8>
R/W-0
R/W-0
R/W-0
PDC3<7:0>
R/W-0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
PDC3<15:0>: PWM Duty Cycle 3 Value bits
© 2007-2011 Microchip Technology Inc.
DS70265E-page 167
dsPIC33FJ12MC201/202
NOTES:
DS70265E-page 168
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
This section describes the Quadrature Encoder Inter-
face (QEI) module and associated operational modes.
The QEI module provides the interface to incremental
encoders for obtaining mechanical position data.
16.0 QUADRATURE ENCODER
INTERFACE (QEI) MODULE
Note 1: This data sheet summarizes the features
of the dsPIC33FJ12MC201/202 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 15. “Quadrature
Encoder Interface (QEI)” (DS70208) of
the “dsPIC33F/PIC24H Family Refer-
ence Manual”, which is available from the
Microchip website (www.microchip.com).
The operational features of the QEI include:
• Three input channels for two phase signals and
index pulse
• 16-bit up/down position counter
• Count direction status
• Position Measurement (x2 and x4) mode
• Programmable digital noise filters on inputs
• Alternate 16-bit Timer/Counter mode
• Quadrature Encoder Interface interrupts
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
These operating modes are determined by setting the
appropriate bits, QEIM<2:0> in (QEIxCON<10:8>).
Figure 16-1 depicts the Quadrature Encoder Interface
block diagram.
FIGURE 16-1:
QUADRATURE ENCODER INTERFACE BLOCK DIAGRAM
TQCKPS<1:0>
2
Sleep Input
TQCS
TCY
0
1
Synchronize
Det
Prescaler
1, 8, 64, 256
1
QEIM<2:0>
0
QEIIF
Event
Flag
D
Q
Q
TQGATE
CK
16-bit Up/Down Counter
(POSCNT)
2
Programmable
Digital Filter
QEAx
Reset
Equal
Quadrature
Encoder
Interface Logic
UPDN_SRC
Comparator/
Zero Detect
QEIxCON<11>
0
1
3
QEIM<2:0>
Mode Select
Max Count Register
(MAXCNT)
Programmable
Digital Filter
QEBx
Programmable
Digital Filter
INDXx
3
PCDOUT
Existing Pin Logic
0
UPDNx
Up/Down
1
© 2007-2011 Microchip Technology Inc.
DS70265E-page 169
dsPIC33FJ12MC201/202
REGISTER 16-1: QEIxCON: QEI CONTROL REGISTER
R/W-0
U-0
—
R/W-0
R-0
R/W-0
UPDN
R/W-0
R/W-0
R/W-0
bit 8
CNTERR
QEISIDL
INDEX
QEIM<2:0>
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TQCS
R/W-0
UPDN_SRC
bit 0
SWPAB
PCDOUT
TQGATE
TQCKPS<1:0>
POSRES
bit 7
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
CNTERR: Count Error Status Flag bit
1= Position count error has occurred
0= No position count error has occurred
Note:
CNTERR flag only applies when QEIM<2:0> = ‘110’ or ‘100’.
bit 14
bit 13
Unimplemented: Read as ‘0’
QEISIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12
bit 11
INDEX: Index Pin State Status bit (Read-Only)
1= Index pin is High
0= Index pin is Low
UPDN: Position Counter Direction Status bit
1= Position Counter Direction is positive (+)
0= Position Counter Direction is negative (-)
(Read-only bit when QEIM<2:0> = ‘1XX’)
(Read/Write bit when QEIM<2:0> = ‘001’)
bit 10-8
QEIM<2:0>: Quadrature Encoder Interface Mode Select bits
111= Quadrature Encoder Interface enabled (x4 mode) with position counter reset by match
(MAXCNT)
110= Quadrature Encoder Interface enabled (x4 mode) with Index Pulse reset of position counter
101= Quadrature Encoder Interface enabled (x2 mode) with position counter reset by match
(MAXCNT)
100= Quadrature Encoder Interface enabled (x2 mode) with Index Pulse reset of position counter
011= Unused (Module disabled)
010= Unused (Module disabled)
001= Starts 16-bit Timer
000= Quadrature Encoder Interface/Timer off
bit 7
bit 6
bit 5
SWPAB: Phase A and Phase B Input Swap Select bit
1= Phase A and Phase B inputs swapped
0= Phase A and Phase B inputs not swapped
PCDOUT: Position Counter Direction State Output Enable bit
1= Position Counter Direction Status Output Enable (QEI logic controls state of I/O pin)
0= Position Counter Direction Status Output Disabled (Normal I/O pin operation)
TQGATE: Timer Gated Time Accumulation Enable bit
1= Timer gated time accumulation enabled
0= Timer gated time accumulation disabled
DS70265E-page 170
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
REGISTER 16-1: QEIxCON: QEI CONTROL REGISTER (CONTINUED)
bit 4-3 TQCKPS<1:0>: Timer Input Clock Prescale Select bits
11= 1:256 prescale value
10= 1:64 prescale value
01= 1:8 prescale value
00= 1:1 prescale value
(Prescaler utilized for 16-bit Timer mode only)
POSRES: Position Counter Reset Enable bit
1= Index Pulse resets Position Counter
0= Index Pulse does not reset Position Counter
bit 2
Note:
Bit applies only when QEIM<2:0> = 100or 110.
bit 1
bit 0
TQCS: Timer Clock Source Select bit
1= External clock from pin QEA (on the rising edge)
0= Internal clock (TCY)
UPDN_SRC: Position Counter Direction Selection Control bit
1= QEB pin state defines position counter direction
0= Control/Status bit, UPDN (QEICON<11>), defines timer counter (POSCNT) direction
Note:
When configured for QEI mode, control bit is a ‘don’t care’.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 171
dsPIC33FJ12MC201/202
REGISTER 16-2: DFLTxCON: DIGITAL FILTER CONTROL REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
CEID
IMV<2:0>
bit 15
bit 8
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
QEOUT
QECK<2:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-11
bit 10-9
Unimplemented: Read as ‘0’
IMV<1:0>: Index Match Value bits – These bits allow the user application to specify the state of the
QEA and QEB input pins during an Index pulse when the POSxCNT register is to be reset.
In x4 Quadrature Count Mode:
IMV1= Required State of Phase B input signal for match on index pulse
IMV0= Required State of Phase A input signal for match on index pulse
In x2 Quadrature Count Mode:
IMV1= Selects Phase input signal for Index state match (0= Phase A, 1= Phase B)
IMV0= Required state of the selected Phase input signal for match on index pulse
bit 8
CEID: Count Error Interrupt Disable bit
1= Interrupts due to count errors are disabled
0= Interrupts due to count errors are enabled
bit 7
QEOUT: QEA/QEB/INDX Pin Digital Filter Output Enable bit
1= Digital filter outputs enabled
0= Digital filter outputs disabled (normal pin operation)
bit 6-4
QECK<2:0>: QEA/QEB/INDX Digital Filter Clock Divide Select Bits
111= 1:256 Clock Divide
110= 1:128 Clock Divide
101= 1:64 Clock Divide
100= 1:32 Clock Divide
011= 1:16 Clock Divide
010= 1:4 Clock Divide
001= 1:2 Clock Divide
000= 1:1 Clock Divide
bit 3-0
Unimplemented: Read as ‘0’
DS70265E-page 172
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
The Serial Peripheral Interface (SPI) module is a syn-
chronous serial interface useful for communicating with
other peripheral or microcontroller devices. These
peripheral devices can be serial EEPROMs, shift regis-
ters, display drivers, analog-to-digital converters, etc.
The SPI module is compatible with SPI and SIOP from
Motorola®.
17.0 SERIAL PERIPHERAL
INTERFACE (SPI)
Note 1: This data sheet summarizes the features
of the dsPIC33FJ12MC201/202 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 18. “Serial
Peripheral Interface (SPI)” (DS70206)
of the “dsPIC33F/PIC24H Family Refer-
ence Manual”, which is available on the
Microchip website (www.microchip.com).
Each SPI module consists of a 16-bit shift register,
SPIxSR (where x = 1 or 2), used for shifting data in and
out, and a buffer register, SPIxBUF. A control register,
SPIxCON, configures the module. Additionally, a status
register, SPIxSTAT, indicates status conditions.
The serial interface consists of four pins:
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
• SDIx (serial data input)
• SDOx (serial data output)
• SCKx (shift clock input or output)
• SSx (active low slave select).
In Master mode operation, SCK is a clock output. In
Slave mode, it is a clock input.
FIGURE 17-1:
SPI MODULE BLOCK DIAGRAM
SCKx
1:1 to 1:8
Secondary
Prescaler
1:1/4/16/64
Primary
Prescaler
FCY
SSx
Sync
Control
Select
Edge
Control
Clock
SPIxCON1<1:0>
SPIxCON1<4:2>
Shift Control
SDOx
SDIx
Enable
Master Clock
bit 0
SPIxSR
Transfer
Transfer
SPIxRXB SPIxTXB
SPIxBUF
Write SPIxBUF
Read SPIxBUF
16
Internal Data Bus
© 2007-2011 Microchip Technology Inc.
DS70265E-page 173
dsPIC33FJ12MC201/202
REGISTER 17-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER
R/W-0
SPIEN
U-0
—
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
SPISIDL
bit 15
bit 8
U-0
—
R/C-0
U-0
—
U-0
—
U-0
—
U-0
—
R-0
R-0
SPIROV
SPITBF
SPIRBF
bit 0
bit 7
Legend:
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
SPIEN: SPIx Enable bit
1= Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins
0= Disables module
bit 14
bit 13
Unimplemented: Read as ‘0’
SPISIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12-7
bit 6
Unimplemented: Read as ‘0’
SPIROV: Receive Overflow Flag bit
1= A new byte/word is completely received and discarded. The user software has not read the
previous data in the SPIxBUF register.
0= No overflow has occurred.
bit 5-2
bit 1
Unimplemented: Read as ‘0’
SPITBF: SPIx Transmit Buffer Full Status bit
1= Transmit not yet started, SPIxTXB is full
0= Transmit started, SPIxTXB is empty
Automatically set in hardware when CPU writes SPIxBUF location, loading SPIxTXB
Automatically cleared in hardware when SPIx module transfers data from SPIxTXB to SPIxSR
bit 0
SPIRBF: SPIx Receive Buffer Full Status bit
1= Receive complete, SPIxRXB is full
0= Receive is not complete, SPIxRXB is empty
Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB
Automatically cleared in hardware when core reads SPIxBUF location, reading SPIxRXB
DS70265E-page 174
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
REGISTER 17-2: SPIXCON1: SPIx CONTROL REGISTER 1
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
SMP
R/W-0
CKE(1)
DISSCK
DISSDO
MODE16
bit 15
bit 8
R/W-0
SSEN(2)
R/W-0
CKP
R/W-0
R/W-0
R/W-0
SPRE<2:0>(3)
R/W-0
R/W-0
R/W-0
MSTEN
PPRE<1:0>(3)
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12
Unimplemented: Read as ‘0’
DISSCK: Disable SCKx pin bit (SPI Master modes only)
1= Internal SPI clock is disabled, pin functions as I/O
0= Internal SPI clock is enabled
bit 11
bit 10
bit 9
DISSDO: Disable SDOx pin bit
1= SDOx pin is not used by module; pin functions as I/O
0= SDOx pin is controlled by the module
MODE16: Word/Byte Communication Select bit
1= Communication is word-wide (16 bits)
0= Communication is byte-wide (8 bits)
SMP: SPIx Data Input Sample Phase bit
Master mode:
1= Input data sampled at end of data output time
0= Input data sampled at middle of data output time
Slave mode:
SMP must be cleared when SPIx is used in Slave mode.
bit 8
bit 7
bit 6
bit 5
CKE: SPIx Clock Edge Select bit(1)
1= Serial output data changes on transition from active clock state to Idle clock state (see bit 6)
0= Serial output data changes on transition from Idle clock state to active clock state (see bit 6)
SSEN: Slave Select Enable bit (Slave mode)(2)
1= SSx pin used for Slave mode
0= SSx pin not used by module. Pin controlled by port function.
CKP: Clock Polarity Select bit
1= Idle state for clock is a high level; active state is a low level
0= Idle state for clock is a low level; active state is a high level
MSTEN: Master Mode Enable bit
1= Master mode
0= Slave mode
Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes
(FRMEN = 1).
2: This bit must be cleared when FRMEN = 1.
3: Do not set both Primary and Secondary prescalers to a value of 1:1.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 175
dsPIC33FJ12MC201/202
REGISTER 17-2: SPIXCON1: SPIx CONTROL REGISTER 1 (CONTINUED)
bit 4-2
SPRE<2:0>: Secondary Prescale bits (Master mode)(3)
111= Secondary prescale 1:1
110= Secondary prescale 2:1
.
.
.
000= Secondary prescale 8:1
bit 1-0
PPRE<1:0>: Primary Prescale bits (Master mode)(3)
11= Primary prescale 1:1
10= Primary prescale 4:1
01= Primary prescale 16:1
00= Primary prescale 64:1
Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes
(FRMEN = 1).
2: This bit must be cleared when FRMEN = 1.
3: Do not set both Primary and Secondary prescalers to a value of 1:1.
DS70265E-page 176
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
REGISTER 17-3: SPIxCON2: SPIx CONTROL REGISTER 2
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
FRMEN
SPIFSD
FRMPOL
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
U-0
—
FRMDLY
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
bit 13
FRMEN: Framed SPIx Support bit
1= Framed SPIx support enabled (SSx pin used as frame sync pulse input/output)
0= Framed SPIx support disabled
SPIFSD: Frame Sync Pulse Direction Control bit
1= Frame sync pulse input (slave)
0= Frame sync pulse output (master)
FRMPOL: Frame Sync Pulse Polarity bit
1= Frame sync pulse is active-high
0= Frame sync pulse is active-low
bit 12-2
bit 1
Unimplemented: Read as ‘0’
FRMDLY: Frame Sync Pulse Edge Select bit
1= Frame sync pulse coincides with first bit clock
0= Frame sync pulse precedes first bit clock
bit 0
Unimplemented: This bit must not be set to ‘1’ by the user application.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 177
dsPIC33FJ12MC201/202
NOTES:
DS70265E-page 178
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
18.1 Operating Modes
18.0 INTER-INTEGRATED CIRCUIT™
2
(I C™)
The hardware fully implements all the master and slave
functions of the I2C Standard and Fast mode
specifications, as well as 7-bit and 10-bit addressing.
The I2C module can operate either as a slave or a
master on an I2C bus.
Note 1: This data sheet summarizes the features
of the dsPIC33FJ12MC201/202 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 19. “Inter-Inte-
grated Circuit™ (I2C™)” (DS70195) of
the “dsPIC33F/PIC24H Family Refer-
ence Manual”, which is available on the
Microchip website (www.microchip.com).
The following types of I2C operation are supported:
• I2C slave operation with 7-bit address
• I2C slave operation with 10-bit address
• I2C master operation with 7-bit or 10-bit address
For details about the communication sequence in each
of these modes, refer to the Microchip web site
(www.microchip.com) for the latest “dsPIC33F/PIC24H
Family Reference Manual” sections.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
18.2 I2C Registers
I2CxCON and I2CxSTAT are control and status
registers, respectively. The I2CxCON register is
readable and writable. The lower six bits of I2CxSTAT
are read-only. The remaining bits of the I2CSTAT are
read/write:
The Inter-Integrated Circuit™ (I2C™) module provides
complete hardware support for both Slave and Multi-
Master modes of the I2C serial communication
standard, with a 16-bit interface.
The I2C module has a 2-pin interface:
• I2CxRSR is the shift register used for shifting data
• I2CxRCV is the receive buffer and the register to
which data bytes are written, or from which data
bytes are read
• The SCLx pin is clock
• The SDAx pin is data
The I2C module offers the following key features:
• I2C interface supporting both Master and Slave
modes of operation.
• I2C Slave mode supports 7-bit and 10-bit addresses
• I2C Master mode supports 7-bit and 10-bit addresses
• I2C port allows bidirectional transfers between
master and slaves
• Serial clock synchronization for I2C port can be
used as a handshake mechanism to suspend and
resume serial transfer (SCLREL control)
• I2C supports multi-master operation, detects bus
collision and arbitrates accordingly
• I2CxTRN is the transmit register to which bytes
are written during a transmit operation
• I2CxADD register holds the slave address
• ADD10 status bit indicates 10-bit Address mode
• I2CxBRG acts as the Baud Rate Generator (BRG)
reload value
In receive operations, I2CxRSR and I2CxRCV together
form a double-buffered receiver. When I2CxRSR
receives a complete byte, it is transferred to I2CxRCV,
and an interrupt pulse is generated.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 179
dsPIC33FJ12MC201/202
2
FIGURE 18-1:
I C™ BLOCK DIAGRAM (X = 1)
Internal
Data Bus
I2CxRCV
Read
Shift
Clock
SCLx
SDAx
I2CxRSR
LSb
Address Match
Write
Read
Match Detect
I2CxMSK
Write
Read
I2CxADD
Start and Stop
Bit Detect
Write
Start and Stop
Bit Generation
I2CxSTAT
I2CxCON
Read
Write
Collision
Detect
Acknowledge
Generation
Read
Clock
Stretching
Write
Read
I2CxTRN
LSb
Shift Clock
Reload
Control
Write
Read
BRG Down Counter
TCY/2
I2CxBRG
DS70265E-page 180
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
REGISTER 18-1: I2CxCON: I2Cx CONTROL REGISTER
R/W-0
I2CEN
U-0
—
R/W-0
R/W-1 HC
SCLREL
R/W-0
R/W-0
A10M
R/W-0
R/W-0
SMEN
I2CSIDL
IPMIEN
DISSLW
bit 15
bit 8
R/W-0
GCEN
R/W-0
R/W-0
R/W-0 HC
ACKEN
R/W-0 HC
RCEN
R/W-0 HC
PEN
R/W-0 HC
RSEN
R/W-0 HC
SEN
STREN
ACKDT
bit 7
bit 0
Legend:
U = Unimplemented bit, read as ‘0’
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
HS = Set in hardware
‘0’ = Bit is cleared
HC = Cleared in hardware
x = Bit is unknown
bit 15
I2CEN: I2Cx Enable bit
1= Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins
0= Disables the I2Cx module. All I2C pins are controlled by port functions.
bit 14
bit 13
Unimplemented: Read as ‘0’
I2CSIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters an Idle mode
0= Continue module operation in Idle mode
bit 12
SCLREL: SCLx Release Control bit (when operating as I2C slave)
1= Release SCLx clock
0= Hold SCLx clock low (clock stretch)
If STREN = 1:
Bit is R/W (i.e., software can write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware clear
at beginning of slave transmission. Hardware clear at end of slave reception.
If STREN = 0:
Bit is R/S (i.e., software can only write ‘1’ to release clock). Hardware clear at beginning of slave
transmission.
bit 11
bit 10
bit 9
IPMIEN: Intelligent Peripheral Management Interface (IPMI) Enable bit
1= IPMI mode is enabled; all addresses Acknowledged
0= IPMI mode disabled
A10M: 10-bit Slave Address bit
1= I2CxADD is a 10-bit slave address
0= I2CxADD is a 7-bit slave address
DISSLW: Disable Slew Rate Control bit
1= Slew rate control disabled
0= Slew rate control enabled
bit 8
SMEN: SMBus Input Levels bit
1= Enable I/O pin thresholds compliant with SMBus specification
0= Disable SMBus input thresholds
bit 7
GCEN: General Call Enable bit (when operating as I2C slave)
1= Enable interrupt when a general call address is received in the I2CxRSR
(module is enabled for reception)
0= General call address disabled
bit 6
STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave)
Used in conjunction with SCLREL bit.
1= Enable software or receive clock stretching
0= Disable software or receive clock stretching
© 2007-2011 Microchip Technology Inc.
DS70265E-page 181
dsPIC33FJ12MC201/202
REGISTER 18-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED)
bit 5
ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive)
Value that will be transmitted when the software initiates an Acknowledge sequence.
1= Send NACK during Acknowledge
0= Send ACK during Acknowledge
bit 4
ACKEN: Acknowledge Sequence Enable bit
(when operating as I2C master, applicable during master receive)
1= Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit.
Hardware clear at end of master Acknowledge sequence.
0= Acknowledge sequence not in progress
bit 3
bit 2
bit 1
RCEN: Receive Enable bit (when operating as I2C master)
1= Enables Receive mode for I2C. Hardware clear at end of eighth bit of master receive data byte.
0= Receive sequence not in progress
PEN: Stop Condition Enable bit (when operating as I2C master)
1= Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence.
0= Stop condition not in progress
RSEN: Repeated Start Condition Enable bit (when operating as I2C master)
1= Initiate Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of
master Repeated Start sequence.
0= Repeated Start condition not in progress
bit 0
SEN: Start Condition Enable bit (when operating as I2C master)
1= Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence.
0= Start condition not in progress
DS70265E-page 182
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
REGISTER 18-2: I2CxSTAT: I2Cx STATUS REGISTER
R-0 HSC
R-0 HSC
TRSTAT
U-0
—
U-0
—
U-0
—
R/C-0 HS
BCL
R-0 HSC
GCSTAT
R-0 HSC
ADD10
ACKSTAT
bit 15
bit 8
R/C-0 HS
IWCOL
R/C-0 HS
I2COV
R-0 HSC
D_A
R/C-0 HSC R/C-0 HSC
R-0 HSC
R_W
R-0 HSC
RBF
R-0 HSC
TBF
P
S
bit 7
bit 0
Legend:
U = Unimplemented bit, read as ‘0’
R = Readable bit
W = Writable bit
‘1’ = Bit is set
HS = Set in hardware
‘0’ = Bit is cleared
HSC = Hardware set/cleared
x = Bit is unknown
-n = Value at POR
bit 15
bit 14
ACKSTAT: Acknowledge Status bit
(when operating as I2C master, applicable to master transmit operation)
1= NACK received from slave
0= ACK received from slave
Hardware set or clear at end of slave Acknowledge.
TRSTAT: Transmit Status bit (when operating as I2C master, applicable to master transmit operation)
1= Master transmit is in progress (8 bits + ACK)
0= Master transmit is not in progress
Hardware set at beginning of master transmission. Hardware clear at end of slave Acknowledge.
bit 13-11
bit 10
Unimplemented: Read as ‘0’
BCL: Master Bus Collision Detect bit
1= A bus collision has been detected during a master operation
0= No collision
Hardware set at detection of bus collision.
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
GCSTAT: General Call Status bit
1= General call address was received
0= General call address was not received
Hardware set when address matches general call address. Hardware clear at Stop detection.
ADD10: 10-bit Address Status bit
1= 10-bit address was matched
0= 10-bit address was not matched
Hardware set at match of 2nd byte of matched 10-bit address. Hardware clear at Stop detection.
IWCOL: Write Collision Detect bit
1= An attempt to write the I2CxTRN register failed because the I2C module is busy
0= No collision
Hardware set at occurrence of write to I2CxTRN while busy (cleared by software).
I2COV: Receive Overflow Flag bit
1= A byte was received while the I2CxRCV register is still holding the previous byte
0= No overflow
Hardware set at attempt to transfer I2CxRSR to I2CxRCV (cleared by software).
D_A: Data/Address bit (when operating as I2C slave)
1= Indicates that the last byte received was data
0= Indicates that the last byte received was device address
Hardware clear at device address match. Hardware set by reception of slave byte.
P: Stop bit
1= Indicates that a Stop bit has been detected last
0= Stop bit was not detected last
Hardware set or clear when Start, Repeated Start or Stop detected.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 183
dsPIC33FJ12MC201/202
REGISTER 18-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED)
bit 3
bit 2
bit 1
S: Start bit
1= Indicates that a Start (or Repeated Start) bit has been detected last
0= Start bit was not detected last
Hardware set or clear when Start, Repeated Start or Stop detected.
R_W: Read/Write Information bit (when operating as I2C slave)
1= Read – indicates data transfer is output from slave
0= Write – indicates data transfer is input to slave
Hardware set or clear after reception of I2C device address byte.
RBF: Receive Buffer Full Status bit
1= Receive complete, I2CxRCV is full
0= Receive not complete, I2CxRCV is empty
Hardware set when I2CxRCV is written with received byte. Hardware clear when software
reads I2CxRCV.
bit 0
TBF: Transmit Buffer Full Status bit
1= Transmit in progress, I2CxTRN is full
0= Transmit complete, I2CxTRN is empty
Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission.
DS70265E-page 184
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
REGISTER 18-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
AMSK9
AMSK8
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
AMSK7
AMSK6
AMSK5
AMSK4
AMSK3
AMSK2
AMSK1
AMSK0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-10
bit 9-0
Unimplemented: Read as ‘0’
AMSKx: Mask for Address bit x Select bit
1= Enable masking for bit x of incoming message address; bit match not required in this position
0= Disable masking for bit x; bit match required in this position
© 2007-2011 Microchip Technology Inc.
DS70265E-page 185
dsPIC33FJ12MC201/202
NOTES:
DS70265E-page 186
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
The primary features of the UART module are:
19.0 UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART)
• Full-Duplex, 8-bit or 9-bit Data Transmission
through the UxTX and UxRX pins
• Even, Odd, or No Parity Options (for 8-bit data)
• One or two stop bits
Note 1: This data sheet summarizes the features
of the dsPIC33FJ12MC201/202 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 17. “UART”
(DS70188) of the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available on the Microchip website
(www.microchip.com).
• Hardware flow control option with UxCTS and
UxRTS pins
• Fully integrated Baud Rate Generator with 16-bit
prescaler
• Baud rates ranging from 10 Mbps to 38 bps at 40
MIPS
• 4-deep First-In First-Out (FIFO) Transmit Data
buffer
• 4-deep FIFO Receive Data buffer
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
• Parity, framing and buffer overrun error detection
• Support for 9-bit mode with Address Detect
(9th bit = 1)
• Transmit and Receive interrupts
• A separate interrupt for all UART error conditions
• Loopback mode for diagnostic support
• Support for sync and break characters
• Support for automatic baud rate detection
• IrDA® encoder and decoder logic
The Universal Asynchronous Receiver Transmitter
(UART) module is one of the serial I/O modules
available in the dsPIC33FJ12MC201/202 device
family. The UART is a full-duplex asynchronous system
that can communicate with peripheral devices, such as
personal computers, LIN, and RS-232, and RS-485
interfaces. The module also supports a hardware flow
control option with the UxCTS and UxRTS pins and
also includes an IrDA® encoder and decoder.
• 16x baud clock output for IrDA® support
A simplified block diagram of the UART module is
shown in Figure 19-1. The UART module consists of
these key hardware elements:
• Baud Rate Generator
• Asynchronous Transmitter
• Asynchronous Receiver
FIGURE 19-1:
UART SIMPLIFIED BLOCK DIAGRAM
Baud Rate Generator
IrDA®
Hardware Flow Control
UART Receiver
UxRTS/BCLK
UxCTS
UxRX
UxTX
UART Transmitter
© 2007-2011 Microchip Technology Inc.
DS70265E-page 187
dsPIC33FJ12MC201/202
REGISTER 19-1: UxMODE: UARTx MODE REGISTER
R/W-0
UARTEN(1)
U-0
—
R/W-0
USIDL
R/W-0
IREN(2)
R/W-0
U-0
—
R/W-0
R/W-0
RTSMD
UEN<1:0>
bit 15
bit 8
R/W-0 HC
WAKE
R/W-0
R/W-0 HC
ABAUD
R/W-0
R/W-0
BRGH
R/W-0
R/W-0
R/W-0
LPBACK
URXINV
PDSEL<1:0>
STSEL
bit 7
bit 0
Legend:
HC = Hardware cleared
W = Writable bit
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
‘1’ = Bit is set
bit 15
UARTEN: UARTx Enable bit(1)
1= UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0>
0= UARTx is disabled; all UARTx pins are controlled by port latches; UARTx power consumption
minimal
bit 14
bit 13
Unimplemented: Read as ‘0’
USIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12
bit 11
IREN: IrDA® Encoder and Decoder Enable bit(2)
1= IrDA encoder and decoder enabled
0= IrDA encoder and decoder disabled
RTSMD: Mode Selection for UxRTS Pin bit
1= UxRTS pin in Simplex mode
0= UxRTS pin in Flow Control mode
bit 10
Unimplemented: Read as ‘0’
UEN<1:0>: UARTx Enable bits
bit 9-8
11= UxTX, UxRX and BCLK pins are enabled and used; UxCTS pin controlled by port latches
10= UxTX, UxRX, UxCTS and UxRTS pins are enabled and used
01= UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin controlled by port latches
00= UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLK pins controlled by
port latches
bit 7
WAKE: Wake-up on Start bit Detect During Sleep Mode Enable bit
1= UARTx will continue to sample the UxRX pin; interrupt generated on falling edge; bit cleared
in hardware on following rising edge
0= No wake-up enabled
bit 6
bit 5
LPBACK: UARTx Loopback Mode Select bit
1= Enable Loopback mode
0= Loopback mode is disabled
ABAUD: Auto-Baud Enable bit
1= Enable baud rate measurement on the next character – requires reception of a Sync field (55h)
before other data; cleared in hardware upon completion
0= Baud rate measurement disabled or completed
Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for
inormation on enabling the UART module for receive or transmit operation.
2: This feature is only available for the 16x BRG mode (BRGH = 0).
DS70265E-page 188
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
REGISTER 19-1: UxMODE: UARTx MODE REGISTER (CONTINUED)
bit 4
URXINV: Receive Polarity Inversion bit
1= UxRX Idle state is ‘0’
0= UxRX Idle state is ‘1’
bit 3
BRGH: High Baud Rate Enable bit
1= BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode)
0= BRG generates 16 clocks per bit period (16x baud clock, Standard mode)
bit 2-1
PDSEL<1:0>: Parity and Data Selection bits
11= 9-bit data, no parity
10= 8-bit data, odd parity
01= 8-bit data, even parity
00= 8-bit data, no parity
bit 0
STSEL: Stop Bit Selection bit
1= Two Stop bits
0= One Stop bit
Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for
inormation on enabling the UART module for receive or transmit operation.
2: This feature is only available for the 16x BRG mode (BRGH = 0).
© 2007-2011 Microchip Technology Inc.
DS70265E-page 189
dsPIC33FJ12MC201/202
REGISTER 19-2: UxSTA: UARTx STATUS AND CONTROL REGISTER
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0 HC
UTXBRK
R/W-0
UTXEN(1)
R-0
R-1
UTXISEL1
UTXINV
UTXISEL0
UTXBF
TRMT
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R-1
R-0
R-0
R/C-0
R-0
URXISEL<1:0>
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
bit 7
bit 0
Legend:
HC = Hardware cleared
W = Writable bit
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
‘1’ = Bit is set
bit 15,13
UTXISEL<1:0>: Transmission Interrupt Mode Selection bits
11= Reserved; do not use
10= Interrupt when a character is transferred to the Transmit Shift Register, and as a result, the
transmit buffer becomes empty
01= Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit
operations are completed
00= Interrupt when a character is transferred to the Transmit Shift Register (this implies there is
at least one character open in the transmit buffer)
bit 14
UTXINV: Transmit Polarity Inversion bit
If IREN = 0:
1= UxTX Idle state is ‘0’
0= UxTX Idle state is ‘1’
If IREN = 1:
1= IrDA encoded UxTX Idle state is ‘1’
0= IrDA encoded UxTX Idle state is ‘0’
bit 12
bit 11
Unimplemented: Read as ‘0’
UTXBRK: Transmit Break bit
1= Send Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit;
cleared by hardware upon completion
0= Sync Break transmission disabled or completed
bit 10
UTXEN: Transmit Enable bit(1)
1= Transmit enabled, UxTX pin controlled by UARTx
0= Transmit disabled, any pending transmission is aborted and buffer is reset. UxTX pin controlled
by port.
bit 9
UTXBF: Transmit Buffer Full Status bit (read-only)
1= Transmit buffer is full
0= Transmit buffer is not full, at least one more character can be written
bit 8
TRMT: Transmit Shift Register Empty bit (read-only)
1= Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)
0= Transmit Shift Register is not empty, a transmission is in progress or queued
bit 7-6
URXISEL<1:0>: Receive Interrupt Mode Selection bits
11= Interrupt is set on UxRSR transfer making the receive buffer full (i.e., has 4 data characters)
10= Interrupt is set on UxRSR transfer making the receive buffer 3/4 full (i.e., has 3 data characters)
0x= Interrupt is set when any character is received and transferred from the UxRSR to the receive
buffer. Receive buffer has one or more characters.
Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for
information on enabling the UART module for transmit operation.
DS70265E-page 190
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
REGISTER 19-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)
bit 5
bit 4
bit 3
bit 2
ADDEN: Address Character Detect bit (bit 8 of received data = 1)
1= Address Detect mode enabled. If 9-bit mode is not selected, this does not take effect
0= Address Detect mode disabled
RIDLE: Receiver Idle bit (read-only)
1= Receiver is Idle
0= Receiver is active
PERR: Parity Error Status bit (read-only)
1= Parity error has been detected for the current character (character at the top of the receive FIFO)
0= Parity error has not been detected
FERR: Framing Error Status bit (read-only)
1= Framing error has been detected for the current character (character at the top of the receive
FIFO)
0= Framing error has not been detected
bit 1
bit 0
OERR: Receive Buffer Overrun Error Status bit (read-only/clear-only)
1= Receive buffer has overflowed
0= Receive buffer has not overflowed. Clearing a previously set OERR bit (1→0transition) will reset
the receiver buffer and the UxRSR to the empty state.
URXDA: Receive Buffer Data Available bit (read-only)
1= Receive buffer has data, at least one more character can be read
0= Receive buffer is empty
Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for
information on enabling the UART module for transmit operation.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 191
dsPIC33FJ12MC201/202
NOTES:
DS70265E-page 192
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
Depending on the particular device pinout, the ADC
can have up to six analog input pins, designated AN0
through AN5. In addition, there are two analog input
pins for external voltage reference connections. These
voltage reference inputs can be shared with other
analog input pins.
20.0 10-BIT/12-BIT ANALOG-TO-
DIGITAL CONVERTER (ADC)
Note 1: This data sheet summarizes the features
of the dsPIC33FJ12MC201/202 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 16. “Analog-to-
Digital Converter (ADC)” (DS70183) of
the “dsPIC33F/PIC24H Family Refer-
ence Manual”, which is available on the
Microchip website (www.microchip.com).
The actual number of analog input pins and external
voltage reference input configuration will depend on the
specific device.
Block diagrams of the ADC module are shown in
Figure 20-1 and Figure 20-2.
20.2 ADC Initialization
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
To configure the ADC module:
1. Select
port
pins
as
analog
inputs
(ADxPCFGH<15:0> or ADxPCFGL<15:0>).
2. Select voltage reference source to match
expected
range
on
analog
inputs
(ADxCON2<15:13>).
The dsPIC33FJ12MC201/202 devices have up to six
ADC module input channels.
3. Select the analog conversion clock to match the
desired data rate with the processor clock
(ADxCON3<7:0>).
The AD12B bit (ADxCON1<10>) allows each of the
ADC modules to be configured as either a 10-bit, 4-
sample-and-hold ADC (default configuration), or a
12-bit, 1 sample-and-hold ADC.
4. Determine how many sample-and-hold chan-
nels will be used (ADxCON2<9:8> and
ADxPCFGH<15:0> or ADxPCFGL<15:0>).
Note:
The ADC module must be disabled before
the AD12B bit can be modified.
5. Select the appropriate sample/conversion
sequence
(ADxCON1<7:5>
and
ADxCON3<12:8>).
20.1 Key Features
6. Select the way conversion results are presented
in the buffer (ADxCON1<9:8>).
The 10-bit ADC configuration has the following key
features:
7. Turn on the ADC module (ADxCON1<15>).
8. Configure ADC interrupt (if required):
a) Clear the ADxIF bit.
• Successive Approximation (SAR) conversion
• Conversion speeds of up to 1.1 Msps
• Up to six analog input pins
b) Select the ADC interrupt priority.
• External voltage reference input pins
• Simultaneous sampling of up to four analog input
pins
• Automatic Channel Scan mode
• Selectable conversion trigger source
• Selectable Buffer Fill modes
• Four result alignment options (signed/unsigned,
fractional/integer)
• Operation during CPU Sleep and Idle modes
• 16-word conversion result buffer
The 12-bit ADC configuration supports all the above
features, except:
• In the 12-bit configuration, conversion speeds of
up to 500 ksps are supported
• There is only one sample-and-hold amplifier in the
12-bit configuration, so simultaneous sampling of
multiple channels is not supported.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 193
dsPIC33FJ12MC201/202
FIGURE 20-1:
ADC1 BLOCK DIAGRAM FOR dsPIC33FJ12MC201 DEVICES
AN0
AN7
S/H0
Channel
Scan
+
-
CH0SB<4:0>
CH0SA<4:0>
CH0
CSCNA
AN1
VREFL
CH0NB
CH0NA
(1)
(1)
AVDD
VREF-
VREF+
AVSS
AN0
AN3
S/H1
+
-
CH123SA
CH123SB
(2)
CH1
AN6
ADC1BUF0
ADC1BUF1
ADC1BUF2
VREFL
VREFH
VREFL
CH123NB
CH123NA
AN1
SAR ADC
S/H2
ADC1BUFE
ADC1BUFF
+
-
CH123SA
CH123SB
(2)
CH2
AN7
VREFL
CH123NA
CH123NB
AN2
S/H3
+
-
CH123SA CH123SB
(2)
CH3
VREFL
CH123NA
CH123NB
Alternate
Input Selection
Note 1: VREF+, VREF- inputs can be multiplexed with other analog inputs.
2: Channels 1, 2, and 3 are not applicable for the 12-bit mode of operation.
DS70265E-page 194
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
FIGURE 20-2:
ADC1 BLOCK DIAGRAM FOR dsPIC33FJ12MC202 DEVICES
AN0
AN9
S/H0
Channel
Scan
+
-
CH0SB<4:0>
CH0SA<4:0>
CH0
CSCNA
AN1
VREFL
(1)
VREF-
AVSS
CH0NB
CH0NA
(1)
VREF+
AVDD
AN0
AN3
S/H1
+
-
CH123SA
CH123SB
(2)
CH1
AN6
AN9
ADC1BUF0
ADC1BUF1
ADC1BUF2
VREFL
VREFL
VREFH
CH123NB
CH123NA
SAR ADC
AN1
AN4
S/H2
ADC1BUFE
ADC1BUFF
+
-
CH123SA
CH123SB
(2)
CH2
AN7
VREFL
CH123NA
CH123NB
AN2
AN5
S/H3
+
-
CH123SA CH123SB
AN8
(2)
CH3
VREFL
CH123NA
CH123NB
Alternate
Input Selection
Note 1: VREF+, VREF- inputs can be multiplexed with other analog inputs.
2: Channels 1, 2, and 3 are not applicable for the 12-bit mode of operation.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 195
dsPIC33FJ12MC201/202
FIGURE 20-3:
ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM
ADxCON3<15>
ADC Internal
RC Clock(2)
1
TAD
ADxCON3<5:0>
6
0
ADC Conversion
Clock Multiplier
TCY
(1)
X2
TOSC
1, 2, 3, 4, 5,..., 64
Note 1: Refer to Figure 8-2 for the derivation of FOSC when the PLL is enabled. If the PLL is not used, FOSC is equal
to the clock frequency. TOSC = 1/FOSC.
2: See the ADC Electrical Characteristics for the exact RC clock value.
DS70265E-page 196
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
REGISTER 20-1: AD1CON1: ADC1 CONTROL REGISTER 1
R/W-0
ADON
U-0
—
R/W-0
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
ADSIDL
AD12B
FORM<1:0>
bit 15
bit 8
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0
R/W-0
ASAM
R/W-0
HC,HS
R/C-0
HC, HS
SSRC<2:0>
SIMSAM
SAMP
DONE
bit 7
Legend:
bit 0
HC = Cleared by hardware
W = Writable bit
HS = Set by hardware
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
R = Readable bit
-n = Value at POR
‘1’ = Bit is set
bit 15
ADON: ADC Operating Mode bit
1= ADC module is operating
0= ADC is off
bit 14
bit 13
Unimplemented: Read as ‘0’
ADSIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12-11
bit 10
Unimplemented: Read as ‘0’
AD12B: 10-bit or 12-bit Operation Mode bit
1= 12-bit, 1-channel ADC operation
0= 10-bit, 4-channel ADC operation
bit 9-8
FORM<1:0>: Data Output Format bits
For 10-bit operation:
11= Signed fractional (DOUT = sddd dddd dd00 0000, where s= .NOT.d<9>)
10= Fractional (DOUT = dddd dddd dd00 0000)
01= Signed integer (DOUT = ssss sssd dddd dddd, where s= .NOT.d<9>)
00= Integer (DOUT = 0000 00dd dddd dddd)
For 12-bit operation:
11= Signed fractional (DOUT = sddd dddd dddd 0000, where s= .NOT.d<11>)
10= Fractional (DOUT = dddd dddd dddd 0000)
01= Signed Integer (DOUT = ssss sddd dddd dddd, where s= .NOT.d<11>)
00= Integer (DOUT = 0000 dddd dddd dddd)
bit 7-5
SSRC<2:0>: Sample Clock Source Select bits
111= Internal counter ends sampling and starts conversion (auto-convert)
110= Reserved
101= Motor Control PWM2 interval ends sampling and starts conversion
100= Reserved
011= Motor Control PWM1 interval ends sampling and starts conversion
010= GP timer 3 compare ends sampling and starts conversion
001= Active transition on INT0 pin ends sampling and starts conversion
000= Clearing sample bit ends sampling and starts conversion
bit 4
bit 3
Unimplemented: Read as ‘0’
SIMSAM: Simultaneous Sample Select bit (applicable only when CHPS<1:0> = 01or 1x)
When AD12B = 1, SIMSAM is: U-0, Unimplemented, Read as ‘0’
1= Samples CH0, CH1, CH2, CH3 simultaneously (when CHPS<1:0> = 1x); or
Samples CH0 and CH1 simultaneously (when CHPS<1:0> = 01)
0= Samples multiple channels individually in sequence
© 2007-2011 Microchip Technology Inc.
DS70265E-page 197
dsPIC33FJ12MC201/202
REGISTER 20-1: AD1CON1: ADC1 CONTROL REGISTER 1 (CONTINUED)
bit 2
ASAM: ADC Sample Auto-Start bit
1= Sampling begins immediately after last conversion. SAMP bit is auto-set.
0= Sampling begins when SAMP bit is set
bit 1
SAMP: ADC Sample Enable bit
1= ADC sample-and-hold amplifiers are sampling
0= ADC sample-and-hold amplifiers are holding
If ASAM = 0, software can write ‘1’ to begin sampling. Automatically set by hardware if ASAM = 1.
If SSRC = 000, software can write ‘0’ to end sampling and start conversion. If SSRC ≠ 000,
automatically cleared by hardware to end sampling and start conversion.
bit 0
DONE: ADC Conversion Status bit
1= ADC conversion cycle is completed
0= ADC conversion not started or in progress
Automatically set by hardware when ADC conversion is complete. Software can write ‘0’ to clear
DONE status (software not allowed to write ‘1’). Clearing this bit will NOT affect any operation in prog-
ress. Automatically cleared by hardware at start of a new conversion.
DS70265E-page 198
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
REGISTER 20-2: AD1CON2: ADC1 CONTROL REGISTER 2
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
VCFG<2:0>
CSCNA
CHPS<1:0>
bit 15
bit 8
R-0
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BUFM
R/W-0
ALTS
BUFS
SMPI<3:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
VCFG<2:0>: Converter Voltage Reference Configuration bits
ADREF+
AVDD
ADREF-
000
AVSS
AVSS
001 External VREF+
010 AVDD
011 External VREF+
1xx AVDD
External VREF-
External VREF-
AVSS
bit 12-11
bit 10
Unimplemented: Read as ‘0’
CSCNA: Scan Input Selections for CH0+ during Sample A bit
1= Scan inputs
0= Do not scan inputs
bit 9-8
bit 7
CHPS<1:0>: Select Channels Utilized bits
When AD12B = 1, CHPS<1:0> is: U-0, Unimplemented, Read as ‘0’
1x= Converts CH0, CH1, CH2 and CH3
01= Converts CH0 and CH1
00= Converts CH0
BUFS: Buffer Fill Status bit (valid only when BUFM = 1)
1= ADC is currently filling second half of buffer, user should access data in the first half
0= ADC is currently filling first half of buffer, user application should access data in the second half
bit 6
Unimplemented: Read as ‘0’
bit 5-2
SMPI<3:0>: Sample/Convert Sequences Per Interrupt Selection bits
1111= Interrupts at the completion of conversion for each 16th sample/convert sequence
1110= Interrupts at the completion of conversion for each 15th sample/convert sequence
•
•
•
0001= Interrupts at the completion of conversion for each 2nd sample/convert sequence
0000= Interrupts at the completion of conversion for each sample/convert sequence
bit 1
bit 0
BUFM: Buffer Fill Mode Select bit
1= Starts filling first half of buffer on first interrupt and the second half of buffer on next interrupt
0= Always starts filling buffer from the beginning
ALTS: Alternate Input Sample Mode Select bit
1= Uses channel input selects for Sample A on first sample and Sample B on next sample
0= Always uses channel input selects for Sample A
© 2007-2011 Microchip Technology Inc.
DS70265E-page 199
dsPIC33FJ12MC201/202
REGISTER 20-3: AD1CON3: ADC1 CONTROL REGISTER 3
R/W-0
ADRC
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
SAMC<4:0>(1)
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
ADCS<7:0>(2)
R/W-0
R/W-0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
ADRC: ADC Conversion Clock Source bit
1= ADC internal RC clock
0= Clock derived from system clock
bit 14-13
bit 12-8
Unimplemented: Read as ‘0’
SAMC<4:0>: Auto Sample Time bits(1)
11111= 31 TAD
•
•
•
00001= 1 TAD
00000= 0 TAD
bit 7-0
ADCS<7:0>: ADC Conversion Clock Select bits(2)
11111111= Reserved
•
•
•
•
01000000= Reserved
00111111= TCY ·(ADCS<7:0> + 1) = 64 ·TCY = TAD
•
•
•
00000010= TCY ·(ADCS<7:0> + 1) = 3 ·TCY = TAD
00000001= TCY ·(ADCS<7:0> + 1) = 2 ·TCY = TAD
00000000= TCY ·(ADCS<7:0> + 1) = 1 ·TCY = TAD
Note 1: These bits are used only if the SSRC<2:0> bits (AD1CON1<7:5>) = 111.
2: These bits are not used if the ADRC bit (AD1CON3<15>) = 1.
DS70265E-page 200
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
REGISTER 20-4: AD1CHS123: ADC1 INPUT CHANNEL 1, 2, 3 SELECT REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
CH123NB<1:0>
CH123SB
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
CH123NA<1:0>
CH123SA
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-11
bit 10-9
Unimplemented: Read as ‘0’
CH123NB<1:0>: Channel 1, 2, 3 Negative Input Select for Sample B bits
If AD12B = 1:
11= Reserved
10= Reserved
01= Reserved
00= Reserved
If AD12B = 0:
11= Reserved
10= Reserved
01= CH1, CH2, CH3 negative input is VREF-
00= CH1, CH2, CH3 negative input is VREF-
bit 8
CH123SB: Channel 1, 2, 3 Positive Input Select for Sample B bit
dsPIC33FJ12MC201 devices only:
If AD12B = 1:
1= Reserved
0= Reserved
If AD12B = 0:
1= CH1 positive input is AN3, CH2 and CH3 positive inputs are not connected
0= CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2
dsPIC33FJ12MC202 devices only:
If AD12B = 1:
1= Reserved
0= Reserved
If AD12B = 0:
1= CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5
0= CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2
bit 7-3
Unimplemented: Read as ‘0’
© 2007-2011 Microchip Technology Inc.
DS70265E-page 201
dsPIC33FJ12MC201/202
REGISTER 20-4: AD1CHS123: ADC1 INPUT CHANNEL 1, 2, 3 SELECT REGISTER (CONTINUED)
bit 2-1
CH123NA<1:0>: Channel 1, 2, 3 Negative Input Select for Sample A bits
If AD12B = 1:
11= Reserved
10= Reserved
01= Reserved
00= Reserved
If AD12B = 0:
11= Reserved
10= Reserved
01= CH1, CH2, CH3 negative input is VREF-
00= CH1, CH2, CH3 negative input is VREF-
bit 0
CH123SA: Channel 1, 2, 3 Positive Input Select for Sample A bit
dsPIC33FJ12MC201 devices only:
If AD12B = 1:
1= Reserved
0= Reserved
If AD12B = 0:
1= CH1 positive input is AN3, CH2 and CH3 positive inputs are not connected
0= CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2
dsPIC33FJ12MC202 devices only:
If AD12B = 1:
1= Reserved
0= Reserved
If AD12B = 0:
1= CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5
0= CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2
DS70265E-page 202
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
REGISTER 20-5: AD1CHS0: ADC1 INPUT CHANNEL 0 SELECT REGISTER
R/W-0
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
CH0NB
CH0SB<4:0>
bit 15
R/W-0
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
CH0NA
CH0SA<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
CH0NB: Channel 0 Negative Input Select for Sample B bit
1= Channel 0 negative input is AN1
0= Channel 0 negative input is VREF-
bit 14-13
bit 12-8
Unimplemented: Read as ‘0’
CH0SB<4:0>: Channel 0 Positive Input Select for Sample B bits
dsPIC33FJ12MC201 devices only:
00011= Channel 0 positive input is AN3
00010= Channel 0 positive input is AN2
00001= Channel 0 positive input is AN1
00000= Channel 0 positive input is AN0
dsPIC33FJ12MC202 devices only:
00101= Channel 0 positive input is AN5
00100= Channel 0 positive input is AN4
00011= Channel 0 positive input is AN3
00010= Channel 0 positive input is AN2
00001= Channel 0 positive input is AN1
00000= Channel 0 positive input is AN0
bit 7
CH0NA: Channel 0 Negative Input Select for Sample A bit
1= Channel 0 negative input is AN1
0= Channel 0 negative input is VREF-
bit 6-5
bit 4-0
Unimplemented: Read as ‘0’
CH0SA<4:0>: Channel 0 Positive Input Select for Sample A bits
dsPIC33FJ12MC201 devices only:
00011= Channel 0 positive input is AN3
00010= Channel 0 positive input is AN2
00001= Channel 0 positive input is AN1
00000= Channel 0 positive input is AN0
dsPIC33FJ12MC202 devices only:
00101= Channel 0 positive input is AN5
00100= Channel 0 positive input is AN4
00011= Channel 0 positive input is AN3
00010= Channel 0 positive input is AN2
00001= Channel 0 positive input is AN1
00000= Channel 0 positive input is AN0
© 2007-2011 Microchip Technology Inc.
DS70265E-page 203
dsPIC33FJ12MC201/202
,2
(1,2)
REGISTER 20-6: AD1CSSL: ADC1 INPUT SCAN SELECT REGISTER LOW
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
R/W-0
CSS5
R/W-0
CSS4
R/W-0
CSS3
R/W-0
CSS2
R/W-0
CSS1
R/W-0
CSS0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-6
bit 5-0
Unimplemented: Read as ‘0’
CSS<5:0>: ADC Input Scan Selection bits
1= Select ANx for input scan
0= Skip ANx for input scan
Note 1: On devices without 6 analog inputs, all AD1CSSL bits can be selected by user application. However,
inputs selected for scan without a corresponding input on device converts VREFL.
2: CSSx = ANx, where x = 0 through 5.
(1,2,3)
REGISTER 20-7: AD1PCFGL: ADC1 PORT CONFIGURATION REGISTER LOW
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PCFG5
PCFG4
PCFG3
PCFG2
PCFG1
PCFG0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-6
bit 5-0
Unimplemented: Read as ‘0’
PCFG<5:0>: ADC Port Configuration Control bits
1= Port pin in Digital mode, port read input enabled, ADC input multiplexer connected to AVSS
0= Port pin in Analog mode, port read input disabled, ADC samples pin voltage
Note 1: On devices without 6 analog inputs, all PCFG bits are R/W by user. However, PCFG bits are ignored on
ports without a corresponding input on device.
2: PCFGx = ANx, where x = 0 through 5.
3: PCFGx bits have no effect if the ADC module is disabled by setting ADxMD bit in the PMDx register. When
the bit is set, all port pins that have been multiplexed with ANx will be in Digital mode.
DS70265E-page 204
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
21.1 Configuration Bits
21.0 SPECIAL FEATURES
dsPIC33FJ12MC201/202 devices provide nonvolatile
memory implementation for device configuration bits.
Refer to Section 25. “Device Configuration”
(DS70194) of the “dsPIC33F/PIC24H Family
Reference Manual”, for more information on this
implementation.
Note:
This data sheet summarizes the features
of the dsPIC33FJ12MC201/202 devices.
It is not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to the
“dsPIC33F/PIC24H Family Reference
Manual”. Please see the Microchip web
site (www.microchip.com) for the latest
dsPIC33F/PIC24H Family Reference
Manual sections.
The Configuration bits can be programmed (read as
‘0’), or left unprogrammed (read as ‘1’), to select vari-
ous device configurations. These bits are mapped
starting at program memory location 0xF80000.
The individual Configuration bit descriptions for the
Configuration registers are shown in Table 21-2.
dsPIC33FJ12MC201/202 devices include several
features intended to maximize application flexibility and
reliability, and minimize cost through elimination of
external components. These are:
Note that address 0xF80000 is beyond the user program
memory space. It belongs to the configuration memory
space (0x800000-0xFFFFFF), which can only be
accessed using table reads and table writes.
• Flexible configuration
• Watchdog Timer (WDT)
The Device Configuration register map is shown in
Table 21-1.
• Code Protection and CodeGuard™ Security
• JTAG Boundary Scan Interface
• In-Circuit Serial Programming™ (ICSP™)
• In-Circuit emulation
TABLE 21-1: DEVICE CONFIGURATION REGISTER MAP
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0xF80000 FBS
—
—
—
—
—
—
—
—
—
—
—
BSS<2:0>
—
BWRP
—
0xF80002 Reserved
0xF80004 FGS
—
—
—
—
—
GSS<1:0>
FNOSC<2:0>
GWRP
0xF80006 FOSCSEL
0xF80008 FOSC
0xF8000A FWDT
0xF8000C FPOR
0xF8000E FICD
0xF80010 FUID0
0xF80012 FUID1
0xF80014 FUID2
0xF80016 FUID3
IESO
—
—
FCKSM<1:0>
FWDTEN WINDIS
PWMPIN HPOL
Reserved(1)
IOL1WAY
—
—
—
OSCIOFNC POSCMD<1:0>
WDTPOST<3:0>
WDTPRE
ALTI2C
—
LPOL
JTAGEN
—
—
FPWRT<2:0>
—
ICS<1:0>
User Unit ID Byte 0
User Unit ID Byte 1
User Unit ID Byte 2
User Unit ID Byte 3
Legend: — = unimplemented bit, read as ‘0’.
Note 1: These bits are reserved for use by development tools and must be programmed as ‘1’.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 205
dsPIC33FJ12MC201/202
TABLE 21-2: dsPIC33F CONFIGURATION BITS DESCRIPTION
RTSP
Bit Field
Register
Description
Effect
BWRP
FBS
Immediate Boot Segment Program Flash Write Protection
1= Boot segment can be written
0= Boot segment is write-protected
BSS<2:0>
FBS
Immediate Boot Segment Program Flash Code Protection Size
X11= No Boot program Flash segment
Boot space is 256 Instruction Words (except interrupt vectors)
110= Standard security; boot program Flash segment ends at 0x0003FE
010= High security; boot program Flash segment ends at 0x0003FE
Boot space is 768 Instruction Words (except interrupt vectors)
101= Standard security; boot program Flash segment, ends at 0x0007FE
001= High security; boot program Flash segment ends at 0x0007FE
Boot space is 1792 Instruction Words (except interrupt vectors)
100= Standard security; boot program Flash segment ends at 0x000FFE
000= High security; boot program Flash segment ends at 0x000FFE
GSS<1:0>
FGS
FGS
Immediate General Segment Code-Protect bit
11= User program memory is not code-protected
10= Standard security
0x= High security
GWRP
IESO
Immediate General Segment Write-Protect bit
1= User program memory is not write-protected
0= User program memory is write-protected
FOSCSEL Immediate Two-speed Oscillator Start-up Enable bit
1= Start-up device with FRC, then automatically switch to the
user-selected oscillator source when ready
0= Start-up device with user-selected oscillator source
FNOSC<2:0> FOSCSEL If clock Initial Oscillator Source Selection bits
switch is 111= Internal Fast RC (FRC) oscillator with postscaler
enabled, 110= Internal Fast RC (FRC) oscillator with divide-by-16
RTSP 101= LPRC oscillator
effect is 100= Secondary (LP) oscillator
on any 011= Primary (XT, HS, EC) oscillator with PLL
device
Reset;
010= Primary (XT, HS, EC) oscillator
001= Internal Fast RC (FRC) oscillator with PLL
otherwise, 000= FRC oscillator
Immediate
FCKSM<1:0>
FOSC
Immediate Clock Switching Mode bits
1x= Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01= Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00= Clock switching is enabled, Fail-Safe Clock Monitor is enabled
IOL1WAY
OSCIOFNC
FOSC
FOSC
FOSC
Immediate Peripheral pin select configuration
1= Allow only one reconfiguration
0= Allow multiple reconfigurations
Immediate OSC2 Pin Function bit (except in XT and HS modes)
1= OSC2 is clock output
0= OSC2 is general purpose digital I/O pin
POSCMD<1:0>
Immediate Primary Oscillator Mode Select bits
11= Primary oscillator disabled
10= HS Crystal Oscillator mode
01= XT Crystal Oscillator mode
00= EC (External Clock) mode
DS70265E-page 206
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
TABLE 21-2: dsPIC33F CONFIGURATION BITS DESCRIPTION (CONTINUED)
RTSP
Effect
Bit Field
Register
Description
FWDTEN
FWDT
Immediate Watchdog Timer Enable bit
1= Watchdog Timer always enabled (LPRC oscillator cannot be disabled.
Clearing the SWDTEN bit in the RCON register will have no effect.)
0= Watchdog Timer enabled/disabled by user software (LPRC can be dis-
abled by clearing the SWDTEN bit in the RCON register)
WINDIS
WDTPRE
FWDT
FWDT
FWDT
Immediate Watchdog Timer Window Enable bit
1= Watchdog Timer in Non-Window mode
0= Watchdog Timer in Window mode
Immediate Watchdog Timer Prescaler bit
1= 1:128
0= 1:32
WDTPOST<3:0>
Immediate Watchdog Timer Postscaler bits
1111= 1:32,768
1110= 1:16,384
•
•
•
0001= 1:2
0000= 1:1
PWMPIN
FPOR
Immediate Motor Control PWM Module Pin Mode bit
1= PWM module pins controlled by PORT register at device Reset
(tri-stated)
0= PWM module pins controlled by PWM module at device Reset
(configured as output pins)
HPOL
LPOL
FPOR
FPOR
FPOR
Immediate Motor Control PWM High Side Polarity bit
1= PWM module high side output pins have active-high output polarity
0= PWM module high side output pins have active-low output polarity
Immediate Motor Control PWM Low Side Polarity bit
1= PWM module low side output pins have active-high output polarity
0= PWM module low side output pins have active-low output polarity
FPWRT<2:0>
Immediate Power-on Reset Timer Value Select bits
111= PWRT = 128 ms
110= PWRT = 64 ms
101= PWRT = 32 ms
100= PWRT = 16 ms
011= PWRT = 8 ms
010= PWRT = 4 ms
001= PWRT = 2 ms
000= PWRT = Disabled
ALTI2C
FPOR
FICD
Immediate Alternate I2C pins
1 = I2C mapped to SDA1/SCL1 pins
0 = I2C mapped to ASDA1/ASCL1 pins
JTAGEN
Immediate JTAG Enable bit
1= JTAG enabled
0= JTAG disabled
ICS<1:0>
FICD
Immediate ICD Communication Channel Select bits
11= Communicate on PGEC1 and PGED1
10= Communicate on PGEC2 and PGED2
01= Communicate on PGEC3 and PGED3
00= Reserved, do not use
© 2007-2011 Microchip Technology Inc.
DS70265E-page 207
dsPIC33FJ12MC201/202
21.2 On-Chip Voltage Regulator
21.3 Brown-out Reset (BOR)
All of the dsPIC33FJ12MC201/202 devices power their
core digital logic at a nominal 2.5V. This can create a
conflict for designs that are required to operate at a
higher typical voltage, such as 3.3V. To simplify system
design, all devices in the dsPIC33FJ12MC201/202
family incorporate an on-chip regulator that allows the
device to run its core logic from VDD.
The Brown-out Reset (BOR) module is based on an
internal voltage reference circuit that monitors the reg-
ulated supply voltage VCAP. The main purpose of the
BOR module is to generate a device Reset when a
brown-out condition occurs. Brown-out conditions are
generally caused by glitches on the AC mains (for
example, missing portions of the AC cycle waveform
due to bad power transmission lines, or voltage sags
due to excessive current draw when a large inductive
load is turned on).
The regulator provides power to the core from the other
VDD pins. When the regulator is enabled, a low-ESR
(less than 5 ohms) capacitor (such as tantalum or
ceramic) must be connected to the VCAP pin
(Figure 21-1). This helps to maintain the stability of the
regulator. The recommended value for the filter capac-
itor is provided in Table 24-13 located in Section 24.1
“DC Characteristics”.
A BOR generates a Reset pulse, which resets the
device. The BOR selects the clock source, based on
the device Configuration bit values (FNOSC<2:0> and
POSCMD<1:0>).
If an oscillator mode is selected, the BOR activates the
Oscillator Start-up Timer (OST). The system clock is
held until OST expires. If the PLL is used, the clock is
held until the LOCK bit (OSCCON<5>) is ‘1’.
Note:
It is important for low-ESR capacitors to
be placed as close as possible to the VCAP
pin.
Concurrently, the PWRT time-out (TPWRT) is applied
before the internal Reset is released. If TPWRT = 0and
a crystal oscillator is being used, then a nominal delay
of TFSCM = 100 is applied. The total delay in this case
is TFSCM.
On a POR, it takes approximately 20 μs for the on-chip
voltage regulator to generate an output voltage. During
this time, designated as TSTARTUP, code execution is
disabled. TSTARTUP is applied every time the device
resumes operation after any power-down.
The BOR Status bit (RCON<1>) is set to indicate that a
BOR has occurred. The BOR circuit continues to oper-
ate while in Sleep or Idle modes and resets the device
should VDD fall below the BOR threshold voltage.
FIGURE 21-1:
CONNECTIONS FOR THE
ON-CHIP VOLTAGE
REGULATOR
(1,2,3)
3.3V
dsPIC33F
VDD
VCAP
VSS
CEFC
10 µF
Tantalum
Note 1: These are typical operating voltages. Refer
to Section TABLE 24-13: “Internal Volt-
age Regulator Specifications” located in
Section 24.1 “DC Characteristics” for the
full operating ranges of VDD and VCAP.
2: It is important for low-ESR capacitors to be
placed as close as possible to the VCAP
pin.
3: Typical VCAP pin voltage = 2.5V when
VDD ≥ VDDMIN.
DS70265E-page 208
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
21.4.2
SLEEP AND IDLE MODES
21.4 Watchdog Timer (WDT)
If the WDT is enabled, it will continue to run during Sleep
or Idle modes. When the WDT time-out occurs, the
device will wake the device and code execution will
continue from where the PWRSAV instruction was
executed. The corresponding SLEEP or IDLE bits
(RCON<3> and RCON<2>, respectively) will need to be
cleared in software after the device wakes up.
For dsPIC33FJ12MC201/202 devices, the WDT is
driven by the LPRC oscillator. When the WDT is
enabled, the clock source is also enabled.
21.4.1
PRESCALER/POSTSCALER
The nominal WDT clock source from LPRC is 32 kHz.
This feeds a prescaler than can be configured for either
5-bit (divide-by-32) or 7-bit (divide-by-128) operation.
The prescaler is set by the WDTPRE Configuration bit.
With a 32 kHz input, the prescaler yields a nominal
WDT time-out period (TWDT) of 1 ms in 5-bit mode, or
4 ms in 7-bit mode.
21.4.3
ENABLING WDT
The WDT is enabled or disabled by the FWDTEN
Configuration bit in the FWDT Configuration register.
When the FWDTEN Configuration bit is set, the WDT is
always enabled.
A variable postscaler divides down the WDT prescaler
output and allows for a wide range of time-out periods.
The postscaler is controlled by the WDTPOST<3:0>
Configuration bits (FWDT<3:0>), which allow the selec-
tion of 16 settings, from 1:1 to 1:32,768. Using the pres-
caler and postscaler, time-out periods ranging from
1 ms to 131 seconds can be achieved.
The WDT can be optionally controlled in software when
the FWDTEN Configuration bit has been programmed
to ‘0’. The WDT is enabled in software by setting the
SWDTEN control bit (RCON<5>). The SWDTEN con-
trol bit is cleared on any device Reset. The software
WDT option allows the user application to enable the
WDT for critical code segments and disable the WDT
during non-critical segments for maximum power
savings.
The WDT, prescaler, and postscaler are reset:
• On any device Reset
• On the completion of a clock switch, whether
invoked by software (i.e., setting the OSWEN bit
after changing the NOSC bits) or by hardware
(i.e., Fail-Safe Clock Monitor)
Note:
If the WINDIS bit (FWDT<6>) is cleared,
the CLRWDTinstruction should be executed
by the application software only during the
last 1/4 of the WDT period. This CLRWDT
window can be determined by using a timer.
If a CLRWDTinstruction is executed before
this window, a WDT Reset occurs.
• When a PWRSAVinstruction is executed
(i.e., Sleep or Idle mode is entered)
• When the device exits Sleep or Idle mode to
resume normal operation
The WDT flag bit, WDTO (RCON<4>), is not automatically
cleared following a WDT time-out. To detect subsequent
WDT events, the flag must be cleared in software.
• By a CLRWDTinstruction during normal execution
Note:
The CLRWDT and PWRSAV instructions
clear the prescaler and postscaler counts
when executed.
FIGURE 21-2:
WDT BLOCK DIAGRAM
All Device Resets
Transition to New Clock Source
Exit Sleep or Idle Mode
PWRSAVInstruction
CLRWDTInstruction
Watchdog Timer
Sleep/Idle
WDTPRE
WDTPOST<3:0>
SWDTEN
FWDTEN
WDT
Wake-up
1
RS
RS
Prescaler
(divide by N1)
Postscaler
WDT
Reset
LPRC Clock
(divide by N2)
0
WDT Window Select
WINDIS
CLRWDTInstruction
© 2007-2011 Microchip Technology Inc.
DS70265E-page 209
dsPIC33FJ12MC201/202
21.5 JTAG Interface
21.8 Code Protection and
CodeGuard™ Security
dsPIC33FJ12MC201/202 devices implement a JTAG
interface, which supports boundary scan device test-
ing, as well as in-circuit programming. Detailed infor-
mation on this interface will be provided in future
revisions of the document.
The dsPIC33FJ12MC201/202 devices offer the
intermediate implementation of CodeGuard Security.
CodeGuard Security enables multiple parties to
securely share resources (memory, interrupts and
peripherals) on a single chip. This feature helps protect
individual Intellectual Property in collaborative system
designs.
21.6
In-Circuit Serial Programming
The dsPIC33FJ12MC201/202 devices can be serially
programmed while in the end application circuit. This is
done with two lines for clock and data and three other
lines for power, ground and the programming
sequence. Serial programming allows customers to
manufacture boards with unprogrammed devices and
then program the digital signal controller just before
shipping the product. Serial programming also allows
the most recent firmware or a custom firmware to be
programmed. Refer to the dsPIC33F/PIC24H Flash
Programming Specification (DS70152) for details
about In-Circuit Serial Programming (ICSP).
When coupled with software encryption libraries,
CodeGuard Security can be used to securely update
Flash even when multiple IPs reside on the single chip.
The code protection features vary depending on the
actual dsPIC33F implemented. The following sections
provide an overview of these features.
Secure segment and RAM protection is not
implemented in dsPIC33FJ12MC201/202 devices.
TABLE 21-3: CODE FLASH SECURITY
SEGMENT SIZES FOR
12 KBYTE DEVICES
Any of the three pairs of programming clock/data pins
can be used:
CONFIG BITS
000000h
VS = 256 IW
• PGEC1 and PGED1
• PGEC2 and PGED2
• PGEC3 and PGED3
0001FEh
000200h
0003FEh
000400h
0007FEh
000800h
000FFEh
001000h
BSS<2:0> = x11
0K
GS = 3840 IW
21.7 In-Circuit Debugger
When MPLAB® ICD 2 is selected as a debugger, the in-
circuit debugging functionality is enabled. This function
allows simple debugging functions when used with
MPLAB IDE. Debugging functionality is controlled
through the PGECx (Emulation/Debug Clock) and
PGEDx (Emulation/Debug Data) pin functions.
001FFEh
000000h
VS = 256 IW
BS = 256 IW
0001FEh
000200h
0003FEh
000400h
0007FEh
000800h
000FFEh
001000h
BSS<2:0> = x10
256
Any of the three pairs of debugging clock/data pins can
be used:
GS = 3584 IW
001FFEh
000000h
0001FEh
000200h
0003FEh
000400h
0007FEh
000800h
000FFEh
001000h
VS = 256 IW
BS = 768 IW
• PGEC1 and PGED1
• PGEC2 and PGED2
• PGEC3 and PGED3
BSS<2:0> = x01
768
To use the in-circuit debugger function of the device,
the design must implement ICSP connections to
MCLR, VDD, VSS, and the PGECx/PGEDx pin pair. In
addition, when the feature is enabled, some of the
resources are not available for general use. These
resources include the first 80 bytes of data RAM and
two I/O pins.
GS = 3072 IW
001FFEh
000000h
0001FEh
000200h
0003FEh
000400h
0007FEh
000800h
000FFEh
001000h
VS = 256 IW
BS = 1792 IW
BSS<2:0> = x00
1792
GS = 2048 IW
001FFEh
Note:
Refer to Section 23. “CodeGuard™
Security” (DS70199) of the “dsPIC33F/
PIC24H Family Reference Manual” for fur-
ther information on usage, configuration
and operation of CodeGuard Security.
DS70265E-page 210
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
Most bit-oriented instructions (including simple rotate/
shift instructions) have two operands:
22.0 INSTRUCTION SET SUMMARY
Note:
This data sheet summarizes the features
of the dsPIC33FJ12MC201/202 devices.
It is not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to the
“dsPIC33F/PIC24H Family Reference
Manual”. Please see the Microchip web
site (www.microchip.com) for the latest
dsPIC33F/PIC24H Family Reference
Manual sections.
• The W register (with or without an address
modifier) or file register (specified by the value of
‘Ws’ or ‘f’)
• The bit in the W register or file register (specified
by a literal value or indirectly by the contents of
register ‘Wb’)
The literal instructions that involve data movement can
use some of the following operands:
• A literal value to be loaded into a W register or file
register (specified by ‘k’)
The dsPIC33F instruction set is identical to that of the
dsPIC30F.
• The W register or file register where the literal
value is to be loaded (specified by ‘Wb’ or ‘f’)
Most instructions are a single program memory word
(24 bits). Only three instructions require two program
memory locations.
However, literal instructions that involve arithmetic or
logical operations use some of the following operands:
• The first source operand, which is a register ‘Wb’
without any address modifier
Each single-word instruction is a 24-bit word, divided
into an 8-bit opcode, which specifies the instruction
type and one or more operands, which further specify
the operation of the instruction.
• The second source operand, which is a literal
value
• The destination of the result (only if not the same
as the first source operand), which is typically a
register ‘Wd’ with or without an address modifier
The instruction set is highly orthogonal and is grouped
into five basic categories:
• Word or byte-oriented operations
• Bit-oriented operations
• Literal operations
The MACclass of DSP instructions can use some of the
following operands:
• The accumulator (A or B) to be used (required
operand)
• DSP operations
• Control operations
• The W registers to be used as the two operands
• The X and Y address space prefetch operations
• The X and Y address space prefetch destinations
• The accumulator write back destination
Table 22-1 shows the general symbols used in
describing the instructions.
The dsPIC33F instruction set summary in Table 22-2
lists all the instructions, along with the status flags
affected by each instruction.
The other DSP instructions do not involve any
multiplication and can include:
Most word or byte-oriented W register instructions
(including barrel shift instructions) have three
operands:
• The accumulator to be used (required)
• The source or destination operand (designated as
Wso or Wdo, respectively) with or without an
address modifier
• The first source operand, which is typically a
register ‘Wb’ without any address modifier
• The amount of shift specified by a W register ‘Wn’
or a literal value
• The second source operand, which is typically a
register ‘Ws’ with or without an address modifier
The control instructions can use some of the following
operands:
• The destination of the result, which is typically a
register ‘Wd’ with or without an address modifier
• A program memory address
However, word or byte-oriented file register instructions
have two operands:
• The mode of the table read and table write
instructions
• The file register specified by the value ‘f’
• The destination, which could be either the file
register ‘f’ or the W0 register, which is denoted as
‘WREG’
© 2007-2011 Microchip Technology Inc.
DS70265E-page 211
dsPIC33FJ12MC201/202
Most instructions are a single word. Certain double-
word instructions are designed to provide all the
required information in these 48 bits. In the second
word, the 8 MSbs are ‘0’s. If this second word is exe-
cuted as an instruction (by itself), it will execute as a
NOP.
tional/computed branch), indirect CALL/GOTO, all table
reads and writes and RETURN/RETFIE instructions,
which are single-word instructions but take two or three
cycles. Certain instructions that involve skipping over the
subsequent instruction require either two or three cycles
if the skip is performed, depending on whether the
instruction being skipped is a single-word or two-word
instruction. Moreover, double-word moves require two
cycles.
The double-word instructions execute in two instruction
cycles.
Most single-word instructions are executed in a single
instruction cycle, unless a conditional test is true, or the
program counter is changed as a result of the instruc-
tion. In these cases, the execution takes two instruction
cycles with the additional instruction cycle(s) executed
as a NOP. Notable exceptions are the BRA (uncondi-
Note:
For more details on the instruction set,
refer to the “16-bit MCU and DSC
Programmer’s
Reference
Manual”
(DS70157).
TABLE 22-1: SYMBOLS USED IN OPCODE DESCRIPTIONS
Field
Description
#text
(text)
[text]
{ }
Means literal defined by “text”
Means “content of text”
Means “the location addressed by text”
Optional field or operation
Register bit field
<n:m>
.b
Byte mode selection
.d
Double-Word mode selection
Shadow register select
.S
.w
Word mode selection (default)
One of two accumulators {A, B}
Acc
AWB
bit4
Accumulator write back destination address register ∈ {W13, [W13]+ = 2}
4-bit bit selection field (used in word addressed instructions) ∈ {0...15}
MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero
Absolute address, label or expression (resolved by the linker)
File register address ∈ {0x0000...0x1FFF}
C, DC, N, OV, Z
Expr
f
lit1
1-bit unsigned literal ∈ {0,1}
lit4
4-bit unsigned literal ∈ {0...15}
lit5
5-bit unsigned literal ∈ {0...31}
lit8
8-bit unsigned literal ∈ {0...255}
lit10
10-bit unsigned literal ∈ {0...255} for Byte mode, {0:1023} for Word mode
14-bit unsigned literal ∈ {0...16384}
lit14
lit16
16-bit unsigned literal ∈ {0...65535}
lit23
23-bit unsigned literal ∈ {0...8388608}; LSb must be ‘0’
Field does not require an entry, can be blank
DSP Status bits: ACCA Overflow, ACCB Overflow, ACCA Saturate, ACCB Saturate
Program Counter
None
OA, OB, SA, SB
PC
Slit10
Slit16
Slit6
Wb
10-bit signed literal ∈ {-512...511}
16-bit signed literal ∈ {-32768...32767}
6-bit signed literal ∈ {-16...16}
Base W register ∈ {W0..W15}
Wd
Destination W register ∈ { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }
Wdo
Destination W register ∈
{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }
Wm,Wn
Dividend, Divisor working register pair (direct addressing)
DS70265E-page 212
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
TABLE 22-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED)
Field
Description
Wm*Wm
Wm*Wn
Multiplicand and Multiplier working register pair for Square instructions ∈
{W4 * W4,W5 * W5,W6 * W6,W7 * W7}
Multiplicand and Multiplier working register pair for DSP instructions ∈
{W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7}
Wn
One of 16 working registers ∈ {W0..W15}
Wnd
Wns
WREG
Ws
One of 16 destination working registers ∈ {W0..W15}
One of 16 source working registers ∈ {W0..W15}
W0 (working register used in file register instructions)
Source W register ∈ { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }
Wso
Source W register ∈
{ Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }
Wx
X data space prefetch address register for DSP instructions
∈ {[W8] + = 6, [W8] + = 4, [W8] + = 2, [W8], [W8] - = 6, [W8] - = 4, [W8] - = 2,
[W9] + = 6, [W9] + = 4, [W9] + = 2, [W9], [W9] - = 6, [W9] - = 4, [W9] - = 2,
[W9 + W12], none}
Wxd
Wy
X data space prefetch destination register for DSP instructions ∈ {W4..W7}
Y data space prefetch address register for DSP instructions
∈ {[W10] + = 6, [W10] + = 4, [W10] + = 2, [W10], [W10] - = 6, [W10] - = 4, [W10] - = 2,
[W11] + = 6, [W11] + = 4, [W11] + = 2, [W11], [W11] - = 6, [W11] - = 4, [W11] - = 2,
[W11 + W12], none}
Wyd
Y data space prefetch destination register for DSP instructions ∈ {W4..W7}
© 2007-2011 Microchip Technology Inc.
DS70265E-page 213
dsPIC33FJ12MC201/202
TABLE 22-2: INSTRUCTION SET OVERVIEW
Base
Instr
#
Assembly
Mnemonic
# of
# of
Status Flags
Affected
Assembly Syntax
Description
Words Cycles
1
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADDC
ADDC
ADDC
ADDC
ADDC
AND
AND
AND
AND
AND
ASR
ASR
ASR
ASR
ASR
BCLR
BCLR
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BSET
BSET
BSW.C
BSW.Z
BTG
BTG
Acc
Add Accumulators
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
OA,OB,SA,SB
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
OA,OB,SA,SB
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
N,Z
f
f = f + WREG
f,WREG
WREG = f + WREG
1
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
Wso,#Slit4,Acc
f
Wd = lit10 + Wd
1
Wd = Wb + Ws
1
Wd = Wb + lit5
1
16-bit Signed Add to Accumulator
f = f + WREG + (C)
1
2
3
4
ADDC
AND
1
f,WREG
WREG = f + WREG + (C)
Wd = lit10 + Wd + (C)
Wd = Wb + Ws + (C)
Wd = Wb + lit5 + (C)
1
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
f
1
1
1
f = f .AND. WREG
1
f,WREG
WREG = f .AND. WREG
Wd = lit10 .AND. Wd
1
N,Z
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
f
1
N,Z
Wd = Wb .AND. Ws
1
N,Z
Wd = Wb .AND. lit5
1
N,Z
ASR
f = Arithmetic Right Shift f
WREG = Arithmetic Right Shift f
Wd = Arithmetic Right Shift Ws
Wnd = Arithmetic Right Shift Wb by Wns
Wnd = Arithmetic Right Shift Wb by lit5
Bit Clear f
1
C,N,OV,Z
C,N,OV,Z
C,N,OV,Z
N,Z
f,WREG
1
Ws,Wd
1
Wb,Wns,Wnd
Wb,#lit5,Wnd
f,#bit4
Ws,#bit4
C,Expr
1
1
N,Z
5
6
BCLR
BRA
1
None
Bit Clear Ws
1
None
Branch if Carry
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
2
None
GE,Expr
GEU,Expr
GT,Expr
GTU,Expr
LE,Expr
LEU,Expr
LT,Expr
LTU,Expr
N,Expr
Branch if greater than or equal
Branch if unsigned greater than or equal
Branch if greater than
Branch if unsigned greater than
Branch if less than or equal
Branch if unsigned less than or equal
Branch if less than
None
None
None
None
None
None
None
Branch if unsigned less than
Branch if Negative
None
None
NC,Expr
NN,Expr
NOV,Expr
NZ,Expr
OA,Expr
OB,Expr
OV,Expr
SA,Expr
SB,Expr
Expr
Branch if Not Carry
None
Branch if Not Negative
Branch if Not Overflow
Branch if Not Zero
None
None
None
Branch if Accumulator A overflow
Branch if Accumulator B overflow
Branch if Overflow
None
None
None
Branch if Accumulator A saturated
Branch if Accumulator B saturated
Branch Unconditionally
Branch if Zero
None
None
None
Z,Expr
1 (2)
2
None
Wn
Computed Branch
None
7
8
9
BSET
BSW
f,#bit4
Ws,#bit4
Ws,Wb
Bit Set f
1
None
Bit Set Ws
1
None
Write C bit to Ws<Wb>
Write Z bit to Ws<Wb>
Bit Toggle f
1
None
Ws,Wb
1
None
BTG
f,#bit4
Ws,#bit4
1
None
Bit Toggle Ws
1
None
DS70265E-page 214
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
TABLE 22-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic
# of
# of
Status Flags
Affected
Assembly Syntax
Description
Words Cycles
10
BTSC
BTSS
BTST
BTSC
BTSC
BTSS
BTSS
f,#bit4
Ws,#bit4
f,#bit4
Ws,#bit4
Bit Test f, Skip if Clear
1
1
1
1
1
None
None
None
None
(2 or 3)
Bit Test Ws, Skip if Clear
Bit Test f, Skip if Set
1
(2 or 3)
11
12
1
(2 or 3)
Bit Test Ws, Skip if Set
1
(2 or 3)
BTST
f,#bit4
Ws,#bit4
Ws,#bit4
Ws,Wb
Bit Test f
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Z
BTST.C
BTST.Z
BTST.C
BTST.Z
BTSTS
Bit Test Ws to C
C
Bit Test Ws to Z
Z
C
Bit Test Ws<Wb> to C
Bit Test Ws<Wb> to Z
Bit Test then Set f
Ws,Wb
Z
13
BTSTS
f,#bit4
Z
BTSTS.C Ws,#bit4
BTSTS.Z Ws,#bit4
Bit Test Ws to C, then Set
Bit Test Ws to Z, then Set
Call subroutine
C
Z
14
15
CALL
CLR
CALL
CALL
CLR
CLR
CLR
CLR
CLRWDT
COM
COM
COM
CP
lit23
None
Wn
Call indirect subroutine
f = 0x0000
None
f
None
WREG
WREG = 0x0000
None
Ws
Ws = 0x0000
None
Acc,Wx,Wxd,Wy,Wyd,AWB
Clear Accumulator
Clear Watchdog Timer
f = f
OA,OB,SA,SB
WDTO,Sleep
N,Z
16
17
CLRWDT
COM
f
f,WREG
Ws,Wd
f
WREG = f
N,Z
Wd = Ws
N,Z
18
CP
Compare f with WREG
Compare Wb with lit5
Compare Wb with Ws (Wb – Ws)
Compare f with 0x0000
Compare Ws with 0x0000
Compare f with WREG, with Borrow
Compare Wb with lit5, with Borrow
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
CP
Wb,#lit5
Wb,Ws
f
CP
19
20
CP0
CPB
CP0
CP0
CPB
CPB
CPB
Ws
f
Wb,#lit5
Wb,Ws
Compare Wb with Ws, with Borrow
(Wb – Ws – C)
21
22
23
24
CPSEQ
CPSGT
CPSLT
CPSNE
CPSEQ
CPSGT
CPSLT
CPSNE
Wb, Wn
Wb, Wn
Wb, Wn
Wb, Wn
Compare Wb with Wn, skip if =
Compare Wb with Wn, skip if >
Compare Wb with Wn, skip if <
Compare Wb with Wn, skip if ≠
1
1
1
1
1
None
None
None
None
(2 or 3)
1
(2 or 3)
1
(2 or 3)
1
(2 or 3)
25
26
DAW
DEC
DAW
Wn
Wn = decimal adjust Wn
f = f – 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C
DEC
f
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
None
DEC
f,WREG
Ws,Wd
f
WREG = f – 1
DEC
Wd = Ws – 1
27
28
DEC2
DISI
DEC2
DEC2
DEC2
DISI
f = f – 2
f,WREG
Ws,Wd
#lit14
WREG = f – 2
Wd = Ws – 2
Disable Interrupts for k instruction cycles
© 2007-2011 Microchip Technology Inc.
DS70265E-page 215
dsPIC33FJ12MC201/202
TABLE 22-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic
# of
# of
Status Flags
Affected
Assembly Syntax
Description
Words Cycles
29
DIV
DIV.S
DIV.SD
DIV.U
DIV.UD
DIVF
DO
Wm,Wn
Signed 16/16-bit Integer Divide
1
1
1
1
1
2
2
1
18
18
18
18
18
2
N,Z,C,OV
N,Z,C,OV
N,Z,C,OV
N,Z,C,OV
N,Z,C,OV
None
Wm,Wn
Signed 32/16-bit Integer Divide
Wm,Wn
Unsigned 16/16-bit Integer Divide
Unsigned 32/16-bit Integer Divide
Signed 16/16-bit Fractional Divide
Do code to PC + Expr, lit14 + 1 times
Do code to PC + Expr, (Wn) + 1 times
Euclidean Distance (no accumulate)
Wm,Wn
30
31
DIVF
DO
Wm,Wn
#lit14,Expr
Wn,Expr
DO
2
None
32
33
ED
ED
Wm*Wm,Acc,Wx,Wy,Wxd
1
OA,OB,OAB,
SA,SB,SAB
EDAC
EDAC
Wm*Wm,Acc,Wx,Wy,Wxd
Euclidean Distance
1
1
OA,OB,OAB,
SA,SB,SAB
34
35
36
37
38
EXCH
FBCL
FF1L
FF1R
GOTO
EXCH
FBCL
FF1L
FF1R
GOTO
GOTO
INC
Wns,Wnd
Ws,Wnd
Ws,Wnd
Ws,Wnd
Expr
Swap Wns with Wnd
Find Bit Change from Left (MSb) Side
Find First One from Left (MSb) Side
Find First One from Right (LSb) Side
Go to address
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
1
None
C
C
C
None
Wn
Go to indirect
None
39
40
41
INC
f
f = f + 1
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
N,Z
INC
f,WREG
Ws,Wd
WREG = f + 1
INC
Wd = Ws + 1
INC2
IOR
INC2
INC2
INC2
IOR
f
f = f + 2
f,WREG
Ws,Wd
WREG = f + 2
Wd = Ws + 2
f
f = f .IOR. WREG
IOR
f,WREG
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
Wso,#Slit4,Acc
WREG = f .IOR. WREG
Wd = lit10 .IOR. Wd
Wd = Wb .IOR. Ws
Wd = Wb .IOR. lit5
Load Accumulator
N,Z
IOR
N,Z
IOR
N,Z
IOR
N,Z
42
LAC
LAC
OA,OB,OAB,
SA,SB,SAB
43
44
LNK
LSR
LNK
LSR
LSR
LSR
LSR
LSR
MAC
#lit14
Link Frame Pointer
1
1
1
1
1
1
1
1
1
1
1
1
1
1
None
C,N,OV,Z
C,N,OV,Z
C,N,OV,Z
N,Z
f
f = Logical Right Shift f
f,WREG
WREG = Logical Right Shift f
Wd = Logical Right Shift Ws
Wnd = Logical Right Shift Wb by Wns
Wnd = Logical Right Shift Wb by lit5
Ws,Wd
Wb,Wns,Wnd
Wb,#lit5,Wnd
N,Z
45
46
MAC
MOV
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd Multiply and Accumulate
,
AWB
OA,OB,OAB,
SA,SB,SAB
MAC
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square and Accumulate
1
1
OA,OB,OAB,
SA,SB,SAB
MOV
f,Wn
Move f to Wn
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
None
N,Z
MOV
f
Move f to f
MOV
f,WREG
Move f to WREG
None
None
None
None
None
None
None
None
None
MOV
#lit16,Wn
#lit8,Wn
Wn,f
Move 16-bit literal to Wn
Move 8-bit literal to Wn
Move Wn to f
MOV.b
MOV
MOV
Wso,Wdo
Move Ws to Wd
MOV
WREG,f
Move WREG to f
MOV.D
MOV.D
MOVSAC
Wns,Wd
Move Double from W(ns):W(ns + 1) to Wd
Move Double from Ws to W(nd + 1):W(nd)
Prefetch and store accumulator
Ws,Wnd
47
MOVSAC
Acc,Wx,Wxd,Wy,Wyd,AWB
DS70265E-page 216
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
TABLE 22-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic
# of
# of
Status Flags
Affected
Assembly Syntax
Description
Words Cycles
48
MPY
MPY
Multiply Wm by Wn to Accumulator
Square Wm to Accumulator
1
1
1
1
1
1
1
1
OA,OB,OAB,
SA,SB,SAB
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd
MPY
OA,OB,OAB,
SA,SB,SAB
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd
49
50
MPY.N
MSC
MPY.N
-(Multiply Wm by Wn) to Accumulator
None
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd
MSC
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Multiply and Subtract from Accumulator
OA,OB,OAB,
SA,SB,SAB
,
AWB
51
MUL
MUL.SS
MUL.SU
MUL.US
MUL.UU
Wb,Ws,Wnd
Wb,Ws,Wnd
Wb,Ws,Wnd
Wb,Ws,Wnd
{Wnd + 1, Wnd} = signed(Wb) * signed(Ws)
{Wnd + 1, Wnd} = signed(Wb) * unsigned(Ws)
{Wnd + 1, Wnd} = unsigned(Wb) * signed(Ws)
1
1
1
1
1
1
1
1
None
None
None
None
{Wnd + 1, Wnd} = unsigned(Wb) *
unsigned(Ws)
MUL.SU
MUL.UU
Wb,#lit5,Wnd
Wb,#lit5,Wnd
{Wnd + 1, Wnd} = signed(Wb) * unsigned(lit5)
1
1
1
1
None
None
{Wnd + 1, Wnd} = unsigned(Wb) *
unsigned(lit5)
MUL
NEG
f
W3:W2 = f * WREG
Negate Accumulator
1
1
1
1
None
52
NEG
Acc
OA,OB,OAB,
SA,SB,SAB
NEG
f
f = f + 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
None
NEG
f,WREG
Ws,Wd
WREG = f + 1
NEG
Wd = Ws + 1
53
54
NOP
POP
NOP
No Operation
NOPR
POP
No Operation
None
f
Pop f from Top-of-Stack (TOS)
Pop from Top-of-Stack (TOS) to Wdo
None
POP
Wdo
Wnd
None
POP.D
Pop from Top-of-Stack (TOS) to
W(nd):W(nd + 1)
None
POP.S
PUSH
Pop Shadow Registers
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
All
None
None
None
None
WDTO,Sleep
None
None
None
None
None
None
None
None
C,N,Z
C,N,Z
C,N,Z
N,Z
55
PUSH
f
Push f to Top-of-Stack (TOS)
Push Wso to Top-of-Stack (TOS)
Push W(ns):W(ns + 1) to Top-of-Stack (TOS)
Push Shadow Registers
1
PUSH
Wso
Wns
1
PUSH.D
PUSH.S
PWRSAV
RCALL
RCALL
REPEAT
REPEAT
RESET
RETFIE
RETLW
RETURN
RLC
2
1
56
57
PWRSAV
RCALL
#lit1
Expr
Wn
Go into Sleep or Idle mode
Relative Call
1
2
Computed Call
2
58
REPEAT
#lit14
Wn
Repeat Next Instruction lit14 + 1 times
Repeat Next Instruction (Wn) + 1 times
Software device Reset
1
1
59
60
61
62
63
RESET
RETFIE
RETLW
RETURN
RLC
1
Return from interrupt
3 (2)
#lit10,Wn
Return with literal in Wn
3 (2)
Return from Subroutine
3 (2)
1
f
f = Rotate Left through Carry f
WREG = Rotate Left through Carry f
Wd = Rotate Left through Carry Ws
f = Rotate Left (No Carry) f
RLC
f,WREG
Ws,Wd
f
1
RLC
1
64
65
RLNC
RRC
RLNC
1
RLNC
f,WREG
Ws,Wd
f
WREG = Rotate Left (No Carry) f
Wd = Rotate Left (No Carry) Ws
f = Rotate Right through Carry f
WREG = Rotate Right through Carry f
Wd = Rotate Right through Carry Ws
1
N,Z
RLNC
1
N,Z
RRC
1
C,N,Z
C,N,Z
C,N,Z
RRC
f,WREG
Ws,Wd
1
RRC
1
© 2007-2011 Microchip Technology Inc.
DS70265E-page 217
dsPIC33FJ12MC201/202
TABLE 22-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic
# of
# of
Status Flags
Affected
Assembly Syntax
Description
Words Cycles
66
RRNC
RRNC
RRNC
RRNC
SAC
f
f = Rotate Right (No Carry) f
WREG = Rotate Right (No Carry) f
Wd = Rotate Right (No Carry) Ws
Store Accumulator
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
N,Z
N,Z
f,WREG
Ws,Wd
N,Z
67
SAC
Acc,#Slit4,Wdo
None
None
C,N,Z
None
None
None
SAC.R
SE
Acc,#Slit4,Wdo
Store Rounded Accumulator
Wnd = sign-extended Ws
f = 0xFFFF
68
69
SE
Ws,Wnd
f
SETM
SETM
SETM
SETM
SFTAC
WREG
Ws
WREG = 0xFFFF
Ws = 0xFFFF
70
71
SFTAC
SL
Acc,Wn
Arithmetic Shift Accumulator by (Wn)
OA,OB,OAB,
SA,SB,SAB
SFTAC
Acc,#Slit6
Arithmetic Shift Accumulator by Slit6
1
1
OA,OB,OAB,
SA,SB,SAB
SL
SL
SL
SL
SL
SUB
f
f = Left Shift f
1
1
1
1
1
1
1
1
1
1
1
1
C,N,OV,Z
C,N,OV,Z
C,N,OV,Z
N,Z
f,WREG
Ws,Wd
WREG = Left Shift f
Wd = Left Shift Ws
Wb,Wns,Wnd
Wb,#lit5,Wnd
Acc
Wnd = Left Shift Wb by Wns
Wnd = Left Shift Wb by lit5
Subtract Accumulators
N,Z
72
SUB
OA,OB,OAB,
SA,SB,SAB
SUB
f
f = f – WREG
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
1
1
1
1
1
1
1
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
None
SUB
f,WREG
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
f
WREG = f – WREG
Wn = Wn – lit10
SUB
SUB
Wd = Wb – Ws
SUB
Wd = Wb – lit5
73
SUBB
SUBB
SUBB
SUBB
SUBB
SUBB
SUBR
SUBR
SUBR
SUBR
SUBBR
SUBBR
SUBBR
SUBBR
SWAP.b
SWAP
TBLRDH
TBLRDL
TBLWTH
TBLWTL
ULNK
XOR
f = f – WREG – (C)
WREG = f – WREG – (C)
Wn = Wn – lit10 – (C)
Wd = Wb – Ws – (C)
Wd = Wb – lit5 – (C)
f = WREG – f
f,WREG
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
f
74
75
SUBR
f,WREG
Wb,Ws,Wd
Wb,#lit5,Wd
f
WREG = WREG – f
Wd = Ws – Wb
Wd = lit5 – Wb
SUBBR
f = WREG – f – (C)
WREG = WREG – f – (C)
Wd = Ws – Wb – (C)
Wd = lit5 – Wb – (C)
Wn = nibble swap Wn
Wn = byte swap Wn
Read Prog<23:16> to Wd<7:0>
Read Prog<15:0> to Wd
Write Ws<7:0> to Prog<23:16>
Write Ws to Prog<15:0>
Unlink Frame Pointer
f = f .XOR. WREG
f,WREG
Wb,Ws,Wd
Wb,#lit5,Wd
Wn
76
SWAP
Wn
None
77
78
79
80
81
82
TBLRDH
TBLRDL
TBLWTH
TBLWTL
ULNK
Ws,Wd
None
Ws,Wd
None
Ws,Wd
None
Ws,Wd
None
None
XOR
f
N,Z
XOR
f,WREG
WREG = f .XOR. WREG
Wd = lit10 .XOR. Wd
Wd = Wb .XOR. Ws
Wd = Wb .XOR. lit5
Wnd = Zero-extend Ws
N,Z
XOR
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
Ws,Wnd
N,Z
XOR
N,Z
XOR
N,Z
83
ZE
ZE
C,Z,N
DS70265E-page 218
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
23.1 MPLAB Integrated Development
Environment Software
23.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers and dsPIC® digital signal
controllers are supported with a full range of software
and hardware development tools:
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16/32-bit
microcontroller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• Integrated Development Environment
- MPLAB® IDE Software
• A single graphical interface to all debugging tools
- Simulator
• Compilers/Assemblers/Linkers
- MPLAB C Compiler for Various Device
Families
- Programmer (sold separately)
- In-Circuit Emulator (sold separately)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
- HI-TECH C for Various Device Families
- MPASMTM Assembler
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Customizable data windows with direct edit of
contents
• Simulators
• High-level source code debugging
• Mouse over variable inspection
- MPLAB SIM Software Simulator
• Emulators
• Drag and drop variables from source to watch
windows
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers
• Extensive on-line help
• Integration of select third party tools, such as
IAR C Compilers
- MPLAB ICD 3
- PICkit™ 3 Debug Express
• Device Programmers
- PICkit™ 2 Programmer
- MPLAB PM3 Device Programmer
The MPLAB IDE allows you to:
• Edit your source files (either C or assembly)
• One-touch compile or assemble, and download to
emulator and simulator tools (automatically
updates all project information)
• Low-Cost Demonstration/Development Boards,
Evaluation Kits, and Starter Kits
• Debug using:
- Source files (C or assembly)
- Mixed C and assembly
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 219
dsPIC33FJ12MC201/202
23.2 MPLAB C Compilers for Various
Device Families
23.5 MPLINK Object Linker/
MPLIB Object Librarian
The MPLAB C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC18,
PIC24 and PIC32 families of microcontrollers and the
dsPIC30 and dsPIC33 families of digital signal control-
lers. These compilers provide powerful integration
capabilities, superior code optimization and ease of
use.
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
23.3 HI-TECH C for Various Device
Families
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
The HI-TECH C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC
family of microcontrollers and the dsPIC family of digital
signal controllers. These compilers provide powerful
integration capabilities, omniscient code generation
and ease of use.
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
23.6 MPLAB Assembler, Linker and
Librarian for Various Device
Families
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
The compilers include a macro assembler, linker, pre-
processor, and one-step driver, and can run on multiple
platforms.
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC devices. MPLAB C Compiler uses
the assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
23.4 MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command line interface
• Rich directive set
• Flexible macro language
The MPASM Assembler features include:
• Integration into MPLAB IDE projects
• MPLAB IDE compatibility
• User-defined macros to streamline
assembly code
• Conditional assembly for multi-purpose
source files
• Directives that allow complete control over the
assembly process
DS70265E-page 220
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
23.7 MPLAB SIM Software Simulator
23.9 MPLAB ICD 3 In-Circuit Debugger
System
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
MPLAB ICD 3 In-Circuit Debugger System is Micro-
chip's most cost effective high-speed hardware
debugger/programmer for Microchip Flash Digital Sig-
nal Controller (DSC) and microcontroller (MCU)
devices. It debugs and programs PIC® Flash microcon-
trollers and dsPIC® DSCs with the powerful, yet easy-
to-use graphical user interface of MPLAB Integrated
Development Environment (IDE).
The MPLAB ICD 3 In-Circuit Debugger probe is con-
nected to the design engineer's PC using a high-speed
USB 2.0 interface and is connected to the target with a
connector compatible with the MPLAB ICD 2 or MPLAB
REAL ICE systems (RJ-11). MPLAB ICD 3 supports all
MPLAB ICD 2 headers.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C Compilers,
and the MPASM and MPLAB Assemblers. The soft-
ware simulator offers the flexibility to develop and
debug code outside of the hardware laboratory envi-
ronment, making it an excellent, economical software
development tool.
23.10 PICkit 3 In-Circuit Debugger/
Programmer and
23.8 MPLAB REAL ICE In-Circuit
Emulator System
PICkit 3 Debug Express
The MPLAB PICkit 3 allows debugging and program-
ming of PIC® and dsPIC® Flash microcontrollers at a
most affordable price point using the powerful graphical
user interface of the MPLAB Integrated Development
Environment (IDE). The MPLAB PICkit 3 is connected
to the design engineer's PC using a full speed USB
interface and can be connected to the target via an
Microchip debug (RJ-11) connector (compatible with
MPLAB ICD 3 and MPLAB REAL ICE). The connector
uses two device I/O pins and the reset line to imple-
ment in-circuit debugging and In-Circuit Serial Pro-
gramming™.
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs PIC® Flash MCUs and dsPIC® Flash DSCs
with the easy-to-use, powerful graphical user interface of
the MPLAB Integrated Development Environment (IDE),
included with each kit.
The emulator is connected to the design engineer’s PC
using a high-speed USB 2.0 interface and is connected
to the target with either a connector compatible with in-
circuit debugger systems (RJ11) or with the new high-
speed, noise tolerant, Low-Voltage Differential Signal
(LVDS) interconnection (CAT5).
The PICkit 3 Debug Express include the PICkit 3, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
The emulator is field upgradable through future firmware
downloads in MPLAB IDE. In upcoming releases of
MPLAB IDE, new devices will be supported, and new
features will be added. MPLAB REAL ICE offers
significant advantages over competitive emulators
including low-cost, full-speed emulation, run-time
variable watches, trace analysis, complex breakpoints, a
ruggedized probe interface and long (up to three meters)
interconnection cables.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 221
dsPIC33FJ12MC201/202
23.11 PICkit 2 Development
Programmer/Debugger and
PICkit 2 Debug Express
23.13 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
The PICkit™ 2 Development Programmer/Debugger is
a low-cost development tool with an easy to use inter-
face for programming and debugging Microchip’s Flash
families of microcontrollers. The full featured
Windows® programming interface supports baseline
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully func-
tional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
(PIC10F,
PIC12F5xx,
PIC16F5xx),
midrange
(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,
dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit
microcontrollers, and many Microchip Serial EEPROM
products. With Microchip’s powerful MPLAB Integrated
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
Development Environment (IDE) the PICkit™
2
enables in-circuit debugging on most PIC® microcon-
trollers. In-Circuit-Debugging runs, halts and single
steps the program while the PIC microcontroller is
embedded in the application. When halted at a break-
point, the file registers can be examined and modified.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™ demon-
stration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
The PICkit 2 Debug Express include the PICkit 2, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
®
for analog filter design, KEELOQ security ICs, CAN,
IrDA®, PowerSmart battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
23.12 MPLAB PM3 Device Programmer
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modu-
lar, detachable socket assembly to support various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an MMC card for file
storage and data applications.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
DS70265E-page 222
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
24.0 ELECTRICAL CHARACTERISTICS
This section provides an overview of dsPIC33FJ12MC201/202 electrical characteristics. Additional information will be
provided in future revisions of this document as it becomes available.
Absolute maximum ratings for the dsPIC33FJ12MC201/202 family are listed below. Exposure to these maximum rating
conditions for extended periods may affect device reliability. Functional operation of the device at these or any other
conditions above the parameters indicated in the operation listings of this specification is not implied.
Absolute Maximum Ratings(1)
Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V
Voltage on any pin that is not 5V tolerant with respect to VSS(4) .................................................... -0.3V to (VDD + 0.3V)
Voltage on any 5V tolerant pin with respect to VSS when VDD ≥ 3.0V(4) .................................................. -0.3V to +5.6V
Voltage on any 5V tolerant pin with respect to VSS when VDD < 3.0V(4) ....................................... -0.3V to (VDD + 0.3V)
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin(2)...........................................................................................................................250 mA
Maximum output current sunk by any I/O pin(3) ........................................................................................................4 mA
Maximum output current sourced by any I/O pin(3)...................................................................................................4 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports(2)...............................................................................................................200 mA
Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at those or any other conditions
above those indicated in the operation listings of this specification is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.
2: Maximum allowable current is a function of device maximum power dissipation (see Table 24-2).
3: Exceptions are CLKOUT, which is able to sink/source 25 mA, and the VREF+, VREF-, SCLx, SDAx, PGECx,
and PGEDx pins, which are able to sink/source 12 mA.
4: See the “Pin Diagrams” section for 5V tolerant pins.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 223
dsPIC33FJ12MC201/202
24.1 DC Characteristics
TABLE 24-1: OPERATING MIPS VS. VOLTAGE
Max MIPS
VDD Range
(in Volts)
Temp Range
(in °C)
Characteristic
dsPIC33FJ12MC201/202
—
—
3.0-3.6V
3.0-3.6V
-40°C to +85°C
-40°C to +125°C
40
40
TABLE 24-2: THERMAL OPERATING CONDITIONS
Rating
Symbol
Min
Typ
Max
Unit
Industrial Temperature Devices
Operating Junction Temperature Range
Operating Ambient Temperature Range
Extended Temperature Devices
TJ
TA
-40
-40
—
—
+125
+85
°C
°C
Operating Junction Temperature Range
Operating Ambient Temperature Range
TJ
TA
-40
-40
—
—
+140
+125
°C
°C
Power Dissipation:
Internal chip power dissipation:
PINT = VDD x (IDD – Σ IOH)
PD
PINT + PI/O
W
W
I/O Pin Power Dissipation:
I/O = Σ ({VDD – VOH} x IOH) + Σ (VOL x IOL)
Maximum Allowed Power Dissipation
PDMAX
(TJ – TA)/θJA
TABLE 24-3: THERMAL PACKAGING CHARACTERISTICS
Characteristic
Symbol
Typ
Max
Unit
Notes
Package Thermal Resistance, 20-pin PDIP
Package Thermal Resistance, 28-pin SPDIP
Package Thermal Resistance, 20-pin SOIC
Package Thermal Resistance, 28-pin SOIC
Package Thermal Resistance, 20-pin SSOP
Package Thermal Resistance, 28-pin SSOP
Package Thermal Resistance, 28-pin QFN
θJA
θJA
θJA
θJA
θJA
θJA
θJA
45
45
—
—
—
—
—
—
—
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
1
1
1
1
1
1
1
60
50
108
71
35
Note 1: Junction to ambient thermal resistance, Theta-JA (θJA) numbers are achieved by package simulations.
DS70265E-page 224
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
TABLE 24-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Typ(1)
Max Units
Conditions
Operating Voltage
DC10 Supply Voltage
VDD
3.0
1.8
—
—
—
—
3.6
—
V
V
V
Industrial and Extended
DC12
DC16
VDR
RAM Data Retention Voltage(2)
VDD Start Voltage(3)
—
—
VPOR
VSS
to ensure internal
Power-on Reset signal
DC17
SVDD
VDD Rise Rate
0.03
—
—
V/ms 0-3.0V in 0.1s
to ensure internal
Power-on Reset signal
Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
2: This is the limit to which VDD may be lowered without losing RAM data.
3: VDD voltage must remain at VSS for a minimum of 200 µs to ensure POR.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 225
dsPIC33FJ12MC201/202
TABLE 24-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
Parameter
Typical(1)
Max
Units
Conditions
No.
Operating Current (IDD)(2)
DC20d
DC20a
DC20b
DC20c
DC21d
DC21a
DC21b
DC21c
DC22d
DC22a
DC22b
DC22c
DC23d
DC23a
DC23b
DC23c
DC24d
DC24a
DC24b
DC24c
24
27
27
27
30
31
32
33
35
38
38
39
47
48
48
48
56
56
54
54
30
30
30
35
40
40
45
45
50
50
55
55
70
70
70
70
90
90
90
90
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
-40°C
+25°C
+85°C
+125°C
-40°C
3.3V
3.3V
3.3V
3.3V
3.3V
10 MIPS(3)
16 MIPS(3)
20 MIPS(3)
30 MIPS(3)
40 MIPS
+25°C
+85°C
+125°C
-40°C
+25°C
+85°C
+125°C
-40°C
+25°C
+85°C
+125°C
-40°C
+25°C
+85°C
+125°C
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have
an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSC1
driven with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VSS.
MCLR = VDD, WDT and FSCM are disabled. CPU, SRAM, program memory and data memory are opera-
tional. No peripheral modules are operating; however, every peripheral is being clocked (PMD bits are all
zeroed).
3: These parameters are characterized, but not tested in manufacturing.
DS70265E-page 226
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
TABLE 24-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
DC CHARACTERISTICS
Parameter
Typical(1)
No.
Max
Units
Conditions
Idle Current (IIDLE): Core OFF Clock ON Base Current(2)
DC40d
DC40a
DC40b
DC40c
DC41d
DC41a
DC41b
DC41c
DC42d
DC42a
DC42b
DC42c
DC43a
DC43d
DC43b
DC43c
DC44d
DC44a
DC44b
DC44c
3
3
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
-40°C
+25°C
+85°C
+125°C
-40°C
10 MIPS(3)
16 MIPS(3)
20 MIPS(3)
30 MIPS(3)
40 MIPS
3.3V
3.3V
3
3
4
4
+25°C
+85°C
+125°C
-40°C
5
5
6
6
+25°C
+85°C
+125°C
+25°C
-40°C
3.3V
3.3V
3.3V
7
7
9
9
9
+85°C
+125°C
-40°C
9
10
10
10
10
+25°C
+85°C
+125°C
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated.
2: Base IIDLE current is measured with core off, clock on and all modules turned off. Peripheral Module
Disable SFR registers are zeroed. All I/O pins are configured as inputs and pulled to VSS.
3: These parameters are characterized, but not tested in manufacturing.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 227
dsPIC33FJ12MC201/202
TABLE 24-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
Parameter
Typical(1)
Max
Units
Conditions
No.
Power-Down Current (IPD)(2)
DC60d
DC60a
DC60b
DC60c
DC61d
DC61a
DC61b
DC61c
55
63
85
146
8
500
500
500
1000
13
μA
μA
μA
μA
μA
μA
μA
μA
-40°C
+25°C
+85°C
+125°C
-40°C
3.3V
3.3V
Base Power-Down Current(3,4)
10
12
13
15
+25°C
+85°C
+125°C
(3,5)
Watchdog Timer Current: ΔIWDT
20
25
Note 1: Data in the Typical column is at 3.3V, 25°C unless otherwise stated.
2: Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and
pulled to VSS. WDT, etc., are all switched off, and VREGS (RCON<8>) = 1.
3: The Δ current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current.
4: These currents are measured on the device containing the most memory in this family.
5: These parameters are characterized, but not tested in manufacturing.
TABLE 24-8: DC CHARACTERISTICS: DOZE CURRENT (IDOZE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
Doze
Parameter No.
Typical(1)
Max
Units
Conditions
Ratio(2)
DC73a
DC73f
DC73g
DC70a
DC70f
DC70g
DC71a
DC71f
DC71g
DC72a
DC72f
DC72g
11
11
11
11
11
11
12
12
12
12
12
12
35
30
30
50
30
30
50
30
30
50
30
30
1:2
1:64
1:128
1:2
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
-40°C
+25°C
+85°C
3.3V
40 MIPS
40 MIPS
40 MIPS
40 MIPS
1:64
1:128
1:2
3.3V
3.3V
1:64
1:128
1:2
1:64
1:128
+125°C 3.3V
Note 1: Data in the Typical column is at 3.3V, 25°C unless otherwise stated.
2: Parameters with DOZE ratios of 1:2 and 1:64 are characterized, but are not
tested in manufacturing.
DS70265E-page 228
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
TABLE 24-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Typ(1)
Max
Units
Conditions
VIL
Input Low Voltage
I/O pins
DI10
DI15
DI16
DI18
DI19
VSS
VSS
VSS
VSS
VSS
—
—
—
—
—
0.2 VDD
0.2 VDD
0.2 VDD
0.3 VDD
0.8
V
V
V
V
V
MCLR
I/O Pins with OSC1 or SOSCI
SDA, SCL
SMBus disabled
SDA, SCL
SMBus enabled
VIH
Input High Voltage(10)
DI20
DI21
I/O Pins Not 5V Tolerant(4)
0.7 VDD
0.7 VDD
—
—
VDD
5.5
V
V
I/O Pins 5V Tolerant(4)
I/O Pin with Schmitt Trigger
Input
0.7 VDD
—
0.8 VDD
V
DI25
DI26
MCLR
0.8 VDD
0.7 VDD
—
—
VDD
VDD
V
V
OSC1 (in XT, HS, and LP
modes)
DI27
DI28
DI29
OSC1 (in RC mode)
SDAx, SCLx
0.9 VDD
0.7 VDD
2.1
—
—
—
VDD
VDD
VDD
V
V
V
SMBus disabled
SMBus enabled
SDAx, SCLx
ICNPU
CNx Pull-up Current
DI30
50
250
400
μA
VDD = 3.3V, VPIN = VSS
Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: See “Pin Diagrams” for a list of 5V tolerant pins.
5: VIL source < (VSS – 0.3). Characterized but not tested.
6: Non-5V tolerant pins VIH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V. Characterized but not
tested.
7: Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V.
8: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts.
9: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted pro-
vided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not
exceed the specified limit. Characterized but not tested.
10: These parameters are characterized, but not tested.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 229
dsPIC33FJ12MC201/202
TABLE 24-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
Param
No.
Symbol
Characteristic
Min
Typ(1)
Max
Units
Conditions
IIL
Input Leakage Current(2,3)
DI50
I/O Pins 5V Tolerant(4)
—
—
—
—
±2
±1
μA
μA
VSS ≤VPIN ≤VDD,
Pin at high-impedance
DI51
I/O Pins Not 5V Tolerant(4)
VSS ≤VPIN ≤VDD,
Pin at high-impedance,
-40°C ≤TA ≤+85°C
DI51a
DI51b
I/O Pins Not 5V Tolerant(4)
I/O Pins Not 5V Tolerant(4)
—
—
—
—
±2
μA Shared with external reference
pins, -40°C ≤TA ≤+85°C
±3.5
μA
VSS ≤VPIN ≤VDD, Pin at
high-impedance,
-40°C ≤TA ≤+125°C
DI51c
I/O Pins Not 5V Tolerant(4)
—
—
±8
μA Analog pins shared with
external reference pins,
-40°C ≤TA ≤+125°C
DI55
DI56
MCLR
OSC1
—
—
—
—
±2
±2
μA
μA
VSS ≤VPIN ≤VDD
VSS ≤VPIN ≤VDD,
XT and HS modes
Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: See “Pin Diagrams” for a list of 5V tolerant pins.
5: VIL source < (VSS – 0.3). Characterized but not tested.
6: Non-5V tolerant pins VIH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V. Characterized but not
tested.
7: Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V.
8: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts.
9: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted pro-
vided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not
exceed the specified limit. Characterized but not tested.
10: These parameters are characterized, but not tested.
DS70265E-page 230
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
TABLE 24-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
Param
No.
Symbol
Characteristic
Min
Typ(1)
Max
Units
Conditions
IICL
Input Low Injection Current
DI60a
All pins except VDD, VSS, AVDD,
AVSS, MCLR, VCAP, SOSCI,
and SOSCO
0
—
-5(5,8)
mA
IICH
Input High Injection Current
DI60b
DI60c
All pins except VDD, VSS, AVDD,
AVSS, MCLR, VCAP, SOSCI,
SOSCO, and digital 5V-tolerant
designated pins
0
—
—
+5(6,7,8) mA
∑IICT
Total Input Injection Current
(sum of all I/O and control
pins)
-20(9)
+20(9)
mA Absolute instantaneous sum of
all ± input injection currents
from all I/O pins
( | IICL + | IICH | ) ≤ ∑IICT
Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: See “Pin Diagrams” for a list of 5V tolerant pins.
5: VIL source < (VSS – 0.3). Characterized but not tested.
6: Non-5V tolerant pins VIH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V. Characterized but not
tested.
7: Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V.
8: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts.
9: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted pro-
vided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not
exceed the specified limit. Characterized but not tested.
10: These parameters are characterized, but not tested.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 231
dsPIC33FJ12MC201/202
TABLE 24-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
Param
No.
Symbol
Characteristic
Min
Typ
Max Units
Conditions
VOL
Output Low Voltage
I/O ports
DO10
DO16
—
—
—
—
0.4
0.4
V
V
IOL = 2 mA, VDD = 3.3V
IOL = 2 mA, VDD = 3.3V
OSC2/CLKO
VOH
Output High Voltage
I/O ports
DO20
DO26
2.40
2.41
—
—
—
—
V
V
IOH = -2.3 mA, VDD = 3.3V
IOH = -1.3 mA, VDD = 3.3V
OSC2/CLKO
TABLE 24-11: ELECTRICAL CHARACTERISTICS: BOR
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min(1) Typ Max(1) Units
Conditions
BO10
VBOR
BOR Event on VDD transition
high-to-low
2.40 2.55
—
V
VDD
Note 1: Parameters are for design guidance only and are not tested in manufacturing.
DS70265E-page 232
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
TABLE 24-12: DC CHARACTERISTICS: PROGRAM MEMORY
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic(3)
Min
Typ(1) Max Units
Conditions
Program Flash Memory
Cell Endurance
D130a EP
10,000
VMIN
—
—
—
E/W -40°C to +125°C
D131
VPR
VDD for Read
3.6
V
VMIN = Minimum operating
voltage
D132B VPEW
VDD for Self-Timed Write
Characteristic Retention
VMIN
20
—
—
10
—
—
—
—
—
—
3.6
—
V
VMIN = Minimum operating
voltage
D134
D135
TRETD
IDDP
Year Provided no other specifications
are violated
Supply Current during
Programming
—
—
mA
D136a TRW
D136b TRW
D137a TPE
D137b TPE
D138a TWW
D138b TWW
Row Write Time
1.32
1.28
20.1
19.5
42.3
41.1
1.74
1.79
26.5
27.3
55.9
57.6
ms TRW = 11064 FRC cycles,
TA = +85°C, See Note 2
Row Write Time
ms TRW = 11064 FRC cycles,
TA = +125°C, See Note 2
Page Erase Time
Page Erase Time
Word Write Cycle Time
Word Write Cycle Time
ms TPE = 168517 FRC cycles,
TA = +85°C, See Note 2
ms TPE = 168517 FRC cycles,
TA = +125°C, See Note 2
µs
µs
TWW = 355 FRC cycles,
TA = +85°C, See Note 2
TWW = 355 FRC cycles,
TA = +125°C, See Note 2
Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
2: Other conditions: FRC = 7.37 MHz, TUN<5:0> = b'011111(for Min), TUN<5:0> = b'100000(for Max).
This parameter depends on the FRC accuracy (see Table 24-18) and the value of the FRC Oscillator
Tuning register (see Register 8-4). For complete details on calculating the Minimum and Maximum time
see Section 5.3 “Programming Operations”.
3: These parameters are ensured by design, but are not characterized or tested in manufacturing.
TABLE 24-13: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
Param
No.
Symbol
Characteristics
Min
Typ
Max
Units
Comments
CEFC
External Filter Capacitor
Value(1)
4.7
10
—
μF
Capacitor must be low
series resistance
(< 5 ohms)
Note 1: Typical VCAP pin voltage = 2.5V when VDD ≥ VDDMIN.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 233
dsPIC33FJ12MC201/202
24.2 AC Characteristics and Timing
Parameters
This section defines dsPIC33FJ12MC201/202
AC characteristics and timing parameters.
TABLE 24-14: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
AC CHARACTERISTICS
-40°C ≤TA ≤+125°C for Extended
Operating voltage VDD range as described in Section 24.1 “DC
Characteristics”.
FIGURE 24-1:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 – for all pins except OSC2
VDD/2
Load Condition 2 – for OSC2
CL
RL
Pin
VSS
CL
Pin
RL = 464Ω
CL = 50 pF for all pins except OSC2
VSS
15 pF for OSC2 output
TABLE 24-15: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS
Param
Symbol
Characteristic
Min
Typ
Max Units
Conditions
No.
DO50 COSC2
OSC2/SOSC2 pin
—
—
15
pF In XT and HS modes when
external clock is used to drive
OSC1
DO56 CIO
DO58 CB
All I/O pins and OSC2
SCLx, SDAx
—
—
—
—
50
pF EC mode
pF In I2C mode
400
DS70265E-page 234
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
FIGURE 24-2:
EXTERNAL CLOCK TIMING
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
CLKO
OS20
OS25
OS30 OS30
OS31 OS31
OS41
OS40
TABLE 24-16: EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
Symb
No.
Characteristic
Min
Typ(1)
Max
Units
Conditions
OS10
FIN
External CLKI Frequency
(External clocks allowed only
in EC and ECPLL modes)
DC
—
40
MHz EC
Oscillator Crystal Frequency
3.5
10
—
—
—
—
10
40
33
MHz XT
MHz HS
kHz SOSC
OS20
OS25
OS30
TOSC
TCY
TOSC = 1/FOSC
Instruction Cycle Time(2,4)
12.5
25
—
—
—
DC
DC
ns
ns
TosL, External Clock in (OSC1)(5)
TosH High or Low Time
TosR, External Clock in (OSC1)(5)
TosF Rise or Fall Time
0.375 x TOSC
0.625 x TOSC
ns
EC
EC
OS31
—
—
20
ns
OS40
OS41
OS42
TckR CLKO Rise Time(3,5)
—
—
14
5.2
5.2
16
—
—
18
ns
ns
—
—
TckF
GM
CLKO Fall Time(3,5)
External Oscillator
mA/V VDD = 3.3V
TA = +25ºC
Transconductance(4)
Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
2: Instruction cycle period (TCY) equals two times the input oscillator time-base period. All specified values
are based on characterization data for that particular oscillator type under standard operating conditions
with the device executing code. Exceeding these specified limits may result in an unstable oscillator
operation and/or higher than expected current consumption. All devices are tested to operate at “min.”
values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the
“max.” cycle time limit is “DC” (no clock) for all devices.
3: Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin.
4: These parameters are characterized by similarity, but are tested in manufacturing at FIN = 40 MHz only.
5: These parameters are characterized by similarity, but are not tested in manufacturing.
6: Data for this parameter is Preliminary. This parameter is characterized, but not tested in manufacturing.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 235
dsPIC33FJ12MC201/202
TABLE 24-17: PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0V TO 3.6V)
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Typ(1)
Max
Units
Conditions
OS50
FPLLI
PLL Voltage Controlled
Oscillator (VCO) Input
Frequency Range
0.8
—
8
MHz ECPLL, HSPLL, XTPLL
modes
OS51
OS52
OS53
FSYS
On-Chip VCO System Frequency 100
—
200
3.1
3
MHz
mS
%
—
—
TLOCK PLL Start-up Time (Lock Time)
CLKO Stability (Jitter)(2)
0.9
-3
1.5
0.5
DCLK
Measured over 100 ms
period
Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2: These parameters are characterized by similarity, but are not tested in manufacturing. This specification is
based on clock cycle by clock cycle measurements. To calculate the effective jitter for individual time bases
or communication clocks use this formula:
DCLK
Peripheral Clock Jitter = -----------------------------------------------------------------------
FOSC
⎛
⎝
⎞
⎠
-------------------------------------------------------------
Peripheral Bit Rate Clock
For example: Fosc = 32 MHz, DCLK = 3%, SPI bit rate clock, (i.e., SCK) is 2 MHz.
DCLK
3%
3%
-------
-----------------------------
---------
SPI SCK Jitter =
=
=
= 0.75%
4
16
32 MHz
⎛
⎝
⎞
⎠
--------------------
2 MHz
TABLE 24-18: AC CHARACTERISTICS: INTERNAL RC ACCURACY
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature
-40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
Param
No.
Characteristic
Min
Typ
Max
Units
Conditions
Internal FRC Accuracy @ 7.3728 MHz(1)
F20a
F20b
FRC
FRC
-2
-5
—
—
+2
+5
%
%
-40°C ≤TA ≤+85°C
-40°C ≤TA ≤+125°C
VDD = 3.0-3.6V
VDD = 3.0-3.6V
Note 1: Frequency calibrated at 25°C and 3.3V. TUN bits may be used to compensate for temperature drift.
TABLE 24-19: INTERNAL RC ACCURACY
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
Param
No.
Characteristic
Min
Typ
Max
Units
Conditions
LPRC @ 32.768 kHz(1,2)
F21a LPRC
F21b LPRC
-20
-70
±6
—
+20
+70
%
%
-40°C ≤TA ≤+85°C
-40°C ≤TA ≤+125°C
VDD = 3.0-3.6V
VDD = 3.0-3.6V
Note 1: Change of LPRC frequency as VDD changes.
2: LPRC accuracy impacts the Watchdog Timer Time-out Period (TWDT1). See Section 21.4 “Watchdog
Timer (WDT)” for more information.
DS70265E-page 236
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
FIGURE 24-3:
CLKO AND I/O TIMING CHARACTERISTICS
I/O Pin
(Input)
DI35
DI40
I/O Pin
(Output)
New Value
Old Value
DO31
DO32
Note: Refer to Figure 24-1 for load conditions.
TABLE 24-20: I/O TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(2)
Min
Typ(1)
Max
Units
Conditions
DO31
DO32
DI35
TIOR
TIOF
TINP
TRBP
Port Output Rise Time
—
—
25
2
10
10
—
—
25
25
—
—
ns
ns
—
—
—
—
Port Output Fall Time
INTx Pin High or Low Time (input)
CNx High or Low Time (input)
ns
DI40
TCY
Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
2: These parameters are characterized, but are not tested in manufacturing.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 237
dsPIC33FJ12MC201/202
FIGURE 24-4:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING CHARACTERISTICS
VDD
SY12
MCLR
SY10
Internal
POR
SY11
SY30
PWRT
Time-out
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
SY20
SY13
SY13
I/O Pins
SY35
FSCM
Delay
Note: Refer to Figure 24-1 for load conditions.
DS70265E-page 238
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
TABLE 24-21: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
Param
No.
Symbol
Characteristic(1)
Min Typ(2) Max Units
Conditions
SY10
SY11
TMCL
MCLR Pulse Width (low)
Power-up Timer Period(1)
2
—
—
—
μs
-40°C to +85°C
TPWRT
—
2
4
ms
-40°C to +85°C
User programmable
8
16
32
64
128
SY12
SY13
TPOR
TIOZ
Power-on Reset Delay(3)
3
10
30
μs
μs
-40°C to +85°C
—
I/O High-Impedance from MCLR
Low or Watchdog Timer Reset(1)
0.68 0.72
1.2
SY20
TWDT1
Watchdog Timer Time-out
Period(1)
—
—
—
ms
See Section 21.4 “Watch-
dog Timer (WDT)” and
LPRC parameter F21a
(Table 24-19).
SY30
SY35
TOST
Oscillator Start-up Time
—
—
1024
TOSC
—
—
TOSC = OSC1 period
TFSCM
Fail-Safe Clock Monitor Delay(1)
500
900
μs
-40°C to +85°C
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
3: These parameters are characterized, but are not tested in manufacturing.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 239
dsPIC33FJ12MC201/202
FIGURE 24-5:
TIMER1, 2, 3 AND 4 EXTERNAL CLOCK TIMING CHARACTERISTICS
TxCK
Tx11
Tx10
Tx15
Tx20
OS60
TMRx
Note: Refer to Figure 24-1 for load conditions.
(1)
TABLE 24-22: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Typ
Max
Units
Conditions
TA10
TA11
TA15
TTXH
TTXL
TTXP
TxCK High Time Synchronous,
no prescaler
TCY + 20
—
—
ns
Must also meet
parameterTA15.
N = prescale
value
Synchronous, (TCY + 20)/N
with prescaler
—
—
ns
(1, 8, 64, 256)
Asynchronous
20
—
—
—
—
ns
ns
TxCK Low Time Synchronous,
no prescaler
(TCY + 20)
Must also meet
parameterTA15.
N = prescale
value
Synchronous, (TCY + 20)/N
with prescaler
—
—
ns
(1, 8, 64, 256)
Asynchronous
20
—
—
—
—
ns
ns
TxCK Input
Period
Synchronous,
no prescaler
2 TCY + 40
—
Synchronous,
with prescaler
Greater of:
40 ns or
(2 TCY + 40)/
N
—
—
—
N = prescale
value
(1, 8, 64, 256)
Asynchronous
40
—
—
—
ns
—
—
OS60 Ft1
SOSCI/T1CK Oscillator Input
frequency Range (oscillator
enabled by setting bit TCS
(T1CON<1>))
DC
50
kHz
TA20
TCKEXTMRL Delay from External TxCK Clock
Edge to Timer Increment
0.75 TCY +
40
1.75 TCY +
40
—
—
Note 1: Timer1 is a Type A.
DS70265E-page 240
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
TABLE 24-23: TIMER2 AND TIMER4 EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min
Typ
Max
Units
Conditions
Synchronous
mode
Greater of:
20 or
(TCY + 20)/N
—
—
ns
TB10 TtxH
TB11 TtxL
TB15 TtxP
TxCKHigh
Time
Must also meet
parameter TB15
N = prescale
value
(1, 8, 64, 256)
TxCK Low Synchronous
Greater of:
20 or
(TCY + 20)/N
—
—
ns
Must also meet
parameter TB15
N = prescale
value
Time
mode
(1, 8, 64, 256)
TxCK
Input
Period
Synchronous
mode
Greater of:
40 or
(2 TCY + 40)/N
—
—
—
ns
ns
N = prescale
value
(1, 8, 64, 256)
TB20 TCKEXTMRL Delay from External TxCK 0.75 TCY + 40
1.75 TCY + 40
—
Clock Edge to Timer Incre-
ment
Note 1: These parameters are characterized, but are not tested in manufacturing.
TABLE 24-24: TIMER3 AND TIMER5 EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
TtxH
Characteristic(1)
Min
Typ
Max
Units
Conditions
TC10
TC11
TC15
TxCK High Synchronous
Time
TCY + 20
—
—
ns
Must also meet
parameter TC15
TtxL
TtxP
TxCK Low Synchronous
Time
TCY + 20
—
—
—
—
ns
ns
Must also meet
parameter TC15
TxCK Input Synchronous,
2 TCY + 40
N = prescale
value
Period
with prescaler
(1, 8, 64, 256)
TC20
TCKEXTMRL Delay from External TxCK
Clock Edge to Timer Incre-
ment
0.75 TCY + 40
—
1.75 TCY + 40
ns
—
Note 1: These parameters are characterized, but are not tested in manufacturing.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 241
dsPIC33FJ12MC201/202
FIGURE 24-6:
TIMERQ (QEI MODULE) EXTERNAL CLOCK TIMING CHARACTERISTICS
QEB
TQ11
TQ10
TQ15
TQ20
POSCNT
TABLE 24-25: QEI MODULE EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min
Typ
Max
Units
Conditions
TQ10 TtQH
TQ11 TtQL
TQ15 TtQP
TQCK High Time Synchronous,
with prescaler
TCY + 20
—
ns
Must also meet
parameter TQ15
TQCK Low Time
Synchronous,
with prescaler
TCY + 20
—
—
ns
ns
—
Must also meet
parameter TQ15
TQCP Input
Period
Synchronous, 2 * TCY + 40
with prescaler
—
TQ20
TCKEXTMRL Delay from External TxCK Clock
Edge to Timer Increment
0.5 TCY
1.5 TCY
—
Note 1: These parameters are characterized by similarity, but are not tested in manufacturing.
FIGURE 24-7:
INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS
ICx
IC10
IC11
IC15
Note: Refer to Figure 24-1 for load conditions.
DS70265E-page 242
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
TABLE 24-26: INPUT CAPTURE TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min
Max
Units
Conditions
IC10
IC11
IC15
TccL
TccH
TccP
ICx Input Low Time No Prescaler
With Prescaler
0.5 TCY + 20
10
—
—
—
—
—
ns
ns
ns
ns
ns
—
ICx Input High Time No Prescaler
With Prescaler
0.5 TCY + 20
10
—
ICx Input Period
(TCY + 40)/N
N = prescale
value (1, 4, 16)
Note 1: These parameters are characterized by similarity, but are not tested in manufacturing.
FIGURE 24-8:
OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS
OCx
(Output Compare
or PWM Mode)
OC10
OC11
Note: Refer to Figure 24-1 for load conditions.
TABLE 24-27: OUTPUT COMPARE MODULE TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min
Typ
Max
Units
Conditions
OC10 TccF
OC11 TccR
OCx Output Fall Time
OCx Output Rise Time
—
—
—
—
—
—
ns
ns
See parameter D032
See parameter D031
Note 1: These parameters are characterized by similarity, but are not tested in manufacturing.
FIGURE 24-9:
OC/PWM MODULE TIMING CHARACTERISTICS
OC20
OCFA
OC15
Tri-State
Active
OCx
© 2007-2011 Microchip Technology Inc.
DS70265E-page 243
dsPIC33FJ12MC201/202
TABLE 24-28: SIMPLE OC/PWM MODE TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min
Typ
Max
Units
Conditions
OC15
TFD
Fault Input to PWM I/O
Change
—
—
TCY + 20
ns
—
OC20
TFLT
Fault Input Pulse Width
TCY + 20
—
—
ns
—
Note 1: These parameters are characterized by similarity, but are not tested in manufacturing.
FIGURE 24-10:
MOTOR CONTROL PWM MODULE FAULT TIMING CHARACTERISTICS
MP30
FLTA
MP20
PWMx
FIGURE 24-11:
MOTOR CONTROL PWM MODULE TIMING CHARACTERISTICS
MP11 MP10
PWMx
Note: Refer to Figure 24-1 for load conditions.
DS70265E-page 244
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
TABLE 24-29: MOTOR CONTROL PWM MODULE TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min
Typ
Max
Units
Conditions
MP10
MP11
TFPWM
TRPWM
TFD
PWM Output Fall Time
PWM Output Rise Time
—
—
—
—
—
—
—
—
50
ns
ns
ns
See parameter D032
See parameter D031
—
Fault Input ↓to PWM
I/O Change
MP20
MP30
TFH
Minimum Pulse Width
50
—
—
ns
—
Note 1: These parameters are characterized by similarity, but are not tested in manufacturing.
FIGURE 24-12:
QEA/QEB INPUT CHARACTERISTICS
TQ36
QEA
(input)
TQ30
TQ31
TQ35
QEB
(input)
TQ41
TQ40
TQ30
TQ31
TQ35
QEB
Internal
© 2007-2011 Microchip Technology Inc.
DS70265E-page 245
dsPIC33FJ12MC201/202
TABLE 24-30: QUADRATURE DECODER TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Typ(2)
Max
Units
Conditions
TQ30
TQ31
TQ35
TQ36
TQ40
TQUL
Quadrature Input Low Time
Quadrature Input High Time
Quadrature Input Period
Quadrature Phase Period
6 TCY
6 TCY
—
—
—
—
—
ns
ns
ns
ns
ns
—
—
—
—
TQUH
TQUIN
TQUP
TQUFL
12 TCY
3 TCY
Filter Time to Recognize Low,
with Digital Filter
3 * N * TCY
N = 1, 2, 4, 16, 32, 64,
128 and 256 (Note 3)
TQ41
TQUFH
Filter Time to Recognize High,
with Digital Filter
3 * N * TCY
—
ns
N = 1, 2, 4, 16, 32, 64,
128 and 256 (Note 3)
Note 1: These parameters are characterized by similarity, but are not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
3: N = Index Channel Digital Filter Clock Divide Select bits. Refer to Section 15. “Quadrature Encoder
Interface (QEI)” (DS70208) in the dsPIC33F/PIC24H Family Reference Manual. Please see the
Microchip (www.microchip.com) web site for the latest family reference manual chapters.
FIGURE 24-13:
QEI MODULE INDEX PULSE TIMING CHARACTERISTICS
QEA
(input)
QEB
(input)
Ungated
Index
TQ50
TQ51
Index Internal
TQ55
Position Coun-
ter Reset
DS70265E-page 246
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
TABLE 24-31: QEI INDEX PULSE TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min
Max
Units
Conditions
TQ50
TQ51
TQ55
TqIL
Filter Time to Recognize Low,
with Digital Filter
3 * N * TCY
—
ns
N = 1, 2, 4, 16, 32, 64,
128 and 256 (Note 2)
TqiH
Tqidxr
Filter Time to Recognize High,
with Digital Filter
3 * N * TCY
3 TCY
—
—
ns
ns
N = 1, 2, 4, 16, 32, 64,
128 and 256 (Note 2)
Index Pulse Recognized to Position
Counter Reset (ungated index)
—
Note 1: These parameters are characterized by similarity, but are not tested in manufacturing.
2: Alignment of index pulses to QEA and QEB is shown for position counter Reset timing only. Shown for
forward direction only (QEA leads QEB). Same timing applies for reverse direction (QEA lags QEB) but
index pulse recognition occurs on falling edge.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 247
dsPIC33FJ12MC201/202
TABLE 24-32: SPIx MAXIMUM DATA/CLOCK RATE SUMMARY
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Master
Transmit Only
(Half-Duplex)
Master
Slave
Maximum
Data Rate
Transmit/Receive Transmit/Receive
(Full-Duplex)
CKE
CKP
SMP
(Full-Duplex)
15 MHz
9 MHz
Table 24-33
—
—
0,1
1
0,1
0,1
0,1
0
0,1
1
—
—
—
—
—
—
Table 24-34
—
9 MHz
Table 24-35
—
0
1
15 MHz
11 MHz
15 MHz
11 MHz
—
—
—
—
Table 24-36
Table 24-37
Table 24-38
Table 24-39
1
0
1
1
0
0
1
0
0
0
0
FIGURE 24-14:
SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY CKE = 0) TIMING
CHARACTERISTICS
SCKx
(CKP = 0)
SP10
SP21
SP20
SP20
SCKx
(CKP = 1)
SP35
SP21
LSb
Bit 14 - - - - - -1
MSb
SDOx
SP30, SP31
SP30, SP31
Note: Refer to Figure 24-1 for load conditions.
FIGURE 24-15:
SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY CKE = 1) TIMING
CHARACTERISTICS
SP36
SCKx
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
Bit 14 - - - - - -1
SP30, SP31
MSb
LSb
SDOx
Note: Refer to Figure 24-1 for load conditions.
DS70265E-page 248
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
TABLE 24-33: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS
AC CHARACTERISTICS
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
Param
No.
Symbol
TscP
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
See Note 3
SP10
SP20
Maximum SCK Frequency
SCKx Output Fall Time
—
—
—
—
15
—
MHz
ns
TscF
TscR
TdoF
TdoR
See parameter DO32
and Note 4
SP21
SP30
SP31
SP35
SP36
SCKx Output Rise Time
—
—
—
—
30
—
—
—
6
—
—
—
20
—
ns
ns
ns
ns
ns
See parameter DO31
and Note 4
SDOx Data Output Fall Time
SDOx Data Output Rise Time
See parameter DO32
and Note 4
See parameter DO31
and Note 4
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
—
TdiV2scH, SDOx Data Output Setup to
—
TdiV2scL
First SCKx Edge
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
3: The minimum clock period for SCKx is 66.7 ns. Therefore, the clock generated in Master mode must not
violate this specification.
4: Assumes 50 pF load on all SPIx pins.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 249
dsPIC33FJ12MC201/202
FIGURE 24-16:
SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = X, SMP = 1) TIMING
CHARACTERISTICS
SP36
SCKx
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
Bit 14 - - - - - -1
SP30, SP31
MSb
LSb
SDOx
SDIx
SP40
MSb In
SP41
LSb In
Bit 14 - - - -1
Note: Refer to Figure 24-1 for load conditions.
TABLE 24-34: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING
REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
Param
No.
Symbol
TscP
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
See Note 3
SP10
SP20
Maximum SCK Frequency
SCKx Output Fall Time
—
—
—
—
9
MHz
ns
TscF
TscR
TdoF
TdoR
—
See parameter DO32
and Note 4
SP21
SP30
SP31
SP35
SP36
SP40
SP41
SCKx Output Rise Time
—
—
—
—
30
30
30
—
—
—
6
—
—
—
20
—
—
—
ns
ns
ns
ns
ns
ns
ns
See parameter DO31
and Note 4
SDOx Data Output Fall Time
SDOx Data Output Rise Time
See parameter DO32
and Note 4
See parameter DO31
and Note 4
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
—
—
—
TdoV2sc, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
—
—
—
TdiV2scH, Setup Time of SDIx Data
TdiV2scL Input to SCKx Edge
TscH2diL, Hold Time of SDIx Data Input
TscL2diL
to SCKx Edge
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
3: The minimum clock period for SCKx is 111 ns. The clock generated in Master mode must not violate this
specification.
4: Assumes 50 pF load on all SPIx pins.
DS70265E-page 250
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
FIGURE 24-17:
SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = X, SMP = 1) TIMING
CHARACTERISTICS
SCKx
(CKP = 0)
SP10
SP21
SP20
SP20
SCKx
(CKP = 1)
SP35
SP21
LSb
Bit 14 - - - - - -1
MSb
SDOx
SDIx
SP30, SP31
MSb In
SP30, SP31
LSb In
Bit 14 - - - -1
SP40
SP41
Note: Refer to Figure 24-1 for load conditions.
TABLE 24-35: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING
REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
Param
No.
Symbol
TscP
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
-40ºC to +125ºC and
SP10
Maximum SCK Frequency
—
—
9
MHz
see Note 3
SP20
SP21
SP30
SP31
SP35
SP36
SP40
SP41
TscF
TscR
TdoF
TdoR
SCKx Output Fall Time
—
—
—
—
—
30
30
30
—
—
—
—
6
—
—
—
—
20
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
See parameter DO32
and Note 4
SCKx Output Rise Time
SDOx Data Output Fall Time
SDOx Data Output Rise Time
See parameter DO31
and Note 4
See parameter DO32
and Note 4
See parameter DO31
and Note 4
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
—
—
—
TdoV2scH, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
—
—
—
TdiV2scH, Setup Time of SDIx Data
TdiV2scL Input to SCKx Edge
TscH2diL, Hold Time of SDIx Data Input
TscL2diL
to SCKx Edge
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
3: The minimum clock period for SCKx is 111 ns. The clock generated in Master mode must not violate this
specification.
4: Assumes 50 pF load on all SPIx pins.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 251
dsPIC33FJ12MC201/202
FIGURE 24-18:
SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING
CHARACTERISTICS
SP60
SSx
SP52
SP50
SCKx
(CKP = 0)
SP70
SP72
SP73
SP73
SCKx
(CKP = 1)
SP35
SP72
LSb
MSb
Bit 14 - - - - - -1
SDOx
SDIx
SP30,SP31
Bit 14 - - - -1
SP51
MSb In
SP41
LSb In
SP40
Note: Refer to Figure 24-1 for load conditions.
DS70265E-page 252
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
TABLE 24-36: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING
REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
Param
No.
Symbol
TscP
Characteristic(1)
Min
Typ(2) Max Units
Conditions
See Note 3
SP70
SP72
Maximum SCK Input Frequency
SCKx Input Fall Time
—
—
—
—
15
—
MHz
ns
TscF
TscR
TdoF
TdoR
See parameterDO32
and Note 4
SP73
SP30
SP31
SP35
SP36
SP40
SCKx Input Rise Time
—
—
—
—
30
30
—
—
—
6
—
—
—
20
—
—
ns
ns
ns
ns
ns
ns
See parameter DO31
and Note 4
SDOx Data Output Fall Time
SDOx Data Output Rise Time
See parameter DO32
and Note 4
See parameter DO31
and Note 4
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
—
—
TdoV2scH, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
—
—
TdiV2scH, Setup Time of SDIx Data Input
TdiV2scL
TscH2diL, Hold Time of SDIx Data Input
TscL2diL to SCKx Edge
to SCKx Edge
SP41
SP50
SP51
SP52
SP60
30
—
—
—
—
—
—
—
50
—
50
ns
ns
ns
ns
ns
—
—
TssL2scH, SSx ↓to SCKx ↑ or SCKx Input
TssL2scL
120
TssH2doZ SSx ↑ to SDOx Output
10
1.5 TCY + 40
—
—
High-Impedance(4)
See Note 4
TscH2ssH SSx after SCKx Edge
TscL2ssH
TssL2doV SDOx Data Output Valid after
SSx Edge
—
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
3: The minimum clock period for SCKx is 66.7 ns. Therefore, the SCK clock generated by the Master must
not violate this specification.
4: Assumes 50 pF load on all SPIx pins.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 253
dsPIC33FJ12MC201/202
FIGURE 24-19:
SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING
CHARACTERISTICS
SP60
SSx
SP52
SP50
SCKx
(CKP = 0)
SP72
SP73
SP70
SP73
SCKx
(CKP = 1)
SP35
SP72
LSb
SP52
Bit 14 - - - - - -1
MSb
SDOx
SDIx
SP30,SP31
Bit 14 - - - -1
SP51
MSb In
SP41
LSb In
SP40
Note: Refer to Figure 24-1 for load conditions.
DS70265E-page 254
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
TABLE 24-37: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING
REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
Param
No.
Symbol
TscP
Characteristic(1)
Min
Typ(2) Max Units
Conditions
See Note 3
SP70
SP72
Maximum SCK Input Frequency
SCKx Input Fall Time
—
—
—
—
11
—
MHz
ns
TscF
TscR
TdoF
TdoR
See parameterDO32
and Note 4
SP73
SP30
SP31
SP35
SP36
SP40
SP41
SCKx Input Rise Time
—
—
—
—
30
30
30
—
—
—
6
—
—
—
20
—
—
—
ns
ns
ns
ns
ns
ns
ns
See parameter DO31
and Note 4
SDOx Data Output Fall Time
SDOx Data Output Rise Time
See parameter DO32
and Note 4
See parameter DO31
and Note 4
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
—
—
—
TdoV2scH, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
—
—
—
TdiV2scH, Setup Time of SDIx Data Input
TdiV2scL
TscH2diL, Hold Time of SDIx Data Input
TscL2diL to SCKx Edge
to SCKx Edge
SP50
SP51
SP52
SP60
TssL2scH, SSx ↓to SCKx ↑ or SCKx Input
120
—
—
—
—
—
50
—
50
ns
ns
ns
ns
—
—
TssL2scL
TssH2doZ SSx ↑ to SDOx Output
10
1.5 TCY + 40
—
High-Impedance(4)
See Note 4
TscH2ssH SSx after SCKx Edge
TscL2ssH
TssL2doV SDOx Data Output Valid after
SSx Edge
—
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
3: The minimum clock period for SCKx is 91 ns. Therefore, the SCK clock generated by the Master must not
violate this specification.
4: Assumes 50 pF load on all SPIx pins.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 255
dsPIC33FJ12MC201/202
FIGURE 24-20:
SPIx SLAVE MODE (FULL-DUPLEX CKE = 0, CKP = 1, SMP = 0) TIMING
CHARACTERISTICS
SSX
SP52
SP50
SCKX
(CKP = 0)
SP70
SP72
SP73
SP72
SCKX
(CKP = 1)
SP73
LSb
SP35
MSb
Bit 14 - - - - - -1
SDOX
SDIX
SP51
SP30,SP31
Bit 14 - - - -1
MSb In
LSb In
SP41
SP40
Note: Refer to Figure 24-1 for load conditions.
DS70265E-page 256
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
TABLE 24-38: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING
REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
Param
No.
Symbol
TscP
Characteristic(1)
Min
Typ(2) Max Units
Conditions
See Note 3
SP70
SP72
Maximum SCK Input Frequency
SCKx Input Fall Time
—
—
—
—
15
—
MHz
ns
TscF
TscR
TdoF
TdoR
See parameterDO32
and Note 4
SP73
SP30
SP31
SP35
SP36
SP40
SP41
SCKx Input Rise Time
—
—
—
—
30
30
30
—
—
—
6
—
—
—
20
—
—
—
ns
ns
ns
ns
ns
ns
ns
See parameter DO31
and Note 4
SDOx Data Output Fall Time
SDOx Data Output Rise Time
See parameter DO32
and Note 4
See parameter DO31
and Note 4
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
—
—
—
TdoV2scH, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
—
—
—
TdiV2scH, Setup Time of SDIx Data Input
TdiV2scL
TscH2diL, Hold Time of SDIx Data Input
TscL2diL to SCKx Edge
to SCKx Edge
SP50
SP51
SP52
TssL2scH, SSx ↓to SCKx ↑ or SCKx Input
120
10
—
—
—
—
50
—
ns
ns
ns
—
—
TssL2scL
TssH2doZ SSx ↑ to SDOx Output
High-Impedance(4)
See Note 4
TscH2ssH SSx after SCKx Edge
TscL2ssH
1.5 TCY + 40
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
3: The minimum clock period for SCKx is 66.7 ns. Therefore, the SCK clock generated by the Master must
not violate this specification.
4: Assumes 50 pF load on all SPIx pins.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 257
dsPIC33FJ12MC201/202
FIGURE 24-21:
SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING
CHARACTERISTICS
SSX
SP52
SP50
SCKX
(CKP = 0)
SP70
SP72
SP73
SP72
SCKX
(CKP = 1)
SP73
LSb
SP35
MSb
SDOX
SDIX
Bit 14 - - - - - -1
SP51
SP30,SP31
Bit 14 - - - -1
MSb In
LSb In
SP41
SP40
Note: Refer to Figure 24-1 for load conditions.
DS70265E-page 258
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
TABLE 24-39: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING
REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
Param
No.
Symbol
TscP
Characteristic(1)
Min
Typ(2) Max Units
Conditions
See Note 3
SP70
SP72
Maximum SCK Input Frequency
SCKx Input Fall Time
—
—
—
—
11
—
MHz
ns
TscF
TscR
TdoF
TdoR
See parameterDO32
and Note 4
SP73
SP30
SP31
SP35
SP36
SP40
SP41
SCKx Input Rise Time
—
—
—
—
30
30
30
—
—
—
6
—
—
—
20
—
—
—
ns
ns
ns
ns
ns
ns
ns
See parameter DO31
and Note 4
SDOx Data Output Fall Time
SDOx Data Output Rise Time
See parameter DO32
and Note 4
See parameter DO31
and Note 4
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
—
—
—
TdoV2scH, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
—
—
—
TdiV2scH, Setup Time of SDIx Data Input
TdiV2scL
TscH2diL, Hold Time of SDIx Data Input
TscL2diL to SCKx Edge
to SCKx Edge
SP50
SP51
SP52
TssL2scH, SSx ↓to SCKx ↑ or SCKx Input
120
10
—
—
—
—
50
—
ns
ns
ns
—
—
TssL2scL
TssH2doZ SSx ↑ to SDOx Output
High-Impedance(4)
See Note 4
TscH2ssH SSx after SCKx Edge
TscL2ssH
1.5 TCY + 40
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
3: The minimum clock period for SCKx is 91 ns. Therefore, the SCK clock generated by the Master must not
violate this specification.
4: Assumes 50 pF load on all SPIx pins.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 259
dsPIC33FJ12MC201/202
FIGURE 24-22:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)
SCLx
IM31
IM34
IM30
IM33
SDAx
Stop
Condition
Start
Condition
Note: Refer to Figure 24-1 for load conditions.
FIGURE 24-23:
I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE)
IM20
IM21
IM11
IM10
SCLx
IM11
IM26
IM10
IM33
IM25
SDAx
In
IM45
IM40
IM40
SDAx
Out
Note: Refer to Figure 24-1 for load conditions.
DS70265E-page 260
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
TABLE 24-40: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(3)
Min(1)
Max
Units
Conditions
IM10
IM11
IM20
IM21
IM25
IM26
IM30
IM31
IM33
IM34
IM40
IM45
TLO:SCL Clock Low Time 100 kHz mode TCY/2 (BRG + 1)
400 kHz mode TCY/2 (BRG + 1)
—
—
μs
μs
μs
μs
μs
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
ns
ns
ns
ns
ns
ns
μs
μs
μs
pF
ns
—
—
—
—
—
—
1 MHz mode(2) TCY/2 (BRG + 1)
—
THI:SCL Clock High Time 100 kHz mode TCY/2 (BRG + 1)
—
400 kHz mode TCY/2 (BRG + 1)
1 MHz mode(2) TCY/2 (BRG + 1)
—
—
TF:SCL
TR:SCL
SDAx and SCLx 100 kHz mode
—
300
300
100
1000
300
300
—
CB is specified to be
from 10 to 400 pF
Fall Time
400 kHz mode
1 MHz mode(2)
20 + 0.1 CB
—
SDAx and SCLx 100 kHz mode
—
CB is specified to be
from 10 to 400 pF
Rise Time
400 kHz mode
1 MHz mode(2)
100 kHz mode
400 kHz mode
1 MHz mode(2)
100 kHz mode
400 kHz mode
1 MHz mode(2)
20 + 0.1 CB
—
250
100
40
0
TSU:DAT Data Input
Setup Time
—
—
—
—
THD:DAT Data Input
Hold Time
—
0
0.9
—
0.2
TSU:STA Start Condition 100 kHz mode TCY/2 (BRG + 1)
—
Only relevant for
Repeated Start
condition
Setup Time
400 kHz mode TCY/2 (BRG + 1)
1 MHz mode(2) TCY/2 (BRG + 1)
—
—
THD:STA Start Condition 100 kHz mode TCY/2 (BRG + 1)
—
After this period the
first clock pulse is
generated
Hold Time
400 kHz mode TCY/2 (BRG + 1)
1 MHz mode(2) TCY/2 (BRG + 1)
—
—
TSU:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1)
—
—
Setup Time
400 kHz mode TCY/2 (BRG + 1)
1 MHz mode(2) TCY/2 (BRG + 1)
—
—
THD:STO Stop Condition
Hold Time
100 kHz mode TCY/2 (BRG + 1)
400 kHz mode TCY/2 (BRG + 1)
1 MHz mode(2) TCY/2 (BRG + 1)
—
—
—
—
TAA:SCL Output Valid
From Clock
100 kHz mode
400 kHz mode
1 MHz mode(2)
—
—
3500
1000
400
—
—
—
—
—
TBF:SDA Bus Free Time 100 kHz mode
400 kHz mode
4.7
1.3
0.5
—
Time the bus must be
free before a new
transmission can start
—
1 MHz mode(2)
—
IM50
IM51
CB
Bus Capacitive Loading
400
—
PGD
Pulse Gobbler Delay
65
390
See Note 4
Note 1: BRG is the value of the I2C Baud Rate Generator. Refer to Section 19. “Inter-Integrated Circuit (I2C™)”
(DS70195) in the “dsPIC33F/PIC24H Family Reference Manual”. Please see the Microchip web site
(www.microchip.com) for the latest family reference manual sections.
2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
3: These parameters are characterized by similarity, but are not tested in manufacturing.
4: Typical value for this parameter is 130 ns.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 261
dsPIC33FJ12MC201/202
FIGURE 24-24:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)
SCLx
IS34
IS31
IS30
IS33
SDAx
Stop
Condition
Start
Condition
FIGURE 24-25:
I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)
IS20
IS21
IS11
IS10
SCLx
IS30
IS26
IS31
IS33
IS25
SDAx
In
IS45
IS40
IS40
SDAx
Out
DS70265E-page 262
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
TABLE 24-41: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param. Symbol
Characteristic(2)
Min
Max
Units
Conditions
IS10
IS11
TLO:SCL Clock Low Time 100 kHz mode
4.7
—
μs
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
1.3
—
μs
Device must operate at a
minimum of 10 MHz
1 MHz mode(1)
0.5
4.0
—
—
μs
μs
—
THI:SCL Clock High Time 100 kHz mode
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
1 MHz mode(1)
0.6
—
μs
Device must operate at a
minimum of 10 MHz
0.5
—
300
300
100
1000
300
300
—
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
ns
ns
ns
ns
ns
ns
μs
μs
μs
pF
—
IS20
IS21
IS25
IS26
IS30
IS31
IS33
IS34
IS40
IS45
IS50
TF:SCL
SDAx and SCLx 100 kHz mode
—
CB is specified to be from
10 to 400 pF
Fall Time
400 kHz mode
1 MHz mode(1)
20 + 0.1 CB
—
—
TR:SCL SDAx and SCLx 100 kHz mode
CB is specified to be from
10 to 400 pF
Rise Time
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
20 + 0.1 CB
—
TSU:DAT Data Input
Setup Time
250
100
100
0
—
—
—
—
THD:DAT Data Input
Hold Time
—
0
0.9
0.3
—
0
TSU:STA Start Condition
Setup Time
4.7
0.6
0.25
4.0
0.6
0.25
4.7
0.6
0.6
4000
600
250
0
Only relevant for Repeated
Start condition
—
—
THD:STA Start Condition
Hold Time
—
After this period, the first
clock pulse is generated
—
—
TSU:STO Stop Condition
Setup Time
—
—
—
—
—
—
THD:ST Stop Condition
O
—
Hold Time
—
TAA:SCL Output Valid
From Clock
3500
1000
350
—
0
0
TBF:SDA Bus Free Time
4.7
1.3
0.5
—
Time the bus must be free
before a new transmission
can start
—
—
CB
Bus Capacitive Loading
400
—
Note 1: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
2: These parameters are characterized by similarity, but are not tested in manufacturing.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 263
dsPIC33FJ12MC201/202
TABLE 24-42: ADC MODULE SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min.
Typ
Max.
Units
Conditions
Device Supply
AD01
AVDD
Module VDD Supply(2)
Module VSS Supply(2)
Greater of
VDD – 0.3
or 3.0
—
—
Lesser of
VDD + 0.3
or 3.6
V
V
—
—
AD02
AVSS
VSS – 0.3
VSS + 0.3
Reference Inputs
AD05
VREFH
Reference Voltage High AVSS + 2.5
3.0
—
—
AVDD
3.6
V
V
See Note 1
AD05a
VREFH = AVDD
VREFL = AVSS = 0, see Note 2
AD06
VREFL
Reference Voltage Low
AVSS
0
—
—
AVDD – 2.5
0
V
V
See Note 1
AD06a
VREFH = AVDD
VREFL = AVSS = 0, see Note 2
AD07
AD08
VREF
IREF
Absolute Reference
Voltage(2)
2.5
—
3.6
V
VREF = VREFH - VREFL
Current Drain
—
—
250
—
550
10
μA ADC operating, See Note 1
μA ADC off, See Note 1
AD08a IAD
Operating Current
—
—
7.0
2.7
9.0
3.2
mA 10-bit ADC mode, See Note 2
mA 12-bit ADC mode, See Note 2
Analog Input
AD12
AD13
AD17
VINH
Input Voltage Range
VINH
VINL
—
VREFH
V
This voltage reflects Sample
and Hold Channels 0, 1, 2,
and 3 (CH0-CH3), positive
input
(2)
VINL
RIN
Input Voltage Range
VREFL
—
AVSS + 1V
V
This voltage reflects Sample
and Hold Channels 0, 1, 2,
and 3 (CH0-CH3), negative
input
(2)
VINL
Recommended Imped-
ance of Analog Voltage
Source(3)
—
—
—
—
200
200
Ω
Ω
10-bit ADC
12-bit ADC
Note 1: These parameters are not characterized or tested in manufacturing.
2: These parameters are characterized, but are not tested in manufacturing.
3: These parameters are assured by design, but are not characterized or tested in manufacturing.
DS70265E-page 264
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
TABLE 24-43: ADC MODULE SPECIFICATIONS (12-BIT MODE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min.
Typ
Max. Units
Conditions
ADC Accuracy (12-bit Mode) – Measurements with external VREF+/VREF-(3)
AD20a Nr
AD21a INL
Resolution(4)
12 data bits
—
bits
—
Integral Nonlinearity
-2
>-1
—
+2
<1
10
5.0
—
LSb VINL = AVSS = VREFL = 0V, AVDD
= VREFH = 3.6V
AD22a DNL
Differential Nonlinearity
Gain Error
—
3.4
0.9
—
LSb VINL = AVSS = VREFL = 0V, AVDD
= VREFH = 3.6V
AD23a
AD24a
AD25a
GERR
EOFF
—
LSb VINL = AVSS = VREFL = 0V, AVDD
= VREFH = 3.6V
Offset Error
—
LSb VINL = AVSS = VREFL = 0V, AVDD
= VREFH = 3.6V
Monotonicity
—
—
Guaranteed(1)
ADC Accuracy (12-bit Mode) – Measurements with internal VREF+/VREF-(3)
AD20a Nr
AD21a INL
AD22a DNL
Resolution(4)
12 data bits
bits
—
Integral Nonlinearity
Differential Nonlinearity
Gain Error
-2
>-1
2
—
—
+2
<1
20
10
—
LSb VINL = AVSS = 0V, AVDD = 3.6V
LSb VINL = AVSS = 0V, AVDD = 3.6V
LSb VINL = AVSS = 0V, AVDD = 3.6V
LSb VINL = AVSS = 0V, AVDD = 3.6V
AD23a
AD24a
AD25a
GERR
EOFF
—
10.5
3.8
—
Offset Error
2
Monotonicity
—
—
Guaranteed(1)
Dynamic Performance (12-bit Mode)(2)
AD30a THD
Total Harmonic Distortion
—
—
-75
—
dB
dB
—
—
AD31a SINAD
Signal to Noise and
Distortion
68.5
69.5
AD32a SFDR
Spurious Free Dynamic
Range
80
—
—
dB
—
AD33a
FNYQ
Input Signal Bandwidth
Effective Number of Bits
—
—
250
—
kHz
bits
—
—
AD34a ENOB
11.09
11.3
Note 1: The A/D conversion result never decreases with an increase in the input voltage, and has no missing
codes.
2: These parameters are characterized by similarity, but are not tested in manufacturing.
3: These parameters are characterized, but are tested at 20 ksps only.
4: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 265
dsPIC33FJ12MC201/202
TABLE 24-44: ADC MODULE SPECIFICATIONS (10-BIT MODE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min.
Typ
Max. Units
Conditions
ADC Accuracy (10-bit Mode) – Measurements with external VREF+/VREF-(3)
AD20b Nr
AD21b INL
Resolution(4)
10 data bits
—
bits
—
Integral Nonlinearity
-1.5
>-1
—
+1.5
<1
6
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
AD22b DNL
Differential Nonlinearity
Gain Error
—
3
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
AD23b
AD24b
AD25b
GERR
EOFF
—
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
Offset Error
—
2
5
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
Monotonicity
—
—
—
—
Guaranteed(1)
ADC Accuracy (10-bit Mode) – Measurements with internal VREF+/VREF-(3)
AD20b Nr
AD21b INL
AD22b DNL
Resolution(4)
10 data bits
bits
—
Integral Nonlinearity
Differential Nonlinearity
Gain Error
-1
>-1
—
—
—
7
+1
<1
15
7
LSb VINL = AVSS = 0V, AVDD = 3.6V
LSb VINL = AVSS = 0V, AVDD = 3.6V
LSb VINL = AVSS = 0V, AVDD = 3.6V
LSb VINL = AVSS = 0V, AVDD = 3.6V
AD23b
AD24b
AD25b
GERR
EOFF
—
Offset Error
—
3
Monotonicity
—
—
—
—
Guaranteed(1)
Dynamic Performance (10-bit Mode)(2)
AD30b THD
Total Harmonic Distortion
—
—
-64
—
dB
dB
—
—
AD31b SINAD
Signal to Noise and
Distortion
57
58.5
AD32b SFDR
Spurious Free Dynamic
Range
72
—
—
dB
—
AD33b
FNYQ
Input Signal Bandwidth
Effective Number of Bits
—
—
550
—
kHz
bits
—
—
AD34b ENOB
9.16
9.4
Note 1: The A/D conversion result never decreases with an increase in the input voltage, and has no missing
codes.
2: These parameters are characterized by similarity, but are not tested in manufacturing.
3: These parameters are characterized, but are tested at 20 ksps only.
4: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts.
DS70265E-page 266
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
FIGURE 24-26:
ADC CONVERSION (12-BIT MODE) TIMING CHARACTERISTICS
(ASAM = 0, SSRC<2:0> = 000)
AD50
ADCLK
Instruction
Execution
Set SAMP
AD61
Clear SAMP
SAMP
AD60
TSAMP
AD55
DONE
ADxIF
1
2
3
4
5
6
7
8
9
– Software sets ADxCON. SAMP to start sampling.
– Convert bit 11.
– Convert bit 10.
– Convert bit 1.
– Convert bit 0.
1
2
5
6
7
8
9
– Sampling starts after discharge period. TSAMP is described in
Section 16. “Analog-to-Digital Converter (ADC)” (DS70183) in the
“dsPIC33F/PIC24H Family Reference Manual”.
– Software clears ADxCON. SAMP to start conversion.
– Sampling ends, conversion sequence starts.
3
4
– One TAD for end of conversion.
TABLE 24-45: ADC CONVERSION (12-BIT MODE) TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min.
Typ(2) Max.
Units
Conditions
Clock Parameters(1)
AD50
AD51
TAD
tRC
ADC Clock Period
117.6
—
—
—
—
ns
ns
—
—
ADC Internal RC Oscillator
Period
250
Conversion Rate
AD55
AD56
AD57
tCONV
FCNV
Conversion Time
Throughput Rate
Sample Time
—
—
14 TAD
ns
Ksps
—
—
—
—
—
—
500
—
TSAMP
3.0 TAD
Timing Parameters
AD60
tPCS
2.0 TAD
—
3.0 TAD
—
Auto-convert trigger not
selected
Conversion Start from Sample
Trigger(2)
AD61
AD62
AD63
tPSS
tCSS
tDPU
Sample Start from Setting
Sample (SAMP) bit(2)
2.0 TAD
—
—
0.5 TAD
—
3.0 TAD
—
—
—
μs
—
—
—
Conversion Completion to
Sample Start (ASAM = 1)(2)
Time to Stabilize Analog Stage
from ADC Off to ADC On(2)
—
20
Note 1: Because the sample caps will eventually lose charge, clock rates below 10 kHz may affect linearity
performance, especially at elevated temperatures.
2: These parameters are characterized but not tested in manufacturing.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 267
dsPIC33FJ12MC201/202
FIGURE 24-27:
ADC CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS
(CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000)
AD50
Set SAMP
AD61
ADCLK
Instruction
Execution
Clear SAMP
AD60
SAMP
TSAMP
AD55
AD55
DONE
ADxIF
1
2
3
4
5
6
7
8
5
6
7
8
– Software sets ADxCON. SAMP to start sampling.
1
2
– Sampling starts after discharge period. TSAMP is described in Section 16. “Analog-to-Digital Converter (ADC)”
(DS70183) in the “dsPIC33F/PIC24H Family Reference Manual”.
– Software clears ADxCON. SAMP to start conversion.
– Sampling ends, conversion sequence starts.
– Convert bit 9.
3
4
5
6
7
8
– Convert bit 8.
– Convert bit 0.
– One TAD for end of conversion.
FIGURE 24-28:
ADC CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01,
SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001)
AD50
ADCLK
Instruction
Set ADON
Execution
SAMP
ADxIF
TSAMP
TSAMP
AD55
AD55
AD55
DONE
1
2
3
4
5
6
7
3
4
5
6
8
– Software sets ADxCON. ADON to start AD operation.
– Convert bit 0.
5
1
2
– Sampling starts after discharge period. TSAMP is described in
Section 16. “Analog-to-Digital Converter (ADC)” (DS70183)
in the 'dsPIC33F/PIC24H Family Reference Manual”.
– One TAD for end of conversion.
– Begin conversion of next channel.
6
7
8
– Convert bit 9.
3
4
– Sample for time specified by SAMC<4:0>.
– Convert bit 8.
DS70265E-page 268
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
TABLE 24-46: ADC CONVERSION (10-BIT MODE) TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min.
Typ(1)
Max.
Units
Conditions
Clock Parameters(2)
AD50 TAD
AD51 tRC
ADC Clock Period
76
—
—
—
—
ns
ns
—
—
ADC Internal RC Oscillator Period
250
Conversion Rate
AD55 tCONV
AD56 FCNV
Conversion Time
Throughput Rate
—
—
12 TAD
—
1.1
—
—
Msps
—
—
—
—
—
—
AD57 TSAMP Sample Time
2.0 TAD
Timing Parameters
AD60 tPCS
Conversion Start from Sample
2.0 TAD
—
3.0 TAD
—
Auto-Convert Trigger
(SSRC<2:0> = 111) not
selected
Trigger(1)
AD61 tPSS
AD62 tCSS
AD63 tDPU
Sample Start from Setting
Sample (SAMP) bit(1)
2.0 TAD
—
—
0.5 TAD
—
3.0 TAD
—
—
—
μs
—
—
—
Conversion Completion to
Sample Start (ASAM = 1)(1)
Time to Stabilize Analog Stage
from ADC Off to ADC On(1)
—
20
Note 1: These parameters are characterized but not tested in manufacturing.
2: Because the sample caps will eventually lose charge, clock rates below 10 kHz may affect linearity
performance, especially at elevated temperatures.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 269
dsPIC33FJ12MC201/202
NOTES:
DS70265E-page 270
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
25.0 PACKAGING INFORMATION
25.1 Package Marking Information
20-Lead PDIP
Example
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
dsPIC33FJ12MC
e
3
201-E/P
0730235
20-Lead SSOP
Example
XXXXXXXXXXX
XXXXXXXXXXX
dsPIC33FJ12
MC201-ISS
e
3
YYWWNNN
0730235
20-Lead SOIC
Example
dsPIC33FJ12
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
e
3
MC201-ISO
0610017
YYWWNNN
28-Lead SPDIP
Example
dsPIC33FJ12MC
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
202-E/SP
e3
YYWWNNN
0730235
28-Lead SOIC
Example
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
dsPIC33FJ12MC
202-E/SO
e
3
0730235
YYWWNNN
Legend: XX...X Customer-specific information
Y
YY
WW
NNN
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
e
3
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: If the full Microchip part number cannot be marked on one line, it is carried over to the next
line, thus limiting the number of available characters for customer-specific information.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 271
dsPIC33FJ12MC201/202
25.1 Package Marking Information (Continued)
28-Lead SSOP
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
33FJ12MC
202-E/SS
e
3
YYWWNNN
0730235
28-Lead QFN
Example
XXXXXXXX
XXXXXXXX
YYWWNNN
33FJJ12MC
202EML
0730235
e
3
Legend: XX...X Customer-specific information
Y
YY
WW
NNN
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
e
3
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e
3
Note: If the full Microchip part number cannot be marked on one line, it is carried over to the next
line, thus limiting the number of available characters for customer-specific information.
DS70265E-page 272
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
25.2 Package Details
20-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
N
E1
NOTE 1
1
2
3
D
E
A2
A
L
c
A1
b1
eB
e
b
Units
Dimension Limits
INCHES
NOM
20
.100 BSC
–
MIN
MAX
Number of Pins
Pitch
N
e
A
Top to Seating Plane
–
.210
.195
–
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
Tip to Seating Plane
Lead Thickness
Upper Lead Width
A2
A1
E
E1
D
L
c
b1
b
eB
.115
.015
.300
.240
.980
.115
.008
.045
.014
–
.130
–
.310
.250
1.030
.130
.010
.060
.018
–
.325
.280
1.060
.150
.015
.070
.022
.430
Lower Lead Width
Overall Row Spacing §
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-019B
© 2007-2011 Microchip Technology Inc.
DS70265E-page 273
dsPIC33FJ12MC201/202
20-Lead Plastic Shrink Small Outline (SS) – 5.30 mm Body [SSOP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
N
E
E1
NOTE 1
1
2
e
b
c
A2
A
φ
A1
L1
L
Units
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
Number of Pins
Pitch
N
e
20
0.65 BSC
Overall Height
Molded Package Thickness
Standoff
Overall Width
Molded Package Width
Overall Length
Foot Length
Footprint
Lead Thickness
Foot Angle
A
–
–
1.75
–
7.80
5.30
7.20
0.75
1.25 REF
–
2.00
1.85
–
8.20
5.60
7.50
0.95
A2
A1
E
E1
D
L
L1
c
1.65
0.05
7.40
5.00
6.90
0.55
0.09
0°
0.25
8°
φ
4°
Lead Width
b
0.22
–
0.38
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.20 mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-072B
DS70265E-page 274
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
© 2007-2011 Microchip Technology Inc.
DS70265E-page 275
dsPIC33FJ12MC201/202
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS70265E-page 276
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
© 2007-2011 Microchip Technology Inc.
DS70265E-page 277
dsPIC33FJ12MC201/202
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS70265E-page 278
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
28-Lead Skinny Plastic Dual In-Line (SP) – 300 mil Body [SPDIP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
N
NOTE 1
E1
1
2 3
D
E
A2
A
L
c
b1
A1
b
e
eB
Units
Dimension Limits
INCHES
NOM
28
.100 BSC
–
MIN
MAX
Number of Pins
Pitch
N
e
A
Top to Seating Plane
–
.200
.150
–
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
Tip to Seating Plane
Lead Thickness
Upper Lead Width
A2
A1
E
E1
D
L
c
b1
b
eB
.120
.015
.290
.240
1.345
.110
.008
.040
.014
–
.135
–
.310
.285
1.365
.130
.010
.050
.018
–
.335
.295
1.400
.150
.015
.070
.022
.430
Lower Lead Width
Overall Row Spacing §
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-070B
© 2007-2011 Microchip Technology Inc.
DS70265E-page 279
dsPIC33FJ12MC201/202
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇꢎꢏꢐꢌꢑꢒꢇꢎꢓꢅꢉꢉꢇꢔꢕꢋꢉꢌꢑꢄꢇꢖꢎꢎꢗꢇMꢇꢘꢙꢚꢛꢇꢓꢓꢇꢜ ꢆ!ꢇ"ꢎꢎꢔꢈ#
$ ꢋꢄ% 2ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢐꢆꢌ3ꢆꢓꢈꢅ#ꢉꢆ*ꢃꢄꢓ!(ꢅꢐꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢑꢃꢌꢉꢋꢌꢍꢃꢐꢅꢂꢆꢌ3ꢆꢓꢃꢄꢓꢅꢕꢐꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ
ꢍ&&ꢐ144***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢐꢁꢌꢋ'4ꢐꢆꢌ3ꢆꢓꢃꢄꢓ
D
N
E
E1
1
2
b
NOTE 1
e
c
A2
A
φ
A1
L
L1
5ꢄꢃ&!
ꢑꢙ66ꢙꢑ+ꢗ+ꢘꢕ
ꢏꢃ'ꢈꢄ!ꢃꢋꢄꢅ6ꢃ'ꢃ&!
ꢑꢙ7
78ꢑ
ꢑꢔ9
7"')ꢈꢉꢅꢋ%ꢅꢂꢃꢄ!
ꢂꢃ&ꢌꢍ
7
ꢈ
ꢎ:
ꢒꢁꢚ.ꢅ/ꢕ0
8 ꢈꢉꢆꢇꢇꢅ;ꢈꢃꢓꢍ&
ꢑꢋꢇ#ꢈ#ꢅꢂꢆꢌ3ꢆꢓꢈꢅꢗꢍꢃꢌ3ꢄꢈ!!
ꢕ&ꢆꢄ#ꢋ%%ꢅ
8 ꢈꢉꢆꢇꢇꢅ=ꢃ#&ꢍ
ꢑꢋꢇ#ꢈ#ꢅꢂꢆꢌ3ꢆꢓꢈꢅ=ꢃ#&ꢍ
8 ꢈꢉꢆꢇꢇꢅ6ꢈꢄꢓ&ꢍ
2ꢋꢋ&ꢅ6ꢈꢄꢓ&ꢍ
2ꢋꢋ&ꢐꢉꢃꢄ&
6ꢈꢆ#ꢅꢗꢍꢃꢌ3ꢄꢈ!!
2ꢋꢋ&ꢅꢔꢄꢓꢇꢈ
ꢔ
M
M
ꢀꢁꢛ.
M
ꢛꢁ:ꢒ
.ꢁ,ꢒ
ꢀꢒꢁꢎꢒ
ꢒꢁꢛ.
ꢀꢁꢎ.ꢅꢘ+2
M
ꢎꢁꢒꢒ
ꢀꢁ:.
M
:ꢁꢎꢒ
.ꢁꢚꢒ
ꢀꢒꢁ.ꢒ
ꢒꢁꢜ.
ꢔꢎ
ꢔꢀ
+
+ꢀ
ꢏ
6
6ꢀ
ꢌ
ꢀꢁꢚ.
ꢒꢁꢒ.
ꢛꢁꢖꢒ
.ꢁꢒꢒ
ꢜꢁꢜꢒ
ꢒꢁ..
ꢒꢁꢒꢜ
ꢒꢝ
ꢒꢁꢎ.
:ꢝ
ꢀ
ꢖꢝ
6ꢈꢆ#ꢅ=ꢃ#&ꢍ
)
ꢒꢁꢎꢎ
M
ꢒꢁ,:
$ ꢋꢄꢊ%
ꢀꢁ ꢂꢃꢄꢅꢀꢅ ꢃ!"ꢆꢇꢅꢃꢄ#ꢈ$ꢅ%ꢈꢆ&"ꢉꢈꢅ'ꢆꢊꢅ ꢆꢉꢊ(ꢅ)"&ꢅ'"!&ꢅ)ꢈꢅꢇꢋꢌꢆ&ꢈ#ꢅ*ꢃ&ꢍꢃꢄꢅ&ꢍꢈꢅꢍꢆ&ꢌꢍꢈ#ꢅꢆꢉꢈꢆꢁ
ꢎꢁ ꢏꢃ'ꢈꢄ!ꢃꢋꢄ!ꢅꢏꢅꢆꢄ#ꢅ+ꢀꢅ#ꢋꢅꢄꢋ&ꢅꢃꢄꢌꢇ"#ꢈꢅ'ꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢐꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢁꢅꢑꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢐꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢅ!ꢍꢆꢇꢇꢅꢄꢋ&ꢅꢈ$ꢌꢈꢈ#ꢅꢒꢁꢎꢒꢅ''ꢅꢐꢈꢉꢅ!ꢃ#ꢈꢁ
,ꢁ ꢏꢃ'ꢈꢄ!ꢃꢋꢄꢃꢄꢓꢅꢆꢄ#ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢃꢄꢓꢅꢐꢈꢉꢅꢔꢕꢑ+ꢅ-ꢀꢖꢁ.ꢑꢁ
/ꢕ01 /ꢆ!ꢃꢌꢅꢏꢃ'ꢈꢄ!ꢃꢋꢄꢁꢅꢗꢍꢈꢋꢉꢈ&ꢃꢌꢆꢇꢇꢊꢅꢈ$ꢆꢌ&ꢅ ꢆꢇ"ꢈꢅ!ꢍꢋ*ꢄꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ!ꢁ
ꢘ+21 ꢘꢈ%ꢈꢉꢈꢄꢌꢈꢅꢏꢃ'ꢈꢄ!ꢃꢋꢄ(ꢅ"!"ꢆꢇꢇꢊꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ(ꢅ%ꢋꢉꢅꢃꢄ%ꢋꢉ'ꢆ&ꢃꢋꢄꢅꢐ"ꢉꢐꢋ!ꢈ!ꢅꢋꢄꢇꢊꢁ
ꢑꢃꢌꢉꢋꢌꢍꢃꢐ ꢗꢈꢌꢍꢄꢋꢇꢋꢓꢊ ꢏꢉꢆ*ꢃꢄꢓ 0ꢒꢖꢞꢒꢛ,/
DS70265E-page 280
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
© 2007-2011 Microchip Technology Inc.
DS70265E-page 281
dsPIC33FJ12MC201/202
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS70265E-page 282
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
© 2007-2011 Microchip Technology Inc.
DS70265E-page 283
dsPIC33FJ12MC201/202
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS70265E-page 284
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
28-Lead Plastic Quad Flat, No Lead Package (ML) – 6x6 mm Body [QFN]
with 0.55 mm Contact Length
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
D2
EXPOSED
PAD
e
E
b
E2
2
1
2
1
K
N
N
NOTE 1
L
BOTTOM VIEW
TOP VIEW
A
A3
A1
Units
Dimension Limits
MILLIMETERS
NOM
MIN
MAX
Number of Pins
Pitch
Overall Height
Standoff
Contact Thickness
Overall Width
Exposed Pad Width
Overall Length
Exposed Pad Length
Contact Width
Contact Length
Contact-to-Exposed Pad
N
e
A
A1
A3
E
E2
D
28
0.65 BSC
0.90
0.80
0.00
1.00
0.05
0.02
0.20 REF
6.00 BSC
3.70
6.00 BSC
3.70
0.30
0.55
–
3.65
4.20
D2
b
L
3.65
0.23
0.50
0.20
4.20
0.35
0.70
–
K
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-105B
© 2007-2011 Microchip Technology Inc.
DS70265E-page 285
dsPIC33FJ12MC201/202
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇ&ꢕꢅꢆꢇ'ꢉꢅꢋ(ꢇ$ ꢇꢃꢄꢅꢆꢇꢈꢅꢍꢒꢅ)ꢄꢇꢖ*ꢃꢗꢇMꢇ+,+ꢇꢓꢓꢇꢜ ꢆ!ꢇ"&'$#
-ꢌꢋꢏꢇꢛꢙꢘꢘꢇꢓꢓꢇ. ꢑꢋꢅꢍꢋꢇꢃꢄꢑ)ꢋꢏ
$ ꢋꢄ% 2ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢐꢆꢌ3ꢆꢓꢈꢅ#ꢉꢆ*ꢃꢄꢓ!(ꢅꢐꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢑꢃꢌꢉꢋꢌꢍꢃꢐꢅꢂꢆꢌ3ꢆꢓꢃꢄꢓꢅꢕꢐꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ
ꢍ&&ꢐ144***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢐꢁꢌꢋ'4ꢐꢆꢌ3ꢆꢓꢃꢄꢓ
DS70265E-page 286
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
• The following tables in Section 23.0 “Electrical
Characteristics” have been updated with prelim-
inary values:
APPENDIX A: REVISION HISTORY
Revision A (January 2007)
- Updated Max MIPS for -40°C to +125°C
Temp Range (see Table 23-1)
This is the initial released version of this document.
- Updated parameter DC18 (see Table 23-4)
Revision B (May 2007)
- Added new parameters for +125°C, and
updated Typical and Max values for most
parameters (see Table 23-5)
This revision includes the following corrections and
updates:
- Added new parameters for +125°C, and
updated Typical and Max values for most
parameters (see Table 23-6)
• Minor typographical and formatting corrections
throughout the data sheet text.
• New content:
- Added new parameters for +125°C, and
updated Typical and Max values for most
parameters (see Table 23-7)
- Addition of bullet item (16-word conversion
result buffer) (see Section 19.1 “Key
Features”)
- Added new parameters for +125°C, and
updated Typical and Max values for most
parameters (see Table 23-8)
• Figure update:
- Oscillator System Diagram (see Figure 7-1)
- WDT Block Diagram (see Figure 20-2)
• Equation update:
- Updated parameter DI51, added parameters
DI51a, DI51b, and DI51c (see Table 23-9)
- Added Note 1 (see Table 23-11)
- Serial Clock Rate (see Equation 17-1)
• Register updates:
- Updated parameter OS30 (see Table 23-16)
- Updated parameter OS52 (see Table 23-17)
- Clock Divisor Register (see Register 7-2)
- Updated parameter F20, added Note 2 (see
Table 23-18)
- PLL Feedback Divisor Register (see
Register 7-3)
- Updated parameter F21 (see Table 23-19)
- Updated parameter TA15 (see Table 23-22)
- Updated parameter TB15 (see Table 23-23)
- Updated parameter TC15 (see Table 23-24)
- Updated parameter IC15 (see Table 23-26)
- Peripheral Pin Select Input Registers (see
Register 9-1 through Register 9-13)
- Note 2 in PWM Control Register 1 (see
Register 14-5)
- ADC1 Input Channel 1, 2, 3 Select Register
(see Register 19-4)
- Updated parameters AD05, AD06, AD07,
AD08, AD10, and AD11; added parameters
AD05a and AD06a; added Note 2; modified
ADC Accuracy headings to include
- ADC1 Input Channel 0 Select Register (see
Register 19-5)
• Table updates:
measurement information (see Table 23-38)
- AD1CON3 (see Table 3-15 and Table 3-16)
- RPINR15 (see Table 3-17)
- TRISA (see Table 3-20)
- Separated the ADC Module Specifications
table into three tables (see Table 23-38,
Table 23-39, and Table 23-40)
- TRISB (see Table 3-22)
- Updated parameter AD50 (see Table 23-41)
- Reset Flag Bit Operation (see Table 5-1)
- Updated parameters AD50 and AD57 (see
Table 23-42)
- Configuration Bit Values for Clock Operation
(see Table 7-1)
• Operation value update:
- IOLOCK set/clear operation (see
Section 9.4.3.1 “Control Register Lock”)
© 2007-2011 Microchip Technology Inc.
DS70265E-page 287
dsPIC33FJ12MC201/202
Revision C (June 2008)
This revision includes minor typographical and
formatting changes throughout the data sheet text.
The major changes are referenced by their respective
section in the following table.
TABLE 25-1: MAJOR SECTION UPDATES
Section Name
Update Description
“High-Performance, 16-bit
Digital Signal Controllers”
Added SSOP to list of available 28-pin packages (see “Packaging:” and
Table 1).
Added External Interrupts column to Remappable Peripherals in the Controller
Families table and Note 2 (see Table 1).
Added Note 1 to all pin diagrams, which references RPn pin usage by
remappable peripherals (see “Pin Diagrams”).
Section 1.0 “Device Overview”
Changed Capture Input pin names from IC0-IC1 to IC1-IC2 and updated
description for AVDD (see Table 1-1).
Section 3.0 “Memory
Organization”
Added SFR definitions (ACCAL, ACCAH, ACCAU, ACCBL, ACCBH, and
ACCBU) to the CPU Core Register Map (see Table 3-1).
Updated Reset values for the following SFRs: IPC0, IPC2-IPC7, IPC16, and
INTTREG (see Table 3-4).
Updated all SFR names in QEI1 Register Map (see Table 3-11).
The following changes were made to the ADC1 Register Maps:
• Updated the bit range for AD1CON3 from ADCS<5:0> to ADCS<7:0>)
(see Table 3-15 and Table 3-16).
• Added Bit 6 (PCFG7) and Bit 7 (PCFG6) names to AD1PCFGL (Table 3-15).
• Added Bit 6 (CSS7) and Bit 7 (CSS6) names to AD1CSSL (see Table 3-15).
• Changed Bit 5 and Bit 4 in AD1CSSL to unimplemented (see Table 3-15).
Updated the Reset value for CLKDIV in the System Control Register Map
(see Table 3-23).
Section 4.0 “Flash Program
Memory”
Updated Section 4.3 “Programming Operations” with programming time
formula.
Section 5.0 “Resets”
Entire section was replaced to maintain consistency with other dsPIC33F data
sheets.
Section 7.0 “Oscillator
Configuration”
Removed the first sentence of the third clock source item (External Clock) in
Section 7.1.1 “System Clock sources”
Updated the default bit values for DOZE and FRCDIV in the Clock Divisor
Register (see Register 7-2).
Added the center frequency in the OSCTUN register for the FRC Tuning bits
(TUN<5:0>) value 011111and updated the center frequency for bits value
011110(see Register 7-4)
Section 8.0 “Power-Saving
Features”
Added the following three registers:
• PMD1: Peripheral Module Disable Control Register 1
• PMD2: Peripheral Module Disable Control Register 2
• PMD3: Peripheral Module Disable Control Register 3
DS70265E-page 288
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
TABLE 25-1: MAJOR SECTION UPDATES
Section Name
Update Description
Section 9.0 “I/O Ports”
Added paragraph and Table 9-1 to Section 9.1.1 “Open-Drain Configuration”,
which provides details on I/O pins and their functionality.
Removed the following sections, which are now available in the related section
of the dsPIC33F Family Reference Manual:
• 9.4.2 “Available Peripherals”
• 9.4.3.3 “Mapping”
• 9.4.5 “Considerations for Peripheral Pin Selection”
Section 13.0 “Output Compare” Replaced sections 13.1, 13.2, and 13.3 and related figures and tables with
entirely new content.
Section 14.0 “Motor Control
PWM Module”
Removed the following sections, which are now available in the related section
of the dsPIC33F Family Reference Manual:
• 14.3 “PWM Time Base
• 14.4 “PWM Period”
• 14.5 “Edge-Aligned PWM”
• 14.6 “Center-Aligned PWM”
• 14.7 “PWM Duty Cycle Comparison Units”
• 14.8 “Complementary PWM Operation”
• 14.9 “Dead-Time Generators”
• 14.10 “Independent PWM Output”
• 14.11 “Single Pulse PWM Operation”
• 14.12 “PWM Output Override”
• 14.13 “PWM Output and Polarity Control
• 14.14 “PWM Fault Pins”
• 14.15 “PWM Update Lockout”
• 14.16 “PWM Special Event Trigger”
• 14.17 “PWM Operation During CPU Sleep Mode”
• 14.18 “PWM Operation During CPU Idle Mode
Removed the following sections, which are now available in the related section
Section 15.0 “Quadrature
Encoder Interface (QEI) Module” of the dsPIC33F Family Reference Manual:
• 15.1 “Quadrature Encoder Interface Logic”
• 15.2 “16-bit Up/Down Position Counter Mode”
• 15.3 “Position Measurement Mode”
• 15.4 “Programmable Digital Noise Filters”
• 15.5 “Alternate 16-bit Timer/Counter”
• 15.6 QEI Module Operation During CPU Sleep Mode”
• 15.7 “QEI Module Operation During CPU Idle Mode”
• 15.8 “Quadrature Encoder Interface Interrupts”
Section 16.0 “Serial Peripheral
Interface (SPI)”
Removed the following sections, which are now available in the related section
of the dsPIC33F Family Reference Manual:
• 16.1 “Interrupts”
• 16.2 “Receive Operations”
• 16.3 “Transmit Operations”
• 16.4 “SPI Setup: Master Mode”
• 16.5 “SPI Setup: Slave Mode” (retained Figure 16-1: SPI Module Block
Diagram)
© 2007-2011 Microchip Technology Inc.
DS70265E-page 289
dsPIC33FJ12MC201/202
TABLE 25-1: MAJOR SECTION UPDATES
Section Name
Update Description
Section 17.0 “Inter-Integrated
Circuit™ (I2C™)”
Removed the following sections, which are now available in the related section
of the dsPIC33F Family Reference Manual:
• 17.3 “I2C Interrupts”
• 17.4 “Baud Rate Generator” (retained Figure 17-1: I2C Block Diagram)
• 17.5 “I2C Module Addresses
• 17.6 “Slave Address Masking”
• 17.7 “IPMI Support”
• 17.8 “General Call Address Support”
• 17.9 “Automatic Clock Stretch”
• 17.10 “Software Controlled Clock Stretching (STREN = 1)”
• 17.11 “Slope Control”
• 17.12 “Clock Arbitration”
• 17.13 “Multi-Master Communication, Bus Collision, and Bus Arbitration
• 17.14 “Peripheral Pin Select Limitations
Section 18.0 “Universal
Asynchronous Receiver
Transmitter (UART)”
Removed the following sections, which are now available in the related section
of the dsPIC33F Family Reference Manual:
• 18.1 “UART Baud Rate Generator”
• 18.2 “Transmitting in 8-bit Data Mode
• 18.3 “Transmitting in 9-bit Data Mode
• 18.4 “Break and Sync Transmit Sequence”
• 18.5 “Receiving in 8-bit or 9-bit Data Mode”
• 18.6 “Flow Control Using UxCTS and UxRTS Pins”
• 18.7 “Infrared Support”
Removed IrDA references and Note 1, and updated the bit and bit value
descriptions for UTXINV (UxSTA<14>) in the UARTx Status and Control
Register (see Register 18-2).
DS70265E-page 290
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
TABLE 25-1: MAJOR SECTION UPDATES
Section Name
Update Description
Section 19.0 “10-bit/12-bit
Analog-to-Digital Converter
(ADC)”
Updated ADC Conversion Clock Select bits in the AD1CON3 register from
ADCS<5:0> to ADCS<7:0>. Any references to these bits have also been
updated throughout this data sheet (Register 19-3).
Replaced Figure 19-1 (ADC1 Module Block Diagram for dsPIC33FJ12MC201)
and added Figure 19-2 (ADC1 Block Diagram for dsPIC33FJ12MC202).
Removed Equation 19-1: ADC Conversion Clock Period and Figure 19-2: ADC
Transfer Function (10-Bit Example).
Added Note 2 to Figure 19-2: ADC Conversion Clock Period Block Diagram.
Updated ADC1 Input Channel 1, 2, 3 Select Register (see Register 19-4) as
follows:
• Changed bit 10-9 (CH123NB - dsPIC33FJ12MC201 devices only)
description for bit value of 10(if AD12B = 0).
• Updated bit 8 (CH123SB) to reflect device-specific information.
• Updated bit 0 (CH123SA) to reflect device-specific information.
• Changed bit 2-1 (CH123NA - dsPIC33FJ12MC201 devices only)
description for bit value of 10(if AD12B = 0).
Updated ADC1 Input Channel 0 Select Register (see Register 19-5) as follows:
• Changed bit value descriptions for bits 12-8
• Changed bit value descriptions for bits 4-0 (dsPIC33FJ12MC201 devices)
Modified Notes 1 and 2 in the ADC1 Input Scan Select Register Low (see
Register 19-6)
Modified Notes 1 and 2 in the ADC1 Port Configuration Register Low (see
Register 19-7)
Section 20.0 “Special Features” Added FICD register information for address 0xF8000E in the Device
Configuration Register Map (see Table 20-1).
Added FICD register content (BKBUG, COE, JTAGEN, and ICS<1:0> to the
dsPIC33FJ12MC201/202 Configuration Bits Description (see Table 20-2).
Added a note regarding the placement of low-ESR capacitors, after the second
paragraph of Section 20.2 “On-Chip Voltage Regulator” and to Figure 20-2.
Removed the words “if enabled” from the second sentence in the fifth paragraph
of Section 20.3 “BOR: Brown-out Reset”
© 2007-2011 Microchip Technology Inc.
DS70265E-page 291
dsPIC33FJ12MC201/202
TABLE 25-1: MAJOR SECTION UPDATES
Section Name
Update Description
Section 23.0 “Electrical
Characteristics”
Updated Max MIPS value for -40ºC to +125ºC temperature range in Operating
MIPS vs. Voltage (see Table 23-1).
Added 20-pin SOIC and 28-pin SSOP package information to Thermal
Packaging Characteristics and updated Typical values for all devices
(see Table 23-3).
Removed Typ value for parameter DC12 (see Table 23-4).
Updated Note 2 in Table 23-7: DC Characteristics: Power-Down Current (IPD).
Updated MIPS conditions for parameters DC24c, DC44c, DC72a, DC72f, and
DC72g (see Table 23-5, Table 23-6, and Table 23-8).
Added Note 4 (reference to new table containing digital-only and analog pin
information to I/O Pin Input Specifications (see Table 23-9).
Updated Program Memory parameters (D136a, D136b, D137a, D137b, D138a,
and D138b) and added Note 2 (see Table 23-12).
Updated Max value for Internal RC Accuracy parameter F21 for -40°C ≤TA ≤
+125°C condition and added Note 2 (see Table 23-19).
Removed all values for Reset, Watchdog Timer, Oscillator Start-up Timer, and
Power-up Timer parameter SY20 and updated conditions, which now refers to
Section 20.4 “Watchdog Timer (WDT)” and LPRC parameter F21
(Table 23-21).
Updated Min value for Input Capture Timing Requirements parameter IC15
(see Table 23-26).
The following changes were made to the ADC Module Specifications
(Table 23-38):
• Updated Min value for ADC Module Specification parameter AD07.
• Updated Typ value for parameter AD08
• Added references to Note 1 for parameters AD12 and AD13
• Removed Note 2.
The following changes were made to the ADC Module Specifications (12-bit
Mode) (Table 23-39):
• Updated Min and Max values for both AD21a parameters (measurements
with internal and external VREF+/VREF-).
• Updated Min, Typ, and Max values for parameter AD24a.
• Updated Max value for parameter AD32a.
• Removed Note 1.
• Removed VREFL from Conditions for parameters AD21a, AD22a, AD23a,
and AD24a (measurements with internal VREF+/VREF-).
The following changes were made to the ADC Module Specifications (10-bit
Mode) (Table 23-40):
• Updated Min and Max values for parameter AD21b (measurements with
external VREF+/VREF-).
• Removed ± symbol from Min, Typ, and Max values for parameters AD23b
and AD24b (measurements with internal VREF+/VREF-).
• Updated Typ and Max values for parameter AD32b.
• Removed Note 1.
• Removed VREFL from Conditions for parameters AD21a, AD22a, AD23a,
and AD24a (measurements with internal VREF+/VREF-).
Updated Min and Typ values for parameters AD60, AD61, AD62, and AD63 and
removed Note 3 (see Table 23-41 and Table 23-42).
DS70265E-page 292
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
TABLE 25-1: MAJOR SECTION UPDATES
Section Name
Update Description
Section 24.0 “Packaging
Information”
Added 28-lead SSOP package marking information.
“Product Identification System” Added Plastic Shrink Small Outline (SSOP) package information.
Revision D (June 2009)
This revision includes minor typographical and
formatting changes throughout the data sheet text.
Global changes include:
• Changed all instances of OSCI to OSC1 and
OSCO to OSC2
• Changed all instances of PGCx/EMUCx and
PGDx/EMUDx (where x = 1, 2, or 3) to PGECx
and PGEDx
Changed all instances of VDDCORE and VDDCORE/VCAP
to VCAP/VDDCORE
All other major changes are referenced by their
respective section in the following table.
TABLE 25-2: MAJOR SECTION UPDATES
Section Name
Update Description
“High-Performance, 16-bit Digital Signal Added Note 2 to the 28-Pin QFN-S and 44-Pin QFN pin diagrams,
Controllers”
which references pin connections to VSS.
Section 2.0 “Guidelines for Getting
Started with 16-bit Digital Signal
Controllers”
Added new section to the data sheet that provides guidelines on getting
started with 16-bit Digital Signal Controllers.
Section 8.0 “Oscillator Configuration”
Updated the Oscillator System Diagram (see Figure 8-1).
Added Note 1 to the Oscillator Tuning (OSCTUN) register (see
Register 8-4).
Section 10.0 “I/O Ports”
Removed Table 10-1 and added reference to pin diagrams for I/O pin
availability and functionality.
Section 17.0 “Serial Peripheral Interface Added Note 2 to the SPIx Control Register 1 (see Register 17-2).
(SPI)”
Section 19.0 “Universal Asynchronous
Receiver Transmitter (UART)”
Updated the UTXINV bit settings in the UxSTA register and added Note
1 (see Register 19-2).
Section 24.0 “Electrical Characteristics” Updated the Min value for parameter DC12 (RAM Retention Voltage)
and added Note 4 to the DC Temperature and Voltage Specifications
(see Table 24-4).
Updated the Min value for parameter DI35 (see Table 24-20).
Updated AD08 and added reference to Note 2 for parameters AD05a,
AD06a, and AD08a (see Table 24-38).
© 2007-2011 Microchip Technology Inc.
DS70265E-page 293
dsPIC33FJ12MC201/202
Revision E (July 2011)
This revision includes formatting changes and minor
typographical throughout the data sheet text.
Global changes include:
• Removed Preliminary marking from the footer
• Updated all family reference manual information
in the note boxes located at the beginning of most
chapters
• Changed all instances of VCAP/VDDCORE to VCAP
All other major changes are referenced by their
respective section in the following table.
TABLE 25-3: MAJOR SECTION UPDATES
Section Name
Update Description
Section 2.0 “Guidelines for Getting
Started with 16-bit Digital Signal
Controllers”
Changed the title of section 2.3 to Section 2.3 “CPU Logic Filter
Capacitor Connection (VCAP)”.
Updated the second paragraph in Section 2.9 “Unused I/Os”.
Section 4.0 “Memory Organization”
Revised the data memory implementation value in the third paragraph
of Section 4.2 “Data Address Space”.
Updated the All Resets values for TMR1, TMR2, and TMR3 in the
Timer Register Map (see Table 4-5).
Section 8.0 “Oscillator Configuration”
Added Note 3 to the Oscillator Control Register (see Register 8-1).
Added Note 2 to the Clock Divisor Register (see Register 8-2).
Added Note 1 to the PLL Feedback Divisor Register (see Register 8-3).
Added Note 2 to the FRC Oscillator Tuning Register (see Register 8-4).
Section 10.0 “I/O Ports”
Revised the second paragraph in Section 10.1.1 “Open-Drain
Configuration”.
Section 14.0 “Output Compare”
Updated the Output Compare Module Block Diagram (see Figure 14-1).
Section 19.0 “Universal Asynchronous
Receiver Transmitter (UART)”
Revised the UART module Baud Rate features, replacing both items
with “Baud rates ranging from 10 Mbps to 38 bps at 40 MIPS”.
Section 21.0 “Special Features”
Revised all paragraphs in Section 21.1 “Configuration Bits”.
Updated the Device Configuration Register Map (see Table 21-1).
Added the RTSP Effect column in the Configuration Bits Description
(see Table 21-2).
DS70265E-page 294
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
TABLE 25-3: MAJOR SECTION UPDATES (CONTINUED)
Section Name
Update Description
Section 24.0 “Electrical Characteristics” Updated the following Absolute Maximum Ratings:
• Storage temperature
• Voltage on any pin that is not 5V tolerant with respect to VSS
• Voltage on any 5V tolerant pin with respect to VSS when VDD ≥ 3.0V
• Voltage on any 5V tolerant pin with respect to VSS when VDD < 3.0V
• Added Note 4
Revised parameters DI18, DI19, DI50, and DI51, added parameters
DI21, DI25, DI26, DI27, DI28, DI29, DI60a, DI60b, and DI60c, and
added Notes 5, 6, 7, 8, and 9 to the I/O Pin Input Specifications (see
Table 24-9).
Removed Note 2 from the AC Characteristics: Internal RC Accuracy
(see Table 24-19).
Updated the maximum value for parameter OC15 and the minimum
value for parameter OC20 in the Simple OC/PWM Mode Timing
Requirements (see Table 24-28).
Updated all SPI specifications (see Table 24-32 through Table 24-39
and Figure 24-14 through Figure 24-21).
Updated the minimum values for parameters AD05 and AD07, and the
maximum value for parameter AD06 in the ADC Module Specifications
(see Table 24-42).
Added Note 4 regarding injection currents to the ADC Module
Specifications (12-bit mode) (see Table 24-43).
Added Note 4 regarding injection currents to the ADC Module
Specifications (10-bit mode) (see Table 24-44).
© 2007-2011 Microchip Technology Inc.
DS70265E-page 295
dsPIC33FJ12MC201/202
NOTES:
DS70265E-page 296
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
INDEX
Customer Change Notification Service............................. 301
Customer Notification Service .......................................... 301
Customer Support............................................................. 301
A
AC Characteristics ............................................................ 234
Internal RC Accuracy................................................ 236
Load Conditions........................................................ 234
ADC
D
Data Accumulators and Adder/Subtracter .......................... 27
Data Space Write Saturation...................................... 29
Overflow and Saturation............................................. 27
Round Logic ............................................................... 29
Write Back .................................................................. 28
Data Address Space........................................................... 33
Alignment.................................................................... 33
Memory Map for dsPIC33FJ12MC201/202 Devices with
1 KB RAM........................................................... 34
Initialization ............................................................... 193
Key Features............................................................. 193
ADC Module
ADC1 Register Map.................................................... 44
ADC11 Register Map.................................................. 43
Alternate Interrupt Vector Table (AIVT) .............................. 71
Analog-to-Digital Converter (ADC).................................... 193
Arithmetic Logic Unit (ALU)................................................. 25
Assembler
Near Data Space........................................................ 33
Software Stack ........................................................... 48
Width .......................................................................... 33
DC Characteristics............................................................ 224
I/O Pin Input Specifications ...................................... 229
I/O Pin Output Specifications.................................... 232
Idle Current (IDOZE) .................................................. 228
Idle Current (IIDLE).................................................... 227
Operating Current (IDD) ............................................ 226
Power-Down Current (IPD)........................................ 228
Program Memory...................................................... 233
Temperature and Voltage Specifications.................. 225
Development Support....................................................... 219
Doze Mode ....................................................................... 114
DSP Engine........................................................................ 25
Multiplier ..................................................................... 27
MPASM Assembler................................................... 220
B
Barrel Shifter....................................................................... 29
Bit-Reversed Addressing .................................................... 51
Example...................................................................... 52
Implementation ........................................................... 51
Sequence Table (16-Entry)......................................... 52
Block Diagrams
16-bit Timer1 Module................................................ 141
Connections for On-Chip Voltage Regulator............. 208
Device Clock..................................................... 103, 105
DSP Engine ................................................................ 26
dsPIC33FJ12MC201/202............................................ 10
dsPIC33FJ12MC201/202 CPU Core .......................... 20
Input Capture ............................................................ 149
Output Compare ....................................................... 151
PLL............................................................................ 105
PWM Module .................................................... 156, 157
Quadrature Encoder Interface .................................. 169
Reset System.............................................................. 63
Shared Port Structure ............................................... 119
SPI ............................................................................ 173
Timer2 (16-bit) .......................................................... 145
Timer2/3 (32-bit) ....................................................... 144
UART ........................................................................ 187
Watchdog Timer (WDT)............................................ 209
E
Electrical Characteristics .................................................. 223
AC............................................................................. 234
Equations
Device Operating Frequency.................................... 104
Errata.................................................................................... 8
F
Flash Program Memory ...................................................... 57
Control Registers........................................................ 58
Operations.................................................................. 58
Programming Algorithm.............................................. 61
RTSP Operation ......................................................... 58
Table Instructions ....................................................... 57
Flexible Configuration....................................................... 205
C
C Compilers
MPLAB C18 .............................................................. 220
Clock Switching................................................................. 112
Enabling.................................................................... 112
Sequence.................................................................. 112
Code Examples
Erasing a Program Memory Page............................... 61
Initiating a Programming Sequence............................ 62
Loading Write Buffers ................................................. 62
Port Write/Read ........................................................ 120
PWRSAV Instruction Syntax..................................... 113
Code Protection ........................................................ 205, 210
Configuration Bits.............................................................. 205
Configuration Register Map .............................................. 205
Configuring Analog Port Pins............................................ 120
CPU
I
I/O Ports ........................................................................... 119
Parallel I/O (PIO) ...................................................... 119
Write/Read Timing.................................................... 120
I2C
Addresses................................................................. 180
Operating Modes...................................................... 179
Registers .................................................................. 179
I2C Module
I2C1 Register Map...................................................... 41
In-Circuit Debugger........................................................... 210
In-Circuit Emulation .......................................................... 205
In-Circuit Serial Programming (ICSP)....................... 205, 210
Input Capture.................................................................... 149
Registers .................................................................. 150
Input Change Notification ................................................. 120
Instruction Addressing Modes ............................................ 48
File Register Instructions............................................ 48
Control Register.......................................................... 22
CPU Clocking System....................................................... 104
PLL Configuration ..................................................... 105
Selection ................................................................... 104
Sources..................................................................... 104
© 2007-2011 Microchip Technology Inc.
DS70265E-page 297
dsPIC33FJ12MC201/202
Fundamental Modes Supported..................................49
MAC Instructions.........................................................49
MCU Instructions ........................................................48
Move and Accumulator Instructions............................49
Other Instructions........................................................49
Instruction Set
Overview...................................................................214
Summary...................................................................211
Instruction-Based Power-Saving Modes...........................113
Idle ............................................................................114
Sleep.........................................................................113
Internal RC Oscillator
Use with WDT...........................................................209
Internet Address................................................................301
Interrupt Control and Status Registers................................75
IECx ............................................................................75
IFSx.............................................................................75
INTCON1 ....................................................................75
INTCON2 ....................................................................75
IPCx ............................................................................75
Interrupt Setup Procedures...............................................101
Initialization ...............................................................101
Interrupt Disable........................................................101
Interrupt Service Routine ..........................................101
Trap Service Routine ................................................101
Interrupt Vector Table (IVT) ................................................71
Interrupts Coincident with Power Save Instructions..........114
Register Map .............................................................. 47
PORTA
Register Map .............................................................. 46
PORTB
Register Map for dsPIC33FJ12MC201....................... 46
Register Map for dsPIC33FJ12MC202....................... 46
Power-on Reset (POR)....................................................... 68
Power-Saving Features .................................................... 113
Clock Frequency and Switching ............................... 113
Program Address Space..................................................... 31
Construction ............................................................... 53
Data Access from Program Memory Using Program
Space Visibility ................................................... 56
Data Access from Program Memory Using Table Instruc-
tions.................................................................... 55
Data Access from, Address Generation ..................... 54
Memory Map............................................................... 31
Table Read Instructions
TBLRDH ............................................................. 55
TBLRDL.............................................................. 55
Visibility Operation...................................................... 56
Program Memory
Interrupt Vector........................................................... 32
Organization ............................................................... 32
Reset Vector............................................................... 32
PWM Time Base............................................................... 158
Q
J
Quadrature Encoder Interface (QEI)................................. 169
Quadrature Encoder Interface (QEI) Module
JTAG Boundary Scan Interface ........................................205
JTAG Interface..................................................................210
Register Map .............................................................. 41
M
R
Memory Organization..........................................................31
Microchip Internet Web Site..............................................301
Modulo Addressing .............................................................50
Applicability.................................................................51
Operation Example .....................................................50
Start and End Address................................................50
W Address Register Selection ....................................50
Motor Control PWM...........................................................155
Motor Control PWM Module
2-Output Register Map................................................41
4-Output Register Map................................................40
6-Output Register Map................................................40
MPLAB ASM30 Assembler, Linker, Librarian ...................220
MPLAB Integrated Development Environment Software ..219
MPLAB PM3 Device Programmer.....................................222
MPLAB REAL ICE In-Circuit Emulator System.................221
MPLINK Object Linker/MPLIB Object Librarian ................220
Reader Response............................................................. 302
Registers
AD1CHS123 (ADC1 Input Channel 1, 2, 3 Select)... 201
ADxCHS0 (ADCx Input Channel 0 Select ................ 203
ADxCON1 (ADCx Control 1)..................................... 197
ADxCON2 (ADCx Control 2)..................................... 199
ADxCON3 (ADCx Control 3)..................................... 200
ADxCSSL (ADCx Input Scan Select Low)................ 204
ADxPCFGL (ADCx Port Configuration Low)............. 204
CLKDIV (Clock Divisor) ............................................ 109
CORCON (Core Control)...................................... 24, 76
DFLTxCON (QEI Control)......................................... 172
I2CxCON (I2Cx Control)........................................... 181
I2CxMSK (I2Cx Slave Mode Address Mask)............ 185
I2CxSTAT (I2Cx Status) ........................................... 183
IEC0 (Interrupt Enable Control 0)............................... 85
IEC1 (Interrupt Enable Control 1)............................... 87
IEC3 (Interrupt Enable Control 3)............................... 88
IEC4 (Interrupt Enable Control 4)............................... 89
IFS0 (Interrupt Flag Status 0) ..................................... 80
IFS1 (Interrupt Flag Status 1) ..................................... 82
IFS3 (Interrupt Flag Status 3) ..................................... 83
IFS4 (Interrupt Flag Status 4) ..................................... 84
INTCON1 (Interrupt Control 1).................................... 77
INTCON2 (Interrupt Control 2).................................... 79
INTTREG Interrupt Control and Status Register ...... 100
IPC0 (Interrupt Priority Control 0) ............................... 90
IPC1 (Interrupt Priority Control 1) ............................... 91
IPC14 (Interrupt Priority Control 14) ........................... 97
IPC15 (Interrupt Priority Control 15) ........................... 98
IPC16 (Interrupt Priority Control 16) ........................... 98
IPC18 (Interrupt Priority Control 18) ........................... 99
IPC2 (Interrupt Priority Control 2) ............................... 92
N
NVM Module
Register Map...............................................................47
O
Open-Drain Configuration .................................................120
Output Compare................................................................151
P
Packaging .........................................................................271
Details.......................................................................273
Marking .............................................................271, 272
Peripheral Module Disable (PMD).....................................114
Pinout I/O Descriptions (table) ............................................11
PMD Module
DS70265E-page 298
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
IPC3 (Interrupt Priority Control 3) ............................... 93
IPC4 (Interrupt Priority Control 4) ............................... 94
IPC5 (Interrupt Priority Control 5) ............................... 95
IPC7 (Interrupt Priority Control 7) ............................... 96
NVMCON (Flash Memory Control) ............................. 59
NVMKEY (Nonvolatile Memory Key) .......................... 60
OCxCON (Output Compare x Control) ..................... 154
OSCCON (Oscillator Control) ................................... 107
OSCTUN (FRC Oscillator Tuning)............................ 111
P1DC3 (PWM Duty Cycle 3)..................................... 167
PLLFBD (PLL Feedback Divisor).............................. 110
PMD1 (Peripheral Module Disable Control Register 1) ..
115
Timing Characteristics
CLKO and I/O........................................................... 237
Timing Diagrams
10-bit A/D Conversion (CHPS = 01, SIMSAM = 0, ASAM
= 0, SSRC = 000) ............................................. 268
10-bit A/D Conversion (CHPS<1:0> = 01, SIMSAM = 0,
ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> =
00001) .............................................................. 268
12-bit A/D Conversion (ASAM = 0, SSRC = 000)..... 267
Brown-out Situations .................................................. 68
External Clock .......................................................... 235
I2Cx Bus Data (Master Mode).................................. 260
I2Cx Bus Data (Slave Mode).................................... 262
I2Cx Bus Start/Stop Bits (Master Mode)................... 260
I2Cx Bus Start/Stop Bits (Slave Mode)..................... 262
Input Capture (CAPx) ............................................... 242
Motor Control PWM.................................................. 244
Motor Control PWM Fault......................................... 244
OC/PWM .................................................................. 243
Output Compare (OCx) ............................................ 243
QEA/QEB Input ........................................................ 245
QEI Module Index Pulse........................................... 246
Reset, Watchdog Timer, Oscillator Start-up Timer and
Power-up Timer................................................ 238
Timer1, 2 and 3 External Clock ................................ 240
TimerQ (QEI Module) External Clock....................... 242
Timing Requirements
PMD2 (Peripheral Module Disable Control Register 2) ..
116
PMD3 (Peripheral Module Disable Control Register 3) ..
117
PWMxCON1 (PWM Control 1).................................. 161
PWMxCON2 (PWM Control 2).................................. 162
PxDC1 (PWM Duty Cycle 1)..................................... 167
PxDC2 (PWM Duty Cycle 2)..................................... 167
PxDTCON1 (Dead-Time Control 1) .......................... 163
PxDTCON2 (Dead-Time Control 2) .......................... 164
PxFLTACON (Fault A Control).................................. 165
PxOVDCON (Override Control) ................................ 166
PxSECMP (Special Event Compare)........................ 160
PxTCON (PWM Time Base Control)......................... 158
PxTMR (PWM Timer Count Value)........................... 159
PxTPER (PWM Time Base Period) .......................... 159
QEICON (QEI Control).............................................. 170
RCON (Reset Control)................................................ 64
SPIxCON1 (SPIx Control 1)...................................... 175
SPIxCON2 (SPIx Control 2)...................................... 177
SPIxSTAT (SPIx Status and Control) ....................... 174
SR (CPU Status)................................................... 22, 76
T1CON (Timer1 Control)........................................... 142
T2CON Control ......................................................... 146
T3CON Control ......................................................... 147
TCxCON (Input Capture x Control)........................... 150
UxMODE (UARTx Mode).......................................... 188
UxSTA (UARTx Status and Control)......................... 190
CLKO and I/O........................................................... 237
DCI AC-Link Mode.................................................... 264
DCI Multi-Channel, I2S Modes ................................. 264
External Clock .......................................................... 235
Input Capture............................................................ 243
Timing Specifications
10-bit A/D Conversion Requirements....................... 269
12-bit A/D Conversion Requirements....................... 267
I2Cx Bus Data Requirements (Master Mode)........... 261
I2Cx Bus Data Requirements (Slave Mode)............. 263
Motor Control PWM Requirements........................... 245
Output Compare Requirements................................ 243
PLL Clock ................................................................. 236
QEI External Clock Requirements............................ 242
QEI Index Pulse Requirements ................................ 247
Quadrature Decoder Requirements ......................... 246
Reset, Watchdog Timer, Oscillator Start-up Timer, Pow-
er-up Timer and Brown-out Reset Requirements...
239
Reset
Illegal Opcode................................................. 63, 69, 70
Trap Conflict................................................................ 69
Uninitialized W Register.................................. 63, 69, 70
Reset Sequence ................................................................. 71
Resets................................................................................. 63
Simple OC/PWM Mode Requirements..................... 244
Timer1 External Clock Requirements....................... 240
Timer2 External Clock Requirements....................... 241
Timer3 External Clock Requirements....................... 241
S
Serial Peripheral Interface (SPI) ....................................... 173
Software Reset Instruction (SWR)...................................... 69
Software Simulator (MPLAB SIM)..................................... 221
Software Stack Pointer, Frame Pointer
U
UART Module
CALLL Stack Frame.................................................... 48
Special Features of the CPU ............................................ 205
SPI Module
UART1 Register Map ................................................. 42
Universal Asynchronous Receiver Transmitter (UART) ... 187
Using the RCON Status Bits............................................... 70
SPI1 Register Map...................................................... 42
Symbols Used in Opcode Descriptions............................. 212
System Control
V
Voltage Regulator (On-Chip) ............................................ 208
Register Map............................................................... 47
W
T
Watchdog Time-out Reset (WDTR).................................... 69
Watchdog Timer (WDT)............................................ 205, 209
Programming Considerations................................... 209
WWW Address ................................................................. 301
WWW, On-Line Support ....................................................... 8
Temperature and Voltage Specifications
AC............................................................................. 234
Timer1............................................................................... 141
Timer2/3............................................................................ 143
© 2007-2011 Microchip Technology Inc.
DS70265E-page 299
dsPIC33FJ12MC201/202
NOTES:
DS70265E-page 300
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• Development Systems Information Line
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
• General Technical Support – Frequently Asked
Questions (FAQs), technical support requests,
online discussion groups, Microchip consultant
program member listing
Technical support is available through the web site
at: http://microchip.com/support
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
© 2007-2011 Microchip Technology Inc.
DS70265E-page 301
dsPIC33FJ12MC201/202
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our
documentation can better serve you, please FAX your comments to the Technical Publications Manager at
(480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
TO:
RE:
Technical Publications Manager
Reader Response
Total Pages Sent ________
From:
Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Y
N
dsPIC33FJ12MC201/202
DS70265E
Literature Number:
Device:
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS70265E-page 302
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12MC201/202
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
dsPIC 33 FJ 12 MC2 02 T E / SP - XXX
a)
dsPIC33FJ12MC202-E/SP:
Motor Control dsPIC33, 12 KB program
memory, 28-pin, Extended temperature,
SPDIP package.
Microchip Trademark
Architecture
Flash Memory Family
Program Memory Size (KB)
Product Group
Pin Count
Tape and Reel Flag (if applicable)
Temperature Range
Package
Pattern
Architecture:
33
=
=
=
16-bit Digital Signal Controller
Flash program memory, 3.3V
Motor Control family
Flash Memory Family: FJ
Product Group:
Pin Count:
MC2
01
02
=
=
20-pin
28-pin
Temperature Range:
Package:
I
=
=
-40° C to+85° C (Industrial)
-40° C to+125° C (Extended)
E
P
=
=
=
=
=
Plastic Dual In-Line - 300 mil body (PDIP)
SP
SO
ML
SS
Skinny Plastic Dual In-Line - 300 mil body (SPDIP)
Plastic Small Outline - Wide, 7.50 mil body (SOIC)
Plastic Quad, No Lead Package - 6x6 mm body (QFN)
Plastic Shrink Small Outline - 5.3 mm body (SSOP)
© 2007-2011 Microchip Technology Inc.
DS70265E-page 303
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
Web Address:
www.microchip.com
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Korea - Seoul
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
China - Hangzhou
Tel: 86-571-2819-3180
Fax: 86-571-2819-3189
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Taiwan - Hsin Chu
Tel: 886-3-6578-300
Fax: 886-3-6578-370
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Kaohsiung
Tel: 886-7-213-7830
Fax: 886-7-330-9305
Los Angeles
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Toronto
Mississauga, Ontario,
Canada
China - Xiamen
Tel: 905-673-0699
Fax: 905-673-6509
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
05/02/11
DS70265E-page 304
© 2007-2011 Microchip Technology Inc.
相关型号:
DSPIC33FJ12MC202-I/SO
16-BIT, FLASH, 40 MHz, MICROCONTROLLER, PDSO28, 7.50 MM, LEAD FREE, PLASTIC, SOIC-28
MICROCHIP
DSPIC33FJ12MC202-I/SP
16-BIT, FLASH, 40 MHz, MICROCONTROLLER, PDIP28, 0.300 INCH, LEAD FREE, PLASTIC, SDIP-28
MICROCHIP
DSPIC33FJ12MC202T-I/ML
16-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQCC28, 6 X 6 MM, LEAD FREE, PLASTIC, QFN-28
MICROCHIP
©2020 ICPDF网 联系我们和版权申明