DSPIC30F5011P-I/PT [MICROCHIP]
DSPIC30F5011P-I/PT;
| 型号： | DSPIC30F5011P-I/PT |
| 厂家： | 
MICROCHIP |
| 描述： | DSPIC30F5011P-I/PT |
| 文件： | 总350页 (文件大小：5223K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M
dsPIC30F
Data Sheet
High Performance
Digital Signal Controllers
2002 Microchip Technology Inc.
Advance Information
DS70032B
®
Note the following details of the code protection feature on PICmicro MCUs.
•
•
The PICmicro family meets the specifications contained in the Microchip Data Sheet.
Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today,
when used in the intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowl-
edge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet.
The person doing so may be engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable”.
•
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of
our product.
If you have any further questions about this matter, please contact the local sales office nearest to you.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical com-
ponents in life support systems is not authorized except with
express written approval by Microchip. No licenses are con-
veyed, implicitly or otherwise, under any intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, FilterLab,
KEELOQ, MPLAB, PIC, PICmicro, PICMASTER, PICSTART,
PRO MATE, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microID,
microPort, Migratable Memory, MPASM, MPLIB, MPLINK,
MPSIM, MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select
Mode and Total Endurance are trademarks of Microchip
Technology Incorporated in the U.S.A.
Serialized Quick Term Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2002, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
DS70032B - page ii
Advance Information
2002 Microchip Technology Inc.
dsPIC30F
M
dsPIC30F Enhanced FLASH 16-bit Microcontrollers
High Performance Modified RISC CPU:
Peripheral Features (Continued):
• Modified Harvard architecture
• 3-wire SPITM modules (supports 4 frame modes)
• C compiler optimized instruction set architecture
• 89 base instructions
• I2CTM module supports Multi-Master/Slave mode
and 7-bit/10-bit addressing
• Addressable UART modules supporting:
- Interrupt on address bit
• 24-bit wide instructions, 16-bit wide data path
• Linear program memory addressing up to 4M
- Wake-up on START bit
Instruction Words
- 4 characters deep TX and RX FIFO buffers
• CAN bus modules
• Linear data memory addressing up to 64 Kbytes
• Up to 144 Kbytes on-chip FLASH program space
- Up to 48K Instruction Words
Motor Control PWM Module Features:
• Up to 8 Kbytes of on-chip data RAM
• Up to 8 PWM output channels
• Up to 4 Kbytes of non-volatile data EEPROM
- Complementary or Independent Output
modes
- Edge and Center Aligned modes
• 4 duty cycle generators
• Dedicated time-base with 4 modes
• Programmable output polarity
• Dead-time control for Complementary mode
• Manual output control
• 16 x 16-bit working register array
• Three Address Generation Units that enable:
- Dual data fetch
- Accumulator write back for DSP operations
• Flexible addressing modes supporting:
- Indirect, Modulo and Bit-Reversed modes
• Two, 40-bit wide accumulators with optional
saturation logic
• Trigger for A/D conversions
• 16-bit x 16-bit single cycle hardware fractional/
integer multiplier
Quadrature Encoder Interface Module
Features:
• Single cycle Multiply-Accumulate (MAC) operation
• 40-stage Barrel Shifter
• Phase A, Phase B and Index Pulse input
• 16-bit up/down position counter
• Up to 30 MIPS operation:
- DC to 40 MHz external clock input
• Count direction status
- 4 MHz - 10 MHz oscillator input with PLL
active (4x, 8x, 16x)
• Position measurement (x2 and x4) mode
• Programmable digital noise filters on inputs
• Alternate 16-bit Timer/Counter mode
• Interrupt on position counter rollover/underflow
• Up to 45 interrupt sources
- 8 user selectable priority levels
• Vector table with up to 62 vectors
- 54 interrupt vectors
Input Capture Module Features:
- 8 processor exceptions and software traps
• Captures 16-bit timer value
Peripheral Features:
- Capture every 1st, 4th or 16th rising edge
- Capture every falling edge
- Capture every rising and falling edge
• Resolution of 33 ns at 30 MIPS
• Timer2 or Timer3 time-base selection
• Input Capture during IDLE
• High current sink/source I/O pins: 25 mA/25 mA
• Up to 5 external interrupt sources
• Timer module with programmable prescaler:
- Up to five 16-bit timers/counters; optionally
pair up 16-bit timers into 32-bit timer modules
• Interrupt on input capture event
• 16-bit Capture Input functions
• 16-bit Compare/PWM Output functions
- Dual Compare mode available
• Data Converter Interface (DCI), supports common
audio CODEC protocols including I2S and AC’97
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 1
dsPIC30F
Analog Features:
CMOS Technology:
• 12-bit or 10-bit Analog-to-Digital Converter (A/D) with:
• Low power, high speed FLASH technology
• Wide operating voltage range (2.5V to 5.5V)
• Industrial and Extended temperature ranges
• Low power consumption
- 100 Ksps (for 12-bit A/D) or 500 Ksps
(for 10-bit A/D) conversion rate
- Up to 16 input channels
- Conversion available during SLEEP and IDLE
• Programmable Low Voltage Detection (PLVD)
• Programmable Brown-out Detection and RESET
generation
Special Microcontroller Features:
• Enhanced FLASH program memory
- 100,000 erase/write cycle (typical) for
industrial temperature range
• Data EEPROM memory
- 1,000,000 erase/write cycle (typical)
industrial temperature range
- Data EEPROM Retention > 20 years
• Self-reprogrammable under software control
• Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)
• Flexible Watchdog Timer (WDT) with on-chip low
power RC Oscillator for reliable operation
• Fail safe clock monitor operation
- Detects clock failure and switches to on-chip
low power RC oscillator
• Programmable code protection
• In-Circuit Serial Programming™ (ICSP™) via 3
pins and power/ground
• Selectable Power Management modes
- SLEEP, IDLE and Alternate Clock modes
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 2
dsPIC30F
dsPIC30F Sensor Processor Family
Program Memory
SRAM EEPROM Timer Input Output Comp/ A/D 12-bit
Device
Pins
Bytes
Bytes
16-bit
Cap
Std PWM
100 Ksps
Bytes
Instructions
dsPIC30F2011 18
dsPIC30F3012 18
dsPIC30F2012 28
dsPIC30F3013 28
12K
24K
12K
24K
4K
8K
4K
8K
1024
2048
1024
2048
0
3
3
3
3
2
2
2
2
2
2
2
2
8 ch
8 ch
1
1
1
2
1
1
1
1
1
1
1
1
1024
0
10 ch
10 ch
1024
Pin Diagrams
Part No.: 30F2011 / 30F3012
18-Pin SOIC and PDIP
AN6/SCK1/INT0/OCFA/RB6
AN5/U1RX/SDI1/SDA/CN7/RB5
AN4/U1TX/SDO1/SCL/CN6/RB4
1
2
3
4
5
18 AN7/IC2/OC2/RB7
IC1/OC1/RD8
OSC1/CLKIN
OSC2/CLKO/RC15
VDD
17
16
15
14
MCLR
Vss
AN0/VREF+/CN2/RB0
AN1/VREF-/CN3/RB1
AVDD
SOSC2/T2CK/U1ATX/CN1/RC13
SOSC1/T1CK/U1ARX/CN0/RC14
AN3/CN5/RB3
6
7
8
9
13
12
11
AVSS
10 AN2/SS1/CN4/RB2
Note: Pinout subject to change.
28-Pin SDIP
Part No.: 30F2012 / 30F3013
MCLR
AN0/VREF+/CN2/RB0
AN1/VREF-/CN3/RB1
AN2/SS1/CN4/RB2
AN3/CN5/RB3
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
20
19
18
17
16
AVDD
AVSS
AN6/OCFA/RB6
AN7/RB7
AN8/OC1/RB8
AN9/OC2/RB9
U2RX/RF4
U2TX/RF5
VDD
AN4/CN6/RB4
AN5/CN7/RB5
VSS
OSC1/CLKIN
9
OSC2/CLKO/RC15
SOSC2/T2CK/U1ATX/CN1/RC13
SOSC1/T1CK/U1ARX/CN0/RC14
VDD
VSS
10
11
12
13
14
U1RX/SDI1/SDA/RF2
U1TX/SDO1/SCL/RF3
SCK1/INT0/RF6
IC2/INT2/RD9
15 IC1/INT1/RD8
Note: Pinout subject to change.
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 3
dsPIC30F
dsPIC30F Power Conversion and Motion Control Family
Program
Pins Mem. Bytes/
Instructions
Output
Comp/Std Control
PWM
Motor
SRAM EEPROM Timer Input
A/D 10-bit Quad
500 Ksps Enc
Device
Bytes
Bytes
16-bit Cap
PWM
dsPIC30F2010
dsPIC30F3010
dsPIC30F4012
28
28
28
12K/4K
24K/8K
512
1024
1024
1024
1024
1024
1024
2048
4096
3
5
5
5
5
5
5
5
4
4
4
4
4
8
8
8
2
2
2
4
4
8
8
8
6 ch
6 ch
6 ch
6 ch
6 ch
8 ch
8 ch
8 ch
6 ch
6 ch
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
1
1
1
2
2
2
2
2
1
1
1
1
1
2
2
2
1
1
1
1
1
1
1
1
-
1024
2048
1024
2048
2048
4096
8192
-
48K/16K
24K/8K
6 ch
1
-
dsPIC30F3011 40/44
dsPIC30F4011 40/44
9 ch
48K/16K
36K/12K
96K/32K
144K/48K
9 ch
1
1
2
2
dsPIC30F4010
dsPIC30F5010
dsPIC30F6010
64
64
80
16 ch
16 ch
16 ch
Pin Diagrams
28-Pin SDIP
Part No.: 30F2010 / 30F3010 / 30F4012
MCLR
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AVDD
AVSS
PWM0/RE0
PWM1/RE1
PWM2/RE2
PWM3/RE3
PWM4/RE4
PWM5/RE5
VDD
AN0/VREF+/CN2/RB0
AN1/VREF-/CN3/RB1
AN2/SS1/CN4/RB2
AN3/INDX/CN5/RB3
AN4/QEA/IC7/CN6/RB4
AN5/QEB/IC8/CN7/RB5
VSS
OSC1/CLKIN
OSC2/CLKO/RC15
SOSC2/T2CK/U1ATX/CN1/RC13
SOSC1/T1CK/U1ARX/CN0/RC14
VDD
9
VSS
10
11
12
13
14
U1RX/SDI1/SDA/C1RX/RF2
U1TX/SDO1/SCL/C1TX/RF3
FLTA/INT0/SCK1/OCFA/RE8
OC1/IC1/INT1/RD0
OC2/IC2/INT2/RD1
Note: Pinout subject to change.
Part No.: 30F3011 / 30F4011
40-Pin PDIP
MCLR
AN0/VREF+/CN2/RB0
AN1/VREF-/CN3/RB1
AN2/SS1/CN4/RB2
AN3/INDX/CN5/RB3
AN4/QEA/IC7/CN6/RB4
AN5/QEB/IC8/CN7/RB5
AN6/OCFA/RB6
AVDD
AVSS
1
2
3
4
5
6
7
8
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PWM0/RE0
PWM1/RE1
PWM2/RE2
PWM3/RE3
PWM4/RE4
PWM5/RE5
V
V
DD
9
AN7/RB7
SS
10
11
12
13
14
15
16
17
AN8/RB8
C1RX/RF0
C1TX/RF1
VDD
VSS
OSC1/CLKIN
OSC2/CLKO/RC15
SOSC2/T2CK/U1ATX/CN1/RC13
SOSC1/T1CK/U1ARX/CN0/RC14
FLTA/INT0/RE8
U2RX/RF4
U2TX/RF5
U1RX/SDI1/SDA/RF2
U1TX/SDO1/SCK/RF3
SCK1/RF6
OC2/IC2/INT2/RD1 18
OC1/IC1/INT1/RD0
OC3/RD2
OC4/RD3
19
20
V
SS
V
DD
Note: Pinout subject to change.
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 4
dsPIC30F
Pin Diagrams (Cont.)
44-Pin TQFP
Part No.: 30F3011 / 30F4011
PWM3/RE3
PWM4/RE4
PWM5/RE5
VDD
VSS
NC
C1RX/RF0
C1TX/RF1
U2RXRF4
U2TX/RF5
U1RX/SDI1/SDA/RF2
AN4/QEA/IC7/CN6/RB4
AN5/QEB/IC8/CN7/RB5
33
32
31
30
29
28
27
26
1
2
3
4
5
6
7
8
9
AN6/OCFA/RB6
AN7/RB7
AN8/RB8
dsPIC30FXXXX
NC
VDD
VSS
OSC1/CLKIN
OSC2/CLKO/RC15
SOSC2/T2CK/U1ATX/CN1/RC13
25
24
23
10
11
Note: Pinout subject to change.
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 5
dsPIC30F
Pin Diagrams (Cont.)
Part No.: 30F4010 / 30F5010
64-Pin TQFP
PWM5/RE5
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SOSC1/T1CK/CN0/RC14
SOSC2/T4CK/CN1/RC13
OC1/RD0
PWM6/RE6
PWM7/RE7
2
3
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
4
IC4/INT4/RD11
IC3/INT3/RD10
IC2/FLTB/INT2/RD9
IC1/FLTA/INT1/RD8
VSS
5
6
7
SS2/CN11/RG9
VSS
8
dsPIC30FXXXX
9
OSC2/CLKO/RC15
OSC1/CLKIN
VDD
10
11
12
13
14
15
16
AN5/QEB/IC8/CN7/RB5
AN4/QEA/IC7/CN6/RB4
AN3/INDX/CN5/RB3
AN2/SS1/CN4/RB2
AN1/VREF-/CN3/RB1
AN0/VREF+/CN2/RB0
VDD
SCL/RG2
SDA/RG3
SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
Note: Pinout subject to change.
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 6
dsPIC30F
Pin Diagrams (Cont.)
80-Pin TQFP
Part No.: 30F6010
SOSC1/T1CK/CN0/RC14
SOSC2/CN1/RC13
OC1/RD0
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
PWM5/RE5
PWM6/RE6
2
3
PWM7/RE7
T2CK/RC1
IC4/RD11
4
IC3/RD10
T4CK/RC3
5
IC2/RD9
SCLK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
6
IC1/RD8
7
INT4/RA15
8
INT3/RA14
VSS
9
SS2/CN11/RG9
VSS
10
11
12
dsPIC30FXXXX
OSC2/CLKO/RC15
OSC1/CLKIN
VDD
VDD
FLTA/INT1/RE8
FLTB/INT2/RE9
AN5/QEB/CN7/RB5
13
14
15
16
17
18
19
20
SCL/RG2
SDA/RG3
AN4/QEA/CN6/RB4
AN3/INDX/CN5/RB3
SCK1/INT0/RF6
SDI1/RF7
AN2/SS1/CN4/RB2
AN1/CN3/RB1
SDO1/RF8
U1RX/RF2
U1TX/RF3
AN0/CN2/RB0
Note: Pinout subject to change.
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 7
dsPIC30F
dsPIC30F General Purpose Controller Family
Program Memory
Output
Comp/Std
PWM
SRAM EEPROM Timer Input
CODEC A/D12-bit
Interface 100 Ksps
Device
Pins
Bytes
Bytes
16-bit Cap
Bytes Instructions
**
dsPIC30F3014 40/44 24K
8K
2048
2048
2048
4096
4096
6144
8192
2048
4096
4096
6144
8192
1024
1024
1024
1024
2048
2048
4096
1024
1024
2048
2048
4096
3
5
5
5
5
5
5
5
5
5
5
5
2
4
8
8
8
8
8
8
8
8
8
8
2
4
8
8
8
8
8
8
8
8
8
8
-
13 ch
13 ch
16 ch
16 ch
16 ch
16 ch
16 ch
16 ch
16 ch
16 ch
16 ch
16 ch
2
2
2
2
2
2
2
2
2
2
2
2
1
1
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
-
**
2
dsPIC30F4013 40/44 48K
16K
12K
22K
32K
44K
48K
12K
22K
32K
44K
48K
AC97, I S
1
1
2
2
2
2
1
2
2
2
2
**
2
dsPIC30F4014
dsPIC30F5011
dsPIC30F5012
dsPIC30F6011
dsPIC30F6012
64
64
64
64
64
80
80
80
80
80
36K
66K
AC97, I S
-
2
96K
AC97, I S
132K
144K
36K
-
2
AC97, I S
**
2
dsPIC30F4015
dsPIC30F5013
dsPIC30F5014
dsPIC30F6013
dsPIC30F6014
AC97, I S
66K
-
2
96K
AC97, I S
132K
144K
-
2
AC97, I S
**Proposed Products (others are committed)
Pin Diagrams
Part No.: 30F3014 / 30F4013
40-Pin PDIP
MCLR
AVDD
AVSS
AN9/CSCK/RB9
AN10/CSDI/RB10
AN11/CSDO/RB11
AN12/COFS/RB12
OC1/RD0
1
2
3
4
5
6
7
8
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
AN0/VREF+/CN2/RB0
AN1/VREF-/CN3/RB1
AN2/SS1/CN4/RB2
AN3/CN5/RB3
AN4/IC7/CN6/RB4
AN5/IC8/CN7/RB5
AN6/OCFA/RB6
AN7/RB7
OC2/RD1
VDD
9
AN8/RB8
VSS
10
11
12
13
14
15
16
17
18
19
20
VDD
C1RX/RF0
C1TX/RF1
U2RX/RF4
U2TX/RF5
U1RX/SDI1/SDA/RF2
U1TX/SDO1/SCL/RF3
SCK1/RF6
IC1/INT1/RD8
OC3/RD2
VSS
OSC1/CLKIN
OSC2/CLKO/RC15
SOSC2/T2CK/U1ATX/CN1/RC13
SOSC1/T1CK/U1ARX/CN0/RC14
INT0/RA11
IC2/INT2/RD9
OC4/RD3
VSS
VDD
Note: Pinout subject to change.
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 8
dsPIC30F
Pin Diagrams (Cont.)
Part No.: 30F3014 / 30F4013
44-Pin TQFP
AN12/COFS/RB12
OC1/RD0
OC2/RD1
VDD
VSS
NC
C1RX/RF0
C1TX/RF1
U2RX/RF4
U2TX/RF5
U1RX/SDI1/SDA/RF2
33
32
31
30
29
28
27
26
25
24
23
AN4/IC7/CN6/RB4
AN5/IC8/CN7/RB5
AN6/OCFA/RB6
AN7/RB7
1
2
3
4
5
6
7
8
AN8/RB8
dsPIC30FXXXX
NC
VDD
VSS
OSC1/CLKIN
OSC2/CLKO/RC15
SOSC2/T2CK/U1ATX/CN1/RC13
9
10
11
Note: Pinout subject to change.
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 9
dsPIC30F
Pin Diagrams (Cont.)
Part No.: 30F4014 / 30F5011 / 30F5012 /
30F6011 / 30F6012
64-Pin TQFP
COFS/RG15
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SOSC1/T1CK/CN0/RC14
T2CK/RC1
T3CK/RC2
2
SOSC2/T4CK/CN1/RC13
OC1/RD0
3
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
4
IC4/INT4/RD11
IC3/INT3/RD10
IC2/INT2/RD9
IC1/INT1/RD8
VSS
5
6
7
SS2/CN11/RG9
VSS
8
dsPIC30FXXXX
9
OSC2/CLKO/RC15
OSC1/CLKIN
VDD
VDD
10
11
12
13
14
15
16
AN5/IC8/CN7/RB5
AN4/IC7/CN6/RB4
AN3/CN5/RB3
AN2/SS1/CN4/RB2
AN1/VREF-/CN3/RB1
AN0/VREF+/CN2/RB0
SCL/RG2
SDA/RG3
SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
Note: Pinout subject to change.
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 10
dsPIC30F
Pin Diagrams (Cont.)
80-Pin TQFP
Part No.: 30F4015 / 30F5013 / 30F5014 /
30F6013 / 30F6014
SOSC1/T1CK/CN0/RC14
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
COFS/RG15
T2CK/RC1
SOSC2/CN1/RC13
2
3
OC1/RD0
IC4/RD11
IC3/RD10
IC2/RD9
T3CK/RC2
T4CK/RC3
4
T5CK/RC4
5
SCLK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
6
IC1/RD8
7
INT4/RA15
8
INT3/RA14
VSS
9
dsPIC30FXXXX
SS2/CN11/RG9
VSS
10
11
12
OSC2/CLKO/RC15
OSC1/CLKIN
VDD
VDD
INT1/RA12
INT2/RA13
AN5/CN7/RB5
13
14
15
16
17
18
19
20
SCL/RG2
SDA/RG3
AN4/CN6/RB4
AN3/CN5/RB3
SCK1/INT0/RF6
SDI1/RF7
AN2/SS1/CN4/RB2
AN1/CN3/RB1
SDO1/RF8
U1RX/RF2
U1TX/RF3
AN0/CN2/RB0
Note: Pinout subject to change.
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 11
dsPIC30F
Table of Contents
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
Device Overview .................................................................................................................................................................... 15
Core Architecture Overview ................................................................................................................................................... 19
Memory Organization............................................................................................................................................................. 33
FLASH Program Memory....................................................................................................................................................... 45
Data EEPROM Memory......................................................................................................................................................... 55
DSP Engine............................................................................................................................................................................ 61
Address Generator Units........................................................................................................................................................ 69
Exception Processing............................................................................................................................................................. 83
I/O Ports............................................................................................................................................................................... 115
Timer1 Module ..................................................................................................................................................................... 135
Timer2/3 Module .................................................................................................................................................................. 139
Timer4/5 Module .................................................................................................................................................................. 145
Input Capture Module........................................................................................................................................................... 151
Output Compare Module...................................................................................................................................................... 155
Quadrature Encoder Interface (QEI) Module ....................................................................................................................... 163
Motor Control PWM Module................................................................................................................................................. 173
SPI Module........................................................................................................................................................................... 197
I2C Module........................................................................................................................................................................... 209
Universal Asynchronous Receiver Transmitter (UART) Module .......................................................................................... 233
CAN Module......................................................................................................................................................................... 245
Data Converter Interface (DCI) Module ............................................................................................................................... 247
12-bit Analog-to-Digital Converter (A/D) Module.................................................................................................................. 265
10-bit High speed Analog-to-Digital Converter (A/D) Module .............................................................................................. 277
System Integration ............................................................................................................................................................... 293
Instruction Set Summary...................................................................................................................................................... 311
Development Support .......................................................................................................................................................... 321
Electrical Characteristics...................................................................................................................................................... 323
DC and AC Characteristics Graphs and Tables................................................................................................................... 325
Packaging Information ......................................................................................................................................................... 327
9.0
10.0
11.0
12.0
13.0
14.0
15.0
16.0
17.0
18.0
19.0
20.0
21.0
22.0
23.0
24.0
25.0
26.0
27.0
28.0
29.0
Index .................................................................................................................................................................................................. 337
On-Line Support................................................................................................................................................................................. 345
Reader Response.............................................................................................................................................................................. 346
Product Identification System ............................................................................................................................................................ 347
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 12
dsPIC30F
TO OUR VALUED CUSTOMERS
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The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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2002 Microchip Technology Inc.
Advance Information
DS70032B-page 13
dsPIC30F
NOTES:
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 14
dsPIC30F
Table 1-1 provides a brief description of device I/O
pinouts and the functions that may be multiplexed to a
port pin. Multiple functions may exist on one port pin.
When multiplexing occurs, the peripheral module’s
functional requirements may force an override of the
data direction of the port pin.
1.0
DEVICE OVERVIEW
This document contains device family specific informa-
tion for the dsPIC30F family of Digital Signal Controller
(DSC) devices. The dsPIC30F devices contain exten-
sive Digital Signal Processor (DSP) functionality within
a high performance 16-bit Microcontroller (MCU) archi-
tecture.
TABLE 1-1:
PINOUT I/O DESCRIPTIONS
Pin
Type
Buffer
Type
Pin Name
Description
AN0 - AN15
I
Analog
Analog input channels.
AN0 and AN1 are also used for device programming data
and clock inputs, respectively.
AVDD
AVSS
CLKIN
P
P
I
P
P
Positive supply for analog module.
Ground reference for analog module.
ST/CMOS
External clock source input. Always associated with OSC1
pin function.
CLKO
O
-
Oscillator crystal output. Connects to crystal or resonator in
Crystal Oscillator mode. Optionally functions as CLKOUT in
RC and EC modes. Always associated with OSC2 pin
function.
CN0 - CN23
I
ST
Input change notification inputs.
Can be software programmed for internal weak pull-ups on
all inputs.
COFS
CSCK
CSDI
I/O
I/O
I
ST
ST
ST
-
Data Converter Interface frame synchronization pin.
Data Converter Interface serial clock input/output pin.
Data Converter Interface serial data input pin.
Data Converter Interface serial data output pin.
CSDO
O
C1RX
C1TX
C2RX
C2TX
I
O
I
ST
-
ST
-
CAN1 bus receive pin.
CAN1 bus transmit pin.
CAN2 bus receive pin.
CAN1 bus transmit pin
O
IC1 - IC8
I
ST
Capture inputs 1 through 8.
INDX
QEA
I
I
ST
ST
Quadrature Encoder Index Pulse input.
Quadrature Encoder Phase A input in QEI mode.
Auxiliary Timer External Clock/Gate input in Timer mode.
Quadrature Encoder Phase A input in QEI mode.
Auxiliary Timer External Clock/Gate input in Timer mode.
Position Up/Down Counter Direction State.
QEB
I
ST
UPDN
O
CMOS
INT0
INT1
INT2
INT3
INT4
I
I
I
I
I
ST
ST
ST
ST
ST
External Interrupt 0.
External Interrupt 1.
External Interrupt 2.
External Interrupt 3.
External Interrupt 4.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open Drain (no P diode to VDD)
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 15
dsPIC30F
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin
Type
Buffer
Type
Pin Name
Description
FLTA
FLTB
I
I
ST
ST
PWM Fault A input.
PWM Fault B input.
PWM output 0.
PWM output 1.
PWM output 2.
PWM output 3.
PWM output 4.
PWM output 5.
PWM output 6.
PWM output 7.
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
O
O
O
O
O
O
O
O
-
-
-
-
-
-
-
-
MCLR
I/P
ST
Master Clear (Reset) input or programming voltage input.
This pin is an active low RESET to the device.
OCFA
OCFB
OC1
OC2
OC3
OC4
OC5
OC6
OC7
OC8
I
I
ST
ST
Compare Fault A input (for Compare channels 1, 2, 3 and 4).
Compare Fault B input (for Compare channels 5, 6, 7 and 8).
Compare1 output.
Compare2 output.
Compare3 output.
Compare4 output.
Compare5 output.
Compare6 output.
Compare7 output.
O
O
O
O
O
O
O
O
-
-
-
-
-
-
-
-
Compare8 output.
OSC1
I
ST/CMOS
Oscillator crystal input. ST buffer when configured in RC
mode; CMOS otherwise.
OSC2
I/O
-
Oscillator crystal output. Connects to crystal or resonator in
Crystal Oscillator mode. Optionally functions as CLKOUT in
RC and EC modes.
RA0 - RA7
RA9 - RA15
I/O
I/O
ST
ST
PORTA is a bi-directional I/O port.
RB0 - RB15
I/O
ST
PORTB is a bi-directional I/O port.
PORTC is a bi-directional I/O port.
RC0 - RC4
RC13 - RC15
I/O
I/O
ST
ST
RD0 - RD15
RE0 - RE9
I/O
I/O
ST
ST
PORTD is a bi-directional I/O port.
PORTE is a bi-directional I/O port.
PORTF is a bi-directional I/O port.
RF0 - RF8
RF12 - RF13
I/O
I/O
ST
ST
RG0 - RG3
RG6 - RG9
RG12 - RG15
I/O
I/O
I/O
ST
ST
ST
PORTG is a bi-directional I/O port.
SCK1
SDI1
SDO1
SS1
SCK2
SDI2
SDO2
SS2
I/O
ST
ST
-
ST
ST
ST
-
Synchronous serial clock input/output for SPI1.
SPI1 Data In.
SPI1 Data Out.
SPI1 Slave Synchronization.
Synchronous serial clock input/output for SPI2.
SPI2 Data In.
I
O
I
I/O
I
O
I
SPI2 Data Out.
ST
SPI2 Slave Synchronization.
2
SCL
SDA
I/O
I/O
ST
ST
Synchronous serial clock input/output for I C.
Synchronous serial data input/output for I C.
2
SOSC1
SOSC2
I
O
ST/CMOS
-
32 kHz low power oscillator crystal input; CMOS otherwise.
32 kHz low power oscillator crystal output.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open Drain (no P diode to VDD)
DS70032B-page 16
AdvanceInformation
2002 Microchip Technology Inc.
dsPIC30F
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin
Type
Buffer
Type
Pin Name
Description
Timer1 external clock input.
Timer2 external clock input.
Timer3 external clock input.
Timer4 external clock input.
Timer5 external clock input.
T1CK
T2CK
T3CK
T4CK
T5CK
I
I
I
I
I
ST
ST
ST
ST
ST
U1RX
U1TX
U1ARX
U1ATX
U2RX
U2TX
I
O
I
O
I
ST
-
ST
-
ST
-
UART1 Receive.
UART1 Transmit.
UART1 Alternate Receive.
UART1 Alternate Transmit.
UART2 Receive.
O
UART2 Transmit.
VDD
P
P
I
-
Positive supply for logic and I/O pins.
Ground reference for logic and I/O pins.
Analog Voltage Reference (High) input.
Analog Voltage Reference (Low) input.
VSS
-
VREF+
VREF-
Analog
Analog
I
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open Drain (no P diode to VDD)
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 17
dsPIC30F
NOTES:
DS70032B-page 18
AdvanceInformation
2002 Microchip Technology Inc.
dsPIC30F
The X AGU also supports bit-reversed addressing on
destination effective addresses, to greatly simplify input
or output data reordering for radix-2 FFT algorithms.
Refer to Section 7.0 for details on modulo and bit-
reversed addressing.
2.0
2.1
CORE ARCHITECTURE
OVERVIEW
Core Overview
The core has a 24-bit instruction word. The Program
Counter (PC) is 24-bits wide with the Least Significant
(LS) bit always clear (see Section 3.1), and the Most
Significant (MS) bit is ignored during normal program
execution, except for certain specialized instructions.
Thus, the PC can address up to 4M instruction words
of user program space. An instruction pre-fetch mech-
anism is used to help maintain throughput. Uncondi-
tional overhead free program loop constructs are
supported using the DOand REPEATinstructions, both
of which are interruptible at any point.
The core supports Inherent (no operand), Relative, Lit-
eral, Memory Direct, Register Direct, Register Indirect
and Register Offset Addressing modes. Instructions
are associated with predefined addressing modes,
depending upon their functional requirements.
For most instructions, the core is capable of executing
a data (or program data) memory read, a working reg-
ister (data) read, a data memory write and a program
(instruction) memory read per instruction cycle. As a
result, 3-operand instructions are supported, allowing
C = A+B operations to be executed in a single cycle.
The working register array consists of 16 x 16-bit regis-
ters, each of which can act as data, address or offset
registers. One working register (W15) operates as a
software stack pointer for interrupts and calls.
A DSP engine has been included to significantly
enhance the core arithmetic capability and throughput.
It features a high speed 16-bit by 16-bit multiplier, a
40-bit ALU, two 40-bit saturating accumulators and a
40-bit bi-directional barrel shifter. Data in the accumu-
lator or any working register can be shifted up to 15 bits
right or 16 bits left in a single cycle. The DSP instruc-
tions operate seamlessly with all other instructions and
have been designed for optimal real-time performance.
The MAC class of instructions can concurrently fetch
two data operands from memory, while multiplying two
W registers. To enable this concurrent fetching of data
operands, the data space is split for these instructions
and linear for all others. This is achieved in a transpar-
ent and flexible manner, through dedicating certain
working registers to each address space for the MAC
class of instructions.
The data space is 64 Kbytes (32K words), and is split
into two blocks, referred to as X and Y data memory.
Each block has its own independent Address Genera-
tion Unit (AGU). Most instructions operate solely
through the X memory AGU, which provides the
appearance of a single unified data space. The
Multiply-Accumulate (MAC) class of dual source DSP
instructions operate through both the X and Y AGUs,
splitting the data address space into two parts (see
Section 3.2). The X and Y data space boundary is
device specific and cannot be altered by the user. Each
data word consists of 2 bytes, and most instructions
can address data either as words or bytes.
There are two methods of accessing data stored in pro-
gram memory:
The core does not support a multi-stage instruction
pipeline. However, a single stage instruction pre-fetch
mechanism is used, which accesses and partially pre-
decodes instructions a cycle ahead to maximize avail-
able execution time. Most instructions execute in a sin-
gle cycle, with certain exceptions as outlined in
Section 2.3.2.
• The upper 32 Kbytes of data space memory can
optionally be mapped into the lower half (user
space) of program space at any 16K program
word boundary, defined by the 8-bit Program
Space Visibility Page (PSVPAG) register. This lets
any instruction access program space as if it were
data space, with the sole limitation that the access
requires an additional cycle. Moreover, only the
lower 16 bits of each instruction word can be
accessed using this method.
The core features a vectored exception processing
structure for traps and interrupts, with 62 independent
vectors. The exceptions consist of up to 8 traps (of
which 3 are reserved) and 54 interrupts. Each interrupt
is prioritized based on a user assigned priority between
0 and 7 (0 being the lowest priority and 7 being the
highest) in conjunction with a predetermined ‘natural
order’.
• Linear indirect access of 32K word pages within
program space is also possible using any working
register, via table read and write instructions.
Table read and write instructions can be used to
access all 24 bits of an instruction word.
A block diagram of the core is shown in Figure 2-1.
Overhead-free circular buffers (modulo addressing) are
supported in both X and Y address spaces. This is pri-
marily intended to remove the loop overhead for DSP
algorithms.
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 19
dsPIC30F
FIGURE 2-1:
dsPIC30F CPU CORE BLOCK DIAGRAM
Inst. Type
Address Decode
Address Decode
X
Y
Data RAM
Data RAM
Data Latch
16
Data Latch
16
Y Data
X Address
AccA
AccB
16
40
40
40-bit Add/Sub
40
40
40
16
32
16
32
32
32
16 x 16 Multiplier
Operand Latches
24
16
16
Table Data
Divide Shifter
& Incrementer
24
W0
W Array
X Address
(16 x 16-bit regs)
Byte/Word
Select
Data Latch
24-bit wide
Program Memory
Up to 4M Words
(including
W15 / Stack Ptr.
Table & Data Space
Page Registers
1
Divide Quotient
Eval. and Control
1
configuration space)
Program Data EA
Address Generator
16
16
Address Latch
ALU<8/16>
1
23
Status 8/16
Single Bit
Shifter
23
23
Program Counter
23
16
PCT
PCL
PCU
PCH
PCLATU
16
8
PC Register R/W
DO Registers R/W
To/From Peripherals/SFRs
DS70032B-page 20
AdvanceInformation
2002 Microchip Technology Inc.
dsPIC30F
The stack pointer always points to the first available
free word and grows from lower addresses towards
higher addresses. It pre-decrements for stack pops
(reads) and post-increments for stack pushes (writes),
as shown in Figure 2-2. Note that for a PC push during
any CALL instruction, the MSB of the PC is zero
extended before the push, ensuring that the MSB is
always clear.
2.2
Programmer’s Model
The programmer’s model is shown in Figure 2-3 and
consists of 16 x 16-bit working registers (W0 through
W15), 2 x 40-bit accumulators (AccA and AccB),
STATUS register (SR), Data Table Page register
(TBLPAG), Program Space Visibility Page register
(PSVPAG), DO and REPEAT registers (DOSTART,
DOEND, DCOUNT and RCOUNT), and Program
Counter (PC). The working registers can act as data,
address or offset registers. All registers are memory
mapped. W0 acts as the W register for file register
addressing.
Note: A PC push during exception processing
will concatenate the SRL register to the
MSB of the PC prior to the push.
There is a Stack Limit register (SPLIM) associated with
the stack pointer. SPLIM is uninitialized at RESET. As
is the case for the stack pointer, SPLIM<0> is forced to
0 because all stack operations must be word aligned.
Whenever an effective address (EA) is generated using
W15 as a source or destination pointer, the address
thus generated is compared with the value in SPLIM. If
the EA is found to be greater than the contents of
Most of these registers have a shadow register associ-
ated with them, as shown in Figure 2-3. The shadow
register is used as a temporary holding register and
can transfer its contents to or from its host register upon
some event occurring. None of the shadow registers
are accessible directly. The following rules apply for
transfer of registers into and out of shadows.
SPLIM, then
generated.
a Stack Pointer Overflow trap is
• PUSH.sand POP.s
W0...W14, TBLPAG, PSVPAG, SR (DC, N, OV, SZ
and C bits only) transferred
Similarly, a Stack Pointer Underflow trap is generated
when the stack pointer address is found to be less than
0x0800, thus preventing the stack from interfering with
the Special Function Register (SFR) space.
• DOinstruction
DA bit, DOSTART, DOEND, DCOUNT shadows
pushed on loop start, popped on loop end
When a byte operation is performed on a working reg-
ister, only the Least Significant Byte of the target regis-
ter is affected. However, a benefit of memory mapped
working registers is that both the Least and Most Sig-
nificant Bytes can be manipulated through byte wide
data memory space accesses.
FIGURE 2-2:
CALLSTACK FRAME
0x0000
15
0
2.2.1
SOFTWARE STACK POINTER/
FRAME POINTER
PC<15:0>
00000000 PC<23:16>
<Free Word>
W15 (before CALL)
W15 (after CALL)
W15 is the dedicated software stack pointer (SP), and
will be automatically modified by exception processing
and subroutine calls and returns. However, W15 can be
referenced by any instruction in the same manner as all
other W registers. This simplifies the reading, writing
and manipulation of the stack pointer (e.g., creating
stack frames).
POP : [--W15]
PUSH : [W15++]
Note: In order to protect against misaligned stack
accesses, W15<0> is always clear.
W15 is initialized to 0x0800 during a RESET. The user
may reprogram the SP during initialization to any loca-
tion within data space.
W14 has been dedicated as a stack frame pointer as
defined by the LNK and ULNK instructions. However,
W14 can be referenced by any instruction in the same
manner as all other W registers.
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 21
dsPIC30F
2.2.2
STATUS REGISTER
2.2.2.1
Sticky Z (SZ) Status Bit
For most instructions, the SZ status bit is not sticky.
Instructions that use a carry/borrow input will only be
able to clear SZ (for a non-zero result) and can never
set it. A multi-precision sequence of instructions (start-
ing with an instruction with no carry/borrow input) will
thus, automatically logically AND the successive
results of the zero test. All results must be zero for the
SZ flag to remain set by the end of the sequence.
The dsPIC™ core has a 16-bit status register (SR), the
LS Byte of which is referred to as the STATUS register
low byte (SRL). A detailed description is shown in
Register 2-1.
Note: When the memory mapped STATUS regis-
ter is the destination address for an opera-
tion which affects any of the SR bits, data
writes are disabled to all bits.
The following instructions feature sticky operation of
SRL contains all the MCU ALU operation status flags
(including the ‘sticky Z’ bit, SZ), as well as the CPU
Interrupt Priority status bits, IPL<2:0>, and the
REPEAT active status bit, RA. During exception pro-
cessing, SRL is concatenated with the MS Byte of the
PC to form a complete word value which is then
stacked.
the SZ flag: ADDC, CPB, SUBBand SUBBR.
2.2.3
PROGRAM COUNTER
The Program Counter is 24-bits wide. Bit 0 is always
clear. PC<23> may be used to access configuration
fuse settings, using table read and table write instruc-
tions. Bit 23 is also clear for normal user program mem-
ory access. Therefore, the PC can address up to 4M
instruction words.
The upper byte of the STATUS register contains the
DSP Adder/Subtractor status bits, the DO Loop Active
bit (DA) and the Digit Carry (DC) status bit.
Most SR bits are read/write. Exceptions are:
1. The DA bit: DA is read and clear only, because
accidentally setting it could cause erroneous
operation.
2. The RA bit: RA is a read only bit, because acci-
dentally setting it could cause erroneous opera-
tion. RA is only set on entry into a repeat loop,
and cannot be directly cleared by software.
3. The OV, OA, OB and OAB bits: These bits are
read only and can only be set by the DSP engine
overflow logic.
4. The SA, SB and SAB bits: These are read and
clear only and can only be set by the DSP
engine saturation logic. They are ‘sticky’, i.e.,
once set, they remain set until cleared by the
user, irrespective of the results from any subse-
quent DSP operations.
Note: Clearing the SAB bit will also clear both the
SA and SB bits.
DS70032B-page 22
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dsPIC30F
FIGURE 2-3:
PROGRAMMER’S MODEL
D15
D0
W0 / WREG
PUSH.S Shadow
DO Shadow
W1
W2
W3
W4
W5
Legend
DSP Operand
Registers
W6
W7
Working Registers
W8
W9
W10
DSP Address
Registers
W11
W12 / DSP Offset
W13 / DSP Write Back
W14 / Frame Pointer
W15* / Stack Pointer
* W15 & SPLIM not shadowed
Stack Pointer Limit Register
SPLIM*
AD15
AD39
AD31
AD0
DSP
Accumulators
AccA
AccB
PC23
7
PC0
Program Counter
0
TBLPAG
Data Table Page Address
7
0
PSVPAG
Program Space Visibility Page Address
15
0
0
RCOUNT
REPEAT Loop Counter
DO Loop Counter
15
DCOUNT
23
23
0
DOSTART
DOEND
DO Loop Start Address
DO Loop End Address
15
0
Core Configuration Register
CORCON
OA OB SA SB OAB SAB DA DC
SRH
IPL0 RA
N
OV SZ
C
IPL2 IPL1
Status Register
SRL
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REGISTER 2-1:
STATUS REGISTER (SR)
Upper Half (SRH):
R/W-0
OA
R/W-0
OB
R/W-0
SA
R/W-0
SB
R/W-0
OAB
R/W-0
SAB
R-0
DA
R-0
DC
bit 15
bit 8
Lower Half (SRL):
R/W-1
IPL2
R/W-1
IPL1
R/W-1
IPL0
R-0
RA
R/W-0
N
R/W-0
OV
R/W-0
SZ
R/W-0
C
bit 7
bit 0
bit 15
bit 14
bit 13
OA: Accumulator A Overflow Status bit
1= Accumulator A overflowed
0= Accumulator A not overflowed
OB: Accumulator B Overflow Status bit
1= Accumulator B overflowed
0= Accumulator B not overflowed
SA: Accumulator A Saturation Status bit
1= Accumulator A is saturated or has been saturated at some time
0= Accumulator A is not saturated
Note: This bit may be read or cleared, but not set.
bit 12
SB: Accumulator B Saturation Status bit
1= Accumulator B is saturated or has been saturated at some time
0= Accumulator B is not saturated
Note: This bit may be read or cleared, but not set.
bit 11
bit 10
OAB: OA || OB Combined Accumulator Overflow Status bit
1= Accumulators A or B have overflowed
0= Neither Accumulators A or B have overflowed
SAB: SA || SB Combined Accumulator Status bit
1= Accumulators A or B are saturated or have been saturated at some time in the past
0= Neither Accumulator A or B are saturated
Note: This bit may be cleared or read, but not set. Clearing this bit will clear SA and SB.
bit 9
bit 8
DA: DO Loop Active bit
1= DO loop in progress
0= DO loop not in progress
Note: This bit may be read or cleared, but not set.
DC: MCU ALU Half-Carry bit
1= A carry-out from the 4th low order bit (for byte sized data) or 8th low order bit (for word sized data) of
the result occurred
0= No carry-out from the 4th low order bit (for byte sized data) or 8th low order bit (for word sized data) of
the result occurred
bit 7-5
IPL<2:0>: CPU Interrupt Priority Status bits
111= Level 7 interrupts enabled
110= Level 6 to 7 interrupts enabled
101= Level 5 to 7 interrupts enabled
100= Level 4 to 7 interrupts enabled
011= Level 3 to 7 interrupts enabled
010= Level 2 to 7 interrupts enabled
001= Level 1 to 7 interrupts enabled
000= Level 0 to 7 interrupts enabled
bit 4
RA: REPEAT Loop Active Status bit
1= REPEAT loop in progress
0= REPEAT loop not in progress
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REGISTER 2-1:
STATUS REGISTER (SR) (Continued)
bit 3
N: MCU ALU Negative bit
This bit is used for signed arithmetic (2’s complement). It indicates whether the result of the ALU operation
was negative (ALU MSb = 1).
1= Result was negative
0= Result was non-negative (zero or positive)
bit 2
OV: MCU ALU Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the magnitude, which
causes the sign bit to change state.
1= Overflow occurred for signed arithmetic (in this arithmetic operation)
0= No overflow occurred
Example 1: w1 before instruction = 0x7fff. OV = 0.
Instruction executed: ADD #1,w1
w1 after instruction = 0x8000. OV = 1.
Example 2: w1 before instruction = 0xffff. OV = 0.
Instruction executed: ADD #1,w1
w1 after instruction = 0x0000. OV = 1.
bit 1
bit 0
SZ: MCU ALU ‘sticky’ Zero bit
1= An ADDC, CPB, SUBBor SUBBRoperation which affects the SZ bit has set it at some time in the past
0= The most recent operation which affects the SZ bit has cleared it (i.e., generated a non-zero result)
For all other operations, this bit indicates whether the most recent operation has produced a zero result.
C: MCU ALU Carry/Borrow bit
1= A carry-out from the Most Significant bit of the result occurred
0= No carry-out from the Most Significant bit of the result occurred
For Borrow, the polarity is reversed.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
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A consequence of this degree of pipelining is that data
dependencies can now occur between completing
destination write EA operations and already started
source read EA calculations. Data dependencies are
discussed in detail in Section 7.
2.3
Instruction Flow
2.3.1
CLOCKING SCHEME
Each instruction cycle (TCY) is comprised of four Q
cycles (Q1-Q4). The four-phase Q cycles provide the
timing/delineation for the phases of the instruction
cycle, such as Decode, Read, Process Data, and
Write. Figure 2-4 shows the relationship of the Q
cycles to the instruction cycle for both MCU and DSP
instructions. The four Q cycles that make up an execu-
tion instruction cycle (TCY) can be generalized as:
FIGURE 2-4:
BASIC CORE TIMING
MCU Ops
MAC Class Ops
Q1
Q2
Q1:
Instruction decode or forced NOP(FNOP)
Data space read start
Destination EA calculation start
Q3
Q4
Q2:
X and Y X/Y
Instruction decode or FNOP
Data space read complete
Destination EA calculation
Data
Data
Data
Data
Space
Write
Space Space Space
Read
Write
Read
Read Operation
Read Operation
Q3:
Next instruction pre-decode start
Next op read EA calculation start
Process the Data or FNOP
Data space write start
Instruction Pre-Decode
Write Operation
Write Operation
Instruction Decode
Q4:
Program Space
Read
Program Space
Read
Next instruction pre-decode
Next op read EA calculation
Data space write complete or FNOP
TCY1
TCY2
Note: From a Q cycle perspective, the DSP
instructions differ from the MCU instruc-
tions in their ability to perform two simulta-
neous source data reads during the Q1/Q2
access from X and Y data space.
2.3.2
INSTRUCTION FETCH AND
PRE-DECODE MECHANISM
The core does not support an instruction pipeline. A
pre-fetching mechanism accesses instructions a cycle
ahead to maximize available execution time and to
allow for some pre-decode to occur. A conceptual tim-
ing diagram, demonstrating the pre-fetch mechanism,
is shown in Figure 2-5.
The total time required for EA calculation and data
space access is 4 Q clocks, for both read and write
accesses. This device does not support any form of
dual ported data space, so read and write operations
cannot occur simultaneously. As a result, at least a
portion of these operations occur concurrently across
instruction boundaries. Data space accesses are par-
tially pipelined.
There are separate AGUs for X reads and X writes so
as to enable concurrent operation. The X RAGU
(Read AGU) and X WAGU (Write AGU) serve this pur-
pose and are functionally identical, with the exception
that bit-reversed addressing is only supported on the X
WAGU. There is only a single Y AGU.
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FIGURE 2-5:
CLOCK/INSTRUCTION CYCLE
Q2
Q3
Q4
Q2
Q3
Q4
Q2
Q3
Q4
Q1
Q1
Q1
OSC1
Q1
Q2
Q3
Internal
Phase
Clock
Q4
PC
PC
PC+2
PC+4
Fetch INST (PC)
Execute INST (PC-2)
Fetch INST (PC+2)
Execute INST (PC)
Fetch INST (PC+4)
Execute INST (PC+2)
Most instructions execute in a single cycle. Exceptions
are:
During the instruction pre-decode, the core determines
if any address register data dependency is imminent
across an instruction boundary. It compares the work-
ing register (if any) used for the destination EA (effec-
tive address) of the instruction currently being
executed, with that about to be used by the source EA
(if any) of the pre-fetched instruction. When it
observes a match between the destination and source
registers, a set of rules is applied to decide (by the fall-
ing edge of Q3) whether or not to stall the instruction
by one cycle. See Section 7.0 for more details on data
dependencies.
1. Flow control instructions and interrupts where
the IR (Instruction register) and pre-fetch buffer
must be flushed and refilled.
2. Instructions where one operand is to be fetched
from program space (using any method). These
operations consume 2 cycles (with the notable
exception of instructions executed within a
REPEAT loop; in this case, it would execute in 1
cycle).
3. Instructions where an effective address calcula-
tion dependency has been detected and an
instruction stall must be inserted.
Due to the instruction pre-fetch mechanism, each
instruction effectively executes in one cycle. This
remains true until a flow change occurs, which will
require the pre-fetch register (ROMLATCH) to be dis-
carded and refilled again from the new instruction
thread.
Most instructions access data as required during
instruction execution. Instructions which utilize the
multiplier array must have data available at the begin-
ning of the instruction cycle. Consequently, this data
must be pre-fetched, usually by the preceding instruc-
tion, resulting in a simple out of order data processing
model.
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5. Two-word instructions for CALL and GOTO. In
these instructions, the fetch after the instruction
provides the remainder of the jump or call desti-
nation address. These instructions require 2
cycles to execute, 1 for fetching the 2 instruction
words (enabled by a high speed path on the sec-
ond fetch), and 1 for the subsequent pipeline
flush, as shown in Figure 2-10.
2.3.3
INSTRUCTION FLOW TYPES
There are 8 types of instruction flows:
1. Normal one-word, one-cycle pipelined instruc-
tions. These instructions take one effective cycle
to execute, as shown in Figure 2-6.
2. One-word, two-cycle pipeline flush instructions.
These instructions include the relative
branches, relative call, skips and returns. When
an instruction changes the PC (other than to
increment it), the pipelined fetch is discarded.
This causes the instruction to take two effective
cycles to execute as shown in Figure 2-7.
6. Two-word instructions for DO. In these instruc-
tions, the fetch after the instruction contains an
address offset. This address offset is added to
the first instruction address to generate the last
loop instruction address. Therefore, these
instructions require two cycles, as shown in
Figure 2-11.
3. One-word, two-cycle instructions that are not
flow control instructions. The only instructions of
this type are the MOV.D(load and store double
word) instructions, as shown in Figure 2-8.
7. Instructions that are subjected to a stall due to a
data dependency between the X RAGU and X
WAGU. An additional cycle is inserted to resolve
the resource conflict, as shown in Figure 2-11.
Instruction stalls caused by data dependencies
are further discussed in Section 7.0.
4. Table read/write instructions. These instructions
will suspend the fetching to insert a read or write
cycle to the program memory. The instruction
fetched while executing the table operation is
saved for 1 cycle and executed in the cycle
immediately after the table operation, as shown
in Figure 2-9.
8. Interrupt recognition execution. Refer to
Section 8.0 for details on interrupts.
FIGURE 2-6:
INSTRUCTION PIPELINE FLOW - 1-WORD, 1-CYCLE
TCY0
TCY1
Execute 1
Fetch 2
TCY2
TCY3
TCY4
TCY5
1. MOV.b #0x55,W0
2. MOV.b #0x35,W1
3. ADD.b W0,W1,W2
Fetch 1
Execute 2
Fetch 3
Execute 3
FIGURE 2-7:
INSTRUCTION PIPELINE FLOW - 1-WORD, 2-CYCLE
TCY0
TCY1
Execute 1
Fetch 2
TCY2
TCY3
TCY4
TCY5
1. MOV #0x55,W0
2. BTSC W1,#3
Fetch 1
Execute 2
Skip Taken
3. ADD W0,W1,W2
4. BRA SUB_1
Fetch 3
Flush
Fetch 4
Execute 4
Fetch 5
5. SUB W0,W1,W3
Flush
Fetch SUB_1
6. Instruction @ address SUB_1
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FIGURE 2-8:
INSTRUCTION PIPELINE FLOW - 1-WORD, 2-CYCLE MOV.DOPERATIONS
TCY0
TCY1
Execute 1
Fetch 2
TCY2
TCY3
TCY4
TCY5
1. MOV W0,0x1234
2. MOV.D [W0++],W1
Fetch 1
Execute 2
R/W Cycle 1
3. MOV W1,0x00AA
Fetch 3
Execute 2
R/W Cycle2
3a. Stall
Stall
Execute 3
Fetch 4
4. MOV 0x0CC, W0
Execute 4
FIGURE 2-9:
INSTRUCTION PIPELINE FLOW - 1-WORD, 2-CYCLE TABLE OPERATIONS
TCY0
TCY1
Execute 1
Fetch 2
TCY2
TCY3
TCY4
TCY5
1. MOV #0x1234,W0
2. TBLRDL [W0++],W1
3. MOV #0x00AA,W1
Fetch 1
Execute 2
Fetch 3
Execute 2
Read Cycle
3a. Table Operation
4. MOV #0x0CC,W0
Bus Read Execute 3
Fetch 4
Execute 4
FIGURE 2-10:
INSTRUCTION PIPELINE FLOW - 2-WORD, 2-CYCLE GOTO, CALL
TCY0
TCY1
Execute 1
Fetch 2L
TCY2
TCY3
TCY4
TCY5
1. MOV #0x1234,W0
2. GOTO LABEL
Fetch 1
Update PC
2a. Second Word
Fetch 2H NOP
Fetch
LABEL
3. Instruction @ address LABEL
Execute
LABEL
4. BSET W1, #BIT3
Fetch 4
Execute 4
FIGURE 2-11:
INSTRUCTION PIPELINE FLOW - 2-WORD, 2-CYCLE DO, DOW
TCY0
TCY1
Execute 1
Fetch 2L
TCY2
TCY3
TCY4
1. PUSH DOEND
Fetch 1
2. DO LABEL,#COUNT
2a. Second Word
NOP
Fetch 2H Execute 2
Fetch 3
3. 1st Instruction of Loop
Execute 3
FIGURE 2-12:
INSTRUCTION PIPELINE FLOW - 1-WORD, 2-CYCLE WITH INSTRUCTION STALL
TCY0
TCY1
TCY2
TCY3
TCY4
TCY5
1. MOV.b W0,[W1]
2. MOV.b [W1],PORTB
2a. Stall (NOP)
Fetch 1
Execute 1
Fetch 2
NOP
Stall
Execute 2
Fetch 3
3. MOV.b W0,PORTB
Execute 3
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2.4.3
REPEAT EARLY TERMINATION
2.4
Program Loop Control
Clearing the RA bit in the stacked SR from within an
ISR is a method to force an interrupted loop to termi-
nate early (subject to one more iteration) after the
interrupt or trap returns. RA is not software modifiable
within the SR, but will be updated with whatever value
is present in the stacked SRL during a return. Even if
the RCOUNT ‘decrement then test’ does not indicate a
loop end condition (RCOUNT = 0), RA will remain
clear and will force the loop to exit. A subsequent
REPEAT instruction will set RA, but will also update
RCOUNT with the new loop count.
The dsPIC core supports both REPEATand DOinstruc-
tion constructs to provide unconditional automatic pro-
gram loop control.
2.4.1
REPEAT LOOP CONSTRUCT
The REPEAT instruction will cause the RA (Repeat
Active) flag bit to be set if the REPEAT count is greater
than 0. If RA = 1, PC increments and instruction
fetches are inhibited until the REPEAT loop counter,
RCOUNT, reaches 0 (at which point RA will also be
cleared by the loop count hardware).
2.4.4
DO LOOP CONSTRUCT
The REPEAT instruction causes the instruction imme-
diately following it to be repeated a fixed number of
times as defined by either:
The DO instruction executes instructions following the
DO until an end address is reached, at which time
instruction execution will start again at the instruction
immediately following the DO. This will be repeated a
finite number of times as defined by either:
- a fixed, 14-bit literal encoded in the
instruction, or
- the variable contents of bits <13:0> of a W
register declared within the instruction
- a fixed, 14-bit literal encoded in the first word
of the instruction, or
The loop count is held in the 16-bit RCOUNT register
(which is memory mapped) and is thus, user accessi-
ble. It is initialized by the REPEATinstruction during Q2.
- the variable contents of bits <13:0> of a W
register declared within the instruction
The instruction to be repeated is pre-fetched during
the REPEATinstruction and held in the ROMLATCH. It
is not fetched again for all subsequent iterations, and
the Instruction register is loaded from the locked
ROMLATCH.
The instructions within a loop (including the instruction
immediately preceding the last instruction in the loop)
need not be executed in the same order in which they
appear in program memory, i.e., branches within a loop
are allowed. Moreover, the loop end address may be
smaller than the start address.
Note: For a loop count value of 0, REPEATwill be
executed like a NOP. The RA status bit is
not set, but RCOUNT is loaded with the
value 0. However, the instruction within the
REPEAT loop is executed once.
The instruction executed immediately before the last
instruction in the loop does not have to be the one
immediately preceding the last loop instruction in pro-
gram memory.
The DO loop will always be executed at least once,
since the loop count is examined only at the end of
each iteration. For a DCOUNT loop count value of 0,
DO will iterate the loop once.
2.4.2
REPEAT LOOP INTERRUPT AND
NESTING
A REPEAT instruction loop may be interrupted at any
time. As is the case for all instructions, the PC will not
be incremented during the instruction when an excep-
tion is acknowledged. For a repeated instruction, the
PC update is already inhibited (by the RA bit) which
ensures that, upon return, the RETFIEinstruction will
correctly pre-fetch the instruction (i.e. the stacked PC
will point to the instruction to be repeated).
Note: The loop end comparison is an equality
test only. The instruction at the loop end
address must be pre-fetched, in order for
the end of the loop condition to be recog-
nized. That is, exiting the loop to a PC
value greater than the end address (or less
than the start address) will not cause the
loop count to change. An exact address
match must occur in order to change the
loop count.
The RA state bit being present in SRL, is automatically
saved on the stack during exception processing. This
enables execution of further REPEAT loops from
within nested interrupts. After SRL is stacked, RA is
cleared during exception processing to restore normal
execution within the ISR. Exception processing oper-
ates as normal (i.e., with instruction pre-fetch) irre-
spective of the state of RA.
Note: The user must stack the RCOUNT (Repeat
Count register), prior to executing
REPEAT within an ISR.
a
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2.4.5
DO LOOP NESTING
2.4.8
DO AND REPEAT RESTRICTIONS
The DOSTART, DOEND and DCOUNT loop registers
have a shadow register associated with each of them.
This permits a single level of nesting. In addition, as
the DOSTART, DOEND and DCOUNT registers are
user accessible, they may be manually saved to per-
mit additional nesting.
Any instruction can follow a REPEATexcept for:
1. Flow control (any branch, compare and skip,
GOTO, CALL, RCALL, RETURN, RETLW or
RETFIE) instructions
2. DISI, ULNK, LNK, RESET and PWRSAV
instructions
When a DO is executed, the DOSTART, DOEND and
DCOUNT registers are transferred into the shadow
registers, prior to being updated with the new loop val-
ues. The DA bit (SR<7>) is also shadowed prior to
being set during DO execution. Similarly, during all
loop exits, the shadow contents of the DOSTART,
DOEND and DCOUNT registers and the DA bit are
transferred back into their respective host registers.
3. Another REPEATor DO
All DO loops must contain at least 2 instructions,
because the loop termination tests are performed in
the second last instruction executed. REPEAT should
be used for single instruction loops. All other restric-
tions with regard to the DO loop revolve around the
last two instructions. The last instruction in a DO loop
should not be:
2.4.6
DO LOOPS AND INTERRUPTS
1. Flow control (any branch, compare and skip,
GOTO, CALL, RCALL, RETURN, RETLW or
RETFIE) instructions, except the indirect CALL
(CALL Wn)
A DO loop may be interrupted at any time without
penalty.
Note: The LS Byte of the SR (SRL), which is
stacked during exception processing, does
not include the DA bit.
2. Another REPEATor DO
3. Instruction within a REPEAT loop
4. Any 2-word instruction
If a DO loop is required within an exception handler,
the DOSTART, DOEND, DCOUNT and MS Byte of the
SR must be stacked before another DO loop may be
executed. These registers must be restored prior to
returning from the ISR or trap handler.
The (one-word) CALL (CALL Wn) instruction will
function correctly at the end of a DO loop because the
stacked PC will address the first instruction in the loop
(to fetch upon return).
The last instruction in a DO loop should not be either a
REPEAT instruction, or the instruction repeated within
a REPEAT loop. In such cases, the DO loop counter
will take priority, and the REPEAT instruction will not
function correctly.
2.4.7
DO EARLY TERMINATION
The DA bit in the MS Byte of the SR may be cleared
(but not set) by the user. Clearing the DA bit is a
method to force a loop to terminate early at any time.
The loop will complete the current iteration and then
terminate. If DA is cleared during one of the last two
instructions of the loop, one more iteration of the loop
will occur.
If the last instruction of a DO loop or the instruction
within a REPEAT loop detects a data dependency that
indicates an instruction stall is necessary, the extra
cycle will be expended and the loop will continue
normally.
A branch with a target instruction outside the loop may
be executed from within the loop. However, the last
instruction in the DO loop cannot be a flow control
instruction (see Section 2.4.8). It is recommended that
the DA bit is cleared by software whenever a DO loop
is terminated early.
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All other divides can specify any W register for the16-
bit divisor, but the 32-bit dividend must be in the
W1:W0 register pair.
2.5
Divide Support
Note: The Divide Support architecture is under
development. Please refer to our Micro-
chip website (http://www.microchip.com)
for future updates.
The non-restoring divide algorithm requires one cycle
for an initial dividend shift for (integer divides only) one
cycle per divisor bit, plus a remainder/quotient correc-
tion cycle. The correction cycle is the last cycle of the
iteration loop, but must be performed (even if the
remainder is not required) because it may also adjust
the quotient. A consequence of this is that DIVF will
also produce a valid remainder (though it is of little use
in fractional arithmetic).
The dsPIC devices feature
a 16/16-bit signed
fractional divide operation, as well as 32/16-bit and
16/16-bit signed and unsigned integer divide opera-
tions, in the form of single instruction iterative divides.
The following instructions and data sizes are
supported:
The divide instructions must be executed within a
REPEAT loop. Any other form of execution (e.g. a
series of discrete divide instructions) will not function
correctly because the instruction flow is conditional on
RCOUNT. The divide instruction does not automati-
cally set up the RCOUNT value, and it must, therefore,
be explicitly and correctly specified in the REPEAT
instruction, as shown in Table 2-1 (REPEAT will exe-
cute the target instruction {operand value+1} times).
1. DIVF— 16/16 signed fractional divide
2. DIV.sd— 32/16 signed divide
3. DIV.ud— 32/16 unsigned divide
4. DIV.sw— 16/16 signed divide
5. DIV.uw— 16/16 unsigned divide
The 16/16 divides are similar to the 32/16 (same num-
ber of iterations), but either zero or sign extend the div-
idend during the first iteration.
The quotient for all divide instructions ends up in W0,
and the remainder in W1. DIVand DIVF can specify
any W register for both the 16-bit dividend and divisor.
Note: The Divide flow is interruptible.
TABLE 2-1:
Instruction
DIVIDE EXECUTION TIME
Function
Total Execution
Time
(Incl. REPEAT)
REPEATOperand
Iterations
Value
DIVF
Signed fractional divide:
Wm/Wn → W0; Rem → W1
18
18
18
18
18
17
19
19
19
19
19
DIV.sd
DIV.sw
DIV.ud
DIV.uw
Signed divide:
(Wm+1:Wm)/Wn → W0; Rem → W1
Signed divide:
Wm/Wn → W0; Rem → W1
17
17
17
17
Unsigned divide:
(Wm+1:Wm)/Wn → W0; Rem → W1
Unsigned divide:
Wm/Wn → W0; Rem → W1
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User program space access is restricted to the lower
4M instruction word address range (0x000000 to
0x7FFFFE), for all accesses other than TBLRD/TBLWT,
which use TBLPAG<7> to determine user or configura-
tion space access. In Table Read/Write instructions,
bit 23 allows access to the Device ID, the User ID and
the configuration bits. Otherwise, bit 23 is always clear.
3.0
3.1
MEMORY ORGANIZATION
Program Address Space
The program address space is 4M instruction words. It
is addressable by a 24-bit value from either the PC,
table instruction EA, or data space EA, when program
space is mapped into data space, as defined by
Table 3-1. Note that the program space address is
incremented by two between successive program
words, in order to provide compatibility with data space
addressing.
Note: The address map shown in Figure 3-4 is
conceptual, and the actual memory config-
uration may vary across individual devices
depending on available memory.
TABLE 3-1:
PROGRAM SPACE ADDRESS CONSTRUCTION
Program Space Address
Access
Space
Access Type
<23>
<22:16>
<15>
<14:1>
<0>
Instruction Access
User
User
(TBLPAG<7> = 0)
0
PC<22:1>
0
TBLRD/TBLWT
TBLPAG<7:0>
TBLPAG<7:0>
PSVPAG<7:0>
Data EA <15:0>
Data EA <15:0>
TBLRD/TBLWT
Configuration
(TBLPAG<7> = 1)
DS Window into PS User
0
Data EA <14:0>
FIGURE 3-1:
DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
24-bits
Using
Program
Counter
Program Counter
0
0
0
Select
1
EA
Using
Data Space
Addressing
PSVPAG Reg
8-bits
15-bits
EA
Using
Table
Instruction
1/0
TBLPAG Reg
8-bits
16-bits
User /
Byte
Select
24-bit EA
Configuration
Space
Select
Note: PSVPAG cannot be used to access bits <23:16> of a word in program memory.
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dsPIC30F
Figure 3-1 shows how the EA is created for table oper-
ations and data space accesses (PSV = 1). Here,
P<23:0> refers to a program space word, whereas
D<15:0> refers to a data space word.
3.1.1
PROGRAM SPACE ALIGNMENT
AND DATA ACCESS USING TABLE
INSTRUCTIONS
This architecture fetches 24-bit wide program memory.
Consequently, instructions are always aligned. How-
ever, as the architecture is modified Harvard, data can
also be present in program space.
A set of Table instructions are provided to move byte or
word sized data to and from program space.
1. TBLRDL:Table Read Low
Word: Read the LS Word of the program
address;
There are two methods by which program space can
be accessed: via special table instructions, or through
the remapping of a 16K word program space page into
the upper half of data space (see Section 3.1.2). The
TBLRDLand TBLWTLinstructions offer a direct method
of reading or writing the LS Word of any address within
program space, without going through data space. The
TBLRDHand TBLWTHinstructions are the only method
whereby the upper 8 bits of a program word can be
accessed as data.
P<15:0> maps to D<15:0>.
Byte: Read one of the LS Bytes of the program
address;
P<7:0> maps to D<7:0> when byte select = 0;
P<15:8> maps to D<7:0> when byte select = 1.
2. TBLWTL:Table Write Low (refer to Section 4.0
for details on FLASH Programming).
3. TBLRDH:Table Read High
Word: Read the MS Word of the program
address;
The PC is incremented by two for each successive
24-bit program word. This allows program memory
addresses to directly map to data space addresses.
Program memory can thus be regarded as two 16-bit
word wide address spaces, residing side by side, each
with the same address range. TBLRDL and TBLWTL
access the space which contains the LS Data Word,
and TBLRDHand TBLWTHaccess the space which con-
tains the MS data Byte.
P<23:16> maps to D<7:0>; D<15:8> always = 0.
Byte: Read one of the MSBs of the program
address;
P<23:16> maps to D<7:0> when byte select = 0;
D<7:0> will always = 0 when byte select = 1.
4. TBLWTH:Table Write High (refer to Section 4.0
for details on FLASH Programming).
FIGURE 3-2:
PROGRAM DATA TABLE ACCESS (LS WORD)
PC Address
23
8
16
0
0x000000
0x000002
0x000004
0x000006
00000000
00000000
00000000
00000000
TBLRDL.B (EA[0] = 0)
TBLRDL.W
Program Memory
‘Phantom’ Byte,
(read as 0).
TBLRDL.B (EA[0] = 1)
DS70032B-page 34
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this memory region, Y data space should typically con-
tain state (variable) data for DSP operations, whereas
X data space should typically contain coefficient
(constant) data.
3.1.2
PROGRAM SPACE VISIBILITY
FROM DATA SPACE
The upper 32 Kbytes of data space may optionally be
mapped into any 16K word program space page. This
provides transparent access of stored constant data
from X data space, without the need to use special
instructions (i.e., TBLRDL/H, TBLWTL/Hinstructions).
Although each data space address, 0x8000 and higher,
maps directly into a corresponding program memory
address (see Figure 3-3), only the lower 16-bits of the
24-bit program word are used to contain the data. The
upper 8-bits should be programmed to force an illegal
instruction, or software trap, to maintain machine
robustness. Refer to the Programmer’s Reference
Manual (DS70030) for details on instruction encoding.
Program space access through the data space occurs
if the MS bit of the data space EA is set and program
space visibility is enabled, by setting the PSV bit in the
Core Control register (CORCON). The functions of
CORCON are discussed in Section 6.0, DSP Engine.
Note that by incrementing the PC by 2 for each pro-
gram memory word, the LS 14 bits (15 bits for the
TBLRDL/H, TBLWTL/H instructions) of data space
addresses directly map to the LS 14 bits in the corre-
sponding program space addresses. The remaining
bits are provided by the Program Space Visibility Page
register, PSVPAG<7:0>, as shown in Figure 3-3.
Data accesses to this area add an additional cycle to
the instruction being executed, since two program
memory fetches are required.
Note that the upper half of addressable data space is
always part of the X data space. Therefore, when a
DSP operation uses program space mapping to access
FIGURE 3-3:
DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION
Program Space
Data Space
0x0000
0x8000
PSVPAG(1)
0x21
8
15
15
EA<15> = 0
Data
Space
EA
16
0x108000
0x108200
23
15
0
Address
Concatenation
EA<15> = 1
15
23
Upper Half of Data
Space is Mapped
into Program Space
0x10FFFF
0xFFFF
BSET.bCORCON, #2
; PSV bit set
MOV
MOV
MOV
#0x21, W0
W0, PSVPAG
0x8200, W0
; Set PSVPAG register
; Access program memory location
; using a data space access
Data Read
Note 1: PSVPAG is an 8-bit register, containing bits <22:15> of the program space address
(i.e., it defines the page in program space to which the upper half of data space is being mapped).
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FIGURE 3-4:
SAMPLE PROGRAM
SPACE MEMORY MAP
3.2
Data Address Space
The core has two data spaces. The data spaces can be
considered either separate (for some DSP instruc-
tions), or as one unified linear address range (for MCU
instructions). The data spaces are accessed using two
Address Generation Units (AGUs) and separate data
paths.
RESET - GOTOInstruction
000000
000002
000004
RESET - Target Address
Osc. Fail Trap Vector
Stack Error Trap Vector
Address Error Trap Vector
Arithmetic Warn. Trap Vector
Software Trap
Vector Tables
Reserved Vector
3.2.1
DATA SPACES
Reserved Vector
Reserved Vector
Interrupt 0 Vector
000014
The X AGU is used by all instructions and supports all
addressing modes. It consists of a read AGU (X
RAGU) and a write AGU (X WAGU), which operate
independently during different phases of the instruc-
tion cycle. There are separate read and write data
buses. The X read data bus is the return data path for
all instructions that view data space as combined X
and Y address space. It is also the X address space
data path for the dual operand read instructions (MAC
class). The X write data bus is the only write path to
data space for all instructions.
Interrupt 1 Vector
Interrupt 52 Vector
Interrupt 53 Vector
Reserved
00007E
000080
000084
0000FE
000100
Alternate Vector Table
User FLASH
Program Memory
(48K instructions)
017FFE
018000
Reserved
(Read 0’s)
The X RAGU and X WAGU also support Modulo
Addressing for any instructions subject to addressing
mode restrictions. Bit-Reversed Addressing is only
supported by X WAGU.
7FEFFE
7FF000
Data FLASH
(4 Kbytes)
7FFFFE
800000
The Y AGU and data path are used in concert with the
X AGU by the MAC class of instructions (CLR, ED,
EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to
provide two concurrent data read paths. No writes
occur across the Y bus. This class of instructions dedi-
cates two W register pointers, W10 and W11, to always
operate through the Y AGU and address Y data space,
independent of X data space, whereas W8 and W9
operate through the X RAGU and address X data
space. Note that during accumulator write back, the
data address space is considered a combination of X
and Y, so the write occurs across the X bus. Conse-
quently, it can be to any address in the entire data
space.
Reserved
8005BE
8005C0
The Y AGU only supports the Post-Modification
Addressing modes associated with the MAC class of
instructions. It also supports Modulo Addressing for
automated circular buffers. Of course, all other instruc-
tions can access the Y data address space through the
X AGU, when it is regarded as part of the composite
linear space.
UNITID (32 instr.)
Reserved
80043E
800440
F7FFFE
Fuse Configuration
Registers
F80000
F8000E
F90000
The boundary between the X and Y data spaces is
defined as shown in Figure 3-6 and is not user pro-
grammable. Should an EA point to data outside its own
assigned address space, or to a location outside phys-
ical memory, an all zero word/byte will be returned. For
example, although Y address space is visible by all
non-MAC instructions using any addressing mode, an
attempt by a MAC instruction to fetch data from that
space, using W8 or W9 (X space pointers), will return
0x0000.
Reserved
DEVID (2)
FEFFFE
FF0000
FFFFFE
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As a consequence of this byte accessibility, all effective
address calculations (including those generated by the
DSP operations, which are restricted to word sized
data) are internally scaled to step through word aligned
memory. For example, the core would recognize that
Post-Modified Register Indirect Addressing mode
[Ws++], will result in a value of Ws+1 for byte opera-
tions and Ws+2 for word operations.
TABLE 3-2:
EFFECT OF INVALID
MEMORY ACCESSES
Attempted Operation
Data Returned
EA = an unimplemented address
0x0000
0x0000
W8 or W9 used to access Y data
space in a MACinstruction
W10 or W11 used to access X
data space in a MACinstruction
0x0000
All word accesses must be aligned to an even address.
Mis-aligned word data fetches are not supported, so
care must be taken when mixing byte and word opera-
tions, or translating from 8-bit MCU code. Should a mis-
aligned read or write be attempted, an address error
trap will be forced. If the error occurred on a read, the
instruction underway is completed, whereas if it
occurred on a write, the instruction will be inhibited and
the PC will not be incremented. In either case, a trap
will then be executed, allowing the system and/or user
to examine the machine state prior to execution of the
address fault.
All effective addresses are 16-bits wide and point to
bytes within the data space. Therefore, the data space
address range is 64 Kbytes or 32K words.
3.2.2
DATA SPACE WIDTH
The core data width is 16-bits. All internal registers are
organized as 16-bit wide words. Data space memory is
organized in byte addressable, 16-bit wide blocks.
3.2.3
DATA ALIGNMENT
FIGURE 3-5:
DATA ALIGNMENT
To help maintain backward compatibility with
PICmicro® devices and improve data space memory
usage efficiency, the dsPIC30F instruction set supports
both word and byte operations. Data is aligned in data
memory and registers as words, but all data space EAs
resolve to bytes. Data byte reads will read the complete
word, which contains the byte, using the LS bit of any
EA to determine which byte to select. The selected byte
is placed onto the LS Byte of the X data path (no byte
accesses are possible from the Y data path as the MAC
class of instruction can only fetch words). That is, data
memory and registers are organized as two parallel
byte wide entities with shared (word) address decode,
but separate write lines. Data byte writes only write to
the corresponding side of the array or register which
matches the byte address.
MS Byte
LS Byte
15
8
7
0
0000
0002
0004
0001
Byte1
Byte3
Byte5
Byte 0
Byte 2
Byte 4
0003
0005
All byte loads into any W register are loaded into the LS
Byte. The MSB is not modified.
A sign extend (SE) instruction is provided to allow users
to translate 8-bit signed data to 16-bit signed values.
Alternatively, for 16-bit unsigned data, users can clear
the MSB of any W register, by executing a zero extend
(ZE) instruction on the appropriate address.
EXAMPLE 3-1:
SEAND ZEOPERATION
MOV.b
SE
#0x7f, W1 ; W1 = 0x007f (0000 0000 0111 1111)
W1,W1
; W1 = 0x007f (0000 0000 0111 1111)
; Sign bit = 0 is extended to MS byte
MOV.b
SE
#0xf6, W2
W2,W2
; W2 = 0x00f6 (0000 0000 1111 0110)
; W2 = 0xfff6 (1111 1111 1111 0110)
; Sign bit = 1 is extended to MS byte
MOV
ZE
#WREG2, W3
[W3],[W3]
; WREG2 is the memory-mapped address of W2
; W3 = 0x00f6 (0000 0000 1111 0110)
Although most instructions are capable of operating on
word or byte data sizes, it should be noted that some
instructions, including the DSP instructions, operate
only on words.
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3.2.4
DATA SPACE MEMORY MAP
3.2.5
ACCESS RAM SPACE
The data space memory is split into two blocks, X and
Y data space. A key element of this architecture is that
Y space is a subset of X space, and is fully contained
within X space. In order to provide an apparent linear
addressing space, X and Y spaces have contiguous
addresses.
An 8 Kbyte access space is reserved in X address
memory space between 0x0000 and 0x1FFF, which is
directly addressable via a 13-bit absolute address field
within all memory direct instructions. The remaining X
address space and all of the Y address space is
addressable indirectly. Additionally, the whole of X data
space is addressable using MOV instructions, which
support memory direct addressing with a 16-bit
address field.
When executing any instruction other than one of the
MAC class of instructions, the X block consists of the
entire 64 Kbyte data address space (including all Y
addresses). When executing a MACclass of instruction,
the X block consists of the entire 64 Kbyte data address
space, less the Y address block for data reads (only).
In other words, all other instructions regard the entire
data memory as one composite address space. The
MACclass of instructions extracts the Y address space
from data space and addresses it using EAs sourced
from W10 and W11. The remaining X data space is
addressed using W8 and W9. Both address spaces are
concurrently accessed only by the MAC class of
instruction.
An example data space memory map is shown in
Figure 3-6.
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FIGURE 3-6:
SAMPLE DATA SPACE MEMORY MAP
LS Byte
Address
MS Byte
Address
16-bits
MSB
LSB
0x0000
0x0001
SFR Space
2 Kbyte
SFR Space
0x07FE
0x0800
0x07FF
0x0801
Access
RAM
X Data RAM (X)
Y Data RAM (Y)
8 Kbyte
0x17FF
0x1801
0x17FE
0x1800
SRAM Space
0x1FFF
0x1FFE
0x27FF
0x2801
0x27FE
0x2800
8 Kbyte
SRAM boundary
0x8001
0x8000
X Data
Unimplemented (X)
Optionally
Mapped
into Program
Memory
0xFFFE
0xFFFF
Note: The address map shown in Figure 3-6 is conceptual, and may vary across individual devices
depending on available memory.
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FIGURE 3-7:
DATA SPACE FOR MCU AND DSP (MACCLASS) INSTRUCTIONS EXAMPLE
SFR SPACE
SFR SPACE
(Y SPACE)
UNUSED
Y SPACE
UNUSED
UNUSED
Non-MACClass Ops (Read)
MACClass Ops (Read)
Indirect EA from any W
Indirect EA from W8, W9
Indirect EA from W10, W11
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data pre-fetch, as shown in Figure 3-8. In this exam-
ple, the initial 2 data words for the first iteration of the
instruction to be repeated (MAC A) are fetched by a
prior instruction (e.g., CLR Ainstruction). The subse-
quent MAC instructions, therefore, only need to fetch
two more data pairs to complete the loop. The initial
fetch of the MAC A instruction is performed by the
REPEATinstruction.
3.2.6
DATA PRE-FETCH FROM
PROGRAM SPACE WITHIN A
REPEAT LOOP
When pre-fetching data resident in program space, via
the data space window from within a REPEAT loop, all
iterations of the repeated instruction will reload the
instruction from the Instruction Latch without re-
fetching it, thereby releasing the program bus for a
EXAMPLE 3-2:
PROGRAM SPACE DATA READ THROUGH DATA SPACE WITHIN A REPEAT
LOOP
; In this example, data for MAC operations is stored in Program Space.
CLR
REPEAT #99
MAC
A, [W8]+=2, W4, [W10]+=2, W5
; Acc. A cleared, data prefetched (2 cycles)
; Repeat the MAC operation 100 times (1 cycle)
W4*W5, A, [W8]+=2, W4, [W10]+=2, W5 ; MAC operation within REPEAT loop (1 cycle)
FIGURE 3-8: PROGRAM SPACE DATA READ THROUGH DATA SPACE WITHIN A REPEAT LOOP
Data
Space
Fetch
Read
Write
Read
Read
(Y Data)(1)
(Loop cnt.) (Y Data)(1)
(Y Data)(1)
Program
Space
Fetch
Read [15:0] (X Data)(1)
Read (REPEAT)
Read [15:0] (X Data)(1) Read [15:0] (X Data)(1)
Read (MAC A)
Instruction
Executed
T
CY
1
TCY2
CLR A
T
CY
1
T
CY
1
T
CY
1
T 1
3RD MAC A
CY
CLR A
REPEAT
1
ST MAC A
2
ND MAC A
Note 1: Program space window will always reside in X space.
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NOTES:
DS70032B-page 44
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4.3
Table Instruction Operation Summary
4.0
FLASH PROGRAM MEMORY
The TBLRDLand the TBLWTLinstructions are used to
read or write to bits <15:0> of program memory.
TBLRDLand TBLWTLcan access program memory in
Word or Byte mode.
The dsPIC30F family of devices contains internal pro-
gram FLASH memory for executing user code. There
are two methods by which the user can program this
memory:
The TBLRDHand TBLWTHinstructions are used to read
or write to bits<23:16> of program memory. TBLRDH
and TBLWTHcan access program memory in Word or
Byte mode. Since the program memory is only 24-bits
wide, the TBLRDH and TBLWTH instructions have the
ability to address an upper byte of program memory
that does not exist. This byte is called the ‘phantom
byte’. Any read of the phantom byte will return 0x00
and a write to the phantom byte has no effect (see
Figure 4-2).
1. Run Time Self-Programming (RTSP)
2. In-Circuit Serial ProgrammingTM (ICSPTM
)
4.1
In-Circuit Serial Programming
(ICSP)
The details of ICSP will be provided at a later date.
4.2
Run Time Self-Programming
(RTSP)
A 24-bit program memory address is formed using
bits<7:0> of the TBLPAG register and the effective
address (EA) from a W register, specified in the table
instruction. The upper 23 bits of the EA are used to
select the program memory location. For the Byte
mode table instructions, the LS bit of the W register EA
is used to pick which byte of the 16 bit program memory
word is addressed. A “1” selects bits <15:8>, a “0”
selects bits <7:0>. The LSb of the W register EA is
ignored for a table instruction in Word mode.
RTSP is accomplished using TBLRD (table read) and
TBLWT (table write) instructions, and the following
control registers:
• NVMCON: Non-volatile Memory Control Register
• NVMKEY: Non-volatile Memory Key Register
• NVMADR: Non-volatile Memory Address Register
With RTSP, the user may erase program memory, 32
instructions (96 bytes) at a time and can write program
memory data, 4 instructions (12 bytes) at a time.
The table instruction also specifies a W register (or a W
register pointer to a memory location) that is the source
of the program memory data to be written, or the desti-
nation for a program memory read. For a table write
operation in Byte mode, bits<15:8> of the source work-
ing register are ignored
FIGURE 4-1:
ADDRESSING FOR TABLE AND NVM REGISTERS
24-bits
Program Counter
Using
Program
Counter
0
0
NVMADR Reg EA
Using
NVMADR
Addressing
1/0 TBLPAG Reg
8-bits
16-bits
Working Reg EA
Using
Table
Instruction
1/0
TBLPAG Reg
8-bits
16-bits
Byte
Select
User/Configuration
Space Select
24-bit EA
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DSPIC30F
FIGURE 4-2:
TABLE READ OPERATIONS ON PROGRAM MEMORY
Actual 24-bit Program Memory
Table Instruction View of Program Memory
0000 0000
8-bits
16-bits
TBLRDH
TBLRDL
TBLRDH.B
TBLRDH.B
TBLRDL.B
TBLRDL.B
4.4
Using Table Read Instructions
4.4.1
READ WORD MODE
The following instructions can be used to read a word
of program memory, as shown in Example 4-1.
EXAMPLE 4-1:
READING A FLASH PROGRAM MEMORY WORD
; setup pointer
MOV
MOV
MOV
#tblpage(PROG_ADDR),W0
W0,TBLPAG
#tbloffset(PROG_ADDR),W0 ; Initialize in-page EA[15:0] pointer
;
; Initialize PM Page Boundary SFR
TBLRDH [W0],W3
TBLRDL [W0],W4
; Read PM high word into W3
; Read PM low word into W4
The post-increment operator on the read of the low
byte causes the address in working register to incre-
ment by one. This sets EA<0> to a “1”, for access to the
middle byte in the third write instruction. The last post-
increment sets W0 back to an even address, pointing
to the next program memory location.
4.4.2
READ BYTE MODE
The following instructions can be used to read a byte of
program memory, as shown in Example 4-2.
EXAMPLE 4-2:
READING A FLASH PROGRAM MEMORY BYTE
; setup pointer
MOV
MOV
MOV
#tblpage(PROG_ADDR),W0
W0,TBLPAG
#tbloffset(PROG_ADDR),W0; Intialize in-page EA[15:0] pointer
;
; Initialize PM Page Boundary SFR
TBLRDH.b [W0],W3
TBLRDL.b [W0++],W4
TBLRDL.b [W0++],W5
; Read PM high byte
; Read PM low byte
; Read PM middle byte
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4.5
Using Table Write Instructions
In Example 4-3, the contents of the upper byte of W3
has no effect. W0 is post-incremented by 2 after the
TBLWTHinstruction, to prepare for the write to the next
program memory location.
4.5.1
WRITE WORD MODE
To write a single program latch location in Word mode,
the following sequence can be implemented.
EXAMPLE 4-3:
WRITING A SINGLE PROGRAM LATCH LOCATION IN WORD MODE
; setup pointer
MOV
MOV
MOV
#tblpage(PROG_ADDR),W0
W0,TBLPAG
#tbloffset(PROG_ADDR),W0; Intialize in-page EA[15:0] pointer
;
; Initialize PM Page Boundary SFR
; get data into W registers
MOV
MOV
#PROG_LOW_WORD,W2
#PROG_HI_BYTE,W3
; Low PM word into W2
; High PM byte into W3
; do the table writes
TBLWTL
TBLWTH
W2,[W0]
W3,[W0++]
; Write PM low word into program latch
; Write PM high byte into program latch
In Example 4-4, the post-increment operator on the
write to the low byte causes the address in W0 to incre-
ment by one. This sets EA<0> to a “1”, for access to the
middle byte in the third write instruction. The last post-
increment sets W0 back to an even address, pointing
to the next program memory location.
4.5.2
WRITE BYTE MODE
To write a single memory latch location in Byte mode,
the following sequence can be implemented.
EXAMPLE 4-4:
WRITING A SINGLE PROGRAM LATCH LOCATION IN BYTE MODE
; setup pointer
MOV
MOV
MOV
#tblpage(PROG_ADDR),W0
W0,TBLPAG
#tbloffset(PROG_ADDR),W0; Intialize in-page EA[15:0] pointer
;
; Initialize PM Page Boundary SFR
; Load data into working registers
MOV
MOV
MOV
#LOW_BYTE,W2
#MID_BYTE,W3
#HIGH_BYTE,W4
; PM Low byte into W2
; PM Middle byte into W3
; PM High byte W4
; Write data to 24-bit memory
TBLWTH.b W4,[W0]
; Write PM high byte into program latch
; Write PM low byte into program latch
; Write PM middle byte into program latch
TBLWTL.b W2,[W0++]
TBLWTL.b W3,[W0++]
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DSPIC30F
4.7.3
NVMKEY REGISTER
4.6
RTSP Operation
NVMKEY is a write only register that is used for write pro-
tection. To start a programming or an erase sequence,
the user must write 0x55, then 0xAA, to the NVMKEY
register. Refer to Section 4.8 for further details.
The dsPIC30F FLASH program memory is organized
into rows and panels. Each row consists of 32 instruc-
tions, or 96 bytes. Each panel consists of 128 rows, or
4K x 24 instructions. RTSP allows the user to erase one
row (32 instructions) at a time and to program four
instructions at one time. RTSP may be used to program
multiple program memory panels, but the table pointer
must be changed at each panel boundary.
4.8
Programming Operations
A long write operation is necessary for programming or
erasing the internal FLASH in RTSP mode. A long write
is nominally 2 msec in duration and the processor stalls
(waits) until the operation is finished. Setting the WR bit
(NVMCON<15>) starts the operation, and the WR bit is
automatically cleared when the operation is finished.
Each panel of program memory contains write latches
that hold four instructions of programming data. Prior to
the actual programming operation, the write data must
be loaded into the panel write latches. The data to be
programmed into the panel is loaded in sequential
order into the write latches: instruction 0, instruction 1,
etc. The instruction words loaded must always be from
a group of four boundary (e.g., loading of instructions 3,
4, 5, 6 is not allowed).
4.8.1
PROGRAMMING ALGORITHM FOR
PROGRAM FLASH
The user can erase program FLASH memory by rows.
The user can program FLASH in blocks of 4 instruc-
tion words. The general process is:
The basic sequence for RTSP programming is to setup
a table pointer, then do a series of TBLWTinstructions
to load the write latches. Programming is performed by
setting the special bits in the NVMCON register. Four
TBLWTL and four TBLWTH instructions are required to
load the four instructions. To fully program a row of pro-
gram memory, eight cycles of four TBLWTL and four
TBLWTH are required. If multiple panel programming
is required, the table pointer needs to be changed and
the next set of multiple write latches written.
1. Read one row of program FLASH (32 instruction
words) and store into data RAM as a data
“image”.
2. Update the data image with the desired new data.
3. Erase program FLASH row.
a. Setup NVMCON register for multi-word, pro-
gram FLASH, erase, and set WREN bit.
b. Write address of row to be erased into
NVMADR.
All of the table write operations are single word writes
(2 instruction cycles), because only the table latches
are written. A total of 8 programming passes, each writ-
ing 4 instruction words, are required per row. A 128 row
panel requires 1024 programming cycles.
c. Disable interrupts.
d. Write ‘55’ to NVMKEY.
e. Write ‘AA’ to NVMKEY.
f. Set the WR bit. This will begin erase cycle.
g. CPU will stall for the duration of the erase cycle.
h. The WR bit is cleared when erase cycle ends.
i. Re-enable interrupts.
The FLASH Program Memory is readable, writable,
and erasable during normal operation, over the entire
VDD range.
4.7
Control Registers
4. Write four instruction words of data from data
RAM into the program FLASH write latches.
The three SFRs used to read and write the program
FLASH memory are:
5. Program 4 instruction words into program
FLASH.
• NVMCON
• NVMADR
• NVMKEY
a. Setup NVMCON register for multi-word, pro-
gram FLASH, program, and set WREN bit.
b. Disable interrupts.
c. Write ‘55’ to NVMKEY.
4.7.1
NVMCON REGISTER
d. Write ‘AA’ to NVMKEY.
The NVMCON register controls which blocks are to be
erased, which memory type is to be programmed, and
start of the programming cycle.
e. Set the WR bit. This will begin program cycle.
f. CPU will stall for duration of the program cycle.
g. The WR bit is cleared by the hardware when
program cycle ends.
4.7.2
NVMADR REGISTER
h. Re-enable interrupts.
The NVMADR register is used to hold the lower two
bytes of the effective address. The NVMADR register
captures the EA<15:0> of the last table instruction that
has been executed and selects the row to write.
6. Repeat steps (4 - 5) seven more times to finish
programming FLASH row.
7. Repeat steps 1 through 6 as needed to program
desired amount of program FLASH memory.
DS70032B-page 48
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dsPIC30F
4.8.2
ERASING A ROW OF PROGRAM
MEMORY
The following is a code sequence that can be used to
erase a row (32 instructions) of program memory.
EXAMPLE 4-5:
ERASING A ROW OF PROGRAM MEMORY
; Setup NVMCON for erase operation, multi word write
; program memory selected, and writes enabled
MOV
MOV
#0x4003,W0
W0,NVMCON
;
; Init NVMCON SFR
; Init pointer to row to be ERASED
MOV
MOV
MOV
MOV
#tblpag(PROG_ADDR),W0
W0,TBLPAG
#tbloffset(PROG_ADDR),W0
W0, NVMADR
;
; Initialize PM Page Boundary SFR
; Intialize in-page EA[15:0] pointer
; Intialize NVMADR SFR
; Disable interrupts (if required)
;
; Write the 0x55 key
;
; Write the 0xAA key
BCLR.b INTCON1+1, #GIE
MOV
MOV
MOV
MOV
#0x55,W1
W1,NVMKEY
#0xAA,W1
W1,NVMKEY
BSET.b NVMCON+1,#WR
NOP
NOP
; Start the erase sequence
; Insert two NOPs after the erase
; command is asserted
BSET.b INTCON1+1, #GIE
; Re-enable interrupts (if required)
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DSPIC30F
4.8.3
LOADING WRITE LATCHES
The following is a sequence of instructions that can be
used to load the 96-bits of write latches. Four TBLWTL
and four TBLWTH instructions are needed to load the
write latches selected by the table pointer.
EXAMPLE 4-6:
LOADING WRITE LATCHES
; Set up a pointer to the first program memory location to be written
; program memory selected, and writes enabled
MOV
MOV
MOV
#0x0000,W0
W0,TBLPAG
#0x6000,W0
;
; Initialize PM Page Boundary SFR
; An example program memory address
; Perform the TBLWT instructions to write the latches
; 0th_program_word
MOV
MOV
#LOW_WORD_0,W2
#HIGH_BYTE_0,W3
;
;
TBLWTL W2,[W0]
TBLWTH W3,[W0++]
; Write PM low word into program latch
; Write PM high byte into program latch
; 1st_program_word
MOV
MOV
#LOW_WORD_1,W2
#HIGH_BYTE_1,W3
;
;
TBLWTL W2,[W0]
TBLWTH W3,[W0++]
; Write PM low word into program latch
; Write PM high byte into program latch
;
2nd_program_word
MOV
MOV
#LOW_WORD_2,W2
#HIGH_BYTE_2,W3
;
;
TBLWTL W2, [W0]
TBLWTH W3, [W0++]
; Write PM low word into program latch
; Write PM high byte into program latch
; 3rd_program_word
MOV
MOV
#LOW_WORD_3,W2
#HIGH_BYTE_3,W3
;
;
TBLWTL W2, [W0]
TBLWTH W3, [W0++]
; Write PM low word into program latch
; Write PM high byte into program latch
Note: In example 4-6, the contents of the upper byte of W3 has no effect.
DS70032B-page 50
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dsPIC30F
executed, the user must wait for the programming time
until programming is complete. The two instructions fol-
lowing the start of the programming sequence should
be NOPs. If interrupts are implemented, they must be
disabled prior to the programming sequence.
4.8.4
INITIATING THE PROGRAMMING
SEQUENCE
For protection, the write initiate sequence for NVMKEY
must be used to allow any erase or program operation
to proceed. After the programming command has been
EXAMPLE 4-7:
INITIATING A PROGRAMMING SEQUENCE
BCLR.b INTCON1+1, #GIE
; Disable interrupts (if required)
;
; Write the 0x55 Key
;
; Write the 0xAA Key
; Start the erase sequence
; Insert two NOPs after the erase
; command is asserted
; Re-enable interrupts (if required)
MOV
#0x55,W1
W1,NVMKEY
#0xAA,W1
W1,NVMKEY
MOV
MOV
MOV
BSET.b NVMCON+1,#WR
NOP
NOP
BSET.b INTCON1+1, #GIE
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DSPIC30F
REGISTER 4-1:
NVMCON REGISTER
Upper Half:
R/W-0
WR
R/W-0
WREN
R/W-0
U-0
U-0
U-0
U-0
U-0
WRERR
—
—
—
—
—
bit 15
bit 8
Lower Half:
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
MEMSEL1 MEMSEL0 SIZSEL1 SIZSEL0
ERASE
bit 7
bit 0
bit 15
WR: Write (Program or Erase) Control bit
1= Initiates a data FLASH or program FLASH erase or write cycle
(the WR bit can be set (not cleared) in software)
0= Write cycle to the FLASH is complete
bit 14
bit 13
WREN: FLASH Write (Erase or Program) Enable bit
1= Allow an erase or program operation
0= No operation allowed
WRERR: FLASH Error Flag bit
1= A write operation is prematurely terminated (any MCLR or WDT Reset during programming operation)
0= The write operation completed successfully
bit 12-5 Unimplemented: User code should write 0’s to these locations
bit 4-3
bit 2-1
bit 0
MEMSEL<1:0>: Memory Array Select for Program or Erase Operation bits
11= Program, Data and Configuration selected (select for Chip Erase)
10= Configuration bits array selected
01= Data FLASH memory array selected
00= Program FLASH memory array selected (also data FLASH if erasing segments)
SIZSEL<1:0>: Select Memory Unit Size for Program or Erase Operation bits
11= All memory panels of array (select for Chip Erase)
10= Reserved, do not use
01= Multi-words of memory (Row or 4 I-Words)
00= Single word of memory (Data FLASH only)
ERASE: Operation Select bit
1= Perform erase operation
0= Perform program operation
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
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dsPIC30F
REGISTER 4-2:
Upper Half:
NVMKEY REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
Lower Half:
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
NVMKEY7 NVMKEY6 NVMKEY5 NVMKEY4 NVMKEY3 NVMKEY2 NVMKEY1 NVMKEY0
bit 7 bit 0
bit 15-8 Unimplemented: Read as '0’
bit 7-0 NVMKEY<7:0>: Key Register (Write Only) bits
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
REGISTER 4-3:
Upper Half:
NVMADR REGISTER
R/W-x
NVMADR15 NVMADR14 NVMADR13 NVMADR12 NVMADR11 NVMADR10 NVMADR9 NVMADR8
bit 15 bit 8
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
Lower Half:
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
NVMADR7 NVMADR6 NVMADR5 NVMADR4 NVMADR3 NVMADR2 NVMADR1 NVMADR0
bit 7 bit 0
bit 15-0 NVMADR<15:0>: NV Memory Write Address bits
Selects the location to program in program or data FLASH memory.
This register may be read or written to by user. This register will contain the address of EA<15:0> of the last
table write instruction executed, until written to by the user.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
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DSPIC30F
NOTES:
DS70032B-page 54
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dsPIC30F
5.1
Reading the Data EEPROM
5.0
DATA EEPROM MEMORY
A TBLRD instruction reads a word at the current pro-
gram word address. This example uses W0 as a
pointer to data EEPROM. The result is placed in regis-
ter W4, as shown in Example 5-1.
The Data EEPROM Memory is readable and writable
during normal operation over the entire VDD range. The
data memory is directly mapped in the program mem-
ory data space.
The three SFRs used to read and write the program
FLASH memory are used to access data EEPROM
memory, as well. As described in Section 4.0, these
registers are:
EXAMPLE 5-1:
DATA EEPROM READ
MOV
MOV
MOV
#LOW_ADDR_WORD,W0; Init Pointer
#HIGH_ADDR_WORD,W1
W1 TBLPAG
• NVMCON
• NVMADR
• NVMKEY
,
TBLRDL [ W0], W4
; read data Flash
The EEPROM data memory allows read and write of
single words and 16-word blocks. When interfacing to
data memory, NVMADR in conjunction with the
TBLPAG register, are used to address the EEPROM
location being accessed. TBLRDLand TBLWRLinstruc-
tions are used to read and write data EEPROM. The
dsPIC30F devices have up to 8 Kbytes (4K words) of
data EEPROM, with an address range from
0x7FF0000 to 0x7FFFFFE.
A word write operation should be preceded by an erase
of the location. The write time is controlled by an on-
chip timer. The write time will vary with voltage and
temperature, and is typically 2 ms.
A program or erase operation on the data EEPROM
does not stop the instruction flow. The user is respon-
sible for waiting for the appropriate duration of time
before initiating another data EEPROM write/erase
operation. Attempting to read the data EEPROM while
a programming or erase operation is in progress results
in unspecified data.
Control bit WR initiates write operations, similar to pro-
gram FLASH writes. This bit cannot be cleared, only
set, in software. They are cleared in hardware at the
completion of the write operation. The inability to clear
the WR bit in software prevents the accidental or pre-
mature termination of a write operation.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set when a write operation is interrupted by a MCLR
Reset, or a WDT Time-out Reset, during normal oper-
ation. In these situations, following RESET, the user
can check the WRERR bit and rewrite the location. The
address register NVMADR remains unchanged.
Note: Interrupt flag bit NVMIF in the IFS0 register
is set when write is complete. It must be
cleared in software.
2002 Microchip Technology Inc.
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dsPIC30F
5.2
Erasing Data EEPROM
ERASING ENTIRE DATA EEPROM
5.2.1
The following example shows a bulk erase of data
EEPROM.
EXAMPLE 5-2:
DATA EEPROM BULK ERASE
; Select all data EEPROM, set ERASE, WREN bits
MOV
MOV
#0x400F,W0
W0,NVMCON
;
; Initialize NVMCON SFR
BCLR.b INTCON1+1, #GIE
; Disable Interrupts (if-required)
; Start erase cycle by setting WR after writing key sequence
MOV
MOV
MOV
MOV
#0x55,W1
W1,NVMKEY
#0xAA,W1
W1, NVMKEY
; Write the 0x55 key
; Write the 0xAA key
BSET.b NVMCON+1,#WR
BSET.b INTCON1+1, #GIE
; Initiate erase sequence
; Re-enable Interrupts (if-required)
; Erase cycle will complete in 2mS. CPU is not stalled for the Data Erase Cycle
; User can poll WR bit, use NVMIF or Timer IRQ to determine erasure complete
5.2.2
ERASING A BLOCK OF DATA
EEPROM
The TBLPAG and NVMADR registers must point to the
block. Select erase a block of data FLASH, and set the
ERASE and WREN bits in NVMCON register. Setting
the WR bit initiates the erase, as shown in Example 5-3.
EXAMPLE 5-3:
DATA EEPROM BLOCK ERASE
; Select data EEPROM block, ERASE, WREN bits
MOV
#400B,W0
MOV
W0,NVMCON
; Initialize NVMCON SFR
BCLR.b
INTCON1+1, #GIE
; Disable Interrupts (if-required)
; Start erase cycle by setting WR after writing key sequence
MOV
#0x55,W1
MOV
W1,NVMKEY
; Write the 0x55 key
MOV
#0xAA,W1
MOV
W1,NVMKEY
; Write the 0xAA key
BSET.b
BSET.b
NVMCON+1,#WR
INTCON1+1, #GIE
; Initiate erase sequence
; Re-enable Interrupts (if-required)
; Erase cycle will complete in 2mS. CPU is not stalled for the Data Erase Cycle
; User can poll WR bit, use NVMIF or Timer IRQ to determine erasure complete
DS70032B-page 56
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dsPIC30F
5.2.3
ERASING A WORD OF DATA
EEPROM
The TBLPAG and NVMADR registers must point to the
block. Select erase a block of data FLASH, and set the
ERASE and WREN bits in NVMCON register. Setting
the WR bit initiates the erase, as shown in Example 5-4.
EXAMPLE 5-4:
DATA EEPROM WORD ERASE
; Select data EEPROM word, ERASE, WREN bits
MOV
MOV
#4009,W0
W0,NVMCON
BCLR.b INTCON1+1, #GIE ; Disable Interrupts (if-required)
; Start erase cycle by setting WR after writing key sequence
MOV
MOV
MOV
MOV
#0x55,W1
W1,NVMKEY
#0xAA,W1
W1,NVMKEY
; Write the 0x55 key
; Write the 0xAA key
BSET.b NVMCON+1,#WR
; Initiate erase sequence
BSET.b INTCON1+1, #GIE
; Re-enable Interrupts (if-required)
; Erase cycle will complete in 2mS. CPU is not stalled for the Data Erase Cycle
; User can poll WR bit, use NVMIF or Timer IRQ to determine erasure complete
The write will not initiate if the above sequence is not
5.3
Writing to the Data EEPROM
exactly followed (write 0x55 to NVMKEY, write 0xAA to
NVMCON, then set WR bit) for each word. It is strongly
recommended that interrupts be disabled during this
code segment.
To write an EEPROM data location, the following
sequence must be followed:
1. Erase data EEPROM word.
a. Select word, data EEPROM, erase, and set
WREN bit in NVMCON register.
Additionally, the WREN bit in NVMCON must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM, due to unexpected code exe-
cution. The WREN bit should be kept clear at all times,
except when updating the EEPROM. The WREN bit is
not cleared by hardware.
b. Write address of word to be erased into
NVMADR.
c. Optionally, enable NVM interrupt.
d. Write ‘55’ to NVMKEY.
After a write sequence has been initiated, clearing the
WREN bit will not affect the current write cycle. The WR
bit will be inhibited from being set unless the WREN bit
is set. The WREN bit must be set on a previous instruc-
tion. Both WR and WREN cannot be set with the same
instruction.
e. Write ‘AA’ to NVMKEY.
f. Set the WR bit. This will begin erase cycle.
g. Either poll NVMIF bit or wait for NVMIF interrupt.
h. The WR bit is cleared when the erase cycle
ends.
2. Write data word into data EEPROM write
latches.
At the completion of the write cycle, the WR bit is
cleared in hardware and the Non-Volatile Memory
Write Complete Interrupt Flag bit (NVMIF) is set. The
user may either enable this interrupt, or poll this bit.
NVMIF must be cleared by software.
3. Program 1 data word into data EEPROM.
a. Select word, data EEPROM, program, and set
WREN bit in NVMCON register.
b. Optionally, enable NVM write done interrupt.
c. Write ‘55’ to NVMKEY.
d. Write ‘AA’ to NVMKEY.
e. Set The WR bit. This will begin program cycle.
f. Either poll NVMIF bit or wait for NVM interrupt.
g. The WR bit is cleared when the write cycle
ends.
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DS70032B-page 57
dsPIC30F
5.3.1
WRITING A WORD OF DATA
EEPROM
Assuming the user has erased the word to be pro-
grammed, then, use a table write instruction to write
one write latch, as shown in Example 5-5.
EXAMPLE 5-5:
DATA EEPROM WORD WRITE
; Point to data memory
MOV
#LOW_ADDR_WORD,W0
; Init pointer
MOV
MOV
#HIGH_ADDR_WORD,W1
W1,TBLPAG
MOV
TBLWTL
#LOW(WORD),W2
W2,[ W0]
; Get data
; Write data
; The NVMADR captures last table access address
; Select data EEPROM for 1 word op
MOV
#0x4004,W0
MOV
W0,NVMCON
BCLR.b
INTCON1+1, #GIE
; Disable Interrupts (if-required)
; Write the 0x55 key
; Operate key to allow write operation
MOV
MOV
#0x55,W1
W1,NVMKEY
MOV
#0xAA,W1
MOV
W1,NVMKEY
; Write the 0xAA key
BSET.b
BSET.b
NVMCON+1,#WR
INTCON1+1, #GIE
; Initiate program sequence
; Re-enable Interrupts (if-required)
; Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle
; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete
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dsPIC30F
5.3.2
WRITING A BLOCK OF DATA
EEPROM
To write a block of data EEPROM, write to all sixteen
latches first, then set the NVMCON register and pro-
gram the block.
EXAMPLE 5-6:
DATA EEPROM BLOCK WRITE
MOV
MOV
MOV
MOV
#LOW_ADDR_WORD,W0 ; Init pointer
#HIGH_ADDR_WORD,W1
W1 TBLPAG
,
#data1,W2
; Get 1st data
; write data
TBLWTL W2 [ W0]++
,
MOV
#data2,W2
; Get 2nd data
; write data
TBLWTL W2 [ W0]++
,
MOV
#data3,W2
; Get 3rd data
; write data
TBLWTL W2 [ W0]++
,
MOV
#data4,W2
; Get 4th data
; write data
TBLWTL W2 [ W0]++
,
MOV
#data5,W2
; Get 5th data
; write data
TBLWTL W2 [ W0]++
,
MOV
#data6,W2
; Get 6th data
; write data
TBLWTL W2 [ W0]++
,
MOV
#data7,W2
; Get 7th data
; write data
TBLWTL W2 [ W0]++
,
MOV
#data8,W2
; Get 8th data
; write data
TBLWTL W2 [ W0]++
,
MOV
#data9,W2
; Get 9th data
; write data
TBLWTL W2 [ W0]++
,
MOV
#data10,W2
; Get 10th data
; write data
TBLWTL W2 [ W0]++
,
MOV
#data11,W2
; Get 11th data
; write data
TBLWTL W2 [ W0]++
,
MOV
#data12,W2
; Get 12th data
; write data
TBLWTL W2 [ W0]++
,
MOV
#data13,W2
; Get 13th data
; write data
TBLWTL W2 [ W0]++
,
MOV
#data14,W2
; Get 14th data
; write data
TBLWTL W2 [ W0]++
,
MOV
#data15,W2
; Get 15th data
; write data
TBLWTL W2 [ W0]++
,
MOV
#data16,W2
; Get 16th data
TBLWTL W2 [ W0]++
; write data. The NVMADR captures last table access address.
; Select data EEPROM for multi word op
; Operate Key to allow program operation
; Disable Interrupts (If required)
,
MOV
MOV
#0x400A,W0
W0 NVMCON
,
BCLR.b INTCON1+1, #GIE
MOV
MOV
MOV
MOV
#0x55,W1
W1 NVMKEY
; Write the 0x55 key
,
#0xAA,W1
W1 NVMKEY
; Write the 0xAA key
,
BSET.b NVMCON+1, #WR
BSET.b INTCON1+1, #GIE
; Start write cycle
; Re-enable Interrupts (If required)
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dsPIC30F
5.4
Write Verify
5.5
Protection Against Spurious Write
Depending on the application, good programming
practice may dictate that the value written to the mem-
ory should be verified against the original value. This
should be used in applications where excessive writes
can stress bits near the specification limit.
There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built-in. On power-up, the WREN bit is cleared;
also, the Power-up Timer prevents EEPROM write.
Generally, a write failure will be a bit which was written
as a ’1’, but reads back as a ’0’ (due to leakage off the
cell).
The write initiate sequence and the WREN bit together,
help prevent an accidental write during brown-out,
power glitch, or software malfunction.
DS70032B-page 60
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dsPIC30F
Data output from the DSP engine is written to one of the
following:
6.0
DSP ENGINE
Concurrent operation of the DSP engine with MCU
instruction flow is not possible, though both the MCU
ALU and DSP engine resources may be used concur-
rently by the same instruction (e.g., ED and EDAC
instructions).
1. The target accumulator, as defined by the DSP
instruction being executed.
2. The X bus for MAC, MSC, CLR and MOVSAC
accumulator writes, where the EA is derived
from W13 only. (MPY, MPY.N, EDand EDAC
do not offer an accumulator write option.)
The DSP engine consists of a high speed 16-bit x
16-bit multiplier, a barrel shifter and a 40-bit adder/
subtractor with two target accumulators, round and
saturation logic.
3. The X bus for all MCU instructions which use the
barrel shifter.
The DSP engine also has the capability to perform
Data input to the DSP engine is derived from one of the
following:
inherent
accumulator-to-accumulator
operations,
which require no additional data. These instructions are
ADD, SUBand NEG.
1. Directly from the W array (registers W4, W5, W6
or W7) via the X and Y data buses for the MAC
A block diagram of the DSP engine is shown in
Figure 6-1.
class of instructions (MAC,
MSC,
MPY,
MPY.N, ED, EDAC, CLRand MOVSAC).
2. From the X bus for all other DSP instructions.
3. From the X bus for all MCU instructions which
use the barrel shifter.
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dsPIC30F
FIGURE 6-1:
DSP ENGINE BLOCK DIAGRAM
S
a
40
16
40-bit Accumulator A
40-bit Accumulator B
40
t
Round
Logic
u
r
a
t
Carry/Borrow Out
Carry/Borrow In
Saturate
Adder
e
Enable
Negate
40
40
40
Barrel
Shifter
16
40
Sign Extend
32
16
Zero Backfill
32
32
16-bit
Multiplier/Scaler
Operand Latches
16
16
To/From W Array
DS70032B-page 62
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dsPIC30F
When the dsPIC30F controller is in Fractional mode,
data is represented as a two’s complement fraction,
where the MSB is defined as a sign bit and the radix
point is implied to lie just after the sign bit (QX format).
The range of an N-bit two’s complement fraction with
this implied radix point is –1.0 to (1-21-N). For a 16-bit
fraction, the Q15 data range is –1.0 (0x8000) to
0.999969482 (0x7FFF), including 0 and has a precision
of 3.01518x10-5. In Fractional mode, the 16x16
dsPIC30F multiplier generates a 1.31 product, which
6.1
Multiplier
The 16 x 16-bit multiplier is capable of signed or
unsigned operation and can multiplex its output using a
scaler to support either 1.31 fractional (Q31), or 32-bit
integer results. The respective number representation
formats are shown in Figure 6-2. Integer data is inher-
ently represented as a signed two’s complement value,
where the MSB is defined as a sign bit. Generally
speaking, the range of an N-bit two’s complement inte-
ger is –2N-1 to 2N-1-1. For a 16-bit integer, the data
range is –32768 (0x8000) to 32767 (0x7FFF), including
0 (see Figure 6-2). For a 32-bit integer, the data range
is –2,147,483,648 (0x8000 0000) to 2,147,483,645
(0x7FFF FFFF).
has a precision of 4.65661x10-10
.
FIGURE 6-2:
16-BIT INTEGER AND FRACTIONAL MODES
Different representations of 0x4001
Integer:
0
1
0
0
0
2
0
0
0
0
0
0
0
0
0
0
1
0
0
14
13
12
11
2
2
2
2
2
. . . .
14
0
0x4001 = 2 + 2 = 16385
1.15 Fractional:
0
1
0
0
2
0
0
0
0
0
0
0
0
0
0
0
1
0
-1
-2
-3
-15
-2
.
2
2
. . .
2
-1
-15
0x4001 = 2 + 2 = 0.500030518
MAC/MSC, MPY[.N] and ED[AC] operations are
always signed. The 40-bit adder/subtractor may also
optionally negate one of its operand inputs to change
the result sign (without changing the operands). This is
used to create a multiply and subtract (MSC) or multiply
and negate (MPY.N) operation.
multiplying two 16-bit integers produces a 32-bit integer
result. However, multiplying two 1.15 values generates
a 2.30 result. Since the dsPIC30F uses 1.31 format for
the accumulators, a DSP multiply in Fractional mode
also includes a left shift by one bit to keep the radix
point properly aligned. This feature reduces the resolu-
tion of the DSP multiplier to 2-30, but has no other effect
on the computation.
In the special case when both input operands are 1.15
fractions and equal to 0x8000 (-110), the result of the
multiplication is corrected to 0x7FFFFFFF (as the clos-
est approximation to +1) by hardware, before it is used.
The same multiplier is used to support the MCU multi-
ply instructions, which include integer 16-bit signed,
unsigned and mixed sign multiplies. Additional data
paths are provided to allow these instructions to write
the result back into the W array and X data bus (via the
W array). These paths are placed prior to the data
scaler. The IF bit in the CORCON register, therefore,
only affects the result of the MACand MPYinstructions.
All other multiply operations are assumed to be integer
operations. If the user executes a MACor MPYinstruc-
tion on fractional data, without clearing the IF bit, the
result must be explicitly shifted left by the user program
after multiplication, in order to obtain the correct result.
It should be noted that with the exception of DSP mul-
tiplies, the dsPIC30F ALU operates identically on inte-
ger and fractional data. Namely, an addition of two
integers will yield the same result (binary number) as
the addition of two fractional numbers. The only differ-
ence is how the result is interpreted by the user. How-
ever, multiplies performed by DSP operations are
different. In these instructions, data format selection is
made by the IF bit (CORCON<0>), and it must be set
accordingly (‘0’ for Fractional mode, ‘1’ for Integer
mode). This is required because of the implied radix
point used by dsPIC30F fractions. In Integer mode,
2002 Microchip Technology Inc.
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dsPIC30F
The MUL instruction may be directed to use byte or
word sized operands. Byte operands will direct a 16-bit
result, and word operands will direct a 32-bit result to
the specified register(s) in the W array.
Six STATUS register bits have been provided to sup-
port saturation and overflow; they are:
1. OA:
AccA overflowed into guard bits
2. OB:
6.2
Data Accumulators and Adder/
Subtractor
AccB overflowed into guard bits
3. SA:
The data accumulator consists of a 40-bit adder/
subractor with automatic sign extension logic. It can
select one of two accumulators (A or B) as its pre-
accumulation source and post-accumulation destina-
tion. For the ADDand LACinstructions, the data to be
accumulated or loaded can be optionally scaled via the
barrel shifter, prior to accumulation.
AccA saturated (bit 31 overflow and saturation)
or
AccA overflowed into guard bits and saturated
(bit 39 overflow and saturation)
4. SB:
AccB saturated (bit 31 overflow and saturation)
or
AccB overflowed into guard bits and saturated
(bit 39 overflow and saturation)
6.2.1
ADDER/SUBTRACTOR, OVERFLOW
AND SATURATION
5. OAB:
Logical OR of OA and OB
The adder/subtractor is a 40-bit adder with an optional
zero input into one side and either true, or complement
data into the other input. In the case of addition, the
carry/borrow input is active high and the other input is
true data (not complemented), whereas in the case of
subtraction, the carry/borrow input is active low and the
other input is complemented. The adder/subtractor
generates overflow status bits SA/SB and OA/OB,
which are latched and reflected in the STATUS register:
6. SAB:
Logical OR of SA and SB
The OA and OB bits are modified each time data
passes through the adder/subtractor. When set, they
indicate that the most recent operation has overflowed
into the accumulator guard bits (bits 32 through 39).
The OA and OB bits can also optionally generate an
arithmetic warning trap when set and the correspond-
ing overflow trap flag enable bit (OVATEN, OVBTEN) in
the INTCON1 register (see Section 8.0) is set. This
allows the user to take immediate action, for example,
to correct system gain.
• Overflow from bit 39: this is a catastrophic over-
flow in which the sign of the accumulator is
destroyed.
• Overflow into guard bits 32 through 39: this is a
recoverable overflow. This bit is set whenever all
the guard bits bits are not identical to each other.
The SA and SB bits can be set each time data passes
through the adder/subtractor, but can only be cleared
by the user. When set, they indicate that the accumula-
tor has overflowed its maximum range (bit 31 for 32-bit
saturation, or bit 39 for 40-bit saturation) and will be
saturated (if saturation is enabled). When saturation is
not enabled, the SA and SB default to bit 39 overflow
and thus, indicate that a catastrophic overflow has
occurred. If the COVTE bit in the INTCON1 register is
set, SA and SB bits will generate an arithmetic warning
trap when saturation is disabled.
The adder has an additional saturation block which
controls accumulator data saturation, if selected. It
uses the result of the adder, the overflow status bits
described above, and the SATA/B (CORCON<7:6>)
and ACCSAT (CORCON<4>) mode control bits to
determine when to saturate and to what value to
saturate.
The overflow and saturation status bits can optionally
be viewed in the STATUS register as the logical OR of
OA and OB (in bit OAB) and the logical OR of SA and
SB (in bit SAB). This allows programmers to check one
bit in the STATUS register to determine if either accu-
mulator has overflowed, or one bit to determine if either
accumulator has saturated. This would be useful for
complex number arithmetic which typically uses both
the accumulators.
DS70032B-page 64
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dsPIC30F
The device supports three saturation and overflow
modes.
6.2.3
ROUND LOGIC
The round logic is a combinational block, which per-
forms a conventional (biased) or convergent (unbiased)
round function during an accumulator write (store). The
Round mode is determined by the state of the RND bit
in the CORCON register. It generates a 16-bit, 1.15 data
value which is passed to the data space write saturation
logic (see Figure 6-3). If rounding is not indicated by the
instruction, a truncated 1.15 data value is stored and the
LS Word is simply discarded.
1. Bit 39 Overflow and Saturation:
Using the bit 39 overflow status bit from the
adder, and the bit 39 value after the addition, the
correct sign of the 9.31 result can be determined.
The saturate logic then loads the maximally pos-
itive 9.31 (0x7FFFFFFFFF) or maximally nega-
tive 9.31 value (0x8000000000) into the target
accumulator. The SA or SB bit is set and remains
set until cleared by the user. This is referred to as
‘super saturation’ and provides protection against
erroneous data, or unexpected algorithm prob-
lems (e.g., gain calculations).
The two Rounding modes are shown in Figure 7-7.
Conventional rounding takes bit 15 of the accumulator,
zero extends it and adds it to the ACCH word (bits 16
through 31 of the accumulator). If the ACCL word (bits
0 through 15 of the accumulator) is between 0x8000
and 0xFFFF (0x8000 included), ACCH is incremented.
If ACCL is between 0x0000 and 0x7FFF, ACCH is left
unchanged. A consequence of this algorithm is that
over a succession of random rounding operations, the
value will tend to be biased slightly positive.
2. Bit 31 Overflow and Saturation:
Using the bit 31 to 39 overflow status bit from the
adder, and the bit 39 value after the addition, the
correct sign of the required 1.31 result can be
determined. The saturate logic then loads the
maximally positive 1.31 value (0x007FFFFFFF)
or
maximally
negative
1.31
value
Convergent (or unbiased) rounding operates in the
same manner as conventional rounding, except when
ACCL equals 0x8000. If this is the case, the LS bit (bit
16 of the accumulator) of ACCH is examined. If it is 1,
ACCH is incremented. If it is 0, ACCH is not modified.
Assuming that bit 16 is effectively random in nature,
this scheme will remove any rounding bias that may
accumulate.
(0x0080000000) into the target accumulator.
The SA or SB bit is set and remains set until
cleared by the user. When this Saturation mode
is in effect, the guard bits are not used (so the
OA, OB or OAB bits are never set).
3. Bit 39 Catastrophic Overflow
The bit 39 overflow status bit from the adder is
used to set the SA or SB bit, which remain set
until cleared by the user. No saturation operation
is performed and the accumulator is allowed to
overflow (destroying its sign). If the COVTE bit in
the INTCON1 register is set, a catastrophic
overflow can initiate a trap exception.
The SAC and SAC.R instructions store either a trun-
cated (SAC) or rounded (SAC.R) version of the contents
of the target accumulator to data memory, via the X bus
(subject to data saturation, see Section 6.2.4). Note
that for the MACclass of instructions, the accumulator
write back operation will function in the same manner,
addressing combined MCU (X and Y) data space
though the X bus. For this class of instructions, the data
is always subject to rounding.
6.2.2
ACCUMULATOR ‘WRITE BACK’
The MAC class of instructions (with the exception of
MPY, MPY.N, ED and EDAC) can optionally write a
rounded version of the high word (bits 31 through 16)
of the accumulator, that is not targeted by the instruc-
tion into data space memory. The write is performed
across the X bus into combined X and Y address
space. The following addressing modes are supported.
1. W13, Register Direct:
The rounded contents of the non-target accumu-
lator are written into W13 as a 1.15 fraction.
2. [W13]+=2, Register Indirect with Post-Increment:
The rounded contents of the non-target accumu-
lator are written into the address pointed to by
W13 as a 1.15 fraction. W13 is then incre-
mented by 2 (for a word write).
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dsPIC30F
If the SATDW bit in the CORCON register is set, data
(after rounding or truncation) is tested for overflow and
adjusted accordingly, For input data greater than
0x007FFF, data written to memory is forced to the max-
imum positive 1.15 value, 0x7FFF. For input data less
than 0xFF8000, data written to memory is forced to the
maximum negative 1.15 value, 0x8000. The MS bit of
the source (bit 39) is used to determine the sign of the
operand being tested.
6.2.4
DATA SPACE WRITE SATURATION
In addition to adder/subtractor saturation, writes to data
space may also be saturated, but without affecting the
contents of the source accumulator. The data space
write saturation logic block accepts a 16-bit, 1.15 frac-
tional value from the round logic block as its input,
together with overflow status from the original source
(accumulator) and the 16-bit round adder. These are
combined and used to select the appropriate 1.15 frac-
tional value as output to write to data space memory.
If the SATDW bit in the CORCON register is not set, the
input data is always passed through unmodified under
all conditions. All data writes from the DSP Engine into
data space, may be optionally saturated by setting the
SATDW bit.
FIGURE 6-3:
CONVENTIONAL AND CONVERGENT ROUNDING MODES
CONVENTIONAL (BIASED)
[RND = 1]
CONVERGENT (UNBIASED)
[RND = 0]
31
31
16 15
0
16 15
0
1XXX XXXX XXXX XXXX
ACCAH
1 1000 0000 0000 0000
ACCAH
Round Up (add 1 to MS Word) when:
1. LS Word = 0x8000 and bit 16 =1
2. LS Word > 0x8000
Round Up (add 1 to MS Word) when:
LS Word ≥ 0x8000
31
31
16 15
0
16 15
0
0XXX XXXX XXXX XXXX
ACCAH
0 1000 0000 0000 0000
ACCAH
Round Down (add nothing) when:
1. LS Word = 0x8000 and bit 16 =0
2. LS Word < 0x8000
Round Down (add nothing) when:
LS Word < 0x8000
Examples:
Examples:
1. Acc A=0x0000728000
RND=1
1. Acc A=0x0000738000
RND=0
SAC.R A, #0, W0
SAC.R A, #0, W0
W0=0x0073
W0=0x0074
2. Acc A=0x0000726000
RND=1
2. Acc A=0x0000728000
RND=0
SAC.R A, #0, W0
SAC.R A, #0, W0
W0=0x0072
W0=0x0072
DS70032B-page 66
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dsPIC30F
The barrel shifter is 40 bits wide to accommodate the
width of the accumulators. The barrel shifter is used for
both DSP and MCU shift operations. A 40-bit result is
obtained for DSP shift operations, and a 16-bit result is
obtained for MCU shift operations. Data from the X bus
is presented to the barrel shifter between bit positions
16 to 31 for right shifts, and bit positions 0 to 15 for left
shifts.
6.3
Barrel Shifter
The barrel shifter is capable of performing up to 15-bit
arithmetic or logic right shifts, or up to 16-bit left shifts
in a single cycle. The source can be either of the two
DSP accumulators, or the X bus (to support multi-bit
shifts of register or memory data).
The shifter requires a signed binary value to determine
both the magnitude (number of bits) and direction of the
shift operation. A positive value will shift the operand
right. A negative value will shift the operand left. A
value of 0 will not modify the operand.
The block diagram of the barrel shifter sub-system is
shown in Figure 6-4.
FIGURE 6-4:
BARREL SHIFTER SIMPLIFIED BLOCK DIAGRAM
Acc.
X Data Path
Shift Value (Wn or k)
5
40
16
Input Data
40
Barrel Shifter
Control Block
Shift Direction
To DSP
Adder
40
40
Left Shift Out
Right Shift Out
Shift Register (40-bit)
16
X Data Path
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dsPIC30F
6.4
DSP Engine Mode Selection
The DSP engine has various options selected through
the CPU Core Configuration Register (CORCON), as
listed below:
1. Fractional or integer.
2. Conventional or convergent rounding.
3. Automatic saturation on/off for AccA.
4. Automatic saturation on/off for AccB.
5. Automatic saturation on/off for writes to data
memory.
6. Accumulator Saturation mode selection.
REGISTER 6-1:
Upper Half:
CORCON CPU MODE CONTROL REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
Lower Half:
R/W-0
SATA
R/W-0
SATB
R/W-0
SATDW
R/W-0
ACCSAT
U-0
R/W-0
PSV
R/W-0
RND
R/W-0
IF
—
bit 7
bit 0
bit 15-8 Unimplemented: Read as '0’
bit 7
bit 6
bit 5
bit 4
SATA: AccA Saturation Enable bit
1= Accumulator A saturation enabled
0= Accumulator A saturation disabled
SATB: AccB Saturation Enable bit
1= Accumulator B saturation enabled
0= Accumulator B saturation disabled
SATDW: Data Space Write from DSP Engine Saturation Enable bit
1= Data space write saturation enabled
0= Data space write saturation disabled
ACCSAT: Accumulator Saturation Mode Select bit
1= 9.31 saturation (super saturation)
0= 1.31 saturation (normal saturation)
bit 3
bit 2
Unimplemented: Read as ’0’
PSV: Program Space Visibility in Data Space Enable bit
1= Program Space Visible in Data Space
0= Program Space Not Visible in Data Space
bit 1
bit 0
RND: Rounding Mode Select bit
1= Biased (conventional) rounding enabled
0= Unbiased (convergent) rounding enabled
IF: Integer or Fractional Multiplier Mode Select bit
1= Integer mode enabled for DSP ops
0= Fractional mode enabled for DSP ops
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
DS70032B-page 68
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dsPIC30F
low overhead circular buffers. The X WAGU also sup-
ports Bit-Reversed Addressing to facilitate FFT data
reorganization.
7.0
ADDRESS GENERATOR UNITS
The dsPIC core contains three independent address
generator units. The X RAGU (Read AGU) and X
WAGU (Write AGU) support byte and word sized data
space reads and writes, respectively, for MCU and
DSP instructions. The Y AGU supports word sized
data reads for the DSP MACclass of instructions only.
They are each capable of supporting two types of data
addressing:
When executing instructions which require two source
operands to be concurrently fetched (i.e., the MACclass
of DSP instructions), both the X RAGU and Y AGU are
used simultaneously and the data space is split into 2
independent address spaces, X and Y. The Y AGU sup-
ports Register Indirect Post-Modified and Modulo
Addressing only. Note that the data write phase of the
MACclass of instruction does not split X and Y address
space. The write EA is calculated using the X WAGU
and the data space is configured for full 64 Kbyte
access.
• Linear Addressing
• Modulo (Circular) Addressing
In addition, the X WAGU can support:
• Bit-Reversed Addressing
In the Split Data Space mode, some W register address
pointers are dedicated to X RAGU, and others to Y
AGU. The EAs of each operand must, therefore, be
restricted to be within different address spaces. If they
are not, one of the EAs will be outside the address
space of the corresponding data space (and will fetch
the bus default value, 0x0000).
Linear and Modulo Data Addressing modes can be
applied to data space or program space. Bit-Reversed
addressing is only applicable to data space addresses.
7.1
Data Space Organization
Although the data space memory is organized as 16-bit
words, all effective addresses (EAs) are byte
addresses. Instructions can thus, access individual
bytes, as well as properly aligned words. Word
addresses must be aligned at even boundaries. Mis-
aligned word accesses are not supported, and if
attempted, will initiate an address error trap.
7.2
Instruction Addressing Modes
The Addressing modes in Table 7-1 form the basis of
the Addressing modes optimized to support the specific
features of individual instructions. The Addressing
modes provided in the MAC class of instructions are
somewhat different from those in the other instruction
types.
When executing instructions which require just one
source operand to be fetched from data space, the X
RAGU and X WAGU are used to calculate the effective
address. The X RAGU and X WAGU can generate any
address in the 64 Kbyte data space. They support all
MCU Addressing modes and Modulo Addressing for
Some Addressing mode combinations may lead to a
one-cycle stall during instruction execution, or are not
allowed, as discussed in Section 7.3.
TABLE 7-1:
FUNDAMENTAL ADDRESSING MODES SUPPORTED
Addressing Mode
Description
File Register Direct
Register Direct
The address of the file register is specified explicitly.
The contents of a register are accessed directly.
The contents of Wn forms the EA.
Register Indirect
Register Indirect Post-modified
The contents of Wn forms the EA. Wn is post-modified (incremented or decre-
mented) by a constant value.
Register Indirect Pre-modified
Wn is pre-modified (incremented or decremented) by a signed constant value
to form the EA.
Register Indirect with Register Offset The sum of Wn and Wb forms the EA.
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dsPIC30F
In summary, the following addressing modes supported
by Move and Accumulator instructions:
7.2.1
FILE REGISTER INSTRUCTIONS
Most file register instructions use a 13-bit address field
(f) to directly address data present in the first 8192
bytes of data memory. These memory locations are
known as File Registers. Most file register instructions
employ a working register W0, which is denoted as
WREG in these instructions. The destination is typically
either the same file register, or WREG (with the excep-
tion of the MULinstruction), which writes the result to a
register or register pair.
• Register Direct
• Register Indirect
• Register Indirect Post-decremented
• Register Indirect Post-incremented
• Register Indirect Pre-decremented
• Register Indirect Pre-incremented
• Register Indirect with Register Offset (Indexed)
• 10-bit Literal
7.2.2
MCU INSTRUCTIONS
• 16-bit Literal
The three-operand MCU instructions are of the form:
Operand 3 = Operand 1 <function> Operand 2
Note: Not all instructions support all the Address-
ing modes given above. Individual instruc-
tions may support different subsets of
these Addressing modes.
where Operand 1 is always a working register (i.e., the
Addressing mode can only be register direct), which is
referred to as Wb. Operand 2 can be W register,
fetched from data memory, or 5-bit literal. In two-
operand instructions, the result location is the same as
that of one of the operands. Certain MCU instructions
are one-operand operations. The following addressing
modes are supported by MCU instructions:
7.2.4
MAC INSTRUCTIONS
The dual source operand DSP instructions (CLR, ED,
EDAC, MAC, MPY, MPY.N, MOVSACand MSC), also
referred to as MACinstructions, utilize a simplified set of
Addressing modes to allow the user to effectively
manipulate the data pointers through register indirect
tables.
• Register Direct
• Register Indirect
The 2 source operand pre-fetch registers must be a
member of the set {W8, W9, W10, W11}. For data
reads, W8 and W9 will always be directed to the X
RAGU and W10 and W11 will always be directed to the
Y AGU. The effective addresses generated (before and
after modification) must, therefore, be valid addresses
within X data space for W8 and W9, and Y data space
for W10 and W11.
• Register Indirect Post-decremented
• Register Indirect Post-incremented
• Register Indirect Pre-decremented
• Register Indirect Pre-incremented
• 5-bit or 10-bit Literal
Note: Not all instructions support all the Address-
ing modes given above. Individual instruc-
tions may support different subsets of
these Addressing modes.
Note: Register Indirect with Register Offset
Addressing is only available for W9 (in X
space) and W11 (in Y space).
7.2.3
MOVE AND ACCUMULATOR
INSTRUCTIONS
In summary, the following addressing modes are sup-
ported by the MACclass of instructions:
Move instructions and the DSP accumulator class of
instructions provide a greater degree of addressing
flexibility than other instructions. In addition to the
Addressing modes supported by most MCU instruc-
tions, Move and Accumulator instructions also support
Register Indirect with Register Offset Addressing
mode, also referred to as Register Indexed mode.
• Register Indirect
• Register Indirect Post-incremented by 2
• Register Indirect Post-incremented by 4
• Register Indirect Post-incremented by 6
• Register Indirect with Register Offset (Indexed)
7.2.5
OTHER INSTRUCTIONS
Note: For the MOV instructions, the Addressing
mode specified in the instruction can differ
for the source and destination EA. How-
ever, the 4-bit Wb (Register Offset) field is
shared between both source and destina-
tion (but typically only used by one).
Besides the various Addressing modes outlined above,
some instructions use literal constants of various sizes.
For example, BRA (branch) instructions use 16-bit
signed literals to specify the branch destination directly,
whereas the DISI instruction uses a 14-bit unsigned
literal field. In some instructions, such as ADD Acc, the
source of an operand or result is implied by the opcode
itself. Certain operations, such as NOP, do not have any
operands.
DS70032B-page 70
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by stalling the instruction execution for one instruction
cycle, thereby, allowing the write to complete before
the next read is started.
7.3
Instruction Stalls
7.3.1
INTRODUCTION
In order to maximize data space EA calculation and
operand fetch time, the X data space read and write
accesses are partially pipelined. The latter half of the
read phase overlaps the first half of the write phase of
an instruction, as shown in Section 2.
7.3.2
RAW DEPENDENCY DETECTION
During the instruction pre-decode, the core determines
if any address register dependency is imminent across
an instruction boundary. The stall detection logic com-
pares the W register (if any) used for the destination
EA of the instruction currently being executed, with the
W register to be used by the source EA (if any) of the
pre-fetched instruction. As the W registers are also
memory mapped, the stall detection logic also derives
an SFR address from the W register being used by the
destination EA (see Figure 7-1), and determines
whether this address is being issued during the write
phase of the instruction currently being executed.
Address register data dependencies may arise
between successive read and write operations, using
common registers.
There are two types of dependencies possible in the
dsPIC30F architecture. ‘Read After Write’ (RAW)
dependencies occur across instruction boundaries
and are detected by the hardware. ‘Write After Read’
(WAR) dependencies occur within instructions and are
detected by the assembler, enabling users to modify
their program to avoid it.
When it observes a match between the destination
and source registers, a set of rules are applied to
decide whether or not to stall the instruction by one
cycle. Table 7-2 lists out the various RAW conditions
which cause an instruction execution stall.
An example of a RAW dependency is a write operation
that modifies W5 (on falling Q4), followed by a read
operation that uses W5 as an address pointer (starting
in Q3). W5 will not be valid for the read operation until
the earlier write completes. This problem is resolved
FIGURE 7-1:
W REGISTER SFR ADDRESS DERIVATION
WDST FROM IR
0 0 0 0 0 0 0 0 0 0 0
0
N3 N2 N1 N0
WDST SFR ADDRESS
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TABLE 7-2:
RAW DEPENDENCY RULES (DETECTION BY HARDWARE)
Destination
Addressing Mode
Using Wn
Source Addressing
Mode Using Wn
Examples
(Wn = W2)
Status
Direct
Direct
Allowed ADD.w W0, W1, W2
MOV.w W2, W3
Direct
Indirect
Stall
Stall
ADD.w W0, W1, W2
MOV.w [W2], W3
ADD.w W0, W1, W2
MOV.w [W2++], W3
Direct
Indirect with Pre- or
Post-Modification
Direct
Indirect
Indirect
Indirect
Indirect
Indirect
Allowed ADD.w W0, W1, [W2]
MOV.w W2, W3
Indirect
Indirect
Allowed ADD.w W0, W1, [W2]
MOV.w [W2], W3
Stall
ADD.w W0, W1, [W2] ; W2=0x0004 (mapped W2)
MOV.w [W2], W3 ; (i.e. if W2 = addr. of W2)
Indirect with Pre- or
Post-Modification
Indirect with Pre- or
Post-Modification
Allowed ADD.w W0, W1, [W2]
MOV.w [W2++], W3
Stall
ADD.w W0, W1, [W2] ; W2=0x0004 (mapped W2)
MOV.w [W2++], W3 ; (i.e. if W2 = addr. of W2)
Indirect with Pre- or Direct
Post-Modification
Allowed ADD.w W0, W1, [W2++]
MOV.w W2, W3
Indirect with Pre- or Indirect
Post-Modification
Indirect with Pre- or Indirect with Pre- or
Post-Modification Post-Modification
Stall
Stall
ADD.w W0, W1, [W2++]
MOV.w [W2], W3
ADD.w W0, W1, [W2++]
MOV.w [W2++], W3
7.3.3
INSTRUCTION STALLS AND
EXCEPTIONS
7.3.5
INSTRUCTION STALLS AND PSV
Instructions operating in PSV address space are sub-
ject to instruction stalls just like any other instructions.
In order to maintain deterministic operation, instruction
stalls are allowed even if they occur immediately prior
to exception processing.
Should a data dependency be detected in the instruc-
tion immediately following the PSV data access, the
second cycle of the instruction will initiate a stall.
7.3.4
INSTRUCTION STALLS AND FLOW
CHANGE INSTRUCTIONS
Should a data dependency be detected in the instruc-
tion immediately before the PSV data access, the last
cycle of the previous instruction will initiate a stall.
CALL[W]and RCALLwrite to the stack using W15 and
may, therefore, be subjected to an instruction stall if
the source read of the subsequent instruction uses
W15.
7.3.6
WAR DEPENDENCY DETECTION
In this architecture, WAR dependencies can only
occur within an instruction (i.e., not across instruction
boundaries). Therefore, all WAR dependencies are
detected by the assembler by disallowing the use of a
common W register for both source and destination
under certain conditions, as listed in Table 7-3.
GOTO, RETFIE and RETURN instructions are never
subjected to an instruction stall, because they only
perform read operations.
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TABLE 7-3:
WAR DEPENDENCY RULES (DETECTION BY ASSEMBLER)
Source
Addressing Mode Using Wn
Destination Addressing
Mode Using Wn
Examples
(Wn = W1)
Allowed?
Direct
Direct
Yes
Yes
Yes
ADD.w W0, W1, W1
Direct
Direct
Indirect
ADD.w W0, W1, [W1]
Indirect with Pre- or Post-
Modification
ADD.w W0, W1, [W1++]
Indirect
Indirect
Direct
Yes
Yes
Yes
ADD.w W0, [W1], W1
Indirect
ADD.w W0, [W1], [W1]
ADD.w W0, [W1], [W1++]
Indirect with Pre- or Post-Modification Indirect with Pre- or Post-
Modification
Indirect with Pre- or Post-Modification Direct
Indirect with Pre- or Post-Modification Indirect
Yes
No
No
ADD.w W0, [W1++], W1
ADD.w W0, [W1++], [W1]
ADD.w W0, [W1++], [W1++]
Indirect with Pre- or Post-Modification Indirect with Pre- or Post-
Modification
7.4.1
START AND END ADDRESS
7.4
Modulo Addressing
The Modulo Addressing scheme requires that a start-
ing and an end address be specified and loaded into
the 16-bit modulo buffer address registers: XMODSRT,
XMODEND, YMODSRT, YMODEND.
Modulo addressing is a method of providing an auto-
mated means to support circular data buffers using
hardware. The objective is to remove the need for soft-
ware to perform data address boundary checks when
executing tightly looped code, as is typical in many
DSP algorithms.
Note: The start and end addresses are the first
and last byte addresses of the buffer (irre-
spective of whether it is a word or byte
buffer, or an increasing or decreasing
buffer).
Modulo Addressing can operate in either data or pro-
gram space (since the data pointer mechanism is essen-
tially the same for both). One circular buffer can be
supported in each of the X (which also provides the
pointers into Program space) and Y data spaces. Mod-
ulo Addressing can operate on any W register pointer.
However, it is not advisable to use W14 or W15 for Mod-
ulo Addressing, since these two registers are used as
the Stack Frame Pointer and Stack Pointer, respectively.
If the length of an incrementing buffer is greater than
M = 2N-1, but not greater than M = 2N bytes, then the
last ’N’ bits of the data buffer start address must be
zeros. There are no such restrictions on the end
address of an incrementing buffer. For example, if the
buffer size (modulus value) is chosen to be 100 bytes
(0x64), then the buffer start address for an increment-
ing buffer must contain 7 Least Significant zeros. Valid
start addresses may, therefore, be 0xXX00 and
0xXX80, where ‘X’ is any hexadecimal value. Adding
the buffer length to this value and subtracting 1 will
give the end address to be written into X/YMODEND.
For example, if the start address was chosen to be
In order to minimize the hardware size for modulo
addressing support, certain usage restrictions are
imposed which are discussed in detail in Section 7.4.1
and Section 7.4.4. In summary, any particular circular
buffer can only be allowed to operate in one direction,
as there are certain restrictions on the buffer start
address (for incrementing buffers) or end address (for
decrementing buffers), based upon the direction of the
buffer. The direction is determined from the address
offset sign.
0x2000, then the
X/YMODEND would be set to
(0x2000 + 0x0064 - 1) = 0x2063.
Note: ‘Starting address’ refers to the smallest
address boundary of the circular buffer.
The first access of the buffer may be at any
address within the modulus range (see
Section 7.4.4).
The only exception to the usage restrictions is for buff-
ers which have a power-of-2 length. As these buffers
satisfy the start and end address criteria, they may
operate in a Bi-Directional mode, i.e., address bound-
ary checks will be performed on both the lower and
upper address boundaries.
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In the case of a decrementing buffer, the last ‘N’ bits of
the data buffer end address must be ones. There are
no such restrictions on the start address of a decre-
menting buffer. For example, if the buffer size (modulus
value) is chosen to be 100 bytes (0x64), then the buffer
end address for a decrementing buffer must contain 7
Least Significant ones. Valid end addresses may,
therefore, be 0xXXFF and 0xXX7F, where ‘X’ is any
hexadecimal value. Subtracting the buffer length from
this value and adding 1 will give the start address to be
written into X/YMODSRT. For example, if the end
address was chosen to be 0x207F, then the start
address would be (0x207F - 0x0064+1) = 0x201C,
which is the first physical address of the buffer.
7.4.2
W ADDRESS REGISTER
SELECTION
The Modulo and Bit-Reversed Addressing control reg-
ister MODCON<15:0> contains enable flags plus W
register field to specify the W address registers. The
XWM and YWM fields select which registers will oper-
ate with Modulo Addressing. If XWM = 15, X RAGU and
X WAGU Modulo Addressing is disabled. Similarly, if
YWM = 15, Y AGU Modulo Addressing is disabled.
Note: The XMODSRT and XMODEND registers,
and the XWM register selection, are
shared between X RAGU and X WAGU.
The X address space pointer W register (XWM) to
which Modulo Addressing is to be applied, is stored in
MODCON<3:0> (see Register 7-1). Modulo Address-
ing is enabled for X data space when XWM is set to any
value other than 15 and the XMODEN bit is set at
MODCON<15>.
Note: Y AGU Modulo Addressing EA calcula-
tions assume word sized data (LS bit of
every EA is always clear), since the Y AGU
only supports word accesses.
In incrementing, as well as decrementing modulo buff-
ers, the buffers must start and end on an aligned word.
Therefore, XMODSRT must be an even address (LS
bit = 0), whereas XMODEND must be an odd address
(LS bit = 1).
The Y address space pointer W register (YWM) to
which Modulo Addressing is to be applied, is stored in
MODCON<7:4> (see Register 7-1). Modulo address-
ing is enabled for Y data space when YWM is set to any
value other than 15 and the YMODEN bit is set at
MODCON<14>.
The length of a circular buffer is not directly specified. It
is determined by the difference between the correspond-
ing start and end addresses. The maximum possible
length of the circular buffer is 32K words (64 Kbytes).
FIGURE 7-2:
INCREMENTING BUFFER MODULO ADDRESSING OPERATION EXAMPLE
Byte
Address
MOV
MOV
MOV
MOV
MOV
MOV
#0x0100,W0
W0,XMODSRT
#0x0163,W0
W0,MODEND
#0x8001,W0
W0,MODCON
;set modulo start address
;set modulo end address
;enable W1, X AGU for modulo
;W0 holds buffer fill value
;point W1 to buffer
0x0100
MOV
MOV
#0x0000,W0
#0x0110,W1
DO
AGAIN,#0x31
W0,[W1++]
;fill the 50 buffer locations
;fill the next location
;increment the fill value
MOV
AGAIN: INC
W0,W0
0x0163
Start Addr = 0x0100
End Addr = 0x0163
Length = 0x0032 words
DS70032B-page 74
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dsPIC30F
FIGURE 7-3:
DECREMENTING BUFFER MODULO ADDRESSING OPERATION EXAMPLE
Byte
Address
MOV
MOV
MOV
MOV
MOV
MOV
#0x01D0,W0
#0,XMODSRT
0x01FF,W0
W0,XMODEND
#0x8001,W0
W0,MODCON
;set modulo start address
;set modulo end address
;enable W1, X AGU for modulo
;W0 holds buffer fill value
;point W1 to buffer
MOV
MOV
#0x000F,W0
#0x01E0,W1
0x01D0
DO
AGAIN,#0x17
W0,[W1--]
;fill the 24 buffer locations
;fill the next location
MOV
AGAIN: DEC
W0,W0 ; decrement the fill value
0x01FF
Start Addr = 0x01D0
End Addr = 0x01FF
Length = 0x0018 words
7.4.3
MODULO ADDRESSING
APPLICABILITY
7.4.4
MODULO ADDRESSING
RESTRICTIONS
Modulo Addressing can be applied to the effective
address (EA) calculation associated with any W regis-
ter. It is important to realize that the address bound-
aries check for addresses less than or greater than the
upper (for incrementing buffers), and lower (for decre-
menting buffers) boundary addresses (not just equal
to). Address changes may, therefore, jump over bound-
aries and still be adjusted correctly (see Section 7.4.4
for restrictions).
As stated in Section 7.4.1, for an incrementing buffer
the circular buffer start address (lower boundary) is
arbitrary, but must be at a ‘zero’ power-of-two bound-
ary. For a decrementing buffer, the circular buffer end
address is arbitrary, but must be at a ‘ones’ boundary.
There are no restrictions regarding how much an EA
calculation can exceed the address boundary being
checked, and still be successfully corrected.
Note: Modulo Addressing works only when Pre-
Modify or Post-Modify Addressing mode is
used to compute the Effective Address.
When an address offset (e.g., [W7+W2] ) is
used, no address correction is performed
and Modulo Addressing fails to produce
the desired result.
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Once configured, the direction of successive
addresses into a buffer should not be changed.
Although all EAs will continue to be generated correctly
irrespective of offset sign, only one address boundary
is checked for each type of buffer. Thus, if a buffer is set
up to be an incrementing buffer by choosing an appro-
priate starting address, then correction of the effective
address will be performed by the AGU at the upper
address boundary, but no address correction will occur
if the EA crosses the lower address boundary. Similarly,
for a decrementing boundary, address correction will
be performed by the AGU at the lower address bound-
ary, but no address correction will take place if the EA
crosses the upper address boundary. The circular
buffer pointer may be freely modified in both directions
without a possibility of out-of-range address access
only when the start address satisfies the condition for
an incrementing buffer (last ‘N’ bits are zeroes) and the
end address satisfies the condition for a decrementing
buffer (last ‘N’ bits are ones). Thus, the Modulo
Addressing capability is truly bi-directional only for
modulo-2 length buffers.
7.5.1
BIT-REVERSED ADDRESSING
IMPLEMENTATION
Bit-Reversed Addressing is enabled when:
1. BWM (W register selection) in the MODCON
register is any value other than 15 (the stack can
not be accessed using Bit-Reversed Address-
ing) and
2. the BREN bit is set in the XBREV register and
3. the Addressing mode is Register Indirect with
Post-Increment.
XB<14:0> is the Bit-Reversed Address modifier or
‘pivot point’ which is typically a constant. In the case of
an FFT computation, its value is equal to half of the FFT
data buffer size.
Note: All Bit-Reversed EA calculations assume
word sized data (LS bit of every EA is
always clear). The XB value is scaled
accordingly to generate compatible (byte)
addresses.
When enabled, Bit-Reversed Addressing will only be
executed with register indirect with Post-Increment
Addressing and word sized data writes. It will not func-
tion for any other Addressing mode or for byte-sized
data, and normal addresses will be generated instead.
When Bit-Reversed Addressing is active, the W
address pointer will always be added to the address
modifier (XB) and the offset associated with the register
Indirect Addressing mode will be ignored. In addition,
as word sized data is a requirement, the LS bit of the
EA is ignored (and always clear).
7.5
Bit-Reversed Addressing
Bit-Reversed Addressing is intended to simplify data
re-ordering for radix-2 FFT algorithms. It is supported
by the X WAGU only, i.e., for data writes only.
The modifier, which may be a constant value or register
contents, is regarded as having its bit order reversed.
The address source and destination are kept in normal
order. Thus, the only operand requiring reversal is the
modifier.
Note: Modulo Addressing and Bit-Reversed
Addressing should not be enabled together.
In the event that the user attempts to do
this, bit reversed addressing will assume
priority when active for the X WAGU, and X
WAGU Modulo Addressing will be disabled.
However, Modulo Addressing will continue
to function in the X RAGU.
FIGURE 7-4:
BIT-REVERSED ADDRESS EXAMPLE
Sequential Address
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Bit Locations Swapped Left-to-Right
Around Center of Binary Value
b0 b1 b2 b3
Bit-Reversed Address
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4
Pivot Point
XB = 0x0008 for a 16-word Bit-Reversed Buffer
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TABLE 7-4:
BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY)
Normal
Bit-Reversed
Address
Address
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A2
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Decimal
A3
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A2
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Decimal
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
0
8
2
4
3
12
2
4
5
10
6
6
7
14
1
8
9
9
10
11
12
13
14
15
5
13
3
11
7
15
TABLE 7-5:
BIT-REVERSED ADDRESS MODIFIER VALUES
Buffer Size (Words)
XB<14:0> Bit-Reversed Address Modifier Value
32768
16384
8192
4096
2048
1024
512
256
128
64
0x4000
0x2000
0x1000
0x0800
0x0400
0x0200
0x0100
0x0080
0x0040
0x0020
0x0010
0x0008
0x0004
0x0002
0x0001
32
16
8
4
2
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REGISTER 7-1:
MODCON,MODULOANDBIT-REVERSEDADDRESSINGCONTROLREGISTER
Upper Half:
R/W-0
R/W-0
U
U
R/W-0
BWM3
R/W-0
BWM2
R/W-0
BWM1
R/W-0
BWM0
XMODEN YMODEN
bit 15
—
—
bit 8
Lower Half:
R/W-0
YWM3
R/W-0
YWM2
R/W-0
YWM1
R/W-0
YWM0
R/W-0
XWM3
R/W-0
XWM2
R/W-0
R/W-0
XWM0
XWM1
bit 7
bit 0
bit 15
bit 14
XMODEN: X RAGU and X WAGU Modulus Addressing Enable bit
1= X RAGU and X WAGU Modulus Addressing enabled
0= X RAGU and X WAGU Modulus Addressing disabled
YMODEN: Y AGU Modulus Addressing Enable bit
1= Y AGU Modulus Addressing enabled
0= Y AGU Modulus Addressing disabled
bit 13-12 Unimplemented: Read as '0’
bit 11-8 BWM<3:0>: X WAGU W Register Select for Bit-Reversed Addressing bits
1111= Bit-Reversed Addressing disabled
1110= W14 selected for Bit-Reversed Addressing
|
|
0000= W0 selected for Bit-Reversed Addressing
bit 7-4
bit 3-0
YWM<3:0>: Y AGU W Register Select for Modulo Addressing bits
1111= Modulo Addressing disabled
1110= W14 selected for Modulo Addressing
|
|
0000= W0 selected for Modulo Addressing
XWM<3:0>: X RAGU and X WAGU W Register Select for Modulo Addressing bits
1111= Modulo Addressing disabled
1110= W14 selected for Modulo Addressing
|
|
0000= W0 selected for Modulo Addressing
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared
x = bit is unknown
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REGISTER 7-2:
Upper Half:
XMODSRT, X AGU MODULO ADDRESSING START REGISTER
R/W-0
XS15
R/W-0
XS14
R/W-0
XS13
R/W-0
XS12
R/W-0
XS11
R/W-0
XS10
R/W-0
XS9
R/W-0
XS8
bit 8
bit 15
Lower Half:
R/W-0
XS7
R/W-0
XS6
R/W-0
XS5
R/W-0
XS4
R/W-0
XS3
R/W-0
XS2
R/W-0
XS1
R/W-0
XS0
bit 7
bit 0
bit 15-0 XS<15:0>: X RAGU and X WAGU Modulo Addressing Start Address bits
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
REGISTER 7-3:
Upper Half:
XMODEND, X AGU MODULO ADDRESSING END REGISTER
R/W-0
XE15
R/W-0
XE14
R/W-0
XE13
R/W-0
XE12
R/W-0
XE11
R/W-0
XE10
R/W-0
XE9
R/W-0
XE8
bit 15
bit 8
Lower Half:
R/W-0
XE7
R/W-0
XE6
R/W-0
XE5
R/W-0
XE4
R/W-0
XE3
R/W-0
XE2
R/W-0
XE1
R/W-0
XE0
bit 7
bit 0
bit 15-0 XE<15:0>: X RAGU and X WAGU Modulo Addressing End Address bits
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
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REGISTER 7-4:
YMODSRT, Y AGU MODULO ADDRESSING START REGISTER
Upper Half:
R/W-0
YS15
R/W-0
YS14
R/W-0
YS13
R/W-0
YS12
R/W-0
YS11
R/W-0
YS10
R/W-0
YS9
R/W-0
YS8
bit 15
bit 8
Lower Half:
R/W-0
YS7
R/W-0
YS6
R/W-0
YS5
R/W-0
YS4
R/W-0
YS3
R/W-0
YS2
R/W-0
YS1
R/W-0
YS0
bit 7
bit 0
bit 15-0 YS<15:0>: Y AGU Modulo Addressing Start Address bits
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
REGISTER 7-5:
Upper Half:
YMODEND, Y AGU MODULO ADDRESSING END REGISTER
R/W-0
YE15
R/W-0
YE14
R/W-0
YE13
R/W-0
YE12
R/W-0
YE11
R/W-0
YE10
R/W-0
YE9
R/W-0
YE8
bit 8
bit 15
Lower Half:
R/W-0
YE7
R/W-0
YE6
R/W-0
YE5
R/W-0
YE4
R/W-0
YE3
R/W-0
YE2
R/W-0
YE1
R/W-0
YE0
bit 7
bit 0
bit 15-0 YE<15:0>: Y AGU Modulo Addressing End Address bits
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
DS70032B-page 80
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dsPIC30F
REGISTER 7-6:
Upper Half:
XBREV, X WAGU BIT REVERSAL ADDRESSING CONTROL REGISTER
R/W-0
BREN
R/W-0
XB14
R/W-0
XB13
R/W-0
XB12
R/W-0
XB11
R/W-0
XB10
R/W-0
XB9
R/W-0
XB8
bit 8
bit 15
Lower Half:
R/W-0
XB7
R/W-0
XB6
R/W-0
XB5
R/W-0
XB4
R/W-0
XB3
R/W-0
XB2
R/W-0
XB1
R/W-0
XB0
bit 7
bit 0
bit 15
BREN: Bit-Reversed Addressing (X WAGU) Enable bit
1= Bit-Reversed Addressing enabled
0= Bit-Reversed Addressing disabled
bit 14-0 XB<14:0>: X WAGU Bit-Reversed Modifier bits
e.g., XB<14:0> = 0x0080; modifier for a 128-point radix-2 FFT
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
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dsPIC30F
NOTES:
DS70032B-page 82
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dsPIC30F
All interrupt sources can be user assigned to one of 8
priority levels, 0 through 7, via the IPCx registers.
Each interrupt source is associated with an interrupt
vector, as shown in Table 8-2. Levels 6 and 0 repre-
sent the highest and lowest maskable priorities,
respectively. Level 7 interrupts are non-maskable.
8.0
EXCEPTION PROCESSING
The dsPIC30F has 45 interrupt sources and 8 proces-
sor exceptions (traps), which must be arbitrated based
on a priority scheme.
The processor core is responsible for reading the
Interrupt Vector Table (IVT) and transferring the
address contained in the interrupt vector to the pro-
gram counter. The interrupt vector is transferred from
the program data bus into the program counter, via a
24-bit wide multiplexer on the input of the program
counter.
Certain interrupts have specialized control bits for fea-
tures like edge or level triggered interrupts, interrupt-
on-change, etc. Control of these features remains
within the peripheral module, which generates the
interrupt.
The DISIinstruction can be used to disable the pro-
cessing of interrupts of priorities 7 and lower for a cer-
tain number of instructions, during which the DISI bit
(INTCON2<14>) remains set.
The Interrupt Vector Table (IVT) and Alternate Inter-
rupt Vector Table (AIVT) are placed near the beginning
of program memory (0x000004). The IVT and AIVT
are shown in Table 8-2.
When an interrupt is serviced, the PC is loaded with the
address stored in the vector location in Program mem-
ory that corresponds to the interrupt. There are 63 dif-
ferent vectors within the IVT (refer to Table 8-2). These
vectors are contained in locations 0x000004 through
0x0000FE of program memory (refer to Table 8-2).
These locations contain 24-bit addresses, and in order
to preserve robustness, an address error trap will take
place should the PC attempt to fetch any of these
words during normal execution. This prevents execu-
tion of random data through accidentally decrementing
a PC into vector space, accidentally mapping a data
space address into vector space, or the PC rolling over
to 0x000000 after reaching the end of implemented
program memory space. Execution of a GOTOinstruc-
tion to this vector space will also generate an address
error trap.
The interrupt controller is responsible for pre-process-
ing the interrupts, prior to them being presented to the
processor core. The peripheral interrupts are enabled,
prioritized, and controlled using centralized special
function registers:
• IFS0<15:0>, IFS1<15:0>, IFS2<15:0>
All interrupt request flags are maintained in these
three registers. The flags are set by their respec-
tive peripherals or external signals, and they are
cleared via software.
• IEC0<15:0>, IEC1<15:0>, IEC2<15:0>
All interrupt enable control bits are maintained in
these three registers. These control bits are used
to individually enable interrupts from the peripher-
als or external signals.
• IPC0<15:0> ... IPC11<7:0>
The user assignable priority level associated with
each of these 45 interrupts is held centrally in
these twelve registers.
8.1
Interrupt Priority
The user assignable Interrupt Priority (IP<2:0>) bits for
each individual interrupt source are located in the LS
3-bits of each nibble, within the IPCx register(s). Bit 3
of each nibble is not used and is read as a 0. These
bits define the priority level assigned to a particular
interrupt by the user.
• IPL<2:0> The current CPU priority level is explic-
itly stored in the 16-bit STATUS register that
resides in the processor core.
• INTCON1<15:0>, INTCON2<15:0>
Global interrupt control functions are derived from
these two registers. INTCON1 contains the Global
Interrupt Enable (GIE) bit, as well as the control
and status flags for the processor exceptions. The
INTCON2 register controls the external interrupt
request signal behavior and the use of the alter-
nate vector table.
Note: The user selectable priority levels start at 0
as the lowest priority and level 7, as the
highest priority.
Since more than one interrupt request source may be
assigned to a specific user specified priority level, a
means is provided to assign priority within a given
level. This method is called “Natural Order Priority”
Note: Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit. User software should
ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt.
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dsPIC30F
Table 8-1 lists the interrupt numbers and interrupt
sources for the dsPIC device, and their associated
vector numbers. The Natural Order Priority of an inter-
rupt is numerically identical to its Vector Number.
TABLE 8-1:
NATURAL ORDER PRIORITY
Interrupt Source
INT Vector
Number Number
Highest Natural Order Priority
Note 1: The natural order priority scheme has 0
as the highest priority and 53 as the low-
est priority.
0
8
INT0 - External Interrupt 0
IC1 - Input Compare 1
OC1 - Output Compare 1
T1 - Timer 1
1
9
2: The natural order priority number is the
2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
same as the vector number.
3
The ability for the user to assign every interrupt to one
of eight priority levels implies that the user can assign
a very high overall priority level to an interrupt with a
low natural order priority. For example, the PLVD (Low
Voltage Detect) can be given a priority of 7. The INT0
(external interrupt 0) may be assigned to priority level
0, thus giving it a very low effective priority.
4
IC2 - Input Capture 2
5
OC2 - Output Compare 2
T2 - Timer 2
6
7
TMR3 - Timer 3
8
SPI1
9
U1RX - UART1 Receiver
U1TX - UART1 Transmitter
ADC - ADC Convert Done
NVM - NVM Write Complete
I2C - I2C Transfer Complete
BCL - I2C Bus Collision
Input Change Interrupt
INT1 - External Interrupt 1
IC7 - Input Capture 7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
IC8 - Input Capture 8
OC3 - Output Compare 3
OC4 - Output Compare 4
T4 - Timer 4
T5 - Timer 5
INT2 - External Interrupt 2
U2RX - UART2 Receiver
U2TX - UART2 Transmitter
SPI2
C1 - Combined IRQ for CAN1
IC3 - Input Capture 3
IC4 - Input Capture 4
IC5 - Input Capture 5
IC6 - Input Capture 6
OC5 - Output Compare 5
OC6 - Output Compare 6
OC7 - Output Compare 7
OC8 - Output Compare 8
INT3 - External Interrupt 3
INT4 - External Interrupt 4
C2 - Combined IRQ for CAN2
PWM - PWM Period Match
QEI - Position Counter Compare
DCI - CODEC Transfer Done
LVD - Low Voltage Detect
FLTA - Motor Control PWM Fault A
FLTB - Motor Control PWM Fault B
45- 53 53 - 61 Reserved
Lowest Natural Order Priority
DS70032B-page 84
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dsPIC30F
8.3.1
TRAP SOURCES
8.2
RESET Sequence
The following traps are provided with increasing prior-
ity. However, as all traps are nestable, priority has little
effect.
A RESET is not a true exception, because the inter-
rupt controller is not involved in the RESET process.
The processor clears its registers in response to a
RESET, which forces the PC to zero. The processor
then begins program execution at location 0x000000.
A GOTOinstruction is stored in the first program mem-
ory location, immediately followed by the address tar-
get for the GOTO instruction. The processor executes
the GOTO to the specified address and then begins
operation at the specified target (start) address.
• Software Trap:
Execution of the TRAPinstruction causes an
exception.
• Arithmetic Error Trap:
The Arithmetic Error trap executes under the fol-
lowing three circumstances.
1. Should an attempt be made to divide by
zero, the divide operation will be aborted on
a cycle boundary and the trap taken.
8.2.1
RESET SOURCES
In addition to external, Power-on Resets (POR) and
software RESETS, there are three sources of error
conditions which ‘trap’ to the RESET vector.
2. If enabled, an Arithmetic Error trap will be
taken when an arithmetic operation on
either accumulator A or B, causes an over-
flow from bit 31 and the accumulator guard
bits are unutilized.
• Watchdog Time-out:
The watchdog has timed out, indicating that the
processor is no longer executing the correct flow
of code.
3. If enabled, an Arithmetic Error trap will be
taken when an arithmetic operation on
either accumulator A or B causes a cata-
strophic overflow from bit 39 and all satura-
tion is disabled.
• Illegal Instruction Trap:
Attempted execution of any unused opcodes will
result in an illegal instruction trap. Note that a
fetch of an illegal instruction does not result in an
illegal instruction trap if that instruction is flushed
prior to execution due to a flow change.
• Address Error Trap:
This trap is initiated when any of the following cir-
cumstances occurs:
• Brown-out Reset (BOR):
1. A misaligned data word fetch is attempted.
A momentary dip in the power supply to the
device has been detected, which may result in
malfunction.
2. A data fetch from unused data address
space is attempted.
3. A program fetch from unimplemented user
program address space is attempted.
8.3
Traps
4. A program fetch from vector address space
is attempted.
Traps can be considered as non-maskable, non-stable
interrupts, which adhere to a predefined priority as
shown in Table 8-2. They are intended to provide the
user a means to correct erroneous operation during
debug and when operating within the application.
5. A read (for address) of an uninitialized W
register is attempted.
• Stack Error Trap
This trap is initiated under the following
conditions:
Note: If the user does not intend to take correc-
tive action in the event of a trap error con-
dition, these vectors must be loaded with
the RESET vector address. If, on the other
hand, one of the vectors containing an
invalid address is called, an address error
trap is generated.
1. The stack pointer is loaded with a value
which is greater than the (user program-
mable) limit value written into the SPLIM
register (stack overflow).
2. The stack pointer is loaded with a value
which is less than 0x0800 (simple stack
underflow).
Note that many of these trap conditions can only be
detected when they occur. Consequently, the ques-
tionable instruction is allowed to complete prior to trap
exception processing. If the user chooses to recover
from the error, the result of the erroneous action which
caused the trap may, therefore, have to be corrected.
• Oscillator Fail Trap:
This trap is initiated if the external oscillator fails
and operation becomes reliant on an internal RC
backup.
It is possible that multiple traps can become active
within the same cycle (e.g., a mis-aligned word stack
write to an overflowed address). In such a case, the
fixed priority shown in Figure 8-2 is implemented,
which may require the user to check if other traps are
pending, in order to completely correct the fault.
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The RETFIE (Return from Interrupt) instruction will
unstack the program counter and STATUS registers to
return the processor to its state prior to the interrupt
sequence. The RETFIE instruction will also set the
GIE bit to re-enable interrupts.
8.4
Interrupt Sequence
The GIE (Global Interrupt Enable) bit in the INTCON1
register must be set to enable interrupts, but excep-
tions can be processed, regardless of the state of the
GIE bit.
All interrupt event flags are sampled in the beginning
of each instruction cycle by the IFSx registers. A pend-
ing interrupt request (IRQ) is indicated by the flag bit
being equal to a ‘1’ in an IFSx register. The IRQ will
cause the interrupt to occur if the corresponding bit in
the interrupt enable (IECx) registers is set. For the
remainder of the instruction cycle, the priorities of all
pending interrupt requests are evaluated.
TABLE 8-2:
EXCEPTION VECTORS
RESET - GOTOInstruction
RESET - GOTOAddress
Oscillator Fail Trap Vector
Stack Error Trap Vector
0x000000
0x000002
0x000004
Address Error Trap Vector
Arithmetic Warning Trap Vector
Software Trap Vector
Reserved Vector
Reserved Vector
Reserved Vector
Interrupt 0 Vector
Interrupt 1 Vector
~
IVT
0x000014
If there is a pending IRQ with a priority level equal to or
greater than the current processor priority level in the
status register, an interrupt will be presented to the
processor.
~
~
Interrupt 52 Vector
Interrupt 53 Vector
reserved
0x00007E
0x000080
0x000082
The processor reacts to the interrupt request by
asserting the IACK (Interrupt Acknowledge) signal.
The GIE bit in the INTCON1 register is cleared. This
disables all interrupts until either a RETFIEinstruction
is executed, or the user sets the GIE bit.
reserved
0x000084
Oscillator Fail Trap Vector
Stack Error Trap Vector
Address Error Trap Vector
Arithmetic Warning Trap Vector
Software Trap Vector
Reserved Vector
Reserved Vector
Reserved Vector
Interrupt 0 Vector
Interrupt 1 Vector
~
AIVT
The processor then stacks the current program
counter and the low byte of the processor STATUS
register, as shown in Figure 8-1. The low byte of the
STATUS register contains the processor priority level
at the time, prior to the beginning of the interrupt cycle.
0x000094
0x0000FE
~
~
Interrupt 52 Vector
Interrupt 53 Vector
FIGURE 8-1: INTERRUPT STACK FRAME
0x0000
15
0
8.5
Alternate Vector Table
In Program Memory, the Interrupt Vector Table (IVT) is
followed by the Alternate Interrupt Vector Table (AIVT),
as shown in Table 8-2. Access to the Alternate Vector
Table is provided by the ALTIVT bit in the INTCON2
register. If the ALTIVT bit is set, all interrupt and
exception processes will use the alternate vectors
instead of the default vectors. The alternate vectors
are organized in the same manner as the default vec-
tors. The AIVT supports emulation and debugging
efforts by providing a means to switch between an
application and a support environment, without requir-
ing the interrupt vectors to be reprogrammed. This fea-
ture also enables switching between applications for
evaluation of different software algorithms at run time.
PC<15:0>
SR<7:0> PC<23:16>
<Free Word>
W15 (before CALL)
W15 (after CALL)
POP : [--W15]
PUSH : [W15++]
The processor then loads the priority level for this
interrupt into the status register. This action will disable
all lower priority interrupts until the completion of the
Interrupt Service Routine.
If the AIVT is not required, the program memory allo-
cated to the AIVT may be used for other purposes.
AIVT is not a protected section and may be freely pro-
grammed by the user.
Note: The user can always lower the priority level
by writing a new value into the STATUS
register.
Unless the GIE bit is re-enabled, NO further interrupts
will occur. The Interrupt Service Routine must clear the
interrupt flag bits in the IFSx register before re-
enabling interrupts, in order to avoid recursive
interrupts.
DS70032B-page 86
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dsPIC30F
8.6
Fast Context Saving
8.8
Wake-up from SLEEP and IDLE
A context saving option is available using shadow reg-
isters. Shadow registers are provided for the DA, DC,
N, OV, SZ and C bits in SR, the TBLPAG and PSVPAG
registers, and the registers W0 through W14. The
shadows are only one level deep. The shadow regis-
ters are accessible using the PUSH.S and POP.S
instructions only.
The interrupt controller may be used to wake up the
processor from either SLEEP or IDLE modes, if
SLEEP or IDLE mode is active when the interrupt is
generated.
If the GIE in the INTCON1 register is set, and an
enabled interrupt request of sufficient priority is
received by the interrupt controller, then the standard
interrupt request is presented to the processor. At the
same time, the processor will wake-up from SLEEP or
IDLE and begin execution of the Interrupt Service
Routine (ISR), needed to process the interrupt
request.
When the processor vectors to an interrupt, the
PUSH.S instruction can be used to store the current
value of the aforementioned registers into their respec-
tive shadow registers.
If an ISR of a certain priority uses the PUSH.S and
POP.S instructions for fast context saving, then a
higher priority ISR should not include the same instruc-
tions. Users must save the key registers in software
during a lower priority interrupt, if the higher priority ISR
uses fast context saving.
If the GIE control bit is cleared, the interrupt controller
will not generate an interrupt request to the processor.
The interrupt enable bit must be set for a peripheral to
wake the device from SLEEP. In this case, the proces-
sor will resume normal execution without processing
an ISR.
8.7
External Interrupt Requests
The interrupt controller supports up to five external
interrupt request signals, INT0 - INT4. These inputs
are edge sensitive, i.e., they require a low-to-high or a
high-to-low transition to generate an interrupt request.
The INTCON2 register has five bits, INT0EP - INT4EP,
that select the polarity of the edge detection circuitry.
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dsPIC30F
FIGURE 8-2:
INTERRUPT CONTROLLER BLOCK DIAGRAM
e t r s e g i R b e m r u N o r c t e V
g e R e l L Q e v R I
8 to 3 Line
Priority Encoder
r e d o c n E r i t o i y r P
n e 4 o L i
9 t
n e h G a r p r a G B
3 t o
8
1 # C E N
E N C #
# 0 d e c r o n E e n i l t o 6 6 4
2
E N C #
# 7 d e c r o n E e n i l
s t n p u 4 5 i
t o 6 6 4
6
E N C # 5
N E C #
4
E N C # 3
s t p n u i 4 5
0 # r e d c o D e
4
# 4 d e c r o e D
8 l i t n o
r s o d e 4 5 d e c
e n i l
8 3 t o
e
3
s t b i 4 5
e r s t ) e g R i 2 C I E 0 C - E I ( s t i l b o n t o r C e l n a b E u p r r t e I n t
s t b i 4 5
s ) s i t e r R 2 e S g I F 0 S - ( I F s b i t u t s a t S a l g t F p u r t e r I n
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dsPIC30F
REGISTER 8-1: INTCON1: INTERRUPT CONTROL REGISTER1
Upper Half:
R/W-0
GIE
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
OVATE
OVBTE
COVTE
bit 15
bit 8
Lower Half:
U-0
—
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
—
SWTRAP OVRFLOW ADDRERR STKERR
—
bit 7
bit 0
bit 15
GIE: Global Interrupt Enable bit
1= Interrupts are enabled
0= Interrupts are disabled
bit 14-11 Unimplemented: Read as ‘0’
bit 10
bit 9
bit 8
OVATE: Accumulator A Overflow Trap Enable bit
1= Trap overflow of Accumulator A
0= Trap disabled
OVBTE: Accumulator B Overflow Trap Enable bit
1= Trap overflow of Accumulator B
0= Trap disabled
COVTE: Catastrophic Overflow Trap Enable bit
1= Trap on catastrophic overflow of Accumulator A or B enabled
0= Trap disabled
bit 7-5
bit 4
Unimplemented: Read as ‘0’
SWTRAP: Software Trap Status bit
1= Software trap has occurred
0= Software trap has not occurred
bit 3
bit 2
bit 1
bit 0
OVRFLOW: Arithmetic Error Status bit
1= Overflow trap has occurred
0= Overflow trap has not occurred
ADDRERR: Address Error Trap Status bit
1= Address error trap has occurred
0= Address error trap has not occurred
STKERR: Stack Error Trap Status bit
1= Stack error trap has occurred
0= Stack error trap has not occurred
Unimplemented: Read as ‘0’
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
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dsPIC30F
REGISTER 8-2: INTCON2: INTERRUPT CONTROL REGISTER2
Upper Half:
R/W-0
R-0
U-0
U-0
U-0
U-0
HS/HC,
SC-0
U-0
ALTIVT
DISI
—
—
—
—
LEV8F
—
bit 15
bit 8
Lower Half:
U-0
U-0
U-0
R/W-0
INT4EP
R/W-0
INT3EP
R/W-0
R/W-0
INT1EP
R/W-0
—
—
—
INT2EP
INT0EP
bit 7
bit 0
bit 15
bit 14
ALTIVT: Enable Alternate Interrupt Vector Table bit
1= Use alternate vector table
0= Use standard (default) vector table
DISI: DISIInstruction Status bit
1= DISIinstruction is active
0= DISIis not active
bit 13-10 Unimplemented: Read as ‘0’
bit 9
LEV8F: Level 8 Exception in Progress bit
1= New exceptions (level 8 and below) are inhibited
0= Exceptions are enabled
bit 8-5
bit 4
Unimplemented: Read as ‘0’
INT4EP: External Interrupt #4 Edge Detect Polarity Select bit
1= Enable negative edge detect
0= Enable positive edge detect
bit 3
bit 2
bit 1
bit 0
INT3EP: External Interrupt #3 Edge Detect Polarity Select bit
1= Enable negative edge detect
0= Enable positive edge detect
INT2EP: External Interrupt #2 Edge Detect Polarity Select bit
1= Enable negative edge detect
0= Enable positive edge detect
INT1EP: External Interrupt #1 Edge Detect Polarity Select bit
1= Enable negative edge detect
0= Enable positive edge detect
INT0EP: External Interrupt #0 Edge Detect Polarity Select bit
1= Enable negative edge detect
0= Enable positive edge detect
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
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REGISTER 8-3: IFS0: INTERRUPT FLAG STATUS REGISTER0
Upper Half:
R/W-0
CNIF
R/W-0
BCLIF
R/W-0
I2CIF
R/W-0
NVMIF
R/W-0
ADIF
R/W-0
U1TXIF
R/W-0
U1RXIF
R/W-0
SPI1IF
bit 15
bit 8
Lower Half:
R/W-0
T3IF
R/W-0
T2IF
R/W-0
OC2IF
R/W-0
IC2IF
R/W-0
T1IF
R/W-0
OC1IF
R/W-0
IC1IF
R/W-0
INT0IF
bit 7
bit 0
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
CNIF: Input Change Notification Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
BCLIF: I2C Bus Collision Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
I2CIF: I2C Transfer Complete Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
NVMIF: Non-Volatile Memory Write Complete Interrupt Flag Status bit
1= Interrupt request has occurred
0= No interrupt request has occurred
ADIF: A/D Conversion Complete Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
U1TXIF: UART1 Transmitter Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
U1RXIF: UART1 Receiver Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 8
SPI1IF: SPI1 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 7
T3IF: Timer3 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 6
T2IF: Timer2 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 5
OC2IF: Output Compare Channel 2 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 4
IC2IF: Input Capture Channel 2 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 3
T1IF: Timer1 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 2
OC1IF: Output Compare Channel 1 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 1
IC1IF: Input Capture Channel 1 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
DS70032B-page 92
AdvanceInformation
2002 Microchip Technology Inc.
dsPIC30F
REGISTER 8-3:
IFS0: INTERRUPT FLAG STATUS REGISTER0 (Continued)
bit 0
INT0IF: External Interrupt 0 Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 93
dsPIC30F
REGISTER 8-4:
IFS1: INTERRUPT FLAG STATUS REGISTER1
Upper Half:
R/W-0
IC6IF
R/W-0
IC5IF
R/W-0
IC4IF
R/W-0
IC3IF
R/W-0
C1IF
R/W-0
SPI2IF
R/W-0
R/W-0
U2TXIF
U2RXIF
bit 15
bit 8
Lower Half:
R/W-0
INT2IF
R/W-0
T5IF
R/W-0
T4IF
R/W-0
OC4IF
R/W-0
OC3IF
R/W-0
IC8IF
R/W-0
IC7IF
R/W-0
INT1IF
bit 7
bit 0
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
IC6IF: Input Capture Channel 6 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
IC5IF: Input Capture Channel 5 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
IC4IF: Input Capture Channel 4 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
IC3IF: Input Capture Channel 3 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
C1IF: CAN1 (Combined) Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
SPI2IF: SPI2 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
U2TXIF: UART2 Transmitter Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 8
U2RXIF: UART2 Receiver Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 7
INT2IF: External Interrupt 2 Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 6
T5IF: Timer5 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 5
T4IF: Timer4 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 4
OC4IF: Output Compare Channel 4 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 3
OC3IF: Output Compare Channel 3 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 2
IC8IF: Input Capture Channel 8 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
DS70032B-page 94
AdvanceInformation
2002 Microchip Technology Inc.
dsPIC30F
REGISTER 8-4:
IFS1: INTERRUPT FLAG STATUS REGISTER1 (CONTINUED)
bit 1
bit 0
IC7IF: Input Capture Channel 7 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
INT1IF: External Interrupt 1 Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 95
dsPIC30F
REGISTER 8-5:
Upper Half:
IFS2: INTERRUPT FLAG STATUS REGISTER2
U-0
—
U-0
—
U-0
—
R/W-0
FLTBIF
R/W-0
FLTAIF
R/W-0
LVDIF
R/W-0
DCIIF
R/W-0
QEIIF
bit 15
bit 8
Lower Half:
R/W-0
PWMIF
R/W-0
C2IF
R/W-0
INT4IF
R/W-0
INT3IF
R/W-0
OC8IF
R/W-0
OC7IF
R/W-0
OC6IF
R/W-0
OC5IF
bit 7
bit 0
bit 15-13 Unimplemented: Read as ‘0’
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
FLTBIF: Fault B Input Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
FLTAIF: Fault A Input Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
LVDIF: Programmable Low Voltage Detect Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
DCIIF: Data Converter Interface Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
QEIIF: Quadrature Encoder Interface Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
PWMIF: Motor Control Pulse Width Modulation Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
C2IF: CAN2 (Combined) Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
INT4IF: External Interrupt 4 Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
INT3IF: External Interrupt 3 Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
OC8IF: Output Compare Channel 8 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
OC7IF: Output Compare Channel 7 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
OC6IF: Output Compare Channel 6 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
OC5IF: Output Compare Channel 5 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
DS70032B-page 96
AdvanceInformation
2002 Microchip Technology Inc.
dsPIC30F
REGISTER 8-6:
Upper Half:
IEC0: INTERRUPT ENABLE CONTROL REGISTER0
R/W-0
CNIE
R/W-0
BCLIE
R/W-0
I2CIE
R/W-0
R/W-0
ADIE
R/W-0
R/W-0
R/W-0
SPI1IE
bit 8
NVMIE
U1TXIE U1RXIE
bit 15
Lower Half:
R/W-0
T3IE
R/W-0
T2IE
R/W-0
OC2IE
R/W-0
IC2IE
R/W-0
T1IE
R/W-0
OC1IE
R/W-0
IC1IE
R/W-0
INT0IE
bit 7
bit 0
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
CNIE: Input Change Notification Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
BCLIE: I2C Bus Collision Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
I2CIE: I2C Transfer Complete Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
NVMIE: Non-Volatile Memory Write Complete Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
ADIE: A/D Conversion Complete Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
U1TXIE: UART1 Transmitter Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
U1RXIE: UART1 Receiver Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 8
SPI1IE: SPI1 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 7
T3IE: Timer3 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 6
T2IE: Timer2 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 5
OC2IE: Output Compare Channel 2 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 4
IC2IE: Input Capture Channel 2 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 3
T1IE: Timer1 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 2
OC1IE: Output Compare Channel 1 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 97
dsPIC30F
REGISTER 8-6:
IEC0 - INTERRUPT ENABLE CONTROL REGISTER0 (Continued)
bit 1
bit 0
IC1IE: Input Capture Channel 1 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
INT0IE: External Interrupt 0 Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
DS70032B-page 98
AdvanceInformation
2002 Microchip Technology Inc.
dsPIC30F
REGISTER 8-7:
Upper Half:
IEC1: INTERRUPT ENABLE CONTROL REGISTER1
R/W-0
IC6IE
R/W-0
IC5IE
R/W-0
IC4IE
R/W-0
IC3IE
R/W-0
C1IE
R/W-0
R/W-0
R/W-0
U2RXIE
bit 8
SPI2IE
U2TXIE
bit 15
Lower Half:
R/W-0
R/W-0
T5IE
R/W-0
T4IE
R/W-0
OC4IE
R/W-0
OC3IE
R/W-0
IC8IE
R/W-0
IC7IE
R/W-0
INT2IE
INT1IE
bit 7
bit 0
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
IC6IE: Input Capture Channel 6 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
IC5IE: Input Capture Channel 5 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
IC4IE: Input Capture Channel 4 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
IC3IE: Input Capture Channel 3 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
C1IE: CAN1 (Combined) Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
SPI2IE: SPI2 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
U2TXIE: UART2 Transmitter Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 8
U2RXIE: UART2 Receiver Interrupt Enable bit
1 = Interrupt request enabled
0= Interrupt request not enabled
bit 7
INT2IE: External Interrupt 2 Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 6
T5IE: Timer5 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 5
T4IE: Timer4 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 4
OC4IE: Output Compare Channel 4 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 3
OC3IE: Output Compare Channel 3 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 2
IC8IE: Input Capture Channel 8 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 99
dsPIC30F
REGISTER 8-7:
IEC1 - INTERRUPT ENABLE CONTROL REGISTER1 (Continued)
bit 1
bit 0
IC7IE: Input Capture Channel 7 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
INT1IE: External Interrupt 1 Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
DS70032B-page 100
AdvanceInformation
2002 Microchip Technology Inc.
dsPIC30F
REGISTER 8-8:
Upper Half:
IEC2: INTERRUPT ENABLE CONTROL REGISTER2
U-0
—
bit 15
U-0
—
U-0
—
R/W-0
FLTBIE
R/W-0
FLTAIE
R/W-0
LVDIE
R/W-0
DCIIE
R/W-0
QEIIE
bit 8
Lower Half:
R/W-0
PWMIE
R/W-0
C2IE
R/W-0
INT4IE
R/W-0
INT3IE
R/W-0
OC8IE
R/W-0
OC7IE
R/W-0
OC6IE
R/W-0
OC5IE
bit 7
bit 0
bit 15-13 Unimplemented: Read as ‘0’
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
FLTBIE: Fault B Input Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
FLTAIE: Fault A Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
LVDIE: Programmable Low Voltage Detect Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
DCIIE: Data Converter Interface Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
QEIIE: Quadrature Encoder Interface Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
PWMIE: Motor Control Pulse Width Modulation Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
C2IE: CAN2 (Combined) Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
INT4IE: External Interrupt 4 Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
INT3IE: External Interrupt 3 Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
OC8IE: Output Compare Channel 8 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
OC7IE: Output Compare Channel 7 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
OC6IE: Output Compare Channel 6 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
OC5IE: Output Compare Channel 5 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 101
dsPIC30F
REGISTER 8-9:
IPC0: INTERRUPT PRIORITY CONTROL REGISTER0
Upper Half:
U-0
R/W-0
T1IP2
R/W-0
T1IP1
R/W-0
T1IP0
U-0
R/W-0
R/W-0
R/W-0
—
—
OC1IP2 OC1IP1
OC1IP0
bit 15
bit 8
Lower Half:
U-0
R/W-0
IC1IP2
R/W-0
IC1IP1
R/W-0
IC1IP0
U-0
R/W-0
R/W-0
R/W-0
—
—
INT0IP2 INT0IP1
INT0IP0
bit 7
bit 0
bit 15
Unimplemented: Read as ‘0’
bit 14-12 T1IP<2:0>: Timer1 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
.
.
.
001= Interrupt is priority 1
000= Interrupt is priority 0 (lowest interrupt priority)
bit 11
Unimplemented: Read as ‘0’
bit 10-8 OC1IP<2:0>: Output Compare Channel 1 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
.
.
.
001= Interrupt is priority 1
000= Interrupt is priority 0 (lowest interrupt priority)
bit 7
Unimplemented: Read as ‘0’
bit 6-4
IC1IP<2:0>: Input Capture Channel 1 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
.
.
.
001= Interrupt is priority 1
000= Interrupt is priority 0 (lowest interrupt priority)
bit 3
Unimplemented: Read as ‘0’
bit 2-0
INT0IP<2:0>: External Interrupt 0 Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
.
.
.
001= Interrupt is priority 1
000= Interrupt is priority 0 (lowest interrupt priority)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
DS70032B-page 102
AdvanceInformation
2002 Microchip Technology Inc.
dsPIC30F
REGISTER 8-10: IPC1: INTERRUPT PRIORITY CONTROL REGISTER1
Upper Half:
U-0
R/W-0
T3IP2
R/W-0
T3IP1
R/W-0
T3IP0
U-0
R/W-0
T2IP2
R/W-0
T2IP1
R/W-0
T2IP0
bit 8
—
—
bit 15
Lower Half:
U-0
R/W-0
R/W-0
OC2IP1
R/W-0
OC2IP0
U-0
R/W-0
IC2IP2
R/W-0
IC2IP1
R/W-0
IC2IP0
—
OC2IP2
—
bit 7
bit 0
bit 15
Unimplemented: Read as ‘0’
bit 14-12 T3IP<2:0>: Timer3 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
.
.
.
001= Interrupt is priority 1
000= Interrupt is priority 0 (lowest interrupt priority)
bit 11
Unimplemented: Read as ‘0’
bit 10-8 T2IP<2:0>: Timer2 Interrupt Priority
111= Interrupt is priority 7 (highest priority interrupt)
.
.
.
001= Interrupt is priority 1
000= Interrupt is priority 0 (lowest interrupt priority)
bit 7
Unimplemented: Read as ‘0’
bit 6-4
OC2IP<2:0>: Output Compare Channel 2 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
.
.
.
001= Interrupt is priority 1
000= Interrupt is priority 0 (lowest interrupt priority)
bit 3
Unimplemented: Read as ‘0’
bit 2-0
IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
.
.
.
001= Interrupt is priority 1
000= Interrupt is priority 0 (lowest interrupt priority)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 103
dsPIC30F
REGISTER 8-11: IPC2: INTERRUPT PRIORITY CONTROL REGISTER2
Upper Half:
U-0
R/W-0
ADIP2
R/W-0
ADIP1
R/W-0
ADIP0
U-0
R/W-0
R/W-0
R/W-0
—
—
U1TXIP2 U1TXIP1 U1TXIP0
bit 8
bit 15
Lower Half:
U-0
R/W-0
R/W-0
U1RXIP1
R/W-0
U1RXIP0
U-0
R/W-0
R/W-0
R/W-0
—
U1RXIP2
—
SPI1IP2 SPI1IP1
SPI1IP0
bit 7
bit 0
bit 15
Unimplemented: Read as ‘0’
bit 14-12 ADIP<2:0>: A/D Conversion Complete Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
.
.
.
001= Interrupt is priority 1
000= Interrupt is priority 0 (lowest interrupt priority)
bit 11
Unimplemented: Read as ‘0’
bit 10-8 U1TXIP<0>: UART1 Transmitter Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
.
.
.
001= Interrupt is priority 1
000= Interrupt is priority 0 (lowest interrupt priority)
bit 7
Unimplemented: Read as ‘0’
bit 6-4
U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
.
.
.
001= Interrupt is priority 1
000= Interrupt is priority 0 (lowest interrupt priority)
bit 3
Unimplemented: Read as ‘0’
bit 2-0
SPI1IP<2:0>: SPI1 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
.
.
.
001= Interrupt is priority 1
000= Interrupt is priority 0 (lowest interrupt priority)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
DS70032B-page 104
AdvanceInformation
2002 Microchip Technology Inc.
dsPIC30F
REGISTER 8-12: IPC3: INTERRUPT PRIORITY CONTROL REGISTER3
Upper Half:
U-0
R/W-0
CNIP2
R/W-0
CNIP1
R/W-0
CNIP0
U-0
R/W-0
R/W-0
R/W-0
BCLIP0
bit 8
—
—
BCLIP2
BCLIP1
bit 15
Lower Half:
U-0
R/W-0
I2CIP2
R/W-0
I2CIP1
R/W-0
I2CIP0
U-0
R/W-0
R/W-0
R/W-0
—
—
NVMIP2 NVMIP1
NVMIP0
bit 7
bit 0
bit 15
Unimplemented: Read as ‘0’
bit 14-12 CNIP<2:0>: Input Change Notification Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
.
.
.
001= Interrupt is priority 1
000= Interrupt is priority 0 (lowest interrupt priority)
bit 11
Unimplemented: Read as ‘0’
bit 10-8 BCLIP<2:0>: I2C Bus Collision Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
.
.
.
001= Interrupt is priority 1
000= Interrupt is priority 0 (lowest interrupt priority)
bit 7
Unimplemented: Read as ‘0’
bit 6-4
I2CIP<2:0>: I2C Transfer Complete Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
.
.
.
001= Interrupt is priority 1
000= Interrupt is priority 0 (lowest interrupt priority)
bit 3
Unimplemented: Read as ‘0’
bit 2-0
NVMIP<2:0>: Non-Volatile Memory Write Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
.
.
.
001= Interrupt is priority 1
000= Interrupt is priority 0 (lowest interrupt priority)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 105
dsPIC30F
REGISTER 8-13: IPC4: INTERRUPT PRIORITY CONTROL REGISTER4
Upper Half:
U-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
IC8IP2
R/W-0
IC8IP1
R/W-0
IC8IP0
—
OC3IP2
OC3IP1
OC3IP0
—
bit 15
bit 8
Lower Half:
U-0
R/W-0
IC7IP2
R/W-0
IC7IP1
R/W-0
IC7IP0
U-0
R/W-0
R/W-0
R/W-0
—
—
INT1IP2 INT1IP1
INT1IP0
bit 7
bit 0
bit 15
Unimplemented: Read as ‘0’
bit 14-12 OC3IP<2:0>: Output Compare Channel 3 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
.
.
.
001= Interrupt is priority 1
000= Interrupt is priority 0 (lowest interrupt priority)
bit 11
Unimplemented: Read as ‘0’
bit 10-8 IC8IP<2:0>: Input Capture Channel 8 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
.
.
.
001= Interrupt is priority 1
000= Interrupt is priority 0 (lowest interrupt priority)
bit 7
Unimplemented: Read as ‘0’
bit 6-4
IC7IP<2:0>: Input Capture Channel 7 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
.
.
.
001= Interrupt is priority 1
000= Interrupt is priority 0 (lowest interrupt priority)
bit 3
Unimplemented: Read as ‘0’
bit 2-0
INT1IP<2:0>: External Interrupt 1 Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
.
.
.
001= Interrupt is priority 1
000= Interrupt is priority 0 (lowest interrupt priority)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
DS70032B-page 106
AdvanceInformation
2002 Microchip Technology Inc.
dsPIC30F
REGISTER 8-14: IPC5: INTERRUPT PRIORITY CONTROL REGISTER5
Upper Half:
U-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
T5IP2
R/W-0
T5IP1
R/W-0
T5IP0
bit 8
—
INT2IP2
INT2IP1
INT2IP0
—
bit 15
Lower Half:
U-0
R/W-0
T4IP2
R/W-0
T4IP1
R/W-0
T4IP0
U-0
R/W-0
R/W-0
R/W-0
—
—
OC4IP2 OC4IP1
OC4IP0
bit 7
bit 0
bit 15
Unimplemented: Read as ‘0’
bit 14-12 INT2IP<2:0>: External Interrupt 2 Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
.
.
.
001= Interrupt is priority 1
000= Interrupt is priority 0 (lowest interrupt priority)
bit 11
Unimplemented: Read as ‘0’
bit 10-8 T5IP<2:0>: Timer5 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
.
.
.
001= Interrupt is priority 1
000= Interrupt is priority 0 (lowest interrupt priority)
bit 7
Unimplemented: Read as ‘0’
bit 6-4
T4IP<2:0>: Timer4 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
.
.
.
001= Interrupt is priority 1
000= Interrupt is priority 0 (lowest interrupt priority)
bit 3
Unimplemented: Read as ‘0’
bit 2-0
OC4IP<2:0>: Output Compare Channel 4 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
.
.
.
001= Interrupt is priority 1
000= Interrupt is priority 0 (lowest interrupt priority)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
2002 Microchip Technology Inc.
Advance Information
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dsPIC30F
REGISTER 8-15: IPC6: INTERRUPT PRIORITY CONTROL REGISTER6
Upper Half:
U-0
R/W-0
C1IP2
R/W-0
C1IP1
R/W-0
C1IP0
U-0
R/W-0
R/W-0
R/W-0
—
—
SPI2IP2 SPI2IP1
SPI2IP0
bit 15
bit 8
Lower Half:
U-0
R/W-0
R/W-0
U2TXIP1
R/W-0
U2TXIP0
U-0
R/W-0
R/W-0
R/W-0
—
U2TXIP2
—
U2RXIP2 U2RXIP1 U2RXIP0
bit 0
bit 7
bit 15
Unimplemented: Read as ‘0’
bit 14-12 C1IP<2:0>: CAN1 (combined) Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
.
.
.
001= Interrupt is priority 1
000= Interrupt is priority 0 (lowest interrupt priority)
bit 11
Unimplemented: Read as ‘0’
bit 10-8 SPI2IP<2:0>: SPI2 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
.
.
.
001= Interrupt is priority 1
000= Interrupt is priority 0 (lowest interrupt priority)
bit 7
Unimplemented: Read as ‘0’
bit 6-4
U2TXIP<2:0>: UART2 Transmitter Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
.
.
.
001= Interrupt is priority 1
000= Interrupt is priority 0 (lowest interrupt priority)
bit 3
Unimplemented: Read as ‘0’
bit 2-0
U2RXIP<2:0>: UART2 Receiver Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
.
.
.
001= Interrupt is priority 1
000= Interrupt is priority 0 (lowest interrupt priority)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
DS70032B-page 108
AdvanceInformation
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dsPIC30F
REGISTER 8-16: IPC7: INTERRUPT PRIORITY CONTROL REGISTER7
Upper Half:
U-0
R/W-0
IC6IP2
R/W-0
IC6IP1
R/W-0
IC6IP0
U-0
R/W-0
IC5IP2
R/W-0
IC5IP1
R/W-0
IC5IP0
bit 8
—
—
bit 15
Lower Half:
U-0
R/W-0
IC4IP2
R/W-0
IC4IP1
R/W-0
IC4IP0
U-0
R/W-0
IC3IP2
R/W-0
IC3IP1
R/W-0
IC3IP0
—
—
bit 7
bit 0
bit 15
Unimplemented: Read as ‘0’
bit 14-12 IC6IP<2:0>: Input Capture Channel 6 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
.
.
.
001= Interrupt is priority 1
000= Interrupt is priority 0 (lowest interrupt priority)
bit 11
Unimplemented: Read as ‘0’
bit 10-8 IC5IP<2:0>: Input Capture Channel 5 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
.
.
.
001= Interrupt is priority 1
000 = Interrupt is priority 0 (lowest interrupt priority)
bit 7
Unimplemented: Read as ‘0’
bit 6-4
IC4IP<2:0>: Input Capture Channel 4 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
.
.
.
001= Interrupt is priority 1
000= Interrupt is priority 0 (lowest interrupt priority)
bit 3
Unimplemented: Read as ‘0’
bit 2-0
IC3IP<2:0>: Input Capture Channel 3 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
.
.
.
001= Interrupt is priority 1
000= Interrupt is priority 0 (lowest interrupt priority)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 109
dsPIC30F
REGISTER 8-17: IPC8: INTERRUPT PRIORITY CONTROL REGISTER8
Upper Half:
U-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
—
OC8IP2
OC8IP1
OC8IP0
—
OC7IP2 OC7IP1
OC7IP0
bit 15
bit 8
Lower Half:
U-0
R/W-0
R/W-0
OC6IP1
R/W-0
OC6IP0
U-0
R/W-0
R/W-0
R/W-0
—
OC6IP2
—
OC5IP2 OC5IP1
OC5IP0
bit 7
bit 0
bit 15
Unimplemented: Read as ‘0’
bit 14-12 OC8IP<2:0>: Output Compare Channel 8 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
.
.
.
001= Interrupt is priority 1
000= Interrupt is priority 0 (lowest interrupt priority)
bit 11
Unimplemented: Read as ‘0’
bit 10-8 OC7IP<2:0>: Output Compare Channel 7 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
.
.
.
001= Interrupt is priority 1
000= Interrupt is priority 0 (lowest interrupt priority)
bit 7
Unimplemented: Read as ‘0’
bit 6-4
OC6IP<2:0>: Output Compare Channel 6 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
.
.
.
001= Interrupt is priority 1
000= Interrupt is priority 0 (lowest interrupt priority)
bit 3
Unimplemented: Read as ‘0’
bit 2-0
OC5IP<2:0>: Output Compare Channel 5 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
.
.
.
001= Interrupt is priority 1
000= Interrupt is priority 0 (lowest interrupt priority)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
DS70032B-page 110
AdvanceInformation
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dsPIC30F
REGISTER 8-18: IPC9: INTERRUPT PRIORITY CONTROL REGISTER9
Upper Half:
U-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
C2IP2
R/W-0
C2IP1
R/W-0
C2IP0
bit 8
—
PWMIP2
PWMIP1
PWMIP0
—
bit 15
Lower Half:
U-0
R/W-0
R/W-0
INT4IP1
R/W-0
INT4IP0
U-0
R/W-0
R/W-0
R/W-0
—
INT4IP2
—
INT3IP2 INT3IP1
INT3IP0
bit 7
bit 0
bit 15
Unimplemented: Read as ‘0’
bit 14-12 PWMIP<2:0>: Motor Control Pulse Width Modulation Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
.
.
.
001= Interrupt is priority 1
000= Interrupt is priority 0 (lowest interrupt priority)
bit 11
Unimplemented: Read as ‘0’
bit 10-8 C2IP<2:0>: CAN2 (combined) Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
.
.
.
001= Interrupt is priority 1
000= Interrupt is priority 0 (lowest interrupt priority)
bit 7
Unimplemented: Read as ‘0’
bit 6-4
INT4IP<2:0>: External Interrupt 4 Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
.
.
.
001= Interrupt is priority 1
000= Interrupt is priority 0 (lowest interrupt priority)
bit 3
Unimplemented: Read as ‘0’
bit 2-0
INT3IP<2:0>: External Interrupt 3 Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
.
.
.
001= Interrupt is priority 1
000= Interrupt is priority 0 (lowest interrupt priority)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared
x = bit is unknown
2002 Microchip Technology Inc.
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DS70032B-page 111
dsPIC30F
REGISTER 8-19: IPC10: INTERRUPT PRIORITY CONTROL REGISTER10
Upper Half:
U-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
—
FLTAIP2
FLTAIP1
FLTAIP0
—
LVDIP2
LVDIP1
LVDIP0
bit 15
bit 8
Lower Half:
U-0
R/W-0
R/W-0
DCIIP1
R/W-0
DCIIP0
U-0
R/W-0
QEIIP2
R/W-0
QEIIP1
R/W-0
—
DCIIP2
—
QEIIP0
bit 7
bit 0
bit 15
Unimplemented: Read as ‘0’
bit 14-12 FLTAIP<2:0>: Fault A Input Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
.
.
.
001= Interrupt is priority 1
000= Interrupt is priority 0 (lowest interrupt priority)
bit 11
Unimplemented: Read as ‘0’
bit 10-8 LVDIP<2:0>: Programmable Low Voltage Detect Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
.
.
.
001= Interrupt is priority 1
000= Interrupt is priority 0 (lowest interrupt priority)
bit 7
Unimplemented: Read as ‘0’
bit 6-4
DCIIP<2:0>: Data Converter Interface Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
.
.
.
001= Interrupt is priority 1
000= Interrupt is priority 0 (lowest interrupt priority)
bit 3
Unimplemented: Read as ‘0’
bit 2-0
QEIIP<2:0>: Quadrature Encoder Interface Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
.
.
.
001= Interrupt is priority 1
000= Interrupt is priority 0 (lowest interrupt priority)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
DS70032B-page 112
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dsPIC30F
REGISTER 8-20: IPC11: INTERRUPT PRIORITY CONTROL REGISTER11
Upper Half:
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
Lower Half:
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
FLTBIP2 FLTBIP1 FLTBIP0
bit 7
bit 0
bit 15-3 Unimplemented: Read as ‘0’
bit 2-0 FLTBIP<2:0>: Fault B Input Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
.
.
.
001= Interrupt is priority 1
000= Interrupt is priority 0 (lowest interrupt priority)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
2002 Microchip Technology Inc.
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DS70032B-page 113
dsPIC30F
NOTES:
DS70032B-page 114
AdvanceInformation
2002 Microchip Technology Inc.
dsPIC30F
latch. Writes to the latch, write the latch (LATx). Reads
from the port (PORTx), read the port pins, and writes
to the port pins, write the latch (LATx).
9.0
I/O PORTS
All of the device pins (except VDD, VSS, MCLR, and
OSC1/CLKIN) are shared between the peripherals
and the parallel I/O ports.
Any bit and its associated data and control registers
that is not valid for a particular device will be disabled.
That means the corresponding LATx and TRISx regis-
ters, and the port pin, will read as zeros.
All I/O input ports feature Schmitt Trigger inputs for
improved noise immunity.
When a pin is shared with another peripheral or func-
tion that is defined as an input only, it is nevertheless
regarded as a dedicated port because there is no
other competing source of outputs. An example is the
INT4 pin.
9.1
Parallel I/O (PIO) Ports
When a peripheral is enabled, the use of any associ-
ated pin as a general purpose output pin is disabled.
The I/O pin may be read, but the output driver for the
parallel port bit will be disabled. If a peripheral is
enabled, but the peripheral is not actively driving a pin,
that pin may be driven by a port.
The format of the registers for PORTA is shown in
Table 9-1.
The TRISA (Data Direction Control) register controls
the direction of the RA<7:0> pins, as well as the INTx
pins and the VREF pins. TRISA is a read/write register.
The LATA register supplies data to the outputs, and is
readable/writable. Reading the PORTA register yields
the state of the input pins, while writing the PORTA
register yields the contents of the LATA register.
All port pins have three registers directly associated
with the operation of the port pin. The data direction
register (TRISx) determines whether the pin is an input
or an output. If the Data Direction bit is a ‘1’, then the
pin is an input. All port pins are defined as inputs after
a RESET. Reads from the latch (LATx), read the
FIGURE 9-1:
BLOCK DIAGRAM OF A DEDICATED PORT STRUCTURE
Dedicated Port Module
Read TRIS
I/O Cell
TRIS Latch
D
Q
Data Bus
WR TRIS
CK
Data Latch
I/O Pad
D
Q
WR LAT +
WR Port
CK
Read LAT
Read Port
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 115
dsPIC30F
DS70032B-page 116
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2002 Microchip Technology Inc.
dsPIC30F
A parallel I/O (PIO) port that shares a pin with another
peripheral is always subservient to the other periph-
eral. The peripheral’s output buffer data and control
signals are provided to a pair of multiplexers. The mul-
tiplexers select whether the peripheral or the associ-
ated port has ownership of the output data and control
signals of the I/O pad cell. Figure 9-2 shows how ports
are shared with other peripherals, and the associated
I/O cell (pad) to which they are connected. Table 9-2
through Table 9-7 show the formats of the registers for
the shared ports, PORTB through PORTG.
Note: The actual bits in use vary between
devices.
FIGURE 9-2:
BLOCK DIAGRAM OF A SHARED PORT STRUCTURE
Output Multiplexers
Peripheral Module
Peripheral Input Data
Peripheral Module Enable
I/O Cell
Peripheral Output Enable
Peripheral Output Data
1
Output Enable
0
1
PIO Module
Output Data
0
Read TRIS
I/O Pad
Data Bus
WR TRIS
D
Q
CK
TRIS Latch
D
Q
WR LAT +
WR Port
CK
Data Latch
Read LAT
Input Data
Read Port
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 117
dsPIC30F
DS70032B-page 118
AdvanceInformation
2002 Microchip Technology Inc.
dsPIC30F
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 119
dsPIC30F
9.2
Input Change Notification Module
The Input Change Notification module provides the
dsPIC30F devices the ability to generate interrupt
requests to the processor in response to a change of
state on selected input pins. This module is capable of
detecting input change of states even in SLEEP mode,
when the clocks are disabled. There are up to 24
external signals (CN0 through CN23) that may be
selected (enabled) for generating an interrupt request
on a change of state.
TABLE 9-8:
INPUT CHANGE NOTIFICATION REGISTER MAP (BITS 15-8)
SFR
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
RESET State
Name
CNEN1
CNEN2
CNPU1
CNPU2
00C0
00C2
00C4
00C6
CN15IE
CN14IE
CN13IE
CN12IE
CN11IE
CN10IE
CN9IE
CN8IE
—
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
—
—
—
—
—
—
—
CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE
CN8PUE
—
—
—
—
—
—
—
—
TABLE 9-9:
INPUT CHANGE NOTIFICATION REGISTER MAP (BITS 7-0)
SFR
Addr.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESET State
Name
CNEN1
CNEN2
CNPU1
CNPU2
00C0
00C2
00C4
00C6
CN7IE
CN6IE
CN5IE
CN4IE
CN3IE
CN2IE
CN1IE
CN0IE
CN16IE
CN0PUE
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
CN23IE
CN22IE
CN21IE
CN20IE
CN19IE
CN18IE
CN17IE
CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE
CN23PUE CN22PUE CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE
DS70032B-page 120
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2002 Microchip Technology Inc.
dsPIC30F
REGISTER 9-1: TRISA: PORTA DATA DIRECTION REGISTER
Upper Half:
R/W-1
TRISA15
bit 15
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
U-0
TRISA14
TRISA13
TRISA12
TRISA11 TRISA10 TRISA9
—
bit 8
Lower Half:
R/W-1
R/W-1
R/W-1
TRISA5
R/W-1
R/W-1
R/W-1
R/W-1
TRISA1
R/W-1
TRISA7
TRISA6
TRISA4
TRISA3
TRISA2
TRISA0
bit 7
bit 0
bit 15-9 TRISA<15:9>: PORTA Data Direction Control bits
1= I/O configured as an input
0= I/O configured as an output
bit 8
Unimplemented: Read as ‘0’
bit 7-0
TRISA<7:0>: PORTA Data Direction Control bits
1= I/O configured as an input
0= I/O configured as an output
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
REGISTER 9-2: PORTA: READ PIN/WRITE PORTA LATCH REGISTER
Upper Half:
R/W-x
RA15
R/W-x
RA14
R/W-x
RA13
R/W-x
RA12
R/W-x
RA11
R/W-x
RA10
R/W-x
RA9
U-0
—
bit 15
bit 8
Lower Half:
R/W-x
RA7
R/W-x
RA6
R/W-x
RA5
R/W-x
RA4
R/W-x
RA3
R/W-x
RA2
R/W-x
RA1
R/W-x
RA0
bit 7
bit 0
bit 15-9 RA<15:9>: PORTA PIO Read Pin/Write Latch Data bits
bit 8
Unimplemented: Read as ‘0’
bit 7-0
RA<7:0>: PORTA PIO Read Pin/Write Latch Data bits
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 121
dsPIC30F
REGISTER 9-3: LATA: READ/WRITE PORTA LATCH REGISTER
Upper Half:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LATA9
U-0
LATA15
LATA14
LATA13
LATA12
LATA11
LATA10
—
bit 15
bit 8
Lower Half:
R/W-0
LATA7
R/W-0
LATA6
R/W-0
LATA5
R/W-0
LATA4
R/W-0
LATA3
R/W-0
LATA2
R/W-0
LATA1
R/W-0
LATA0
bit 7
bit 0
bit 15-9 LATA<15:9>: PORTA Read/Write Latch Data bits
bit 8
Unimplemented: Read as ‘0’
bit 7-0
LATA<7:0>: PORTA Read/Write Latch Data bits
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
REGISTER 9-4: TRISB: PORTB PIO DATA DIRECTION REGISTER
Upper Half:
R/W-1
TRISB15
bit 15
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
TRISB14
TRISB13
TRISB12
TRISB11 TRISB10 TRISB9
TRISB8
bit 8
Lower Half:
R/W-1
R/W-1
R/W-1
TRISB5
R/W-1
R/W-1
R/W-1
R/W-1
TRISB1
R/W-1
TRISB7
TRISB6
TRISB4
TRISB3
TRISB2
TRISB0
bit 7
bit 0
bit 15-0 TRISB<15:0>: PORTB PIO Data Direction Control bits
1= I/O configured as an input
0= I/O configured as an output
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
DS70032B-page 122
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dsPIC30F
REGISTER 9-5: PORTB: READ PORTB PIO PIN/WRITE PORTB PIO LATCH REGISTER
Upper Half:
R/W-x
R/W-x
RB14
R/W-x
RB13
R/W-x
RB12
R/W-x
RB11
R/W-x
RB10
R/W-x
RB9
R/W-x
RB8
RB15
bit 15
bit 8
Lower Half:
R/W-x
RB7
R/W-x
RB6
R/W-x
RB5
R/W-x
RB4
R/W-x
RB3
R/W-x
RB2
R/W-x
RB1
R/W-x
RB0
bit 7
bit 0
bit 15-0 RB<15:0>: PORTB PIO Read Pin/Write Latch Data bits
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
REGISTER 9-6: LATB: READ/WRITE PORTB PIO LATCH REGISTER
Upper Half:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LATB9
R/W-0
LATB8
LATB15
LATB14
LATB13
LATB12
LATB11
LATB10
bit 15
bit 8
Lower Half:
R/W-0
LATB7
R/W-0
LATB6
R/W-0
LATB5
R/W-0
LATB4
R/W-0
LATB3
R/W-0
LATB2
R/W-0
LATB1
R/W-0
LATB0
bit 7
bit 0
bit 15-0 LATB<15:0>: PORTB PIO Read/Write Latch Data bits
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 123
dsPIC30F
REGISTER 9-7: TRISC: PORTC PIO DATA DIRECTION REGISTER
Upper Half:
R/W-1
TRISC15
bit 15
R/W-1
R/W-1
U-0
U-0
U-0
U-0
U-0
TRISC14
TRISC13
—
—
—
—
—
bit 8
Lower Half:
U-0
U-0
U-0
R/W-1
TRISC4
R/W-1
TRISC3
R/W-1
R/W-1
R/W-1
TRISC2 TRISC1
TRISC0
—
—
—
bit 7
bit 0
bit 15-13 TRISC<15:13>: PORTC PIO Data Direction Control bits
1= I/O configured as an input
0= I/O configured as an output
bit 12-5 Unimplemented: Read as ‘0’
bit 4-0
TRISC<4:0>: PORTC PIO Data Direction Control bits
1= I/O configured as an input
0= I/O configured as an output
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
REGISTER 9-8: PORTC: READ PORTC PIO PIN/WRITE PORTC PIO LATCH REGISTER
Upper Half:
R/W-x
RC15
R/W-x
RC14
R/W-x
RC13
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
bit 15
bit 8
Lower Half:
U-0
U-0
U-0
R/W-x
RC4
R/W-x
RC3
R/W-x
RC2
R/W-x
RC1
R/W-x
RC0
—
—
—
bit 7
bit 0
bit 15-13 RC<15:13>: PORTC PIO Read Pin/Write Latch Data bits
bit 12-5 Unimplemented: Read as ‘0’
bit 4-0
RC<4:0>: PORTC PIO Read Pin/Write Latch Data bits
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
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REGISTER 9-9: LATC: READ/WRITE PORTC PIO LATCH REGISTER
Upper Half:
R/W-0
LATC15
bit 15
R/W-0
R/W-0
U-0
U-0
U-0
U-0
U-0
LATC14
LATC13
—
—
—
—
—
bit 8
Lower Half:
U-0
U-0
U-0
R/W-0
LATC4
R/W-0
LATC3
R/W-0
LATC2
R/W-0
LATC1
R/W-0
LATC0
—
—
—
bit 7
bit 0
bit 15-13 LATC<15:13>: PORTC PIO Read/Write Latch Data bits
bit 12-5 Unimplemented: Read as ‘0’
bit 4-0
LATC<4:0> : PORTC PIO Read/Write Latch Data bits
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
REGISTER 9-10: TRISD: PORTD PIO DATA DIRECTION REGISTER
Upper Half:
R/W-1
TRISD15
bit 15
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
TRISD14
TRISD13
TRISD12
TRISD11 TRISD10 TRISD9
TRISD8
bit 8
Lower Half:
R/W-1
R/W-1
R/W-1
TRISD5
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
TRISD7
TRISD6
TRISD4
TRISD3
TRISD2 TRISD1
TRISD0
bit 7
bit 0
bit 15-0 TRISD<15:0>: PORTD PIO Data Direction Control bits
1= I/O configured as an input
0= I/O configured as an output
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
2002 Microchip Technology Inc.
Advance Information
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REGISTER 9-11: PORTD: READ PORTD PIO PIN/WRITE PORTD PIO LATCH REGISTER
Upper Half:
R/W-x
RD15
R/W-x
RD14
R/W-x
RD13
R/W-x
RD12
R/W-x
RD11
R/W-x
RD10
R/W-x
RD9
R/W-x
RD8
bit 15
bit 8
Lower Half:
R/W-x
RD7
R/W-x
RD6
R/W-x
RD5
R/W-x
RD4
R/W-x
RD3
R/W-x
RD2
R/W-x
RD1
R/W-x
RD0
bit 7
bit 0
bit 15-0 RD<15:0>: PORTD PIO Read Pin/Write Latch Data bits
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
REGISTER 9-12: LATD: READ/WRITE PORTD PIO LATCH REGISTER
Upper Half:
R/W-0
LATD15
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LATD9
R/W-0
LATD8
LATD14
LATD13
LATD12
LATD11
LATD10
bit 8
Lower Half:
R/W-0
LATD7
R/W-0
LATD6
R/W-0
LATD5
R/W-0
LATD4
R/W-0
LATD3
R/W-0
LATD2
R/W-0
LATD1
R/W-0
LATD0
bit 7
bit 0
bit 15-0 LATD<15:0>: PORTD PIO Read/Write Latch Data bits
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
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REGISTER 9-13: TRISE: PORTE PIO DATA DIRECTION REGISTER
Upper Half:
U-0
U-0
U-0
U-0
U-0
U-0
R/W-1
R/W-1
TRISE8
bit 8
TRISE9
—
—
—
—
—
—
bit 15
Lower Half:
R/W-1
R/W-1
R/W-1
TRISE5
R/W-1
TRISE4
R/W-1
TRISE3
R/W-1
R/W-1
TRISE1
R/W-1
TRISE7
TRISE6
TRISE2
TRISE0
bit 7
bit 0
bit 15-10 Unimplemented: Read as ‘0’
bit 9-0
TRISE<9:0>: PORTE PIO Data Direction Control bits
1= I/O configured as an input
0= I/O configured as an output
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
REGISTER 9-14: PORTE: READ PORTE PIO PIN/WRITE PORTE PIO LATCH REGISTER
Upper Half:
U-0
U-0
U-0
U-0
U-0
U-0
R/W-x
RE9
R/W-x
RE8
—
—
—
—
—
—
bit 15
bit 8
Lower Half:
R/W-x
RE7
R/W-x
RE6
R/W-x
RE5
R/W-x
RE4
R/W-x
RE3
R/W-x
RE2
R/W-x
RE1
R/W-x
RE0
bit 7
bit 0
bit 15-10 Unimplemented: Read as ‘0’
bit 9-0
RE<9:0>: PORTE PIO Read Pin/Write Latch Data bits
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 127
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REGISTER 9-15: LATE: READ/WRITE PORTE PIO LATCH REGISTER
Upper Half:
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
LATE9
R/W-0
LATE8
—
—
—
—
—
—
bit 15
bit 8
Lower Half:
R/W-0
LATE7
R/W-0
LATE6
R/W-0
LATE5
R/W-0
LATE4
R/W-0
LATE3
R/W-0
LATE2
R/W-0
LATE1
R/W-0
LATE0
bit 7
bit 0
bit 15-10 Unimplemented: Read as ‘0’
bit 9-0
LATE<9:0>: PORTE PIO Read/Write Latch Data bits
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
REGISTER 9-16: TRISF: PORTF PIO DATA DIRECTION REGISTER
Upper Half:
U-0
U-0
R/W-1
R/W-1
U-0
U-0
U-0
R/W-1
TRISF13
TRISF12
TRISF8
—
—
—
—
—
bit 15
bit 8
Lower Half:
R/W-1
R/W-1
R/W-1
TRISF5
R/W-1
TRISF4
R/W-1
TRISF3
R/W-1
R/W-1
TRISF1
R/W-1
TRISF7
TRISF6
TRISF2
TRISF0
bit 7
bit 0
bit 15-14 Unimplemented: Read as ‘0’
bit 13-12 TRISF<13:12>: PORTF PIO Data Direction Control bits
1= I/O configured as an input
0= I/O configured as an output
bit 11-9 Unimplemented: Read as ‘0’
bit 8-0
TRISF<8:0>: PORTF PIO Data Direction Control bits
1= I/O configured as an input
0= I/O configured as an output
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
DS70032B-page 128
AdvanceInformation
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REGISTER 9-17: PORTF: READ PORTF PIO PIN/WRITE PORTF PIO LATCH REGISTER
Upper Half:
U-0
U-0
R/W-x
RF13
R/W-x
RF12
U-0
U-0
U-0
R/W-1
RF8
—
—
—
—
—
bit 15
bit 8
Lower Half:
R/W-x
RF7
R/W-x
RF6
R/W-x
RF5
R/W-x
RF4
R/W-x
RF3
R/W-x
RF2
R/W-x
RF1
R/W-x
RF0
bit 7
bit 0
bit 15-14 Unimplemented: Read as ‘0’
bit 13-12 RF<13:12>: PORTF PIO Read Pin/Write Latch Data bits
bit 11-9 Unimplemented: Read as ‘0’
bit 8-0
RF<8:0>: PORTF PIO Read Pin/Write Latch Data bits
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
REGISTER 9-18: LATF: READ/WRITE PORTF PIO LATCH REGISTER
Upper Half:
U-0
U-0
R/W-0
R/W-0
U-0
U-0
U-0
R/W-0
LATF8
LATF13
LATF12
—
—
—
—
—
bit 15
bit 8
Lower Half:
R/W-0
LATF7
R/W-0
LATF6
R/W-0
LATF5
R/W-0
LATF4
R/W-0
LATF3
R/W-0
LATF2
R/W-0
LATF1
R/W-0
LATF0
bit 7
bit 0
bit 15-14 Unimplemented: Read as ‘0’
bit 13-12 LATF<13:12>: PORTF PIO Read/Write Latch Data bits
bit 11-9 Unimplemented: Read as ‘0’
bit 8-0
LATF<8:0>: PORTF PIO Read/Write Latch Data bits
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
2002 Microchip Technology Inc.
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REGISTER 9-19: TRISG: PORTG PIO DATA DIRECTION REGISTER
Upper Half:
R/W-1
TRISG15
bit 15
R/W-1
R/W-1
R/W-1
U-0
U-0
R/W-1
R/W-1
TRISG14
TRISG13
TRISG12
TRISG9
TRISG8
—
—
bit 8
Lower Half:
R/W-1
R/W-1
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
TRISG7
TRISG6
TRISG3
TRISG2 TRISG1
TRISG0
—
—
bit 7
bit 0
bit 15-12 TRISG<15:12>: PORTG PIO Data Direction Control bits
1= I/O configured as an input
0= I/O configured as an output
bit 11-10 Unimplemented: Read as ‘0’
bit 9-6
TRISG<9:6>: PORTG PIO Data Direction Control bits
1= I/O configured as an input
0= I/O configured as an output
bit 5-4
bit 3-0
Unimplemented: Read as ‘0’
TRISG<3:0>: PORTG PIO Data Direction Control bits
1= I/O configured as an input
0= I/O configured as an output
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
REGISTER 9-20: PORTG: READ PORTG PIO PIN/WRITE PORTG PIO LATCH REGISTER
Upper Half:
R/W-x
RG15
R/W-x
RG14
R/W-x
RG13
R/W-x
RG12
U-0
U-0
R/W-x
RG9
R/W-x
RG8
—
—
bit 15
bit 8
Lower Half:
R/W-x
RG7
R/W-x
RG6
U-0
U-0
R/W-x
RG3
R/W-x
RG2
R/W-x
RG1
R/W-x
RG0
—
—
bit 7
bit 0
bit 15-12 RG<15:12>: PORTG PIO Read Pin/Write Latch Data bits
bit 11-10 Unimplemented: Read as ‘0’
bit 9-6
bit 5-4
bit 3-0
RG<9:6>: PORTG PIO Read Pin/Write Latch Data bits
Unimplemented: Read as ‘0’
RG<3:0>: PORTG PIO Read Pin/Write Latch Data bits
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
DS70032B-page 130
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REGISTER 9-21: LATG: READ/WRITE PORTG PIO LATCH REGISTER
Upper Half:
R/W-0
LATG15
bit 15
R/W-0
R/W-0
R/W-0
U-0
U-0
R/W-0
LATG9
R/W-0
LATG8
bit 8
LATG14
LATG13
LATG12
—
—
Lower Half:
R/W-0
LATG7
R/W-0
U-0
U-0
R/W-0
LATG3
R/W-0
LATG2
R/W-0
LATG1
R/W-0
LATG6
LATG0
—
—
bit 7
bit 0
bit 15-12 LATG<15:12>: PORTG PIO Read/Write Latch Data bits
bit 11-10 Unimplemented: Read as ‘0’
bit 9-6
bit 5-4
bit 3-0
LATG<9:6>: PORTG PIO Read/Write Latch Data bits
Unimplemented: Read as ‘0’
LATG<3:0>: PORTG PIO Read/Write Latch Data bits
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
REGISTER 9-22: CNEN1: INPUT CHANGE NOTIFICATION INTERRUPT ENABLE REGISTER1
Upper Half:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CN9IE
R/W-0
CN8IE
CN15IE
CN14IE
CN13IE
CN12IE
CN11IE
CN10IE
bit 15
bit 8
Lower Half:
R/W-0
R/W-0
CN6IE
R/W-0
CN5IE
R/W-0
CN4IE
R/W-0
CN3IE
R/W-0
CN2IE
R/W-0
CN1IE
R/W-0
CN0IE
bit 0
CN7IE
bit 7
bit 15-0 CN<15:0>IE: Input Change Notification Interrupt Enable bit
1= Interrupt on input change is enabled
0= Interrupt on input change not enabled
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
2002 Microchip Technology Inc.
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REGISTER 9-23: CNEN2: INPUT CHANGE NOTIFICATION INTERRUPT ENABLE REGISTER2
Upper Half:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
—
—
—
bit 15
bit 8
Lower Half:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CN23IE
bit 7
CN22IE
CN21IE
CN20IE
CN19IE
CN18IE
CN17IE
CN16IE
bit 0
bit 15-8 Unimplemented: Read as ‘0’
bit 7-0
CN<23:16>IE: Input Change Notification Interrupt Enable bits
1= Interrupt on input change is enabled
0= Interrupt on input change not enabled
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
REGISTER 9-24: CNPU1: INPUT CHANGE NOTIFICATION PULL-UP ENABLE REGISTER1
Upper Half:
R/W-0
CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE
bit 15 bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Lower Half:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CN0PUE
bit 0
CN7PUE
bit 7
CN6PUE
CN5PUE
CN4PUE
CN3PUE CN2PUE
CN1PUE
bit 15-0 CN<15:0>PUE : Input Change Notification Pull-up Enable bit
1= Pull-up on input change is enabled
0= Pull-up on input change not enabled
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
DS70032B-page 132
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REGISTER 9-25: CNPU2: INPUT CHANGE NOTIFICATION PULL-UP ENABLE REGISTER2
Upper Half:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
—
—
—
bit 15
bit 8
Lower Half:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CN23PUE CN22PUE CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE
bit 7
bit 0
bit 15-8 Unimplemented: Read as ‘0’
bit 7-0 CN<23:16>PUE: Input Change Notification Pull-up Enable bit
1= Pull-up on input change is enabled
0= Pull-up on input change not enabled
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 133
dsPIC30F
NOTES:
DS70032B-page 134
AdvanceInformation
2002 Microchip Technology Inc.
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16-bit Timer Mode: In the 16-bit Timer mode, the timer
increments on every instruction cycle up to a match
value, preloaded into the period register PR1, then
resets to 0 and continues to count.
10.0 TIMER1 MODULE
This section describes the 16-bit General Purpose
(GP) Timer1 module and associated operational
modes. Figure 10-1 depicts the simplified block dia-
gram of the 16-bit Timer1 Module.
When the CPU goes into the IDLE mode, the timer will
stop incrementing, unless the TSIDL (T1CON<13>)
bit = 0. If TSIDL = 1, the timer module logic will resume
the incrementing sequence upon termination of the
CPU IDLE mode.
The following sections provide a detailed description,
including setup and control registers along with associ-
ated block diagrams for the operational modes of the
timers.
16-bit Synchronous Counter Mode: In the 16-bit
Synchronous Counter mode, the timer increments on
the rising edge of the applied external clock signal,
which is synchronized with the internal phase clocks.
The timer counts up to a match value preloaded in PR1,
then resets to 0 and continues.
The Timer1 module is a 16-bit timer which can serve as
the time counter for the real-time clock, or operate as a
free running interval timer/counter. The 16-bit timer has
the following modes:
• 16-bit Timer
• 16-bit Synchronous Counter
• 16-bit Asynchronous Counter
When the CPU goes into the IDLE mode, the timer will
stop incrementing, unless the respective TSIDL bit = 0.
If TSIDL = 1, the timer module logic will resume the
incrementing sequence upon termination of the CPU
IDLE mode.
Further, the following operational characteristics are
supported:
• Timer gate operation
16-bit Asynchronous Counter Mode: In the 16-bit
Asynchronous Counter mode, the timer increments on
every rising edge of the applied external clock signal.
The timer counts up to a match value preloaded in PR1,
then resets to 0 and continues.
• Selectable prescaler settings
• Timer operation during CPU IDLE and SLEEP
modes
• Interrupt on 16-bit period register match or falling
edge of external gate signal
When the timer is configured for the Asynchronous mode
of operation and the CPU goes into the IDLE mode, the
timer will not stop incrementing, independent of the
TSIDL bit. The TSIDL bit is ignored for this Timer mode.
These operating modes are determined by setting the
appropriate bit(s) in the 16-bit SFR, T1CON. Figure 10-1
presents a block diagram of the 16-bit timer module.
FIGURE 10-1:
16-BIT TIMER1 MODULE BLOCK DIAGRAM
PR1
Comparator x 16
TMR1
TCKPS<1:0>
2
Equal
Prescaler
1, 8, 64, 256
RESET
0
1
T1IF
Event Flag
Q
Q
D
TGATE
CK
TCS
0
TGATE
TCY
SLEEP Input
TSYNC
0
LPOSC
Synchronize
Det
1
SOSC1/T1CK
TGATE
1
LPOSCEN
Enable
Oscillator(1)
1
SOSC2
TON
On/Off
0
Note 1:
When enable bit LPOSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 135
dsPIC30F
When the Gated Time Accumulation mode is enabled,
an interrupt will also be generated on the falling edge of
the gate signal (at the end of the accumulation cycle).
10.1 Timer Gate Operation
The 16-bit timer can be placed in the Gated Time Accu-
mulation mode. This mode allows the internal TCY to
increment the respective timer when the gate input sig-
nal (T1CK pin) is asserted high. Control bit TGATE
(T1CON<6>) must be set to enable this mode. The
timer must be enabled (TON = 1) and the timer clock
source set to internal (TCS = 0).
Enabling an interrupt is accomplished via the respec-
tive timer interrupt enable bit, T1IE. The timer interrupt
enable bit is located in the IEC0 control register in the
Interrupt Controller.
10.5 Real-Time Clock
When the CPU goes into the IDLE mode, the timer will
stop incrementing, unless TSIDL = 0. If TSIDL = 1, the
timer will resume the incrementing sequence upon ter-
mination of the CPU IDLE mode.
The Real-Time Clock (RTC) provides time-of-day and
event time stamping capabilities. Key operational fea-
tures of the RTC are:
• RTC Oscillator operation
• 8-bit prescaler
10.2 Timer Prescaler
The input clock (FOSC/4 or external clock) to the 16-bit
Timer, has a prescale option of 1:1, 1:8, 1:64, and
1:256 selected by control bits TCKPS<1:0>
(T1CON<5:4>). The prescaler counter is cleared when
any of the following occurs:
• Low power
• Real-Time Clock Interrupts
• These operating modes are determined by setting
the appropriate bit(s) in the T1CON Control
register.
• a write to the TMR1 register
10.5.1
RTC OSCILLATOR OPERATION
• a write to the T1CON register
• device RESET such as POR and BOR
When the TON = 1, TCS = 1 and TGATE = 0, the timer
increments on the rising edge of the 32 kHz LP oscilla-
tor output signal, up to the value specified in the period
register, and is then reset to 0.
However, if the timer is disabled (TON = 0), then the
timer prescaler cannot be reset since the prescaler
clock is halted.
The TSYNC bit must be asserted to a logic 0 (Asyn-
chronous mode) for correct operation.
TMR1 is not cleared when T1CON is written. It is
cleared by writing to the TMR1 register.
Enabling LPOSCEN (OSCCON<1>) will disable the
normal Timer and Counter modes and enable a timer
carry-out wake-up event.
10.3 Timer Operation During SLEEP
Mode
When the CPU enters SLEEP or IDLE mode, the timer
will continue to increment, provided the external clock
is active and the control bits have not been changed.
The TSIDL bit is excluded from the control of the timer
module for this mode.
During CPU SLEEP mode, the timer will operate if:
• The timer module is enabled (TON = 1) and
• The timer clock source is selected as external
(TCS = 0) and
• The TSYNC bit is asserted to a logic 0, which
defines the external clock source as asynchro-
nous.
10.5.2
REAL-TIME CLOCK INTERRUPTS
When an interrupt event occurs, the respective inter-
rupt flag, T1IF, is asserted and an interrupt will be gen-
erated, if enabled. The T1IF bit must be cleared in
software. The respective Timer interrupt flag, T1IF, is
located in the IFS0 status register in the Interrupt
Controller.
When all three conditions are true, the timer will con-
tinue to count up to the period register and be reset to
0x0000.
When a match between the timer and the period regis-
ter occurs, an interrupt can be generated, if the respec-
tive timer interrupt enable bit is asserted.
Enabling an interrupt is accomplished via the respec-
tive timer interrupt enable bit, T1IE. The Timer interrupt
enable bit is located in the IEC0 control register in the
Interrupt Controller.
10.4 Timer Interrupt
The 16-bit timer has the ability to generate an interrupt
on period match. When the timer count matches the
period register, the T1IF bit is asserted and an interrupt
will be generated if enabled. The T1IF bit must be
cleared in software. The timer interrupt flag T1IF is
located in the IFS0 control register in the Interrupt
Controller.
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REGISTER 10-1: T1CON: TIMER1 CONTROL REGISTER
Upper Half:
R/W-0
TON
R/W-0
R/W-0
TSIDL
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
bit 15
bit 8
Lower Half:
U-0
R/W-0
R/W-0
TCKPS1
R/W-0
TCKPS0
U-0
R/W-0
TSYNC
R/W-0
TCS
U-0
—
TGATE
—
—
bit 7
bit 0
bit 15
TON: Timer1 On bit
1= Starts 16-bit Timer1
0= Stops 16-bit Timer1
bit 14
bit 13
Unimplemented: Read as '0’
TSIDL: Timer1 Stop in IDLE Control bit
1= Timer will halt in CPU IDLE mode
0= Timer will continue to operate in CPU IDLE mode
bit 12-7 Unimplemented: Read as ’0’
bit 6
TGATE: Timer1 Gated Time Accumulation Enable bit
1= Timer1 gated time accumulation enabled
0= Timer1 gated time accumulation disabled
(TCS must be set to logic 0 when TGATE = 1)
bit 5-4
TCKPS<1:0> Timer1 Input Clock Prescale Select bits
11 = 1:256 prescale value
10 = 1:64 prescale value
01 = 1:8 prescale value
00 = 1:1 prescale value
bit 3
bit 2
Unimplemented: Read as '0
TSYNC: Timer1 External Clock Input Synchronization Select bit
When TCS = 1:
1= Synchronize external clock input
0= Do not synchronize external clock input
When TCS = 0:
This bit is ignored. Timer1 uses the internal clock when TCS = 0.
bit 1
bit 0
TCS: Timer1 Clock Source Select bit
1= External clock from pin TCKI (on the rising edge)
0= Internal clock (FOSC/4)
Unimplemented: Read as '0’
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
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32-bit Timer Mode: In the 32-bit Timer mode, the timer
increments on every instruction cycle up to a match
value, preloaded into the combined 32-bit period regis-
ter PR3/PR2, then resets to 0 and continues to count.
11.0 TIMER2/3 MODULE
This section describes the 32-bit General Purpose
(GP) Timer modules (Timer2/3) and associated opera-
tional modes. Figure 11-1 depicts the simplified block
diagram of the 32-bit GP Timer module.
For synchronous 32-bit reads of the Timer2/Timer3
pair, reading the LSB (TMR2 register) will cause the
MSB to be read and latched into a 16-bit holding regis-
ter, termed TMR3HLD.
The Timer2/3 module is a 32-bit timer (which can be
configured as two 16-bit timers) with selectable operat-
ing modes. These timers are utilized by other periph-
eral modules such as:
For synchronous 32-bit writes, the holding register
(TMR3HLD) must first be written to. When followed by
a write to the TMR2 register, the contents of TMR3HLD
will be transferred and latched into the MSB of the 32-
bit timer (TMR3).
• Input Capture
• Output Compare/Simple PWM
The following sections provide a detailed description,
including setup and control registers, along with asso-
ciated block diagrams for the operational modes of the
timers.
32-bit Synchronous Counter Mode: In the 32-bit
Synchronous Counter mode, the timer increments on
the rising edge of the applied external clock signal,
which is synchronized with the internal phase clocks.
The timer counts up to a match value preloaded in the
combined 32-bit period register PR3/PR2, then resets
to 0 and continues.
The 32-bit timer has the following modes:
• Two independent 16-bit timers (Timer2 and
Timer3) with all 16-bit Operating modes
• Single 32-bit Timer operation
When the timer is configured for the Synchronous
Counter mode of operation and the CPU goes into the
IDLE mode, the timer will stop incrementing, unless the
TSIDL (T2CON<13>) bit = 0. If TSIDL = 1, the timer
module logic will resume the incrementing sequence
upon termination of the CPU IDLE mode.
• Single 32-bit Synchronous Counter
Further, the following operational characteristics are
supported:
• ADC Event Trigger
• Timer gate operation
• Selectable prescaler settings
• Timer operation during IDLE and SLEEP modes
• Interrupt on a 32-bit period register match
These operating modes are determined by setting the
appropriate bit(s) in the 16-bit T2CON and T3CON
SFRs. Figure 11-1 presents a simple block diagram of
the 32-bit timer.
For 32-bit timer/counter operation, Timer2 is the LS
Word (LSW) and Timer3 is the MS Word (MSW) of the
32-bit timer.
Note: For 32-bit timer operation, T3CON control
bits are ignored. Only T2CON control bits
are used for setup and control. Timer 2
clock and gate inputs are utilized for the
32-bit timer module, but an interrupt is gen-
erated with the Timer3 interrupt flag (T3IF).
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FIGURE 11-1:
32-BIT TIMER MODULE BLOCK DIAGRAM(1)
Data Bus<15:0>
TMR3HLD
16
16
Write TMR2
Read TMR2
TCKPS<1:0>
2
16
RESET
Prescaler
1, 8, 64, 256
TMR3
TMR2
LSW
MSW
ADC Event
Trigger
Comparator x 32
Equal
PR3
PR2
0
1
T3IF
Event Flag
Q
Q
D
TGATE
CK
TCS
0
TGATE
TCY
SLEEP Input
TSYNC
Synchronize
Det
1
0
1
T2CK
TGATE
1
TON
On/Off
0
Note 1: Timer configuration bit T32, T2CON(<3>), must be set to 1 for a 32-bit timer/counter operation.
11.1 Timer Gate Operation
11.2 ADC Event Trigger
The 32-bit timer can be placed in the Gated Time Accu-
mulation mode. This mode allows the internal TCY to
increment the respective timer when the gate input sig-
nal (T2CK pin) is asserted high. Control bit TGATE
(T2CON<6>) must be set to enable this mode. When in
this mode, Timer2 is the originating clock source. The
TGATE setting is ignored for Timer3. The timer must be
enabled (TON = 1) and the timer clock source set to
internal (TCS = 0).
When a match occurs between the 32-bit timer (TMR3/
TMR2) and the 32-bit combined period register (PR3/
PR2), a special ADC trigger event signal is generated
by Timer3.
The falling edge of the external signal terminates the
count operation, but does not reset the timer. The user
must reset the timer in order to start counting from zero.
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11.3 Timer Prescaler
11.5 Timer Interrupt
The input clock (FOSC/4 or external clock) to the timer
has a prescale option of 1:1, 1:8, 1:64, and 1:256
selected by control bits TCKPS<1:0> (T2CON<5:4>
and T3CON<5:4>). For the 32-bit timer operation, the
originating clock source is Timer2. The prescaler oper-
ation for Timer3 is not applicable in this mode. The
prescaler counter is cleared when any of the following
occurs:
The 32-bit timer module can generate an interrupt on
period match, or on the falling edge of the external gate
signal. When the 32-bit timer count matches the
respective 32-bit period register, or the falling edge of
the external “gate” signal is detected, the T3IF bit is
asserted and an interrupt will be generated if enabled.
In this mode, the T3IF interrupt flag is used as the
source of the interrupt. The T3IF bit must be cleared in
software. The timer interrupt flag, T3IF, is located in the
IFS0 status register in the Interrupt Controller.
• a write to the TMR2/TMR3 register
• a write to the T2CON/T3CON register
• device RESET such as POR and BOR
Enabling an interrupt is accomplished via the respec-
tive timer interrupt enable bit, T3IE. The timer interrupt
enable bit is located in the IEC0 control register.
However, if the timer is disabled (TON = 0), then the
Timer 2 prescaler cannot be reset, since the prescaler
clock is halted.
TMR2/TMR3 is not cleared when T2CON/T3CON is
written.
11.4 Timer Operation During SLEEP
Mode
During CPU SLEEP mode, the timer will operate if:
• The timer module is enabled (TON = 1) and
• The timer clock source is selected as external
(TCS = 0) and
• The TSYNC bit is asserted to a logic 0, which
defines the external clock source as asynchro-
nous.
When all three conditions are true, the timer will con-
tinue to count up to the period register and be reset to
0x00000000.
When a match between the timer and the period regis-
ter occurs, an interrupt can be generated, if the
respective timer interrupt enable bit is asserted.
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REGISTER 11-1: T2CON: TIMER2 CONTROL REGISTER
Upper Half:
R/W-0
TON
R/W-0
R/W-0
TSIDL
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
bit 15
bit 8
Lower Half:
U-0
R/W-0
R/W-0
TCKPS1
R/W-0
TCKPS0
R/W-0
T32
R/W-0
R/W-0
TCS
U-0
—
TGATE
TSYNC
—
bit 7
bit 0
bit 15
TON: Timer2 On bit
When T32 = 1 (in 32-bit Timer mode):
1= Starts 32-bit TMR3:TMR2
0= Stops 32-bit TMR3:TMR2
When T32 = 0 (in 16-bit Timer mode):
1= Starts 16-bit Timer2
0= Stops 16-bit Timer2
bit 14
bit 13
Unimplemented: Read as '0’
TSIDL: Timer2 Stop in IDLE Control bit
1= Timer will halt in CPU IDLE mode
0= Timer will continue to operate in CPU IDLE mode
(Bit enables 16- and 32-bit timer operation for CPU SLEEP IDLE state)
bit 12-7 Unimplemented: Read as ’0’
bit 6
TGATE: Timer2 Gated Time Accumulation Enable bit
1= Timer2 gated time accumulation enabled
0= Timer2 gated time accumulation disabled
(TCS must be set to logic 0 when TGATE = 1)
bit 5-4
TCKPS<1:0> Timer2 Input Clock Prescale Select bits
11 = 1:256 prescale value
10 = 1:64 prescale value
01 = 1:8 prescale value
00 = 1:1 prescale value
bit 3
bit 2
T32: 32-bit Timer Mode Select bits
1= Timer2 and Timer3 form a 32-bit timer
0= Timer2 and Timer3 form 16-bit timers
Note: For 32-bit timer operation, T3CON control bits do not affect 32-bit timer operation.
TSYNC: Timer2 External Clock Input Synchronization Select bit
When TCS = 1:
1= Synchronize external clock input
0= Do not synchronize external clock input
When TCS = 0:
This bit is ignored. Timer2 uses the internal clock when TCS = 0.
bit 1
bit 0
TCS: Timer2 Clock Source Select bit
1= External clock from pin T2CK (on the rising edge)
0= Internal clock (FOSC/4)
Unimplemented: Read as '0’
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
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REGISTER 11-2: T3CON: TIMER3 CONTROL REGISTER
Upper Half:
R/W-0
TON
R/W-0
R/W-0
TSIDL
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
bit 15
bit 8
Lower Half:
U-0
R/W-0
R/W-0
TCKPS1
R/W-0
TCKPS0
U-0
R/W-0
TSYNC
R/W-0
TCS
U-0
—
TGATE
—
—
bit 7
bit 0
bit 15
TON: Timer3 On bit
1= Starts 16-bit Timer3
0= Stops 16-bit Timer3
Note: For 32-bit timer operation, T3CON control bits do not affect 32-bit timer operation.
bit 14
bit 13
Unimplemented: Read as '0’
TSIDL: Timer3 Stop in IDLE Control bit
1= Timer will halt in CPU IDLE mode
0= Timer will continue to operate in CPU IDLE mode
bit 12-7 Unimplemented: Read as ’0’
bit 6
TGATE: Timer3 Gated Time Accumulation Enable bit
1= Timer3 gated time accumulation enabled
0= Timer3 gated time accumulation disabled
(TCS must be set to logic 0 when TGATE = 1)
bit 5-4
TCKPS<1:0> Timer3 Input Clock Prescale Select bits
11 = 1:256 prescale value
10 = 1:64 prescale value
01 = 1:8 prescale value
00 = 1:1 prescale value
bit 3
bit 2
Unimplemented: Read as '0’
TSYNC: Timer3 External Clock Input Synchronization Select bit
When TCS = 1:
1= Synchronize external clock input
0= Do not synchronize external clock input
When TCS = 0:
This bit is ignored. Timer3 uses the internal clock when TCS = 0.
bit 1
bit 0
TCS: Timer3 Clock Source Select bit
1= External clock from pin T3CKI (on the rising edge)
0= Internal clock (FOSC/4)
Unimplemented: Read as '0’
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
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32-bit Timer Mode: In the 32-bit Timer mode, the timer
increments on every instruction cycle up to a match
value, preloaded into the combined 32-bit period regis-
ter PR5/PR4, then resets to 0 and continues to count.
12.0 TIMER4/5 MODULE
This section describes the second 32-bit General Pur-
pose (GP) Timer module (Timer4/5) and associated
operational modes. Figure 12-1 depicts the simplified
block diagram of the 32-bit GP Timer Module. The
Timer 4/5 module is identical in operation to the Timer
2/3 module.
For synchronous 32-bit reads of the Timer4/Timer5
pair, reading the LSB (TMR4 register) will cause the
MSB to be read and latched into a 16-bit holding regis-
ter, termed TMR5HLD.
The Timer4/5 module is a 32-bit timer (which can be
configured as two 16-bit timers) with selectable operat-
ing modes. These timers are utilized by other periph-
eral modules such as:
For synchronous 32-bit writes, the holding register
(TMR5HLD) must first be written to. When followed by
a write to the TMR4 register, the contents of TMR5HLD
will be transferred and latched into the MSB of the 32-
bit timer (TMR5).
• Input Capture
• Output Compare/Simple PWM
32-bit Synchronous Counter Mode: In the 32-bit
Synchronous Counter mode, the timer increments on
the rising edge of the applied external clock signal,
which is synchronized with the internal phase clocks.
The timer counts up to a match value, preloaded in the
combined 32-bit period register PR5/PR4, then resets
to 0 and continues.
The following sections provide a detailed description,
including setup and control registers, along with asso-
ciated block diagrams for the operational modes of the
timers.
The 32-bit timer has the following modes:
• Two independent 16-bit timers (Timer4 and
When the timer is configured for the Synchronous
Counter mode of operation and the CPU goes into the
IDLE mode, the timer will stop incrementing, unless the
TSIDL (T4CON<13>) bit = 0. If TSIDL = 1, the timer
module logic will resume the incrementing sequence
upon termination of the CPU IDLE mode.
Timer5) with all 16-bit Operating modes.
• Single 32-bit Timer operation
• Single 32-bit Synchronous Counter
Further, the following operational characteristics are
supported:
• Timer Gate operation
• Selectable prescaler settings
• Timer operation during IDLE and SLEEP modes
• Interrupt on a 32-bit period register match
These operating modes are determined by setting the
appropriate bit(s) in the 16-bit T4CON and T5CON
SFRs. Figure 12-1 presents a simple block diagram of
the 32-bit timer.
For 32-bit timer/counter operation, Timer4 is the LS
Word (LSW) and Timer5 is the MS Word (MSW) of the
32-bit timer.
Note: For 32-bit timer operation, T5CON control
bits are ignored. Only T4CON control bits
are used for setup and control. Timer4
clock and gate inputs are utilized for the
32-bit timer module, but an interrupt is gen-
erated with the Timer5 interrupt flag (T5IF).
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FIGURE 12-1:
32-BIT TIMER MODULE BLOCK DIAGRAM(1)
Data Bus<15:0>
TMR5HLD
16
16
Write TMR4
Read TMR4
TCKPS<1:0>
2
16
RESET
Prescaler
1, 8, 64, 256
TMR5
TMR4
LSW
MSW
Comparator x 32
Equal
PR5
PR4
0
1
T5IF
Event Flag
Q
D
TGATE
Q
CK
TCS
0
TGATE
TCY
SLEEP Input
TSYNC
0
Synchronize
Det
1
T4CK
TGATE
1
1
TON
On/Off
0
Note 1: Timer configuration bit T45, T4CON(<3>), must be set to 1 for a 32-bit timer/counter operation.
The falling edge of the external signal terminates the
count operation but does not reset the timer. The user
must reset the timer in order to start counting from zero.
12.1 Timer Gate Operation
The 32-bit timer can be placed in the Gated Time Accu-
mulation mode. This mode allows the internal TCY to
increment the respective timer when the gate input sig-
nal (T4CK pin) is asserted high. Control bit TGATE
(T4CON<6>) must be set to enable this mode. When in
this mode, Timer4 is the originating clock source. The
TGATE setting is ignored for Timer5. The timer must be
enabled (TON = 1) and the timer clock source set to
internal (TCS = 0).
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12.2 Timer Prescaler
12.4 Timer Interrupt
The input clock (FOSC/4 or external clock) to the timer
has a prescale option of 1:1, 1:8, 1:64, and 1:256,
selected by control bits TCKPS<1:0> (T4CON<5:4>
and T5CON<5:4>). For the 32-bit timer operation, the
originating clock source is Timer4. The prescaler oper-
ation for Timer5 is not applicable in this mode. The
prescaler counter is cleared when any of the following
occurs:
The 32-bit timer module can generate an interrupt on
period match or on the falling edge of the external gate
signal. When the 32-bit timer count matches the
respective 32-bit period register, or the falling edge of
the external “gate” signal is detected, the T5IF bit is
asserted and an interrupt will be generated, if enabled.
In this mode, the T5IF interrupt flag is used as the
source of the interrupt. The T5IF bit must be cleared in
software. The timer interrupt flag, T5IF, is located in the
corresponding IFS1 Status register in the Interrupt
Controller.
• a write to the TMR4/TMR5 register
• a write to the T4CON/T5CON register
• device RESET such as POR and BOR
Enabling an interrupt is accomplished via the respec-
tive timer interrupt enable bit, T5IE. The timer interrupt
enable bit, is located in the corresponding IEC1 Control
register.
However, if the timer is disabled (TON = 0), then the
Timer 4 prescaler cannot be reset, since the prescaler
clock is halted.
TMR4/TMR5 is not cleared when T4CON/T5CON is
written.
12.3 Timer Operation During SLEEP
Mode
During CPU SLEEP mode, the timer will operate if:
• The timer module is enabled (TON = 1) and
• The timer clock source is selected as external
(TCS = 0) and
• The TSYNC bit is asserted to a logic 0, which
defines the external clock source as asynchro-
nous.
When all three conditions are true, the timer will con-
tinue to count up to the period register and be reset to
0x00000000.
When a match between the timer and the period regis-
ter occurs, an interrupt can be generated if the respec-
tive timer interrupt enable bit is asserted.
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REGISTER 12-1: T4CON: TIMER4 CONTROL REGISTER
Upper Half:
R/W-0
TON
R/W-0
R/W-0
TSIDL
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
bit 15
bit 8
Lower Half:
U-0
R/W-0
R/W-0
TCKPS1
R/W-0
TCKPS0
R/W-0
T45
R/W-0
R/W-0
TCS
U-0
—
TGATE
TSYNC
—
bit 7
bit 0
bit 15
TON: Timer4 On bit
When T45 = 1 (in 32-bit Timer mode):
1= Starts 32-bit TMR5:TMR4
0= Stops 32-bit TMR5:TMR4
When T45 = 0 (in 16-bit Timer mode):
1= Starts 16-bit Timer4
0= Stops 16-bit Timer4
bit 14
bit 13
Unimplemented: Read as '0’
TSIDL: Timer4 Stop in IDLE Control bit
1= Timer will halt in CPU IDLE mode
0= Timer will continue to operate in CPU IDLE mode
(Bit enables 16- and 32-bit timer operation for CPU SLEEP IDLE state)
bit 12-7 Unimplemented: Read as ’0’
bit 6
TGATE: Timer4 Gated Time Accumulation Enable bit
1= Timer4 gated time accumulation enabled
0= Timer4 gated time accumulation disabled
(TCS must be set to logic 0 when TGATE = 1)
bit 5-4
TCKPS<1:0> Timer4 Input Clock Prescale Select bits
11 = 1:256 prescale value
10 = 1:64 prescale value
01 = 1:8 prescale value
00 = 1:1 prescale value
bit 3
bit 2
T45: 32-bit Timer Mode Select bits
1= Timer4 and Timer5 form a 32-bit timer
0= Timer4 and Timer5 form 16-bit timers
Note: For 32-bit Timer operation, T5CON control bits do not affect 32-bit timer operation.
TSYNC: Timer4 External Clock Input Synchronization Select bit
When TCS = 1:
1= Synchronize external clock input
0= Do not synchronize external clock input
When TCS = 0:
This bit is ignored. Timer4 uses the internal clock when TCS = 0.
bit 1
bit 0
TCS: Timer4 Clock Source Select bit
1= External clock from pin T4CK (on the rising edge)
0= Internal clock (FOSC/4)
Unimplemented: Read as '0’
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
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REGISTER 12-2: T5CON: TIMER5 CONTROL REGISTER
Upper Half:
R/W-0
TON
R/W-0
R/W-0
TSIDL
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
bit 15
bit 8
Lower Half:
U-0
R/W-0
R/W-0
TCKPS1
R/W-0
TCKPS0
U-0
R/W-0
TSYNC
R/W-0
TCS
U-0
—
TGATE
—
—
bit 7
bit 0
bit 15
TON: Timer5 On bit
1= Starts 16-bit Timer5
0= Stops 16-bit Timer5
Note: For 32-bit Timer operation, T5CON control bits do not affect 32-bit timer operation.
bit 14
bit 13
Unimplemented: Read as '0’
TSIDL: Timer5 Stop in IDLE Control bit
1= Timer will halt in CPU IDLE mode
0= Timer will continue to operate in CPU IDLE mode
bit 12-7 Unimplemented: Read as ’0’
bit 6
TGATE: Timer5 Gated Time Accumulation Enable bit
1= Timer5 gated time accumulation enabled
0= Timer5 gated time accumulation disabled
(TCS must be set to logic 0 when TGATE = 1)
bit 5-4
TCKPS<1:0> Timer5 Input Clock Prescale Select bits
11 = 1:256 prescale value
10 = 1:64 prescale value
01 = 1:8 prescale value
00 = 1:1 prescale value
bit 3
bit 2
Unimplemented: Read as '0’
TSYNC: Timer5 External Clock Input Synchronization Select bit
When TCS = 1:
1= Synchronize external clock input
0= Do not synchronize external clock input
When TCS = 0:
This bit is ignored. Timer5 uses the internal clock when TCS = 0.
bit 1
bit 0
TCS: Timer5 Clock Source Select bit
1= External clock from pin T5CK (on the rising edge)
0= Internal clock (FOSC/4)
Unimplemented: Read as '0’
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
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The key operational features of the Input Capture mod-
ule are:
13.0 INPUT CAPTURE MODULE
This section describes the Input Capture module and
associated operational modes. The features provided
by this module are useful in applications requiring Fre-
quency (Period) and Pulse measurement. Figure 13-1
depicts a block diagram of the Input Capture Module.
Input capture is useful for such modes as:
• Simple Capture Event mode
• Timer2 and Timer3 mode selection
• Interrupt on input capture event
These operating modes are determined by setting the
appropriate bits in the ICxCON register (where x =
1,2,...,N). The dsPIC devices contain up to 8 capture
channels, i.e., the maximum value of N is 8.
• Frequency/Period/Pulse Measurements
• Additional sources of external interrupts
FIGURE 13-1:
INPUT CAPTURE MODULE BLOCK DIAGRAM
TMR3<15:0>
TMR2<15:0>
From GP Timer Module
Set Interrupt Flag
ICxIF
ICTMR
1
0
ICxBUF x 16
Prescaler - 1, 4, 16
and Mode Select
ICx
pin
3
ICM<2:0>
Mode Select
Note 1: Where ‘x’ is shown, reference is made to the registers or bits associated with the respective input capture
channels 1 through N.
13.1.2
CAPTURE BUFFER OPERATION
13.1 Simple Capture Event Mode
Each capture channel has an associated FIFO buffer,
which is four 16-bit words deep. There are two status
flags, which provide status on the FIFO buffer:
The simple capture events in the dsPIC30F product
family are:
• Capture every falling edge
• ICBFNE - Input Capture Buffer Not Empty
• ICOV - Input Capture Overflow
• Capture every rising edge
• Capture every 4th rising edge
• Capture every 16th rising edge
• Capture every rising and falling edge
The ICBFNE will be set on the first input capture event
and remain set until all capture events have been read
from the FIFO. As each word is read from the FIFO, the
remaining words are advanced by one position within
the buffer.
These simple Input Capture modes are configured by
setting the appropriate bits ICM<2:0> (ICxCON<2:0>).
In the event that the FIFO is full with four capture
events and a fifth capture event occurs prior to a read
of the FIFO, an overflow condition will occur and the
ICOV bit will be set to a logic 1. The fifth capture event
is lost and is not stored in the FIFO. No additional
events will be captured till all four events have been
read from the buffer.
13.1.1
CAPTURE PRESCALER
There are four input capture prescaler settings, speci-
fied by bits ICM<2:0> (ICxCON<2:0>). Whenever the
capture channel is turned off, the prescaler counter will
be cleared. In addition, any RESET will clear the
prescaler counter.
If a FIFO read is performed after the last read and no
new capture event has been received, the read will
yield indeterminate results.
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13.1.3
TIMER2 AND TIMER3 SELECTION
MODE
13.2.1
INPUT CAPTURE IN CPU SLEEP
MODE
The input capture module consists of up to four input
capture channels. Each channel can select between
one of two timers for the time-base, Timer2 or Timer3.
CPU SLEEP mode allows input capture module oper-
ation with reduced functionality. In the CPU SLEEP
mode, the ICI<1:0> bits are not applicable, and the
input capture module can only function as an external
interrupt source.
Selection of the timer resource is accomplished
through SFR bit ICTMR (ICxCON<7>). Timer3 is the
default timer resource available for the input capture
module.
The capture module must be configured for interrupt
only on rising edge (ICM<2:0> = 111), in order for the
input capture module to be used while the device is in
SLEEP mode. The prescale settings of 4:1 or 16:1 are
not applicable in this mode.
13.1.4
HALL SENSOR MODE
When the input capture module is set for capture on
every edge, rising and falling, ICM<2:0> = 001, the fol-
lowing operations are performed by the input capture
logic:
13.2.2
INPUT CAPTURE IN CPU IDLE
MODE
CPU IDLE mode allows input capture module opera-
tion with full functionality. In the CPU IDLE mode, the
interrupt mode selected by the ICI<1:0> bits are appli-
cable, as well as the 4:1 and 16:1 capture prescale
settings, which are defined by control bits ICM<2:0>.
This mode requires the selected timer to be enabled.
Moreover, the ICSIDL bit must be asserted to a logic 0.
• The input capture interrupt flag is set on every
edge, rising and falling.
• The interrupt on Capture mode setting bits,
ICI<1:0>, is ignored, since every capture gener-
ates an interrupt.
• A capture overflow condition is not generated in
this mode.
If the input capture module is defined as
ICM<2:0> = 111in CPU IDLE mode, the input capture
pin will serve only as an external interrupt pin.
13.2 Input Capture Operation During
SLEEP and IDLE Modes
13.3 Input Capture Interrupts
An input capture event will generate a device wake-up
or interrupt, if enabled, if the device is in CPU IDLE or
SLEEP mode.
The input capture channels have the ability to generate
an interrupt, based upon the selected number of cap-
ture events.
Independent of the timer being enabled, the input
capture module will wake-up from the CPU SLEEP
or IDLE mode when a capture event occurs, if
ICM<2:0> = 111 and the interrupt enable bit is
asserted. The same wake-up can generate an inter-
rupt, if the conditions for processing the interrupt have
been satisfied. The wake-up feature is useful as a
method of adding extra external pin interrupts.
The selection number is set by control bits ICI<1:0>
(ICxCON<6:5>).
Each channel provides an interrupt flag (ICxIF) bit. The
respective capture channel interrupt flag is located in
the corresponding IFSx Status register.
Enabling an interrupt is accomplished via the respec-
tive capture channel interrupt enable (ICxIE) bit. The
capture interrupt enable bit is located in the corre-
sponding IEC Control register.
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REGISTER 13-1: ICXCON: INPUT CAPTURE X CONTROL REGISTER
Upper Half:
U-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
U-0
—
—
ICSIDL
—
—
—
—
—
bit 15
bit 8
Lower Half:
R/W-0
R/W-0
ICI1
R/W-0
ICI0
R-0
ICOV
R-0
ICBNE
R/W-0
ICM2
R/W-0
ICM1
R/W-0
ICM0
ICTMR
bit 7
bit 0
bit 15-14 Unimplemented: Read as '0’
bit 13
ICSIDL: Input Capture Stop in IDLE Control bit
1= Input Capture x will halt in CPU IDLE mode
0= Input Capture x will continue to operate in CPU IDLE mode
bit 12-8 Unimplemented: Read as '0’
bit 7
ICTMR: Input Capture Timer Select bits
1= Timer2 is the clock source for Capture x
0= Timer3 is the clock source for Capture x
bit 6-5
ICI<1:0> Select Number of Captures per Interrupt bits
11= Interrupt on every fourth Capture event
10= Interrupt on every third Capture event
01= Interrupt on every second Capture event
00= Interrupt on every Capture event
bit 4
ICOV: Input Capture Overflow Status Flag (Read Only) bit
1= Input Capture x overflow occurred
0= No Input Capture x overflow occurred
bit 3
ICBNE: Input Capture Buffer Empty Status (Read Only) bit
1= Input Capture x buffer is not empty, at least one more capture value can be read
0= Input Capture x buffer is empty
bit 2-0
ICM<2:0> Input Capture Mode Select bits
111= Input Capture x functions as interrupt pin only in CPU SLEEP and IDLE mode
(Rising edge detect only, all other control bits are not applicable)
110= Unused (module disabled)
101= Capture mode, every 16th rising edge
100= Capture mode, every 4th rising edge
011= Capture mode, every rising edge
010= Capture mode, every falling edge
001= Capture mode, every edge (rising and falling)
(ICI<1:0> ignored for this mode)
000= Input Capture x off
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
Note: There is one ICxCON register for each input capture channel (x = 1, 2, ...., N).
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These operating modes are determined by setting the
appropriate bits in the 16-bit OCxCON SFR (where x =
1,2,3,...,N). The dsPIC devices contain up to 8 com-
pare channels, i.e., the maximum value of N is 8.
14.0 OUTPUT COMPARE MODULE
This section describes the Output Compare module
and associated operational modes. The features pro-
vided by this module are useful in applications requiring
operational modes such as:
OCxRS and OCxR in the figure represent the dual
compare registers. In the Dual Compare mode, the
OCxR register is used for the first compare and OCxRS
is used for the second compare. When configured for
the PWM mode of operation, the OCxR is the Main
latch (read only) and OCxRS is the Secondary latch.
• Generation of Variable Width Output Pulses
• Power Factor Correction
Figure 14-1 depicts a block diagram of the Output
Compare module.
The key operational features of the Output Compare
module include:
• Timer2 and Timer3 Selection mode
• Simple Output Compare Match mode
• Dual Output Compare Match mode
• Simple PWM mode
• Output Compare during SLEEP and IDLE modes
• Interrupt on Output Compare/PWM Event
FIGURE 14-1:
OUTPUT COMPARE MODE BLOCK DIAGRAM
Set Flag bit
OCxIF
OCxRS
OCxR
Output
Logic
S
R
Q
OCx
Output Enable
3
OCM<2:0>
Mode Select
OCFA
Comparator
(for x = 1, 2, 3 or 4)
OCTSEL
1
1
or OCFB
0
0
(for x = 5, 6, 7 or 8)
From GP Timer Module
T3P3_MATCH
TMR3<15:0> T2P2_MATCH
TMR2<15:0
Note 1: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels 1
through N.
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14.3.2
CONTINUOUS PULSE MODE
14.1 Timer2 and Timer3 Selection Mode
For the user to configure the module for the generation
of a continuous stream of output pulses, the following
steps are required:
Each output compare channel can select between one
of two 16-bit timers, Timer2 or Timer3.
The selection of the timers is controlled by the OCTSEL
bit (OCxCON<3>). Timer2 is the default timer resource
for the Output Compare module.
• Determine instruction cycle time TCY.
• Calculate desired pulse value base upon TCY.
• Calculate timer to start pulse width from timer start
value of 0x0000.
14.2 Simple Output Compare Match
Mode
• Write pulse width start and stop times into OCxR
and OCxRS (x denotes channel 1, 2, ...,N) com-
pare registers, respectively.
When control bits OCM<2:0> (OCxCON<2:0>) = 001,
010 or 011, the selected output compare channel is
configured for one of three simple output compare
match modes:
• Set timer period register to value equal to, or
greater than, value in OCxRS compare register.
• Set OCM<2:0> = 101.
• Compare forces I/O pin low
• Compare forces I/O pin high
• Compare toggles I/O pin
• Enable timer, TON (TxCON<15>) = 1.
Figure 14-3 depicts the Dual Compare Continuous
Output Pulse mode.
The OCxR register is used in these modes. The OCxR
register is loaded with a value and is compared to the
selected incrementing timer count. When a compare
occurs, one of these Compare Match modes occurs. If
the counter resets to zero before reaching the value in
OCxR, the state of the OCx pin remains unchanged.
14.3 Dual Output Compare Match Mode
When control bits OCM<2:0> (OCxCON<2:0>) = 100
or 101, the selected output compare channel is config-
ured for one of two Dual Output Compare modes,
which are:
• Single Output Pulse mode
• Continuous Output Pulse mode
14.3.1
SINGLE PULSE MODE
For the user to configure the module for the generation
of a single output pulse, the following steps are
required (assuming timer is off):
• Determine instruction cycle time TCY.
• Calculate desired pulse width value base upon
TCY.
• Calculate time to start pulse from timer start value
of 0x0000.
• Write pulse width start and stop times into OCxR
and OCxRS compare registers (x denotes
channel 1, 2, ...,N).
• Set timer period register to value equal to, or
greater than, value in OCxRS compare register.
• Set OCM<2:0> = 100.
• Enable timer, TON (TxCON<15>) = 1.
To initiate another single pulse, issue another write to
set OCM<2:0> = 100.
Figure 14-2 depicts the Dual Compare Single Output
Pulse mode.
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FIGURE 14-2:
DUAL COMPARE, SINGLE OUTPUT PULSE MODE
Timer = Period Register, (PRy = 0xFFFF)
Timer = Period Register, (PRy = 0x8000)
New Compare Value
Timer
OCxRS
OCxR
0
OCxRS
(0x7000)
(0x2000)
(0x4000)
OCxR
Time
OCx pin
OCM<2:0> = 100
TON = 1
OCM<2:0> = 100
TON = 1
OCx
Interrupt
1 TCY Delay
between Event
and Interrupt
OCxIF = 1
OCxIF = 1
Note 1: Where ‘x’ is shown, reference is made to the control bits and registers associated with output compare channels
1, 2, 3 ... to N.
2: Where ‘y’ is shown, reference is made to Timer2 or Timer3.
3: IF bit is generated by interrupt controller module.
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FIGURE 14-3:
DUAL COMPARE, CONTINUOUS OUTPUT PULSE MODE
Timer = Period Register, (PRy = 0xFFFF)
Timer = Period Register, (PRy = 0x8000)
New Compare Value
Timer
OCxRS
OCxR
0
OCxRS
OCxR
Time
(0x7000)
(0x2000)
(0x4000)
OCx pin
OCM<2:0> = 101
TON = 1
OCx
Interrupt
OCxIF = 1
OCxIF = 1 OCxIF = 1 OCxIF = 1
OCxIF = 1 OCxIF = 1
Note 1: Where ‘x’ is shown, reference is made to the control bits and registers associated with output compare channels 1, 2,
3 ... to N.
2: Where ‘y’ is shown, reference is made to Timer2 or Timer3.
3: IF bit is asserted by interrupt controller module.
14.4.1
INPUT PIN FAULT PROTECTION
FOR PWM
14.4 Simple PWM Mode
When control bits OCM<2:0> (OCxCON<2:0>) = 110
or 111, the selected output compare channel is config-
ured for the PWM mode of operation.
When control bits OCM<2:0> (OCxCON<2:0>) = 111,
the selected output compare channel is again config-
ured for the PWM mode of operation, with the addi-
tional feature of input fault protection. While in this
mode, if a logic 0 is detected on the OCFA/B pin, the
respective PWM output pin is placed in the high imped-
ance input state. The OCFLT bit (OCxCON<4>) indi-
cates whether a fault condition has occurred. This state
will be maintained until:
The user must perform the following steps in order to
configure the output compare module for PWM opera-
tion:
1. Set the PWM period by writing to the appropriate
period register.
2. Set the PWM duty cycle by writing to the OCxRS
register.
• The external fault condition has been removed
and
3. Configure the output compare module for PWM
operation.
• The PWM mode is re-enabled by writing to the
appropriate control bits.
4. Set the TMRx prescale value and enable the
Timer, TON (TxCON<15>) = 1.
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When the selected TMRx is equal to its respective
period register, PRx, the following four events occur on
the next increment cycle:
14.4.2
PWM PERIOD
The PWM period is specified by writing to the PRx reg-
ister. The PWM period can be calculated using the fol-
lowing formula:
• TMRx is cleared.
• The OCx pin is set (exception: if PWM duty
cycle = 0%, the OCx pin will not be set).
PWM period = [(PRx) + 1] • 4 • TOSC •
(TMRx prescale value)
• The PWM duty cycle is latched from OCxRS into
OCxR.
PWM frequency is defined as 1 / [PWM period].
• The corresponding timer interrupt flag is set.
See Figure 14-4 for key PWM period comparisons.
Timer3 is referred to in the figure for clarity.
FIGURE 14-4:
PWM OUTPUT TIMING
Period
Duty Cycle
TMR3 = PR3
TMR3 = PR3
T3IF = 1
T3IF = 1
(Interrupt Flag)
(Interrupt Flag)
OCxR = OCxRS
OCxR = OCxRS
TMR3 = Duty Cycle (OCxR)
TMR3 = Duty Cycle (OCxR)
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14.5 Output Compare Operation During
CPU SLEEP Mode
14.7 Output Compare Interrupts
The output compare channels have the ability to gener-
ate an interrupt on a compare match, for whichever
Match mode has been selected.
When the CPU enters the SLEEP mode, limited func-
tionality is provided for the output compare module.
During SLEEP, all internal clocks are stopped. There-
fore, the output compare module can operate if the
timer clock is configured for the External Asynchro-
nous Clock mode. In addition, the module will gener-
ate an interrupt signal when a match occurs between
the timer (TMRx) and period register (PRx).
For all modes except the PWM mode, when a compare
event occurs, the respective interrupt flag (OCxIF) bit is
asserted and an interrupt will be generated, if enabled.
The OCxIF bit is located in the corresponding IFS
Status register, and must be cleared in software. The
interrupt is enabled via the respective compare inter-
rupt enable (OCxIE) bit, located in the corresponding
IEC Control register.
If the output compare timer source is configured for
internal instruction cycle, or External Synchronized
Clock mode when the CPU enters the SLEEP state,
the output compare channel will drive the pin to the
active state that was observed prior to entering the
CPU SLEEP state.
For the PWM mode, when an event occurs, the respec-
tive timer interrupt flag (T2IF or T3IF) is asserted and
an interrupt will be generated if enabled. The IF bit is
located in the IFS0 Status register, and must be cleared
in software. The interrupt is enabled via the respective
timer interrupt enable bit (T2IE or T3IE), located in the
IEC0 Control register. The output compare interrupt
flag is never set during the PWM mode of operation.
For example, if the pin was high when the CPU
entered the SLEEP state, the pin will remain high.
Likewise, if the pin was low when the CPU entered the
SLEEP state, the pin will remain low. In either case,
the output compare module will resume operation
when the device wakes up.
14.6 Output Compare Operation During
CPU IDLE Mode
When the CPU enters the IDLE mode, the output com-
pare module operates with full functionality.
The output compare channel will operate during the
CPU IDLE mode if the OCSIDL bit (OCxCON<13>) is
at logic 0 and the selected time-base (Timer2 or
Timer3) is enabled and the TSIDL bit of the selected
timer is set to logic 0.
The selected time-base for the output compare can be
configured for:
• Internal Instruction Cycle
• External Synchronous
• External Asynchronous
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REGISTER 14-1: OCXCON: OUTPUT COMPARE CONTROL X REGISTER
Upper Half:
U-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
U-0
—
—
OCSIDL
—
—
—
—
—
bit 15
bit 8
Lower Half:
U-0
U-0
U-0
R-0
OCFLT
R/W-0
OCTSEL
R/W-0
OCM2
R/W-0
OCM1
R/W-0
OCM0
—
—
—
bit 7
bit 0
bit 15-14 Unimplemented: Read as '0’
bit 13
OCSIDL: Output Compare Stop in IDLE Control bit
1= Output Compare x will halt in CPU IDLE mode
0= Output Compare x will continue to operate in CPU IDLE mode
bit 12-5 Unimplemented: Read as '0’
bit 4
OCFLT: PWM Fault Condition Status bit
1= PWM fault condition has occurred (cleared in HW only)
0= No PWM fault condition has occurred
(Status bit is unimplemented in non-PWM mode)
bit 3
OCTSEL: Output Compare Timer Select bits
1= Timer3 is the clock source for Compare x
0= Timer2 is the clock source for Compare x
bit 2-0
OCM<2:0>: Output Compare Mode Select bits
111= PWM mode on OCx, fault pin enabled, (T2IF/T3IF bit is set for PWM, OCxIF is set for fault)
110= PWM mode on OCx, fault pin disabled, (T2IF/T3IF bit is set for PWM)
101= Initialize OCx pin Low, generate continuous output pulses on OCx pin, (OCxIF bit is set)
100= Initialize OCx pin Low, generate single output pulse on OCx pin, (OCxIF bit is set)
011= Initialize OCx pin Low, Compare x toggles OCx pin, (OCxIF bit is set)
010= Initialize OCx pin High, Compare x forces OCx pin Low, (OCxIF bit is set)
001= Initialize OCx pin Low, Compare x forces OCx pin High, (OCxIF bit is set)
000= Output Compare x off
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
Note: There is one OCxCON register for each output compare channel (x = 1, 2, ...., N).
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• Three input channels for two phase signals and
index pulse
15.0 QUADRATURE ENCODER
INTERFACE (QEI) MODULE
• 16-bit up/down position counter
This section describes the Quadrature Encoder Inter-
face (QEI) module and associated operational modes.
The QEI module provides the interface to incremental
encoders for obtaining motor positioning data. Incre-
mental encoders are very useful in motor control appli-
cations.
• Count direction status
• Position Measurement (x2 and x4) mode
• Programmable digital noise filters on inputs
• Alternate 16-bit Timer/Counter mode
• Quadrature Encoder Interface interrupts
The Quadrature Encoder Interface (QEI) is a key fea-
ture requirement for several motor control applications,
such as Switched Reluctance (SR) and AC Induction
Motor (ACIM). The operational features of the QEI are,
but not limited to:
These operating modes are determined by setting the
appropriate bits QEIM<2:0> (QEICON<10:8>).
Figure 15-1 depicts the Quadrature Encoder Interface
block diagram.
FIGURE 15-1:
QUADRATURE ENCODER INTERFACE BLOCK DIAGRAM
TQCKPS<1:0>
2
SLEEP Input
TQCS
TQSYNC
1
TCY
0
1
Synchronize
Det
Prescaler
1, 8, 64, 256
1
0
0
QEIM<2:0>
QEIIF
Event
Flag
D
Q
Q
TQGATE
CK
16-bit Up/Down Counter
(POSCNT)
2
Programmable
Digital Filter
QEA
RESET
Equal
Quadrature
Encoder
Interface Logic
UPDN_CNT
Comparator
QEICON<11>
0
3
QEIM<2:0>
Mode Select
1
Max Count Register
(MAXCNT)
Programmable
Digital Filter
QEB
Programmable
Digital Filter
INDX
3
PCDOUT
Existing Pin Logic
0
UPDN
Up/Down
1
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Within the x2 Measurement mode, there are two varia-
tions of how the position counter is RESET:
15.1 Quadrature Encoder Interface
Logic
1. Position counter RESET by detection of index
A typical incremental (a.k.a. optical) encoder has three
outputs: Phase A, Phase B, and an index pulse. These
signals are useful and often required in position and
speed control of ACIM and SR motors.
pulse, QEIM<2:0> = 100.
2. Position counter RESET by match with
MAXCNT, QEIM<2:0> = 101.
When control bits QEIM<2:0> = 110 or 111, the x4
Measurement mode is selected and the QEI logic looks
at both edges of the Phase A and Phase B input sig-
nals. Every edge of both signals causes the position
counter to increment or decrement.
The two channels, Phase A (QEA) and Phase B (QEB),
have a unique relationship. If Phase A leads Phase B,
then the direction (of the motor) is deemed positive or
forward. If Phase A lags Phase B, then the direction (of
the motor) is deemed negative or reverse.
Within the x4 Measurement mode, there are two varia-
tions of how the position counter is reset:
A third channel, termed index pulse, occurs once per
revolution and is used as a reference to establish an
absolute position. The index pulse coincides with
Phase A and Phase B, both low.
1. Position counter reset by detection of index
pulse, QEIM<2:0> = 110.
2. Position counter reset by match with MAXCNT,
15.2 16-bit Up/Down Position Counter
Mode
QEIM<2:0> = 111.
The x4 Measurement mode provides for finer resolu-
tion data (more position counts) for determining motor
position.
The 16-bit Up/Down Counter counts up or down on
every count pulse, which is generated by the difference
of the Phase A and Phase B input signals. The counter
acts as an integrator, whose count value is proportional
to position. The direction of the count is determined by
the UPDN signal, which is generated by the Quadra-
ture Encoder Interface Logic.
15.5 Programmable Digital Noise
Filters
The digital noise filter section is responsible for reject-
ing noise on the incoming capture or quadrature sig-
nals. Schmitt Trigger inputs and a three-clock cycle
delay filter combine to reject low level noise and large,
short duration noise spikes that typically occur in noise
prone applications, such as a motor system.
15.3 Count Direction Status
As mentioned in the previous section, the QEI logic
generates an UPDN signal, based upon the relation-
ship between Phase A and Phase B. In addition to the
output pin, the state of this internal UPDN signal is sup-
plied to a SFR bit UPDN (QEICON<11>) as a read only
bit. To place the state of this signal on an I/O pin, the
SFR bit PCDOUT (QEICON<6>) must be 1.
The filter ensures that the filtered output signal is not
permitted to change until a stable value has been reg-
istered for three consecutive clock cycles.
To enable the filter output for channels QEA and QEB,
the QEOUT bit must be 1. To enable the filter output for
the index channel, the INDOUT bit must be 1. The filter
network for all channels is disabled on POR and BOR
RESET.
15.4 Position Measurement Mode
There are two Measurement modes which are sup-
ported and are termed x2 and x4. These modes are
selected by the EIM<2:0> mode select bits located in
SFR QEICON<10:8>.
Figure 15-2 demonstrates the effect of the digital noise
filter.
When control bits QEIM<2:0> = 100 or 101, the x2
Measurement mode is selected and the QEI logic only
looks at the Phase A input for the position counter
increment rate. Every rising and falling edge of the
Phase A signal causes the position counter to be incre-
mented or decremented. The Phase B signal is still uti-
lized for the determination of the counter direction, just
as in the x4 mode.
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FIGURE 15-2:
SIGNAL RELATIONSHIP THROUGH FILTER, 1:1 CLOCK DIVIDE
TCY
INPUT 1
INPUT 2
FILTERED OUT 1
FILTERED OUT 2
15.6 Alternate 16-bit Timer/Counter
15.7 QEI Module Operation During CPU
SLEEP Mode
When the QEI module is not configured for the QEI
mode QEIM<2:0> = 001, the module can be configured
for a simple 16-bit timer/counter. The setup and control
for the auxiliary timer is accomplished through the
QEICON SFR register. This timer functions identical to
Timer1. The QEA pin is used as the timer clock input.
15.7.1
QEI OPERATION DURING CPU
SLEEP MODE
The QEI module will be halted during the CPU SLEEP
mode.
When configured as a timer, the POSCNT register
serves as the Timer Count Register and the MAXCNT
register serves as the Period Register. When a timer/
period register match occur, the QEI interrupt flag will
be asserted.
15.7.2
TIMER OPERATION DURING CPU
SLEEP MODE
During CPU SLEEP mode, the timer will operate if:
• The timer module is enabled (TQON = 1), and
The only exception between the general purpose tim-
ers and this timer is the added feature of external
up_down input select. When the UPDN pin is asserted
high, the timer will increment up. When the UPDN pin
is asserted low, the timer will be decremented.
• The timer clock source is selected as external
(TQCS = 0), and
• The TQSYNC bit is asserted to a logic 0, which
defines the external clock source as
asynchronous.
Note: Changing the operational mode, i.e., from
QEI to Timer or vice versa, will not affect the
Timer/Position Count Register contents.
When all three conditions are true, the timer will con-
tinue to count up to the period register and be reset to
0x0000.
The UPDN control/status bit (QEICON<11>) can be
used to select the count direction state of the Timer reg-
ister. When QEICON<11> = 1, the timer will count up.
When QEICON<11> = 0, the timer will count down.
When a match between the timer and the period regis-
ter occurs, an interrupt can be generated if the respec-
tive timer interrupt enable bit is asserted.
In addition, control bit UPDN_CNT (QEICON<0>)
determines whether the timer count direction state is
based on the logic state, written into control/status bit
UPDN (QEICON<11>), or the QEB pin state. When
QEICON<0> = 1, the timer count direction is controlled
from the QEB pin. Likewise, when QEICON<0> = 0, the
timer count direction is controlled by QEICON<11>.
15.8 QEI Module Operation During CPU
IDLE Mode
Since the QEI module can function as a quadrature
encoder interface, or as a 16-bit timer, the following
section describes operation of the module in both
modes.
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15.8.1
QEI OPERATION DURING CPU IDLE
MODE
15.9 Quadrature Encoder Interface
Interrupts
When the CPU is placed in the IDLE mode, the QEI
module will operate if the QEISIDL bit (QEICON<13>)
= 0. This bit defaults to a logic 0 upon executing POR
and BOR. For halting the QEI module during the CPU
IDLE mode, QEISIDL should be set to 1.
The quadrature encoder interface has the ability to
generate an interrupt on occurrence of the following
events:
• Interrupt on 16-bit up/down position counter
rollover/underflow
• Timer period match event (overflow/underflow)
• Gate accumulation event
15.8.2
TIMER OPERATION DURING CPU
IDLE MODE
The QEI interrupt flag bit, QEIIF, is asserted upon the
16-bit up/down position counter rollover/underflow, or
timer period match (POSCNT = MAXCNT). The QEIIF
bit must be cleared in software. QEIIF is located in the
IFS2 Status register.
When the CPU is placed in the IDLE mode and the
QEI module is configured in the 16-bit Timer mode, the
16-bit timer will operate if the QEISIDL bit
(QEICON<13>) = 0. This bit defaults to a logic 0 upon
executing POR and BOR. For halting the timer module
during the CPU IDLE mode, QEISIDL should be set
to 1.
Enabling an interrupt is accomplished via the respec-
tive enable bit, QEIIE. The QEIIE bit is located in the
IEC2 Control register.
If the QEISIDL bit is cleared, the timer will function nor-
mally, as if the CPU IDLE mode had not been entered.
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REGISTER 15-1: QEICON: QEI CONTROL REGISTER
Upper Half:
U-0
R/W-0
R/W-0
R-0
R/W-0
UPDN
R/W-0
R/W-0
R/W-0
—
—
QEISIDL
INDX
QEIM2
QEIM1
QEIM0
bit 15
bit 8
Lower Half:
R/W-0
R/W-0
R/W-0
TQGATE
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SWPAB
bit 7
PCDOUT
TQCKPS1 TQCKPS0 TQSYNC TQCS UPDN_CNT
bit 0
bit 15-14 Unimplemented: Read as '0’
bit 13
bit 12
bit 11
QEISIDL: Module Stop in IDLE Control bit
1= Module will halt in CPU IDLE mode
0= Module will continue to operate CPU IDLE mode
INDX: Index Pin State Status bit (Read Only)
1= Index pin is high
0= Index pin is low
UPDN: Position Counter Direction Status bit
1= Position counter direction is positive (+)
0= Position counter direction is negative (-
(Read only bit in QEI mode. Read/Write bit in Timer Operation mode.)
bit 10-8 QEIM<2:0>: Quadrature Encoder Interface Mode Select bits
111= Quadrature Encoder Interface enabled (x4 mode) with Position Counter Reset by match (MAXCNT)
110= Quadrature Encoder Interface enabled (x4 mode) with Index Pulse Reset of position counter
101= Quadrature Encoder Interface enabled (x2 mode) with Position Counter Reset by match (MAXCNT)
100= Quadrature Encoder Interface enabled (x2 mode) with Index Pulse Reset of position counter
011= Unused (module disabled)
010= Unused (module disabled)
001= Starts 16-bit Timer
000= Quadrature Encoder Interface/Timer off
bit 7
bit 6
SWPAB: Phase A and Phase B Input Swap Select bit
1= Phase A and Phase B inputs swapped
0= Phase A and Phase B inputs not swapped
PCDOUT: Position Counter Direction State Output Enable bit
1= Position counter direction status output enable
(QEI logic controls state of I/O pin)
0= Position counter direction status output disabled
(Normal I/O pin operation.)
bit 5
TQGATE: Timer Gated Time Accumulation Enable bit
1= Timer gated time accumulation enabled
0= Timer gated time accumulation disabled
bit 4-3
TQCKPS<1:0>: Timer Input Clock Prescale Select bits
11= 1:256 prescale value
10= 1:64 prescale value
01= 1:8 prescale value
00= 1:1 prescale value
(Prescaler utilized for 16-bit Timer mode only.)
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REGISTER 15-1: QEICON: QEI CONTROL REGISTER (Continued)
bit 2
TQSYNC: Timer External Clock Input Synchronization Select bit
When TQCS = 1:
1= Synchronize external clock input
0= Do not synchronize external clock input
When TQCS = 0:
This bit is ignored. Timer uses the internal clock when TQCS = 0.
bit 1
bit 0
TQCS: Timer Clock Source Select bit
1= External clock from pin TQCK (on the rising edge)
0= Internal clock (FOSC/4)
UPDN_CNT: Position Counter Direction Selection Control bit
1= QEB pin state defines position counter direction
0= Control/Status bit, QEICON<11>, defines timer counter (POSCNT) direction
Note:When configured for QEI mode, this bit is ignored.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
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REGISTER 15-2: DFLTCON: DIGITAL FILTER CONTROL REGISTER
Upper Half:
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
Lower Half:
R/W-0
R/W-0
QECK2
R/W-0
QECK1
R/W-0
QECK0
R/W-0
R/W-0
R/W-0
R/W-0
QEOUT
bit 7
INDOUT INDCK2 INDCK1
INDCK0
bit 0
bit 15-8 Unimplemented: Read as '0’
bit 7
QEOUT: QEA/QEB Digital Filter Output Enable bit
1= Digital filter outputs enabled
0= Digital filter outputs disabled (Normal pin operation)
bit 6-4
QECK<2:0>: QEA/QEB Digital Filter Clock Divide Select bits
111 = 1:256 Clock divide
110 = 1:128 Clock divide
101 = 1:64 Clock divide
100 = 1:32 Clock divide
011 = 1:16 Clock divide
010 = 1:4 Clock divide
001 = 1:2 Clock divide
000 = 1:1 Clock divide
bit 3
INDOUT: Index Channel Digital Filter Output Enable bit
1= Digital filter output is enabled
0= Digital filter output is disabled (normal pin operation)
bit 2-0
INDCK<2:0>: Index Channel Digital Filter Clock Divide Select bits
111 = 1:256 Clock divide
110 = 1:128 Clock divide
101 = 1:64 Clock divide
100 = 1:32 Clock divide
011 = 1:16 Clock divide
010 = 1:4 Clock divide
001 = 1:2 Clock divide
000 = 1:1 Clock divide
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
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REGISTER 15-3: POSCNT: 16-BIT POSITION COUNTER REGISTER
Upper Half:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
POSCNT15 POSCNT14 POSCNT13 POSCNT12 POSCNT11 POSCNT10 POSCNT9 POSCNT8
bit 15 bit 8
Lower Half:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
POSCNT7 POSCNT6 POSCNT5 POSCNT4 POSCNT3 POSCNT2 POSCNT1 POSCNT0
bit 7 bit 0
bit 15-0 POSCNT<15:0>: 16-bit Up_Down Position Counter Register bits
(Serves as Timer/Counter register when in Timer mode)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
REGISTER 15-4: MAXCNT: MAXIMUM COUNT REGISTER
Upper Half:
R/W-1
MAXCNT15 MAXCNT14 MAXCNT13 MAXCNT12 MAXCNT11 MAXCNT10 MAXCNT9 MAXCNT8
bit 15 bit 8
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
Lower Half:
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
MAXCNT7 MAXCNT6 MAXCNT5 MAXCNT4 MAXCNT3 MAXCNT2 MAXCNT1 MAXCNT0
bit 7
bit 0
bit 15-0 MAXCNT<15:0>: 16-bit Maximum Count Register bits
(Serves as Period register when in Timer mode)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
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NOTES:
DS70032B-page 172
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A simplified block diagram of the PWM module is
shown in Figure 16-1. Figure 16-5 and Figure 16-9
show how the module hardware is partitioned for each
PWM output pair for the Complementary and Indepen-
dent Output modes, respectively.
16.0 MOTOR CONTROL PWM
MODULE
This module simplifies the task of generating multiple,
synchronized Pulse Width Modulated (PWM) outputs.
In particular, the following power and motion control
applications are supported by the PWM module:
This module contains 4 duty cycle generators, num-
bered 1 through 4. The module has 8 PWM output pins,
numbered 0 through 7. The eight I/O pins are grouped
into odd numbered/even numbered pairs. For comple-
mentary loads, the even PWM pins are always the
complement of the corresponding odd I/O pin.
• Three Phase AC Induction Motor
• Switched Reluctance (SR) Motor
• Brushless DC (BLDC) Motor
• Uninterruptible Power Supply (UPS)
The PWM module has the following features:
• 8 PWM I/O pins with 4 duty cycle generators
• Up to 16-bit resolution
• ‘On-the-Fly’ PWM frequency changes
• Edge and Center Aligned Output modes
• Single Pulse Generation mode
• Interrupt support for asymmetrical updates in
Center Aligned mode
• Output override control for Electrically Commuta-
tive Motor (ECM) operation
• ‘Special Event’ comparator for scheduling other
peripheral events
• Fault pins to optionally drive each of the PWM I/O
pins to a defined state
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FIGURE 16-1:
PWM MODULE BLOCK DIAGRAM
PWMCON1
PWMCON2
DTCON1
PWM Enable and Mode SFRs
Dead-Time Control SFRs
DTCON2
FLTACON
FLTBCON
OVDCON
Fault Pin Control SFRs
PWM Manual
Control SFR
PWM Generator #4
PDC4 Buffer
PDC4
PWM7
PWM6
Comparator
Channel 4 Dead-Time
Generator and
Override Logic
PWM Generator
#3
PWM5
PWM4
PTMR
Comparator
PTPER
Channel 3 Dead-Time
Generator and
Output
Driver
Block
Override Logic
PWM Generator
#2
PWM3
PWM2
Channel 2 Dead-Time
Generator and
Override Logic
PWM Generator
#1
PWM1
PWM0
Channel 1 Dead-Time
Generator and
Override Logic
PTPER Buffer
PTCON
FLTA
FLTB
Comparator
SEVTCMP
Special Event
Postscaler
Special Event Trigger
SEVTDIR
PTDIR
PWM Time-Base
Note: Details of PWM Generator #1, #2, and #3 not shown for clarity.
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The PWM module allows several modes of operation,
which are beneficial for specific power control applica-
tions. Each mode of operation is described subse-
quently.
The PTPER SFR sets the counting period for PTMR.
The user must write a 15-bit value to PTPER<14:0>.
When the value in PTMR<14:0> matches the value in
PTPER<14:0>, the time-base will either reset to 0, or
reverse the count direction on the next occurring clock
cycle. The action taken depends on the operating
mode of the time-base.
16.1 PWM Time-Base
The PWM time-base is provided by a 15-bit timer with
a prescaler and postscaler. The time-base is accessi-
ble via the PTMR SFR. PTMR<15:0> contains a read
only status bit, PDIR, that indicates the present count
direction of the PWM time-base. If PTDIR is cleared,
PTMR is counting upwards, whereas PTDIR set, indi-
cates that PTMR is counting downwards. The PWM
time-base is configured via the PTCON SFR. The time-
base is enabled/disabled by setting/clearing the PTEN
bit in the PTCON SFR. PTMR is not cleared when the
PTEN bit is cleared in software.
Note: If the period register is set to 0x0000, the
timer will stop counting, and the interrupt
and the special event trigger will not be
generated, even if the special event value
is also 0x0000. The module will not update
the period register, if it is already at
0x0000; therefore, the user must disable
the module in order to update the period
register.
FIGURE 16-2:
PWM TIME-BASE BLOCK DIAGRAM
PTMR Register
PTMR Clock
Timer Reset.
Up/Down
Zero Match
Comparator
Timer
Direction
Control
PTDIR
Period Match
PTMOD1
Comparator
Duty Cycle Load
PTPER
Period Load
PTPER Buffer
Update Disable (UDIS)
Zero Match
Period Match
PTMOD<1:0>
PTMR clock
PTEN
Clock
Control
Prescaler
1:1, 1:4, 1:16, 1:64
FOSC/4
Zero
Match
Postscaler
1:1 - 1:16
Interrupt
Control
PWMIF
Period
Match
PTMOD<1:0>
2
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The PWM time-base can be configured for four differ-
ent modes of operation:
The postscaler counter is cleared when any of the fol-
lowing occurs:
• Free Running mode
• a write to the PTMR register
• a write to the PTCON register
• any device RESET
• Single Shot mode
• Continuous Up/Down Count mode
• Continuous up/Down count mode with interrupts
for double updates
The PTMR register is not cleared when PTCON is written.
16.2 PWM Time-Base Interrupts
These four modes are selected by the PTMOD<1:0>
bits in the PTCON SFR. The Up/Down Counting modes
support center aligned PWM generation. The Single
Shot mode allows the PWM module to support pulse
control of certain Electronically Commutative Motors
(ECMs).
The interrupt signals generated by the PWM time-base
depend on the mode selection bits (PTMOD<1:0>) and
the postscaler bits (PTOPS<3:0>) in the PTCON SFR.
16.2.1
FREE RUNNING MODE
When the PWM time-base is in the Free Running mode
(PTMOD<1:0> = 00), an interrupt event is generated
each time a match with the PTPER register occurs and
the PTMR register is reset to zero. The postscaler
selection bits may be used in this mode of the timer to
reduce the frequency of the interrupt events.
16.1.1
FREE RUNNING MODE
In the Free Running mode, the PWM time-base counts
upwards until the value in the time-base period register
(PTPER) is matched. The PTMR register is reset on the
following input clock edge and the time-base will con-
tinue to count upwards as long as the PTEN bit remains
set.
16.2.2
SINGLE SHOT MODE
When the PWM time-base is in the Single Shot mode
(PTMOD<1:0> = 01), an interrupt event is generated
when a match with the PTPER register occurs, the
PTMR register is reset to zero on the following input
clock edge, and the PTEN bit is cleared. The postscaler
selection bits have no effect in this mode of the timer.
16.1.2
SINGLE SHOT MODE
In the Single Shot Counting mode, the PWM time-base
begins counting upwards when the PTEN bit is set.
When the value in the PTMR register matches the
PTPER register, the PTMR register will be reset on the
following input clock edge and the PTEN bit will be
cleared by the hardware to halt the time-base.
16.2.3
CONTINUOUS UP/DOWN
COUNTING MODE
16.1.3
CONTINUOUS UP/DOWN
COUNTING MODES
In the Up/Down Counting mode (PTMOD<1:0> = 10),
an interrupt event is generated each time the value of
the PTMR register becomes zero and the PWM time-
base begins to count upwards. The postscaler selec-
tion bits may be used in this mode of the timer to reduce
the frequency of the interrupt events.
In the Continuous Up/Down Counting modes, the PWM
time-base counts upwards until the value in the PTPER
register is matched. The timer will begin counting
downwards on the following input clock edge. The
PTDIR bit in the PTCON SFR is read only and indicates
the counting direction The PTDIR bit is set when the
timer counts downwards.
16.2.4
DOUBLE UPDATE MODE
In the Double Update mode (PTMOD<1:0> = 11), an
interrupt event is generated each time the PTMR regis-
ter is equal to zero, as well as each time a period match
occurs. The postscaler selection bits have no effect in
this mode of the timer.
16.1.4
PWM TIME-BASE PRESCALER
The input clock to PTMR (FOSC/4), has prescaler
options of 1:1, 1:4, 1:16, or 1:64, selected by control
bits PTCKPS<1:0> in the PTCON SFR. The prescaler
counter is cleared when any of the following occurs:
The Double Update mode provides two additional func-
tions to the user. First, the control loop bandwidth is
doubled because the PWM duty cycles can be
updated, twice per period. Secondly, asymmetrical
center aligned PWM waveforms can be generated,
which are useful for minimizing output waveform distor-
tion in certain motor control applications.
• a write to the PTMR register
• a write to the PTCON register
• any device RESET
The PTMR register is not cleared when PTCON is
written.
Note: Programming a value of 0x0001 in the
period register could generate a continuous
interrupt pulse, and hence, must be
avoided.
16.1.5
PWM TIME-BASE POSTSCALER
The match output of PTMR can optionally be post-
scaled through a 4-bit postscaler (which gives a 1:1 to
1:16 scaling) to generate an interrupt.
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FIGURE 16-3:
EDGE ALIGNED PWM
16.3 PWM Period
PTPER is a 15-bit register and is used to set the count-
ing period for the PWM time-base. PTPER is a double
buffered register. The PTPER buffer contents are
loaded into the PTPER register at the following
instants:
New Duty Cycle Latched
PTPER
PTMR
Value
• Free Running and Single Shot modes: When the
PTMR register is reset to zero after a match with
the PTPER register.
• Up/Down Counting modes: When the PTMR
register is zero.
0
The value held in the PTPER buffer is automatically
loaded into the PTPER register, when the PWM time-
base is disabled (PTEN = 0).
Duty Cycle
Period
The PWM period can be determined from the following
formula:
EQUATION 16-1: PWM PERIOD
16.5 Center Aligned PWM
Center aligned PWM signals are produced by the mod-
ule when the PWM time-base is configured in an Up/
Down Counting mode (see Figure 16-4).
4(PTPER + 1)
PPWM =
FOSC (PTMRprescalevalue)
•
The PWM compare output is driven to the active state
when the value of the duty cycle register matches the
value of PTMR and the PWM time-base is counting
downwards (PTDIR = 1). The PWM compare output is
driven to the inactive state when the PWM time-base is
counting upwards (PTDIR = 0) and the value in the
PTMR register matches the duty cycle value.
If the PWM time-base is configured for one of the Up/
Down Count modes, the PWM period will be twice the
value provided by Equation 16-1.
The maximum resolution (in bits) for a given device
oscillator and PWM frequency can be determined from
the following formula:
If the value in a particular duty cycle register is zero,
then the output on the corresponding PWM pin will be
inactive for the entire PWM period. In addition, the out-
put on the PWM pin will be active for the entire PWM
period if the value in the duty cycle register is equal to
the value held in the PTPER register.
EQUATION 16-2: PWM RESOLUTION
FOSC
log
(
)
2
Fpwm
•
Resolution =
log(2)
FIGURE 16-4:
CENTER ALIGNED PWM
16.4 Edge Aligned PWM
Period/2
Edge aligned PWM signals are produced by the mod-
ule when the PWM time-base is in the Free Running or
Single Shot mode. For edge aligned PWM outputs, the
output for a given PWM channel has a period specified
by the value loaded in PTPER and a duty cycle speci-
fied by the appropriate duty cycle register (see
Figure 16-3). The PWM output is driven active at the
beginning of the period (PTMR = 0) and is driven inac-
tive, when the value in the duty cycle register matches
PTMR.
PTPER
PTMR
Value
Duty
Cycle
0
If the value in a particular duty cycle register is zero,
then the output on the corresponding PWM pin will be
inactive for the entire PWM period. In addition, the out-
put on the PWM pin will be active for the entire PWM
period if the value in the duty cycle register is greater
than the value held in the PTPER register.
Period
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When the PWM time-base is in the Up/Down Counting
mode, new duty cycle values are updated when the
value of the PTMR register is zero and the PWM time-
base begins to count upwards. The contents of the duty
cycle buffers are automatically loaded into the duty
cycle registers, when the PWM time-base is disabled
(PTEN = 0).
16.6 PWM Duty Cycle Comparison
Units
There are four 16-bit special function registers used to
specify duty cycle values for the PWM module:
• PDC1
• PDC2
• PDC3
• PDC4
When the PWM time-base is in the Up/Down Counting
mode with double updates, new duty cycle values are
updated when the value of the PTMR register is zero,
and when the value of the PTMR register matches the
value in the PTPER register. The contents of the duty
cycle buffers are automatically loaded into the duty
cycle registers when the PWM time-base is disabled
(PTEN = 0).
The value in each duty cycle register determines the
amount of time that the PWM output is in the active
state. The duty cycle registers are 16-bits wide. The LS
bit of a duty cycle register determines whether the
PWM edge occurs on Q1 or Q3. Thus, the PWM reso-
lution is effectively doubled.
16.7 Complementary PWM Operation
16.6.1
DUTY CYCLE REGISTER BUFFERS
In the Complementary mode of operation, each pair of
PWM outputs is fed by a complementary PWM signal.
A dead-time may be optionally inserted during device
switching, when both outputs are inactive for a short
period (Refer to Section 16.8).
The four PWM duty cycle registers are double buffered
to allow glitchless updates of the PWM outputs. For
each duty cycle, there is a duty cycle buffer register that
is accessible by the user and a second duty cycle reg-
ister that holds the actual compare value used in the
present PWM period.
In Complementary mode, the duty cycle comparison
units are assigned to the PWM outputs as follows:
For edge aligned PWM output, a new duty cycle value
will be updated whenever a match with the PTPER reg-
ister occurs and PTMR is reset. The contents of the
duty cycle buffers are automatically loaded into the
duty cycle registers when the PWM time-base is dis-
abled (PTEN = 0) and the UDIS bit is cleared in
PWMCON2.
• PDC1 register controls PWM1/PWM0 outputs
• PDC2 register controls PWM3/PWM2 outputs
• PDC3 register controls PWM5/PWM4 outputs
• PDC4 register controls PWM7/PWM6 outputs
The Complementary mode is selected for each PWM
I/O pin pair by clearing the appropriate PMODx bit in the
PWMCON1 SFR. The PWM I/O pins are set to Comple-
mentary mode by default upon a device RESET.
FIGURE 16-5:
PWM MODULE BLOCK DIAGRAM, ONE OUTPUT PAIR, COMPLEMENTARY MODE
VDD
PWM1
Duty Cycle
Comparator
Output
Override
Logic
Dead Band
Generator(1)
Polarity
Control
PWM0
PWM Duty
Cycle Register
Fault B pin
Fault A pin
Note 1: In the Complementary mode, the even channel cannot be forced active by a fault or override
event, when the odd channel is active.
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16.8.3
DEAD-TIME RANGES
16.8 Dead-Time Generators
The amount of dead-time provided by each dead-time
unit is selected by specifying the input clock prescaler
value and a 6-bit unsigned value. The amount of dead-
time provided by each unit may be set independently.
Dead-time generation may be provided when any of
the PWM I/O pin pairs are operating in the Comple-
mentary Output mode. The PWM outputs use Push-
Pull drive circuits. Due to the inability of the power out-
put devices to switch instantaneously, some amount of
time must be provided between the turn-off event of
one PWM output in a complementary pair and the turn-
on event of the other transistor.
Four input clock prescaler selections have been pro-
vided to allow a suitable range of dead-times, based on
the device operating frequency. The clock prescaler
option may be selected independently for each of the
two dead-time values. The dead-time clock prescaler
values are selected using the DTAPS<1:0> and
DTBPS<1:0> control bits in the DTCON1 SFR. The fol-
lowing clock prescaler options may be selected for
each of the dead-time values:
The PWM module allows two different dead-times to be
programmed. These two dead-times may be used in
one of two methods described below to increase user
flexibility:
• The PWM output signals can be optimized for dif-
ferent turn-off times in the high side and low side
transistors in a complementary pair of transistors.
The first dead-time is inserted between the turn-
off event of the lower transistor of the complemen-
tary pair and the turn-on event of the upper tran-
sistor. The second dead-time is inserted between
the turn-off event of the upper transistor and the
turn-on event of the lower transistor.
• FOSC/4
• FOSC/8
• FOSC/16
• FOSC/32
After the prescaler values are selected, the dead-time
for each unit is adjusted by loading two 6-bit unsigned
values into the DTCON1 special function register.
• The two dead-times can be assigned to individual
PWM I/O pin pairs. This operating mode allows
the PWM module to drive different transistor/load
combinations with each complementary PWM I/O
pin pair.
The dead-time unit prescalers are cleared on the fol-
lowing events:
• On a load of the down timer due to a duty cycle
comparison edge event.
• On a write to the DTCON1 or DTCON2 registers.
• On any device RESET.
16.8.1
DEAD-TIME GENERATORS
Note: The user should not modify the DTCON1
or DTCON2 values while the PWM module
is operating (PTEN = 1). Unexpected
results may occur.
Each complementary output pair for the PWM module
has a 6-bit down counter that is used to produce the
dead-time insertion. As shown in Figure 16-8, each
dead-time unit has a rising and falling edge detector
connected to the duty cycle comparison output.
16.8.4
DEAD-TIME DISTORTION
16.8.2
DEAD-TIME ASSIGNMENT
For small PWM duty cycles, the ratio of dead-time to
the active PWM time may become large. In this case,
the inserted dead-time will introduce distortion into
waveforms produced by the PWM module. The user
can ensure that dead-time distortion is minimized by
keeping the PWM duty cycle at least three times larger
than the dead-time (see Figure 16-7).
The DTCON2 SFR contains control bits that allow the
dead-times to be assigned to each of the complemen-
tary outputs. Table 16-1 summarizes the function of
each dead-time selection control bit.
TABLE 16-1: DEAD-TIME SELECTION BITS
A similar effect occurs for duty cycles at or near 100%.
The maximum duty cycle used in the application should
be chosen such that the minimum inactive time of the
signal is at least three times larger than the dead-time.
Bit
Function
DTS1R
DTS1F
DTS2R
DTS2F
DTS3R
DTS3F
DTS4R
DTS4F
Selects PWM0/PWM1 rising edge dead-time.
Selects PWM0/PWM1 falling edge dead-time.
Selects PWM2/PWM3 rising edge dead-time.
Selects PWM2/PWM3 falling edge dead-time.
Selects PWM4/PWM5 rising edge dead-time.
Selects PWM4/PWM5 falling edge dead-time.
Selects PWM6/PWM7 rising edge dead-time.
Selects PWM6/PWM7 falling edge dead-time.
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FIGURE 16-6:
DEAD-TIME CONTROL UNITS BLOCK DIAGRAM
Dead-Time Prescale bits
Dead-Time B (DTCON1H)
6
Dead-Time A (DTCON1L)
6
4
PWM1
PWM0
Dead-Time Unit
#1
PWM In
Note: There are 3 other Dead-Time Units, corresponding to PWM7/6, PWM5/4, and PWM 3/2, respectively.
FIGURE 16-7:
DEAD-TIME TIMING DIAGRAM
Duty Cycle Generator
PWM1
PWM0
Time selected by DTS1R bit (A or B)
Time selected by DTS1F bit (A or B)
FIGURE 16-8:
DEAD-TIME CONTROL UNIT BLOCK DIAGRAM FOR ONE PWM OUTPUT PAIR
Dead-Time
Select bits
(DTSxR, DTSxF)
2
Zero Compare
Clock Control
and Prescaler
FOSC/4
6-bit Down Counter
Odd PWM Signal to
Output Control Block
Dead-Time
Prescale
Select A
Even PWM Signal to
Output Control Block
2
2
Dead-Time
Prescale
Select B
Dead-Time Register B
Dead-Time Register A
Duty Cycle
Compare Input
Note: ’x’ represents Dead-Time Units 1, 2, 3, and 4.
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In the Independent mode, each duty cycle generator is
connected to both of the PWM I/O pins in an output pair
(see Figure 16-9). By using the associated duty cycle
register and the appropriate bits in the OVDCON regis-
ter, the user may select the following signal output
options for each PWM I/O pin operating in the Indepen-
dent mode:
16.9 Independent PWM Output
An independent PWM Output mode is required for driv-
ing certain types of loads. A particular PWM output pair
is in the Independent Output mode when the corre-
sponding PMOD bit in the PWMCON1 register is set.
No dead-time control is implemented between adjacent
PWM I/O pins when the module is operating in the
Independent mode and both I/O pins are allowed to be
active simultaneously.
• I/O pin outputs PWM signal
• I/O pin inactive
• I/O pin active
Refer to Register 16-11 for details on the OVDCON
SFR.
FIGURE 16-9:
PWM MODULE BLOCK DIAGRAM, ONE OUTPUT PAIR, INDEPENDENT MODE
VDD
Duty Cycle
Comparator
PWM1
Output
Polarity
Control
Override
Logic
PWM Duty
Cycle Register
VDD
Fault B
Fault A
PWM0
Output
Polarity
Control
Override
Logic
Fault A
Fault B
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When a match with a duty cycle register occurs, the
PWM I/O pin is driven to the inactive state. When a
match with the PTPER register occurs, the PTMR reg-
ister is cleared, all active PWM I/O pins are driven to
the inactive state, the PTEN bit is cleared, and an inter-
rupt is generated (see Figure 16-10).
16.10 Single Pulse PWM Operation
The PWM module produces single pulse outputs when
the PTCON control bits PTMOD<1:0> = 10. Only edge
aligned outputs may be produced in the Single Pulse
mode. In Single Pulse mode, the PWM I/O pin(s) are
driven to the active state when the PTEN bit is set.
FIGURE 16-10:
SINGLE PULSE PWM OPERATION
PTEN bit Set by
Software
PTEN bit Cleared by
Hardware
PWM Output
PTPER Value
Duty Cycle
PTMR Value
16.11 PWM Output Override
16.12 PWM Output and Polarity Control
The PWM output override bits allow the user to manu-
ally drive the PWM I/O pins to specified logic states,
independent of the duty cycle comparison units.
There are three device configuration bits associated
with the PWM module that provide PWM output pin
control.
All control bits associated with the PWM output over-
ride function are contained in the OVDCON register.
The upper half of the OVDCON register contains eight
bits, POVD<7:0>, that determine which PWM I/O pins
will be overridden. The lower half of the OVDCON reg-
ister contains eight bits, POUT<7:0>, that determine
the state of the PWM I/O pins when a particular output
is overridden, via the POVD bits.
• HPOL configuration bit
• LPOL configuration bit
• PWMPIN configuration bit
These three configuration bits (see Section 23.0) work
in conjunction with the four PWM enable bits
(PWMEN<4:1>), located in the PWMCON1 SFR. The
configuration bits and PWM enable bits ensure that the
PWM pins are in the correct states after a device
RESET occurs. The PWMPIN configuration fuse
allows the PWM module outputs to be optionally
enabled on a device RESET. If PWMPIN = 0, the PWM
outputs will be driven to their inactive states at RESET.
If PWMPIN = 1 (Default), the PWM outputs will be tri-
stated. The HPOL bit specifies the polarity for outputs
1, 3, 5 and 7, whereas the LPOL bit specifies the polar-
ity for outputs 0, 2, 4 and 6.
16.11.1 COMPLEMENTARY OUTPUT MODE
When the even numbered pin is driven active via the
OVDCON register, the output signal is forced to be the
complement of the odd numbered I/O pin in the pair
(see Figure 16-5 for details.) However, dead-time
insertion is still performed when PWM channels are
overridden manually.
16.11.2 OVERRIDE SYNCHRONIZATION
16.12.1 OUTPUT PIN CONTROL
If the OSYNC bit in the PWMCON2 register is set, all
output overrides performed via the OVDCON register
are synchronized to the PWM time-base. Synchronous
output overrides occur at the following times:
The PWMEN<4:1> control bits in the PWMCON1 SFR
enable each PWM output pin pair for use by the mod-
ule. Each PWMEN bit controls the following output
pairs:
• Edge Aligned mode, when PTMR is zero.
• PWMEN1 enables PWM0/PWM1 output pair
• PWMEN2 enables PWM2/PWM3 output pair
• PWMEN3 enables PWM4/PWM5 output pair
• PWMEN4 enables PWM6/PWM7 output pair
• Center Aligned modes, when PTMR is zero and
when the value of PTMR matches PTPER.
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16.13.4 FAULT INPUT MODES
16.13 PWM Fault Pins
Each of the fault input pins has two modes of operation:
There are two fault pins (FLTA and FLTB) associated
with the PWM module. When asserted, these pins can
optionally drive each of the PWM I/O pins to a defined
state.
• Latched Mode: When the fault pin is driven low,
the PWM outputs will go to the states defined in
the FLTACON/FLTBCON register. The PWM out-
puts will remain in this state until the fault pin is
driven high and the corresponding interrupt flag
has been cleared in software. When both of these
actions have occurred, the PWM outputs will
return to normal operation at the beginning of the
next PWM cycle or half-cycle boundary. If the
interrupt flag is cleared before the fault condition
ends, the PWM module will wait until the fault pin
is no longer asserted, to restore the outputs.
16.13.1 FAULT PIN ENABLE BITS
The FLTACON and FLTBCON Special Function Regis-
ters each have 4 control bits that determine whether a
particular pair of PWM I/O pins is to be controlled by the
fault input pin. To enable a specific PWM I/O pin pair for
fault overrides, the corresponding bit should be set in
the FLTACON or FLTBCON register.
If all enable bits are cleared in the FLTACON or
FLTBCON registers, then the corresponding fault input
pin has no effect on the PWM module and the pin may
be used as a general purpose interrupt pin or I/O.
• Cycle-by-Cycle Mode: When the fault input pin is
driven low, the PWM outputs remain in the
defined fault states for as long as the fault pin is
held low. After the fault pin is driven high, the
PWM outputs return to normal operation at the
beginning of the following PWM cycle, or half-
cycle boundary.
Note: The fault pin logic can operate indepen-
dent of the PWM logic. If all the enable bits
in the FLTACON/FLTBCON register are
cleared, then the fault pin(s) could be used
as general purpose interrupt pin(s). Each
fault pin has an interrupt vector, interrupt
flag bit and interrupt priority bits associated
with it.
The operating mode for each fault input pin is selected
using the FLTAM and FLTBM control bits in the
FLTACON and FLTBCON Special Function Registers.
Each of the fault pins can be controlled manually in
software.
16.13.2 FAULT STATES
16.14 PWM Update Lockout
The FLTACON and FLTBCON special function regis-
ters have 8 bits each, that determine the state of each
PWM I/O pin when it is overridden by a fault input.
When these bits are cleared, the PWM I/O pin is driven
to the inactive state. If the bit is set, the PWM I/O pin
will be driven to the active state. The active and inactive
states are referenced to the polarity defined for each
PWM I/O pin (HPOL and LPOL polarity control bits).
For a complex PWM application, the user may need to
write up to four duty cycle registers and the time-base
period register, PTPER, at a given time. In some appli-
cations, it is important that all buffer registers be written
before the new duty cycle and period values are loaded
for use by the module.
The PWM update lockout feature may optionally be
enabled so that the user may specify when new duty
cycle buffer values are valid. The PWM update lockout
feature is enabled by setting the UDIS control bit in the
PWMCON2 SFR. The UDIS bit affects all duty cycle
buffer registers and the PWM time-base period buffer,
PTPER.
A special case exists when a PWM module I/O pair is
in the Complementary mode and both pins are pro-
grammed to be active on a fault condition. The odd
numbered PWM I/O pin always has priority in the Com-
plementary mode, so that both I/O pins cannot be
driven active simultaneously. Refer to Figure 16-5 for
details.
16.13.3 FAULT PIN PRIORITY
If both fault input pins have been assigned to control a
particular PWM I/O pin, the fault state programmed for
the Fault A input pin will take priority over the Fault B
input pin.
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16.15.1 SPECIAL EVENT TRIGGER
POSTSCALER
16.15 PWM Special Event Trigger
The PWM module has a special event trigger that
allows A/D conversions to be synchronized to the PWM
time-base. The A/D sampling and conversion time may
be programmed to occur at any point within the PWM
period. The special event trigger allows the user to min-
imize the delay between the time when A/D conversion
results are acquired and the time when the duty cycle
value is updated.
The PWM special event trigger has a postscaler that
allows a 1:1 to 1:16 postscale ratio. The postscaler is
configured by writing the SEVOPS<3:0> control bits in
the PWMCON2 SFR.
The special event output postscaler is cleared on the
following events:
• Any write to the SEVTCMP register.
• Any device RESET.
The PWM special event trigger has an SFR named
SEVTCMP, and five control bits to control its operation.
The PTMR value for which a special event trigger
should occur is loaded into the SEVTCMP register.
When the PWM time-base is in an Up/Down Counting
mode, an additional control bit is required to specify the
counting phase for the special event trigger. The count
phase is selected using the SEVTDIR control bit in the
SEVTCMP SFR. If the SEVTDIR bit is cleared, the spe-
cial event trigger will occur on the upward counting
cycle of the PWM time-base. If the SEVTDIR bit is set,
the special event trigger will occur on the downward
count cycle of the PWM time-base. The SEVTDIR
control bit has no effect unless the PWM time-base is
configured for an Up/Down Counting mode.
16.16 PWM Operation During CPU
SLEEP Mode
The Fault A and Fault B input pins have the ability to
wake the CPU from SLEEP mode. The PWM module
generates an interrupt if either of the fault pins is
driven low while in SLEEP.
16.17 PWM Operation During CPU IDLE
Mode
The PTCON SFR contains a PTSIDL control bit. This
bit determines if the PWM module will continue to
operate or stop when the device enters IDLE mode. If
PTSIDL = 0, the module continues to operate. If
PTSIDL = 1, the module will stop operation as long as
the CPU remains in IDLE mode.
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REGISTER 16-1: PTCON: PWM TIME-BASE CONTROL REGISTER
Upper Half:
R/W-0
PTEN
R-0
R/W-0
U-0
U-0
U-0
U-0
U-0
—
PTSIDL
—
—
—
—
—
bit 15
bit 8
Lower Half:
R/W-0
PTOPS3
bit 7
R/W-0
R/W-0
PTOPS1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTOPS2
PTOPS0 PTCKPS1 PTCKPS0 PTMOD1 PTMOD0
bit 0
bit 15
PTEN: PWM Time-Base Timer Enable bit
1= PWM time-base is ON
0= PWM time-base is OFF
bit 14
bit 13
Unimplemented: Read as ‘0’. User software should write 0 to this bit
PTSIDL: PWM Time-Base Stop in IDLE Mode bit
1= PWM time-base halts in CPU IDLE mode
0= PWM time-base runs in CPU IDLE mode
bit 12-8 Unimplemented: Read as ‘0’. User software should write 0 to these bits.
bit 7-4
PTOPS<3:0>: PWM Time-Base Output Postscale Select bits
1111= 1:16 Postscale
1110= 1:8 Postscale
| |
| |
0000= 1:1 Postscale
bit 3-2
bit 1-0
PTCKPS<1:0>: PWM Time-Base Input Clock Prescale Select bits
11= PWM time-base input clock is FOSC/256 (1:64 prescale)
10= PWM time-base input clock is FOSC/64 (1:16 prescale)
01= PWM time-base input clock is FOSC/16 (1:4 prescale)
00= PWM time-base input clock is FOSC/4 (1:1 prescale)
PTMOD<1:0>: PWM Time-Base Mode Select bits
11= PWM time-base operates in a Continuous Up/Down mode with interrupts for double PWM updates
10= PWM time-base operates in a Continuous Up/Down counting mode
01= PWM time-base configured for Single Shot mode
00= PWM time-base operates in a Free Running mode
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
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REGISTER 16-2: PTMR: PWM TIME-BASE COUNT REGISTER
Upper Half:
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTMR8
bit 8
PTDIR
PTMR14
PTMR13
PTMR12
PTMR11 PTMR10 PTMR9
bit 15
Lower Half:
R/W-0
R/W-0
PTMR6
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTMR1
R/W-0
PTMR7
PTMR5
PTMR4
PTMR3
PTMR2
PTMR0
bit 7
bit 0
bit 15
PTDIR: PWM Time-Base Count Direction Status bit
1= PWM time-base counts down
0= PWM time-base counts up
bit 14-0 PTMR<14:0>: PWM Time-Base Count Value bits
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
REGISTER 16-3: PTPER: PWM TIME-BASE PERIOD REGISTER
Upper Half:
U-0
R/W-0
PTPER14 PTPER13 PTPER12 PTPER11 PTPER10 PTPER9 PTPER8
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
bit 15
Lower Half:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTPER0
bit 0
PTPER7
bit 7
PTPER6
PTPER5
PTPER4
PTPER3
PTPER2
PTPER1
bit 15
Unimplemented: Read as ‘0’. User software should write 0 to this bit.
bit 14-0 PTPER<14:0>: PWM Time-Base Period Value bits
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
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REGISTER 16-4: SEVTCMP: SPECIAL EVENT TRIGGER COMPARE COUNT REGISTER
Upper Half:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SEVTDIR SEVTCMP14 SEVTCMP13 SEVTCMP12 SEVTCMP11 SEVTCMP10 SEVTCMP9 SEVTCMP8
bit 15
bit 8
Lower Half:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SEVTCMP7 SEVTCMP6 SEVTCMP5 SEVTCMP4 SEVTCMP3 SEVTCMP2 SEVTCMP1 SEVTCMP0
bit 7 bit 0
bit 15
SEVTDIR: Special Event Trigger Time-Base Direction bit
1= A special event trigger will occur when the PWM time-base is counting downwards
0= A special event trigger will occur when the PWM time-base is counting upwards
bit 14-0 SEVTCMP<14:0>: Special Event Compare Count Value bits
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
REGISTER 16-5: PWMCON1: PWM CONTROL REGISTER1
Upper Half:
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
PMOD4
PMOD3 PMOD2
PMOD1
bit 15
bit 8
Lower Half:
U-0
—
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
—
—
—
PWMEN4 PWMEN3 PWMEN2 PWMEN1
bit 0
bit 7
bit 15-12 Unimplemented: Read as ‘0’. User software should write 0 to these bits.
bit 11-8 PMOD<4:1>: PWM I/O Pair Mode bits
1= PWM I/O pin pair is in the Independent Output mode
0= PWM I/O pin pair is in the Complementary Output mode
bit 7-4
bit 3-0
Unimplemented: Read as ‘0’. User software should write 0 to these bits.
PWMEN<4:1>: PWM I/O Pair Enable bits
1= PWM I/O pin pair is enabled for PWM output
0= PWM I/O pin pair disabled. I/O pins becomes general purpose I/O.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
DS70032B-page 188
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2002 Microchip Technology Inc.
dsPIC30F
REGISTER 16-6: PWMCON2: PWM CONTROL REGISTER2
Upper Half:
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
SEVOPS3 SEVOPS2 SEVOPS1 SEVOPS0
bit 8
bit 15
Lower Half:
U-0
—
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
UDIS
—
—
—
—
—
OSYNC
bit 7
bit 0
bit 15-12 Unimplemented: Read as ‘0’. User software should write 0 to these bits.
bit 11-8 SEVOPS<3:0>: PWM Special Event Trigger Output Postscale Select bits
1111= 1:16 Postscale
1110= 1:8 Postscale
| |
| |
0000= 1:1 Postscale
bit 7-2
bit 1
Unimplemented: Read as ‘0’. User software should write 0 to these bits.
OSYNC: Output Override Synchronization bit
1= Output overrides via the OVDCON register are synchronized to the PWM time-base
0= Output overrides via the OVDCON register are asynchronous
bit 0
UDIS: PWM Update Disable bit
1= Updates from duty cycle and period buffer registers are disabled
0= Updates from duty cycle and period buffer registers are enabled
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 189
dsPIC30F
REGISTER 16-7: DTCON1: DEAD-TIME CONTROL REGISTER1
Upper Half:
R/W-0
DTBPS1
bit 15
R/W-0
R/W-0
DTB5
R/W-0
DTB4
R/W-0
DTB3
R/W-0
DTB2
R/W-0
DTB1
R/W-0
DTB0
DTBPS0
bit 8
Lower Half:
R/W-0
R/W-0
R/W-0
DTA5
R/W-0
DTA4
R/W-0
DTA3
R/W-0
DTA2
R/W-0
DTA1
R/W-0
DTA0
DTAPS1
DTAPS0
bit 7
bit 0
bit 15-14 DTBPS<1:0>: Dead-Time Unit B Prescale Select bits
11= Clock source for dead-time Unit B is FOSC/32
10= Clock source for dead-time Unit B is FOSC/16
01= Clock source for dead-time Unit B is FOSC/8
00= Clock source for dead-time Unit B is FOSC/4
bit 13-8 DTB<5:0>: Unsigned 6-bit Dead-Time Value bits for Dead-Time Unit B
bit 7-6
DTAPS<1:0>: Dead-Time Unit A Prescale Select bits
11= Clock source for dead-time Unit A is FOSC/32
10= Clock source for dead-time Unit A is FOSC/16
01= Clock source for dead-time Unit A is FOSC/8
00= Clock source for dead-time Unit A is FOSC/4.
bit 5-0
DTA<5:0>: Unsigned 6-bit Dead-Time Value bits for Dead-Time Unit A
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
DS70032B-page 190
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REGISTER 16-8: DTCON2: DEAD-TIME CONTROL REGISTER2
Upper Half:
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
Lower Half:
R/W-0
R/W-0
DTS4F
R/W-0
DTS3R
R/W-0
DTS3F
R/W-0
R/W-0
R/W-0
DTS1R
R/W-0
DTS4R
bit 7
DTS2R
DTS2F
DTS1F
bit 0
bit 15-8 Unimplemented: Read as ‘0’. User software should write 0 to these bits.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DTS4R: Dead-Time Select bit
1= Dead-time is provided from Unit B
0= Dead-time is provided from Unit A
DTS4F: Dead-Time Select bit
1= Dead-time is provided from Unit B
0= Dead-time is provided from Unit A
DTS3R: Dead-Time Select bit
1= Dead-time is provided from Unit B
0= Dead-time is provided from Unit A
DTS3F: Dead-Time Select bit
1= Dead-time is provided from Unit B
0= Dead-time is provided from Unit A
DTS2R: Dead-Time Select bit
1= Dead-time is provided from Unit B
0= Dead-time is provided from Unit A
DTS2F: Dead-Time Select bit
1= Dead-time is provided from Unit B
0= Dead-time is provided from Unit A
DTS1R: Dead-Time Select bit
1= Dead-time is provided from Unit B
0= Dead-time is provided from Unit A
DTS1F: Dead-Time Select bit
1= Dead-time is provided from Unit B
0= Dead-time is provided from Unit A
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
2002 Microchip Technology Inc.
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DS70032B-page 191
dsPIC30F
REGISTER 16-9: FLTACON: FAULT A CONTROL REGISTER
Upper Half:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FAOV7
FAOV6
FAOV5
FAOV4
FAOV3
FAOV2
FAOV1
FAOV0
bit 15
bit 8
Lower Half:
R/W-0
U-0
U-0
U-0
R/W-0
FAEN4
R/W-0
R/W-0
R/W-0
FLTAM
—
—
—
FAEN3
FAEN2
FAEN1
bit 7
bit 0
bit 15-8 FAOV<7:0>: Fault Input A PWM Override Value bits
1= The PWM output pin is driven ACTIVE on an external fault input event
0= The PWM output pin is driven INACTIVE on an external fault input event
bit 7
FLTAM: Fault A Mode bit
1= The Fault A input pin functions in the Cycle-by-Cycle Limit mode
0= The Fault A input pin latches all control pins to the programmed states in FAOV7:FAOV0
bit 6-4
bit 3-0
Unimplemented. Read as ‘0’. User software should write 0 to these bits.
FAEN<4:1>: Fault Input A Enable bits
1= PWM I/O pin pair is controlled by Fault Input A
0= PWM I/O pin pair is not controlled by Fault Input A
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
REGISTER 16-10: FLTBCON: FAULT B CONTROL REGISTER
Upper Half:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FBOV7
FBOV6
FBOV5
FBOV4
FBOV3
FBOV2
FBOV1
FBOV0
bit 15
bit 8
Lower Half:
R/W-0
U-0
U-0
U-0
R/W-0
FBEN4
R/W-0
R/W-0
R/W-0
FLTBM
—
—
—
FBEN3
FBEN2
FBEN1
bit 7
bit 0
bit 15-8 FBOV<7:0>: Fault Input B PWM Override Value bits
1= The PWM output pin is driven ACTIVE on an external fault input event
0= The PWM output pin is driven INACTIVE on an external fault input event
bit 7
FLTBM: Fault B Mode bit
1= The Fault B input pin functions in the Cycle-by-Cycle Limit mode
0= The Fault B input pin latches all control pins to the programmed states in FBOV7:FBOV0
bit 6-4
bit 3-0
Unimplemented: Read as 0. User software should write 0 to these bits.
FBEN<4:1>: Fault Input B Enable bits
1= PWM I/O pin pair is controlled by Fault Input A
0= PWM I/O pin pair is not controlled by Fault Input A
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
DS70032B-page 192
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dsPIC30F
REGISTER 16-11: OVDCON: OUTPUT OVERRIDE CONTROL REGISTER
Upper Half:
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
POVD0
bit 8
POVD7
POVD6
POVD5
POVD4
POVD3
POVD2
POVD1
bit 15
Lower Half:
R/W-0
R/W-0
R/W-0
POUT5
R/W-0
POUT4
R/W-0
POUT3
R/W-0
R/W-0
POUT1
R/W-0
POUT7
POUT6
POUT2
POUT0
bit 7
bit 0
bit 15-8 POVD<7:0>: PWM Output Override bits
1= Output on PWM I/O pin is controlled by the value in the duty cycle register and the PWM time-base
0= Output on PWM I/O pin is controlled by the value in the corresponding POUT bit
bit 7-0
POUT<7:0> : PWM Manual Output bits
1= Output on PWM I/O pin is driven active HIGH when the corresponding PWM output override bit
is cleared
0= Output on PWM I/O pin is driven active LOW when the corresponding PWM output override bit
is cleared
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
2002 Microchip Technology Inc.
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DS70032B-page 193
dsPIC30F
REGISTER 16-12: PDC1: PWM DUTY CYCLE 1 REGISTER
Upper Half:
R/W-0
P1DC15
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
P1DC14
P1DC13
P1DC12
P1DC11 P1DC10
P1DC9
P1DC8
bit 8
Lower Half:
R/W-0
R/W-0
R/W-0
P1DC5
R/W-0
R/W-0
P1DC3
R/W-0
P1DC2
R/W-0
P1DC1
R/W-0
P1DC7
P1DC6
P1DC4
P1DC0
bit 7
bit 0
bit 15-0 P1DC<15:0>: PWM Duty Cycle #1 Value bits
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
REGISTER 16-13: PDC2: PWM DUTY CYCLE 2 REGISTER
Upper Half:
R/W-0
P2DC15
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
P2DC14
P2DC13
P2DC12
P2DC11 P2DC10
P2DC9
P2DC8
bit 8
Lower Half:
R/W-0
R/W-0
R/W-0
P2DC5
R/W-0
R/W-0
P2DC3
R/W-0
P2DC2
R/W-0
P2DC1
R/W-0
P2DC7
P2DC6
P2DC4
P2DC0
bit 7
bit 0
bit 15-0 P2DC<15:0>: PWM Duty Cycle #2 Value bits
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
DS70032B-page 194
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REGISTER 16-14: PDC3: PWM DUTY CYCLE 3 REGISTER
Upper Half:
R/W-0
P3DC15
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
P3DC8
bit 8
P3DC14
P3DC13
P3DC12
P3DC11 P3DC10
P3DC9
Lower Half:
R/W-0
R/W-0
R/W-0
P3DC5
R/W-0
R/W-0
P3DC3
R/W-0
P3DC2
R/W-0
P3DC1
R/W-0
P3DC7
P3DC6
P3DC4
P3DC0
bit 7
bit 0
bit 15-0 P3DC<15:0>: PWM Duty Cycle #3 Value bits
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
REGISTER 16-15: PDC4: PWM DUTY CYCLE 4 REGISTER
Upper Half:
R/W-0
P4DC15
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
P4DC14
P4DC13
P4DC12
P4DC11 P4DC10
P4DC9
P4DC8
bit 8
Lower Half:
R/W-0
R/W-0
R/W-0
P4DC5
R/W-0
R/W-0
P4DC3
R/W-0
P4DC2
R/W-0
P4DC1
R/W-0
P4DC7
P4DC6
P4DC4
P4DC0
bit 7
bit 0
bit 15-0 P4DC<15:0>: PWM Duty Cycle #4 Value bits
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 195
dsPIC30F
NOTES:
DS70032B-page 196
AdvanceInformation
2002 Microchip Technology Inc.
dsPIC30F
The clock provided to the module is (FOSC/4). This
clock is then prescaled by the primary (PPRE<1:0>)
and the secondary (SPRE<2:0>) prescale factors. The
CKE bit determines whether transmit occurs on transi-
tion from active clock state to IDLE clock state, or vice
versa. The CKP bit selects the IDLE state (high or low)
for the clock.
17.0 SPI MODULE
The Serial Peripheral Interface (SPI) module is a syn-
chronous serial interface, useful for communicating
with other peripheral or microcontroller devices, such
as EEPROMs, shift registers, display drivers and A/D
converters. It is compatible with Motorola’s SPITM and
SIOPTM interfaces.
17.1.1
WORD AND BYTE
COMMUNICATION
17.1 Operating Function Description
Each SPI module consists of a 16-bit shift register,
SPIxSR (where x = 1 or 2), used for shifting data in
and out, and a buffer register, SPIxBUF. A control reg-
ister, SPIxCON, configures the module. Additionally, a
status register, SPIxSTAT, indicates various status
conditions.
A control bit, MODE16 (SPIxCON<10>), allows the
module to communicate in either 16-bit or 8-bit mode.
Figure 17-5 through Figure 17-7 demonstrate the func-
tionality of the module in 8-bit mode. 16-bit operation is
identical to 8-bit operation, except that the number of
bits transmitted is 16 instead of 8.
The serial interface consists of 4 pins: SDIx (serial
data input), SDOx (serial data output), SCKx (shift
clock input or output), and SSx (active low slave
select).
The SPI module always gets reset to start a new com-
munication when the MODE16 bit is changed by the
user.
A basic difference between 8-bit and 16-bit operation is
that the data is transmitted out of bit 7 of the SPIxSR for
8-bit operation, and data is transmitted out of bit15 of
the SPIxSR for 16-bit operation. In both modes, data is
shifted into bit 0 of the SPIxSR.
In Master mode operation, SCK is a clock output, but
in Slave mode, it is a clock input.
A series of eight (8) or sixteen (16) clock pulses shifts
out bits from the SPIxSR to SDOx pin and simulta-
neously shifts in data from SDIx pin. An interrupt is
generated when the transfer is complete and the cor-
responding interrupt flag bit (SPI1IF or SPI2IF) is set.
This interrupt can be disabled through an interrupt
enable bit (SPI1IE or SPI2IE).
17.1.2
SDOx DISABLE
A control bit, DISSDO, is provided to the SPIxCON reg-
ister to allow the SDOx output to be disabled. This will
allow the SPI module to be connected in an input only
configuration. SDO can also be used for general
purpose I/O.
The receive operation is double buffered. When a
complete byte is received, it is transferred from
SPIxSR to SPIxBUF.
17.2 Framed SPI Support
If the receive buffer is full when new data is being
transferred from SPIxSR to SPIxBUF, the module will
set the SPIROV bit, indicating an overflow condition.
The transfer of the data from SPIxSR to SPIxBUF will
not be completed and the new data will be lost. The
module will not respond to SCL transitions while
SPIROV is 1, effectively disabling the module until
SPIxBUF is read by user software.
The module supports a basic framed SPI protocol in
Master or Slave mode. The control bit FRMEN enables
framed SPI support and causes the SSx pin to perform
the frame synchronization pulse (FSYNC) function.
The control bit SPIFSD determines whether the SSx
pin is an input or an output, i.e., whether the module
receives or generates the frame synchronization pulse.
The frame pulse is an active high pulse for a single SPI
clock cycle. When frame synchronization is enabled,
the data starts transmitting only on the subsequent
transmit edge of the SPI clock.
Transmit writes are also double buffered. The user
writes to SPIxBUF. When the master or slave transfer
is completed, the SPIxSR is swapped with SPIxBUF.
The received data is thus placed in SPIxBUF and the
transmit data in SPIxSR is ready for the next transfer.
17.2.1
MODE: SPI MASTER, FRAME
MASTER
In Master mode, the clock is generated by prescaling
the system clock. Data is transmitted as soon as
SPIBUF is written to. The interrupt is generated at the
middle of the transfer of the last bit.
With framed SPI enabled, the clock will be output con-
tinuously, regardless of whether the module is transmit-
ting. The FRMEN bit is high, and the SPIFSD bit is low.
When the SPIxBUF is written, the SSx pin will be driven
high on the next transmit edge of the SPI clock. The
SSx pin will be high for one SPI clock cycle. Data will
start transmitting on the next transmit edge of the SPI
clock, as shown in Figure 17-1.
In Slave mode, data is transmitted and received as
external clock pulses appear on SCK. Again, the inter-
rupt is generated when the last bit is latched in. If SSx
control is enabled, then transmission and reception are
enabled only when SSx = low. The SDOx output will be
disabled in SSx mode with SSx high.
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 197
dsPIC30F
17.2.2
MODE: SPI MASTER, FRAME
SLAVE
17.2.3
MODE: SPI SLAVE, FRAME
MASTER
The FRMEN bit is high, and the SPIFSD bit is high. The
SSx pin is an input, and it is sampled on the sample
edge of the SPI clock. When it is sampled high, data will
be transmitted on the subsequent transmit edge of the
SPI clock, as shown in Figure 17-2. An interrupt will be
generated when the transmission is complete. The
user must make sure that the correct data is loaded into
the SPIxBUF for transmission before the SSx signal is
received.
With framed SPI enabled, FRMEN = high, the input SPI
clock will be continuous in Slave mode. the SSx pin will
be an output when the SPIFSD bit is low. Therefore,
when the SPIxBUF is written, the module will drive the
SSx pin high on the next transmit edge of the SPI clock.
The SSx pin will be driven high for one SPI clock cycle.
Data will start transmitting on the next SPI clock trans-
mit edge.
17.2.4
MODE: SPI SLAVE, FRAME SLAVE
The FRMEN bit is high, and the SPIFSD bit is high.
Therefore, both the SCK and SSx pins will be inputs.
The SSx pin will be sampled on the sample edge of the
SPI clock. When SSx is sampled high, data will be
transmitted on the next transmit edge of SCK.
FIGURE 17-1:
SPI MASTER, FRAME MASTER
SCKx
(CKP = 0, CKE = 0)
SSx
SDOx
SDIx
Bit 15
Bit 15
Bit 14
Bit 14
Bit 13
Bit 13
Bit 12
Bit 12
Write to
SPIxBUF
Sample
FIGURE 17-2:
SPI MASTER, FRAME SLAVE
SCKx
(CKP = 0, CKE = 0)
SSx
SDOx
SDIx
Bit 15
Bit 15
Bit 14
Bit 14
Bit 13
Bit 13
Bit 12
Bit 12
Sample
SSx
Sample
DS70032B-page 198
AdvanceInformation
2002 Microchip Technology Inc.
dsPIC30F
FIGURE 17-3:
SPI BLOCK DIAGRAM
Internal
Data Bus
Read
Write
SPIxBUF
SWAP Buffers
SPIxSR
bit0
SDIx
SDOx
Shift
Clock
SS & FSYNC
Control
Clock
Control
Edge
Select
SSx
Secondary
Prescaler
1,2,4,6,8
Primary
FOSC
Prescaler
1, 4, 16, 64
SCKx
Enable Master Clock
Note: x = 1 or 2.
FIGURE 17-4:
SPI MASTER/SLAVE CONNECTION
SPI Master
SPI Slave
SDOx
SDIy
Serial Input Buffer
(SPIxBUF)
Serial Input Buffer
(SPIxBUF)
SDIx
SDOy
SCKy
Shift Register
(SPIxSR)
Shift Register
(SPIxSR)
LSb
MSb
MSb
LSb
Serial Clock
SCKx
PROCESSOR 1
PROCESSOR 2
Note: x = 1 or 2, y = 1 or 2.
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 199
dsPIC30F
FIGURE 17-5:
SPI MODE TIMING (8-BIT MASTER MODE)
Write to
SPIxBUF
SCKx
(CKP = 0
CKE =0)
SCKx
(CKPx = 1
CKE = 0)
4 Clock
Modes
SCKx
(CKP = 0
CKE = 1)
SCKx
(CKP = 1
CKE = 1)
bit6
bit6
bit2
bit2
bit5
bit5
bit4
bit4
bit1
bit1
bit0
bit0
SDOx
(CKE = 0)
bit7
bit7
bit3
bit3
SDOx
(CKE = 1)
SDIx
(SMP=0)
bit0
bit7
Input
Sample
(SMP=0)
SDIx
(SMP=1)
bit0
bit7
Input
Sample
(SMP=1)
SPIxIF
bit
SPIxSR to
SPIxBUF
Write Collision
(1)
Enabled
Note 1: When Write Collision is enabled (= 1), an attempt by the CPU to write to SPIxBUF will set the SWCOL status
bit, and SPIxBUF will not be written.
DS70032B-page 200
AdvanceInformation
2002 Microchip Technology Inc.
dsPIC30F
FIGURE 17-6:
SPI MODE TIMING (8-BIT SLAVE MODE WITH CKE = 0)
SSx
Optional
SCKx
(CKP = 0
CKE =0)
SCKx
(CKP = 1
CKE = 0)
Write to
SPIxBUF
bit6
bit2
bit5
bit4
bit1
bit0
bit0
SDOx
bit7
bit3
SDIx
(SMP=0)
bit7
Input
Sample
(SMP=0)
SPIxIF
bit
SPIxSR to
SPIxBUF
Write Collision
(1)
Enabled
Note 1: When Write Collision is enabled (= 1), an attempt by the CPU to write to SPIxBUF will set the SWCOL status
bit, and SPIxBUF will not be written.
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 201
dsPIC30F
FIGURE 17-7:
SPI MODE TIMING (8-BIT SLAVE MODE WITH CKE = 1)
SSx
Not Optional
SCKx
(CKP = 0
CKE =1)
SCKx
(CKP = 1
CKE = 1)
Write to
SPIxBUF
bit6
bit2
bit5
bit4
bit1
bit0
bit0
SDOx
bit7
bit7
bit3
SDIx
(SMP=0)
Input
Sample
(SMP=0)
SPIxIF
bit
SPIxSR to
SPIxBUF
Write Collision
(1)
Enabled
Note 1: When Write Collision is enabled (= 1), an attempt by the CPU to write to SPIxBUF will set the SWCOL status
bit, and SPIxBUF will not be written.
DS70032B-page 202
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pin is no longer driven. Also, the SPI module is re-
synchronized, all counters and control circuitry are
reset; therefore, when the SSx pin is asserted low
again, transmission/reception will begin at the Most
Significant bit, even if SSx had been de-asserted in the
middle of a transmit/receive (see Figure 17-8).
17.3 Slave Select Synchronization
The SSx pin allows a Synchronous Slave mode. The
SPI must be configured in SPI Slave mode, with SSx
pin control enabled (SSEN = 1). When the SSx pin is
low, transmission and reception are enabled, and the
SDOx pin is driven. When SSx pin goes high, the SDOx
FIGURE 17-8:
SLAVE SYNCHRONIZATION TIMING (MODE 16 = 0)
SSx
Optional
SCKx
(CKP = 0
CKE =0)
SCKx
(CKP = 1
CKE = 0)
Write to
SPIxBUF
bit6
bit7
bit7
bit6
bit5
bit4
SDOx
bit7
SDIx
(SMP=0)
bit7
Input
Sample
(SMP = 0)
SPIxIF
bit
SPIxSR to
SPIxBUF
17.4 SPI Operation During CPU SLEEP
Mode
17.5 SPI Operation During CPU IDLE
Mode
During SLEEP mode, the SPI module is shut-down. If
the CPU enters SLEEP mode while an SPI transaction
is in progress, then the transmission and reception is
aborted.
When the device enters IDLE mode, all clock sources
remain functional. The SPISIDL bit selects if the SPI
module will stop on IDLE or continue on IDLE. If
SPISIDL = 0, the module will continue operation when
the CPU enters IDLE mode. If SPISIDL = 1, the mod-
ule will stop when the CPU enters IDLE mode.
The transmitter and receiver will stop in SLEEP mode.
However, register contents are not affected by enter-
ing or exiting SLEEP mode.
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REGISTER 17-1: SPIXSTAT: SPI STATUS REGISTER
Upper Half:
R/W-0
SPIEN
R/W-0
R/W-0
U-0
U-0
U-0
U-0
U-0
—
SPISIDL
—
—
—
—
—
bit 15
bit 8
Lower Half:
U-0
R/W-0
HS
U-0
U-0
U-0
U-0
U-0
R-0
HS,HC
—
SPIROV
—
—
—
—
—
SBF
bit 7
bit 0
bit 15
SPIEN: SPI Enable bit
1= Enables module and configures SCK, SDOx, SDIx and SS as serial port pins
0= Disables module. All pins controlled by PORT functions. Power consumption is minimal.
Unimplemented: Read as ‘0’
SPISIDL: Stop in IDLE Mode bit
bit 14
bit 13
1= Discontinue module operation when device enters a IDLE mode
0= Continue module operation in IDLE mode
bit 12-7 Unimplemented: Read as ‘0’
bit 6
SPIROV: Receive Overflow Flag bit
1= A new byte/word is completely received, and the CPU has not read the previous data in the SPIBUF
register
0= No overflow
bit 5-1
bit 0
Unimplemented: Read as ‘0’
SBF: SPI Buffer Full Status bit (cleared in hardware when SPIBUF is read or written)
1= Receive complete, SPIBUF is full
0= Receive is not complete, SPIBUF is empty
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
HC = Cleared by Hardware
1 = bit is set
HS = Set by Hardware
0 = bit is cleared
x = bit is unknown
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REGISTER 17-2: SPIXCON: SPI CONTROL REGISTER
Upper Half:
U-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
SMP
R/W-0
CKE
—
FRMEN
SPIFSD
—
DISSDO MODE16
bit 15
bit 8
Lower Half:
R/W-0
SSEN
R/W-0
CKP
R/W-0
MSTEN
R/W-0
R/W-0
SPRE1
R/W-0
SPRE0
R/W-0
PPRE1
R/W-0
SPRE2
PPRE0
bit 7
bit 0
bit 15
bit 14
Unimplemented: Read as ‘0’
FRMEN: Framed SPI Support bit
1= Framed SPI support enabled
0= Framed SPI support disabled
bit 13
SPIFSD: Frame Sync Pulse Direction Control bit
1= Frame sync pulse input (slave)
0= Frame sync pulse output (master)
Unimplemented: Read as ‘0’
bit 12
bit 11
DISSDO: Disable SDOx Pin bit
1= SDOx pin is not used by module. Pin controlled by PORT function.
0= SDOx pin is controlled by the module
MODE16: Word/Byte Communication Select bit
1= Communication is word wide (16-bits)
0= Communication is byte wide (8-bits)
SMP: SPI Data Input Sample Phase bit
Master mode:
bit 10
bit 9
1= Input data sampled at end of data output time
0= Input data sampled at middle of data output time
Slave mode:
SMP must be cleared when SPI is used in Slave mode
bit 8
bit 7
bit 6
bit 5
bit 4-2
CKE: SPI Clock Edge Select bit
1= Transmit happens on transition from active clock state to IDLE clock state
0= Transmit happens on transition from IDLE clock state to active clock state
SSEN: Slave Select Enable bit (Slave Mode)
1= SS pin used for Slave mode
0= SS pin not used by module. Pin controlled by PORT function.
CKP: Clock Polarity Select bit
1= IDLE state for clock is a high level; active state is a low level
0= IDLE state for clock is a low level; active state is a high level
MSTEN: Master Mode Enable bit
1= Master mode
0= Slave mode
SPRE<2:0>: Secondary Prescale bits (Master Mode)
111= Secondary prescale 1:1
110= Secondary prescale 2:1
101= Reserved, do not use
100= Secondary prescale 4:1
011= Reserved, do not use
010= Secondary prescale 6:1
001= Reserved, do not use
000= Secondary prescale 8:1
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REGISTER 17-2: SPIXCON: SPI CONTROL REGISTER (Continued)
bit 1-0
PPRE<1:0>: Primary Prescale bits (Master Mode)
11= Primary prescale 1:1
10= Primary prescale 4:1
01= Primary prescale 16:1
00= Primary prescale 64:1
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
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NOTES:
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2
18.1 Operating Function Description
18.0 I C MODULE
The Inter-Integrated CircuitTM (I2CTM) module provides
complete hardware support for both Slave and Multi-
Master modes of the I2C serial communication stan-
dard, with a 16-bit interface.
The hardware fully implements all the master and slave
functions of the I2C Standard and Fast mode specifica-
tions, as well as 7 and 10-bit addressing.
Thus, the I2C module can operate either as a slave or
a master on an I2C bus.
This module offers the following key features:
• Inter-Integrated Circuit (I2C) interface
18.1.1
VARIOUS I2C MODES
• I2C interface supports both Master and Slave modes.
• I2C Slave mode supports 7 and 10 bit address.
• I2C Master mode supports 7 and 10 bit address.
The following operating modes are supported:
• I2C Slave mode (7-bit address)
• I2C Slave mode (10-bit address)
• I2C Master mode (7 or 10-bit address)
• I2C port allows bi-directional transfers between
master and slaves.
• Serial clock synchronization for I2C port can be
used as a handshake mechanism to suspend and
resume serial transfer (SCLREL control).
See the programmer’s model in Figure 18-3.
• I2C supports Multi-Master mode; detects bus colli-
sion and will arbitrate accordingly.
FIGURE 18-1:
I2C BLOCK DIAGRAM (I2C RECEIVE)
Internal
Data Bus
Read
Write
I2CRCV
Shift
SCL
SDA
Clock
I2CRSR
MSB
Match Detect
I2CADD
Addr_Match
Set, RESET
S, P bits
(I2CSTAT Reg)
START and
STOP bit Detect
Acknowledge
Generation
FIGURE 18-2:
I2C BLOCK DIAGRAM (TRANSMIT)
Internal
Data Bus
Read
Write
Shift
SCL
SDA
Clock
I2CTRN
MSB
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FIGURE 18-3:
PROGRAMMER’S MODEL
I2CRCV (8 bits)
Bit 7
Bit 7
Bit 0
I2CTRN (8 bits)
I2CBRG (9 bits)
Bit 0
Bit 0
Bit 8
I2CCON (16 bits)
I2CSTAT (16 bits)
Bit 15
Bit 15
Bit 0
Bit 0
I2CADD (10 bits)
Bit 9
Bit 0
PIN CONFIGURATION IN I2C MODE
2
18.1.2
18.2 I C Addresses
I2C has a 2-pin interface: pin SCL is clock and pin SDA
is data.
The I2CADD register contains the Slave mode
addresses. The register is a 10-bit register.
If the A10M bit (I2CCON<10>) is 0, the address is
assumed to be a 7-bit address. When an address is
received, it is compared to the Least Significant 7 bits
of the I2CADD register.
18.1.3
I2C REGISTERS
I2CCON and I2CSTAT are control and status registers,
respectively. The I2CCON register is readable and writ-
able. The lower 6 bits of I2CSTAT are read only. The
remaining bits of the I2CSTAT are read/write.
If the A10M bit is 1, the address is assumed to be a
10-bit address. When an address is received, it will be
compared with the binary value ‘1 1 1 1 0 A9 A8’
(where A9, A8 are two Most Significant bits of
I2CADD). If that value matches, the next address will
be compared with the Least Significant 8-bits of
I2CADD, as specified in the 10-bit addressing proto-
col.
I2CRSR is the shift register used for shifting data,
whereas I2CRCV is the buffer register to which data
bytes are written to or read from. This register is the
receive buffer, as shown in Figure 16-1. I2CTRN is the
transmit register to which bytes are written during a
transmit operation, as shown in Figure 16-2.
The I2CADD register holds the slave address. A status
bit, ADD10, indicates 10-bit Address mode. The
I2CBRG acts as the baud rate generator reload value.
2
18.3 I C 7-bit Slave Mode Operation
Once enabled (I2CEN = 1), the slave module will wait
for a START bit to occur (i.e., the I2C module is ‘IDLE’).
Following the detection of a START bit, 8 bits are
shifted into I2CRSR and the address is compared
against I2CADD. In 7-bit mode (A10M = 0), bits
I2CADD<6:0> are compared against I2CRSR<7:1>
and I2CRSR<0> is the R_W bit. All incoming bits are
sampled on the rising edge of SCL.
In receive operations, I2CRSR and I2CRCV together
form a double buffered receiver. When I2CRSR
receives a complete byte, it is transferred to I2CRCV
and the I2CIF interrupt pulse is generated. During
transmission, the I2CTRN is not double buffered.
Note: Following a RESTART condition in 10-bit
mode, the user only needs to match the
first 7-bit address.
If an address match occurs, an Acknowledge will be
sent, and on the falling edge of the ninth bit (ACK bit)
the I2CIF interrupt pulse is generated. The address
match does not affect the contents of the I2CRCV
buffer or the RBF bit.
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TBF Status Flag: During transmit, the TBF bit
(I2CSTAT<0>) is set when the CPU writes to I2CTRN,
and TBF is cleared in hardware when all 8 bits are
shifted out.
18.3.1
SLAVE MODE TRANSMISSION
If the R_W bit received is a ’1’, then the serial port will
go into Transmit mode. It will send ACK on the ninth bit
and then hold SCL to ’0’ until the CPU responds by writ-
ing to I2CTRN. SCL is released and 8 bits of data are
shifted out. Data bits are shifted out on the falling edge
of SCL, such that SDA is valid during SCL high (see
timing diagram). The interrupt pulse is sent on the fall-
ing edge of the ninth clock pulse, regardless of the sta-
tus of the ACK received from the master.
IWCOL Status Flag: If the user attempts to write a byte
to the I2CTRN register when TBF = 1 (i.e., I2CTRN is
still shifting out previous data byte), then IWCOL is set.
IWCOL must be cleared in software.
R_W Status Flag: Latches and holds the R_W bit
received following the last address match, which indi-
cates whether the data transfer was an input or an
output.
The ACK bit from master is latched on the ninth clock
pulse. If ACK = 1, then the Transmit mode ends and the
serial port resumes looking for another START bit.
If ACK = 0, then it will again hold SCL low until SCLREL
is set by user software. The user must write I2CTRN
prior to setting SCLREL.
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2
FIGURE 18-4:
I C SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS)
DS70032B-page 212
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RBF Status Flag: RBF is set when an address or data
byte is loaded into I2CRCV from I2CRSR. It is cleared
when I2CRCV is read.
18.3.2
SLAVE MODE RECEPTION
If the R_W bit received is a ’0’ during an address match,
then Receive mode is initiated. Incoming bits are sam-
pled on the rising edge of SCL. After 8 bits are
received, if I2CRCV is not full or I2COV is not set,
I2CRSR is transferred to I2CRCV. ACK is sent on the
ninth clock.
I2COV Status Flag: I2COV is set when 8 bits are
received into the I2CRSR, and the RBF flag has not
been cleared from a previous reception.
R_W Status Flag: Latches and holds the R_W bit
received following the last address match, which indi-
cates whether the data transfer was an input or an
output.
If the RBF flag is set, indicating that I2CRCV is still
holding data from a previous operation (RBF = 1), then
ACK is not sent; however, the interrupt pulse is gener-
ated. In the case of an overflow, the contents of the
I2CRSR are not loaded into the I2CRCV.
D_A Status Flag: Indicates whether the last byte
received was data or an address.
Note: The I2CRCV will be loaded if the I2COV
bit = 1 and the RBF flag = 0. In this case, a
read of the I2CRCV was performed, but
the user did not clear the state of the
I2COV bit before the next receive
occurred. The Acknowledge is not sent
(ACK = 1) and the I2CRCV is updated.
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FIGURE 18-5:
I C SLAVE MODE TIMING WITH STREN = 0 (RECEPTION, 7-BIT ADDRESS)
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2
18.4.1
10-BIT SLAVE TRANSMISSION
18.4 I C 10-bit Slave Mode Operation
Once a slave is addressed in this fashion with the full
10-bit address (we will refer to this state as
"PRIOR_ADDR_MATCH"), the master can begin
sending data bytes for a slave reception operation.
In 10-bit mode, the basic receive and transmit opera-
tions are the same as in the 7-bit mode. However, the
criteria for address match is more complex.
The I2C specification dictates that a slave must be
addressed for a write operation, with two address bytes
following a START bit.
18.4.2
10-BIT SLAVE RECEPTION
Once addressed, the master can, without generating a
STOP bit, generate a Repeated START bit and reset
the high byte of the address and R_W = 1, thus initiat-
ing a slave transmit operation.
The A10M bit is a control bit that signifies that the
address in I2CADD is a 10-bit address rather than a
7-bit address. The address detection protocol for the
first byte of a message address is identical for 7-bit
and 10-bit messages, but the bits being compared are
different.
I2CADD holds the entire 10-bit address. Upon receiv-
ing an address following a START bit, I2CRSR <7:3> is
compared against a literal ‘11110’ (the default 10-bit
address) and I2CRSR<2:1> are compared against
I2CADD<9:8>. If a match occurs and only if R_W = 0,
the interrupt pulse is sent. The ADD10 bit will be
cleared to indicate a partial address match. If a match
fails or R_W = 1, the ADD10 bit is cleared and the mod-
ule returns to the IDLE state.
Then, the low byte of the address is received and com-
pared against I2CADD<7:0>. If an address match
occurs, the interrupt pulse is generated and the ADD10
bit is set, indicating a complete 10-bit address match. If
an address match did not occur, the ADD10 bit is
cleared and the module returns to the IDLE state.
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FIGURE 18-6:
I C SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)
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FIGURE 18-7:
I2C SLAVE MODE TIMING WITH STREN = 0 (RECEPTION, 10-BIT ADDRESS)
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18.5.3
CLOCK STRETCHING DURING
7-BIT ADDRESSING (STREN = 1)
18.5 Automatic Clock Stretch
In the Slave modes, the module can synchronize
buffer reads and write to the master device by clock
stretching.
When the STREN bit is set in Slave Receive mode,
the SCL line is held low when the buffer register is full.
The method for stretching the SCL output is the same
for both 7 and 10-bit addressing modes.
18.5.1
TRANSMIT MODE CLOCK
STRETCHING
Clock stretching takes place following the ninth clock
of the receive sequence. On the falling edge of the
ninth clock at the end of the ACK sequence, if the RBF
bit is set, the SCLREL bit is automatically cleared,
forcing the SCL output to be held low. The user’s ISR
must set the SCLREL bit before reception is allowed to
continue. By holding the SCL line low, the user has
time to service the ISR and read the contents of the
I2CRCV before the master device can initiate another
receive sequence. This will prevent buffer overruns
from occurring.
Both 10-bit and 7-bit Transmit modes implement clock
stretching by asserting the SCLREL bit after the falling
edge of the ninth clock if the TBF bit is cleared, indicat-
ing the buffer is empty. This occurs regardless of the
state of the STREN bit.
In Slave Transmit modes, clock stretching is always
performed, irrespective of the STREN bit.
Clock synchronization takes place following the ninth
clock of the transmit sequence. If the device samples
an ACK on the falling edge of the ninth clock, and if the
TBF bit is still clear, then the SCLREL bit is automati-
cally cleared. The SCLREL being cleared to ‘0’ will
assert the SCL line low. The user’s ISR must set the
SCLREL bit before transmission is allowed to con-
tinue. By holding the SCL line low, the user has time to
service the ISR and load the contents of the I2CTRN
before the master device can initiate another transmit
sequence.
Note 1: If the user reads the contents of the
I2CRCV, clearing the RBF bit before the
falling edge of the ninth clock, the
SCLREL bit will not be cleared and clock
stretching will not occur.
2: The SCLREL bit can be set in software,
regardless of the state of the RBF bit. The
user should be careful to clear the RBF bit
in the ISR before the next receive
sequence in order to prevent an overflow
condition.
Note 1: If the user loads the contents of I2CTRN,
setting the TBF bit before the falling edge
of the ninth clock, the SCLREL bit will not
be cleared and clock stretching will not
occur.
18.5.4
CLOCK STRETCHING DURING
10-BIT ADDRESSING (STREN = 1)
2: The SCLREL bit can be set in software,
Clock stretching takes place automatically during the
addressing sequence. Because this module has a reg-
ister for the entire address, it is not necessary for the
protocol to wait for the address to be updated.
regardless of the state of the TBF bit.
18.5.2
RECEIVE MODE CLOCK
STRETCHING
After the address phase is complete, clock stretching
will occur on each data receive or transmit sequence
as is described earlier.
The STREN bit in the I2CCON register can be used to
enable clock stretching in Slave Receive mode. When
the STREN bit is set, the SCL pin will be held low at
the end of each data receive sequence.
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2
FIGURE 18-8:
I C SLAVE MODE TIMING WITH STREN = 1 (RECEPTION, 7-BIT ADDRESS)
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FIGURE 18-9:
I2C SLAVE MODE TIMING STREN = 1 (RECEPTION, 10-BIT ADDRESS)
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18.6 Software Controlled Clock
Stretching (STREN = 1)
18.10 General Call Address Support
The general call address can address all devices.
When this address is used, all devices should, in the-
ory, respond with an Acknowledge.
When the STREN bit is ‘1’, the SCLREL bit may be
cleared by software to allow software to control the
clock stretching. The logic will synchronize writes to
the SCLREL bit with the SCL clock. Clearing the
SCLREL bit will not assert the SCL output until the
module detects a falling edge on the SCL output and
SCL is sampled low. If the SCLREL bit is cleared by
the user while the SCL line is already sampled low, the
SCL output will be asserted. The SCL output will
remain low until the SCLREL bit is set, and all other
devices on the I2C bus have de-asserted SCL. This
ensures that a write to the SCLREL bit will not violate
the minimum high time requirement for SCL.
The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all 0’s with R_W = 0.
The general call address is recognized when the Gen-
eral Call Enable bit (GCEN) is set (I2CCON<15> = 1).
Following a START bit detect, 8 bits are shifted into
I2CRSR and the address is compared against
I2CADD, and is also compared to the general call
address, which is fixed in hardware.
If a general call address match occurs, the I2CRSR is
transferred to the I2CRCV after the eighth clock, the
RBF flag is set, and on the falling edge of the ninth bit
(ACK bit), the I2CIF interrupt is set.
If the STREN bit is ‘0’, a software write to the SCLREL
bit will be disregarded and have no effect on the
SCLREL bit.
When the interrupt is serviced, the source for the inter-
rupt can be checked by reading the contents of the
I2CRCV to determine if the address was device
specific, or a general call address.
18.7 Interrupts
The I2C module generates two interrupt flags, I2CIF
(I2C Transfer Complete Interrupt Flag) and BCLIF (I2C
Bus Collision Interrupt Flag). The I2CIF interrupt flag is
pulsed high for one TCY on the falling edge of the 9th
clock pulse. The BCLIF interrupt flag is pulsed high for
one TCY when a bus collision event is detected.
2
18.11 I C Master Mode Support
In Master mode, the user has six options.
• Assert a START condition on SDA and SCL.
• Assert a RESTART condition on SDA and SCL.
18.8 Slope Control
• Write to the I2CTRN register initiating transmis-
sion of data/address.
The I2C standard requires slope control on the SDA
and SCL signals for Fast Mode (400 kHz). The control
bit, DISSLW, enables the user to disable slew rate con-
trol, if desired. It is necessary to disable the slew rate
control for 1 MHz mode.
• Generate a STOP condition on SDA and SCL.
• Configure the I2C port to receive data.
• Generate an Acknowledge condition at the end of
a received byte of data.
18.9 IPMI Support
2
18.12 I C Master Mode Operation
The control bit IPMIEN enables the module to support
Intelligent Peripheral Management Interface (IPMI).
When this bit is set, the module accepts and acts upon
all addresses.
The master device generates all the serial clock pulses
and the START and STOP conditions. A transfer is
ended with a STOP condition or with a Repeated
START condition. Since the Repeated START condi-
tion is also the beginning of the next serial transfer, the
I2C bus will not be released.
18.9.1
SLEEP OPERATION
The control bit, SLPEN, dictates the operation of the
I2C module when a SLEEP event occurs. With SLPEN
= 0 (RESET state), the module continues operation in
SLEEP mode, assuming support signals are provided.
Interrupts will be generated at the appropriate time.
When SLPEN = 1, the module discontinues all func-
tions when a SLEEP mode is entered. Interrupts are
not generated while SLEEP is active.
In Master Transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the data direction bit. In
this case, the data direction bit (R_W) is logic 0. Serial
data is transmitted 8 bits at a time. After each byte is
transmitted, an Acknowledge bit is received. START
and STOP conditions are output to indicate the begin-
ning and the end of a serial transfer.
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In Master Receive mode, the first byte transmitted con-
tains the slave address of the transmitting device (7
bits) and the data direction bit. In this case, the data
direction bit (R_W) is logic 1. Thus, the first byte trans-
mitted is a 7-bit slave address, followed by a ‘1’ to indi-
cate receive bit. Serial data is received via SDA while
SCL outputs the serial clock. Serial data is received 8
bits at a time. After each byte is received, an Acknowl-
edge bit is transmitted. START and STOP conditions
indicate the beginning and end of transmission.
The baud rate generator used for I2C mode operation
is now used to set the SCL clock frequency for either
100 kHz or 400 kHz I2C operation. 1 MHz operation is
also supported. The baud rate generator re-load value
is contained in the I2CBRG register. The baud rate
generator will automatically begin counting on a write to
the I2CTRN. Once the given operation is complete (i.e.,
transmission of the last data bit is followed by ACK) the
internal clock will automatically stop counting and the
SCL pin will remain in its last state.
The Transmit Status Flag, TRSTAT (I2CSTAT<14>),
indicates that a master transmit is in progress.
TBF Status Flag:
In Transmit mode, the TBF bit (I2CSTAT<0>) is set
when the CPU writes to I2CTRN and is cleared when
all 8 bits are shifted out.
IWCOL Status Flag:
If the user writes the I2CTRN when a transmit is
already in progress, then IWCOL is set and the con-
tents of the buffer are unchanged (the write doesn’t
occur). It must be cleared in software.
ACKSTAT Status Flag:
In Transmit mode, the ACKSTAT bit (I2CSTAT<15>) is
cleared when the slave has sent an Acknowledge
(ACK = 0), and is set when the slave does Not
Acknowledge (ACK = 1). A slave sends an Acknowl-
edge when it has recognized its address, or when the
slave has properly received its data.
The D_A and R_W status bits are not applicable in
Master mode.
18.12.1 I2C MASTER MODE
TRANSMISSION
Transmission of a data byte, a 7 bit address, or the sec-
ond half of a 10 bit address is accomplished by simply
writing a value to I2CTRN register. The user should
only write to I2CTRN when the module is in a WAIT
state. This action will set the buffer full flag (TBF) and
allow the baud rate generator to begin counting and
start the next transmission. Each bit of address/data
will be shifted out onto the SDA pin after the falling
edge of SCL is asserted. SCL is held low for 1 baud
rate generator rollover count (TBRG). Data should be
valid before SCL is released high. When the SCL pin is
released high, it is held high for TBRG. The data on the
SDA pin must remain stable for that duration and some
hold time after the next falling edge of SCL. After the
eighth bit is shifted out (the falling edge of the eighth
clock), the TBF flag is cleared and the master releases
SDA, allowing the slave device being addressed to
respond with an ACK bit during the ninth bit time, if an
address match occurs or if data was received properly.
If the master receives an Acknowledge, the Acknowl-
edge status bit (ACKSTAT) is cleared. If not, the bit is
set. After the ninth clock the I2CIF is set, and the mas-
ter clock (baud rate generator) is suspended until the
next event, thus leaving SCL low and SDA unchanged
(see Figure 18-10).
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FIGURE 18-10:
I C MASTER MODE TIMING (TRANSMISSION, 7- OR 10-BIT ADDRESS)
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18.12.2 I2C MASTER MODE RECEPTION
RBF Status Flag:
In receive operation, RBF is set when an address or
data byte is loaded into I2CRCV from I2CRSR. It is
cleared when I2CRCV is read.
Master mode reception is enabled by programming the
receive enable (RCEN) bit (I2CCON<11>). The I2C
module must be IDLE before the RCEN bit is set, oth-
erwise the RCEN bit will be disregarded. The baud rate
generator begins counting, and on each rollover, the
state of the SCL pin changes (high to low/low to high),
and data is shifted in to the I2CRSR on the rising edge
of each clock. After the falling edge of the eighth clock,
the receive enable flag is automatically cleared, the
contents of the I2CRSR are loaded into the I2CRCV,
the RBF and I2CIF bits are set, and the baud rate gen-
erator is suspended from counting, holding SCL low.
The I2C is now in IDLE state, awaiting the next com-
mand. When the I2CRCV is read by the CPU, the RBF
flag is automatically cleared. The user can then send
an Acknowledge bit at the end of reception, by setting
the Acknowledge sequence enable (ACKEN) bit
(I2CCON<12>).
I2COV Status Flag:
In receive operation, I2COV is set when 8 bits are
received into the I2CRSR, and the RBF flag is already
set from a previous reception.
IWCOL Status Flag:
If the user writes the I2CTRN when a receive is already
in progress, then IWCOL is set and the contents of the
buffer are unchanged (the write does not occur).
The D_A and R_W status bits are not applicable in
Master mode.
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2
FIGURE 18-11:
I C MASTER MODE TIMING (RECEPTION, 7 BIT ADDRESS)
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The Master will continue to monitor the SDA and SCL
pins, and if a STOP condition occurs, the I2CIF bit will
be set.
18.12.3 BAUD RATE GENERATOR
In I2C Master mode, the reload value for the BRG is
located in the I2CBRG register. When the BRG is
loaded with this value, the BRG counts down to 0 and
stops until another reload has taken place. In I2C Mas-
ter mode, the BRG is not reloaded automatically. If
clock arbitration is taking place, for instance, the BRG
is reloaded when the SCL pin is sampled high.
A write to the I2CTRN will start the transmission of data
at the first data bit, regardless of where the transmitter
left off when bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of START and STOP conditions allows the
determination of when the bus is free. Control of the I2C
bus can be taken when the P bit is set in the I2CSTAT reg-
ister, or the bus is IDLE and the S and P bits are cleared.
EQUATION 18-1: SERIAL CLOCK RATE
FSCK = (FOSC/2) / (I2CBRG * 2)
18.12.5.1 Bus Collision During a START
Condition
18.12.4 CLOCK ARBITRATION
During a START condition, a bus collision occurs if:
Clock arbitration occurs when the master de-asserts
the SCL pin (SCL allowed to float high) during any
receive, transmit, or RESTART/STOP condition. When
the SCL pin is allowed to float high, the baud rate gen-
erator (BRG) is suspended from counting until the SCL
pin is actually sampled high. When the SCL pin is sam-
pled high, the baud rate generator is reloaded with the
contents of I2CBRG and begins counting. This guaran-
tees that the SCL high time will always be at least one
BRG rollover count, in the event that the clock is held
low by an external device.
1. SDA or SCL are sampled low at the beginning of
the START condition.
2. SCL is sampled low before SDA is asserted low.
18.12.5.2 Bus Collision During a RESTART
Condition
During a RESTART condition, bus collision occurs if:
1. A 0 is sampled on SDA, when SCL goes from 0
to 1.
2. SCL goes low before SDA is asserted low, indi-
cating that another master is attempting to trans-
mit a data 1.
18.12.5 MULTI-MASTER COMMUNICATION,
BUS COLLISION, AND BUS
ARBITRATION
18.12.5.3 Bus Collision During a STOP
Condition
Multi-Master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a 1 on SDA, by letting SDA float high and
another master asserts a 0. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a 1 and the data sampled on the SDA pin = 0,
then a bus collision has taken place. The master will set
the Bus Collision Interrupt (BCLIF) pulse and reset the
master portion of the I2C port to its IDLE state.
Bus collision occurs during a STOP condition if:
1. After the SDA pin has been de-asserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
2. After the SCL pin is de-asserted, SCL is sam-
pled low before SDA goes high.
2
18.13 I C Module Operation During CPU
SLEEP and IDLE Modes
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the TBF flag is
cleared, the SDA and SCL lines are de-asserted, and
the I2CTRN can now be written to. When the user ser-
vices the bus collision Interrupt Service Routine, and if
the I2C bus is free (i.e., the P bit is set), the user can
18.13.1 I2C OPERATION DURING CPU
SLEEP MODE
When the device enters SLEEP mode, all Q clock
sources to the module are shut-down and stay at logic
‘0’. If SLEEP occurs in the middle of a transmission,
and the state machine is partially into a transmission as
the clocks stop, then the transmission is aborted. Sim-
ilarly, if SLEEP occurs in the middle of a reception, then
the reception is aborted.
resume communication by asserting
condition.
a
START
If a START, RESTART, STOP, or Acknowledge condi-
tion was in progress when the bus collision occurred,
the condition is aborted, the SDA and SCL lines are de-
asserted, and the respective control bits in the I2CCON
register are cleared to 0. When the user services the
bus collision Interrupt Service Routine, and if the I2C
bus is free, the user can resume communication by
asserting a START condition.
18.13.2 I2C OPERATION DURING CPU IDLE
MODE
For the I2C, the I2CSIDL bit selects if the module will
stop on IDLE or continue on IDLE. If I2CSIDL = 0, the
module will continue operation on assertion of the IDLE
mode. If I2CSIDL = 1, the module will stop on IDLE.
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REGISTER 18-1: I2CSTAT: I2C STATUS REGISTER
Upper Half:
R-0
R-0
U-0
U-0
U-0
U-0
R-0
R/W-0
HS, HC
HS, HC
HS, HC
AKSTAT
bit 15
TRSTAT
—
—
—
BCL
GCSTAT
ADD10
bit 8
Lower Half:
R/W-0
HS
R/W-0
HS
R-0
HS, HC
R-0
HS, HC
R-0
HS, HC
R-0
HS, HC
R-0
HS, HC
R-0
HS, HC
IWCOL
I2COV
D_A
P
S
R_W
RBF
TBF
bit 7
bit 0
bit 15
bit 14
AKSTAT: Acknowledge Status bit (In I2C master mode only. Applicable to Master Transmit mode.)
1= Acknowledge was not received from slave
0= Acknowledge was received from slave.
TRSTAT: Transmit Status bit (In I2C master mode only. Applicable to Master Transmit mode.)
1= Master transmit is in progress (8 bits + ACK)
0= Master transmit is not in progress.
Or’ing this bit with SEN, RCEN, PEN and AKEN will indicate if the I2C master circuitry is active.
bit 13-11 Unimplemented: Read as ‘0’
bit 10
bit 9
bit 8
bit 7
BCL: Master Bus Collision Detect bit (cleared when the I2C module is disabled, I2CEN = 0)
1= A bus collision has been detected during a master operation
0= No collision
GCSTAT: General Call Status bit
1= General call address was received
0= General call address was not received
ADD10: 10-bit Address Status bit
1= 10-bit address was matched
0= 10-bit address was not matched
IWCOL: Write Collision Detect bit
1= An attempt to write the I2CTRN register failed because the I2C module is busy (must be cleared
in software)
0= No collision
bit 6
I2COV: Receive Overflow Flag bit
1= A byte is received while the I2CRCV register is still holding the previous byte. I2COV is a “don’t care”
in Transmit mode. I2COV must be cleared in software in either mode.
0= No overflow
bit 5
bit 4
D_A: Data/Address bit (valid only for Slave mode operation)
1= Indicates that the last byte received was data
0= Indicates that the last byte received was address
P: STOP bit (This bit is updated when START, RESTART or STOP detected. Cleared when the I2C
module is disabled, I2CEN = 0.)
1= Indicates that a STOP bit has been detected last
0= STOP bit was not detected last
bit 3
bit 2
S: START bit (This bit is updated when START, RESTART or STOP detected. Cleared when the I2C
module is disabled, I2CEN = 0.)
1= Indicates that a START (or RESTART) bit has been detected last
0= START bit was not detected last
R_W: Read/Write bit Information (valid only for Slave mode operation)
1= Read - indicates data transfer is output from slave
0= Write - indicates data transfer is input to slave
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REGISTER 18-1: I2CSTAT: I2C STATUS REGISTER (Continued)
bit 1
bit 0
RBF: Receive Buffer Full Status bit (cleared by reading I2CRCV)
1= Receive complete, I2CRCV is full
0= Receive not complete, I2CRCV is empty
TBF: Transmit Buffer Full Status bit
1= Transmit in progress, I2CTRN is full (8 bits)
0= Transmit complete, I2CTRN is empty
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
HC = Cleared by Hardware
1 = bit is set
HS = Set by Hardware
0 = bit is cleared
-n = Value at POR
x = bit is unknown
x = bit is unknown
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REGISTER 18-2: I2CCON: I2C CONTROL REGISTER
Upper Half:
R/W-0
I2CEN
R/W-0
R/W-0
R/W-0
HC
R/W-0
U-0
R/W-0
R/W-0
SMEN
—
I2CSIDL
SCLREL
IPMIEN
A10M
DISSLW
bit 15
bit 8
Lower Half:
R/W-0
R/W-0
R/W-0
AKDT
R/W-0
HC
R/W-0
HC
R/W-0
HC
R/W-0
HC
R/W-0
HC
GCEN
STREN
AKEN
RCEN
PEN
RSEN
SEN
bit 7
bit 0
bit 15
I2CEN: I2C Enable bit (only writable from software)
1= Enables the I2C module and configures the SDA and SCL pins as serial port pins
0= Disables I2C module. All I2C pins are controlled by PORT functions. Power consumption is minimal.
Unimplemented: Read as ‘0’
bit 14
bit 13
I2CSIDL: Stop in IDLE Mode bit
1= Discontinue module operation when device enters a IDLE mode
0= Continue module operation in IDLE mode
bit 12
SCLREL: SCL Release Control bit (in I2C Slave mode only)
If STREN = 0:
1= Release clock
0= Force clock low (clock stretch). Automatically cleared to 0 at beginning of slave transmission.
If STREN = 1:
1= Release clock
0= Holds clock low (clock stretch). (User may program this bit to 0, will clock stretch at next SCL low.)
Automatically cleared to 0 at beginning of slave transmission.
Automatically cleared to 0 at end of slave reception.
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
IPMIEN: Intelligent Peripheral Management Interface (IPMI) Enable bit
1= Enable IPMI Support mode. All addresses Acknowledged.
0= IPMI mode not enabled
A10M: Indicates a 10-bit Slave Address bit
1= I2CADD is a 10-bit slave address
0= I2CADD is a 7-bit slave address
DISSLW: Disable Slew Rate Control bit
1= Slew rate control disabled for Standard Speed mode (100 kHZ). (Also disabled for 1 MHz mode.)
0= Slew rate control enabled for High Speed mode (400 kHz)
SMEN: SM bus Input Levels bit
1= Enable input logic so that thresholds are compliant with SM bus specification
0= Disable SM bus specific inputs
GCEN: General Call Enable bit (in I2C Slave mode only)
1= Enable interrupt when a general call address is received in the I2CSR. (Module is enabled for reception.)
0= General call address disabled.
STREN: SCL Clock Stretch Enable bit (in I2C slave mode only, used in conjunction with SCLREL bit)
1= Enable clock stretching
0= Disable clock stretching.
bit 5
bit 4
AKDT: Acknowledge Data bit (In I2C Master mode only. Applicable during master receive.)
Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
AKEN: Acknowledge Sequence Enable bit (In I2C Master mode only. Applicable during master receive.)
1= Initiate Acknowledge sequence on SDA and SCL pins, and transmit AKDT data bit.
Automatically cleared by hardware at end of master Acknowledge sequence.
0= Acknowledge sequence IDLE
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REGISTER 18-2: I2CCON: I2C CONTROL REGISTER (Continued)
bit 3
bit 2
RCEN: Receive Enable bit (in I2C Master mode only)
1= Enables Receive mode for I2C. Automatically cleared by hardware at end eighth bit of receive data byte.
0= Receive sequence not in progress
PEN: STOP Condition Enable bit (in I2C Master mode only)
1= Initiate STOP condition on SDA and SCL pins. Automatically cleared by hardware at end of
master STOP sequence.
0= STOP condition IDLE
bit 1
bit 0
RSEN: RESTART Condition Enabled bit (in I2C Master mode only)
1 = Initiate RESTART condition on SDA and SCL pins. Automatically cleared by hardware at end of master
RESTART sequence.
0= RESTART condition IDLE
SEN: START Condition Enabled bit (in I2C Master mode only)
1 = Initiate START condition on SDA and SCL pins. Automatically cleared by hardware at end of
master START sequence.
0 = START condition IDLE
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
HC = Cleared by Hardware
1 = bit is set
HS = Set by Hardware
0 = bit is cleared
x = bit is unknown
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NOTES:
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19.1 UART Module Overview
19.0 UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART) MODULE
The key features of the UART module are:
• Full-duplex, 8 or 9-bit data transmission
• Even, Odd or No Parity options (for 8-bit data)
• One or two STOP bits
This section describes the Universal Asynchronous
Receiver/Transmitter Communications module.
• Fully integrated Baud Rate Generator with 16-bit
prescaler
• Baud rates range from 38 bps to 1.875 Mbps at
30 MIPS
• 4-deep transmit data buffer
• 4-deep receive data buffer
• Parity, Framing and Buffer Overrun error detection
• Support for Interrupt only on Address Detect
(9th bit = 1)
• Separate Transmit and Receive Interrupts
• Loopback mode for diagnostic support
FIGURE 19-1:
UART TRANSMITTER BLOCK DIAGRAM
Internal Data Bus
Control and Status bits
Write
Write
UTX8
UxTXREG Low Byte
Transmit Control
– Control TSR
– Control Buffer
– Generate Flags
– Generate Interrupt
Load TSR
UxTXIF
UTXBRK
Data
UxTX
Transmit Shift Register (UxTSR)
‘0’ (START)
‘1’ (STOP)
UxTX
16X Baud Clock
from Baud Rate
Generator
Parity
Generator
16 Divider
Parity
Control
Signals
Note: x = 1 or 2.
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FIGURE 19-2:
UART RECEIVER BLOCK DIAGRAM
Internal Data Bus
16
Read
Write
Read Read
Write
UxMODE
UxSTA
UxRXREG Low Byte
URX8
Receive Buffer Control
– Generate Flags
– Generate Interrupt
– Shift Data Characters
8-9
LPBACK
From UxTX
UxRX
Load RSR
to Buffer
Receive Shift Register
(UxRSR)
1
0
Control
Signals
· START bit Detect
· Parity Check
· STOP bit Detect
· Shift Clock Generation
· Wake Logic
16 Divider
16X Baud Clock from
Baud Rate Generator
UxRXIF
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19.2 Enabling and Setting Up UART
19.2.1 ENABLING THE UART
19.3 Transmitting Data
19.3.1
TRANSMITTING IN 8-BIT DATA
MODE
The UART module is enabled by setting the UARTEN
bit in the UxMODE register (where x = 1 or 2). Once
enabled, the UxTX and UxRX pins are configured as an
output and an input respectively, overriding the TRIS
and LATCH register bit settings for the corresponding
I/O port pin. The UxTX pin is at logic ‘1’ when no trans-
mission is taking place.
The following steps must be performed in order to
transmit 8-bit data:
1. Set up the UART:
First, the data length, parity and number of
STOP bits must be selected, and then, the
Transmit and Receive Interrupt enable and pri-
ority bits are setup in the UxMODE and UxSTA
registers. Also, the appropriate baud rate value
must be written to the UxBRG register.
19.2.2
DISABLING THE UART
The UART module is disabled by clearing the
UARTEN bit in the UxMODE register. This is the
default state after any RESET. If the UART is disabled,
all I/O pins operate as port pins, under the control of
the latch and TRIS bits of the corresponding port pins.
2. Enable the UART by setting the UARTEN bit
(UxMODE<15>).
3. Set the UTXEN bit (UxSTA<10>), thereby
enabling a transmission.
Disabling the UART module resets the buffers to
empty states. Any data characters in the buffers are
lost, and the baud rate counter is reset.
4. Write the data byte to be transmitted, to the
lower byte of UxTXREG. The value will be trans-
ferred to Transmit Shift register (UxTSR) imme-
diately and the serial bit stream will start shifting
out during the next rising edge of the baud clock.
All error and status flags associated with the UART
module are reset when the module is disabled. The
URXDA, OERR, FERR, PERR, UTXEN, UTXBRK and
UTXBF bits are cleared, whereas RIDLE and TRMT
are set. Other control bits, including ADDEN,
URXISEL<1:0>, UTXISEL, as well as the UxMODE
and UxBRG registers, are not affected.
5. A Transmit interrupt will be generated depend-
ing on the value of the interrupt control bit
UTXISEL (UxSTA<15>).
Alternatively, the data byte may be written while
UTXEN = 0, following which, the user may set UTXEN.
This will cause the serial bit stream to begin immedi-
ately because the baud clock will start from a cleared
state.
Clearing the UARTEN bit while the UART is active will
abort all pending transmissions and receptions and
reset the module as defined above. Re-enabling the
UART will restart the UART in the same configuration.
19.3.2
TRANSMITTING IN 9-BIT DATA
MODE
19.2.3
ALTERNATE I/O
The alternate I/O function is enabled by setting the
ALTIO bit (UxMODE<10>). If ALTIO = 1, the UxATX
and UxARX pins (alternate transmit and alternate
receive pins, respectively) are used by the UART mod-
ule, instead of the UxTX and UxRX pins. If ALTIO = 0,
the UxTX and UxRX pins are used by the UART
module.
The sequence of steps involved in the transmission of
9-bit data is similar to 8-bit transmission, except that a
16-bit data word (of which the upper 7 bits are always
clear) must be written to the UxTXREG register.
19.3.3
TRANSMIT BUFFER (UXTXB)
The transmit buffer is 9-bits wide and 4 characters
deep. Including the Transmit Shift Register (UxTSR),
the user effectively has a 5-deep FIFO (First In First
Out) buffer. The UTXBF status bit (UxSTA<9>) indi-
cates whether the transmit buffer is full.
19.2.4
SETTING UP DATA, PARITY AND
STOP BIT SELECTIONS
Control bits PDSEL<1:0> in the UxSTA register are
used to select the data length and parity used in the
transmission. The data length may either be 8-bits with
even, odd or no parity, or 9-bits with no parity.
If a user attempts to write to a full buffer, the new data
will not be accepted into the FIFO, and no data shift
will occur within the buffer. This enables recovery from
a buffer overrun condition.
The STSEL bit determines whether one or two STOP
bits will be used during data transmission.
The FIFO is reset during any device RESET, but is not
affected when the device enters a Power Saving mode,
or wakes up from a Power Saving mode.
The default (Power-on) setting of the UART is 8 bits, no
parity, 1 STOP bit (typically represented as 8, N, 1).
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19.3.4
TRANSMIT INTERRUPT
19.4.2
RECEIVE BUFFER (UXRXB)
The transmit interrupt flag (U1TXIF or U2TXIF) is
located in the corresponding interrupt flag register.
The receive buffer is 4-deep. Including the Receive
Shift register (UxRSR), the user effectively has a
5-deep FIFO (First In First Out) buffer.
The transmitter generates an edge to set the UxTXIF
bit. The condition of generating the interrupt depends
on UTXISEL control bit.
URXDA (UxSTA<0>) = 1 indicates that the receive
buffer has data available. URXDA = 0 implies that the
buffer is empty. If a user attempts to read an empty
buffer, the old values in the buffer will be read, and no
data shift will occur within the FIFO.
a) If UTXISEL = 0, an interrupt is generated when
a word is transferred from the Transmit buffer to
Transmit Shift register (UxTSR). This implies
that the transmit buffer has at least one empty
word.
The FIFO is reset during any device RESET. It is not
affected when the device enters a power-saving mode
or wakes up from a power-saving mode.
b) If UTXISEL = 1, an interrupt is generated when
a word is transferred from the Transmit buffer to
Transmit Shift register (UxTSR) and the Trans-
mit buffer is empty.
19.4.3
RECEIVE INTERRUPT
The receive interrupt flag (U1RXIF or U2RXIF) can be
read from the corresponding interrupt flag register. The
interrupt flag is set by an edge generated by the
receiver. The condition for setting the receive interrupt
flag depends on the settings specified by the
URXISEL<1:0> (UxSTA<7:6>) control bits.
Switching between the two interrupt modes during
operation is possible and sometimes offers more
flexibility.
19.3.5
TRANSMIT BREAK
a) If URXISEL<1:0> = 00 or 01, an interrupt is
generated every time a data word is transferred
from the Receive Shift Register (UxRSR) to the
Receive Buffer. There may be one or more char-
acters in the receive buffer.
Setting the UTXBRK bit (UxSTA<11>) will cause the
UxTX line to be driven to logic ‘0’. The UTXBRK bit
overrides all transmission activity. Therefore, the user
should generally wait for the transmitter to be IDLE
before setting UTXBRK.
b) If URXISEL<1:0> = 10, an interrupt is generated
when a word is transferred from the Receive
Shift Register (UxRSR) to the Receive Buffer
and as a result, the Receive Buffer contains 3 or
4 characters.
To send a break character, the UTXBRK bit must be
set by software and must remain set for a minimum of
13 baud clock cycles. The UTXBRK bit is then cleared
by software to generate STOP bits. The user must wait
for a duration of at least one or two baud clock cycles
in order to ensure a valid STOP bit(s), before reloading
the UxTXB or starting other transmitter activity. Trans-
mission of a break character does not generate a
transmit interrupt.
c) If URXISEL<1:0> = 11, an interrupt is set when
a word is transferred from the Receive Shift
Register (UxRSR) to the Receive Buffer and as
a result, the Receive Buffer contains 4 charac-
ters (i.e., becomes full).
19.4 Receiving Data
Switching between the interrupt modes during opera-
tion is possible, though generally not advisable during
normal operation.
19.4.1
RECEIVING IN 8-BIT OR 9-BIT DATA
MODE
19.5 Reception Error Handling
The following steps must be performed while receiving
8-bit or 9-bit data:
19.5.1
RECEIVE BUFFER OVERRUN
ERROR (OERR BIT)
1. Set up the UART (see Section 19.3.1).
2. Enable the UART (see Section 19.3.1).
The OERR bit (UxSTA<1>) is set if all of the following
conditions occur:
3. A receive interrupt will be generated when one
or more data bytes have been received,
depending on the receive interrupt settings
specified by the URXISEL bits (UxSTA<7:6>).
a) The receive buffer is full.
b) The receive shift register is full, but unable to
transfer the character to the receive buffer.
4. Read the OERR bit to determine if an overrun
error has occurred. The OERR bit must be reset
in software.
c) The STOP bit of the character in the UxRSR is
detected, indicating that the UxRSR needs to
transfer the character to the buffer.
5. Read the received data from UxRXREG. The act
of reading UxRXREG will move the next word to
the top of the receive FIFO, and the PERR and
FERR values will be updated.
Once OERR is set, no further data is shifted in UxRSR
(until the OERR bit is cleared in software or a RESET
occurs). The data held in UxRSR and UxRXREG
remain valid.
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19.5.2
FRAMING ERROR (FERR)
19.6 Address Detect Mode
The FERR bit (UxSTA<2>) is set if a ‘0’ is detected
instead of a STOP bit. If two STOP bits are selected,
both STOP bits must be ‘1’, otherwise FERR will be set.
The read only FERR bit is buffered along with the
received data. It is cleared on any RESET.
Setting the ADDEN bit (UxSTA<5>) enables this spe-
cial mode, in which a 9th bit (URX8) value of ‘1’ identi-
fies the received word as an address rather than data.
This mode is only applicable for 9-bit data transmis-
sion. The URXISEL control bit does not have any
impact on interrupt generation in this mode, since an
interrupt (if enabled) will be generated if the received
word has the 9th bit set.
19.5.3
PARITY ERROR (PERR)
The PERR bit (UxSTA<3>) is set if the parity of the
received word is incorrect. This error bit is applicable
only if a Parity mode (odd or even) is selected. The
read only PERR bit is buffered along with the received
data bytes. It is cleared on any RESET.
19.7 Loopback Mode
Setting the LPBACK bit enables this special mode, in
which the UxTX pin is internally connected to the UxRX
pin. When configured for the loopback mode, the UxRX
pin is disconnected from the internal UART receive
logic. However, the UxTX pin still functions as in a nor-
mal operation.
19.5.4
IDLE STATUS
When the receiver is active, i.e., between the initial
detection of the START bit and the completion of the
STOP bit, the RIDLE bit (UxSTA<4>) is ‘0’. Between
the completion of the STOP bit and detection of the
next START bit, the RIDLE bit is ‘1’, indicating that the
UART is IDLE.
To select this mode:
a) Configure UART for desired mode of operation.
a) Set LPBACK = 1 to enable Loopback mode.
b) Enable transmission as defined in Section 19.3.
19.5.5
RECEIVE BREAK
19.8 Baud Rate Generator
The receiver will count and expect a certain number of
bit times based on the values programmed in the
PDSEL (UxMODE<2:1>) and STSEL (UxMODE<0>)
bits.
The UART has a 16-bit baud rate generator to allow
maximum flexibility in baud rate generation. The baud
rate generator register (UxBRG) is readable and writ-
able. The baud rate is computed as follows:
If the break is much longer than 13 bit times, the
reception is considered complete after the number of
bit times specified by PDSEL and STSEL. The
URXDA bit is set, FERR is set, zeros are loaded into
the receive FIFO, interrupts are generated if appropri-
ate, and the RIDLE bit is set.
BRG = 16-bit value held in UxBRG register (0 through
65535)
fCY = Instruction Clock Rate (1/TCY)
Then Baud Rate = fCY / (16* (BRG + 1) )
Therefore, maximum baud rate possible is = fCY /16
(If BRG = 0),
When the module receives a long break signal and the
receiver has detected the START bit, the data bits and
the invalid STOP bit (which sets the FERR), the
receiver must wait for a valid STOP bit before looking
for the next START bit. It cannot assume that the
break condition on the line is the next START bit.
and minimum baud rate possible is = fCY / (16* 65536).
With a full 16-bit baud rate generator, at 30 MIPS oper-
ation, the minimum baud rate achievable is 28.5 bps.
19.9 Auto Baud Support
Break is regarded as a character containing all 0’s,
with the FERR bit set. The break character is loaded
into the buffer. No further reception can occur until a
STOP bit is received. Note that RIDLE goes high when
the STOP bit has not been received yet.
To allow the system to determine baud rates of
received characters, the input can be optionally linked
to a selected capture input. To enable this mode, the
user must program the input capture module to detect
the falling and rising edges of the START bit.
2002 Microchip Technology Inc.
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19.10.2 UART OPERATION DURING CPU
IDLE MODE
19.10 UART Operation During CPU
SLEEP and IDLE Modes
For the UART, the USIDL bit selects if the module will
stop operation when the device enters IDLE mode, or
whether the module will continue on IDLE. If
USIDL = 0, the module will continue operation during
IDLE mode. If USIDL = 1, the module will stop on
IDLE.
19.10.1 UART OPERATION DURING CPU
SLEEP MODE
When the device enters SLEEP mode, all clock
sources to the module are shut-down and stay at logic
‘0’. If entry into SLEEP mode occurs while a transmis-
sion is in progress, then the transmission is aborted.
The UxTX pin is driven to logic ‘1’. Similarly, if entry
into SLEEP mode occurs while a reception is in
progress, then the reception is aborted. The UxSTA,
UxMODE, transmit and receive registers and buffers,
and the UxBRG register are not affected by SLEEP
mode.
If the WAKE bit (UxSTA<7>) is set before the device
enters SLEEP mode, then a falling edge on the UxRX
pin will generate a receive interrupt. The Receive
Interrupt Select mode bit (URXISEL) has no effect for
this function. If the receive interrupt is enabled, then
this will wake-up the device from SLEEP. The UAR-
TEN bit must be set in order to generate a wake-up
interrupt.
DS70032B-page 238
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Advance Information
DS70032B-page 239
dsPIC30F
REGISTER 19-1: UXMODE: UARTX MODE REGISTER
Upper Half:
R/W-0
UARTEN
bit 15
U-0
R/W-0
USIDL
U-0
U-0
R/W-0
ALTIO
U-0
U-0
—
—
—
—
—
bit 8
Lower Half:
R/W-0
WAKE
R/W-0
R/W-0
ABAUD
U-0
U-0
R/W-0
R/W-0
R/W-0
LPBACK
—
—
PDSEL1 PDSEL0
STSEL
bit 7
bit 0
bit 15
UARTEN: UART Enable bit
1= UART is enabled, all UART pins are controlled by UART
0= UART is disabled, all UART pins are controlled by PORT latches. UART power consumption is minimal.
bit 14
bit 13
Unimplemented: Read as '0'
USIDL: Stop in IDLE Mode bit
1= Discontinue module operation when device enters an IDLE mode
0= Continue module operation in IDLE mode
bit 12-11 Unimplemented: Read as '0'
bit 10
ALTIO: UART Alternate I/O Selection bit (bit is U-0 when UALTIO configuration signal = 0)
1= UART communicates on UxATX and UxARX signals
0= UART communicates on UxTX and UxRX signals
bit 9-8
bit 7
Unimplemented: Read as '0'
WAKE: Enable Wake-up on START bit Detect During SLEEP Mode bit
1= Enable wake-up
0= No wake-up enabled
bit 6
bit 5
LPBACK: UART Loopback Mode Select bit
1= Enable Loopback mode
0= Loopback mode is disabled
ABAUD: Auto Baud Enable bit
1= Input to Capture module from UxRX Pin
0= Input to Capture module from ICx Pin
bit 4-3
bit 2-1
Unimplemented: Read as '0'
PDSEL<1:0>: Parity and Data bits Selection bits
11= 9-bit data, no parity
10= 8-bit data, odd parity
01= 8-bit data, even parity
00= 8-bit data, no parity
bit 0
STSEL: STOP bit Selection bit
1= 2 STOP bits
0= 1 STOP bit
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
DS70032B-page 240
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REGISTER 19-2: UXSTA: UARTX STATUS AND CONTROL REGISTER
Upper Half:
R/W-0
UTXISEL
bit 15
U-0
U-0
U-0
R/W-0
R/W-0
R-0
R-1
TRMT
bit 8
—
—
—
UTXBRK UTXEN
UTXBF
Lower Half:
R/W-0
R/W-0
R/W-0
ADDEN
R-1
RIDLE
R-0
PERR
R-0
FERR
R/C-0
OERR
R-0
URXISEL1 URXISEL0
bit 7
URXDA
bit 0
bit 15
UTXISEL: Transmission Interrupt Mode Selection bit
1= Interrupt when a character is transferred to the Transmit Shift register and as a result, the transmit buffer
becomes empty
0= Interrupt when a character is transferred to the Transmit Shift register (this implies that there is at least
one character open in the Transmit buffer)
bit 14-12 Unimplemented: Read as '0'
bit 11
UTXBRK : Transmit Break bit
1= UxTX pin taken low, regardless of state of transmitter
0= UxTX pin in its normal condition
bit 10
UTXEN: Transmit Enable bit
1= Transmit enabled, UxTX pin controlled by UART
0= Transmit disabled, any pending transmission is aborted and buffer is reset. UxTX pin controlled by
PORT.
bit 9
UTXBF: Transmit Buffer Full Status bit (Read Only)
1= Transmit buffer is full
0= Transmit buffer is not full, at least one more character can be written
bit 8
TRMT: Transmit Shift Register is Empty bit (Read Only)
1= Transmit shift register is empty and transmit buffer is empty (the last transmission has completed)
0= Transmit shift register is not empty, a transmission is in progress or queued
bit 7-6
URXISEL<1:0>: Receive Interrupt Mode Selection bits
11= Interrupt is set when Receive buffer is full, i.e., has 4 data characters
10= Interrupt is set when Receive buffer is 3/4 full, i.e., has 3 data characters
0x= Interrupt is set when a character is received and transferred from the RSR to the Receive Buffer.
Receive buffer has one or more characters.
bit 5
bit 4
bit 3
bit 2
bit 1
ADDEN: Address Character Detect bit (bit 8 of received data = 1)
1= Address Detect mode enabled. If 9-bit mode is not selected, this does not take effect.
0= Address Detect mode disabled
RIDLE: Receiver IDLE bit (Read Only)
1= Receiver is IDLE
0= Receiver is active
PERR: Parity Error Status bit (Read Only)
1= Parity Error has been detected for the current character (the character at top of the receive FIFO)
0= Parity Error has not been detected
FERR: Framing Error Status bit (Read Only)
1= Framing Error has been detected for the current character (the character at top of the receive FIFO)
0= Framing Error has not been detected
OERR: Receive Buffer Overrun Error Status bit (Read/Clear Only)
1= Receive buffer has overflowed
0= Receive buffer has not overflowed
(Clearing a previously set OERR bit (1 -> 0 transition) will reset the receiver buffer and the RSR to empty
state.)
2002 Microchip Technology Inc.
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REGISTER 19-2: UXSTA: UARTX STATUS AND CONTROL REGISTER (Continued)
bit 0
URXDA: Receive Buffer Data Available bit (Read Only)
1= Receive buffer has data, at least one more character can be read
0= Receive buffer is empty
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
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REGISTER 19-3: UXRXREG: UARTX RECEIVE REGISTER
Upper Half:
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R-0
URX8
bit 8
—
—
—
—
—
—
—
bit 15
Lower Half:
R-0
R-0
R-0
R-0
R-0
R-0
URX2
R-0
URX1
R-0
URX7
URX6
URX5
URX4
URX3
URX0
bit 7
bit 0
bit 15-9 Unimplemented: Read as '0'
bit 8
URX8: Data bit 8 of the Received Character (in 9-bit mode)
URX<7:0>: Data bits 7-0 of the Received Character
bit 7-0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
REGISTER 19-4:
Upper Half:
UXTXREG: UARTX TRANSMIT REGISTER (NORMALLY WRITE ONLY)
U-x
U-x
U-x
U-x
U-x
U-x
U-x
W-x
—
—
—
—
—
—
—
UTX8
bit 15
bit 8
Lower Half:
W-x
W-x
W-x
W-x
W-x
W-x
UTX2
W-x
UTX1
W-x
UTX7
UTX6
UTX5
UTX4
UTX3
UTX0
bit 7
bit 0
bit 15-9 Unimplemented: Read as '0'
bit 8
UTX8: Data bit 8 of the Transmitted Character (in 9-bit mode)
UTX<7:0>: Data bits 7-0 of the Transmitted Character
bit 7-0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
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REGISTER 19-5:
UXBRG: UARTX BAUD RATE REGISTER
Upper Half:
R/W-0
R/W-0
BRG14
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BRG15
BRG13
BRG12
BRG11
BRG10
BRG09
BRG08
bit 15
bit 8
Lower Half:
R/W-0
R/W-0
R/W-0
BRG05
R/W-0
BRG04
R/W-0
BRG03
R/W-0
BRG02
R/W-0
BRG01
R/W-0
BRG07
BRG06
BRG00
bit 7
bit 0
bit 15-0 BRG<15:0>: Baud Rate Divisor bits
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
DS70032B-page 244
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dsPIC30F
20.1.1
OVERVIEW OF THE MODULE
20.0 CAN MODULE
20.1 Overview
The CAN bus module consists of a Protocol Engine
and message buffering and control. The CAN protocol
engine handles all functions for receiving and transmit-
ting messages on the CAN bus. Messages are trans-
mitted by first loading the appropriate data registers.
Status and errors can be checked by reading the
appropriate registers. Any message detected on the
CAN bus is checked for errors and then matched
against filters to see if it should be received and stored
in one of the 2 receive registers.
The Controller Area Network (CAN) module is a serial
interface, useful for communicating with other peripher-
als or microcontroller devices. This interface/protocol
was designed to allow communications within noisy
environments.
The CAN module is a communication controller imple-
menting the CAN 2.0 A/B protocol, as defined in the
BOSCH specification. The module will support CAN
1.2, CAN 2.0A, CAN2.0B Passive, and CAN 2.0B
Active versions of the protocol. The module implemen-
tation is a Full CAN system. The CAN specification is
not covered within this data sheet. The reader may
refer to the BOSCH CAN specification for further
details.
The CAN Module supports the following Frame types:
• Standard Data Frame
• Extended Data Frame
• Remote Frame
• Error Frame
• Overload Frame Reception
• Interframe Space
The module features are as follows:
• Implementation of the CAN protocol CAN1.2,
CAN2.0A and CAN2.0B
20.1.2
TRANSMIT/RECEIVE BUFFERS
• Standard and extended data frames
• 0 - 8 bytes data length
The dsPIC30F has three transmit and two receive buff-
ers, two acceptance masks (one for each receive
buffer), and a total of six acceptance filters. Figure 20-1
is a block diagram of these buffers and their connection
to the protocol engine.
• Programmable bit rate up to 1 Mbit/sec
• Support for remote frames
• Double buffered receiver with two prioritized
received message storage buffers
• 6 full (standard/extended identifier) acceptance fil-
ters, 2 associated with the high priority receive
buffer, and 4 associated with the low priority
receive buffer
• 2 full acceptance filter masks, one each associ-
ated with the high and low priority receive buffers
• Three transmit buffers with application specified
prioritization and abort capability
• Programmable wake-up functionality with
integrated low pass filter
• Programmable Loopback mode supports self-test
operation
• Signaling via interrupt capabilities for all CAN
receiver and transmitter error states
• Programmable clock source
• Programmable link to timer module for time-
stamping and network synchronization
• Low power SLEEP mode
2002 Microchip Technology Inc.
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dsPIC30F
FIGURE 20-1:
CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM
Acceptance Mask
RXM1
BUFFERS
Acceptance Filter
RXF2
A
c
c
e
p
t
Acceptance Mask
RXM0
Acceptance Filter
RXF3
TXB0
TXB1
TXB2
A
c
c
e
p
t
Acceptance Filter
RXF0
Acceptance Filter
RXF4
Acceptance Filter
RXF1
Acceptance Filter
RXF5
R
X
B
0
R
X
B
1
M
A
B
Identifier
Identifier
Message
Queue
Control
Transmit Byte Sequencer
Data Field
Data Field
Receive
Error
Counter
RXERRCNT
TXERRCNT
PROTOCOL
ENGINE
Transmit
Error
ErrPas
BusOff
Counter
Transmit Shift
Receive Shift
CRC Check
Protocol
Finite
State
CRC Generator
Machine
Bit
Timing
Logic
Transmit
Logic
Bit Timing
Generator
CxTX
CxRX
Note: x = 1 or 2.
DS70032B-page 246
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dsPIC30F
21.2.3.1
COFS PIN
21.0 DATA CONVERTER
INTERFACE (DCI) MODULE
The Codec frame synchronization (COFS) pin is used
to synchronize data transfers that occur on the SDO
and CSDI pins. The COFS pin may be configured as an
input or an output. The data direction for the COFS pin
is determined by the COFSD control bit in the
DCICON1 Register (see Register 21-1).
21.1 Module Introduction
The dsPIC30F Data Converter Interface (DCI) module
allows simple interfacing of devices such as audio
coder/decoders (Codecs), A/D converters, and D/A
converters. The following interfaces are supported:
The DCI module accesses the shadow registers while
the CPU is in the process of accessing the memory
mapped buffer registers.
• Framed Synchronous Serial Transfer (Single or
Multi-Channel)
• Inter-IC Sound (I2S) Interface
21.2.4
BUFFER DATA ALIGNMENT
• AC-Link compliant mode
Data values are always stored left justified in the buff-
ers, since most Codec data is represented as a signed
2’s complement fractional number. If the received word
length is less than 16-bits, the unused LS bits in the
receive buffer registers are set to 0 by the module. If the
transmitted word length is less than 16 bits, the unused
LS bits in the transmit buffer register are ignored by the
module. The word length setup is described in subse-
quent sections of this document.
The DCI module provides the following general
features:
• Programmable word size up to 16-bits
• Support for up to 16 time slots, for a maximum
frame size of 256 bits
• Data buffering for up to 4 samples without CPU
overhead
21.2 Module I/O Pins
21.2.5
TRANSMIT/RECEIVE SHIFT
REGISTER
There are four I/O pins associated with the module.
When enabled, the module controls the data direction
of each of the four pins.
The DCI module has a 16-bit shift register for shifting
serial data in and out of the module. Data is shifted in/
out of the shift register MS bit first, since audio PCM
data is transmitted in signed 2’s complement format.
21.2.1
CSCK PIN
The CSCK pin provides the serial clock for the DCI
module. The CSCK pin may be configured as an input
or output, using the CSCKD control bit in the DCICON2
SFR (see Register 21-2). When configured as an out-
put, the serial clock is provided by the dsPIC30F. When
configured as an input, the serial clock must be pro-
vided by an external device.
21.2.6
DCI BUFFER CONTROL
The DCI module contains a buffer control unit for trans-
ferring data between the shadow buffer memory and
the serial shift register. The buffer control unit is a sim-
ple 2-bit address counter that points to word locations
in the shadow buffer memory. For the receive memory
space (high address portion of DCI buffer memory), the
address counter is concatenated with a ‘0’ in the MSb
location to form a 3-bit address. For the transmit mem-
ory space (high portion of DCI buffer memory), the
address counter is concatenated with a ‘1’ in the MSb
location.
21.2.2
CSDO PIN
The serial data output (CSDO) pin is configured as an
output only pin when the module is enabled. The
CSDO pin drives the serial bus whenever data is to be
transmitted. The CSDO pin is tri-stated or driven to ‘0’
during CSCK periods when data is not transmitted,
depending on the state of the CSDOM control bit. This
allows other devices to place data on the serial bus dur-
ing transmission periods not used by the DCI module.
Note: The DCI buffer control unit always
accesses the same relative location in the
transmit and receive buffers, so only one
address counter is provided.
21.2.3
CSDI PIN
The serial data input (CSDI) pin is configured as an
input only pin when the module is enabled.
2002 Microchip Technology Inc.
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dsPIC30F
FIGURE 21-1:
DCI MODULE BLOCK DIAGRAM
BCG Control bits
SCKD
FSD
Sample Rate
Generator
FOSC/4
CSCK
COFS
Word Size Selection bits
Frame Length Selection bits
DCI Mode Selection bits
Frame
Synchronization
Generator
Receive Buffer
Registers w/Shadow
DCI Buffer
Control Unit
15
0
Transmit Buffer
Registers w/Shadow
DCI Shift Register
CSDI
CSDO
21.3.2
WORD SIZE SELECTION BITS
21.3 DCI Module Operation
21.3.1 MODULE ENABLE
The WS<3:0> word size selection bits in the DCICON2
SFR (see Register 21-2) determine the number of bits
in each DCI data word. Essentially, the WS<3:0> bits
determine the counting period for a 4-bit counter
clocked from the CSCK signal.
The DCI module is enabled or disabled by setting/
clearing the DCIEN control bit in the DCICON1 SFR.
Clearing the DCIEN control bit has the effect of reset-
ting the module. In particular, all counters associated
with CSCK generation, frame sync, and the DCI buffer
control unit are RESET.
Any data length, up to 16-bits may be selected. The
value loaded into the WS<3:0> bits is one less the
desired word length. For example, a 16-bit data word
size is selected when WS<3:0> = 1111.
The DCI clocks are shut-down when the DCIEN bit is
cleared.
Note: These WS<3:0> control bits are used only
in the Multi-Channel and I2S modes.
These bits have no effect in AC-Link mode,
since the data slot sizes are fixed by the
protocol.
When enabled, the DCI controls the data direction for
the four I/O pins associated with the module. The
PORT, LAT and TRIS register values for these I/O pins
are overridden by the DCI module when the DCIEN bit
is set.
It is also possible to override the CSCK pin separately
when the bit clock generator is enabled. This permits
the bit clock generator to operate, without enabling the
rest of the DCI module.
DS70032B-page 248
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21.3.3
FRAME SYNC GENERATOR
21.3.5
MASTER FRAME SYNC
OPERATION
The frame sync generator (COFSG) is a 4-bit counter
that sets the frame length in data words. The frame
sync generator is incremented each time the word size
counter is reset (refer to Section 21.3.2). The period for
the frame synchronization generator is set by writing
the COFSG<3:0> control bits in the DCICON2 SFR.
The COFSG period in clock cycles is determined by the
following formula:
When the DCI module is operating as a frame sync
master device (COFSD = 0), the COFSM mode bits
determine the type of frame sync pulse that is gener-
ated by the frame sync generator logic.
A new COFS signal is generated when the frame sync
generator resets to 0.
In the Multi-Channel mode, the frame sync pulse is
driven high for the CSCK period to initiate a data trans-
fer. The number of CSCK cycles between successive
frame sync pulses will depend on the word size and
frame sync generator control bits. A timing diagram for
the frame sync signal in Multi-Channel mode is shown
in Figure 21-2.
EQUATION 21-1: COFSG PERIOD
FrameLength = WordLength (FSGvalue + 1)
•
Frame lengths, up to 16 data words may be selected.
The frame length in CSCK periods can vary up to a
maximum of 256 depending on the word size that is
selected.
In the AC-Link mode of operation, the frame sync sig-
nal has a fixed period and duty cycle. The AC-Link
frame sync signal is high for 16 CSCK cycles and is low
for 240 CSCK cycles. A timing diagram with the timing
details at the start of an AC-Link frame is shown in
Figure 21-3.
In the I2S mode, a frame sync signal having a 50% duty
cycle is generated. The period of the I2S frame sync
signal in CSCK cycles is determined by the word size
and frame sync generator control bits. A new I2S data
transfer boundary is marked by a high-to-low or a low-
to-high transition edge on the COFS pin.
Note: The COFSG control bits will have no effect
in AC-Link mode, since the frame length is
set to 256 CSCK periods by the protocol.
21.3.4
FRAME SYNC MODE CONTROL
BITS
The type of frame sync signal is selected using the
Frame Synchronization mode control bits
(COFSM<1:0>) in the DCICON1 SFR (see
Register 21-1). The following operating modes can be
selected:
21.3.6
SLAVE FRAME SYNC OPERATION
When the DCI module is operating as a frame sync
slave (COFSD = 1), data transfers are controlled by the
Codec device attached to the DCI module. The
COFSM control bits control how the DCI module
responds to incoming COFS signals.
• Multi-Channel mode
• I2S mode
• AC-Link mode (16-bit)
• AC-Link mode (20-bit)
In the Multi-Channel mode, a new data frame transfer
will begin one CSCK cycle after the COFS pin is sam-
pled high (see Figure 21-2). The pulse on the COFS
pin resets the frame sync generator logic.
The operation of the COFSM control bits depends on
whether the DCI module generates the frame sync sig-
nal as a master device, or receives the frame sync sig-
nal as a slave device.
In the I2S mode, a new data word will be transferred
one CSCK cycle after a low-to-high or a high-to-low
transition is sampled on the COFS pin. A rising or fall-
ing edge on the COFS pin resets the frame sync gen-
erator logic.
The master device in a DSP/Codec pair is the device
that generates the frame sync signal. The frame sync
signal initiates data transfers on the CSDI and CSDO
pins and usually has the same frequency as the data
sample rate (COFS).
In the AC-Link mode, the tag slot and subsequent data
slots for the next frame will be transferred one CSCK
cycle after the COFS pin is sampled high.
The DCI module is a frame sync master, if the COFSD
control bit is cleared and is a frame sync slave, if the
COFSD control bit is set.
The COFSG and WS bits must be configured to pro-
vide the proper frame length when the module is oper-
ating in the Slave mode. Once a valid frame sync
pulse has been sampled by the module on the COFS
pin, an entire data frame transfer will take place. The
module will not respond to further frame sync pulses
until the data frame transfer has completed.
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FIGURE 21-2:
FRAME SYNC TIMING, MULTI-CHANNEL MODE
CSCK
COFS
CSDI/CSDO
MSB
LSB
FIGURE 21-3:
FRAME SYNC TIMING, AC-LINK START OF FRAME
BIT_CLK
S12 S12 S12 Tag
Tag Tag
CSDO or CSDI
SYNC
bit 2 bit 1 LSb MSb bit 14 bit 13
FIGURE 21-4:
I2S INTERFACE FRAME SYNC TIMING
CSCK
CSDI or CSDO
MSB
LSB MSB
LSB
WS
2
Note:
A 5-bit transfer is shown here for illustration purposes. The I S protocol does not specify word length — this
will be system dependent.
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21.3.7
BIT CLOCK GENERATOR
21.3.8
SAMPLE CLOCK EDGE CONTROL
BIT
The DCI module has a dedicated 12-bit time-base that
produces the bit clock. The bit clock rate (period) is set
by writing a non-zero 12-bit value to the BCG<11:0>
control bits in the DCICON1 SFR.
The sample clock edge (CSCKE) control bit determines
the sampling edge for the CSCK signal. If the CSCK bit
is cleared (default), data will be sampled on the falling
edge of the CSCK signal. The AC-Link protocols and
most Multi-Channel formats require that data be sam-
pled on the falling edge of the CSCK signal. If the
CSCK bit is set, data will be sampled on the rising edge
of CSCK. The I2S protocol requires that data be sam-
pled on the rising edge of the CSCK signal.
When the BCG<11:0> bits are set to zero, the bit clock
will be disabled. If the BCG<11:0> bits are set to a non-
zero value, the bit clock generator is enabled. These
bits should be set to ‘0’ and the CSCKD bit set to 1, if
the serial clock for the DCI is received from an external
device.
The formula for the bit clock frequency is given in
Equation 21-2.
21.3.9
DATA JUSTIFICATION CONTROL
BIT
In most applications, the data transfer begins one
CSCK cycle after the COFS signal is sampled active.
This is the default configuration of the DCI module. An
alternate data alignment can be selected by setting the
DJST control bit in the DCICON2 SFR. When DJST = 1,
data transfers will begin during the same CSCK cycle
when the COFS signal is sampled active.
EQUATION 21-2: BIT CLOCK FREQUENCY
fCYC
fBCK =
2
(BCG + 1)
•
The required bit clock frequency will be determined by
the system sampling rate and frame size. Typical bit
clock frequencies range from 16x to 512x the converter
sample rate, depending on the data converter and the
communication protocol that is used.
21.3.10 TRANSMIT SLOT ENABLE BITS
The TSCON SFR (see Register 21-5) has control bits
that are used to enable up to 16 time-slots for transmis-
sion. These control bits are the TSE<15:0> bits. The
size of each time-slot is determined by the WS<3:0>
word size selection bits and can vary up to 16-bits.
To achieve bit clock frequencies associated with com-
mon audio sampling rates, the user will need to select
a crystal frequency that has an ‘even’ binary value.
Examples of such crystal frequencies are listed in
Table 21-1.
If a transmit time-slot is enabled via one of the TSE bits
(TSEx = 1), the contents of the current transmit shadow
buffer location will be loaded into the CSDO shift regis-
ter and the DCI buffer control unit is incremented to
point to the next location.
TABLE 21-1: DEVICE FREQUENCIES FOR
COMMON CODEC CSCK
During an unused transmit time-slot, the CSDO pin will
drive 0’s or will be tri-stated during all disabled time-
slots, depending on the state of the CSDOM bit in the
DCICON1 SFR.
FREQUENCIES
FOSC
PLL
FCYC
2.048 MHz
4.096 MHz
4.800 MHz
9.600 MHz
16x
8x
32.768 MIPS
32.768 MIPS
38.4 MIPS
The data frame size in bits is determined by the chosen
data word size and the number of data word elements
in the frame. If the chosen frame size has less than 16
elements, the additional slot enable bits will have no
effect.
8x
4x
38.4 MIPS
Each transmit data word is written to the 16-bit transmit
buffer as left justified data. If the selected word size is
less than 16-bits, then the LS bits of the transmit buffer
memory will have no effect on the transmitted data. The
user should write 0’s to the unused LS bits of each
transmit buffer location.
Note 1: When the CSCK signal is applied exter-
nally (CSCKD = 1), the BCG<9:0> bits
have no effect on the operation of the DCI
module.
2: When the CSCK signal is applied exter-
nally (CSCKD = 1), the external clock
high and low times must meet the device
timing requirements.
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21.3.11 RECEIVE SLOT ENABLE BITS
21.3.14
BUFFER LENGTH CONTROL
The RSCON SFR (see Register 21-6) contains control
bits that are used to enable up to 16 time-slots for
reception. These control bits are the RSE<15:0> bits.
The size of each receive time-slot is determined by the
WS<3:0> word size selection bits and can vary from 1
to 16 bits.
The amount of data that is buffered between interrupts
is determined by the buffer length (BLEN<1:0>) control
bits in the DCISTAT SFR (see Register 21-4). The size
of the transmit and receive buffers may be varied from
1 to 4 data words, using the BLEN control bits. The
BLEN control bits are compared to the current value of
the DCI buffer control unit address counter. When the 2
LS bits of the DCI address counter match the
BLEN<1:0> value, the buffer control unit will be reset to
0. In addition, the contents of the receive shadow reg-
isters are transferred to the receive buffer registers and
the contents of the transmit buffer registers are trans-
ferred to the transmit shadow registers.
If a receive time-slot is enabled via one of the RSE bits
(RSEx = 1), the shift register contents will be written to
the current DCI receive shadow buffer location and the
buffer control unit will be incremented to point to the
next buffer location.
Data is not packed in the receive memory buffer loca-
tions if the selected word size is less than 16 bits. Each
received slot data word is stored in a separate 16-bit
buffer location. Data is always stored in a left justified
format in the receive memory buffer.
21.3.15 BUFFER ALIGNMENT WITH DATA
FRAMES
There is no direct coupling between the position of the
AGU address pointer and the data frame boundaries.
This means that there will be an implied assignment of
each transmit and receive buffer that is a function of
the BLEN control bits and the number of enabled data
slots via the TSE and RSE control bits.
21.3.12 SLOT ENABLE BITS OPERATION
WITH FRAME SYNC
The TSE and RSE control bits operate in concert with
the DCI frame sync generator. In the Master mode, a
COFS signal is generated whenever the frame sync
generator is reset. In the Slave mode, the frame sync
generator is reset whenever a COFS pulse is received.
As an example, assume that a 4-word data frame is
chosen and that we want to transmit on all four time-
slots in the frame. This configuration would be estab-
lished by setting the TSE0, TSE1, TSE2, and TSE3
control bits in the TSCON SFR. With this module
setup, the TXBUF0 register would be naturally
assigned to slot #0, the TXBUF1 register would be
naturally assigned to slot #1, and so on.
The TSE and RSE control bits allow up to 16 consecu-
tive time-slots to be enabled for transmit or receive.
After the last enabled time-slot has been transmitted/
received, the DCI will stop buffering data until the next
occurring COFS pulse.
Note: When more than four time-slots are active
within a data frame, the user code must
keep track of which time-slots are to be
read/written at each interrupt. In some
cases, the alignment between transmit/
receive buffers and their respective slot
assignments could be lost. Examples of
such cases include an emulation break-
point or a hardware trap. In these situa-
tions, the user should poll the SLOT status
bits to determine what data should be
loaded into the buffer registers to resyn-
chronize the software with the DCI module.
21.3.13 SYNCHRONOUS DATA
TRANSFERS
The DCI buffer control unit will be incremented by one
word location, whenever a given time-slot has been
enabled for transmission or reception. In most cases,
data input and output transfers will be synchronized,
which means that a data sample is received for a given
channel at the same time a data sample is transmitted.
Therefore, the transmit and receive buffers will be filled
with equal amounts of data when a DCI interrupt is gen-
erated.
In some cases, the amount of data transmitted and
received during a data frame may not be equal. As an
example, assume a two-word data frame is used. Fur-
thermore, assume that data is only received during slot
#0, but is transmitted during slot #0 and slot #1. In this
case, the buffer control unit counter would be incre-
mented twice during a data frame, but only one receive
register location would be filled with data.
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21.3.16 TRANSMIT STATUS BITS
21.3.19 CSDO MODE BIT
There are two transmit status bits in the DCISTAT SFR.
The CSDOM control bit controls the behavior of the
CSDO pin during unused transmit slots. A given trans-
mit time-slot is unused if its corresponding TSEx bit in
the TSCON SFR is cleared.
The TMPTY bit is set when the contents of the trans-
mit buffer registers are transferred to the transmit
shadow registers. The TMPTY bit may be polled in
software to determine when the transmit buffer regis-
ters may be written. The TMPTY bit is cleared auto-
matically by the hardware when a write to one of the
four transmit buffers occurs.
If the CSDOM bit is cleared (default), the CSDO pin
will drive 0’s onto the CSDO pin during unused time-
slot periods. This mode will be used when there are
only two devices attached to the serial bus.
The TUNF bit is read only and indicates that a transmit
underflow has occurred for at least one of the transmit
buffer registers that is in use. The TUNF bit is set at the
time the transmit buffer registers are transferred to the
transmit shadow registers. The TUNF status bit is
cleared automatically when the buffer register that
underflowed is written by the CPU.
If the CSDOM bit is set, the CSDO pin will be tri-stated
during unused time-slot periods. This mode allows
multiple devices to share the same CSDO line in a
Multi-Channel application. Each device on the CSDO
line is configured so that it will only transmit data dur-
ing specific time-slots. No two devices will transmit
data during the same time-slot.
Note: The transmit status bits only indicate status
for buffer locations that are used by the
module. If the buffer length is set to less
than four words, for example, the unused
buffer locations will not affect the transmit
status bits.
21.3.20 DIGITAL LOOPBACK MODE
Digital Loopback mode is enabled by setting the
DLOOP control bit in the DCISTAT SFR. When the
DLOOP bit is set, the module internally connects the
SDO signal to CSDI. The actual data input on the CSDI
I/O pin will be ignored in Digital Loopback mode.
21.3.17 RECEIVE STATUS BITS
21.3.21 UNDERFLOW MODE CONTROL BIT
There are two receive status bits in the DCISTAT SFR.
When an underflow occurs, one of two actions may
occur, depending on the state of the Underflow mode
(UNFM) control bit in the DCICON2 SFR. If the UNFM
bit is cleared (default), the module will transmit 0’s on
the SDO pin during the active time-slot for the buffer
location. In this operating mode, the Codec device
attached to the DCI module will simply be fed digital
‘silence’. If the UNFM control bit is set, the module will
transmit the last data written to the buffer location. This
operating mode permits the user to send continuous
data to the Codec device without consuming CPU
overhead.
The RFUL status bit is read only and indicates that new
data is available in the receive buffers. The RFUL bit is
cleared automatically when all receive buffers in use
have been read by the CPU.
The ROV status bit is read only and indicates that a
receive overflow has occurred for at least one of the
receive buffer locations. A receive overflow occurs
when the buffer location is not read by the CPU before
new data is transferred from the shadow registers. The
ROV status bit is cleared automatically when the buffer
register that caused the overflow is read by the CPU.
When a receive overflow occurs for a specific buffer
location, the old contents of the buffer are overwritten.
21.4 DCI Module interrupts
The frequency of DCI module interrupts is dependent
on the BLEN<1:0> control bits in the DCICON2 SFR.
An interrupt to the CPU is generated each time the set
buffer length has been reached and a shadow register
transfer takes place. A shadow register transfer is
defined as the time when the previously written
TXBUF values are transferred to the transmit shadow
registers and new received values in the receive
shadow registers are transferred into the RXBUF reg-
isters.
Note: The receive status bits only indicate status
for buffer locations that are used by the
module. If the buffer length is set to less
than four-words, for example, the unused
buffer locations will not affect the transmit
status bits.
21.3.18 SLOT STATUS BITS
The SLOT<3:0> status bits in the DCISTAT SFR indi-
cate the current active time-slot. These bits will corre-
spond to the value of the frame sync generator
counter. The user may poll these status bits in soft-
ware when a DCI interrupt occurs, to determine what
time-slot data was last received and which time-slot
data should be loaded into the TXBUF registers.
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21.6.1
SETUP DETAILS FOR SINGLE
CHANNEL CODEC
21.5 DCI Module Operation During CPU
SLEEP and IDLE Modes
This section addresses the setup requirements for a
single channel Codec. The setup example that follows
assumes a single channel 16-bit Codec that requires a
256 x fS CSCK frequency.
21.5.1
DCI MODULE OPERATION DURING
CPU SLEEP MODE
The DCI module has the ability to operate while in
SLEEP mode and wake the CPU when the CSCK sig-
nal is supplied by an external device (CSCKD = 1). The
DCI module will generate an asynchronous interrupt
when a DCI buffer transfer has completed and the CPU
is in SLEEP mode.
Most Codecs require a CSCK signal that is some mul-
tiple of the sampling frequency. In many cases, the
CSCK signal has a frequency that is 256 x fs. There-
fore, a frame sync pulse must be generated every 256
CSCK cycles to start a data transfer.
In some cases, the CSCK signal is derived from a crys-
tal oscillator on the Codec. In this case, the CSCKD
control bit would be set to allow the DCI module to
operate from external clock sources. In other applica-
tions, the CSCK signal can be provided to the Codec by
the DCI module. In this case, a PLL may be present on
the Codec to generate internal clocks from the CSCK
input. The CSCKD bit would be cleared and the BCG
control bits would be loaded with a value to produce the
desired CSCK frequency.
21.5.2
DCI MODULE OPERATION DURING
CPU IDLE MODE
If the DCISIDL control bit is cleared (default), the mod-
ule will continue to operate normally even in IDLE
mode. If the DCISIDL bit is set, the module will halt
when IDLE mode is asserted.
21.6 Multi-Channel Mode Operation
The module is enabled for multi-channel operation by
writing a value of 0 to the COFSM<1:0> control bits in
the DCICON1 SFR. The Multi-Channel mode is used
for both single and multi-channel transfers. The setup
values for Multi-Channel mode are summarized in
Table 21-2.
To generate a 256-bit frame interval, the WS<3:0> con-
trol bits are set to a value of ‘1111’ to provide a 16-bit
data word size. Next, the COFSG<3:0> control bits are
set to a value of ‘1111’ to provide 16 data words per
frame. The 256-bit frame could be set up to transfer six-
teen, 16-bit data words between frame sync pulses.
Because a single channel Codec is used, data is only
transferred during the first 16 CSCK periods of the
frame. Therefore, the RSE0 and TSE0 control bits are
set to enable reception and transmission during the first
data slot of the frame.
TABLE 21-2: MULTI-CHANNEL SETUP
VALUES
COFSM<1:0>
BCG<9:0>
00
The amount of data to be buffered between interrupts
must be decided. The BLEN<1:0> control bits must be
set accordingly. One sample of data is received from
the codec ADC for every sample that is transmitted to
the codec DAC. For an application that requires mini-
mal processing delay, the DCI module may be setup to
provide an interrupt after each sample is transmitted/
received. Optionally, up to four samples may be buff-
ered before an interrupt is generated. The data sam-
ples can be stored and processed together to generate
four new output samples. This process is known as
‘block processing’ and helps to reduce interrupt over-
head.
Select desired bit clock frequency
(CSCKD = 0only)
UNFM
CMOD
Select behavior for a transmit
underflow
Select single or continuous transfer
operation
(COFSD = 0only)
COFSD
0for master COFS
1for slave COFS
CSCKE
CSCKD
0
0for master CSCK
1for slave CSCK
DJST
0
The value written to the COFSD control bit depends on
which device will initiate data transfers. The DCI mod-
ule is the master device if the COFSD bit is cleared,
and is the slave device if the bit is set. The DCI module
may be a master or slave device depending on user
preference and Codec functionality.
WS<3:0>
COFSG<3:0>
BLEN<1:0>
Set for desired word length
Set for desired frame sync interval
Set for # data words to buffer
between interrupts
TSE<15:0>
RSE<15:0>
Select active transmit slots
Select active receive slots
If the DCI module is the master device, data transfers
do not have to be continuous. If the CMOD bit is
cleared, data transfers will only take place during frame
periods when the transmit buffers are written.
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21.6.2
MULTI-CHANNEL CODEC
CONFIGURATION
21.7.2
16-BIT AC-LINK MODE
In the 16-bit AC-Link mode, data word lengths are
restricted to 16-bits. Note that this restriction only affects
the 20-bit data time-slots of the AC-Link protocol. For
received time-slots, the incoming data is simply trun-
cated to 16-bits. For outgoing time-slots, the 4 LS bits of
the data word are set to 0 by the module. This trunca-
tion of the time-slots limits the A/D and DAC data to 16-
bits, but permits proper data alignment in the TXBUF
and RXBUF registers. Each RXBUF and TXBUF regis-
ter will contain one data time-slot value.
The transfer of control data and multiple data channels
over the serial connection between the dsPIC device
and the Codec is enabled by Time Division Multiplexing
(TDM) of the data. The number of TDM time-slots will
depend on the actual Codec that is selected.
A hypothetical example of serial time-slot assignment
for a Codec is given below:
Transmit Time-slots
• Slot #0: Control Register Address
• Slot #1: Control Register Write Data
• Slot #2: DAC Channel 1 Data
• Slot #3: DAC Channel 2 Data
21.7.3
20-BIT AC-LINK MODE
The 20-bit AC-Link mode allows all bits in the data
time-slots to be transmitted and received, but does not
maintain data alignment in the TXBUF and RXBUF
registers.
Receive Time-slots
• Slot #0: Control Register Address Echo
• Slot #1: Control Register Read Data
• Slot #2: ADC Channel 1 Data
The 20-bit AC-Link mode functions similar to the Multi-
Channel mode of the DCI module, except for the duty
cycle of the frame synchronization signal. The AC-Link
frame synchronization signal should remain high for
16 CSCK cycles and should be low for the following
240 cycles.
• Slot #3: ADC Channel 2 Data
The DCI module is configured similar to the single
channel setup described in Section 21.6.1, except that
multiple slots are enabled for transmission and recep-
tion. In this example, TSE0, TSE1, TSE2, and TSE3
are set to transmit data on the first four slots of the
frame. Similarly, RSE0, RSE1, RSE2, and RSE3 are
set to enable reception during the first four time-slots.
The 20-bit mode treats each 256-bit AC-Link frame as
sixteen, 16-bit time-slots. In the 20-bit AC-Link mode,
the module operates as if COFSG<3:0> = 1111 and
WS<3:0> = 1111. The data alignment for 20-bit data
slots is ignored. For example, an entire AC-link data
frame can be transmitted and received in a packed
fashion by setting all bits in the TSCON and RSCON
SFRs. Since the total available buffer length is 64-bits,
it would take 4 consecutive interrupts to transfer the
AC-Link frame. The application software must keep
track of the current AC-Link frame segment.
The WS<3:0> control bits should be set to the native
word size of the Codec and the COFSG<3:0> control
bits should be set to provide the correct number of
CSCK cycles per frame.
21.7 AC-Link Mode Operation
21.7.4
AC-LINK SETUP
21.7.1
AC-LINK WORD SIZE ISSUES
The module is enabled for AC-Link mode by writing 10
or 11to the COFSM<1:0> control bits in the DCICON1
SFR. The word size selection bits (WS<3:0>) and the
frame synchronization generator bits (COFS<4:0>)
have no effect in the AC-Link modes, since the frame
and word sizes are set by the protocol.
The AC-Link protocol is a 256-bit frame with one 16-bit
data slot, followed by twelve 20-bit data slots. The DCI
module has two operating modes for the AC-Link pro-
tocol. These operating modes are selected by the
COFSM<1:0> control bits in the DCICON1 SFR. The
first AC-Link mode is called ‘16-bit AC-Link mode’ and
is selected by setting COFSM<1:0> = 10. The second
AC-Link mode is called ‘20-bit AC-Link mode’ and is
selected by setting COFSM<1:0> = 11.
The CSCKD control bit is set in software. The COFSD
control bit is cleared because the DCI will generate the
COFS signal from the incoming CSCK signal. The
CSCKE bit is cleared so that data is sampled on the
rising edge.
The user must decide which time-slots in the AC-Link
data frame are to be buffered, and set the TSE and
RSE control bits accordingly. At a minimum, it will be
necessary to buffer the transmit and receive Tag slots,
which implies that the TSE0 and RSE0 bits should be
set in software.
Note: Only the TSE<12:0> and RSE12:0> bits will
have an effect in the 16-bit AC-Link mode
since an AC-Link frame has 13 time-slots.
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I2S DATA JUSTIFICATION
2
21.8.2
21.8 I S Mode Operation
As per the I2S specification, a data word transfer will, by
default, begin one CSCK cycle after a transition of the
WS signal. A ‘MS bit left justified’ option can be
selected using the DJST control bit in the DCICON2
SFR.
If DJST = 1, the I2S data transfers will be MS bit left jus-
tified. The MS bit of the data word will be presented on
the SDO pin during the same CSCK cycle as the rising
or falling edge of the COFS signal. The SDO pin is tri-
stated after the data word has been sent.
The DCI module is configured for I2S mode by writing
a value of 01 to the COFSM<1:0> control bits in the
DCICON1 SFR. When operating in the I2S mode, the
DCI module will generate frame synchronization sig-
nals with a 50% duty cycle. Each edge of the frame
synchronization signal marks the boundary of a new
data word transfer.
The user must also select the frame length and data
word size using the COFSG and WS control bits in the
DCICON2 SFR.
The left justified data option allows two stereo Codecs
to be connected to the same serial bus. The word size
selection bits are set to twice the Codec word length
and data is read/written to the DCI memory in a packed
format.
Timing diagrams for I2S mode are shown in Figure 21-5.
For reference, these diagrams assume an 8-bit word
size (WS<3:0> = 0111). Two elements would be
required to achieve a 16-bit sub-frame (COFSG<3:0> =
0001). The third timing diagram in Figure 21-5 uses
packed data to read/write from two Codecs. For this
example, the DCI module is configured for a 16-bit data
word (WS<3:0> = 1111). Two packed 8-bit words are
written to each 16-bit location in the DCI memory buffer.
21.8.1
I2S FRAME AND DATA WORD
LENGTH SELECTION
The WS and COFSG control bits are set to produce the
period for one half of an I2S data frame. That is, the
frame length is the total number of CSCK cycles
required for a left or a right data word transfer.
Although only one data word is transferred per I2S sub-
frame, It may be necessary to set the COFSG value to
a higher value to produce the appropriate number of
CSCK cycles per frame. For example, many I2S
Codecs use a 64x serial clock. In other words, there are
64 CSCK cycles per frame and 32 cycles per left/right
subframe. Assuming that a 16-bit Codec is connected
to the DCI module, the user should configure the
COFSG bits for 2 words per frame (COFSG<3:0> =
0001) and the WS bits are configured for a 16-bit data
word (WS<3:0> = 1111).
A 4 data word frame has been defined for this example,
but only the first time-slot is of interest. Therefore, the
TSE0 and RSE0 control bits are set to make the mod-
ule actively transmit and receive data during these
time-slots.
The BLEN bits must be set for the desired buffer length.
Setting BLEN<1:0> = 01will produce a CPU interrupt,
once per I2S frame.
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FIGURE 21-5:
I2S TIMING DIAGRAMS
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REGISTER 21-1: DCICON1: DCI MODULE CONTROL REGISTER1
Upper Half:
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
COFSD
bit 8
DCIEN
—
DCISIDL
—
DLOOP
CSCKD
CSCKE
bit 15
Lower Half:
R/W-0
UNFM
R/W-0
DJST
R/W-0
CSDOM
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
COFSM1 COFSM0
bit 0
bit 7
bit 15
DCIEN: DCI Module Enable bit
1= Module is enabled
0= Module is disabled
bit 14
bit 13
Unimplemented: Read as ‘0’
DCISIDL: DCI Stop in IDLE Control bit
1= Module will halt in CPU IDLE mode
0= Module will continue to operate in CPU IDLE mode
bit 12
bit 11
Unimplemented: Read as ‘0’
DLOOP: Digital Loopback Mode Control bit
1= Digital Loopback mode is enabled
0= Digital Loopback mode is disabled
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
CSCKD: Sample Clock Direction Control bit
1= CSCK pin is an input when DCI module is enabled
0= CSCK pin is an output when DCI module is enabled
CSCKE: Sample Clock Edge Control bit
1= Data changes on CSCK falling edge, sampled on CSCK rising edge
0= Data changes on CSCK rising edge, sampled on CSCK falling edge
COFSD: Output Frame Synchronization Direction Control bit
1= COFS pin is an input when DCI module is enabled
0= COFS pin is an output when DCI module is enabled
UNFM: Underflow Mode bit
1= Transmit last value written to the transmit buffers on a transmit underflow
0= Transmit 0’s on a transmit underflow
CSDOM: Serial Data Output Mode bit
1= SDO pin will be tri-stated during disabled transmit time-slots
0= SDO pin drives 0’s during disabled transmit time-slots
DJST: DCI Data Justification Control bit
1= Data transmission/reception is begun during the same CSCK cycle as the frame synchronization pulse
0= Data transmission/reception is begun one CSCK cycle after frame synchronization pulse
bit 4-2
bit 1-0
Unimplemented: Read as ‘0’
COFSM<1:0>: Frame Sync Mode bits
11= 20-bit AC-Link mode
10= 16-bit AC-Link mode
01= I2S Frame Sync mode
00= Multi-Channel Frame Sync mode
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
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REGISTER 21-2: DCICON2: DCI MODULE CONTROL REGISTER2
Upper Half:
U-0
U-0
U-0
U-0
R/W-0
R/W-0
U-0
R/W-0
COFSG3
bit 8
—
—
—
—
BLEN1
BLEN0
—
bit 15
Lower Half:
R/W-0
R/W-0
R/W-0
U-0
R/W-0
WS2
R/W-0
WS1
R/W-0
WS0
R/W-0
WS0
COFSG2 COFSG1 COFSG0
bit 7
—
bit 0
bit 15-12 Unimplemented: Read as ‘0’
bit 11-10 BLEN<1:0>: Buffer Length Control bits
11= Four data words will be buffered between interrupts
10= Three data words will be buffered between interrupts
01= Two data words will be buffered between interrupts
00= One data word will be buffered between interrupts
bit 9
Unimplemented: Read as ‘0’
bit 8-5
COFSG<3:0>: Frame Sync Generator Control bits
1111= Data frame has 16 words
||
0010= Data frame has 3 words
0001= Data frame has 2 words
0000= Data frame has 1 word
bit 4
Unimplemented: Read as ‘0’
bit 3-0
WS<3:0>: DCI Data Word Size bits
1111= Data word size is 16-bits
||
0010= Data word size is 3-bits
0001= Data word size is 2-bits
0000= Data word size is 1-bit
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
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REGISTER 21-3: DCICON3: DCI MODULE CONTROL REGISTER3
Upper Half:
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
BCG9
R/W-0
BCG8
bit 8
—
—
—
—
BCG11
BCG10
bit 15
Lower Half:
R/W-0
BCG7
R/W-0
BCG6
R/W-0
BCG5
R/W-0
BCG4
R/W-0
BCG3
R/W-0
BCG2
R/W-0
BCG1
R/W-0
BCG0
bit 7
bit 0
bit 15-12 Unimplemented: Read as ‘0’
bit 11-0 BCG<11:0>: DCI bit Clock Generator Control bits
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
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REGISTER 21-4: DCISTAT: DCI STATUS REGISTER
Upper Half:
U-0
U-0
U-0
U-0
R-0
R-0
R-0
R-0
—
—
—
—
SLOT3
SLOT2
SLOT1
SLOT0
bit 15
bit 8
Lower Half:
U-0
U-0
U-0
U-0
R-0
ROV
R-0
RFUL
R-0
TUNF
R-0
—
—
—
—
TMPTY
bit 7
bit 0
bit 15-12 Unimplemented: Read as ‘0’
bit 11-8
SLOT<3:0>: DCI Slot Status bits
1111= Slot #15 is currently active
||
0010 = Slot #2 is currently active
0001= Slot #1 is currently active
0000= Slot #0 is currently active
bit 7-4
bit 3
Unimplemented: Read as ‘0’
ROV: Receive Overflow Status bit
1= A receive overflow has occurred for at least one buffer location
0= A receive overflow has not occurred
bit 2
bit 1
bit 0
RFUL: Receive Buffer Full Status bit
1= New data is available in the receive buffers
0= The receive buffer is empty
TUNF: Transmit Buffer Underflow Status bit
1= A transmit underflow has occurred for at least one transmit buffer
0= A transmit underflow has not occurred
TMPTY: Transmit Buffer Empty Status bit
1= The transmit buffer is empty
0= The transmit buffer is not empty
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
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REGISTER 21-5: TSCON: TRANSMIT SLOT CONTROL REGISTER
Upper Half:
R/W-0
TSE15
R/W-0
TSE14
R/W-0
TSE13
R/W-0
TSE12
R/W-0
TSE11
R/W-0
TSE10
R/W-0
TSE9
R/W-0
TSE8
bit 8
bit 15
Lower Half:
R/W-0
TSE7
R/W-0
TSE6
R/W-0
TSE5
R/W-0
TSE4
R/W-0
TSE3
R/W-0
TSE2
R/W-0
TSE1
R/W-0
TSE0
bit 7
bit 0
bit 11
TSE<15:0>: Transmit Slot Enable Control bits
1= Transmit buffer contents are sent during the time-slot
0= SDO pin is tri-stated during the time-slot
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
REGISTER 21-6: RSCON: RECEIVE SLOT CONTROL REGISTER
Upper Half:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RSE11
R/W-0
R/W-0
RSE9
R/W-0
RSE8
RSE15
RSE14
RSE13
RSE12
RSE10
bit 15
bit 8
Lower Half:
R/W-0
RSE7
R/W-0
RSE6
R/W-0
RSE5
R/W-0
RSE4
R/W-0
RSE3
R/W-0
RSE2
R/W-0
RSE1
R/W-0
RSE0
bit 7
bit 0
bit 11
RSE<15:0> : Receive Slot Enable bits
1= CSDI data is received during time-slot n
0= CSDI data is ignored during time-slot n
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
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NOTES:
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The A/D module has six 16-bit registers.
22.0 12-BIT ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
•
•
•
•
•
•
A/D Control Register1 (ADCON1)
A/D Control Register2 (ADCON2)
The 12-bit Analog-to-Digital Converter (A/D) allows
conversion of an analog input signal to a corresponding
12-bit digital number. This module is based on a Suc-
cessive Approximation Register (SAR) architecture,
and provides a maximum sampling rate of 500 ksps.
The A/D module has up to 16 analog inputs, which are
multiplexed into a sample and hold amplifier. The out-
put of the sample and hold is the input into the con-
verter, which generates the result. The analog
reference voltage is software selectable to either the
device supply voltage (AVDD/AVSS), or the voltage level
on the (VREF+/VREF-) pin. The A/D converter has a
unique feature of being able to operate while the device
is in SLEEP mode, with RC oscillator selection.
A/D Control Register3 (ADCON3)
A/D Input Select Register (ADCHS)
A/D Port Configuration Register (ADPCFG)
A/D Input Scan Selection Register (ADCSSL)
The ADCON1, ADCON2 and ADCON3 registers con-
trol the operation of the A/D module. The ADCHS reg-
ister selects the input channels to be converted. The
ADPCFG register configures the port pins as analog
inputs or as digital I/O. The ADCSSL register selects
inputs for scanning.
Note: The SSRC<2:0>, ASAM, SMPI<3:0>,
BUFM and ALTS bits, as well as the
ADCON3 and ADCSSL registers, must not
be written to while ADON = 1. This would
lead to indeterminate results.
The block diagram of the 12-bit A/D module is shown in
Figure 22-1.
FIGURE 22-1:
12-BIT A/D FUNCTIONAL BLOCK DIAGRAM
VREF+
VREF-
AVDD AVSS
Comparator
DAC
0000
AN0
0001
0010
0011
AN1
AN2
AN3
12-Bit SAR
Conversion Logic
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
AN4
AN5
16-word, 12-bit
Dual Port
RAM
AN6
AN7
Sample/Sequence
Control
Sample
AN8
AN9
Input
Switches
AN10
AN11
AN12
AN13
AN14
AN15
Input Mux
Control
CH0
CH0G
CH0R
S/H
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Use of the BUFM bit will depend on how much time is
available for the moving of the buffers after the
interrupt.
22.1 A/D Result Buffer
The module contains a 16-word dual port RAM, called
ADRES<15:0>, to buffer the A/D results. The RAM is
12-bits wide, but the data obtained is represented in
one of four different 16-bit data formats.
If the processor can quickly unload a full buffer within
the time it takes to sample and convert one channel,
the BUFM bit can be 0 and up to 16 conversions (cor-
responding to the 16 input channels) may be done per
interrupt. The processor will have one sample and con-
version time to move the sixteen conversions.
Only word writes are allowed to the result buffer. If byte
writes are attempted, the results are indeterminate.
22.2 Conversion Operation
If the processor cannot unload the buffer within the
sample and conversion time, the BUFM bit should be 1.
For example, if SMPI<3:0> (ADCON2<5:2>) = 0111,
then eight conversions will be loaded into 1/2 of the
buffer, following which, an interrupt occurs. The next
eight conversions will be loaded into the other 1/2 of the
buffer. The processor will have the entire time between
interrupts to move the eight conversions.
After the A/D module has been configured as desired,
the sampling is started by setting the SAMP bit. Various
sources, such as a programmable bit, timer time-outs
and external events, will terminate sampling and start a
conversion. When the A/D conversion is completed,
the result is loaded into ADRES<15:0>, the CONV bit
is cleared, and the A/D interrupt flag, ADIF, is set. The
ADC module can be configured for different interrupt
rates, as described in Section 22.3.
The ALTS bit can be used to alternate the inputs
selected during the sampling sequence. If the ALTS bit
is 0, only the SAMPLE A inputs are selected for sam-
pling. If the ALTS bit is 1 and SMPI<3:0> = 0000, on
the first sample/convert sequence, the SAMPLE A
inputs are selected, and on the next sample/convert
sequence, the SAMPLE B inputs are selected.
The following steps should be followed for doing an
A/D conversion:
1. Configure the A/D module
• Configure analog pins/voltage reference/
and digital I/O
The CSCNA bit (ADCON2<10>) will allow the CH0
channel inputs to be scanned across a selected num-
ber of analog inputs during SAMPLE A samples. The
inputs are selected by the ADCSSL register. If a partic-
ular bit in the ADCSSL register is ‘1’, the corresponding
input is selected. The inputs are always scanned from
lower to higher numbered inputs, starting after each
interrupt occurs. If the number of inputs selected is
greater than the number of samples taken per interrupt,
the higher numbered inputs are unused.
• Select A/D input channels
• Select A/D conversion clock
• Select A/D conversion trigger
• Turn on A/D module
2. Configure A/D interrupt (if required)
• Clear ADIF bit
• Select A/D interrupt priority
3. Start sampling
4. Wait the required sampling time
5. Trigger sample end, start conversion
• Module sets CONV bit
22.4 Programming the Sample Trigger
The sample trigger will terminate sampling and start the
requested conversions.
6. Wait for A/D conversion to complete, by either:
• Polling for the CONV bit to be cleared
• Waiting for the A/D interrupt
The SSRC<2:0> bits select the source of the sample
trigger.
7. Read A/D result buffer, clear ADIF if required.
When SSRC<2:0> = 000, the sample trigger is under
software control. Clearing the SAMP bit will cause the
sample trigger.
22.3 Selecting the Conversion
Sequence
When SSRC<2:0> = 111, the sample trigger is under
A/D clock control. The SAMC bits select the number of
A/D clocks between the start of sampling and the start
of conversion. This provides the fastest conversion
rates on multiple channels. SAMC must always be at
least 1 clock cycle.
Several groups of control bits select the sequence that
the A/D connects inputs to the sample/hold channel,
converts a channel, writes the buffer memory and gen-
erates interrupts.
The sequence is controlled by the sampling clocks.
Other trigger sources can come from timer modules or
external interrupts.
The SMPI bits will select how many sample clocks
occur before an interrupt occurs. This can vary from 1
sample per interrupt, to 16 samples per interrupt.
The SSRC bits provide for up to 6 alternate sources of
sample trigger.
The BUFM bit will split the 16-word results buffer into
(2) 8-word groups. Writing to the 8-word buffers will be
alternated on each interrupt event.
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22.5 Aborting a Conversion
22.6 Selecting the A/D Conversion
Clock
Clearing the CONV bit during a conversion will abort
the current conversion and stop the sampling sequenc-
ing until the next sampling trigger. The ADRES will not
be updated with the partially completed A/D conversion
sample. That is, the ADRES will continue to contain the
value of the last completed conversion (or the last
value written to the ADRES register).
The A/D conversion requires 13 TAD. The source of the
A/D conversion clock is software selected, using a
six-bit counter. There are 64 possible options for TAD.
TAD = TCY * (0.5*(ADCS<5:0> +1))
The internal RC oscillator is selected by setting the
ADRC bit.
If the clearing of the CONV bit coincides with an auto
start, the clearing has a higher priority, and a new con-
version will not start.
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 350 nsec. Table 22-1 shows the resultant TAD times
derived from the device operating frequencies and the
A/D clock source selected.
After the A/D conversion is aborted, a 2TAD wait is
required before the next sampling may be started by
setting the SAMP bit.
TABLE 22-1: TYPICAL TAD VS. DEVICE OPERATING FREQUENCIES
AD Clock Interval (TAD)/TCONV
AD Clock Source Select
Device TCY/Device MIPS/TQ/FOSC
33.33 nsec/
30 MIPS/
8.33 nsec/
120 MHz
40 nsec/
25 MIPS/
10 nsec/
100 MHz
80 nsec/
12.5 MIPS/
20 nsec/
50 MHz
160 nsec/
6.25 MIPS/
40 nsec/
25 MHz
1000 nsec/
1 MIPS/
250 nsec/
4 MHz
Clock ADRC ADCS<5:0>
16.67 ns(2)
0.22 µs
33.33 ns(2)
0.44 µs
66.66 ns(2)
0.88 µs
/
/
/
20 ns(2)
0.26 µs
/
40 ns(2)
0.52 µs
80 ns(2)
/
1.04 µs
160 ns/
/
80 ns(2)
/
1.04 µs
160 ns/
2.08 µs
2 TQ
4 TQ
8 TQ
0
0
0
000000
000001
000011
500 ns/
6.5 µs
40 ns(2)
/
1.0 µs/
13 µs
0.52 µs
80 ns(2)
/
2.0 µs(3)
26 µs
/
/
/
320 ns/
4.16 µs
2.08 µs
1.04 µs
133.32 ns(2)
/
640 ns(3)
8.32 µs
/
4.0 µs(3)
52 µs
16 TQ
32 TQ
64 TQ
RC
0
0
0
1
000111
001111
011111
xxxxxx
160 ns/
2.08 µs
320 ns/
4.16 µs
1.76 µs
640 ns(3)
8.32 µs
/
1.28 µs(3)
8.0 µs(3)
104 µs
266.64 ns/
3.52 µs
320 ns/
4.16 µs
533.28 ns(3)
/
640 ns(3)
8.32 µs
/
1.28 µs(3)
2.56 µs(3)
16.0 µs(3)
208 µs
/
7.04 µs
200 - 400 ns/
3.9 µs(1,4)
200 - 400 ns/
3.9 µs(1,4)
200 - 400 ns/
3.9 µs(1)
200 - 400 ns / 200 - 400 ns /
3.9 µs(1,4) 3.9 µs(1,4)
Note 1: The RC source has a typical TAD time of 300 ns for VDD > 3.0V.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: A/D cannot meet full accuracy with RC clock source and FOSC > 20 MHz.
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EQUATION 22-1: A/D SAMPLING TIME
EQUATIONS
22.7 A/D Sampling Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 22-2. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impedance varies over the device voltage
(VDD), see Figure 22-2. The impedance for analog
sources must be small enough to meet accuracy
requirements at the given speed. After the analog input
channel is selected (changed), this sampling must be
done before the conversion can be started.
(-TC/CHOLD (RIC+RSS+RS))
∆VO
= ∆VI • (1 -e
)
(-TC/CHOLD (RIC+RSS+RS))
1 - (∆VO / ∆VI) = e
∆VI
= n • LSB
∆VO
= n • LSB - 1/2 LSB
∆VO / ∆VI
= (n • LSB - 1/2 LSB) / n • LSB
1 - (∆VO / ∆VI) = 1 / 2n
(-TC/CHOLD (RIC+RSS+RS)
1 / 2n
= e
)
TC
= CHOLD • (RIC+RSS+RS) • -In(1/2 • n)
TSMP
= Amplifier Settling Time
+ Holding Capacitor Charging Time (TC)
+Temperature Coefficient
†
To calculate the minimum sampling time, Equation 22-1
may be used. This equation assumes that the input is
stepped some multiple (n) of the LSB step size and the
output must be captured to within 1/2 LSb error (8192
steps for 12-bit A/D). The 1/2 LSb error is the maximum
error allowed for the A/D to meet its specified resolution.
† The temperature coefficient is only required for
temperatures > 25°C.
TSMP
= 0.5 ms
+ CHOLD • (RIC+RSS+RS) • -In(1/2 • n)
+ [(Temp - 25°C)(0.05 µs/°C)]
The CHOLD is assumed to be 18 pF for the A/D.
FIGURE 22-2:
ANALOG INPUT MODEL
VDD
Sampling
Switch
VT = 0.6V
ANx
SS
RIC ≤ 1k
RSS
Rs
CHOLD
= DAC capacitance
= 18 pF
CPIN
5 pF
VA
I leakage
500 nA
VT = 0.6V
VSS
Sampling
3.5
3.0
2.5
2.0
1.5
Legend: CPIN
VT
= input capacitance
= threshold voltage
Switch
(Rss kΩ)
I leakage = leakage current at the pin due to
various junctions
RIC
SS
= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)
1.0
0.5
0
CHOLD
2
3
4
5
6
VDD (V)
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instruction cycle before starting the conversion. This
allows the SLEEPinstruction to be executed, which elimi-
nates all digital switching noise from the conversion.
When the conversion is completed, the CONV bit will be
cleared and the result loaded into the ADRES register.
22.8 Module Power-down Modes
The module has 3 internal Power modes.
When the ADON bit is 1, the module is in Active mode
and is fully powered and functional.
If the A/D interrupt is enabled, the device will wake up
from SLEEP. If the A/D interrupt is not enabled, the
A/D module will then be turned off, although the ADON
bit will remain set.
When ADON is 0 and ADSTBY is 1, the module is in
Standby mode. In Standby mode, the digital portions of
the module are active; however, the analog portions
are powered down, including the bias generators.
When ADON is 0 and ADSTBY is 0, the module is in Off
mode. The digital and analog portions of the circuit are
disabled for maximum current savings.
22.9.2
A/D OPERATION DURING CPU IDLE
MODE
For the A/D, the ADSIDL bit selects if the module will
stop on IDLE or continue on IDLE. If ADSIDL = 0, the
module will continue operation on assertion of IDLE
mode. If ADSIDL = 1, the module will stop on IDLE.
In order to return to the active mode from Standby or
Off mode, the user must wait for the bias generators to
stabilize.
22.9 A/D Operation During CPU SLEEP
and IDLE Modes
22.10 Effects of a RESET
A device RESET forces all registers to their RESET
state. This forces the A/D module to be turned off, and
any conversion and sampling sequence is aborted. The
values that are in the ADRES registers are not modi-
fied. The A/D result register will contain unknown data
after a Power-on Reset.
22.9.1
A/D OPERATION DURING CPU
SLEEP MODE
When the device enters SLEEP mode, all clock sources
to the module are shut-down and stay at logic ‘0’.
If SLEEP occurs in the middle of a conversion, the
conversion is aborted. The converter will not continue
with a partially completed conversion on exiting from
SLEEP mode.
22.11 Output Formats
The A/D result is 12-bits wide. The data buffer RAM is
also 12-bits wide. The 12-bit data can be read in one of
four different formats. The FORM<1:0> bits select the
format. Each of the output formats translates to a 16-bit
result on the data bus.
Register contents are not affected by the device enter-
ing or leaving SLEEP mode.
The A/D module can operate during SLEEP mode, if the
A/D clock source is set to RC (ADRC = 1). When the RC
clock source is selected, the A/D module waits for one
Write data will always be right justified (integer) format.
FIGURE 22-3:
A/D OUTPUT DATA FORMATS
RAM Contents:
d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
Read to Bus:
Signed Fractional
d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
0
0
0
0
0
0
0
0
Fractional
Signed Integer
Integer
d11 d11 d11 d11 d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
0
0
0
0
d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
2002 Microchip Technology Inc.
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22.12 Configuring Analog Port Pins
22.13 Connection Considerations
The use of the ADPCFG and TRIS registers control the
operation of the A/D port pins. The port pins that are
desired as analog inputs must have their correspond-
ing TRIS bit set (input). If the TRIS bit is cleared (out-
put), the digital output level (VOH or VOL) will be
converted.
Since the analog inputs employ ESD protection, they
have diodes to VDD and VSS. This requires that the
analog input must be between VDD and VSS. If the input
voltage exceeds this range by greater than 0.3V (either
direction), one of the diodes becomes forward biased
and it may damage the device if the input current spec-
ification is exceeded.
The A/D operation is independent of the state of the
CHS<3:0> bits and the TRIS bits.
An external RC filter is sometimes added for anti-
aliasing of the input signal. The R component should be
selected to ensure that the sampling time requirements
are satisfied. Any external components connected (via
high impedance) to an analog input pin (capacitor,
zener diode, etc.) should have very little leakage
current at the pin.
When reading the PORT register, all pins configured as
analog input channel will read as cleared (a low level).
Pins configured as digital inputs, will convert an analog
input. Analog levels on a digitally configured input will
not affect the conversion accuracy.
Analog levels on any pin that is defined as a digital
input (including the AN pins), may cause the input
buffer to consume current that exceeds the device
specifications.
DS70032B-page 270
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REGISTER 22-1: ADCON1: A/D CONTROL REGISTER1
Upper Byte:
R/W-0
ADON
R/W-0
R/W-0
R/W-0
U-0
U-0
R/W-0
R/W-0
—
ADSIDL
ADSTBY
—
—
FORM1
FORM0
bit 15
bit 8
Lower Byte:
R/W-0
R/W-0
SSRC1
R/W-0
U-0
U-0
R/W-0
ASAM
R/W-0
HC, HS
R/C-0
HC, HS
SSRC2
SSRC0
—
—
SAMP
CONV
bit 7
bit 0
bit 15
ADON: A/D Operating Mode bit
1= A/D converter module is operating
0= A/D converter is in Standby mode or off
bit 14
bit 13
Unimplemented: Read as '0'
ADSIDL: Stop in IDLE Mode bit
1= Discontinue module operation when device enters IDLE mode
0= Continue module operation in IDLE mode
bit 12
ADSTBY: A/D Standby Mode bit
1= If ADON = 0, A/D converter module in Standby mode. Analog circuits powered down.
0= If ADON = 0, A/D converter is shut-off and consumes no operating current
bit 11-10 Unimplemented: Read as '0'
bit 9-8
FORM<1:0>: Data Output Format bits
11= Signed Fractional (DOUT = sddd dddd dddd 0000where s= .NOT.d<11>)
10= Fractional (DOUT = dddd dddd dddd 0000)
01= Signed Integer (DOUT = ssss sddd dddd dddd where s= .NOT.d<11>)
00= Integer (DOUT = 0000 dddd dddd dddd)
bit 7-5
SSRC<2:0>: Sample Clock Source Select bits
111= Internal counter ends sampling and starts conversion (auto convert)
110= Reserved
101= Reserved
100= Reserved
011= MPWM interval ends sampling and starts conversion
010= GP Timer compare ends sampling and starts conversion
001= Active transition on INT pin ends sampling and starts conversion
000= Clearing sample bit ends sampling and starts conversion
bit 4-3
bit 2
Unimplemented: Read as '0'
ASAM: A/D Sample Auto Start bit
1= Sampling begins immediately after last conversion. SAMP bit is auto set.
0= Sampling begins when SAMP bit set
bit 1
bit 0
SAMP: A/D Sample Enable bit
1= A/D sample/hold amplifiers are sampling
0= A/D sample/hold amplifiers are holding
CONV: A/D Conversion Status bit
1= A/D conversion cycle in progress. Cleared by hardware when A/D conversion complete.
0= A/D conversion completed/not in progress
Legend:
R = Readable bit
C = Clearable bit
1 = bit is set
W = Writable bit
S = Settable bit
0 = bit is cleared
U = Unimplemented bit, read as ‘0’
-n = Value at POR
x = bit is unknown
HC = Hardware Clear
HS = Hardware Set
DS70032B-page 272
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REGISTER 22-2: ADCON2: A/D CONTROL REGISTER2
Upper Byte:
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
U-0
U-0
VCFG2
VCFG1
VCFG0
OFFCAL
—
CSCNA
—
—
bit 15
bit 8
Lower Byte:
R-0
U-0
R/W-0
SMPI3
R/W-0
SMPI2
R/W-0
SMPI1
R/W-0
SMPI0
R/W-0
BUFM
R/W-0
ALTS
BUFS
—
bit 15-13 VCFG<2:0>: Voltage Reference Configuration bits
A/D VREF+
A/D VREF-
AVSS
000
001
010
011
100
101
101
111
AVDD
External VREF+
AVDD
AVSS
External VREF-
External VREF-
Internal VRL
AVSS
External VREF+
Internal VRH
Internal VRL
Internal VRH
AVDD
AVSS
Internal VRL
Note:
Shaded regions in the table are unused. If these options are selected, the A/D references will default to
AVDD and AVSS.
bit 12
OFFCAL: Selects Offset Calibration Mode bit
1= + and - inputs of channel sample/hold shorted together
0= + and - inputs of channel sample/hold normal
bit 11
bit 10
Unimplemented: Read as '0'
CSCNA: Scan Input Selections for CH0+ bit during SAMPLE A
1= Scan inputs
0= Do not scan inputs
bit 9-8
bit 7
Unimplemented: Read as '0'
BUFS: Buffer Fill Status bit (only valid when BUFM = 1)
1= A/D is currently filling buffer 0x8 - 0xF, user should access data in 0x0 - 0x7
0= A/D is currently filling buffer 0x0 - 0x7, user should access data in 0x8 - 0xF
bit 6
Unimplemented: Read as '0'
bit 5-2
SMPI<3:0>: Selects Number of Samples per Interrupt bits
1111= Interrupts at the completion of conversion for each 16th sample
1110= Interrupts at the completion of conversion for each 15th sample
......
0001= Interrupts at the completion of conversion for each 2nd sample
0000= Interrupts at the completion of conversion for each sample
bit 1
bit 0
BUFM: Buffer Fill Mode Select bit
1= Starts buffer filling at address 0x0 on first interrupt and 0x8 on next interrupt
0= Always starts filling buffer at address 0x0
ALTS: Alternate Input Sample Mode Select bit
1= Uses channel input selects for SAMPLE A on first sample and SAMPLE B on next samples
0= Always uses channel input selects for SAMPLE A
Legend:
HC = Hardware Cleared
R = Readable bit
HS = Hardware Set
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
-n = Value at POR
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REGISTER 22-3: ADCON3: A/D CONTROL REGISTER3
Upper Byte:
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
SAMC4
SAMC3
SAMC2
SAMC1
SAMC0
bit 15
bit 8
Lower Byte:
R/W-0
ADRC
U-0
R/W-0
ADCS5
R/W-0
ADCS4
R/W-0
ADCS3
R/W-0
R/W-0
ADCS1
R/W-0
—
ADCS2
ADCS0
bit 7
bit 0
bit 15-13 Unimplemented: Read as '0'
bit 12-8 SAMC<4:0>: Auto Sample Time bits
11111= 31 TAD
·····
00001= 1 TAD
00000= 0 TAD
bit 7
ADRC: A/D Conversion Clock Source bit
1= A/D internal RC clock
0= Clock derived from system clock
bit 6
Unimplemented: Read as ’0’
bit 5-0
ADCS<5:0>: A/D Conversion Clock Select bits
111111= TQ·2·(ADCS<5:0> +1) = 128·TQ
······
000001= TQ·2·(ADCS<5:0> +1) = 4·TQ
000000= TQ·2·(ADCS<5:0> +1) = 2·TQ
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
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REGISTER 22-4: ADCHS: A/D INPUT SELECT REGISTER
Upper Byte:
U-0
U-0
U-0
R/W-0
R/W-0
CH0SB3 CH0SB2 CH0SB1 CH0SB0
bit 8
R/W-0
R/W-0
R/W-0
—
—
—
CH0NB
bit 15
Lower Byte:
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
CH0NA
CH0SA3 CH0SA2 CH0SA1 CH0SA0
bit 7
bit 0
bit 15-13 Unimplemented: Read as '0'
bit 12
CH0NB: Channel 0 Negative Input Select bit for SAMPLE B
Same definition as bit <4>
bit 11-8 CH0SB<3:0>: Channel 0 Positive Input Select bit for SAMPLE B
Same definition as bits <3:0>
bit 7-5
bit 4
Unimplemented: Read as '0'
CH0NA: Channel 0 Negative Input Select bit for SAMPLE A
1= Channel 0 negative input is AN1
0= Channel 0 negative input is VREF-
bit 3-0
CH0SA<3:0>: Channel 0 Positive Input Select bit for SAMPLE A
1111 = Channel 0 positive input is AN15
1110 = Channel 0 positive input is AN14
1101 = Channel 0 positive input is AN13
1100 = Channel 0 positive input is AN12
1011 = Channel 0 positive input is AN11
1010 = Channel 0 positive input is AN10
1001 = Channel 0 positive input is AN9
1000 = Channel 0 positive input is AN8
0111 = Channel 0 positive input is AN7
0110 = Channel 0 positive input is AN6
0101 = Channel 0 positive input is AN5
0100 = Channel 0 positive input is AN4
0011 = Channel 0 positive input is AN3
0010 = Channel 0 positive input is AN2
0001 = Channel 0 positive input is AN1
0000 = Channel 0 positive input is AN0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
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REGISTER 22-5: ADPCFG: A/D PORT CONFIGURATION REGISTER
Upper Byte:
R/W-0
PCFG15
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PCFG14
PCFG13
PCFG12
PCFG11 PCFG10 PCFG9
PCFG8
bit 8
Lower Byte:
R/W-0
R/W-0
R/W-0
PCFG5
R/W-0
R/W-0
R/W-0
R/W-0
PCFG1
R/W-0
PCFG7
PCFG6
PCFG4
PCFG3
PCFG2
PCFG0
bit 7
bit 0
bit 15-0 PCFG<15:0>: A/D Port Configuration Control bits
1= Port pin in Digital mode, port read input enabled, A/D input multiplexor connected to AVSS
0= Port pin in Analog mode, port read input disabled, A/D samples pin voltage
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
REGISTER 22-6: ADCSSL: A/D INPUT SCAN SELECT REGISTER
Upper Byte:
R/W-0
CSSL15
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CSSL14
CSSL13
CSSL12
CSSL11 CSSL10
CSSL9
CSSL8
bit 8
Lower Byte:
R/W-0
R/W-0
R/W-0
CSSL5
R/W-0
R/W-0
CSSL3
R/W-0
CSSL2
R/W-0
CSSL1
R/W-0
CSSL7
CSSL6
CSSL4
CSSL0
bit 7
bit 0
bit 15-0 CSSL<15:0>: A/D Input Scan Selection bits
1= Select ANx for input scan
0= Skip ANx for input scan
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
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23.0 10-BIT HIGH SPEED ANALOG-
TO-DIGITAL CONVERTER (A/D)
MODULE
The10-bit high-speed analog-to-digital converter (A/D)
allows conversion of an analog input signal to a corre-
sponding 10-bit digital number. This module is based
on a Successive Approximation Register (SAR) archi-
tecture, and provides a maximum sampling rate of 500
ksps. The A/D module has up to 16 analog inputs,
which are multiplexed into four sample and hold ampli-
fiers. The output of the sample and hold is the input into
the converter, which generates the result. The analog
reference voltage is software selectable to either the
device supply voltage (AVDD/AVSS) or the voltage level
on the (VREF+/VREF-) pin. The A/D converter has a
unique feature of being able to operate while the device
is in SLEEP mode.
The A/D module has six 16-bit registers.
• A/D Control Register1 (ADCON1)
• A/D Control Register2 (ADCON2)
• A/D Control Register3 (ADCON3)
• A/D Input Select Register (ADCHS)
• A/D Port Configuration Register (ADPCFG)
• A/D Input Scan Selection Register (ADCSSL)
The ADCON1, ADCON2 and ADCON3 registers con-
trol the operation of the A/D module. The ADCHS reg-
ister selects the input channels to be converted. The
ADPCFG register configures the port pins as analog
inputs or as digital I/O. The ADCSSL register selects
inputs for scanning.
Note: The SSRC<2:0>, ASAM, SMPI<3:0>,
BUFM and ALTS bits, as well as the
ADCON3 and ADCSSL registers, must not
be written to while ADON = 1. This would
lead to indeterminate results.
The block diagram of the A/D module is shown in
Figure 23-1.
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FIGURE 23-1:
10-BIT HIGH SPEED A/D FUNCTIONAL BLOCK DIAGRAM
AVDD AVSS
VREF+
VREF-
CHA0
CHA6
AN0
AN1
+
S/H
-
CHA
ADC
CHA1
CHA7
CHAG
10-Bit Result
Conversion Logic
CHB2
CHB8
AN2
AN3
+
CHB
S/H
CHB3
CHB9
CHBG
-
16-word, 10-bit
Dual Port
RAM
CHC4
CHC10
AN4
AN5
+
CHC
S/H
CHC5
CHC11
CHCG
CHA,CHB,
CHC,CH0
-
Sample/Sequence
Control
Sample
0000
0001
0010
0011
Input
Switches
Input Mux
Control
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
AN6
AN7
AN8
AN9
AN10
AN11
AN12
AN13
AN14
AN15
+
CH0
S/H
CH0G
CH0R
-
DS70032B-page 278
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The CHPS bits selects how many channels are sam-
pled. This can vary from 1, 2 or 4 channels. If CHPS
selects 1 channel, the CH0 channel will be sampled
and at the sample clock, CH0 will be converted. The
result is stored in the buffer. If CHPS selects 2 chan-
nels, the CH0 and CHA channels will be sampled and
converted. If CHPS selects 4 channels, the CH0, CHA,
CHB and CHC channels will be sampled and
converted.
23.1 A/D Result Buffer
The module contains a 16-word dual port RAM, called
ADRES<15:0>, to buffer the A/D results. The RAM is
10-bits wide, but is read into different format 16-bit words.
Only word writes are allowed to the result buffer. If byte
writes are attempted, the results are indeterminate.
23.2 Conversion Operation
The SMPI bits will select how many sample clocks
occur before an interrupt occurs. This can vary from 1
sample per interrupt to 16 samples per interrupt.
After the A/D module has been configured as desired, the
sampling is started by setting the SAMP bit. Various
sources, such as a programmable bit, timer time-outs
and external events, will terminate sampling and start a
conversion. When the A/D conversion is completed, the
result is loaded into ADRES<15:0>, the CONV bit is
cleared, and if, at the correct number of samples as spec-
ified by the SMPI bit, the A/D interrupt flag ADIF is set.
The user cannot program a combination of CHPS and
SMPI bits that specifies more than 16 conversions per
interrupt or 8 conversions per interrupt depending on
the BUFM bit. The BUFM bit, when set, will split the
16-word results buffer (ADRES) into two 8-word
groups. Writing to the 8-word buffers will be alternated
on each interrupt event. Use of the BUFM bit will
depend on how much time is available for moving data
out of the buffers after the interrupt, as determined by
the application.
The following steps should be followed for doing an
A/D conversion:
1. Configure the A/D module:
• Configure analog pins/voltage reference/and
digital I/O
If the processor can quickly unload a full buffer within
the time it takes to sample and convert one channel,
the BUFM bit can be 0 and up to 16 conversions may
be done per interrupt. The processor will have one
sample and conversion time to move the sixteen
conversions.
• Select A/D input channels
• Select A/D conversion clock
• Select A/D conversion trigger
• Turn on A/D module
2. Configure A/D interrupt (if required):
• Clear ADIF bit
If the processor cannot unload the buffer within the
sample and conversion time, the BUFM bit should be 1.
For example, if SMPI<3:0> (ADCON2<5:2>) = 0111,
then eight conversions will be loaded into 1/2 of the
buffer, following which, an interrupt occurs. The next
eight conversions will be loaded into the other 1/2 of the
buffer. The processor will have the entire time between
interrupts to move the eight conversions.
• Select A/D interrupt priority
3. Start sampling.
4. Wait the required sampling time.
5. Trigger sample end, start conversion:
• Module sets CONV bit
6. Wait for A/D conversion to complete, by either:
• Polling for the CONV bit to be cleared
• Waiting for the A/D interrupt
The ALTS bit can be used to alternate the inputs
selected during the sampling sequence. If the ALTS bit
is 0, only the SAMPLE A inputs are selected for sam-
pling. If the ALTS bit is 1 and SMPI<3:0> = 0000, on
the first sample/convert sequence, the SAMPLE A
inputs are selected, and on the next sample/convert
sequence, the SAMPLE B inputs are selected.
7. Read A/D result buffer, clear ADIF if required.
23.3 Selecting the Conversion
Sequence
Several groups of control bits select the sequence that
the A/D connects inputs to the sample/hold channels,
converts channels, writes the buffer memory, and gen-
erates interrupts. The sequence is controlled by the
sampling clocks.
The CSCNA bit (ADCON2<10>) will allow the CH0
channel inputs to be scanned across a selected num-
ber of analog inputs during SAMPLE A samples. The
inputs are selected by the ADCSSL register. If a partic-
ular bit in the ADCSSL register is ‘1’, the corresponding
input is selected. The inputs are always scanned from
lower to higher numbered inputs, starting after each
interrupt occurs. If the number of inputs selected is
greater than the number of samples taken per interrupt,
the higher numbered inputs are unused.
The SIMSAM bit controls the sample/convert sequence
for multiple channels. If the SIMSAM bit is 0, the two or
four selected channels are sampled and converted
sequentially, with two or four sample clocks. If the
SIMSAM bit is 1, two or four selected channels are
sampled simultaneously, with one sample clock. The
channels are then converted sequentially. Obviously, if
there is only 1 channel selected, the SIMSAM bit is not
applicable.
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23.4 Programming the Start-of-
Conversion Trigger
23.6 Selecting the A/D Conversion Clock
The A/D conversion requires 11 TAD. The source of the
A/D conversion clock is software selected using a six
bit counter. There are 64 possible options for TAD.
The sample trigger will terminate sampling and start the
requested conversions.
TAD = TCY * (0.5*(ADCS<5:0> +1))
The SSRC<2:0> bits select the source of the sample
trigger.
The internal RC oscillator is selected by setting the
ADRC bit.
When SSRC<2:0> = 000, the sample trigger is under
software control. Clearing the SAMP bit will cause the
sample trigger.
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 150 nsec. Table 23-1 shows the resultant TAD times
derived from the device operating frequencies and the
A/D clock source selected.
When SSRC<2:0> = 111, the sample trigger is under
A/D clock control. The SAMC bits select the number of
A/D clocks between the start of sampling and the start
of conversion. This provides the fastest conversion
rates on multiple channels. SAMC must always be at
least 1 clock cycle.
Other trigger sources can come from timer modules or
external interrupts.
The SSRC bits provide for up to 6 alternate sources of
sample trigger.
23.5 Aborting a Conversion
Clearing the CONV bit during a conversion will abort
the current conversion and stop the sampling sequenc-
ing until the next sampling trigger. The ADRES will not
be updated with the partially completed A/D conversion
sample. That is, the ADRES will continue to contain the
value of the last completed conversion (or the last
value written to the ADRES register).
If the clearing of the CONV bit coincides with an auto
start, the clearing has a higher priority.
After the A/D conversion is aborted, a 2TAD wait is
required before the next sampling may be started by
setting the SAMP bit.
If sequential sampling is specified, the A/D will continue
at the next sample pulse which corresponds with the
next channel converted. If simultaneous sampling is
specified, the A/D will continue with the next multi-
channel group conversion sequence.
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TABLE 23-1: TYPICAL TAD VS. DEVICE OPERATING FREQUENCIES
AD Clock Interval (TAD /TCONV)
AD Clock Source Select
Device TCY/Device MIPS/TQ/FOSC
33.33 nsec/
30 MIPS/
8.33 nsec/
120 MHz
40 nsec/
25 MIPS/
10 nsec/
100 MHz
80 nsec/
12.5 MIPS/
20 nsec/
50 MHz
160 nsec/
1000 nsec/
1 MIPS/
250 nsec/
4 MHz
6.25 MIPS/
40 nsec/
25 MHz
Clock
ADRC ADCS<5:0>
16.67 ns(2)
0.22 µs
33.33 ns(2)
0.44 µs
66.66 ns(2)
0.88 µs
133.32 ns(2)
/
/
/
20 ns(2)
0.26 µs
/
40 ns(2)
0.52 µs
80 ns(2)
/
1.04 µs
160 ns/
/
80 ns(2)
/
1.04 µs
160 ns/
2.08 µs
2 TQ
4 TQ
0
0
0
0
0
0
0
1
000000
000001
000011
000111
001111
011111
111111
xxxxxx
500 ns/
6.5 µs
40 ns(2)
/
1.0 µs/
13 µs
0.52 µs
80 ns(2)
/
2.0 µs(3)
26 µs
4.0 µs(3)
52 µs
8.0 µs(3)
104 µs
16.0 µs(3)
208 µs
/
/
/
8 TQ
320 ns/
4.16 µs
2.08 µs
1.04 µs
160 ns/
2.08 µs
/
640 ns(3)
8.32 µs
/
16 TQ
32 TQ
64 TQ
128 TQ
RC
320 ns/
4.16 µs
1.76 µs
266.64 ns/
3.52 µs
640 ns(3)
8.32 µs
1.28 µs(3)
/
1.28 µs(3)
2.56 µs(3)
5.12 µs(3)
320 ns/
4.16 µs
533.28 ns(3)
7.04 µs
1066.56 ns(3)
14.08 µs
200 - 400 ns/
/
640 ns(3)
8.32 µs
1280 ns(3)
16.64 µs
/
/
/
/
/
2.56 µs(3)
32.0 µs(3)
416 µs
200 - 400 ns/
200 - 400 ns/
200 - 400 ns/
200 - 400 ns/
3.9 µs(1,4)
3.9 µs(1,4)
3.9 µs(1,4)
3.9 µs(1,4)
3.9 µs(1)
Note 1: The RC source has a typical TAD time of 300 ns for VDD > 3.0V.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: A/D cannot meet full accuracy with RC clock source and FOSC > 20 MHz
2002 Microchip Technology Inc.
Advance Information
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dsPIC30F
EQUATION 23-1: A/D SAMPLING TIME
EQUATIONS
23.7 A/D Sampling Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 23-2. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impedance varies over the device voltage
(VDD), see Figure 23-2. The impedance for analog
sources must be small enough to meet accuracy
requirements at the given speed. After the analog input
channel is selected (changed), this sampling must be
done before the conversion can be started.
(-TC/CHOLD (RIC+RSS+RS))
∆VO
=
=
=
=
=
=
=
=
=
∆VI • (1 - e
)
(-TC/CHOLD (RIC+RSS+RS))
1 - (∆VO / ∆VI)
∆VI
e
n • LSB
∆VO
n • LSB - 1/2 LSB
(n • LSB - 1/2 LSB) / n • LSB
∆VO / ∆VI
1 - (∆VO / ∆VI)
1 / 2n
1 / 2n
(-TC/CHOLD (RIC+RSS+RS)
e
)
TC
CHOLD • (RIC+RSS+RS) • -In(1/2 • n)
TSMP
Amplifier Settling Time
+ Holding Capacitor Charging Time (TC)
+Temperature Coefficient
†
† The temperature coefficient is only required for
temperatures > 25°C.
To calculate the minimum sampling time, Equation 23-1
may be used. This equation assumes that the input is
stepped some multiple (n) of the LSB step size and the
output must be captured to within 1/2 LSb error (2096
steps for 10-bit A/D). The 1/2 LSb error is the maximum
error allowed for the A/D to meet its specified resolution.
TSMP
=
0.5 ms
+ CHOLD • (RIC+RSS+RS) • -In(1/2 • n)
+ [(Temp - 25°C)(0.05 ms/°C)]
The CHOLD is assumed to be 5 pF for the A/D.
FIGURE 23-2:
ANALOG INPUT MODEL
VDD
Sampling
Switch
VT = 0.6V
ANx
SS
RIC ≤ 250Ω
RSS
Rs
CHOLD
= DAC capacitance
= 5 pF
CPIN
5 pF
VA
I leakage
500 nA
VT = 0.6V
VSS
Sampling
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
Legend: CPIN
VT
= input capacitance
= threshold voltage
Switch
(Rss k
Ω
)
I leakage = leakage current at the pin due to
various junctions
RIC
SS
= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)
CHOLD
2
3
4
5
6
VDD (V)
DS70032B-page 282
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dsPIC30F
The A/D module can operate during SLEEP mode, if
the A/D clock source is set to RC (ADRC = 1). When
the RC clock source is selected, the A/D module waits
for one instruction cycle before starting the conversion.
This allows the SLEEP instruction to be executed,
which eliminates all digital switching noise from the
conversion. When the conversion is completed, the
CONV bit will be cleared and the result loaded into the
ADRES register.
23.8 Module Power-down Modes
The module has 3 internal Power modes.
When the ADON bit is 1, the module is in Active mode
and is fully powered and functional.
When ADON is 0 and ADSTBY is 1, the module is in
Standby mode. In Standby mode, the digital portions of
the module are active; however, the analog portions
are powered down, including the bias generators.
If the A/D interrupt is enabled, the device will wake-up
from SLEEP. If the A/D interrupt is not enabled, the
A/D module will then be turned off, although the ADON
bit will remain set.
When ADON is 0 and ADSTBY is 0, the module is in Off
mode. The digital and analog portions of the circuit are
disabled for maximum current savings.
In order to return to the Active mode from Standby or
Off mode, the user must wait for the bias generators to
stabilize.
23.9.2
A/D OPERATION DURING CPU IDLE
MODE
For the A/D, the ADSIDL bit selects if the module will
stop on IDLE or continue on IDLE. If ADSIDL = 0, the
module will continue operation on assertion of IDLE
mode. If ADSIDL = 1, the module will stop on IDLE.
23.9 A/D Operation During CPU SLEEP
and IDLE Modes
23.9.1
A/D OPERATION DURING CPU
SLEEP MODE
23.10 Effects of a RESET
When the device enters SLEEP mode, all clock
sources to the module are shut-down and stay at logic
‘0’.
A device RESET forces all registers to their RESET
state. This forces the A/D module to be turned off, and
any conversion and sampling sequence are aborted.
The values that are in the ADRES registers are not
modified. The A/D result register will contain unknown
data after a Power-on Reset.
If SLEEP occurs in the middle of a conversion, the
conversion is aborted. The converter will not continue
with a partially completed conversion on exiting from
SLEEP mode.
Register contents are not affected by the device enter-
ing or leaving SLEEP mode.
2002 Microchip Technology Inc.
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dsPIC30F
23.11 Output Formats
The A/D result is 10 bits wide. The data buffer RAM is
also 10 bits wide. The 10-bit data can be read in one of
four different formats. The FORM<1:0> bits select the
format. Each of the output formats translates to a 16-bit
result on the data bus.
Write data will always be right justified (integer) format.
FIGURE 23-3:
A/D OUTPUT DATA FORMATS
RAM contents:
d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
Read to Bus:
Signed Fractional (1.15)
Fractional (1.15)
Signed Integer
Integer
d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
0
0
0
0
0
0
0
0
0
0
0
0
d09 d09 d09 d09 d09 d09 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
0
0
0
0
0
0
d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
23.12 Configuring Analog Port Pins
23.13 Connection Considerations
The use of the ADCON1 and TRIS registers control the
operation of the A/D port pins. The port pins that are
desired as analog inputs must have their correspond-
ing TRIS bit set (input). If the TRIS bit is cleared (out-
put), the digital output level (VOH or VOL) will be
converted.
Since the analog inputs employ ESD protection, they
have diodes to VDD and VSS. This requires that the
analog input must be between VDD and VSS. If the input
voltage exceeds this range by greater than 0.3V (either
direction), one of the diodes becomes forward biased
and it may damage the device if the input current spec-
ification is exceeded.
The A/D operation is independent of the state of the
CHS<3:0> bits and the TRIS bits.
An external RC filter is sometimes added for anti-
aliasing of the input signal. The R component should be
selected to ensure that the sampling time requirements
are satisfied. Any external components connected (via
high impedance) to an analog input pin (capacitor,
zener diode, etc.) should have very little leakage
current at the pin.
When reading the port register, all pins configured as
analog input channel will read as cleared (a low level).
Pins configured as digital inputs, will convert an analog
input. Analog levels on a digitally configured input will
not affect the conversion accuracy.
Analog levels on any pin that is defined as a digital
input (including the AN pins), may cause the input
buffer to consume current that exceeds the device
specifications.
DS70032B-page 284
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2002 Microchip Technology Inc.
Advance Information
DS70032B-page 285
dsPIC30F
REGISTER 23-1: ADCON1: A/D CONTROL REGISTER1
Upper Byte:
R/W-0
ADON
R/W-0
R/W-0
R/W-0
U-0
U-0
R/W-0
R/W-0
—
ADSIDL
ADSTBY
—
—
FORM1
FORM0
bit 15
bit 8
Lower Byte:
R/W-0
R/W-0
SSRC1
R/W-0
U-0
R/W-0
SIMSAM
R/W-0
ASAM
R/W-0
HC, HS
R/C-0
HC, HS
SSRC2
SSRC0
—
SAMP
CONV
bit 7
bit 0
bit 15
ADON: A/D Operating Mode bit
1= A/D converter module is operating
0= A/D converter is in Standby mode or off
bit 14
bit 13
Unimplemented: Read as '0'
ADSIDL: Stop in IDLE Mode bit
1= Discontinue module operation when device enters IDLE mode
0= Continue module operation in IDLE mode
bit 12
ADSTBY: A/D Standby Mode bit
1= If ADON = 0, A/D converter module in Standby mode. Analog circuits powered down.
0= If ADON = 0, A/D converter is shut-off and consumes no operating current
bit 11-10 Unimplemented: Read as '0'
bit 9-8
FORM<1:0>: Data Output Format bits
11= Signed Fractional (DOUT = sddd dddd dd00 0000where s= .NOT.d<9>)
10= Fractional (DOUT = dddd dddd dd00 0000)
01= Signed Integer (DOUT = ssss sssd dddd ddddwhere s= .NOT.d<9>)
00= Integer (DOUT = 0000 00dd dddd dddd)
bit 7-5
SSRC<2:0>: Sample Clock Source Select bits
111= Internal counter ends sampling and starts conversion (auto convert)
110= Reserved
101= Reserved
100= Reserved
011= Motor Control PWM interval ends sampling and starts conversion
010= GP Timer compare ends sampling and starts conversion
001= Active transition on INT pin ends sampling and starts conversion
000= Clearing sample bit ends sampling and starts conversion
bit 4
bit 3
Unimplemented: Read as '0'
SIMSAM: Simultaneous Sample Select bit (only applicable when CHPS = 01or 1x)
1= Samples CH0, CHA, CHB, CHC simultaneously (when CHPS = 1x)
- or -
Samples CH0 and CHA simultaneously (when CHPS = 01)
0= Samples multiple channels individually in sequence
bit 2
bit 1
ASAM: A/D Sample Auto Start bit
1= Sampling begins immediately after last conversion. SAMP bit is auto set.
0= Sampling begins when SAMP bit set
SAMP: A/D Sample Enable bit
1= A/D sample/hold amplifiers are sampling
0= A/D sample/hold amplifiers are holding
DS70032B-page 286
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REGISTER 23-1: ADCON1: A/D CONTROL REGISTER1 (Continued)
bit 0 CONV: A/D Conversion Status bit
1= A/D conversion cycle in progress. Cleared by hardware when A/D conversion complete.
0= A/D conversion completed/not in progress.
Legend:
HC = Hardware Clear
R = Readable bit
HS = Hardware Set
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
-n = Value at POR
2002 Microchip Technology Inc.
Advance Information
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dsPIC30F
REGISTER 23-2: ADCON2: A/D CONTROL REGISTER2
Upper Byte:
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
VCFG2
VCFG1
VCFG0
OFFCAL
—
CSCNA
CHPS1
CHPS0
bit 15
bit 8
Lower Byte:
R-0
U-0
R/W-0
SMPI3
R/W-0
SMPI2
R/W-0
SMPI1
R/W-0
SMPI0
R/W-0
BUFM
R/W-0
ALTS
BUFS
—
bit 7
bit 0
bit 15-13 VCFG<2:0>: Voltage Reference Configuration bits
A/D VREF+
A/D VREF-
000
001
010
011
100
101
101
111
AVDD
External VREF+
AVDD
AVSS
AVSS
External VREF-
External VREF-
Internal VRL
AVSS
External VREF+
Internal VRH
Internal VRL
Internal VRH
AVDD
AVSS
Internal VRL
Note: Shaded regions in the table are unused. If these options are selected, the A/D references
will default to AVDD and AVSS.
bit 12
OFFCAL: Selects Offset Calibration Mode bit
1= + and - inputs of channel sample/hold shorted together
0= + and - inputs of channel sample/hold normal
bit 11
bit 10
Unimplemented: Read as '0'
CSCNA: Scan Input Selections for CH0+ during SAMPLE A bit
1= Scan inputs
0= Do not scan inputs
bit 9-8
bit 7
CHPS<1:0>: Selects Channels Utilized bits
1x= Converts CH0, CHA, CHB and CHC
01= Converts CH0 and CHA
00= Converts CH0
BUFS: Buffer Fill Status bit
Only valid when BUFM =1
1= A/D is currently filling buffer 0x8 - 0xF, user should access data in 0x0 - 0x7
0= A/D is currently filling buffer 0x0 - 0x7, user should access data in 0x8 - 0xF
bit 6
Unimplemented: Read as '0'
bit 5-2
SMPI<3:0>: Selects Number of Samples per Interrupt bits
1111= Interrupts at the completion of conversion for each 16th sample
1110= Interrupts at the completion of conversion for each 15th sample
.....
0001= Interrupts at the completion of conversion for each 2nd sample
0000= Interrupts at the completion of conversion for each sample
bit 1
BUFM: Buffer Fill Mode Select bit
1= Starts buffer filling at address 0x0 on first interrupt and 0x8 on next interrupt
0= Always starts filling buffer at address 0x0
DS70032B-page 288
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REGISTER 23-2: ADCON2: A/D CONTROL REGISTER2 (Continued)
bit 0 ALTS: Alternate Input Sample Mode Select bit
1= Uses channel input selects for SAMPLE A on first sample and SAMPLE B on next sample
0= Always uses channel input selects for SAMPLE A
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
2002 Microchip Technology Inc.
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dsPIC30F
REGISTER 23-3: ADCON3: A/D CONTROL REGISTER3
Upper Byte:
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
SAMC4
SAMC3
SAMC2
SAMC1
SAMC0
bit 15
bit 8
Lower Byte:
R/W-0
ADRC
U-0
R/W-0
ADCS5
R/W-0
ADCS4
R/W-0
ADCS3
R/W-0
R/W-0
ADCS1
R/W-0
—
ADCS2
ADCS0
bit 7
bit 0
bit 15-13 Unimplemented: Read as '0'
bit 12-8 SAMC<4:0>: Auto Sample Time bits
11111= 31 TAD
·····
00001= 1 TAD
00000= 0 TAD
bit 7
ADRC: A/D Conversion Clock Source bit
1= A/D internal RC clock
0= Clock derived from system clock
bit 6
Unimplemented: Read as ’0’
bit 5-0
ADCS<5:0>: A/D Conversion Clock Select bits
111111= TQ·2·(ADCS<5:0> +1) = 128·TQ
······
000001= TQ·2·(ADCS<5:0> +1) = 4·TQ
000000= TQ·2·(ADCS<5:0> +1) = 2·TQ
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
DS70032B-page 290
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REGISTER 23-4: ADCHS: A/D INPUT SELECT REGISTER
Upper Byte:
R/W-0
CHXNB1
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
CH0SB3 CH0SB2 CH0SB1 CH0SB0
bit 8
R/W-0
R/W-0
R/W-0
CHXNB0
CHXSB
CH0NB
Lower Byte:
R/W-0
CHXNA1
bit 7
R/W-0
R/W-0
CHXSA
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHXNA0
CH0NA
CH0SA3 CH0SA2 CH0SA1 CH0SA0
bit 0
bit 15-14 CHXNB<1:0>: Channel A, B, C Negative Input Select for SAMPLE B bits
Same definition as bits <6:7>
bit 13
bit 12
CHXSB: Channel A, B, C Positive Input Select for SAMPLE B bit
Same definition as bit <5>
CH0NB: Channel 0 Negative Input Select for SAMPLE B bit
Same definition as bit <4>
bit 11-8 CH0SB<3:0>: Channel 0 Positive Input Select for SAMPLE B bits
Same definition as bits <3:0>
bit 6-7
CHXNA<1:0>: Channel A, B, C Negative Input Select for SAMPLE A bits
11= CHA negative input is AN9, CHB negative input is AN10, CHC negative input is AN11
10= CHA negative input is AN6, CHB negative input is AN7, CHC negative input is AN8
0x= CHA, CHB, CHC negative input is VREF-
bit 5
CHXSA: Channel A, B, C Positive Input Select for SAMPLE A bit
1= CHA positive input is AN3, CHB positive input is AN4, CHC positive input is AN5
0= CHA positive input is AN0, CHB positive input is AN1, CHC positive input is AN2
bit 4
CH0NA: Channel 0 Negative Input Select for SAMPLE A bit
1= Channel 0 negative input is AN1
0= Channel 0 negative input is VREF-
bit 3-0
CH0SA<3:0>: Channel 0 Positive Input Select for SAMPLE A bit
1111 = Channel 0 positive input is AN15
1110 = Channel 0 positive input is AN14
1101 = Channel 0 positive input is AN13
1100 = Channel 0 positive input is AN12
1011 = Channel 0 positive input is AN11
1010 = Channel 0 positive input is AN10
1001 = Channel 0 positive input is AN9
1000 = Channel 0 positive input is AN8
0111 = Channel 0 positive input is AN7
0110 = Channel 0 positive input is AN6
0101 = Channel 0 positive input is AN5
0100 = Channel 0 positive input is AN4
0011 = Channel 0 positive input is AN3
0010 = Channel 0 positive input is AN2
0001 = Channel 0 positive input is AN1
0000 = Channel 0 positive input is AN0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
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dsPIC30F
REGISTER 23-5: ADPCFG: A/D PORT CONFIGURATION REGISTER
Upper Byte:
R/W-0
PCFG15
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PCFG14
PCFG13
PCFG12
PCFG11 PCFG10 PCFG9
PCFG8
bit 8
Lower Byte:
R/W-0
R/W-0
R/W-0
PCFG5
R/W-0
R/W-0
R/W-0
R/W-0
PCFG1
R/W-0
PCFG7
PCFG6
PCFG4
PCFG3
PCFG2
PCFG0
bit 7
bit 0
bit 15-0 PCFG<15:0>: A/D Port Configuration Control bits
1= Port pin in Digital mode, port read input enabled, A/D input multiplexor connected to AVSS
0= Port pin in Analog mode, port read input disabled, A/D samples pin voltage
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
REGISTER 23-6: ADCSSL: A/D INPUT SCAN SELECT REGISTER
Upper Byte:
R/W-0
CSSL15
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CSSL14
CSSL13
CSSL12
CSSL11 CSSL10
CSSL9
CSSL8
bit 8
Lower Byte:
R/W-0
R/W-0
R/W-0
CSSL5
R/W-0
R/W-0
CSSL3
R/W-0
CSSL2
R/W-0
CSSL1
R/W-0
CSSL7
CSSL6
CSSL4
CSSL0
bit 7
bit 0
bit 15-0 CSSL<15:0>: A/D Input Scan Selection bits
1= Select ANx for input scan
0= Skip ANx for input scan
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
DS70032B-page 292
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dsPIC30F
SLEEP mode is designed to offer a very low current
Power-down mode. The user can wake-up from
SLEEP through external RESET, Watchdog Timer
Wake-up or through an interrupt. Several oscillator
options are also made available to allow the part to fit
the application. In the IDLE mode, the clock sources
are still active, but the CPU is shut-off. The RC oscilla-
tor option saves system cost, while the LP crystal
option saves power. A set of configuration bits are used
to select various options
24.0 SYSTEM INTEGRATION
There are several features intended to maximize sys-
tem reliability, minimize cost through elimination of
external components, provide power saving operating
modes and offer code protection:
• Oscillator Selection
• RESET
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Programmable Brown-out Reset (BOR)
• Watchdog Timer (WDT)
• Power Saving Modes (SLEEP and IDLE)
• Code Protection
24.1 Overview
The dsPIC30F oscillator system has the following mod-
ules and features:
• Various external and internal oscillator options as
clock sources
• Unit ID Locations
• An on-chip PLL to boost internal operating
• In-Circuit Serial Programming (ICSP)
frequency
• A clock switching mechanism between various
clock sources
dsPIC30F devices have a Watchdog Timer, which is
permanently enabled via the configuration bits, or it can
be software controlled. It runs off its own RC oscillator
for added reliability. There are two timers that offer nec-
essary delays on power-up. One is the Oscillator Start-
up Timer (OST), intended to keep the chip in RESET
until the crystal oscillator is stable. The other is the
Power-up Timer (PWRT), which provides a delay on
power-up only, designed to keep the part in RESET
while the power supply stabilizes. With these two tim-
ers on-chip, most applications need no external
RESET circuitry.
• Programmable clock post-scaler for system
power savings
• A fail safe clock monitor (FSCM) that detects
clock failure and takes fail safe measures
• Clock Control Register OSCCON
• Configuration bits for main oscillator selection
Table 24-1 provides a summary of the dsPIC30F Oscil-
lator Operating modes.
TABLE 24-1: OSCILLATOR OPERATING MODES
Oscillator Mode
Description
XTL
200 kHz - 4 MHz crystal on OSC1:OSC2.
XT
4 MHz - 10 MHz crystal on OSC1:OSC2.
XT w/ PLL 4x
XT w/ PLL 8x
XT w/ PLL 16x
LP
4 MHz - 10 MHz crystal on OSC1:OSC2. 4x PLL enabled.
4 MHz - 10 MHz crystal on OSC1:OSC2. 8x PLL enabled.
4 MHz - 10 MHz crystal on OSC1:OSC2. 16x PLL enabled(1)
.
32 kHz crystal on SOSC1:SOSC2(2)
.
HS
10 MHz - 25 MHz crystal.
EC
External clock input (0 - 40 MHz).
ECIO
External clock input (0 - 40 MHz). OSC2 pin is I/O.
EC w/ PLL 4x
EC w/ PLL 8x
EC w/ PLL 16x
ERC
External clock input (0 - 40 MHz). OSC2 pin is I/O. 4x PLL enabled(1)
External clock input (0 - 40 MHz). OSC2 pin is I/O. 8x PLL enabled(1)
.
.
External clock input (0 - 40 MHz). OSC2 pin is I/O. 16x PLL enabled(1)
External RC oscillator. OSC2 pin is FOSC/4 output(3)
.
.
ERCIO
External RC oscillator. OSC2 pin is I/O(3)
.
FRC
8 MHz internal RC Oscillator.
LPRC
32 kHz internal RC Oscillator.
Note 1: dsPIC30F maximum operating frequency of 120 MHz must be met.
2: LP oscillator can be conveniently shared as system clock as well as real-time clock for Timer1.
3: Requires external R and C. Frequency operation up to 4 MHz.
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 293
dsPIC30F
A simplified diagram of the oscillator system is shown
in Figure 24-1.
missible clock sources. The OSCCON register con-
trols the clock switching and reflects system clock
related status bits.
Configuration bits determine the clock source upon
Power-on Reset (POR) and Brown-out Reset (BOR).
Thereafter, clock source can be changed between per-
FIGURE 24-1:
OSCILLATOR SYSTEM BLOCK DIAGRAM
Oscillator Configuration bits
PWRSAVInstruction
Wake-up Request
FPLL
OSC1
OSC2
PLL
Primary
Oscillator
PLL
x4, x8, x16
Lock
COSC<1:0>
Primary Osc
NOSC<1:0>
OSWEN
Primary
Oscillator
Stability Detector
Oscillator
Start-up
Timer
POR Done
Clock
Switching
and Control
Programmable
Clock Divider
Secondary Osc
System
Clock
Block
SOSC1
SOSC2
Secondary
Oscillator
32 kHz LP
Oscillator
2
Stability Detector
POST<1:0>
FRC
Internal Fast RC
Oscillator (FRC)
Internal Low
Power RC
LPRC
Oscillator (LPRC)
CF
Fail Safe Clock
Monitor (FSCM)
FCKSM<1:0>
2
Oscillator Trap
to Timer1
DS70032B-page 294
AdvanceInformation
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dsPIC30F
24.2 Oscillator Configurations
24.2.1
INITIAL CLOCK SOURCE
SELECTION
While coming out of Power-on Reset or Brown-out
Reset, the device selects its clock source based on:
a) FOS<1:0> configuration bits that select one of
four oscillator groups
b) AND FPR<3:0> configuration bits that select
one of 13 oscillator choices within the primary
group.
The selection is as shown in Table 24-2.
TABLE 24-2: CONFIGURATION BIT VALUES FOR CLOCK SELECTION
Oscillator
OSC2
FPR0
Oscillator Mode
FOS1
FOS0
FPR3
FPR2
FPR1
Source
Function
EC
Primary
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
1
1
1
1
1
1
0
0
0
0
0
0
-
1
1
1
1
1
0
0
1
1
1
1
0
0
-
1
0
0
1
1
0
0
0
0
1
1
0
1
-
1
0
1
0
1
1
0
0
1
0
1
X
X
-
CLKOUT
I/O
ECIO
Primary
Primary
Primary
Primary
Primary
Primary
Primary
Primary
Primary
Primary
Primary
Primary
Secondary
Internal FRC
EC w/ PLL 4x
EC w/ PLL 8x
EC w/ PLL 16x
ERC
I/O
I/O
I/O
CLKOUT
I/O
ERCIO
XT
OSC2
OSC2
OSC2
OSC2
OSC2
OSC2
(Notes 1, 2)
(Notes 1, 2)
(Notes 1, 2)
XT w/ PLL 4x
XT w/ PLL 8x
XT w/ PLL 16x
XTL
HS
LP
FRC
-
-
-
-
LPRC
Internal
LPRC
-
-
-
-
Note 1: OSC2 pin function is determined by the Primary Oscillator mode selection (FPR<3:0>).
2: Note that OSC1 pin cannot be used as an I/O pin, even if the secondary oscillator or an internal clock
source is selected at all times.
2002 Microchip Technology Inc.
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dsPIC30F
The PLL features a lock output, which is asserted when
the PLL enters a phase locked state. Should the loop
fall out of lock (e.g., due to noise), the lock signal will be
rescinded. The state of this signal is reflected in the
read only LOCK bit in the OSCCON register.
24.2.2
OSCILLATOR START-UP TIMER
(OST)
In order to ensure that a crystal oscillator (or ceramic
resonator) has started and stabilized, an oscillator
start-up timer is included. It is a simple 10-bit counter
that counts 1024 TOSC cycles before releasing the
oscillator clock to the rest of the system. The time-out
period is designated as TOST. The TOST time is
involved every time the oscillator has to restart, i.e., on
POR, BOR and wake-up from SLEEP. The oscillator
start-up timer is applied to the LP Oscillator, XT, XTL,
and HS modes (upon wake-up from SLEEP, POR and
BOR) for the Primary Oscillator.
24.2.5
FAST RC OSCILLATOR (FRC)
The FRC oscillator is a fast (8 MHz nominal) internal
RC oscillator. This oscillator is intended to provide rea-
sonable device operating speeds without the use of an
external crystal, ceramic resonator, or RC network.
The dsPIC30F operates from the FRC Oscillator when-
ever the Current Oscillator Selection control bits in the
OSCCON register (OSCCON<13:12>) are set to ‘01’.
24.2.3
LP OSCILLATOR CONTROL
24.2.6
LOW POWER RC OSCILLATOR
(LPRC)
Enabling the LP oscillator is controlled by two
elements:
The LPRC oscillator is a component of the Watchdog
Timer (WDT) and oscillates at a nominal frequency of
512 kHz. The LPRC Oscillator is the clock source for
the Power-up Timer (PWRT) circuit, WDT, and clock
monitor circuits. It may also be used to provide a low
frequency clock source option for applications where
power consumption is critical, and timing accuracy is
not required
1. The current oscillator group bits COSC<1:0>.
2. The LPOSCEN bit (OSCON register).
In normal operating mode, the LP oscillator is ON if:
•
COSC<1:0> = 00(LP selected as main oscillator)
or
LPOSCEN = 1
•
In SLEEP mode, the LP oscillator is ON if
The LPRC Oscillator is always enabled at a Power-on
Reset, because it is the clock source for the PWRT.
After the PWRT expires, the LPRC Oscillator will
remain ON if one of the following is TRUE:
LPOSCEN = 1.
In IDLE mode, the LP oscillator is ON if:
• COSC<1:0> = 00(LP selected as main oscillator)
or
• The Fail Safe Clock Monitor is enabled
• The WDT is enabled
• LPOSCEN = 1
Keeping the LP oscillator ON at all times allows for a
fast switch to the 32 kHz system clock for lower power
operation. Returning to the faster main oscillator will
still require a start-up time
• The LPRC Oscillator is selected as the system
clock via the COSC<1:0> control bits in the
OSCCON register
If one of the above conditions is not true, the LPRC will
shut-off after the PWRT expires.
24.2.4
PLL
Note 1: OSC2 pin function is determined by the
Primary Oscillator mode selection
(FPR<3:0>).
The PLL multiplies the clock which is generated by the
primary oscillator. The PLL is selectable to have either
gains of x4, x8, and x16. Input and output frequency
ranges are summarized in the table below.
2: Note that OSC1 pin cannot be used as an
I/O pin, even if the secondary oscillator or
an internal clock source is selected at all
times.
TABLE 24-3: PLL FREQUENCY RANGE
PLL
FIN
FOUT
Multiplier
4 MHz - 10 MHz
4 MHz - 10 MHz
x4
x8
16 MHz - 40 MHz
32 MHz - 80 MHz
4 MHz - 10 MHz
x16
64 MHz - 160 MHz(1)
Note 1: User must ensure FIN and selected PLL
multiplier does not exceed 120 MHz.
DS70032B-page 296
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dsPIC30F
The OSCCON Register holds the CONTROL and
STATUS bits related to clock switching.
24.2.7
FAIL SAFE CLOCK MONITOR
The Fail Safe Clock Monitor (FSCM) allows the device
to continue to operate even in the event of an oscillator
failure. The FSCM function is enabled by appropriately
programming the FCKSM configuration bits (Clock
Switch and Monitor Selection bits) in the FOSC device
configuration register. If the FSCM function is enabled,
the LPRC Internal oscillator will run at all times (except
during SLEEP mode) and will not be subject to control
by the SWDTEN bit.
• COSC<1:0>: Read only status bits always reflect
the current oscillator group in effect.
• NOSC<1:0>: Control bits which are written to indi-
cate the new oscillator group of choice.
- On POR and BOR, COSC<1:0> and
NOSC<1:0> are both loaded with the Config-
uration bit values FOS<1:0>.
• LOCK: The LOCK status bit indicates a PLL lock.
In the event of an oscillator failure, the FSCM will gen-
erate a Clock Failure Trap event and will switch the sys-
tem clock over to the FRC Oscillator. The user will then
have the option to either attempt to restart the oscillator
or execute a controlled shut-down. The user may
decide to treat the Trap as a warm RESET by simply
loading the RESET address into the oscillator fail trap
vector. In this event, the CF (Clock Fail) status bit
(OSCCON<3>) is also set whenever a clock failure is
recognized.
• CF: Read only status bit indicating if a clock fail
detect has occurred.
• OSWEN: Control bit changes from a ‘0’ to a ‘1’
when a clock transition sequence is initiated.
Clearing the OSWEN control bit will abort a clock
transition in progress (used for hang-up situa-
tions).
If configuration bits FCKSM<1:0> = 1x, then the clock
switching function and the fail safe clock monitor func-
tion are disabled. This is the default configuration bit
setting.
In the event of a clock failure, the WDT is unaffected
and continues to run on the LPRC clock.
If clock switching is disabled, then the FOS<1:0> and
FPR<3:0> bits directly control the oscillator selection
and the COSC<1:0> bits do not control the clock
selection. However, these bits will reflect the clock
source selection.
If the oscillator has a very slow start-up time coming
out of POR, BOR or SLEEP, it is possible that the
PWRT timer will expire before the oscillator has
started. In such cases, the FSCM will be activated and
the FSCM will initiate a Clock Failure Trap, and the
COSC<1:0> bits are loaded with FRC oscillator selec-
tion. This will effectively shut-off the original oscillator
that was trying to start.
24.2.8
PROTECTION AGAINST
ACCIDENTAL WRITES TO OSCCON
A write to the OSCCON register is intentionally made
difficult, because it controls clock switching and clock
scaling.
The user may detect this situation and restart the oscil-
lator in the Clock Fail Trap ISR.
Upon a clock failure detection the FSCM module will
initiate a clock switch to the FRC Oscillator as follows:
To write to the OSCCON low byte, the following code
sequence must be executed without any other instruc-
tions in between:
1. The COSC bits (OSCCON<13:12>) are loaded
with the FRC Oscillator selection value.
• ByteWrite“46h” to OSCCON low
• Byte Write “57h” to OSCCON low
2. CF bit is set (OSCCON<3>).
3. OSWEN control bit (OSCCON<0>) is cleared.
Byte Write is allowed for one instruction cycle. Write
desired value or use bit manipulation instruction.
For the purpose of clock switching, the clock sources
are sectioned into four groups:
To write to the OSCCON high byte, the following
instructions must be executed without any other
instructions in between:
1. Primary
2. Secondary
3. Internal FRC
4. Internal LPRC
• Byte Write“78h” to OSCCON high
• Byte Write“9Ah” to OSCCON high
The user can switch between these functional groups,
but cannot switch between options within a group. If the
primary group is selected, then the choice within the
group is always determined by the FPR<3:0> configu-
ration bits.
Byte Write is allowed for one instruction cycle. Write
“Desired Value” or use bit manipulation instruction.
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 297
dsPIC30F
REGISTER 24-1: OSCCON: OSCILLATOR CONTROL REGISTER
Upper Half:
U-0
U-0
R-y
R-y
U-0
U-0
R/W-y
R/W-y
—
—
COSC1
COSC0
—
—
NOSC1
NOSC0
bit 15
bit 8
Lower Half:
R/W-0
R/W-0
R-0
LOCK
U-0
R/W-0
CF
U-0
R/W-0
R/W-0
POST1
bit 7
POST0
—
—
LPOSCEN OSWEN
bit 0
bit 15-14 Unimplemented: Read as ‘0’
bit 13-12 COSC<1:0>: Current Oscillator Source Status bits
11= Primary oscillator
10= Internal LPRC oscillator
01= Internal FRC oscillator
00= LP crystal 32 kHz crystal oscillator (Timer1)
bit 11-10 Unimplemented: Read as ‘0’
bit 9-8
bit 7-6
bit 5
NOSC<1:0>: New Oscillator Group Selection bits
11= Primary oscillator
10= Internal LPRC oscillator
01= Internal FRC oscillator
00= Low power 32 kHz crystal oscillator (Timer1)
POST<1:0>: Oscillator Postscaler Selection bits
11= Oscillator postscaler divides clock by 64
10= Oscillator postscaler divides clock by 16
01= Oscillator postscaler divides clock by 4
00= Oscillator postscaler does not alter clock
LOCK: PLL Lock Status bit
1= Indicates that PLL is in lock
0= Indicates that PLL is out of lock (or disabled)
bit 4
bit 3
Unimplemented: Read as ‘0’
CF: Clock Fail Status bit
1= FSCM has detected clock failure
0= FSCM has NOT detected clock failure
bit 2
bit 1
Unimplemented: Read as ‘0’
LPOSCEN: 32 kHz LP Oscillator Enable bit
1= LP oscillator is enabled
0= LP oscillator is disabled
bit 0
OSWEN: Oscillator Switch Enable bit
1= Request oscillator switch to selection specified by NOSC<1:0> bits
0= Oscillator switch is complete
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
y = Value set from configuration bits on POR and BOR
DS70032B-page 298
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dsPIC30F
REGISTER 24-2: FOSC: OSCILLATOR SELECTION CONTROL REGISTER
Upper Third:
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 23
bit 16
Middle Third:
R/P-1
R/P-1
FCKSM0
U-0
U-0
U-0
U-0
R/P-1
FOS1
R/P-1
FOS0
FCKSM1
bit 15
—
—
—
—
bit 8
Lower Third:
U-0
—
U-0
U-0
U-0
R/P-1
FPR3
R/P-1
FPR2
R/P-1
FPR1
R/P-1
FPR0
—
—
—
bit 7
bit 0
bit 23-16 Unimplemented: Read as ‘0’
bit 15-14 FCKSM<1:0>: Clock Switching and Monitor Selection bits
1x= Clock switching is disabled, fail safe clock monitor is disabled
01= Clock switching is enabled, fail safe clock monitor is disabled
00= Clock switching is enabled, fail safe clock monitor is enabled
bit 13-10 Unimplemented: Read as ‘0’
bit 9-8
FOS<1:0>: Oscillator Group Selection bits on POR and BOR
11= Primary group (13 choices)
10= Internal LPRC group (LPRC)
01= Internal FRC group (FRC)
00= Secondary group (LP external)
bit 7-4
bit 3-0
Unimplemented: Read as ‘0’
FPR<3:0>: Primary Oscillator Selection bits
Legend:
R = Readable bit
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
-n = Value at POR
P = FLASH programmable bit
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 299
dsPIC30F
Different registers are affected in different ways by var-
ious RESET conditions. Most registers are not affected
by a WDT wake-up, since this is viewed as the resump-
tion of normal operation. Status bits from the RCON
register are set or cleared differently in different RESET
situations, as indicated in Table 24-4. These bits are
used in software to determine the nature of the RESET.
24.3 RESET
The dsPIC30F differentiates between various kinds of
RESET:
a) Power-on Reset (POR)
b) MCLR Reset during normal operation
c) MCLR Reset during SLEEP
A block diagram of the on-chip RESET circuit is shown
in Figure 24-2.
d) Watchdog Timer (WDT) Reset (during normal
operation)
A MCLR noise filter is provided in the MCLR Reset
path. The filter detects and ignores small pulses.
e) Programmable Brown-out Reset (PBOR)
f) RESETInstruction
Internally generated RESETS do not drive MCLR pin
low.
FIGURE 24-2:
RESET SYSTEM BLOCK DIAGRAM
RESET
Instruction
One Shot
Digital
Glitch Filter
MCLR
SLEEP.IDLE
WDT
Module
POR
VDD Rise
Detect
VDD
Brown-out
Reset
BOR
BOREN
S
R
Q
SYSRST
The POR circuit inserts a small delay, TPOR, which is
nominally 10µs and ensures that the device bias cir-
cuits are stable. Furthermore, a user selected power-
up time-out (TPWRT) is applied. The TPWRT parameter
is based on device configuration bits and can be 0 ms
(no delay), 4 ms, 16 ms, or 64 ms. The total delay is at
device power-up TPOR + TPWRT. When these delays
have expired, SYSRST will be negated on the next
leading edge of the Q1 clock, and the PC will jump to
the RESET vector.
24.3.1
POR: POWER-ON RESET
A power-on event will generate an internal POR Reset
pulse when a VDD rise is detected. The RESET pulse
will occur at the POR circuit threshold voltage (VPOR),
which is nominally 1.85V. The device supply voltage
characteristics must meet specified starting voltage
and rise rate requirements. For more information,
please refer to the Electrical Specifications section
(TBD) of the specific device data sheet. The POR pulse
will reset a POR timer and place the device in the
RESET state. The POR also selects the device clock
source identified by the oscillator configuration fuses.
The timing for the SYSRST signal is shown in
Figure 24-3 through Figure 24-5.
DS70032B-page 300
AdvanceInformation
2002 Microchip Technology Inc.
dsPIC30F
FIGURE 24-3:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TOST
OST TIME-OUT
TPWRT
PWRT TIME-OUT
INTERNAL RESET
FIGURE 24-4:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TOST
OST TIME-OUT
TPWRT
PWRT TIME-OUT
INTERNAL RESET
FIGURE 24-5:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TOST
OST TIME-OUT
TPWRT
PWRT TIME-OUT
INTERNAL RESET
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 301
dsPIC30F
A BOR will generate a RESET pulse which will reset
the device. The BOR Reset will select the clock source,
based on the device configuration bit values
(FOS<1:0> and FPR<3:0>). Furthermore, if an oscilla-
tor mode is selected, the BOR Reset will activate the
Oscillator Start-up Timer (OST). The system clock is
held until OST expires. If the PLL is used, then the
clock will be held until the LOCK bit (OSCCON<5>) is
“1”.
24.3.1.1
POR with Long Crystal Start-up Time
(with FSCM Enabled)
The oscillator start-up circuitry is not linked to the POR
circuitry. Some crystal circuits (especially low fre-
quency crystals) will have a relatively long start-up
time. Therefore, one or more of the following conditions
is possible after the POR timer and the PWRT have
expired:
• The oscillator circuit has not begun to oscillate.
Concurrently, the POR timeout (TPOR) and the PWRT
time-out (TPWRT) will be applied before the internal
RESET is released.
• The oscillator start-up timer has NOT expired (if a
crystal oscillator is used).
• The PLL has not achieved a LOCK (if PLL is
used).
The BOR status bit (RCON<1>) will be set to indicate
that a BOR has occurred.
If the FSCM is enabled and one of the above conditions
is true, then a Clock Failure Trap will occur. The device
will automatically switch to the FRC oscillator and the
user can switch to the desired crystal oscillator in the
TRAP ISR.
The BOR circuit, if enabled, will continue to operate
while in SLEEP or IDLE modes and will reset the
device should VDD fall below the BOR threshold
voltage.
FIGURE 24-6:
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
24.3.1.2
Operating without FSCM and PWRT
If the FSCM is disabled and the Power-up Timer
(PWRT) is also disabled, then on a power-up, the
device will exit from RESET rapidly. If the clock source
is FRC, LPRC, EXTRC or EC, it will be active immedi-
ately.
VDD
D
If the FSCM is disabled and the system clock has not
started, the device will be in a frozen state at the
RESET vector, until the system clock starts. From the
user’s perspective, the device will appear to be in
RESET until a system clock is available.
R
R1
MCLR
dsPIC30F
C
24.3.2
BOR: PROGRAMMABLE
BROWN-OUT RESET
Note 1: External Power-On Reset circuit is
required only if the VDD power-up slope is
too slow. The diode D helps discharge the
capacitor quickly when VDD powers
down.
The BOR (Brown-out Reset) module is based on an
internal voltage reference circuit. The main purpose of
the BOR module is to generate a device RESET when
a brown-out condition occurs. Brown-out conditions are
generally caused by glitches on the AC mains, i.e.,
missing waveform portions of the AC cycles due to bad
power transmission lines, or voltage sags due to exces-
sive current draw when a large inductive load is turned
on.
2: R < TBDkΩ is recommended to make
sure that the voltage drop across R does
not violate the device’s electrical specifi-
cation.
3: R1 = TBDΩ to TBDkΩ will limit any cur-
rent flowing into MCLR from external
capacitor C, in the event of MCLR/VPP
pin breakdown due to Electrostatic Dis-
charge (ESD), or Electrical Overstress
(EOS).
The BOR module allows selection of one of the follow-
ing voltage trip points:
• 2.0V
• 2.7V
• 4.2V
• 4.5V
Note: Dedicated supervisory devices such as the
MCP1XX and MCP8XX may also be used
as an external Power-on Reset circuit.
Note: The BOR voltage trip points indicated
here are nominal values provided for
design guidance only. Refer to the Elec-
trical Specifications in the specific device
data sheet for BOR voltage limit specifi-
cations.
DS70032B-page 302
AdvanceInformation
2002 Microchip Technology Inc.
dsPIC30F
Table 24-4 shows the RESET conditions for the RCON
Register. Since the control bits within the RCON regis-
ter are R/W, the information in the table implies that all
the bits are negated prior to the action specified in the
condition column.
TABLE 24-4: INITIALIZATION CONDITION FOR RCON REGISTER CASE 1
Program
Condition
EXTR SWR WDTO IDLE SLEEP POR BOR
Counter
Power-on Reset
0x0000
0x0000
0x0000
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
Brown-out Reset
MCLR Reset during normal
operation
Software Reset during normal operation
MCLR Reset during SLEEP
MCLR Reset during IDLE
WDT Time-out Reset
0x0000
0x0000
0x0000
0x0000
PC + 2
PC + 2(1)
0x0004
0
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
WDT Wake-up
Interrupt Wake-up from SLEEP
Clock Failure Trap
Legend: u= unchanged, x= unknown, - = unimplemented bit, read as ’0’
Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector.
Table 24-5 shows a second example of the bit
conditions for the RCON Register. In this case, it is not
assumed the user has set/cleared specific bits prior to
action specified in the condition column.
TABLE 24-5: INITIALIZATION CONDITION FOR RCON REGISTER CASE 2
Program
Condition
EXTR SWR WDTO IDLE SLEEP POR BOR
Counter
Power-on Reset
0x0000
0x0000
0x0000
0
u
1
0
u
0
0
u
0
0
u
0
0
u
0
1
0
u
1
1
u
Brown-out Reset
MCLR Reset during normal
operation
Software Reset during normal operation
MCLR Reset during SLEEP
MCLR Reset during IDLE
WDT Time-out Reset
0x0000
0x0000
0x0000
0x0000
PC + 2
PC + 2(1)
0x0004
0
1
1
0
u
u
u
1
u
u
0
u
u
u
0
0
0
1
1
u
u
0
0
1
0
u
u
u
0
1
0
0
1
1
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
WDT Wake-up
Interrupt Wake-up from SLEEP
Clock Failure Trap
Legend: u= unchanged, x= unknown, - = unimplemented bit, read as ’0’
Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector.
2002 Microchip Technology Inc.
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dsPIC30F
REGISTER 24-3: RCON: RESET AND SYSTEM CONTROL REGISTER
Upper Half:
U-0
U-0
U-0
R/W-0
R/W-0
LVDL3
R/W-0
LVDL2
R/W-0
LVDL1
R/W-0
LVDL0
—
—
—
LVDEN
bit 15
bit 8
Lower Half:
R/W-0
R/W-0
SWR
R/W-0
SWDTEN
R/W-0
WDTO
R/W-0
SLEEP
R/W-0
IDLE
R/W-1
BOR
R/W-1
POR
EXTR
bit 7
bit 0
bit 15:13 Unimplemented: Read as ‘0’
bit 12
LVDEN: Low Voltage Detect Power Enable bit
1= Enables LVD, powers up LVD circuit
0= Disables LVD, powers down LVD circuit
bit 11:8 LVDL<3:0>: Low Voltage Detection Limit bits
1111= External analog input is used (input comes from the LVDIN pin)
1110= 4.5V min - 4.77V max
1101= 4.2V min - 4.45V max
1100= 4.0V min - 4.24V max
1011= 3.8V min - 4.03V max
1010= 3.6V min - 3.82V max
1001= 3.5V min - 3.71V max
1000= 3.3V min - 3.50V max
0111= 3.0V min - 3.18V max
0110= 2.8V min - 2.97V max
0101= 2.7V min - 2.86V max
0100= 2.5V min - 2.65V max
0011= 2.4V min - 2.54V max
0010= 2.2V min - 2.33V max
0001= 2.0V min - 2.12V max
0000= 1.8V min - 1.91V max
bit 7
bit 6
bit 5
EXTR: External Reset (MCLR) Pin bit
1= A Master Clear (pin) Reset has occurred
0= A Master Clear (pin) Reset has not occurred
SWR: Software RESET (Instruction) Flag bit
1= A ‘RESET’ instruction has been executed
0= A ‘RESET’ instruction has not been executed
SWDTEN: Software Enable/Disable of WDT bit
1= WDT is turned on
0= WDT is turned off
Note: If FWDTEN configuration bit is = 1, the WDT is ALWAYS ENABLED, regardless of SWDTEN bit
setting.
bit 4
bit 3
bit 2
WDTO: Watchdog Timer Time-out Flag bit
1= WDT time-out has occurred
0= WDT time-out has NOT occurred
SLEEP: Wake from SLEEP Flag bit
1= Device has been in SLEEP mode
0= Device has NOT been in SLEEP mode
IDLE: Wake-up from IDLE Flag bit
1= Device was in IDLE mode
0= Device was NOT in IDLE mode
DS70032B-page 304
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dsPIC30F
REGISTER 24-3: RCON: RESET AND SYSTEM CONTROL REGISTER (Continued)
bit 1
bit 0
BOR: Brown-out Reset Flag bit
1= A Brown-out Reset has occurred. Note that BOR is also set after Power-on Reset.
0= A Brown-out Reset has NOT occurred
POR: Power-on Reset Flag bit
1= A Power-up Reset has occurred
0= A Power-up Reset has NOT occurred
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared
x = bit is unknown
Setting FWDTEN = 1 enables the Watchdog Timer. The
enabling is done when programming the device. By
default, after chip-erase, FWDTEN bit = 1. Any device
programmer capable of programming dsPIC30F
devices allows programming of this and other configu-
ration bits to the desired state.
24.4 Watchdog Timer (WDT)
24.4.1 WATCHDOG TIMER OPERATION
The primary function of the Watchdog Timer (WDT) is
to reset the processor in the event of a software mal-
function. The WDT is a free running timer, which runs
off an on-chip RC oscillator, requiring no external com-
ponent. Therefore, the WDT timer will continue to oper-
ate even if the main processor clock (e.g., the crystal
oscillator) fails.
If enabled, the WDT will increment until it overflows or
“times out”. A WDT time-out will force a device RESET
(except during SLEEP). To prevent a WDT time-out,
the user must clear the Watchdog Timer using a
CLRWDTinstruction.
24.4.2
ENABLING AND DISABLING THE
WDT
If a WDT times out during SLEEP, the device will wake-
up. The WDTO bit in the RCON register will be cleared
to indicate a wake-up resulting from a WDT time-out.
The Watchdog Timer can be “Enabled” or “Disabled”
only through a configuration bit (FWDTEN) in the con-
figuration register FWDT.
Setting FWDTEN = 0 allows user software to enable/
disable Watchdog Timer via the SWDTEN (RCON<5>)
control bit.
2002 Microchip Technology Inc.
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dsPIC30F
REGISTER 24-4: FWDT: CONFIGURATION BITS FOR WDT
Upper Third:
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 23
bit 16
Middle Third:
U-0
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
bit 15
bit 8
Lower Third:
R/P-1
R/P-1
FWPSA0
R/P-1
FWPSB3
R/P-1
R/P-1
R/P-1
U-0
R/P-1
FWPSA1
bit 7
FWPSB2 FWPSB1 FWPSB0
—
FWDTEN
bit 0
bit 23-8: Unimplemented: Read as ‘0’
bit 7-6
FWPSA<1:0>: Prescale Value Selection bits for Prescaler A bits
00= 1:1
01= 1:8
10= 1:64
11= 1:512
bit 5-2
FWPSB<3:0>: Prescale Value Selection bits for Prescaler B bits
0000= 1:1
0001= 1:2
•
•
•
1110= 1:15
1111= 1:16
bit 1
bit 0
Unimplemented: Read as 0
FWDTEN: Watchdog Enable Configuration bit
1= Watchdog enabled (LPRC oscillator cannot be disabled. Clearing the SWDTEN bit in the
WDTCON register will have no effect.)
0= Watchdog disabled (LPRC oscillator can be disabled by clearing the SWDTEN bit in the
WDTCON register)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
DS70032B-page 306
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dsPIC30F
Any interrupt that is individually enabled (using the
corresponding IE bit) and meets the prevailing priority
level will be able to wake-up the processor. If control
bit GIE = 1, then the processor will process the inter-
rupt and branch to the ISR. If GIE = 0, then the proces-
sor will simply continue execution, starting with the
instruction immediately following the SLEEP instruc-
tion. The SLEEP status bit in RCON register is set
upon wake-up.
24.5 Power Saving Modes
There are two power saving states that can be entered
through the execution of a special instruction, PWRSAV.
These are: SLEEP and IDLE.
The format of the PWRSAVinstruction is as follows:
PWRSAV <parameter>, where ‘parameter’ defines
IDLE or SLEEP mode.
Note: In spite of various delays applied (TPOR,
TLOCK and TPWRT) the crystal oscillator
(and PLL) may not be active at the end of
the time-out, e.g., for low frequency crys-
tals. In such cases, if FSCM is enabled,
then the device will detect this as a clock
failure and process the Clock Failure Trap,
the FRC oscillator will be enabled, and the
user will have to re-enable the crystal oscil-
lator. If FSCM is not enabled, then the
device will simply suspend execution of
code until the clock is stable, and will
remain in SLEEP until the oscillator clock
has started.
24.5.1
SLEEP MODE
In SLEEP mode, the clock to the CPU and the periph-
erals is shut-down. If an on-chip oscillator is being
used, it is shut-down.
The fail safe clock monitor is not functional during
SLEEP, since there is no clock to monitor. However,
LPRC clock remains active if WDT is operational dur-
ing SLEEP.
The Brown-out protection circuit and the Low Voltage
Detect circuit, if enabled, will remain functional during
SLEEP.
The processor wakes up from SLEEP if at least one of
the following conditions is true:
All RESETS will wake-up the processor from SLEEP
mode. Any RESET, other than POR, will set the
SLEEP status bit. In a POR Reset, the SLEEP bit is
cleared.
• on occurrence of any interrupt that is individually
enabled and meets the required priority level
• on any RESET (POR, BOR and MCLR)
• on WDT time-out
If Watchdog Timer is enabled, then upon WDT time-
out, the processor will wake-up from SLEEP mode.
SLEEP and WDTO status bits are both set.
On waking up from SLEEP mode, the processor will
restart the same clock that was active prior to entry
into SLEEP mode. When clock switching is enabled,
bits COSC<1:0> will determine the oscillator source
that will be used on wake-up. If clock switch is dis-
abled, then there is only one system clock.
24.5.2
IDLE MODE
In IDLE mode, the clock to the CPU is shut-down while
peripherals keep running. Unlike SLEEP mode, the
clock source remains active.
Note: If a POR or BOR Reset occurred, the
selection of the oscillator is based on the
FOS<1:0> and FPR<3:0> configuration
bits.
Several peripherals have a control bit in each module,
that allows them to operate during IDLE.
LPRC fail safe clock remains active if clock failure
detect is enabled.
If the clock source is an oscillator, the clock to the
device will be held off until OST times out (indicating a
stable oscillator). If PLL is used, the system clock is
held off until LOCK = 1 (indicating that the PLL is sta-
ble). In either case, TPOR, TLOCK and TPWRT delays
are applied.
The processor wakes up from IDLE if at least one of
the following conditions is true:
• on any interrupt that is individually enabled (IE bit
is ‘1’) and meets the required priority level
• on any RESET (POR, BOR, MCLR)
• on WDT time-out
If EC, FRC, LPRC or EXTRC oscillators are used,
then the start-up delay will be a few cycles. A delay of
TPOR (~ 10 µs) is applied. This is the smallest delay
possible on wake-up from SLEEP.
Upon wake-up from IDLE mode, the clock is re-applied
to the CPU and instruction execution begins immedi-
ately, starting with the instruction following the PWRSAV
instruction.
Moreover, if LP oscillator was active during SLEEP,
and LP is the oscillator used on wake-up, then the
start-up delay will be equal to TPOR. PWRT delay and
OST timer delay are not applied. In order to have the
smallest possible start-up delay when waking up from
SLEEP, then one of these faster wake-up options
should be selected before entering SLEEP.
2002 Microchip Technology Inc.
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DS70032B-page 307
dsPIC30F
Any interrupt that is individually enabled (using IE bit)
and meets the prevailing priority level, will be able to
wake-up the processor. If control bit GIE = 1, then the
processor will process the interrupt and branch to the
ISR. If GIE = 0, then the processor will continue exe-
cution with the instruction immediately following the
PWRSAVinstruction. The IDLE status bit in RCON reg-
ister is set upon wake-up.
Any RESET other than POR will set the IDLE status
bit. On a POR Reset, the IDLE bit is cleared.
If Watchdog Timer is enabled, then upon WDT time-
out, the processor will wake-up from IDLE mode. IDLE
and WDTO status bits are both set.
Unlike wake-up from SLEEP, there are no time delays
involved in wake-up from IDLE.
24.6 In-Circuit Serial Programming
(TBD)
DS70032B-page 308
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dsPIC30F
2002 Microchip Technology Inc.
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DS70032B-page 309
dsPIC30F
NOTES:
DS70032B-page 310
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2002 Microchip Technology Inc.
dsPIC30F
The literal instructions that involve data movement
may use some of the following operands:
25.0 INSTRUCTION SET SUMMARY
The dsPIC30F instruction set adds many
enhancements to the previous PICmicro® instruction
sets, while maintaining an easy migration from
PICmicro instruction sets.
• A literal value to be loaded into a W register or file
register (specified by the value of ’k’)
• The desired W register or file register to load the
literal value into (specified by ’Wb’ or ’f’)
Most instructions are a single program memory word
(24-bits), but there are three instructions that require
two program memory locations.
However, literal instructions that involve arithmetic or
logical operations use some of the following operands:
• The first source operand, which is a register ’Wb’
without any address modifier
Each single-word instruction is a 24-bit word divided
into an 8-bit opcode, which specifies the instruction
type and one or more operands, which further specify
the operation of the instruction.
• The second source operand, which is a literal
value
• The destination of the result (only if not the same
as the first source operand), which is typically a
register ’Wd’ with or without an address modifier
The instruction set is highly orthogonal and is grouped
into five basic categories:
• Word or byte-oriented operations
• Bit-oriented operations
• Literal operations
The MACclass of DSP instructions may use some of the
following operands:
• The accumulator (A or B) to be used
• DSP operations
• The W registers to be used as the two operands
• The X and Y address space pre-fetch operations
• The X and Y address space pre-fetch destinations
• The accumulator write-back destination
• Control operations
Table 25-1 shows the general symbols used in describ-
ing the instructions.
The dsPIC30F instruction set summary in Table 25-2
lists all the instructions along with the status flags
affected by each instruction.
The other DSP instructions do not involve any multipli-
cation, and may include:
• The accumulator to be used
Most word or byte-oriented W register instructions
(including barrel shift instructions) have three oper-
ands:
• The source or destination operand (designated as
Wso or Wdo, respectively) with or without an
address modifier
• The first source operand, which is typically a reg-
ister ’Wb’ without any address modifier
• The amount of shift (in the case of accumulator
shift instructions), specified by a W register ’Wn’
or a literal value
• The second source operand, which is typically a
register ’Ws’ with or without an address modifier
The control instructions may use some of the following
operands:
• The destination of the result, which is typically a
register ’Wd’ with or without an address modifier
• A program memory address
However, word or byte-oriented file register instructions
have two operands:
• The mode of the Table Read and Table Write
instructions
• The file register specified by the value ’f’
• No operand required
• The destination, which could either be the file reg-
ister ’f’ or the W0 register, which is denoted as
’WREG’
All instructions are a single-word, except for certain
double-word instructions, which were made double-
word instructions so that all the required information is
available in these 48-bits. In the second word, the
8 MSb’s are 0’s. If this second word is executed as an
instruction (by itself), it will execute as a NOP.
The destination designator ‘d’ specifies where the
result of the operation is to be placed. If 'd' is zero, the
result is placed in WREG. If 'd' is one, the result is
placed in the file register specified in the instruction.
Most bit-oriented instructions (including simple rotate/
shift instructions) have two operands:
• The W register (with or without an address modi-
fier) or file register (specified by the value of ’Ws’
or ’f’)
• The bit in the W register or file register
(specified by a literal value, or indirectly by the
contents of register ’Wb’)
2002 Microchip Technology Inc.
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DS70032B-page 311
dsPIC30F
Most single-word instructions are executed in a single
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of the instruc-
tion. In these cases, the execution takes two instruction
cycles with the additional instruction cycle(s) executed
as a NOP. Notable exceptions are the BRA (uncondi-
tional/computed branch), indirect CALL/GOTO, all
Table Reads and Writes, TRAP, and RETURN/RETFIE
instructions, which are single-word instructions but take
two cycles. Certain instructions that involve skipping
over the subsequent instruction, require either two or
three cycles if the skip is performed, depending on
whether the instruction being skipped is a single-word
or two-word instruction. Moreover, double-word moves
require two cycles.
The double-word instructions execute in two instruction
cycles.
One instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 120 MHz, the nor-
mal instruction execution time is 0.033 µs. If a condi-
tional test is true or the program counter is changed as
a result of an instruction, the instruction execution time
is 0.066 µs.
Note: For more details on the instruction set, refer
to the Programmer’s Reference Manual.
TABLE 25-1: SYMBOLS USED IN ROADRUNNER OPCODE DESCRIPTIONS
Field Description
#text
(text)
.b
Means literal defined by “text“
Means “content of text“
Byte mode selection
.d
Double-word mode selection
Shadow register select
.S
.w
Word mode selection (default)
[text]
Means “the location addressed by text”
Optional field or operation
{
}
<n:m>
Acc
Register bit field
One of two accumulators {A, B}
AWB
Accumulator write back destination address register ∈ {W13, [W13]+=2}
3-bit bit selection field (used in byte addressed instructions) ∈ {0...7}
4-bit bit selection field (used in word addressed instructions) ∈ {0...15}
MCU status bits: Carry, Digit Carry, Negative, Overflow, Sticky-Zero
File register destination d ∈ {WREG, none}
Absolute address, label or expression (resolved by the linker)
File register address ∈ {0x0000...0x1FFF}
1-bit unsigned literal ∈ {0,1}
bit3
bit4
C, DC, N, OV, SZ
d
Expr
f
lit1
lit14
lit16
lit23
lit4
14-bit unsigned literal ∈ {0...16384}
16-bit unsigned literal ∈ {0...65535}
23-bit unsigned literal ∈ {0...8388608}; LSB must be 0
4-bit unsigned literal ∈ {0...15}
lit5
5-bit unsigned literal ∈ {0...31}
lit8
8-bit unsigned literal ∈ {0...255}
lit10
None
10-bit unsigned literal ∈ {0...255} for Byte mode, {0:1023} for Word mode
field does not require an entry, may be blank
DSP status bits: AccA Overflow, AccB Overflow, AccA Saturate, AccB Saturate
Program Counter
OA, OB, SA, SB
PC
Slit10
Slit16
Slit5
10-bit signed literal ∈ {-512...511}
16-bit signed literal ∈ {-32768...32767}
5-bit signed literal ∈ {-16...15}
text1 Π{text2,
text1must be in the set of text2, text3, ...
text3, ...}
Wb
Base W register ∈ {W0..W15}
DS70032B-page 312
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dsPIC30F
TABLE 25-1: SYMBOLS USED IN ROADRUNNER OPCODE DESCRIPTIONS (CONTINUED)
Field Description
Wd
Destination W register ∈ { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }
Wdo
Destination W register ∈
{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }
Wm,Wn
Wm*Wm
Dividend, Divisor working register pair (direct addressing)
Multiplicand and Multiplier working register pair for Square instructions ∈
{W4*W4,W5*W5,W6*W6,W7*W7}
Wm*Wn
Multiplicand and Multiplier working register pair for DSP instructions ∈
{W4*W5,W4*W6,W4*W7,W5*W6,W5*W7,W6*W7}
Wn
One of 16 working registers ∈ {W0..W15}
Wnd
Wns
WREG
Ws
One of 16 destination working registers ∈ {W0..W15}
One of 16 source working registers ∈ {W0..W15}
W0 (working register used in file register instructions)
Source W register ∈ { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }
Wso
Source W register ∈
{ Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }
Wx
X data space pre-fetch address register for DSP instructions
∈ {[W8]+=6, [W8]+=4, [W8]+=2, [W8], [W8]-=6, [W8]-=4, [W8]-=2,
[W9]+=6, [W9]+=4, [W9]+=2, [W9], [W9]-=6, [W9]-=4, [W9]-=2,
[W9+W12],none}
Wxd
Wy
X data space pre-fetch destination register for DSP instructions ∈ {W4..W7}
Y data space pre-fetch address register for DSP instructions
∈ {[W10]+=6, [W10]+=4, [W10]+=2, [W10], [W10]-=6, [W10]-=4, [W10]-=2,
[W11]+=6, [W11]+=4, [W11]+=2, [W11], [W11]-=6, [W11]-=4, [W11]-=2,
[W11+W12],none}
Wyd
Y data space pre-fetch destination register for DSP instructions ∈ {W4..W7}
2002 Microchip Technology Inc.
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DS70032B-page 313
dsPIC30F
TABLE 25-2: INSTRUCTION SET OVERVIEW
Base
Instr
#
Assembly
Mnemonic
# of
words cycles
# of
Status Flags
Affected
Assembly Syntax
Acc
Description
Add Accumulators
1
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADDC
ADDC
ADDC
ADDC
ADDC
AND
AND
AND
AND
AND
ASR
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
OA,OB,SA,SB
C,DC,N,OV,SZ
C,DC,N,OV,SZ
C,DC,N,OV,SZ
C,DC,N,OV,SZ
C,DC,N,OV,SZ
OA,OB,SA,SB
C,DC,N,OV,SZ
C,DC,N,OV,SZ
C,DC,N,OV,SZ
C,DC,N,OV,SZ
C,DC,N,OV,SZ
N,SZ
f
f = f + WREG
f,WREG
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
Wso,#Slit4,Acc
f
WREG = f + WREG
Wd = lit10 + Wd
Wd = Wb + Ws
Wd = Wb + lit5
16-bit Signed Add to Accumulator
f = f + WREG + (C)
2
3
4
ADDC
AND
f,WREG
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
f
WREG = f + WREG + (C)
Wd = lit10 + Wd + (C)
Wd = Wb + Ws + (C)
Wd = Wb + lit5 + (C)
f = f .AND. WREG
f,WREG
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
f
WREG = f .AND. WREG
Wd = lit10 .AND. Wd
Wd = Wb .AND. Ws
N,SZ
N,SZ
N,SZ
Wd = Wb .AND. lit5
N,SZ
ASR
f = Arithmetic Right Shift f
WREG = Arithmetic Right Shift f
Wd = Arithmetic Right Shift Ws
Wnd = Arithmetic Right Shift Wb by Wns
Wnd = Arithmetic Right Shift Wb by lit5
Bit Clear f
C,N,OV,SZ
C,N,OV,SZ
C,N,OV,SZ
N,SZ
ASR
f,WREG
Ws,Wd
ASR
ASR
Wb,Wns,Wnd
Wb,#lit5,Wnd
f,#bit3
ASR
N,SZ
5
6
BCLR
BRA
BCLR.b
BCLR
BRA
None
Ws,#bit4
C,Expr
Bit Clear Ws
None
Branch if Carry
1 (2) None
1 (2) None
1 (2) None
1 (2) None
1 (2) None
1 (2) None
1 (2) None
1 (2) None
1 (2) None
1 (2) None
1 (2) None
1 (2) None
1 (2) None
1 (2) None
1 (2) None
1 (2) None
1 (2) None
1 (2) None
1 (2) None
BRA
GE,Expr
GEU,Expr
GT,Expr
GTU,Expr
LE,Expr
LEU,Expr
LT,Expr
LTU,Expr
N,Expr
Branch if greater than or equal
Branch if unsigned greater than or equal
Branch if greater than
Branch if unsigned greater than
Branch if less than or equal
Branch if unsigned less than or equal
Branch if less than
BRA
BRA
BRA
BRA
BRA
BRA
BRA
Branch if unsigned less than
Branch if Negative
BRA
BRA
NC,Expr
NN,Expr
NOV,Expr
NZ,Expr
OA,Expr
OB,Expr
OV,Expr
SA,Expr
SB,Expr
Expr
Branch if Not Carry
BRA
Branch if Not Negative
Branch if Not Overflow
Branch if Not Zero
BRA
BRA
BRA
Branch if accumulator A overflow
Branch if accumulator B overflow
Branch if Overflow
BRA
BRA
BRA
Branch if accumulator A saturated
Branch if accumulator B saturated
Branch Unconditionally
Branch if Zero
BRA
BRA
2
None
BRA
Z,Expr
1 (2) None
BRA
Wn
Computed Branch
2
1
1
1
1
1
1
None
None
None
None
None
None
None
None
7
BSET
BSW
BTG
BSET.b
BSET
BSW.C
BSW.Z
BTG.b
BTG
f,#bit3
Bit Set f
Ws,#bit4
Ws,Wb
Bit Set Ws
8
Write C bit to Ws<Wb>
Write SZ bit to Ws<Wb>
Bit Toggle f
Ws,Wb
9
f,#bit3
Ws,#bit4
f,#bit3
Bit Toggle Ws
10
BTSC
BTSC.b
Bit Test f, Skip if Clear
1
(2 or 3)
BTSC
Ws,#bit4
Bit Test Ws, Skip if Clear
1
1
None
(2 or 3)
DS70032B-page 314
AdvanceInformation
2002 Microchip Technology Inc.
dsPIC30F
TABLE 25-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic
# of
words cycles
# of
Status Flags
Affected
Assembly Syntax
f,#bit3
Description
Bit Test f, Skip if Set
11
BTSS
BTSS.b
BTSS
1
1
1
None
(2 or 3)
Ws,#bit4
Bit Test Ws, Skip if Set
1
None
(2 or 3)
12
BTST
BTST.b
BTST.C
BTST.Z
BTST.C
BTST.Z
BTSTS.b
f,#bit3
Bit Test f
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
SZ
Ws,#bit4
Ws,#bit4
Ws,Wb
Ws,Wb
f,#bit3
Bit Test Ws to C
C
Bit Test Ws to SZ
SZ
Bit Test Ws<Wb> to C
Bit Test Ws<Wb> to SZ
Bit Test then Set f
C
SZ
13
BTSTS
SZ
BTSTS.C Ws,#bit4
BTSTS.Z Ws,#bit4
Bit Test Ws to C, then Set
Bit Test Ws to SZ, then Set
Call subroutine
C
SZ
14
15
CALL
CLR
CALL
CALL
CLR
CLR
CLR
CLR
CLRWDT
COM
COM
COM
CP
lit23
None
Wn
Call indirect subroutine
f = 0x0000
None
f
None
WREG
WREG = 0x0000
None
Ws
Ws = 0x0000
None
Acc,Wx,Wxd,Wy,Wyd,AWB
Clear Accumulator
Clear Watchdog Timer
f = f
OA,OB,SA,SB
WDTO,SLEEP
N,SZ
16
17
CLRWDT
COM
f
f,WREG
WREG = f
N,SZ
Ws,Wd
Wd = Ws
N,SZ
18
CP
f
Compare f with WREG
Compare Wb with lit5
Compare Wb with Ws (Wb - Ws)
Compare f with 0x0000
Compare Ws with 0x0000
Compare f with 0xFFFF
Compare Ws with 0xFFFF
Compare f with WREG, with Borrow
Compare Wb with lit5, with Borrow
C,DC,N,OV,SZ
C,DC,N,OV,SZ
C,DC,N,OV,SZ
C,DC,N,OV,SZ
C,DC,N,OV,SZ
C,DC,N,OV,SZ
C,DC,N,OV,SZ
C,DC,N,OV,SZ
C,DC,N,OV,SZ
C,DC,N,OV,SZ
CP
Wb,#lit5
CP
Wb,Ws
19
20
21
CP0
CP1
CPB
CP0
CP0
CP1
CP1
CPB
CPB
CPB
f
Ws
f
Ws
f
Wb,#lit5
Wb,Ws
Compare Wb with Ws, with Borrow
(Wb - Ws - C)
22
23
24
25
CPSEQ
CPSGT
CPSLT
CPSNE
CPSEQ
CPSGT
CPSLT
CPSNE
f
f
f
f
Compare f with WREG, skip if =
Compare f with WREG, skip if >
Compare f with WREG, skip if <
Compare f with WREG, skip if ≠
1
1
1
1
1
None
None
None
None
(2 or 3)
1
(2 or 3)
1
(2 or 3)
1
(2 or 3)
26
27
DAW.b
DEC
DAW.b
DEC
Wn
Wn = decimal adjust Wn
f = f -1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C
f
C,DC,N,OV,SZ
C,DC,N,OV,SZ
C,DC,N,OV,SZ
C,DC,N,OV,SZ
C,DC,N,OV,SZ
C,DC,N,OV,SZ
None
DEC
f,WREG
Ws,Wd
f
WREG = f -1
Wd = Ws - 1
f = f -2
DEC
28
29
DEC2
DEC2
DEC2
DEC2
DECSNZ
f,WREG
Ws,Wd
f
WREG = f -2
Wd = Ws - 2
f = f-1, Skip if Not 0
DECSNZ
1
(2 or 3)
DECSNZ f,WREG
WREG = f-1, Skip if Not 0
f = f-1, Skip if 0
1
1
1
1
1
None
None
None
None
(2 or 3)
30
31
DECSZ
DISI
DECSZ
DECSZ
DISI
f
1
(2 or 3)
f,WREG
#lit14
WREG = f-1, Skip if 0
1
(2 or 3)
Disable Interrupts for k instruction cycles
1
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 315
dsPIC30F
TABLE 25-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic
# of
words cycles
# of
Status Flags
Affected
Assembly Syntax
Description
32
DIV
DIV.S
DIV.SD
DIV.U
DIV.UD
DIVF
Wm,Wn
Wm,Wn
Wm,Wn
Wm,Wn
Wm,Wn
#lit14,Expr
Signed 16/16-bit Integer Divide
Signed 32/16-bit Integer Divide
Unsigned 16/16-bit Integer Divide
Unsigned 32/16-bit Integer Divide
Signed 16/16-bit Fractional Divide
Do code to PC+Expr, lit14+1 times
1
1
1
1
1
2
18
18
18
18
18
N,SZ,C
N,SZ,C
N,SZ,C
N,SZ,C
N,SZ,C
None
33
34
DIVF
DO
DO
2 +
(lit14 +
1)*loop
DO
Wn,Expr
Do code to PC+Expr, (Wn)+1 times
2
2 +
None
[(Wn)+
1]*loop
35
36
37
38
39
40
41
ED
ED
Wm*Wm,Acc,Wx,Wy,Wxd
Euclidean Distance
Euclidean Distance Accumulate
Swap Wns with Wnd
Find Bit Change from Left (MSb) Side
Find First One from Left (MSb) Side
Find First One from Right (LSb) Side
Go to address
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
OA,OB
EDAC
EXCH
FBCL
FF1L
FF1R
GOTO
EDAC
EXCH
FBCL
FF1L
FF1R
GOTO
GOTO
INC
Wm*Wm,Acc,Wx,Wy,Wxd
OA,OB,SA,SB
None
Wns,Wnd
Ws,Wnd
Ws,Wnd
Ws,Wnd
Expr
C
C
C
None
Wn
Go to indirect
None
42
43
44
INC
f
f = f + 1
C,DC,N,OV,SZ
C,DC,N,OV,SZ
C,DC,N,OV,SZ
C,DC,N,OV,SZ
C,DC,N,OV,SZ
C,DC,N,OV,SZ
None
INC
f,WREG
Ws,Wd
f
WREG = f + 1
INC
Wd = Ws + 1
INC2
INC2
INC2
INC2
INCSNZ
f = f + 2
f,WREG
Ws,Wd
f
WREG = f + 2
Wd = Ws + 2
INCSNZ
f = f+1, Skip if Not 0
1
(2 or 3)
INCSNZ
INCSZ
INCSZ
f,WREG
f
WREG = f+1, Skip if Not 0
f = f+1, Skip if 0
1
1
1
1
None
None
None
(2 or 3)
45
46
INCSZ
IOR
1
(2 or 3)
f,WREG
WREG = f+1, Skip if 0
1
(2 or 3)
IOR
IOR
IOR
IOR
IOR
LAC
f
f = f .IOR. WREG
1
1
1
1
1
1
1
1
1
1
1
1
N,SZ
N,SZ
N,SZ
N,SZ
N,SZ
f,WREG
WREG = f .IOR. WREG
Wd = lit10 .IOR. Wd
Wd = Wb .IOR. Ws
Wd = Wb .IOR. lit5
Load Accumulator
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
Wso,#Slit4,Acc
47
LAC
OA,OB,OAB,
SA,SB,SAB
48
49
LNK
LSR
LNK
LSR
LSR
LSR
LSR
LSR
MAC
#lit14
Link frame pointer
1
1
1
1
1
1
1
1
1
1
1
1
1
1
None
f
f = Logical Right Shift f
C,N,OV,SZ
C,N,OV,SZ
C,N,OV,SZ
N,SZ
f,WREG
Ws,Wd
WREG = Logical Right Shift f
Wd = Logical Right Shift Ws
Wnd = Logical Right Shift Wb by Wns
Wnd = Logical Right Shift Wb by lit5
Multiply and Accumulate
Wb,Wns,Wnd
Wb,#lit5,Wnd
N,SZ
50
MAC
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd,
AWB
OA,OB,OAB,
SA,SB,SAB
MAC
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd
Square and Accumulate
1
1
OA,OB,OAB,
SA,SB,SAB
DS70032B-page 316
AdvanceInformation
2002 Microchip Technology Inc.
dsPIC30F
TABLE 25-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic
# of
words cycles
# of
Status Flags
Affected
Assembly Syntax
f,Wn
Description
51
MOV
MOV
Move f to Wn
Move f to f
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
None
MOV
f
N,SZ
MOV
f,WREG
#lit16,Wn
#lit8,Wn
Wn,f
Move f to WREG
N,SZ
MOV
Move 16-bit literal to Wn
None
MOV.b
MOV
Move 8-bit literal to Wn
None
Move Wn to f
None
MOV
Wso,Wdo
WREG,f
Wns,Wd
Ws,Wnd
Move Ws to Wd
None
MOV
Move WREG to f
N,SZ
MOV.D
MOV.D
Move Double from W(ns):W(ns+1) to Wd
Move Double from Ws to W(nd+1):W(nd)
Move Special
None
None
52
53
MOVSAC
MPY
MOVSAC Acc,Wx,Wxd,Wy,Wyd,AWB
None
MPY
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd
Multiply Wm by Wn to Accumulator
Square Wm to Accumulator
-(Multiply Wm by Wn) to Accumulator
Multiply and Subtract from Accumulator
OA,OB,OAB
OA,OB,OAB
OA,OB,OAB
MPY
54
55
MPY.N
MSC
MPY.N
MSC
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd,
AWB
OA,OB,OAB,
SA,SB,SAB
56
MUL
MUL.SS
MUL.SU
MUL.US
MUL.UU
Wb,Ws,Wnd
Wb,Ws,Wnd
Wb,Ws,Wnd
Wb,Ws,Wnd
{Wnd+1, Wnd} = signed(Wb) * signed(Ws)
{Wnd+1, Wnd} = signed(Wb) * unsigned(Ws)
{Wnd+1, Wnd} = unsigned(Wb) * signed(Ws)
1
1
1
1
1
1
1
1
None
None
None
None
{Wnd+1, Wnd} = unsigned(Wb) *
unsigned(Ws)
MUL.SU
MUL.UU
Wb,#lit5,Wnd
Wb,#lit5,Wnd
{Wnd+1, Wnd} = signed(Wb) * unsigned(lit5)
1
1
1
1
None
None
{Wnd+1, Wnd} = unsigned(Wb) *
unsigned(lit5)
MUL
NEG
f
W3:W2 = f * WREG
Negate Accumulator
1
1
1
1
None
57
NEG
Acc
OA,OB,OAB,
SA,SB,SAB
NEG
NEG
NEG
NOP
NOPR
POP
f
f = f + 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
C,DC,N,OV,SZ
C,DC,N,OV,SZ
C,DC,N,OV,SZ
None
f,WREG
Ws,Wd
WREG = f + 1
Wd = Ws + 1
58
59
NOP
POP
No Operation
No Operation
None
f
Pop f from top-of-stack (TOS)
Pop from top-of-stack (TOS) to Wdo
None
POP
Wdo
Wnd
None
POP.D
Pop from top-of-stack (TOS) to
W(nd):W(nd+1)
None
POP.S
Pop Shadow Registers
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
2
2
All
60
PUSH
PUSH
f
Push f to top-of-stack (TOS)
Push Wso to top-of-stack (TOS)
Push W(ns):W(ns+1) to top-of-stack (TOS)
Push Shadow Registers
Go into Standby mode
None
PUSH
Wso
Wns
None
PUSH.D
PUSH.S
PWRSAV
RCALL
RCALL
REPEAT
None
None
61
62
PWRSAV
RCALL
#lit1
Expr
Wn
WDTO,SLEEP
None
Relative Call
Computed Call
None
63
REPEAT
#lit14
Repeat Next Instruction lit14+1 times
2 +
None
lit14
REPEAT
Wn
Repeat Next Instruction (Wn)+1 times
1
2 +
(Wn)
None
None
64
65
66
67
68
RESET
RETFIE
RETLW
RETURN
RLC
RESET
RETFIE
RETLW
RETURN
RLC
Software device RESET
1
1
1
1
1
1
1
1
Return from interrupt enable
Return with literal in Wn
3 (2) None
3 (2) None
3 (2) None
#lit10,Wn
Return from Subroutine
f
f = Rotate Left through Carry f
WREG = Rotate Left through Carry f
Wd = Rotate Left through Carry Ws
1
1
1
C,N,SZ
RLC
f,WREG
Ws,Wd
C,N,SZ
C,N,SZ
RLC
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 317
dsPIC30F
TABLE 25-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic
# of
words cycles
# of
Status Flags
Affected
Assembly Syntax
Description
69
70
71
72
RLNC
RLNC
RLNC
RLNC
RRC
f
f = Rotate Left (No Carry) f
WREG = Rotate Left (No Carry) f
Wd = Rotate Left (No Carry) Ws
f = Rotate Right through Carry f
WREG = Rotate Right through Carry f
Wd = Rotate Right through Carry Ws
f = Rotate Right (No Carry) f
WREG = Rotate Right (No Carry) f
Wd = Rotate Right (No Carry) Ws
Store Accumulator
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
N,SZ
f,WREG
Ws,Wd
f
N,SZ
N,SZ
RRC
RRNC
SAC
C,N,SZ
C,N,SZ
C,N,SZ
N,SZ
RRC
f,WREG
Ws,Wd
f
RRC
RRNC
RRNC
RRNC
SAC
f,WREG
Ws,Wd
Acc,#Slit4,Wdo
Acc,#Slit4,Wdo
Ws,Wnd
f
N,SZ
N,SZ
None
None
C,N,SZ
None
None
None
SAC.R
SE
Store Rounded Accumulator
Wnd = sign extended Ws
73
74
SE
SETM
SETM
SETM
SETM
SFTAC
f = 0xFFFF
WREG
Ws
WREG = 0xFFFF
Ws = 0xFFFF
75
76
SFTAC
SL
Acc,Wn
Arithmetic Shift Accumulator by (Wn)
OA,OB,OAB,
SA,SB,SAB
SFTAC
Acc,#Slit5
Arithmetic Shift Accumulator by Slit5
1
1
OA,OB,OAB,
SA,SB,SAB
SL
f
f = Left Shift f
1
1
1
1
1
1
1
1
1
1
1
1
C,N,OV,SZ
C,N,OV,SZ
C,N,OV,SZ
N,SZ
SL
f,WREG
Ws,Wd
Wb,Wns,Wnd
Wb,#lit5,Wnd
Acc
WREG = Left Shift f
Wd = Left Shift Ws
SL
SL
Wnd = Left Shift Wb by Wns
Wnd = Left Shift Wb by lit5
Subtract Accumulators
SL
N,SZ
77
SUB
SUB
OA,OB,OAB,
SA,SB,SAB
SUB
f
f = f - WREG
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
5
1
C,DC,N,OV,SZ
C,DC,N,OV,SZ
C,DC,N,OV,SZ
C,DC,N,OV,SZ
C,DC,N,OV,SZ
C,DC,N,OV,SZ
C,DC,N,OV,SZ
C,DC,N,OV,SZ
C,DC,N,OV,SZ
C,DC,N,OV,SZ
C,DC,N,OV,SZ
C,DC,N,OV,SZ
C,DC,N,OV,SZ
C,DC,N,OV,SZ
C,DC,N,OV,SZ
C,DC,N,OV,SZ
C,DC,N,OV,SZ
C,DC,N,OV,SZ
None
SUB
f,WREG
Wn,#lit10
Wb,Ws,Wd
Wb,#lit5,Wd
f
WREG = f - WREG
Wn = Wn - lit10
SUB
SUB
Wd = Wb - Ws
SUB
Wd = Wb - lit5
78
SUBB
SUBB
SUBB
SUBB
SUBB
SUBB
SUBR
SUBR
SUBR
SUBR
SUBBR
SUBBR
SUBBR
SUBBR
SWAP.b
SWAP
TBLRDH
TBLRDL
TBLWTH
TBLWTL
TRAP
f = f - WREG - (C)
f,WREG
Wn,#lit10
Wb,Ws,Wd
Wb,#lit5,Wd
f
WREG = f - WREG - (C)
Wn = Wn - lit10 - (C)
Wd = Wb - Ws - (C)
Wd = Wb - lit5 - (C)
f = WREG - f
79
80
81
SUBR
SUBBR
SWAP
f,WREG
Wb,Ws,Wd
Wb,#lit5,Wd
f
WREG = WREG - f
Wd = Ws - Wb
Wd = lit5 - Wb
f = WREG - f - (C)
f,WREG
Wb,Ws,Wd
Wb,#lit5,Wd
Wn
WREG = WREG -f - (C)
Wd = Ws - Wb - (C)
Wd = lit5 - Wb - (C)
Wn = nibble swap Wn
Wn = byte swap Wn
Read Prog<23:16> to Wd<7:0>
Read Prog<15:0> to Wd
Write Ws<7:0> to Prog<23:16>
Write Ws to Prog<15:0>
Trap to vector with literal
Unlink frame pointer
Wn
None
82
83
84
85
86
87
TBLRDH
TBLRDL
TBLWTH
TBLWTL
TRAP
Ws,Wd
Ws,Wd
Ws,Wd
Ws,Wd
#lit16
None
None
None
None
None
ULNK
ULNK
None
DS70032B-page 318
AdvanceInformation
2002 Microchip Technology Inc.
dsPIC30F
TABLE 25-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic
# of
words cycles
# of
Status Flags
Affected
Assembly Syntax
Description
f = f .XOR. WREG
88
XOR
XOR
XOR
XOR
XOR
XOR
ZE
f
1
1
1
1
1
1
1
1
1
1
1
1
N,SZ
f,WREG
WREG = f .XOR. WREG
Wd = lit10 .XOR. Wd
Wd = Wb .XOR. Ws
Wd = Wb .XOR. lit5
N,SZ
N,SZ
N,SZ
N,SZ
None
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
Ws,Wnd
89
ZE
Wnd = Zero Extend Ws
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 319
dsPIC30F
NOTES:
DS70032B-page 320
AdvanceInformation
2002 Microchip Technology Inc.
dsPIC30F
The MPLAB IDE allows the engineer to:
26.0 DEVELOPMENT SUPPORT
• Edit your source files in either assembly or ‘C’
Microchip is offering a comprehensive package of
development tools and libraries to support the
dsPIC30F architecture. In addition, the company is
partnering with many third party tools manufacturers for
additional dsPIC30F support. The Microchip tools will
include:
• One-touch compile and download to dsPIC30F
program memory on emulator or simulator.
Updates all project information.
• Debug using:
- Source files
• MPLAB 6.00 Integrated Development Environ-
- Machine code
ment (IDE)
- Mixed mode source and machine code
• dsPIC30F Language Suite including MPLAB C30
C Compiler, Assembler, Linker and Librarian
The ability to use the MPLAB IDE with multiple
development and debugging targets, allows users to
easily switch from the cost effective simulator to a full
featured emulator with minimal retraining.
• MPLAB SIM Software Simulator
• MPLAB ICE 4000 In-Circuit Emulator
• MPLAB ICD 2 In-Circuit Debugger
26.2 dsPIC30F Language Suite
• PRO MATE II Universal Device Programmer
• PICSTART Plus Development Programmer
The Microchip Technology MPLAB C30 C compiler is a
fully ANSI compliant product with standard libraries for
the dsPIC30F architecture. It is highly optimizing and
takes advantage of many dsPIC30F architecture
specific features to provide efficient software code
generation.
26.1 MPLAB V6.00 Integrated
Development Environment
Software
The MPLAB Integrated Development Environment is
available at no cost. The IDE gives users the flexibility
to edit, compile and emulate all from a single user inter-
face. Engineers can design and develop code for the
dsPIC30F in the same design environment that they
have used for PICmicro microcontrollers.
MPLAB C30 also provides extensions that allow for
excellent support of the hardware, such as interrupts
and peripherals. It is fully integrated with the MPLAB
IDE for high level, source debugging.
• 16-bit native data types
• Efficient use of register based, 3-operand
instructions
The MPLAB IDE is a 32-bit Windows based applica-
tion. It provides many advanced features for the critical
engineer in a modern, easy to use interface. MPLAB
IDE integrates:
• Complex Addressing modes
• Efficient multi-bit shift operations
• Efficient signed/unsigned comparisons
• Full featured, color coded text editor
• Easy to use project manager with visual display
• Source level debugging
MPLAB C30 comes complete with its own assembler,
linker and librarian. These allow the user to write Mixed
mode C and assembly programs and link the resulting
object files into a single executable file. The compiler is
sold separately. The assembler, linker and librarian are
available for free with MPLAB IDE.
• Enhanced source level debugging for ‘C’
(Structures, automatic variables, and so on)
• Customizable toolbar and key mapping
• Dynamic status bar displays processor condition
at a glance
26.3 MPLAB SIM Software Simulator
• Context sensitive, interactive on-line help
• Integrated MPLAB SIM instruction simulator
The MPLAB SIM software simulator allows code devel-
opment in a PC-hosted environment by simulating the
dsPIC30F on an instruction level. On any given instruc-
tion, the data areas can be examined or modified and
stimuli can be applied from a file, or user defined key
press, to any of the pins.
• User interface for PRO MATE II and PICSTART
Plus device programmers (sold separately)
• User interface for MPLAB ICE 4000 In-Circuit
Emulator (sold separately)
• User interface for MPLAB ICD 2 In-Circuit
Debugger
The execution can be performed in single step, execute
until break, or Trace mode.
The MPLAB SIM simulator fully supports symbolic
debugging using the MPLAB C30 compiler and assem-
bler. The software simulator offers the flexibility to
develop and debug code outside of the laboratory envi-
ronment, making it an excellent multi-project software
development tool.
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 321
dsPIC30F
26.4 MPLAB ICE 4000 In-Circuit
Emulator
26.5 MPLAB ICD 2 In-Circuit Debugger
Microchip’s In-Circuit Debugger, MPLAB ICD, is a pow-
erful, low cost, run-time development tool. This tool is
based on the PICmicro and dsPIC30F FLASH devices.
The MPLAB ICD utilizes the in-circuit debugging capa-
bility built into the various devices. This feature, along
with Microchip’s In-Circuit Serial ProgrammingTM proto-
col, offers cost effective, in-circuit debugging from the
graphical user interface of MPLAB ICD. This enables a
designer to develop and debug source code by watching
variables, single-stepping and setting break points. Run-
ning at full speed enables testing hardware in real-time.
The MPLAB ICE 4000 In-Circuit Emulator is intended
to provide the product development engineer with a
complete hardware design tool for the dsPIC30F. Soft-
ware control of the emulator is provided by MPLAB,
allowing editing, building, downloading and source
debugging from a single environment.
The MPLAB ICE 4000 is a full featured emulator sys-
tem with enhanced trace, trigger and data monitoring
features. Interchangeable processor modules allow the
system to be easily reconfigured for emulation of differ-
ent processors. The MPLAB ICE 4000 supports the
extended, high-end PICmicro microcontrollers, the
PIC18CXXX and PIC18FXXX devices, as well as the
dsPIC30F family of digital signal controllers. The mod-
ular architecture of the MPLAB ICE in-circuit emulator
allows expansion to support new devices.
• Full speed operation to the range of the device
• Serial or USB PC connector
• Serial interface externally powered
• USB powered from PC interface
• Low noise power (VPP and VDD) for use with ana-
log and other noise sensitive applications
The MPLAB ICE in-circuit emulator system has been
designed as a real-time emulation system, with
advanced features that are generally found on more
expensive development tools.
• Operation down to 2.0V
• Can be used as an ICD or inexpensive serial
programmer
• Modular application connector as MPLAB ICD
• Limited number of breakpoints
• Full speed emulation, up to 50 MHz bus speed, or
200 MHz external clock speed
• “Smart watch” variable windows
• Low voltage emulation down to 1.8 volts
• Some chip resources required (RAM, program
memory and 2 pins)
• Configured with 2 Mb program emulation memory,
additional modular memory up to 16 Mb
• 64K x 248-bit wide Trace Memory
• Unlimited software breakpoints
26.6 PRO MATE II Universal Device
Programmer
• Complex break, trace and trigger logic
• Multi-level trigger up to 4 levels
The PRO MATE II universal device programmer is a full
featured programmer, capable of operating in Stand-
Alone mode, as well as PC-hosted mode. The
PRO MATE II device programmer is CE compliant.
• Filter trigger functions to trace specific event
• 16-bit Pass counter for triggering on sequential
events
The PRO MATE II device programmer has program-
mable VDD and VPP supplies, which allow it to verify
programmed memory at VDDMIN and VDDMAX for max-
imum reliability when programming, requiring this
capability. It has an LCD display for instructions and
error messages, keys to enter commands, and inter-
changeable socket modules for all package types.
• 16-bit Delay counter
• 48-bit time stamp
• Stopwatch feature
• Time between events
• Statistical performance analysis
• Code coverage analysis
• USB and parallel printer port PC connection
In Stand-Alone mode, the PRO MATE II device pro-
grammer can read, verify, or program PICmicro
devices. It can also set code protection in this mode.
• Runs under MPLAB IDE
• Field upgradable firmware
• DOS Command Line interface for production
• Host, Safe, and “Stand-Alone” operation
• Automatic downloading of object file
• SQTPSM serialization adds unique serial number
to each device programmed
• In-Circuit Serial Programming Kit (sold
separately)
• Interchangeable socket modules supports all
package options (sold separately)
DS70032B-page 322
AdvanceInformation
2002 Microchip Technology Inc.
dsPIC30F
27.0 ELECTRICAL
CHARACTERISTICS
Electrical characteristics are not available at this time.
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 323
dsPIC30F
NOTES:
DS70032B-page 324
AdvanceInformation
2002 Microchip Technology Inc.
dsPIC30F
28.0 DC AND AC
CHARACTERISTICS GRAPHS
AND TABLES
Graphs and tables are not available at this time.
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 325
dsPIC30F
NOTES:
DS70032B-page 326
AdvanceInformation
2002 Microchip Technology Inc.
dsPIC30F
29.0 PACKAGING INFORMATION
29.1 Package Marking Information
18-Lead PDIP (Skinny DIP)
Example
dsPIC30F2011-I/SP
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
0248017
18-Lead SOIC
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
XXXXXXXXXXXX
dsPIC30F2011
-I/SO
YYWWNNN
0248017
28-Lead PDIP (Skinny DIP)
Example
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
dsPIC30F3010-I/SP
0248017
28-Lead SOIC
Example
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
dsPIC30F4011-I/SO
YYWWNNN
0248017
Legend: XX...X Customer specific information*
Y
Year code (last digit of calendar year)
YY
WW
NNN
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
*
Standard PICmicro device marking consists of Microchip part number, year code, week code, and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 327
dsPIC30F
29.2 Package Marking Information (Continued)
40-Lead PDIP
Example
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
dsPIC30F4011-I/P
0248017
YYWWNNN
44-Lead TQFP
Example
dsPIC30F4011
-I/PT
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
0248017
64-Lead TQFP
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
dsPIC30F6012
-I/PT
0236017
80-Lead TQFP
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
dsPIC30F5013
-I/PT
0236017
DS70032B-page 328
AdvanceInformation
2002 Microchip Technology Inc.
dsPIC30F
18-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
α
n
1
E
A2
A
L
c
A1
B1
β
p
B
eB
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
18
MAX
n
p
Number of Pins
Pitch
18
.100
.155
.130
2.54
Top to Seating Plane
A
.140
.170
3.56
2.92
3.94
3.30
4.32
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.115
.015
.300
.240
.890
.125
.008
.045
.014
.310
5
.145
3.68
0.38
7.62
6.10
22.61
3.18
0.20
1.14
0.36
7.87
5
.313
.250
.898
.130
.012
.058
.018
.370
10
.325
.260
.905
.135
.015
.070
.022
.430
15
7.94
6.35
22.80
3.30
0.29
1.46
0.46
9.40
10
8.26
6.60
22.99
3.43
0.38
1.78
0.56
10.92
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-007
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 329
dsPIC30F
18-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC)
E
p
E1
D
2
B
n
1
h
α
45°
c
A2
A
φ
β
L
A1
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
18
MAX
n
p
Number of Pins
Pitch
18
.050
.099
.091
.008
.407
.295
.454
.020
.033
4
1.27
Overall Height
A
.093
.104
2.36
2.24
2.50
2.31
0.20
10.34
7.49
11.53
0.50
0.84
4
2.64
2.39
0.30
10.67
7.59
11.73
0.74
1.27
8
Molded Package Thickness
Standoff
A2
A1
E
.088
.004
.394
.291
.446
.010
.016
0
.094
.012
.420
.299
.462
.029
.050
8
§
0.10
10.01
7.39
11.33
0.25
0.41
0
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
φ
Foot Angle
c
Lead Thickness
Lead Width
.009
.014
0
.011
.017
12
.012
.020
15
0.23
0.36
0
0.27
0.42
12
0.30
0.51
15
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
0
12
15
0
12
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-051
DS70032B-page 330
AdvanceInformation
2002 Microchip Technology Inc.
dsPIC30F
28-Lead Skinny Plastic Dual In-line (SP) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
L
A
c
B1
β
A1
eB
p
B
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
28
MAX
n
p
Number of Pins
Pitch
28
.100
.150
.130
2.54
3.81
3.30
Top to Seating Plane
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A
A2
A1
E
.140
.160
3.56
4.06
.125
.015
.300
.275
1.345
.125
.008
.040
.016
.320
.135
3.18
0.38
7.62
6.99
34.16
3.18
0.20
1.02
3.43
.310
.285
1.365
.130
.012
.053
.019
.350
10
.325
.295
1.385
.135
.015
.065
.022
.430
15
7.87
7.24
8.26
7.49
35.18
3.43
0.38
1.65
0.56
10.92
15
E1
D
34.67
3.30
Tip to Seating Plane
Lead Thickness
L
c
0.29
Upper Lead Width
B1
B
1.33
Lower Lead Width
0.41
8.13
5
0.48
8.89
10
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
5
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-095
Drawing No. C04-070
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 331
dsPIC30F
28-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC)
E
E1
p
D
B
2
n
1
h
α
45°
c
A2
A
φ
β
L
A1
Units
INCHES*
NOM
MILLIMETERS
NOM
Dimension Limits
MIN
MAX
MIN
MAX
n
p
Number of Pins
Pitch
28
28
.050
.099
.091
.008
.407
.295
.704
.020
.033
4
1.27
2.50
2.31
0.20
10.34
7.49
17.87
0.50
0.84
4
Overall Height
A
.093
.104
2.36
2.64
Molded Package Thickness
Standoff
A2
A1
E
.088
.004
.394
.288
.695
.010
.016
0
.094
.012
.420
.299
.712
.029
.050
8
2.24
0.10
10.01
7.32
17.65
0.25
0.41
0
2.39
0.30
10.67
7.59
18.08
0.74
1.27
8
§
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
φ
Foot Angle Top
c
Lead Thickness
Lead Width
.009
.014
0
.011
.017
12
.013
.020
15
0.23
0.36
0
0.28
0.42
12
0.33
0.51
15
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
0
12
15
0
12
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-052
DS70032B-page 332
AdvanceInformation
2002 Microchip Technology Inc.
dsPIC30F
40-Lead Plastic Dual In-line (P) – 600 mil (PDIP)
E1
D
2
α
n
1
E
A2
L
A
c
B1
B
β
A1
p
eB
Units
INCHES*
NOM
MILLIMETERS
NOM
Dimension Limits
MIN
MAX
MIN
MAX
n
p
Number of Pins
Pitch
40
40
.100
.175
.150
2.54
4.45
3.81
Top to Seating Plane
A
.160
.190
.160
4.06
4.83
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.140
.015
.595
.530
2.045
.120
.008
.030
.014
.620
5
3.56
0.38
15.11
13.46
51.94
3.05
0.20
0.76
0.36
15.75
5
4.06
.600
.545
2.058
.130
.012
.050
.018
.650
10
.625
.560
2.065
.135
.015
.070
.022
.680
15
15.24
13.84
52.26
3.30
0.29
1.27
0.46
16.51
10
15.88
14.22
52.45
3.43
0.38
1.78
0.56
17.27
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
§
eB
α
β
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
5
10
15
5
10
15
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-011
Drawing No. C04-016
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 333
dsPIC30F
44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
E
E1
#leads=n1
p
D1
D
2
1
B
n
°
CH x 45
α
A
c
φ
β
A1
A2
L
(F)
Units
INCHES
NOM
MILLIMETERS*
Dimension Limits
MIN
MAX
MIN
NOM
44
MAX
n
p
Number of Pins
Pitch
44
.031
11
0.80
11
Pins per Side
Overall Height
n1
A
.039
.037
.002
.018
.043
.039
.004
.024
.039
3.5
.047
1.00
0.95
1.10
1.00
0.10
0.60
1.20
Molded Package Thickness
Standoff
A2
A1
L
(F)
φ
.041
.006
.030
1.05
0.15
0.75
§
0.05
0.45
1.00
0
Foot Length
Footprint (Reference)
Foot Angle
0
.463
.463
.390
.390
.004
.012
.025
5
7
.482
.482
.398
.398
.008
.017
.045
15
3.5
12.00
12.00
10.00
10.00
0.15
0.38
0.89
10
7
12.25
12.25
10.10
10.10
0.20
0.44
1.14
15
Overall Width
E
D
.472
.472
.394
.394
.006
.015
.035
10
11.75
11.75
9.90
9.90
0.09
0.30
0.64
5
Overall Length
Molded Package Width
Molded Package Length
Lead Thickness
E1
D1
c
Lead Width
B
CH
α
Pin 1 Corner Chamfer
Mold Draft Angle Top
Mold Draft Angle Bottom
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-026
Drawing No. C04-076
DS70032B-page 334
AdvanceInformation
2002 Microchip Technology Inc.
dsPIC30F
64-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
E
E1
#leads=n1
p
D1
D
2
1
B
n
°
CH x 45
α
A
c
A2
L
φ
β
A1
(F)
Units
INCHES
NOM
MILLIMETERS*
Dimension Limits
MIN
MAX
MIN
NOM
64
MAX
n
p
Number of Pins
Pitch
64
.020
16
0.50
16
Pins per Side
Overall Height
n1
A
.039
.043
.039
.006
.024
.039
3.5
.047
1.00
0.95
1.10
1.00
0.15
0.60
1.00
3.5
1.20
Molded Package Thickness
Standoff
A2
A1
L
(F)
φ
.037
.002
.018
.041
.010
.030
1.05
0.25
0.75
§
0.05
0.45
Foot Length
Footprint (Reference)
Foot Angle
0
.463
.463
.390
.390
.005
.007
.025
5
7
.482
.482
.398
.398
.009
.011
.045
15
0
11.75
11.75
9.90
9.90
0.13
0.17
0.64
5
7
12.25
12.25
10.10
10.10
0.23
0.27
1.14
15
Overall Width
E
D
.472
.472
.394
.394
.007
.009
.035
10
12.00
12.00
10.00
10.00
0.18
0.22
0.89
10
Overall Length
Molded Package Width
Molded Package Length
Lead Thickness
E1
D1
c
Lead Width
B
Pin 1 Corner Chamfer
Mold Draft Angle Top
Mold Draft Angle Bottom
CH
α
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-026
Drawing No. C04-085
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 335
dsPIC30F
80-Lead Plastic Thin Quad Flatpack (PT) 12x12x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
E
E1
#leads=n1
p
D1
D
2
B
c
1
n
°
CH x 45
A
α
A2
φ
β
L
A1
(F)
Units
INCHES
NOM
MILLIMETERS*
Dimension Limits
MIN
MAX
MIN
NOM
80
MAX
n
p
Number of Pins
Pitch
80
.020
20
0.50
20
Pins per Side
Overall Height
n1
A
.039
.037
.002
.018
.043
.039
.004
.024
.039
3.5
.047
1.00
0.95
1.10
1.00
0.10
0.60
1.00
3.5
1.20
Molded Package Thickness
Standoff
A2
A1
L
(F)
φ
.041
.006
.030
1.05
0.15
0.75
§
0.05
0.45
Foot Length
Footprint (Reference)
Foot Angle
0
.541
.541
.463
.463
.004
.007
.025
5
7
.561
.561
.482
.482
.008
.011
.045
15
0
13.75
13.75
11.75
11.75
0.09
0.17
0.64
5
7
14.25
14.25
12.25
12.25
0.20
0.27
1.14
15
Overall Width
E
D
.551
.551
.472
.472
.006
.009
.035
10
14.00
14.00
12.00
12.00
0.15
0.22
0.89
10
Overall Length
Molded Package Width
Molded Package Length
Lead Thickness
E1
D1
c
Lead Width
B
CH
α
Pin 1 Corner Chamfer
Mold Draft Angle Top
Mold Draft Angle Bottom
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-026
Drawing No. C04-092
DS70032B-page 336
AdvanceInformation
2002 Microchip Technology Inc.
dsPIC30F
INDEX
Analog-to-Digital Converter. See A/D
A
Automatic Clock Stretch .................................................. 218
During 10-bit Addressing (STREN = 1) ................... 218
During 7-bit Addressing (STREN = 1) ..................... 218
Receive Mode .......................................................... 218
Transmit Mode ......................................................... 218
A/D ............................................................................265, 277
AC-Link Mode Operation .................................................. 255
Setup ........................................................................ 255
Word Size Issues ..................................................... 255
16-bit Mode .............................................................. 255
20-bit Mode .............................................................. 255
10-bit High Speed Analog-to-Digital Converter. See A/D
10-bit High Speed A/D
B
Aborting a Conversion ............................................. 280
ADCHS .................................................................... 277
ADCON1 .................................................................. 277
ADCON2 .................................................................. 277
ADCON3 .................................................................. 277
ADPCFG .................................................................. 277
Analog Input Model .................................................. 282
Configuring Analog Port Pins ................................... 284
Connection Considerations ...................................... 284
Conversion Operation .............................................. 279
Effects of a RESET .................................................. 283
Operation During CPU IDLE Mode .......................... 283
Operation During CPU SLEEP Mode ...................... 283
Output Formats ........................................................ 284
Power-down Modes ................................................. 283
Programming the Start-of-Conversion Trigger ......... 280
Register Map ............................................................ 285
Result Buffer ............................................................ 279
Sampling Requirements ........................................... 282
Selecting the Conversion Clock ............................... 280
Selecting the Conversion Sequence ........................ 279
Tad vs. Device Operating Frequencies Table .......... 281
12-Bit Analog-to-Digital Converter (A/D) Module ............. 265
12-Bit A/D
Barrel Shifter ...................................................................... 67
Bit Reversed Addressing ................................................... 76
Example ..................................................................... 76
Implementation .......................................................... 76
Sequence Table (16-Entry) ........................................ 77
Block Diagrams
Barrel Shifter Simplified ............................................. 67
CAN Buffers and Protocol Engine ........................... 246
CPU Core .................................................................. 20
Dead-Time Control Unit for One PWM
Output Pair ...................................................... 180
Dead-Time Control Units ......................................... 180
DSP Engine ............................................................... 62
External Power-on Reset Circuit .............................. 302
Input Capture Module .............................................. 151
Interrupt Controller ..................................................... 88
2
I C Receive .............................................................. 209
2
I C Transmit ............................................................. 209
Oscillator System ..................................................... 294
Output Compare Mode ............................................ 155
PWM Module ........................................................... 174
PWM Module, One Output Pair,
Complementary Mode ..................................... 178
PWM Module, One Output Pair,
ADCHS .................................................................... 265
ADCON1 .................................................................. 265
ADCON2 .................................................................. 265
ADCON3 .................................................................. 265
ADCSSL ................................................................... 265
ADPCFG .................................................................. 265
12-bit A/D
Independent Mode ........................................... 181
PWM Time-Base ...................................................... 175
Quadrature Encoder Interface ................................. 163
RESET System ........................................................ 300
Simplified DCI Module ............................................. 248
SPI ........................................................................... 199
SPI Master/Slave Connection .................................. 199
UART Receiver ........................................................ 234
UART Transmitter .................................................... 233
10-bit High Speed A/D Functional ........................... 278
12-Bit A/D Functional ............................................... 265
16-bit Timer1 Module ............................................... 135
32-bit Timer (Timer2/Timer3) Module ...................... 140
32-bit Timer (Timer4/Timer5) Module ...................... 146
BOR. See Brown-out Reset
Aborting a Conversion ............................................. 267
Analog Input Model .................................................. 268
Configuring Analog Port Pins ................................... 270
Connection Considerations ...................................... 270
Conversion Operation .............................................. 266
Effects of a RESET .................................................. 269
Operation During CPU IDLE Mode .......................... 269
Operation During CPU SLEEP Mode ...................... 269
Output Formats ........................................................ 269
Power-down Modes ................................................. 269
Programming the Start-of-Conversion Trigger ......... 266
Register Map ............................................................ 271
Result Buffer ............................................................ 266
Sampling Requirements ........................................... 268
Selecting the Conversion Clock ............................... 267
Selecting the Conversion Sequence ........................ 266
Tad vs. Device Operating Frequencies .................... 267
Brown-out Reset (BOR) ................................................... 293
C
CAN Module .................................................................... 245
Overview .................................................................. 245
Overview of the Module ........................................... 245
Transmit/Receive Buffers ........................................ 245
Center Aligned PWM ....................................................... 177
Address Generator Units .................................................... 69
Alternate 16-bit Timer/Counter ......................................... 165
Quadrature Encoder Interface Interrupts ................. 166
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 337
DSPIC30F
Code Examples
CSDO Pin ................................................................ 247
Data Justification Control Bit .................................... 251
Device Frequencies for Common Codec
Data EEPROM Block Erase .......................................56
Data EEPROM Block Write ........................................59
Data EEPROM Bulk Erase .........................................56
Data EEPROM Read .................................................55
Data EEPROM Word Erase .......................................57
Data EEPROM Word Write ........................................58
Erasing a Row of Program Memory ...........................49
Initiating a Programming Sequence ...........................51
Loading Write Latches ...............................................50
Program Space Data Read Through Data
Space Within a REPEAT Loop ..........................43
Reading a FLASH Program Memory Byte .................46
Reading a FLASH Program Memory Word ................46
SE and ZE Operation .................................................37
Writing a Single Program Latch Location in
CSCK Frequencies Table ................................ 251
Digital Loopback Mode ............................................ 253
Frame Sync Generator ............................................ 249
Frame Sync Mode Control Bits ................................ 249
Interrupts .................................................................. 253
Introduction .............................................................. 247
I/O Pins .................................................................... 247
Master Frame Sync Operation ................................. 249
Module Enable ......................................................... 248
Operation ................................................................. 248
Operation During CPU IDLE Mode .......................... 254
Operation During CPU SLEEP Mode ...................... 254
Receive Slot Enable Bits ......................................... 252
Receive Status Bits .................................................. 253
Register Map ........................................................... 258
Sample Clock Edge Select Control Bit .................... 251
SCK Pin ................................................................... 247
Slave Frame Sync Operation ................................... 249
Slot Enable Bits Operation with Frame Sync ........... 252
Slot Status Bits ........................................................ 253
Synchronous Data Transfers ................................... 252
Transmit Slot Enable Bits ........................................ 251
Transmit Status Bits ................................................. 253
Transmit/Receive Shift Register .............................. 247
Underflow Mode Control Bit ..................................... 253
Word Size Selection Bits ......................................... 248
Dead-Time Generators .................................................... 179
Assignment .............................................................. 179
Distortion .................................................................. 179
Ranges .................................................................... 179
Selection Bits ........................................................... 179
Development Support ...................................................... 321
Device Overview ................................................................ 15
Disabling the UART ......................................................... 235
Divide Support ................................................................... 32
DSP Engine ....................................................................... 61
Multiplier .................................................................... 63
DSP Engine Mode Selection .............................................. 68
dsPIC30F Language Suite ............................................... 321
Dual Output Compare Match Mode ................................. 156
Continuous Pulse Mode ........................................... 156
Dual Compare, Continuous Output Pulse Mode
Byte Mode ..........................................................47
Writing a Single Program Latch Location in
Word Mode ........................................................47
Code Protection ...............................................................293
Complementary PWM Operation .....................................178
Control Registers ...............................................................48
NVMADR ....................................................................48
NVMCON ...................................................................48
NVMKEY ....................................................................48
Core Architecture
Overview ....................................................................19
Core Register Map .............................................................41
Count Direction Status .....................................................164
D
Data Accumulators and Adder/ .............................. 64, 65, 66
Data Address Space ..........................................................36
Access RAM ...............................................................38
Alignment ...................................................................37
Alignment (Figure) ......................................................37
Effect of Invalid Memory Accesses ............................37
MCU and DSP (MAC Class) Instructions
Example .............................................................40
Memory Map ..............................................................38
Memory Map Example ...............................................39
Spaces .......................................................................36
Width ..........................................................................37
Data Converter Interface (DCI) Module ...........................247
Data EEPROM Memory .....................................................55
Erasing .......................................................................56
Erasing, Block ............................................................56
Erasing, Entire Memory ..............................................56
Erasing, Word ............................................................57
Protection Against Spurious Write .............................60
Reading ......................................................................55
Write Verify .................................................................60
Writing ........................................................................57
Writing, Block .............................................................59
Writing, Word .............................................................58
Data Space Organization ...................................................69
DC and AC Characteristics Graphs and Tables ...............325
DCI Module
Diagram ........................................................... 158
Dual Compare, Single Output Pulse Mode
Diagram ........................................................... 157
Single Pulse Mode ................................................... 156
E
Edge Aligned PWM .......................................................... 177
Electrical Characteristics .................................................. 323
Enabling and Setting Up UART ....................................... 235
Alternate I/O ............................................................. 235
Setting Up Data, Parity and STOP Bit
Selections ........................................................ 235
Enabling the UART .......................................................... 235
Equations
A/D Sampling Time ...........................................268, 282
Bit Clock Frequency ................................................. 251
COFSG Period ......................................................... 249
PWM Period ............................................................. 177
PWM Resolution ...................................................... 177
Serial Clock Rate ..................................................... 226
Errata ................................................................................. 13
Bit Clock Generator ..................................................251
Buffer Alignment with Data Frames .........................252
Buffer Control ...........................................................247
Buffer Data Alignment ..............................................247
Buffer Length Control ...............................................252
COFS Pin .................................................................247
CSDI Pin ..................................................................247
CSDO Mode Bit ........................................................253
DS70032B-page 338
Advance Information
2002 Microchip Technology Inc.
dsPIC30F
2
Exception Processing ......................................................... 83
Exception Sequence .......................................................... 86
Interrupt Stack Frame ................................................ 86
Interrupt/ ..................................................................... 86
RESET Sources ......................................................... 85
Trap Sources ............................................................. 85
External Interrupt Requests ............................................... 87
I C Master Mode
Baud Rate Generator .............................................. 226
Bus Collision During a RESTART Condition ........... 226
Bus Collision During a START Condition ................ 226
Bus Collision During a STOP Condition .................. 226
Clock Arbitration ...................................................... 226
Multi-Master Communication, Bus Collision,
and Bus Arbitration .......................................... 226
Reception ................................................................ 224
Transmission ........................................................... 222
F
Fast Context Saving ........................................................... 87
Firmware Instructions ....................................................... 311
FLASH Program Memory ................................................... 45
In-Circuit Serial Programming (ICSP) ........................ 45
Run Time Self-Programming (RTSP) ......................... 45
Table Reads and Table Writes .................................. 45
2
I C Master Mode Operation ............................................. 221
I C Master Mode Support ................................................ 221
I C Module ....................................................................... 209
2
2
General Call Address Support ................................. 221
Interrupts ................................................................. 221
IPMI Support ............................................................ 221
Operating Function Description ............................... 209
Pin Configuration ..................................................... 210
Register Map ........................................................... 227
Registers ................................................................. 210
Slope Control ........................................................... 221
Software Controlled Clock Stretching
I
ID Locations ..................................................................... 293
In-Circuit Serial Programming .......................................... 308
In-Circuit Serial Programming (ICSP) .............................. 293
Independent PWM Output ................................................ 181
Input Capture Module ....................................................... 151
Input Change Notification Module .................................... 120
Register Map (bit 15-8) ............................................ 120
Register Map (bit 7-0) .............................................. 120
Instruction Set
Overview .................................................................. 314
Instruction Addressing Modes ............................................ 69
File Register Instructions ........................................... 70
Fundamental Modes Supported ................................. 69
MAC Instructions ........................................................ 70
MCU Instructions ....................................................... 70
Move and Accumulator Instructions ........................... 70
Other Instructions ....................................................... 70
Instruction Flow .................................................................. 26
Clocking Scheme ....................................................... 26
Fetch and Pre-Decode Mechanism ........................... 26
Pipeline - 1-Word, 1-Cycle (Figure) ........................... 28
Pipeline - 1-Word, 2-Cycle MOV.D
(STREN = 1) .................................................... 221
Various Modes ......................................................... 209
2
I C Module
Addresses ................................................................ 210
I C Module Operation During CPU SLEEP and
IDLE Modes ............................................................. 226
I C 10-bit Slave Mode Operation ..................................... 215
Reception ................................................................ 215
Transmission ........................................................... 215
I C 7-bit Slave Mode Operation ....................................... 210
2
2
2
Programmer’s Model ............................................... 210
Reception ................................................................ 213
Transmission ........................................................... 211
2
I S Mode Operation ......................................................... 256
Data Justification ..................................................... 256
Frame and Data Word Length Selection ................. 256
I/O Ports ........................................................................... 115
Parallel ..................................................................... 115
Operations (Figure) ............................................ 29
Pipeline - 1-Word, 2-Cycle Table
M
Operations (Figure) ............................................ 29
Pipeline - 1-Word, 2-Cycle with Instruction
Memory Organization ........................................................ 33
3 Module .......................................................................... 139
ADC Event Trigger ................................................... 140
Gate Operation ........................................................ 140
Interrupt ................................................................... 141
Operation During SLEEP Mode ............................... 141
Register Map ........................................................... 142
Timer Prescaler ....................................................... 141
32-bit Synchronous Counter Mode .......................... 139
32-bit Timer Mode .................................................... 139
5 Module Gate Operation ................................................ 146
Interrupt ................................................................... 147
Operation During SLEEP Mode ............................... 147
Register Map ........................................................... 148
Timer Prescaler ....................................................... 147
32-bit Synchronous Counter Mode .......................... 145
32-bit Timer Mode .................................................... 145
Modulo Addressing ............................................................ 73
Applicability ................................................................ 75
Decrementing Buffer Operation Example .................. 75
Incrementing Buffer Operation Example .................... 74
Restrictions ................................................................ 75
Start and End Address .............................................. 73
W Address Register Selection ................................... 74
Stall (Figure) ...................................................... 29
Pipeline - 1-Word, 2-Cycle (Figure) ........................... 28
Pipeline - 2-Word, 2-Cycle DO, DOW (Figure) .......... 29
Pipeline - 2-Word, 2-Cycle GOTO,
CALL (Figure) .................................................... 29
Types ......................................................................... 28
Instruction Set .................................................................. 311
Instruction Stalls ................................................................. 71
and Exceptions .......................................................... 72
and Flow Change Instructions ................................... 72
and PSV ..................................................................... 72
Introduction ................................................................ 71
Raw Dependency Detection ...................................... 71
WAR Dependency Detection ..................................... 72
16-bit Integer and Fractional Modes Example ................... 63
2
Inter-Integrated Circuit. See I C
Interrupt Controller
Register Map .............................................................. 89
Interrupt Priority .................................................................. 83
RESET Sequence ...................................................... 85
Traps .......................................................................... 85
2
I C .................................................................................... 209
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 339
DSPIC30F
Motor Control PWM Module .............................................173
MPLAB ICD 2 In-Circuit Debugger ...................................322
MPLAB ICE 4000 In-Circuit Emulator ..............................322
MPLAB SIM Software Simulator ......................................321
MPLAB V6.00 Integrated Development
Environment Software ..............................................321
Multi-Channel Mode Operation ........................................254
Codec Configuration ................................................255
Setup Details for Single Channel Codec ..................254
Setup Values Table ..................................................254
Table Instructions
TBLRDH ............................................................ 34
TBLRDL ............................................................. 34
TBLWTH ............................................................ 34
TBLWTL ............................................................ 34
Program Counter ............................................................... 22
Program Loop Control ........................................................ 30
DO and REPEAT Restrictions ................................... 31
DO Early Termination ................................................ 31
DO Loop Construct .................................................... 30
DO Loop Nesting ....................................................... 31
DO Loops and Interrupts ........................................... 31
REPEAT Early Termination ....................................... 30
REPEAT Loop Construct ........................................... 30
REPEAT Loop Interrupt and Nesting ......................... 30
Program Space Data Read Through Data Space
O
Oscillator Configurations ..................................................295
Fail Safe Clock Monitor ............................................297
Fast RC (FRC) .........................................................296
Initial Clock Source Selection ...................................295
Low Power RC (LPRC) ............................................296
LP Osc Control .........................................................296
PLL ...........................................................................296
Start-up Timer (OST) ...............................................296
Oscillator Operating Modes Table ....................................293
Oscillator Selection ..........................................................293
Output Compare Interrupts ..............................................160
Output Compare Mode
Within a REPEAT Loop Diagram ............................... 43
Program Space Visibility
Window into Program Space Operation .................... 35
Program Space Visibility from Data Space ........................ 35
Data Pre-fetch from Program Space Within
a REPEAT Loop ................................................ 43
Programmable ................................................................. 293
Programmable Digital Noise Filters ................................. 164
Programmer’s Model .......................................................... 21
Diagram ..................................................................... 23
Programming Operations ................................................... 48
Algorithm for Program FLASH ................................... 48
Erasing a Row of Program Memory ........................... 49
Initiating the Programming Sequence ........................ 51
Loading Write Latches ............................................... 50
Programming, Device Instructions ................................... 311
Protection Against Accidental Writes to OSCCON .......... 297
PWM
Register Map ............................................................161
Output Compare Module ..................................................155
Output Compare Operation During CPU IDLE Mode .......160
Output Compare SLEEP Mode Operation .......................160
P
Packaging
Marking Information .................................................327
Packaging Information .....................................................327
Pinout Descriptions ............................................................15
PORTA
Motor Control PWM Register Map ........................... 185
PWM Duty Cycle Comparison Units ................................ 178
Duty Cycle Register Buffers ..................................... 178
PWM Fault Pins ............................................................... 183
Enable Bits ............................................................... 183
Fault States .............................................................. 183
Modes ...................................................................... 183
Cycle-by-Cycle ................................................. 183
Latched ............................................................ 183
Priority ...................................................................... 183
PWM Operation During CPU IDLE Mode ........................ 184
PWM Operation During CPU SLEEP Mode ..................... 184
PWM Output and Polarity Control .................................... 182
Output Pin Control ................................................... 182
PWM Output Override ...................................................... 182
Complementary Output Mode .................................. 182
Synchronization ....................................................... 182
PWM Period ..................................................................... 177
PWM Special Event Trigger ............................................. 184
Postscaler ................................................................ 184
PWM Time-Base .............................................................. 175
Continuous Up/Down Counting Modes .................... 176
Free Running Mode ................................................. 176
Postscaler ................................................................ 176
Prescaler .................................................................. 176
Single Shot Mode .................................................... 176
PWM Time-Base Interrupts .............................................. 176
Continuous Up/Down Counting Mode ..................... 176
Double Update Mode ............................................... 176
Free Running Mode ................................................. 176
Single Shot Mode .................................................... 176
PWM Update Lockout ...................................................... 183
Register Map ............................................................116
PORTB
Register Map ............................................................118
PORTC
Register Map ............................................................118
PORTD
Register Map ............................................................118
PORTE
Register Map ............................................................118
PORTF
Register Map ............................................................118
PORTG
Register Map ............................................................119
POR. See Power-on Reset
Position Measurement Mode ...........................................164
Power Saving Modes .......................................................307
IDLE .........................................................................307
SLEEP ......................................................................307
Power-on Reset (POR) ....................................................293
Oscillator Start-up Timer (OST) ...............................293
Power-up Timer (PWRT) ..........................................293
PRO MATE II Universal Device Programmer ...................322
Product Identification System ...........................................347
Program Address Space ....................................................33
Alignment and Data Access Using
Table Instructions ...............................................34
Construction ...............................................................33
Data Access from, Address Generation .....................33
Memory Map ..............................................................36
DS70032B-page 340
Advance Information
2002 Microchip Technology Inc.
dsPIC30F
LATG (Read/Write PORTG PIO Latch) Register ..... 131
MAXCNT (Maximum Count) Register ...................... 171
MODCON (Modulo and Bit-Reversed
Q
QEI Module
Operation During CPU IDLE Mode .......................... 165
Addressing Control) Register ............................ 78
NVMADR Register ..................................................... 53
NVMCON Register .................................................... 52
NVMKEY Register ..................................................... 53
OCxCON (Output Compare Control x) Register ...... 162
OSCCON (Oscillator Control) Register .................... 298
OVDCON (Output Override Control) Register ......... 193
PDC1 (PWM Duty Cycle 1) Register ....................... 194
PDC2 (PWM Duty Cycle 2) Register ....................... 194
PDC3 (PWM Duty Cycle 3) Register ....................... 195
PDC4 (PWM Duty Cycle 4) Register ....................... 195
PORTA (Read Pin/Write PORTA Latch) Register ... 121
PORTB -(Read PORTB PIO Pin/Write
PORTB PIO Latch) Register ............................ 123
PORTC (Read PORTC PIO Pin/Write
PORTC PIO Latch) Register ........................... 124
PORTD (Read PORTD PIO Pin/Write
PORTD PIO Latch) Register ........................... 126
PORTE (Read PORTE PIO Pin/Write
PORTE PIO Latch) Register ............................ 127
PORTF (Read PORTF PIO Pin/Write
Operation During CPU SLEEP Mode ...................... 165
Register Map ............................................................ 167
Quadrature Encoder Interface Logic ................................ 164
Quadrature Encoder Interface (QEI) Module ................... 163
R
Registers
ADCHS (A/D Input Select) Register ................. 275, 291
ADCON1 (A/D Control) Register1 .................... 272, 286
ADCON2 (A/D Control) Register2 .................... 273, 288
ADCON3 (A/D Control) Register3 .................... 274, 290
ADCSSL (A/D Input Scan Select) Register ...... 276, 292
ADPCFG (A/D Port Configuration) Register .... 276, 292
CNEN1 (Input Change Notification Interrupt
Enable) Register1 ............................................ 131
CNEN2 (Input Change Notification Interrupt
Enable) Register2 ............................................ 132
CNPU1 (Input Change Notification Pull-up
Enable) Register1 ............................................ 132
CNPU2 (Input Change Notification Pull-up
Enable) Register2 ............................................ 133
CORCON (CPU Mode Control) Register ................... 68
DCICON1 (DCI Module Control) Register1 .............. 259
DCICON2 (DCI Module Control) Register2 .............. 260
DCICON3 (DCI Module Control) Register3 .............. 261
DCISTAT (DCI Status) Register .............................. 262
DFLTCON (Digital Dilter Control) Register .............. 170
DTCON1 (Dead-Time Control) Register1 ................ 190
DTCON2 (Dead-Time Control) Register2 ................ 191
FLTACON (Fault A Control) Register ...................... 192
FLTBCON (Fault B Control) Register ...................... 192
FOSC (Oscillator Selection Control) Register .......... 299
FWDT (Configuration bits for WDT) Register ........... 306
ICxCON (Input Capture x Control) Register ............. 154
IEC0 (Interrupt Enable Control) Register0 ................. 97
IEC1 (Interrupt Enable Control) Register1 ................. 99
IEC2 (Interrupt Enable Control) Register2 ............... 101
IFS0 (Interrupt Flag Status) Register0 ....................... 92
IFS1 (Interrupt Flag Status) Register1 ....................... 94
IFS2 (Interrupt Flag Status) Register2 ....................... 96
INTCON1 (Interrupt Control) Register1 ..................... 90
INTCON2 (Interrupt Control) Register2 ..................... 91
IPC0 (Interrupt Priority Control) Register0 ............... 102
IPC1 (Interrupt Priority Control) Register1 ............... 103
IPC10 (Interrupt Priority Control) Register10 ........... 112
IPC11 (Interrupt Priority Control) Register11 ........... 113
IPC2 (Interrupt Priority Control) Register2 ............... 104
IPC3 (Interrupt Priority Control) Register3 ............... 105
IPC4 (Interrupt Priority Control) Register4 ............... 106
IPC5 (Interrupt Priority Control) Register5 ............... 107
IPC6 (Interrupt Priority Control) Register6 ............... 108
IPC7 (Interrupt Priority Control) Register7 ............... 109
IPC8 (Interrupt Priority Control) Register8 ............... 110
IPC9 (Interrupt Priority Control) Register9 ............... 111
PORTF PIO Latch) Register ............................ 129
PORTG (Read PORTG PIO Pin/Write
PORTG PIO Latch) Register ........................... 130
POSCNT (16-bit Position Counter) Register ........... 171
PTCON (PWM Time-Base Control) Register ........... 186
PTMR (PWM Time-Base Count) Register ............... 187
PWM Time-Base Period) Register ........................... 187
PWMCON1 (PWM Control) Register1 ..................... 188
PWMCON2 (PWM Control) Register2 ..................... 189
QEICON (QEI Control) Register .............................. 168
RCON (RESET and System Control) Register ........ 304
RSCON (Receive Slot Control) Register ................. 263
SEVTCMP (Special Event Trigger Compare
Count) Register ............................................... 188
SPIxCON (SPI Control) Register ............................. 206
SPIxSTAT (SPI Status) Register ............................. 205
STATUS (SR) Register .............................................. 24
TRISA (PORTA Data Direction) Register ................ 121
TRISB (PORTB PIO Data Direction) Register ......... 122
TRISC (PORTC PIO Data Direction) Register ......... 124
TRISD (PORTD PIO Data Direction) Register ......... 125
TRISE (PORTE PIO Data Direction) Register ......... 127
TRISF (PORTF PIO Data Direction) Register ......... 128
TRISG (PORTG PIO Data Direction) Register ........ 130
TSCON (Transmit Slot Control) Register ................. 263
T1CON (Timer1 Control) Register ........................... 138
T2CON (Timer2 Control) Register ........................... 143
T3CON (Timer3 Control) Register ........................... 144
T4CON (Timer4 Control) Register ........................... 149
T5CON (Timer5 Control) Register ........................... 150
UxBRG (UARTx Baud Rate) Register ..................... 244
UxMODE (UARTx Mode) Register .......................... 240
UxRXREG (UARTx Receive) Register .................... 243
UxSTA (UARTx Status and Control) Register ......... 241
XBREV (X WAGU Bit Reversal Addressing
2
I2CCON (I C Control) Register ................................ 230
2
I2CSTAT (I C Status) Register ................................ 228
Control) Register ............................................... 81
XMODEND (X AGU Modulo Addressing End)
Register ............................................................. 79
XMODSRT (X AGU Modulo Addressing Start)
LATA (Read/Write PORTA Latch) Register ............. 122
LATB (Read/Write PORTB PIO Latch) Register ...... 123
LATC (Read/Write PORTC PIO Latch) Register ...... 125
LATD (Read/Write PORTD PIO Latch) Register ...... 126
LATE (Read/Write PORTE PIO Latch) Register ...... 128
LATF (Read/Write PORTF PIO Latch) Register ...... 129
Register ............................................................. 79
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 341
DSPIC30F
YMODEND (Y AGU Modulo Addressing End)
Register ..............................................................80
YMODSRT (Y AGU Modulo Addressing Start)
Symbols used in Roadrunner Opcode Descriptions ........ 312
System Integration ........................................................... 293
Overview .................................................................. 293
Register ..............................................................80
RESET ..................................................................... 293, 300
RESET Vectors ..................................................................86
RESETS
BOR, Programmable ................................................302
POR .........................................................................300
Operating without FSCM and PWRT ...............302
POR with Long Crystal Start-up Time ......................302
RTSP Operation .................................................................48
T
Table Read
Byte Modes ................................................................ 46
Using Table Read Instructions ................................... 46
Word Mode ................................................................ 46
Table Write
Byte Mode .................................................................. 47
Using Table Write Instructions ................................... 47
Word Mode ................................................................ 47
Timer Operation During CPU Idle Mode .......................... 166
Timer Operation During CPU SLEEP Mode .................... 165
Timer1 Module ................................................................. 135
Gate Operation ........................................................ 136
Interrupt ................................................................... 136
Operation During SLEEP Mode ............................... 136
Prescaler .................................................................. 136
Real-Time Clock ...................................................... 136
Interrupts ......................................................... 136
RTC Oscillator Operation ................................. 136
Register Map ........................................................... 137
16-bit Asynchronous Counter Mode ........................ 135
16-bit Synchronous Counter Mode .......................... 135
16-bit Timer Mode .................................................... 135
Timer2 and Timer 3 Selection Mode ................................ 156
Timer2/ ......................................................139, 140, 141, 142
Timer4/ ......................................................145, 146, 147, 148
Timer4/5 Module .............................................................. 145
Timing Diagrams
S
Sales and Support ............................................................347
SCI. See UART
Serial Communication Interface. See UART
Serial Peripheral Interface. See SPI
SIB
Register Map ............................................................309
Simple Capture Event Mode ............................................151
Capture Buffer Operation .........................................151
Capture Prescaler ....................................................151
Hall Sensor Mode .....................................................152
Input Capture in CPU IDLE Mode ............................152
Input Capture in CPU SLEEP Mode ........................152
Input Capture Interrupts ...........................................152
Input Capture Operation During SLEEP Mode ........152
Register Map ............................................................153
Timer2 and Timer3 Selection Mode .........................152
Simple Output Compare Match Mode ..............................156
Simple PWM Mode ..........................................................158
Input Pin Fault Protection .........................................158
Period .......................................................................159
Single Pulse PWM Operation ...........................................182
Software Stack Pointer, Frame Pointer ..............................21
CALL Stack Frame .....................................................21
SPI ...................................................................................197
SPI Mode
Slave Select Synchronization ...................................203
SPI Master, Frame Master .......................................197
SPI Master, Frame Slave .........................................198
SPI Slave, Frame Master .........................................198
SPI Slave, Frame Slave ...........................................198
SPI1 Register Map ...................................................204
SPI2 Register Map ...................................................204
SPI Module .......................................................................197
Framed SPI Support ................................................197
Operating Function Description ................................197
SDOx Disable ...........................................................197
Word and Byte Communication ...............................197
SPI Operation During CPU IDLE Mode ...........................203
SPI Operation During CPU SLEEP Mode ........................203
SSP
Basic Core ................................................................. 26
Center Aligned PWM ............................................... 177
Clock/Instruction Cycle .............................................. 27
Dead-Time ............................................................... 180
Edge Aligned PWM .................................................. 177
Frame Sync, AC-Link Start of Frame ....................... 250
Frame Sync, Multi-Channel Mode ........................... 250
2
I C Master Mode (Reception, 7-bit Address) ........... 225
2
I C Master Mode (Transmission, 7- or
10-bit Address) ................................................ 223
I C Slave Mode with STREN = 0 (Reception,
2
10-bit Address) ................................................ 217
I C Slave Mode with STREN = 0 (Reception,
2
7-bit Address) .................................................. 214
I C Slave Mode with STREN = 1 (Reception,
2
10-bit Address) ................................................ 220
I C Slave Mode with STREN = 1 (Reception,
2
7-bit Address) .................................................. 219
I C Slave Mode (Transmission, 10-bit Address) ...... 216
I C Slave Mode (Transmission, 7-bit Address) ........ 212
I S ............................................................................ 257
2
2
2
2
I S Interface Frame Sync ........................................ 250
SSPCON .......................................................... 205, 206
STATUS Bits, Their Significance and the Initialization
Condition for RCON Register ...................................303
STATUS Register ...............................................................22
Sticky Z (SZ) Status Bit ..............................................22
Subtractor ...........................................................................64
Conventional and Convergent Rounding
PWM Output ............................................................ 159
Signal Relationship Through Filter,
1/1 Clock Divide ............................................... 165
Single Pulse PWM Operation .................................. 182
Slave Synchronization (Mode 16 = 0) ...................... 203
SPI Master, Frame Master ....................................... 198
SPI Master, Frame Slave ......................................... 198
SPI Mode Timing (8-bit Master Mode) ..................... 200
SPI Mode Timing (8-bit Slave Mode w/CKE = 0) ..... 201
SPI Mode Timing (8-bit Slave Mode w/CKE = 1) ..... 202
Time-out Sequence on Power-up (MCLR
Modes Diagram ..................................................66
Data Space Write Saturation ......................................66
Overflow and Saturation .............................................64
Round Logic ...............................................................65
Write Back ..................................................................65
Not Tied to Vdd), Case 1 ................................. 301
DS70032B-page 342
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2002 Microchip Technology Inc.
dsPIC30F
Time-out Sequence on Power-up (MCLR
Not Tied to Vdd), Case 2 ................................. 301
Time-out Sequence on Power-up (MCLR
UART Module
UART1 Register Map ............................................... 239
UART2 Register Map ............................................... 239
UART Module Overview .................................................. 233
UART Operation
Tied to Vdd) ..................................................... 301
Trap..................................................................................... 86
IDLE Mode ............................................................... 238
SLEEP Mode ........................................................... 238
UART Operation During CPU SLEEP and
U
UART
Address Detect Mode .............................................. 237
Auto Baud Support ................................................... 237
Baud Rate Generator ............................................... 237
Framing Error (FERR) .............................................. 237
Loopback Mode ....................................................... 237
Parity Error (PERR) ................................................. 237
Receive Break .......................................................... 237
Receive Buffer Overrun Error (OERR Bit) ................ 236
Receive Buffer (UxRCB) .......................................... 236
Receive Interrupt ...................................................... 236
Receiving Data ......................................................... 236
Receiving in 8-bit or 9-bit Data Mode ....................... 236
Reception Error Handling ......................................... 236
Transmit Buffer (UxTXB) .......................................... 235
Transmit Interrupt ..................................................... 236
Transmitting Data ..................................................... 235
Transmitting in 8-bit Data Mode ............................... 235
Transmitting in 9-bit Data Mode ............................... 235
IDLE Modes ............................................................. 238
Universal Asynchronous Receiver Transmitter. See UART
16-bit Up/Down Position Counter Mode .......................... 164
UxTXREG
UARTx Transmit) Register ....................................... 243
W
Wake-up from SLEEP ...................................................... 293
Wake-up from SLEEP and IDLE ........................................ 87
Watchdog Timer (WDT) ............................................293, 305
Enabling and Disabling ............................................ 305
Operation ................................................................. 305
WWW, On-Line Support .................................................... 13
2002 Microchip Technology Inc.
Advance Information
DS70032B-page 343
DSPIC30F
NOTES:
DS70032B-page 344
Advance Information
2002 Microchip Technology Inc.
dsPIC30F
Systems Information and Upgrade Hot Line
ON-LINE SUPPORT
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip’s development systems software products.
Plus, this line provides information on how customers
can receive any currently available upgrade kits.The
Hot Line Numbers are:
Microchip provides on-line support on the Microchip
World Wide Web (WWW) site.
The web site is used by Microchip as a means to make
files and information easily available to customers. To
view the site, the user must have access to the Internet
and a web browser, such as Netscape or Microsoft
Explorer. Files are also available for FTP download
from our FTP site.
1-800-755-2345 for U.S. and most of Canada, and
1-480-792-7302 for the rest of the world.
013001
ConnectingtotheMicrochipInternetWebSite
The Microchip web site is available by using your
favorite Internet browser to attach to:
www.microchip.com
The file transfer site is available by using an FTP ser-
vice to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User’s Guides, Articles and Sample Programs. A vari-
ety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
• Conferences for products, Development Sys-
tems, technical information and more
• Listing of seminars and events
2002 Microchip Technology Inc.
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DS70032B-page345
dsPIC30F
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
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Literature Number:
DS70032B
Device:
dsPIC30F
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
DS70032B-page346
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2002 Microchip Technology Inc.
dsPIC30F
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
dsPIC30LF1001ATP-I/PT-000
Custom ID
Trademark
Package
PT = TQFP 10x10
PT = TQFP 12x12
PF = TQFP 14x14
SO = SOIC
Family
L = Low Voltage
SP = SDIP
Memory
Type
P
= DIP
S
W
= Die (Waffle Pack)
= Die (Wafers)
FLASH = F
Memory Size in Bytes
0 = ROMless
1 = 1K to 6K
2 = 7K to 12K
Temperature
I = Industrial -40°C to +85°C
E = Extended High Temp -40°C to +125°C
3 = 13K to 24K
4 = 25K to 48K
5 = 49K to 96K
6 = 97K to 192K
7 = 193K to 384K
8 = 385K to 768K
9 = 769K and Up
P = Pilot
T = Tape and Reel
A,B,C… = Revision
Device ID
Examples:
a) dsPIC30F2011ATP-E/SO = Extended temp., SOIC package, Rev. A.
b) dsPIC30F6014ATP-I/PT = Industrial temp., TQFP package, Rev. A.
c) dsPIC30F3011ATP-I/P = Industrial temp., PDIP package, Rev. A.
* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of
each oscillator type.
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
2002 Microchip Technology Inc.
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DS70032B-page 347
M
WORLDWIDE SALES AND SERVICE
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AMERICAS
ASIA/PACIFIC
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01/18/02
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2002 Microchip Technology Inc.
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