DSC2033CI2-200.0000 [MICROCHIP]
DSC2033CI2-200.0000;
| 型号： | DSC2033CI2-200.0000 |
| 厂家： | 
MICROCHIP |
| 描述： | DSC2033CI2-200.0000 |
| 文件： | 总5页 (文件大小：458K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DSC2033
Low-Jitter Configurable Dual LVDS Oscillator
General Description
Features
The DSC2033 series of high performance
dual output LVDS oscillators utilizes a proven
silicon MEMS technology to provide excellent
jitter and stability while incorporating
Low RMS Phase Jitter: <1 ps (typ)
High Stability: ±10, ±25, ±50 ppm
Wide Temperature Range
o Industrial: -40° to 85° C
additional device functionality.
The two
outputs are controlled by separate supply
voltages to allow for high output isolation.
The frequencies of the outputs can be
identical or independently derived from a
o Ext. commercial: -20° to 70° C
High Supply Noise Rejection: -50 dBc
Two Independent LVDS Outputs
common PLL frequency source.
DSC2033 has provision for up to eight user-
defined pre-programmed, pin-selectable
output frequency combinations.
The
Pin-Selectable Configurations
o 3-bit Output Frequency Combinations
Short Lead Times: 2 Weeks
Wide Frequency Range: 10 to 425 MHz
Miniature Footprint of 3.2x2.5mm2
DSC2033 is packaged in a 14-pin 3.2x2.5
mm QFN package and available in
temperature grades from Ext. Commercial to
Industrial.
Excellent Shock & Vibration Immunity
o Qualified to MIL-STD-883
High Reliability
o 20x better MTF than quartz oscillators
Supply Range of 2.25 to 3.6 V
Lead Free & RoHS Compliant
Block Diagram
Applications
Storage Area Networks
o SATA, SAS, Fibre Channel
Passive Optical Networks
o EPON, 10G-EPON, GPON, 10G-PON
Ethernet
o 1G, 10GBASE-T/KR/LR/SR, and FCoE
HD/SD/SDI Video & Surveillance
PCI Express
All Rights Reserved. No part of this document may be copied or reproduced in any form without the prior written permission of Discera, Inc. Discera Inc. may update or make
changes to the contents, products, programs or services described at any time without notice. This document neither states nor implies any kind of warranty, including, but not
limited to implied warranties of merchantability or fitness for a particular use.
Page 1
Low-Jitter Pin-Configurable Dual LVDS Oscillator
DSC2033
Pin Description
Pin
Type
I
NA
NA
Pin No.
Pin Name
Enable
NC
Description
Enables outputs when high and disables (tri-state) them when low
Leave unconnected or grounded
1
2
3
NC
Leave unconnected or grounded
4
GND
Power Ground
5
FS0
I
Least significant bit for frequency selection
6
7
8
9
10
11
12
13
14
FS1
FS2
I
I
O
O
O
O
Middle bit for frequency selection
Most significant bit for frequency selection
Positive LVDS Output 1
Negative LVDS Output 1
Negative LVDS Output 2
Output1+
Output1-
Output 2-
Output 2+
VDD2
VDD
Positive LVDS Output 2
Power Power Supply 2 for LVDS Output 2
Power Power Supply
NA
NC
Leave unconnected or grounded
General Description
The DSC2033 is a dual output LVDS oscillator
consisting of a MEMS resonator and a support
coefficients required by the PLL for up to eight
different frequency combinations. Three
control pins (FS0 – FS2) select the output
frequency combination. Discera supports
customer defined versions of the DSC2033.
Standard frequency options are described in in
the following sections.
PLL IC.
The two outputs are generated
through independent 8-bit programmable
dividers from the output of the internal PLL.
Two constraints are imposed on the output
frequencies: 1) f2=M x f1/N, where M and N
are even integers between 4 and 254, 2)
1.2GHz < N x f2 < 1.7GHz.
When Enable (pin 1) is floated or connected to
VDD, the DSC2033 is in operational mode.
Driving Enable to ground will tri-state both
output drivers (hi-impedance mode).
The actual frequencies output by the DSC2033
are controlled by an internal pre-programmed
memory (OTP).
This memory stores all
Output Frequency Combinations
Table 1 lists the standard frequency configurations and the associated ordering information to be
used in conjunction with the ordering code above. Customer defined combinations are available.
Table 1. Pre-programmed pin-selectable output frequency combinations
Freq Select Bits [FS2, FS1, FS0] – Default is [111]
Ordering
Info
Freq
(MHz)
000
74.25
33
001
156.25
125
010
150
125
011
125
25
100
125
50
101
100
50
110
100
75
111
400
200
fOUT1
fOUT2
fOUT1
fOUT2
A0001
A0002
Contact factory for additional configurations.
Frequency select bit are weakly tied high so if left unconnected the default setting will be [1] and
the device will output the associated frequency highlighted in Bold.
All Rights Reserved. No part of this document may be copied or reproduced in any form without the prior written permission of Discera, Inc. Discera Inc. may update or make
changes to the contents, products, programs or services described at any time without notice. This document neither states nor implies any kind of warranty, including, but not
limited to implied warranties of merchantability or fitness for a particular use.
Page 2
Low-Jitter Pin-Configurable Dual LVDS Oscillator
DSC2033
Absolute Maximum Ratings
Ordering Code
Item
Min
Max
Unit Conditio
Temp Range
E: -20 to 70
I: -40 to 85
Packing
T: Tape & Reel
: Tube
n
Supply Voltage
-0.3
+4.0
V
Input Voltage
Junction Temp
Storage Temp
Soldering Temp
-0.3
VDD+0.3
+150
+150
V
°C
°C
°C
V
-
-55
-
DSC2033 C I 2
xxxxx
T
+260
40sec max.
Package
C: 3.2x2.5mm
Stability
1: ±50ppm
2: ±25ppm
4: ±10ppm
Freq (MHz)
See Freq. table
ESD
HBM
MM
-
4000
400
CDM
1500
Note: 1000+ years of data retention on internal memory
Specifications (Unless specified otherwise: T=25° C)
Parameter
Supply Voltage1
Condition
Min.
Typ.
Max.
3.6
Unit
VDD
IDD
2.25
V
Supply Current
Supply Current2
EN pin low – outputs are disabled
21
38
26
mA
EN pin high – outputs are enabled
LVDS: RL=100Ω, F0=156.25 MHz
Includes frequency variations due
to initial tolerance, temp. and
power supply voltage
IDD
mA
±10
±25
±50
±5
10
Frequency Stability
Aging
Startup Time3
Δf
ppm
Δf
tSU
1 year @25°C
T=25°C
ppm
ms
Input Logic Levels
Input logic high
Input logic low
VIH
VIL
0.75xVDD
-
-
V
0.25xVDD
Output Disable Time4
Output Enable Time
Pull-Up Resistor2
tDA
100
5
ns
us
tEN
Pull-up exists on all digital IO
LVDS Outputs
33
kΩ
Output Offset Voltage
Delta Offset Voltage
Pk to Pk Output Swing
Output Transition time4
Rise Time
R=100Ω Differential
1.125
1.4
50
V
mV
mV
Single-Ended
350
300
20% to 80%
RL=50Ω, CL= 2pF
tR
tF
ps
Fall Time
Frequency
f0
Single Frequency
Differential
10
48
425
52
MHz
%
Output Duty Cycle
SYM
F01 = 156.25 MHz
F02 = 156.25 MHz
Period Jitter5
JPER
3.3
psRMS
200kHz to 20MHz @156.25MHz
100kHz to 20MHz @156.25MHz
12kHz to 20MHz @156.25MHz
0.43
0.55
1.8
Integrated Phase Noise
Spurious Frequencies6
JCC
psRMS
dBc
3
-50
Notes:
1.
Pin 4 VDD should be filtered with 0.01uf capacitor.
2.
3.
4.
5.
6.
Output is enabled if Enable pad is floated or not connected.
tsu is time to stable output frequency after VDD is applied and outputs are enabled.
Output Waveform and Test Circuit figures below define the parameters.
Period Jitter includes crosstalk from adjacent output.
Spurious frequencies include crosstalk from adjacent output within 20 MHz of the output clock frequency.
All Rights Reserved. No part of this document may be copied or reproduced in any form without the prior written permission of Discera, Inc. Discera Inc. may update or make
changes to the contents, products, programs or services described at any time without notice. This document neither states nor implies any kind of warranty, including, but not
limited to implied warranties of merchantability or fitness for a particular use.
Page 3
Low-Jitter Pin-Configurable Dual LVDS Oscillator
DSC2033
Nominal Performance Parameters (Unless specified otherwise: T=25° C, VDD=3.3 V)
2.5
156MHz-LVDS
212MHz-LVDS
320MHz-LVDS
410MHz-LVDS
2.0
1.5
1.0
0.5
0.0
0
200
400
600
800
1000
Low-end of integration BW: x kHz to 20 MHz
LVDS Phase jitter (integrated phase noise)
LVDS Output Waveform
tR
tF
Output
80%
350 mV
50%
20%
Output
tEN
1/fo
tDA
VIH
Enable
VIL
Solder Reflow Profile
20-40
Sec
260°C
MSL 1 @ 260°C refer to JSTD-020C
Ramp-Up Rate (200°C to Peak Temp) 3°C/Sec Max.
217°C
200°C
60-150
Sec
Preheat Time 150°C to 200°C
Time maintained above 217°C
Peak Temperature
Time within 5°C of actual Peak
Ramp-Down Rate
60-180 Sec
60-150 Sec
255-260°C
20-40 Sec
6°C/Sec Max.
8 min Max.
Reflow
60-180
Sec
150°C
Cool
Pre heat
25°C
Time 25°C to Peak Temperature
Time
8 min max
All Rights Reserved. No part of this document may be copied or reproduced in any form without the prior written permission of Discera, Inc. Discera Inc. may update or make
changes to the contents, products, programs or services described at any time without notice. This document neither states nor implies any kind of warranty, including, but not
limited to implied warranties of merchantability or fitness for a particular use.
Page 4
Low-Jitter Pin-Configurable Dual LVDS Oscillator
DSC2033
Package Dimensions
3.2 x 2.5 mm Plastic Package
Recommended
Solder Pad Layout
units: mm[inch]
2.60
1.90
0.50
0.25
0.50
DISCERA, Inc.
Phone: +1 (408) 432-8600
●
1961 Concourse Drive,
San Jose, California
95131
●
●
USA
www.discera.com
●
Fax: +1 (408) 432-8609
●
Email: sales@discera.com
All Rights Reserved. No part of this document may be copied or reproduced in any form without the prior written permission of Discera, Inc. Discera Inc. may update or make
changes to the contents, products, programs or services described at any time without notice. This document neither states nor implies any kind of warranty, including, but not
limited to implied warranties of merchantability or fitness for a particular use.
Page 5
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