DN1509N8-G [MICROCHIP]

N-Channel, Depletion-Mode, Vertical DMOS FET;
DN1509N8-G
型号: DN1509N8-G
厂家: MICROCHIP    MICROCHIP
描述:

N-Channel, Depletion-Mode, Vertical DMOS FET

文件: 总12页 (文件大小:394K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
DN1509  
N-Channel, Depletion-Mode, Vertical DMOS FET  
Features  
Description  
• High-input impedance  
This low threshold, depletion-mode, normally-on, tran-  
sistor utilizes an advanced vertical Diffusion Metal  
Oxide Semiconductor (DMOS) structure and a well  
proven silicon-gate manufacturing process. This com-  
bination produces a device with the power-handling  
capabilities of bipolar transistors, plus the high-input  
impedance and positive-temperature coefficient inher-  
ent in Metal-Oxide Semiconductor (MOS) devices.  
Characteristic of all MOS structures, this device is free  
from thermal runaway and thermally-induced second-  
ary breakdown.  
• Low-input capacitance  
• Fast switching speeds  
• Low on-resistance  
• Free from secondary breakdown  
• Low input and output leakages  
Applications  
• Normally-on switches  
• Battery operated systems  
• Converters  
Vertical DMOS Field-Effect Transistors (FETs) are ide-  
ally suited to a wide range of switching and amplifying  
applications where a very low threshold voltage, high  
breakdown voltage, high input impedance, low input  
capacitance, and fast switching speeds are desired.  
• Linear amplifiers  
• Constant current sources  
Telecom  
2015 Microchip Technology Inc.  
DS20005403B-page 1  
DN1509  
Package Type  
SOURCE  
DRAIN  
GATE  
SOURCE  
DRAIN  
GATE  
N/C  
DRAIN  
N/C  
5-lead SOT-23  
TO-243AA (SOT-89)  
See Table 2-1 for pin information  
DS20005403B-page 2  
2015 Microchip Technology Inc.  
DN1509  
1.0  
ELECTRICAL CHARACTERISTICS  
ABSOLUTE MAXIMUM RATINGS†  
Drain-to-source voltage................................................................................................................................................................ BVDSX  
Drain-to-gate voltage....................................................................................................................................................................BVDGX  
Gate-to-source voltage................................................................................................................................................................... ±20V  
Operating and storage temperature............................................................................................................................. -55°C to +150°C  
† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is  
a stress rating only and functional operation of the device at those or any other conditions above those indicated in the  
operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods  
may affect device reliability.  
1.1  
Electrical Specifications  
TABLE 1-1:  
DC AND AC CHARACTERISTICS  
Electrical Specifications: Unless otherwise specified, for all specifications TA =TJ = +25°C  
Symbol  
Parameter  
Min  
Typ  
Max Units Conditions  
DC Parameters (Note 1, unless otherwise stated)  
BVDSX  
Drain-to-source breakdown voltage  
Gate-to-source off voltage  
90  
-1.8  
V
V
VGS = -5V, ID = 1.0µA  
ID = 10µA  
VGS(OFF)  
-3.5  
VGS(OFF) VGS(OFF) change with temperature  
-4.5 mV/°C VDS = 15V, ID= 10µA (Note 2)  
IGSS  
Gate body leakage  
100  
1.0  
nA  
µA  
VGS = ±20V, VDS = 0V  
DS = BVDSX, VGS = -5.0V  
VDS = 0.8 BVDSX  
VGS = -5.0V, TA= 125°C (Note 2)  
V
ID(OFF)  
Drain-to-source leakage current  
Saturated drain-to-source current  
,
300  
540  
3.2  
1.0  
mA  
IDSS  
mA VGS = 0V, VDS = 25V  
Static drain-to-source on-state  
resistance  
RDS(ON)  
RDS(ON)  
6.0  
1.1  
VGS = 0V, ID= 200mA  
Change in RDS(ON) with temperature  
%/°C VGS = 0V, ID= 200mA (Note 2)  
AC Parameters (Note 2)  
GFS  
CISS  
COSS  
CRSS  
td(ON)  
tr  
Forward transconductance  
200  
150  
40  
15  
30  
45  
45  
60  
mmho VDS = 10V, ID= 200mA  
Input capacitance  
70  
20  
6.0  
12  
16  
15  
25  
VGS = -10V, VDS = 25V,  
f = 1MHz  
Common source output capacitance  
Reverse transfer capacitance  
Turn-on delay time  
Rise time  
pF  
V
DD = 25V,  
ID = 100mA,  
GEN = 25ꢀ  
ns  
td(OFF)  
tf  
Turn-off delay time  
Fall time  
R
Diode Parameters  
VSD Diode forward voltage drop  
trr Reverse recovery time  
V
GS = -5.0V, ISD= 500mA  
1.8  
V
(Note 1)  
VGS = -5.0V, ISD= 500mA  
(Note 2)  
400  
ns  
Note 1: All DC parameters are 100% tested at 25°C unless otherwise stated. Pulse test: 300 µs pulse, 2% duty cycle.  
2: Specification is obtained by characterization and is not 100% tested.  
2015 Microchip Technology Inc.  
DS20005403B-page 3  
DN1509  
TABLE 1-2:  
TYPICAL THERMAL RESISTANCE  
Package  
θja  
5-lead SOT-23  
253°C/W  
78°C/W1  
TO-243AA (SOT-89)  
1. Mounted on FR4 board, 25mm x 25mm x 1.57 mm  
TABLE 1-3:  
THERMAL CHARACTERISTICS  
1
ID  
ID  
pulsed  
(mA)  
Power  
Dissipation  
@TA = 2.5°C (W)  
1
IDR  
IDRM  
(mA)  
Package  
continuous  
(mA)  
(mA)  
5-lead SOT-23  
200  
360  
500  
500  
0.49  
1.62  
200  
360  
500  
500  
TO-243AA (SOT-89)  
1. ID continuous is limited by max rated TJ  
2. Mounted on FR4 board, 25mm x 25mm x 1.57 mm  
2.0  
PIN DESCRIPTION  
The locations of the pins are listed in Package Type.  
TABLE 2-1:  
PIN DESCRIPTION  
Pin # SOT-23  
Pin # TO-243AA  
Function  
5
2
1
2
3
GATE  
DRAIN  
SOURCE  
NC  
4
1,3  
DS20005403B-page 4  
2015 Microchip Technology Inc.  
DN1509  
3.0  
APPLICATION INFORMATION  
Figure 3-1 shows the switching waveform and test cir-  
cuit for DN1509.  
0V  
VDD  
90%  
INPUT  
Pulse  
RL  
10%  
Generator  
-10V  
OUTPUT  
t(ON)  
td(ON)  
t(OFF)  
td(OFF)  
RGEN  
tf  
tr  
VDD  
OUTPUT  
0V  
INPUT  
D.U.T.  
10%  
10%  
90%  
90%  
FIGURE 3-1:  
Switching Waveforms and Test Circuit  
Product Summary  
BVDSX/BVDGX  
(V)  
RDS(ON)  
(max) ()  
IDSS  
(min) (mA)  
90  
6.0  
300  
2015 Microchip Technology Inc.  
DS20005403B-page 5  
DN1509  
4.0  
4.1  
PACKAGING INFORMATION  
Package Marking Information  
Example  
Example  
3-lead TO-243AA *  
(SOT-89)  
5-lead SOT-23 *  
XXXYYWW  
DN5A517  
XXXXY  
WWNNN  
N5A5  
17343  
NNN  
343  
Legend: XX...X Product Code or Customer-specific information  
Y
Year code (last digit of calendar year)  
YY  
WW  
NNN  
Year code (last 2 digits of calendar year)  
Week code (week of January 1 is week ‘01’)  
Alphanumeric traceability code  
Pb-free JEDEC® designator for Matte Tin (Sn)  
This package is Pb-free. The Pb-free JEDEC designator (  
can be found on the outer packaging for this package.  
e
3
*
)
e
3
Note: In the event the full Microchip part number cannot be marked on one line, it will  
be carried over to the next line, thus limiting the number of available  
characters for product code or customer-specific information. Package may or  
not include the corporate logo.  
DS20005403B-page 6  
2015 Microchip Technology Inc.  
DN1509  
3-Lead TO-243AA (SOT-89) Package Outline (N8)  
D
D1  
C
H
E
E1  
1
2
3
L
b
b1  
A
e
e1  
Top View  
Side View  
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.  
Symbol  
A
1.40  
-
b
0.44  
-
b1  
0.36  
-
C
0.35  
-
D
4.40  
-
D1  
1.62  
-
E
2.29  
-
E1  
2.00†  
-
e
e1  
H
3.94  
-
L
0.73†  
-
MIN  
NOM  
MAX  
Dimensions  
(mm)  
1.50  
BSC  
3.00  
BSC  
1.60  
0.56  
0.48  
0.44  
4.60  
1.83  
2.60  
2.29  
4.25  
1.20  
JEDEC Registration TO-243, Variation AA, Issue C, July 1986.  
This dimension differs from the JEDEC drawing  
Drawings not to scale.  
2015 Microchip Technology Inc.  
DS20005403B-page 7  
DN1509  
5-Lead SOT-23 Package Outline (K1)  
2.90x1.60mm body, 1.45mm height (max), 0.95mm pitch  
D
θ1  
e1  
5
E1  
E
Gauge  
Plane  
Note 1  
(Index Area  
D/2 x E1/2)  
L2  
θ
1
L
e
Seating  
Plane  
b
L1  
Top View  
View B  
View B  
A
A
A2  
A1  
Seating  
Plane  
A
View A - A  
Side View  
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.  
Note:  
1. $ꢁ3LQꢁꢃꢁLGHQWL¿HUꢁPXVWꢁEHꢁORFDWHGꢁLQꢁWKHꢁLQGH[ꢁDUHDꢁLQGLFDWHGꢂꢁ7KHꢁ3LQꢁꢃꢁLGHQWL¿HUꢁFDQꢁEHꢄꢁDꢁPROGHGꢁPDUNꢅLGHQWL¿HUꢆꢁDQꢁHPEHGGHGꢁPHWDOꢁPDUNHUꢆꢁRUꢁ  
a printed indicator.  
Symbol  
A
A1  
MIN 0.90* 0.00 0.90 0.30 2.75* 2.60* 1.45*  
NOM 1.15 2.90 2.80 1.60  
MAX 1.45 0.15 1.30 0.50 3.05* 3.00* 1.75*  
A2  
b
D
E
E1  
e
e1  
L
L1  
L2  
ș
șꢀ  
5O  
10O  
15O  
0.30  
0.45  
0.60  
0O  
4O  
8O  
Dimension  
(mm)  
0.95 1.90  
BSC BSC  
0.60 0.25  
REF BSC  
-
-
-
JEDEC Registration MO-178, Variation AA, Issue C, Feb. 2000.  
ꢀꢁ7KLVꢁGLPHQVLRQꢁLVꢁQRWꢁVSHFL¿HGꢁLQꢁWKHꢁ-('(&ꢁGUDZLQJꢂ  
Drawings not to scale.  
DS20005403B-page 8  
2015 Microchip Technology Inc.  
DN1509  
APPENDIX A: REVISION HISTORY  
Revision A (June 2015)  
• Update file to new format  
Revision B (August 2015)  
• Minor fix to Table 1-1  
2015 Microchip Technology Inc.  
DS20005403B-page 9  
DN1509  
PRODUCT IDENTIFICATION SYSTEM  
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.  
-
-
PART NO.  
Device  
XX  
X
X
Examples:  
a)  
DN1509K1-G  
SOT-23 package,  
3000/reel  
TO-243AA package,  
2000/reel  
Package Environmental Media  
Options Type  
b)  
DN1509N8-G  
Device:  
DN1509 = N-Channel, Depletion-Mode,  
vertical DMOS FET  
Package:  
K1  
N8  
= SOT-23, 5-lead  
= TO-243AA (SOT-89), 3-lead  
Environmental  
Media Type:  
G
= Lead (Pb)-free/ROHS-compliant package  
(blank) = 3000/Reel for K1 packages  
= 2000/Reel for N8 packages  
DS20005403B-page 10  
2015 Microchip Technology Inc.  
DN1509  
Note the following details of the code protection feature on Microchip devices:  
Microchip products meet the specification contained in their particular Microchip Data Sheet.  
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the  
intended manner and under normal conditions.  
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our  
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data  
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.  
Microchip is willing to work with the customer who is concerned about the integrity of their code.  
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not  
mean that we are guaranteeing the product as “unbreakable.”  
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our  
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts  
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.  
Information contained in this publication regarding device  
applications and the like is provided only for your convenience  
and may be superseded by updates. It is your responsibility to  
ensure that your application meets with your specifications.  
MICROCHIP MAKES NO REPRESENTATIONS OR  
WARRANTIES OF ANY KIND WHETHER EXPRESS OR  
IMPLIED, WRITTEN OR ORAL, STATUTORY OR  
OTHERWISE, RELATED TO THE INFORMATION,  
INCLUDING BUT NOT LIMITED TO ITS CONDITION,  
QUALITY, PERFORMANCE, MERCHANTABILITY OR  
FITNESS FOR PURPOSE. Microchip disclaims all liability  
arising from this information and its use. Use of Microchip  
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suits, or expenses resulting from such use. No licenses are  
conveyed, implicitly or otherwise, under any Microchip  
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Trademarks  
The Microchip name and logo, the Microchip logo, dsPIC,  
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,  
LANCheck, MediaLB, MOST, MOST logo, MPLAB,  
OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC,  
SST, SST Logo, SuperFlash and UNI/O are registered  
trademarks of Microchip Technology Incorporated in the  
U.S.A. and other countries.  
The Embedded Control Solutions Company and mTouch are  
registered trademarks of Microchip Technology Incorporated  
in the U.S.A.  
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,  
CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit  
Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,  
KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo,  
MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code  
Generation, PICDEM, PICDEM.net, PICkit, PICtail,  
RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total  
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,  
WiperLock, Wireless DNA, and ZENA are trademarks of  
Microchip Technology Incorporated in the U.S.A. and other  
countries.  
SQTP is a service mark of Microchip Technology Incorporated  
in the U.S.A.  
Silicon Storage Technology is a registered trademark of  
Microchip Technology Inc. in other countries.  
GestIC is a registered trademarks of Microchip Technology  
Germany II GmbH & Co. KG, a subsidiary of Microchip  
Technology Inc., in other countries.  
All other trademarks mentioned herein are property of their  
respective companies.  
© 2015, Microchip Technology Incorporated, Printed in the  
U.S.A., All Rights Reserved.  
ISBN: 978-1-63277-700-3  
QUALITYMANAGEMENTꢀꢀSYSTEMꢀ  
CERTIFIEDBYDNVꢀ  
Microchip received ISO/TS-16949:2009 certification for its worldwide  
headquarters, design and wafer fabrication facilities in Chandler and  
Tempe, Arizona; Gresham, Oregon and design centers in California  
and India. The Company’s quality system processes and procedures  
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping  
devices, Serial EEPROMs, microperipherals, nonvolatile memory and  
analog products. In addition, Microchip’s quality system for the design  
and manufacture of development systems is ISO 9001:2000 certified.  
== ISO/TS16949==ꢀ  
2015 Microchip Technology Inc.  
DS20005403B-page 11  
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07/14/15  
DS20005403B-page 12  
2015 Microchip Technology Inc.  

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