ATTINY40-XUR [MICROCHIP]
IC MCU 8BIT 4KB FLASH 20TSSOP;
| 型号： | ATTINY40-XUR |
| 厂家： | 
MICROCHIP |
| 描述： | IC MCU 8BIT 4KB FLASH 20TSSOP 时钟 微控制器 光电二极管 外围集成电路 闪存 |
| 文件： | 总12页 (文件大小：375K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8-bit Atmel tinyAVR Microcontroller with
4K Bytes In-System Programmable Flash
ATtiny40
SUMMARY DATASHEET
Features
• High Performance, Low Power AVR® 8-Bit Microcontroller
• Advanced RISC Architecture
– 54 Powerful Instructions – Most Single Clock Cycle Execution
– 16 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 12 MIPS Throughput at 12 MHz
• Non-volatile Program and Data Memories
– 4K Bytes of In-System Programmable Flash Program Memory
– 256 Bytes Internal SRAM
– Flash Write/Erase Cycles: 10,000
– Data Retention: 20 Years at 85oC / 100 Years at 25oC
• Peripheral Features
– One 8-bit Timer/Counter with Two PWM Channels
– One 8/16-bit Timer/Counter
– 10-bit Analog to Digital Converter
• 12 Single-Ended Channels
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Master/Slave SPI Serial Interface
– Slave TWI Serial Interface
• Special Microcontroller Features
– In-System Programmable
– External and Internal Interrupt Sources
– Low Power Idle, ADC Noise Reduction, Stand-by and Power-down Modes
– Enhanced Power-on Reset Circuit
– Internal Calibrated Oscillator
• I/O and Packages
– 20-pin SOIC: 18 Programmable I/O Lines
– 20-pin TSSOP: 18 Programmable I/O Lines
– 20-pad VQFN: 18 Programmable I/O Lines
• Operating Voltage:
– 1.8 – 5.5V
• Programming Voltage:
– 5V
• Speed Grade
– 0 – 4 MHz @ 1.8 – 5.5V
– 0 – 8 MHz @ 2.7 – 5.5V
– 0 – 12 MHz @ 4.5 – 5.5V
• Industrial Temperature Range
• Low Power Consumption
– Active Mode:
• 200 µA at 1 MHz and 1.8V
– Idle Mode:
• 25 µA at 1 MHz and 1.8V
– Power-down Mode:
• < 0.1 µA at 1.8V
8263BS–AVR–01/2013
1. Pin Configurations
Figure 1-1. Pinout of ATtiny40
SOIC/TSSOP
PB1 (ADC9/PCINT9)
PB2 (ADC10/PCINT10)
PB3 (ADC11/PCINT11)
(PCINT8/ADC8) PB0
1
2
3
4
5
6
7
8
9
10
20
19
18
(PCINT7/ADC7) PA7
(PCINT6/ADC6) PA6
(PCINT5/ADC5/OC0B) PA5
(PCINT4/ADC4/T0) PA4
(PCINT3/ADC3) PA3
(PCINT2/ADC2/AIN1) PA2
(PCINT1/ADC1/AIN0) PA1
(PCINT0/ADC0) PA0
GND
17 PC0 (OC0A/SS/PCINT12)
16
15
14
13
12
11
PC1 (SCK/SCL/ICP1/T1/PCINT13)
PC2 (INT0/CLKO/MISO/PCINT14)
PC3 (RESET/PCINT15)
PC4 (MOSI/SDA/TPIDATA/PCINT16)
PC5 (CLKI/TPICLK/PCINT17)
VCC
VQFN
(PCINT6/ADC6) PA6
(PCINT5/ADC5/OC0B) PA5
(PCINT4/ADC4/T0) PA4
(PCINT3/ADC3) PA3
1
2
3
4
5
15
14
13
12
11
PC0 (OC0A/SS/PCINT12)
PC1 (SCK/SCL/ICP1/T1/PCINT13)
PC2 (INT0/CLKO/MISO/PCINT14)
PC3 (RESET/PCINT15)
(PCINT2/ADC2/AIN1) PA2
PC4 (MOSI/SDA/TPIDATA/PCINT16)
NOTE: Bottom pad should be soldered to ground.
ATtiny40 [SUMMARY DATASHEET]
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8263BS–AVR–01/2013
1.1
Pin Description
1.1.1
VCC
Supply voltage.
1.1.2
1.1.3
GND
Ground.
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock
is not running and provided the reset pin has not been disabled. The minimum pulse length is given in Table 20-4
on page 155. Shorter pulses are not guaranteed to generate a reset.
The reset pin can also be used as a (weak) I/O pin.
1.1.4
Port A (PA7:PA0)
Port A is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers
have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are
externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a
reset condition becomes active, even if the clock is not running.
Port A has alternate functions as analog inputs for the ADC, analog comparator and pin change interrupt as
described in “Alternate Port Functions” on page 47.
1.1.5
1.1.6
Port B (PB3:PB0)
Port B is a 4-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers
have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are
externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a
reset condition becomes active, even if the clock is not running.
The port also serves the functions of various special features of the ATtiny40, as listed on page 37.
Port C (PC5:PC0)
Port C is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buf-
fers have symmetrical drive characteristics with both high sink and source capability except PC3 which has the
RESET capability. To use pin PC3 as an I/O pin, instead of RESET pin, program (‘0’) RSTDISBL fuse. As inputs,
Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins
are tri-stated when a reset condition becomes active, even if the clock is not running.
Port C has alternate functions as analog inputs for the ADC, analog comparator and pin change interrupt as
described in “Alternate Port Functions” on page 47.
The port also serves the functions of various special features of the ATtiny40, as listed on page 37.
2. Overview
ATtiny40 is a low-power CMOS 8-bit microcontroller based on the compact AVR enhanced RISC architecture. By
executing powerful instructions in a single clock cycle, the ATtiny40 achieves throughputs approaching 1 MIPS per
MHz allowing the system designer to optimize power consumption versus processing speed.
Figure 2-1. Block Diagram
The AVR core combines a rich instruction set with 16 general purpose working registers and system registers. All
registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be
ATtiny40 [SUMMARY DATASHEET]
3
8263BS–AVR–01/2013
VCC
RESET
PROGRAMMING
LOGIC
PROGRAM
COUNTER
INTERNAL
OSCILLATOR
CALIBRATED
OSCILLATOR
PROGRAM
FLASH
STACK
POINTER
WATCHDOG
TIMER
TIMING AND
CONTROL
INSTRUCTION
REGISTER
RESET FLAG
REGISTER
SRAM
INSTRUCTION
DECODER
INTERRUPT
UNIT
MCU STATUS
REGISTER
CONTROL
LINES
TIMER/
COUNTER0
GENERAL
PURPOSE
REGISTERS
X
Y
Z
TIMER/
COUNTER1
ANALOG
COMPARATOR
ALU
SPI
ISP
STATUS
REGISTER
TWI
ADC
INTERFACE
8-BIT DATA BUS
DATA REGISTER
PORT A
DIRECTION
REG. PORT A
DATA REGISTER
PORT B
DIRECTION
REG. PORT B
DATA REGISTER
PORT C
DIRECTION
REG. PORT C
DRIVERS
PORT A
DRIVERS
PORT B
DRIVERS
PORT C
PA[7:0]
PB[3:0]
PC[5:0]
GND
accessed in one single instruction executed in one clock cycle. The resulting architecture is compact and code effi-
cient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The ATtiny40 provides the following features: 4K bytes of In-System Programmable Flash, 256 bytes of SRAM,
twelve general purpose I/O lines, 16 general purpose working registers, an 8-bit Timer/Counter with two PWM
channels, a 8/16-bit Timer/Counter, Internal and External Interrupts, an eight-channel, 10-bit ADC, a programma-
ble Watchdog Timer with internal oscillator, a slave two-wire interface, a master/slave serial peripheral interface,
an internal calibrated oscillator, and four software selectable power saving modes.
Idle mode stops the CPU while allowing the Timer/Counter, ADC, Analog Comparator, SPI, TWI, and interrupt sys-
tem to continue functioning. ADC Noise Reduction mode minimizes switching noise during ADC conversions by
stopping the CPU and all I/O modules except the ADC. In Power-down mode registers keep their contents and all
chip functions are disabled until the next interrupt or hardware reset. In Standby mode, the oscillator is running
while the rest of the device is sleeping, allowing very fast start-up combined with low power consumption.
ATtiny40 [SUMMARY DATASHEET]
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8263BS–AVR–01/2013
The device is manufactured using Atmel’s high density non-volatile memory technology. The on-chip, in-system
programmable Flash allows program memory to be re-programmed in-system by a conventional, non-volatile
memory programmer.
The ATtiny40 AVR is supported by a suite of program and system development tools, including macro assemblers
and evaluation kits.
3. General Information
3.1
Resources
A comprehensive set of drivers, application notes, data sheets and descriptions on development tools are available
for download at http://www.atmel.com/avr.
3.2
Code Examples
This documentation contains simple code examples that briefly show how to use various parts of the device. These
code examples assume that the part specific header file is included before compilation. Be aware that not all C
compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent.
Please confirm with the C compiler documentation for more details.
3.3
Capacitive Touch Sensing
Atmel QTouch Library provides a simple to use solution for touch sensitive interfaces on Atmel AVR microcon-
trollers. The QTouch Library includes support for QTouch® and QMatrix® acquisition methods.
Touch sensing is easily added to any application by linking the QTouch Library and using the Application Program-
ming Interface (API) of the library to define the touch channels and sensors. The application then calls the API to
retrieve channel information and determine the state of the touch sensor.
The QTouch Library is free and can be downloaded from the Atmel website. For more information and details of
implementation, refer to the QTouch Library User Guide – also available from the Atmel website.
3.4
3.5
Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20
years at 85°C or 100 years at 25°C.
Disclaimer
Typical values contained in this datasheet are based on simulations and characterization of other AVR microcon-
trollers manufactured on the same process technology.
4. CPU Core
This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure cor-
rect program execution. The CPU must therefore be able to access memories, perform calculations, control
peripherals, and handle interrupts.
ATtiny40 [SUMMARY DATASHEET]
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8263BS–AVR–01/2013
5. Register Summary
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
0x3F
0x3E
0x3D
0x3C
0x3B
0x3A
0x39
0x38
0x37
0x36
0x35
0x34
0x33
0x32
0x31
0x30
0x2F
0x2E
0x2D
0x2C
0x2B
0x2A
0x29
0x28
0x27
0x26
0x25
0x24
0x23
0x22
0x21
0x20
0x1F
0x1E
0x1D
0x1C
0x1B
0x1A
0x19
0x18
0x17
0x16
0x15
0x14
0x13
0x12
0x11
0x10
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
SREG
SPH
I
T
H
S
V
N
Z
C
Page 12
Page 12
Stack Pointer High Byte
Stack Pointer Low Byte
SPL
Page 12
CCP
CPU Change Protection Register
Page 11
RSTFLR
MCUCR
OSCCAL
Reserved
CLKMSR
CLKPSR
–
–
–
–
–
WDRF
SM2
BORF
SM1
EXTRF
SM0
PORF
SE
Page 35
ISC01
ISC00
BODS
Pages 26, 38
Page 23
Oscillator Calibration Register
–
–
–
–
–
–
–
–
–
–
–
–
–
–
CLKMS1
CLKPS1
PRTIM0
CLKMS0
CLKPS0
PRADC
Page 21
Page 22
CLKPS3
PRSPI
CLKPS2
PRTIM1
PRR
PRTWI
Page 27
QTCSR
QTouch Control and Status Register
Page 5
NVMCMD
NVMCSR
WDTCSR
SPCR
–
–
NVM Command Register
Page 151
Page 151
Page 33
NVMBSY
WDIF
SPIE
–
–
–
–
–
–
–
WDIE
SPE
WCOL
WDP3
DORD
–
–
MSTR
–
WDE
CPOL
–
WDP2
CPHA
–
WDP1
SPR1
–
WDP0
SPR0
SPI2X
Page 120
Page 121
Page 122
Page 130
Page 130
Page 131
Page 133
Page 133
Page 133
Page 89
SPSR
SPIF
SPDR
SPI Data Register
TWSCRA
TWSCRB
TWSSRA
TWSA
TWSHE
–
–
–
TWDIE
–
TWASIE
–
TWEN
–
TWSIE
TWAA
TWBE
TWPME
TWSME
TWAS
TWCMD[1.0]
TWDIF
TWASIF
TWCH
TWRA
TWC
TWDIR
TWI Slave Address Register
TWI Slave Address Mask Register
TWI Slave Data Register
TWSAM
TWSD
TCNT1H
TIMSK
Timer/Counter1 – Counter Register High Byte
ICIE1
ICF1
–
–
OCIE1B
OCF1B
ICNC1
OCIE1A
OCF1A
ICES1
TOIE1
TOV1
CTC1
OCIE0B
OCF0B
CS12
OCIE0A
OCF0A
CS11
TOIE0
TOV0
CS10
Pages 75, 90
Pages 76, 90
Page 88
TIFR
TCCR1A
TCNT1L
OCR1A
OCR1B
RAMAR
RAMDR
PUEC
TCW1
ICEN1
Timer/Counter1 – Counter Register Low Byte
Timer/Counter1 – Compare Register A
Timer/Counter1 – Compare Register B
RAM Address Register
Page 89
Page 89
Page 89
Page 17
RAM Data Register
Page 17
–
–
PUEC5
PORTC5
DDRC5
PINC5
PUEC4
PORTC4
DDRC4
PINC4
PUEC3
PORTC3
DDRC3
PINC3
PCINT15
–
PUEC2
PORTC2
DDRC2
PINC2
PCINT14
–
PUEC1
PORTC1
DDRC1
PINC1
PUEC0
PORTC0
DDRC0
PINC0
Page 59
PORTC
DDRC
–
–
Page 59
–
–
Page 59
PINC
–
–
Page 59
PCMSK2
TCCR0A
TCCR0B
TCNT0
OCR0A
OCR0B
ACSRA
ACSRB
ADCSRA
ADCSRB
ADMUX
ADCH
–
–
PCINT17
COM0B1
TSM
PCINT16
COM0B0
PSR
PCINT13
WGM01
CS01
PCINT12
WGM00
CS00
Page 40
COM0A1
FOC0A
COM0A0
FOC0B
Page 71
WGM02
CS02
Pages 74, 93
Page 75
Timer/Counter0 – Counter Register
Timer/Counter0 – Compare Register A
Timer/Counter0 – Compare Register B
Page 75
Page 75
ACBG/ACIRE
HLEV
ACD
HSEL
ADEN
VDEN
–
ACO
ACLP
ADATE
–
ACI
ACIE
ACCE
ADIE
ACIC
ACME
ADPS2
ADTS2
MUX2
ACIS1
ACIRS1
ADPS1
ADTS1
MUX1
ACIS0
ACIRS0
ADPS0
ADTS0
MUX0
Page 95
–
ADIF
–
Page 96
ADSC
Page 111
Page 112
Page 109
Page 111
Page 111
Pages 97, 113
Page 39
VDPD
ADLAR
MUX3
REFS
REFEN
ADC0EN
ADC Conversion Result – High Byte
ADC Conversion Result – Low Byte
ADCL
DIDR0
ADC7D
ADC6D
PCIE2
PCIF2
–
ADC5D
PCIE1
PCIF1
–
ADC4D
PCIE0
PCIF0
–
ADC3D
–
ADC2D
–
ADC1D
–
ADC0D
INT0
GIMSK
GIFR
–
–
–
–
–
INTF0
Page 40
PCMSK1
PCMSK0
PORTCR
PUEB
–
PCINT7
ADC11D
–
PCINT11
PCINT3
–
PCINT10
PCINT2
BBMC
PUEB2
PORTB2
DDRB2
PINB2
PUEA2
PORTA2
DDRA2
PINA2
PCINT9
PCINT1
BBMB
PUEB1
PORTB1
DDRB1
PINB1
PUEA1
PORTA1
DDRA1
PINA1
PCINT8
PCINT0
BBMA
Page 41
PCINT6
ADC10D
–
PCINT5
ADC9D
–
PCINT4
ADC8D
–
Page 41
Pages 58, 113
Page 59
PUEB3
PORTB3
DDRB3
PINB3
PUEA3
PORTA3
DDRA3
PINA3
PUEB0
PORTB0
DDRB0
PINB0
PORTB
DDRB
–
–
–
–
Page 59
–
–
–
–
Page 59
PINB
–
–
–
–
Page 59
PUEA
PUEA7
PORTA7
DDRA7
PINA7
PUEA6
PORTA6
DDRA6
PINA6
PUEA5
PORTA5
DDRA5
PINA5
PUEA4
PORTA4
DDRA4
PINA4
PUEA0
PORTA0
DDRA0
PINA0
Page 58
PORTA
DDRA
Page 58
Page 58
PINA
Page 59
Note:
1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
ATtiny40 [SUMMARY DATASHEET]
6
8263BS–AVR–01/2013
should never be written.
2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The
CBI and SBI instructions work with registers 0x00 to 0x1F only.
6. Ordering Information
Speed (MHz)
Power Supply
Ordering Code(1)
Package(2)
Operational Range
ATtiny40-SU
ATtiny40-SUR
ATtiny40-XU
20S2
20S2
20X
Industrial
12
1.8 - 5.5V
ATtiny40-XUR
ATtiny40-MMH(3)
ATtiny40-MMHR(3)
20X
(-40C to +85C)(4)
20M2(3)
20M2(3)
Notes: 1. Code indicators:
– H: NiPdAu lead finish
– U: matte tin
– R: tape & reel
2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazard-
ous Substances (RoHS).
3. Topside marking for ATtiny40:
– 1st Line: T40
– 2nd & 3rd Line: manufacturing data
4. These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering informa-
tion and minimum quantities.
Package Type
20S2
20X
20-lead, 0.300" Wide Body, Plastic Gull Wing Small Outline Package (SOIC)
20-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)
20-pad, 3 x 3 x 0.85 mm Body, Very Thin Quad Flat No Lead Package (VQFN)
20M2
ATtiny40 [SUMMARY DATASHEET]
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7. Packaging Information
7.1
20S2
ATtiny40 [SUMMARY DATASHEET]
8
8263BS–AVR–01/2013
7.2
20X
Dimensions in Millimeters and (Inches).
Controlling dimension: Millimeters.
JEDEC Standard MO-153 AC
INDEX MARK
PIN
1
6.50 (0.256)
6.25 (0.246)
4.50 (0.177)
4.30 (0.169)
6.60 (.260)
6.40 (.252)
1.20 (0.047) MAX
0.65 (.0256) BSC
0.15 (0.006)
0.05 (0.002)
SEATING
PLANE
0.30 (0.012)
0.19 (0.007)
0.20 (0.008)
0.09 (0.004)
0º ~ 8º
0.75 (0.030)
0.45 (0.018)
10/23/03
TITLE
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
20X, (Formerly 20T), 20-lead, 4.4 mm Body Width,
Plastic Thin Shrink Small Outline Package (TSSOP)
20X
C
R
ATtiny40 [SUMMARY DATASHEET]
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8263BS–AVR–01/2013
7.3
20M2
D
C
y
Pin 1 ID
E
SIDE VIEW
TOP VIEW
A1
A
D2
16
17
18
19
20
COMMON DIMENSIONS
(Unit of Measure = mm)
C0.18 (8X)
MIN
0.75
0.00
0.17
MAX
0.85
0.05
0.27
NOM
0.80
0.02
0.22
0.152
3.00
1.55
3.00
1.55
0.45
0.40
–
NOTE
SYMBOL
15
14
13
12
11
1
2
3
4
5
A
Pin #1 Chamfer
(C 0.3)
A1
b
e
E2
C
D
D2
E
2.90
1.40
2.90
1.40
–
3.10
1.70
3.10
1.70
–
E2
e
b
10
9
8
7
6
L
0.35
0.20
0.00
0.45
–
0.3 Ref (4x)
K
L
K
BOTTOM VIEW
y
–
0.08
10/24/08
GPC
DRAWING NO.
TITLE
REV.
20M2, 20-pad,3 x 3 x 0.85 mm Body, Lead Pitch 0.45 mm,
1.55 x 1.55 mm Exposed Pad, Thermally Enhanced
Plastic Very Thin Quad Flat No Lead Package (VQFN)
Package Drawing Contact:
packagedrawings@atmel.com
ZFC
20M2
B
ATtiny40 [SUMMARY DATASHEET]
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8263BS–AVR–01/2013
8. Errata
The revision letters in this section refer to the revision of the corresponding ATtiny40 device.
8.1
Rev. B
• MISO output driver is not disabled by Slave Select (SS) signal.
• Current consumption in sleep modes may exceed specifications.
1. MISO output driver is not disabled by Slave Select (SS) signal.
When SPI is configured as a slave and the MISO pin is configured as an output the pin output driver is con-
stantly enabled, even when the SS pin is high. If other slave devices are connected to the same MISO line this
behaviour may cause drive contention.
Problem Fix / Workaround
Monitor SS pin by software and use the DDRC2 bit of DDRC to control the MISO pin driver.
2. Current consumption in sleep mode may exceed specifications.
Some settings of register R27 may increase current consumption in sleep mode.
Problem Fix / Workaround
Before entering sleep mode, make sure register R27 is not loaded with 0x00 or 0x01.
8.2
Rev. A
Not sampled.
ATtiny40 [SUMMARY DATASHEET]
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Atmel Corporation
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