ATTINY261A-SUR [MICROCHIP]
IC MCU 8BIT 2KB FLASH 20SOIC;
| 型号： | ATTINY261A-SUR |
| 厂家： | 
MICROCHIP |
| 描述： | IC MCU 8BIT 2KB FLASH 20SOIC 时钟 微控制器 光电二极管 外围集成电路 |
| 文件： | 总22页 (文件大小：418K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• High Performance, Low Power AVR® 8-Bit Microcontroller
• Advanced RISC Architecture
– 123 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 20 MIPS Throughput at 20 MHz
• High Endurance Non-volatile Memory Segments
– 2/4/8K Bytes of In-System Self-Programmable Flash Program Memory
• Endurance: 10,000 Write/Erase Cycles
– 128/256/512 Bytes of In-System Programmable EEPROM
• Endurance: 100,000 Write/Erase Cycles
– 128/256/512 Bytes of Internal SRAM
– Data retention: 20 Years at 85°C / 100 Years at 25°C
– In-System Programmable via SPI Port
– Programming Lock for Software Security
• Peripheral Features
8-bit
Microcontroller
with 2/4/8K
Bytes In-System
Programmable
Flash
– One 8/16-bit Timer/Counter with Prescaler
– One 8/10-bit High Speed Timer/Counter with Prescaler
• 3 High Frequency PWM Outputs with Separate Output Compare Registers
• Programmable Dead Time Generator
– 10-bit ADC
ATtiny261A
ATtiny461A
ATtiny861A
• 11 Single-Ended Channels
• 16 Differential ADC Channel Pairs
• 15 Differential ADC Channel Pairs with Programmable Gain (1x, 8x, 20x, 32x)
– On-Chip Analog Comparator
– Programmable Watchdog Timer with Separate On-Chip Oscillator
– Universal Serial Interface with Start Condition Detector
– Interrupt and Wake-up on Pin Change
• Special Microcontroller Features
Summary
– debugWIRE On-Chip Debug System
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
– Four Sleep Modes: Low Power Idle, ADC Noise Reduction, Standby and Power-
Down
– On-Chip Temperature Sensor
• I/O and Packages
– 16 Programmable I/O Lines
– 20-pin PDIP, 20-pin SOIC, 20-pin TSSOP and 32-pad MLF
• Operating Voltage
– 1.8 – 5.5V
• Speed Grades
– 0 – 4 MHz @ 1.8 – 5.5V
– 0 – 10 MHz @ 2.7 – 5.5V
– 0 – 20 MHz @ 4.5 – 5.5V
• Power Consumption at 1 MHz, 1.8V, 25°C
– Active: 200 µA
– Power-Down Mode: 0.1 µA
8197CS–AVR–05/11
1. Pin Configurations
Figure 1-1. Pinout ATtiny261A/461A/861A
PDIP/SOIC/TSSOP
(MOSI/DI/SDA/OC1A/PCINT8) PB0
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
PA0 (ADC0/DI/SDA/PCINT0)
PA1 (ADC1/DO/PCINT1)
PA2 (ADC2/INT1/USCK/SCL/PCINT2)
PA3 (AREF/PCINT3)
AGND
AVCC
PA4 (ADC3/ICP0/PCINT4)
PA5 (ADC4/AIN2/PCINT5)
PA6 (ADC5/AIN0/PCINT6)
PA7 (ADC6/AIN1/PCINT7)
(MISO/DO/OC1A/PCINT9) PB1
(SCK/USCK/SCL/OC1B/PCINT10) PB2
(OC1B/PCINT11) PB3
VCC
GND
(ADC7/OC1D/CLKI/XTAL1/PCINT12) PB4
(ADC8/OC1D/CLKO/XTAL2/PCINT13) PB5
(ADC9/INT0/T0/PCINT14) PB6
(ADC10/RESET/PCINT15) PB7
NC
24
NC
1
PA2 (ADC2/INT1/USCK/SCL/PCINT2)
23
(OC1B/PCINT11) PB3
2
PA3 (AREF/PCINT3)
22
NC
3
AGND
21
NC
20
VCC
4
GND
5
QFN/MLF
NC
19
NC
6
AVCC
18
(ADC7/OC1D/CLKI/XTAL1/PCINT12) PB4
7
PA4 (ADC3/ICP0/PCINT4)
17
(ADC8/OC1D/CLKO/XTAL2/PCINT13) PB5
8
Note:
To ensure mechanical stability the center pad underneath the QFN/MLF package should be soldered to ground on the board.
2
ATtiny261A/461A/861A
8197CS–AVR–05/11
ATtiny261A/461A/861A
1.1
Pin Descriptions
1.1.1
VCC
Supply voltage.
1.1.2
1.1.3
GND
Ground.
AVCC
Analog supply voltage. This is the supply voltage pin for the Analog-to-digital Converter (ADC),
the analog comparator, the Brown-Out Detector (BOD), the internal voltage reference and Port
A. It should be externally connected to VCC, even if some peripherals such as the ADC are not
used. If the ADC is used AVCC should be connected to VCC through a low-pass filter.
1.1.4
1.1.5
AGND
Analog ground.
Port A (PA7:PA0)
An 8-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each bit.
Output buffers have symmetrical drive characteristics with both high sink and source capability.
As inputs, port pins that are externally pulled low will source current if pull-up resistors have
been activated. Port pins are tri-stated when a reset condition becomes active, even if the clock
is not running.
Port A also serves the functions of various special features of the device, as listed on page 62.
1.1.6
Port B (PB7:PB0)
An 8-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each bit.
Output buffers have symmetrical drive characteristics with both high sink and source capability.
As inputs, port pins that are externally pulled low will source current if pull-up resistors have
been activated. Port pins are tri-stated when a reset condition becomes active, even if the clock
is not running.
Port B also serves the functions of various special features of the device, as listed on page 65.
1.1.7
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running and provided the reset pin has not been disabled. The min-
imum pulse length is given in Table 19-4 on page 188. Shorter pulses are not guaranteed to
generate a reset.
The reset pin can also be used as a (weak) I/O pin.
3
8197CS–AVR–05/11
2. Overview
ATtiny261A/461A/861A are low-power CMOS 8-bit microcontrollers based on the AVR
enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the
devices achieve throughputs approaching 1 MIPS per MHz allowing the system designer to opti-
mize power consumption versus processing speed.
2.1
Block Diagram
Figure 2-1.
Block Diagram
Watchdog
Timer
Power
Supervision
POR / BOD &
RESET
debugWIRE
Watchdog
Oscillator
PROGRAM
LOGIC
Oscillator
Circuits /
Clock
Flash
SRAM
Generation
CPU
EEPROM
AVCC
AGND
AREF
Timer/Counter0
USI
Timer/Counter1
Analog Comp.
A/D Conv.
Internal
Bandgap
3
11
PORT B (8)
PORT A (8)
RESET
XTAL[1:2]
PB[0:7]
PA[0:7]
The AVR core combines a rich instruction set with 32 general purpose working registers. All 32
registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con-
ventional CISC microcontrollers.
4
ATtiny261A/461A/861A
8197CS–AVR–05/11
ATtiny261A/461A/861A
The ATtiny261A/461A/861A provides the following features: 2/4/8K byte of In-System Program-
mable Flash, 128/256/512 bytes EEPROM, 128/256/512 bytes SRAM, 16 general purpose I/O
lines, 32 general purpose working registers, an 8-bit Timer/Counter with compare modes, an 8-
bit high speed Timer/Counter, a Universal Serial Interface, Internal and External Interrupts, an
11-channel, 10-bit ADC, a programmable Watchdog Timer with internal oscillator, and four soft-
ware selectable power saving modes. Idle mode stops the CPU while allowing the SRAM,
Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. Power-
down mode saves the register contents, disabling all chip functions until the next Interrupt or
Hardware Reset. ADC Noise Reduction mode stops the CPU and all I/O modules except ADC,
to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator
oscillator is running while the rest of the device is sleeping, allowing very fast start-up combined
with low power consumption.
The device is manufactured using Atmel’s high density non-volatile memory technology. The
On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI
serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code
running on the AVR core.
The ATtiny261A/461A/861A AVR is supported by a full suite of program and system develop-
ment tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, and
Evaluation kits.
5
8197CS–AVR–05/11
3. General Information
3.1
Resources
A comprehensive set of drivers, application notes, data sheets and descriptions on development
tools are available for download at http://www.atmel.com/avr.
3.2
Code Examples
This documentation contains simple code examples that briefly show how to use various parts of
the device. These code examples assume that the part specific header file is included before
compilation. Be aware that not all C compiler vendors include bit definitions in the header files
and interrupt handling in C is compiler dependent. Please confirm with the C compiler documen-
tation for more details.
For I/O Registers located in the extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”
instructions must be replaced with instructions that allow access to extended I/O. Typically, this
means “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. Note that not all
AVR devices include an extended I/O map.
3.3
Capacitive Touch Sensing
Atmel QTouch Library provides a simple to use solution for touch sensitive interfaces on Atmel
AVR microcontrollers. The QTouch Library includes support for QTouch® and QMatrix® acquisi-
tion methods.
Touch sensing is easily added to any application by linking the QTouch Library and using the
Application Programming Interface (API) of the library to define the touch channels and sensors.
The application then calls the API to retrieve channel information and determine the state of the
touch sensor.
The QTouch Library is free and can be downloaded from the Atmel website. For more informa-
tion and details of implementation, refer to the QTouch Library User Guide – also available from
the Atmel website.
3.4
Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less
than 1 PPM over 20 years at 85°C or 100 years at 25°C.
6
ATtiny261A/461A/861A
8197CS–AVR–05/11
ATtiny261A/461A/861A
4. Register Summary
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
0x3F (0x5F)
0x3E (0x5E)
0x3D (0x5D)
0x3C (0x5C)
0x3B (0x5B)
0x3A (0x5A)
0x39 (0x59)
0x38 (0x58)
0x37 (0x57)
0x36 (0x56)
0x35 (0x55)
0x34 (0x54)
0x33 (0x53)
0x32 (0x52)
0x31 (0x51)
0x30 (0x50)
0x2F (0x4F)
0x2E (0x4E)
0x2D (0x4D)
0x2C (0x4C)
0x2B (0x4B)
0x2A (0x4A)
0x29 (0x49)
0x28 (0x48)
0x27 (0x47)
0x26 (0x46)
0x25 (0x45)
0x24 (0x44)
0x23 (0x43)
0x22 (0x42)
0x21 (0x41)
0x20 (0x40)
0x1F (0x3F)
0x1E (0x3E)
0x1D (0x3D)
0x1C (0x3C)
0x1B (0x3B)
0x1A (0x3A)
0x19 (0x39)
0x18 (0x38)
0x17 (0x37)
0x16 (0x36)
0x15 (0x35)
0x14 (0x34)
0x13 (0x33)
0x12 (0x32)
0x11 (0x31)
0x10 (0x30)
0x0F (0x2F)
0x0E (0x2E)
0x0D (0x2D)
0x0C (0x2C)
0x0B (0x2B)
0x0A (0x2A)
0x09 (0x29)
0x08 (0x28)
0x07 (0x27)
0x06 (0x26)
0x05 (0x25)
0x04 (0x24)
0x03 (0x23)
0x02 (0x22)
0x01 (0x21)
0x00 (0x20)
SREG
SPH
I
–
T
–
H
–
S
–
V
–
N
Z
C
page 8
page 11
page 11
SP10
SP2
SP9
SP1
SP8
SP0
SPL
SP7
SP6
SP5
SP4
SP3
Reserved
GIMSK
GIFR
–
INT1
INT0
PCIE1
PCIE0
–
–
–
–
–
page 51
page 52
INTF1
INTF0
PCIF
–
–
–
–
TIMSK
TIFR
OCIE1D
OCIE1A
OCIE1B
OCIE0A
OCF0A
CTPB
–
OCIE0B
OCF0B
RFLB
PRTIM1
SM0
TOIE1
TOV1
PGWRT
PRTIM0
BODSE
BORF
CS02
TOIE0
TOV0
PGERS
PRUSI
ISC01
EXTRF
CS01
TICIE0
ICF0
page 85, page 122
page 86, page 122
page 167
page 36
OCF1D
OCF1A
OCF1B
SPMCSR
PRR
–
–
–
–
–
SPMEN
PRADC
ISC00
PORF
CS00
–
MCUCR
MCUSR
TCCR0B
TCNT0L
OSCCAL
TCCR1A
TCCR1B
TCNT1
OCR1A
OCR1B
OCR1C
OCR1D
PLLCSR
CLKPR
TCCR1C
TCCR1D
TC1H
BODS
PUD
–
SE
–
SM1
–
page 38, page 68, page 51
page 46,
page 84
–
–
WDRF
PSR0
–
–
TSM
Timer/Counter0 Counter Register Low Byte
Oscillator Calibration Register
page 84
page 32
COM1A1
PWM1X
COM1A0
PSR1
COM1B1
DTPS11
COM1B0
DTPS10
FOC1A
CS13
FOC1B
CS12
PWM1A
CS11
PWM1B
CS10
page 111
page 167
page 120
page 120
page 121
page 121
page 121
page 119
page 32
Timer/Counter1 Counter Register
Timer/Counter1 Output Compare Register A
Timer/Counter1 Output Compare Register B
Timer/Counter1 Output Compare Register C
Timer/Counter1 Output Compare Register D
LSM
CLKPCE
COM1A1S
FPIE1
PCKE
PLLE
CLKPS1
FOC1D
WGM11
TC19
PLOCK
CLKPS0
PWM1D
WGM10
TC18
CLKPS3
COM1D1
FPAC1
–
CLKPS2
COM1D0
FPF1
COM1A0S
FPEN1
–
COM1B1S
FPNC1
–
COM1B0S
FPES1
–
page 116
page 117
page 120
page 123
page 53
–
–
DT1
DT1H3
PCINT7
PCINT15
WDIF
DT1H2
PCINT6
PCINT14
WDIE
DT1H1
PCINT5
PCINT13
WDP3
DT1H0
PCINT4
PCINT12
WDCE
DT1L3
PCINT3
PCINT11
WDE
DT1L2
PCINT2
PCINT10
WDP2
DT1L1
PCINT1
PCINT9
WDP1
DT1L0
PCMSK0
PCMSK1
WDTCR
DWDR
EEARH
EEARL
EEDR
PCINT0
PCINT8
WDP0
page 53
page 46
DWDR[7:0]
page 36
–
–
–
–
–
–
–
EEAR8
EEAR0
page 20
EEAR7
EEAR6
EEAR5
EEAR4
EEAR3
EEAR2
EEAR1
page 21
EEPROM Data Register
page 21
EECR
–
–
EEPM1
PORTA5
DDA5
EEPM0
PORTA4
DDA4
EERIE
PORTA3
DDA3
EEMPE
PORTA2
DDA2
PINA2
PORTB2
DDB2
PINB2
–
EEPE
PORTA1
DDA1
PINA1
PORTB1
DDB1
PINB1
–
EERE
PORTA0
DDA0
page 21
PORTA
DDRA
PORTA7
DDA7
PORTA6
DDA6
page 68
page 68
PINA
PINA7
PORTB7
DDB7
PINA6
PORTB6
DDB6
PINA5
PINA4
PINA3
PINA0
PORTB0
DDB0
page 69
PORTB
DDRB
PORTB5
DDB5
PORTB4
DDB4
PORTB3
DDB3
page 69
page 69
PINB
PINB7
TCW0
PINB6
ICEN0
PINB5
PINB4
PINB3
PINB0
CTC0
page 69
TCCR0A
TCNT0H
OCR0A
OCR0B
USIPP
ICNC0
ICES0
ACIC0
page 83
Timer/Counter0 Counter Register High Byte
Timer/Counter0 Output Compare Register A
Timer/Counter0 Output Compare Register B
page 85
page 85
page 85
–
–
–
–
–
–
–
USIPOS
page 135
page 132
page 131
page 132
page 133
page 23
USIBR
USIDR
USISR
USICR
GPIOR2
GPIOR1
GPIOR0
ACSRB
ACSRA
ADMUX
ADCSRA
ADCH
USI Buffer Register
USI Data Register
USISIF
USISIE
USIOIF
USIOIE
USIPF
USIDC
USIWM0
USICNT3
USICS1
USICNT2
USICS0
USICNT1
USICLK
USICNT0
USITC
USIWM1
General Purpose I/O Register 2
General Purpose I/O Register 1
General Purpose I/O Register 0
page 23
page 23
HSEL
ACD
HLEV
ACBG
REFS0
ADSC
–
–
–
ACM2
ACME
MUX2
ADPS2
ACM1
ACIS1
MUX1
ADPS1
ACM0
ACIS0
MUX0
ADPS0
page 139
page 138
page 155
page 154
page 155
page 155
page 159
page 160
page 160
page 118
ACO
ACI
ACIE
MUX3
ADIE
REFS1
ADEN
ADLAR
ADATE
MUX4
ADIF
ADC Data Register High Byte
ADC Data Register Low Byte
ADCL
ADCSRB
DIDR1
BIN
ADC10D
ADC6D
–
GSEL
ADC9D
ADC5D
–
–
REFS2
ADC7D
ADC3D
OC1OE4
MUX5
–
ADTS2
–
ADTS1
–
ADTS0
–
ADC8D
ADC4D
OC1OE5
DIDR0
AREFD
OC1OE3
ADC2D
OC1OE2
ADC1D
OC1OE1
ADC0D
OC1OE0
TCCR1E
7
8197CS–AVR–05/11
Note:
1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The
CBI and SBI instructions work with registers 0x00 to 0x1F only.
8
ATtiny261A/461A/861A
8197CS–AVR–05/11
ATtiny261A/461A/861A
5. Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
ADC
ADIW
SUB
SUBI
SBC
SBCI
SBIW
AND
ANDI
OR
Rd, Rr
Rd, Rr
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd
Add two Registers
Rd ← Rd + Rr
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,N,V
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Add with Carry two Registers
Add Immediate to Word
Subtract two Registers
Subtract Constant from Register
Subtract with Carry two Registers
Subtract with Carry Constant from Reg.
Subtract Immediate from Word
Logical AND Registers
Logical AND Register and Constant
Logical OR Registers
Rd ← Rd + Rr + C
Rdh:Rdl ← Rdh:Rdl + K
Rd ← Rd - Rr
Rd ← Rd - K
Rd ← Rd - Rr - C
Rd ← Rd - K - C
Rdh:Rdl ← Rdh:Rdl - K
Rd ← Rd • Rr
Rd ← Rd • K
Z,N,V
Rd ← Rd v Rr
Z,N,V
ORI
Logical OR Register and Constant
Exclusive OR Registers
One’s Complement
Rd ← Rd v K
Z,N,V
EOR
COM
NEG
SBR
CBR
INC
Rd ← Rd ⊕ Rr
Rd ← 0xFF − Rd
Rd ← 0x00 − Rd
Rd ← Rd v K
Z,N,V
Z,C,N,V
Z,C,N,V,H
Z,N,V
Rd
Two’s Complement
Rd,K
Rd,K
Rd
Set Bit(s) in Register
Clear Bit(s) in Register
Increment
Rd ← Rd • (0xFF - K)
Rd ← Rd + 1
Z,N,V
Z,N,V
DEC
TST
Rd
Decrement
Rd ← Rd − 1
Z,N,V
Rd
Test for Zero or Minus
Clear Register
Rd ← Rd • Rd
Rd ← Rd ⊕ Rd
Rd ← 0xFF
Z,N,V
CLR
SER
Rd
Z,N,V
Rd
Set Register
None
BRANCH INSTRUCTIONS
RJMP
IJMP
k
k
Relative Jump
PC ← PC + k + 1
None
None
None
None
None
I
2
2
Indirect Jump to (Z)
PC ← Z
RCALL
ICALL
RET
Relative Subroutine Call
Indirect Call to (Z)
PC ← PC + k + 1
3
PC ← Z
3
Subroutine Return
PC ← STACK
4
RETI
Interrupt Return
PC ← STACK
4
CPSE
CP
Rd,Rr
Compare, Skip if Equal
Compare
if (Rd = Rr) PC ← PC + 2 or 3
Rd − Rr
None
Z, N,V,C,H
Z, N,V,C,H
Z, N,V,C,H
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1/2/3
1
Rd,Rr
CPC
Rd,Rr
Compare with Carry
Rd − Rr − C
1
CPI
Rd,K
Compare Register with Immediate
Skip if Bit in Register Cleared
Skip if Bit in Register is Set
Skip if Bit in I/O Register Cleared
Skip if Bit in I/O Register is Set
Branch if Status Flag Set
Branch if Status Flag Cleared
Branch if Equal
Rd − K
1
SBRC
SBRS
SBIC
Rr, b
if (Rr(b)=0) PC ← PC + 2 or 3
if (Rr(b)=1) PC ← PC + 2 or 3
if (P(b)=0) PC ← PC + 2 or 3
if (P(b)=1) PC ← PC + 2 or 3
if (SREG(s) = 1) then PC←PC+k + 1
if (SREG(s) = 0) then PC←PC+k + 1
if (Z = 1) then PC ← PC + k + 1
if (Z = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (N = 1) then PC ← PC + k + 1
if (N = 0) then PC ← PC + k + 1
if (N ⊕ V= 0) then PC ← PC + k + 1
if (N ⊕ V= 1) then PC ← PC + k + 1
if (H = 1) then PC ← PC + k + 1
if (H = 0) then PC ← PC + k + 1
if (T = 1) then PC ← PC + k + 1
if (T = 0) then PC ← PC + k + 1
if (V = 1) then PC ← PC + k + 1
if (V = 0) then PC ← PC + k + 1
if ( I = 1) then PC ← PC + k + 1
if ( I = 0) then PC ← PC + k + 1
1/2/3
1/2/3
1/2/3
1/2/3
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
Rr, b
P, b
P, b
s, k
s, k
k
SBIS
BRBS
BRBC
BREQ
BRNE
BRCS
BRCC
BRSH
BRLO
BRMI
BRPL
BRGE
BRLT
BRHS
BRHC
BRTS
BRTC
BRVS
BRVC
BRIE
BRID
k
Branch if Not Equal
k
Branch if Carry Set
k
Branch if Carry Cleared
Branch if Same or Higher
Branch if Lower
k
k
k
Branch if Minus
k
Branch if Plus
k
Branch if Greater or Equal, Signed
Branch if Less Than Zero, Signed
Branch if Half Carry Flag Set
Branch if Half Carry Flag Cleared
Branch if T Flag Set
k
k
k
k
k
Branch if T Flag Cleared
Branch if Overflow Flag is Set
Branch if Overflow Flag is Cleared
Branch if Interrupt Enabled
Branch if Interrupt Disabled
k
k
k
k
BIT AND BIT-TEST INSTRUCTIONS
SBI
P,b
P,b
Rd
Rd
Rd
Rd
Set Bit in I/O Register
Clear Bit in I/O Register
Logical Shift Left
I/O(P,b) ← 1
None
2
2
1
1
1
1
CBI
I/O(P,b) ← 0
None
LSL
LSR
ROL
ROR
Rd(n+1) ← Rd(n), Rd(0) ← 0
Rd(n) ← Rd(n+1), Rd(7) ← 0
Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)
Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V
Logical Shift Right
Rotate Left Through Carry
Rotate Right Through Carry
9
8197CS–AVR–05/11
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ASR
Rd
Arithmetic Shift Right
Swap Nibbles
Flag Set
Rd(n) ← Rd(n+1), n=0..6
Z,C,N,V
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
SWAP
BSET
BCLR
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
Rd
s
Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)
None
SREG(s) ← 1
SREG(s) ← 0
T ← Rr(b)
Rd(b) ← T
C ← 1
SREG(s)
s
Flag Clear
SREG(s)
Rr, b
Rd, b
Bit Store from Register to T
Bit load from T to Register
Set Carry
T
None
C
C
N
N
Z
Clear Carry
C ← 0
Set Negative Flag
N ← 1
Clear Negative Flag
Set Zero Flag
N ← 0
Z ← 1
Clear Zero Flag
Z ← 0
Z
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
Set Twos Complement Overflow.
Clear Twos Complement Overflow
Set T in SREG
I ← 1
I
CLI
I ← 0
I
SES
CLS
SEV
CLV
SET
CLT
SEH
CLH
S ← 1
S
S
V
V
T
S ← 0
V ← 1
V ← 0
T ← 1
Clear T in SREG
T ← 0
T
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
H ← 1
H
H
H ← 0
DATA TRANSFER INSTRUCTIONS
MOV
MOVW
LDI
LD
Rd, Rr
Rd, Rr
Rd, K
Move Between Registers
Copy Register Word
Rd ← Rr
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
Rd+1:Rd ← Rr+1:Rr
Load Immediate
Rd ← K
Rd, X
Load Indirect
Rd ← (X)
LD
Rd, X+
Rd, - X
Rd, Y
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect
Rd ← (X), X ← X + 1
X ← X - 1, Rd ← (X)
Rd ← (Y)
LD
LD
LD
Rd, Y+
Rd, - Y
Rd,Y+q
Rd, Z
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Indirect
Rd ← (Y), Y ← Y + 1
Y ← Y - 1, Rd ← (Y)
Rd ← (Y + q)
Rd ← (Z)
LD
LDD
LD
LD
Rd, Z+
Rd, -Z
Rd, Z+q
Rd, k
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Direct from SRAM
Store Indirect
Rd ← (Z), Z ← Z+1
Z ← Z - 1, Rd ← (Z)
Rd ← (Z + q)
Rd ← (k)
LD
LDD
LDS
ST
X, Rr
(X) ← Rr
ST
X+, Rr
- X, Rr
Y, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect
(X) ← Rr, X ← X + 1
X ← X - 1, (X) ← Rr
(Y) ← Rr
ST
ST
ST
Y+, Rr
- Y, Rr
Y+q,Rr
Z, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Indirect
(Y) ← Rr, Y ← Y + 1
Y ← Y - 1, (Y) ← Rr
(Y + q) ← Rr
ST
STD
ST
(Z) ← Rr
ST
Z+, Rr
-Z, Rr
Z+q,Rr
k, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Direct to SRAM
Load Program Memory
Load Program Memory
Load Program Memory and Post-Inc
Store Program Memory
In Port
(Z) ← Rr, Z ← Z + 1
Z ← Z - 1, (Z) ← Rr
(Z + q) ← Rr
ST
STD
STS
LPM
LPM
LPM
SPM
IN
(k) ← Rr
R0 ← (Z)
Rd, Z
Rd ← (Z)
Rd, Z+
Rd ← (Z), Z ← Z+1
(z) ← R1:R0
Rd, P
P, Rr
Rr
Rd ← P
1
1
2
2
OUT
PUSH
POP
Out Port
P ← Rr
Push Register on Stack
Pop Register from Stack
STACK ← Rr
Rd ← STACK
Rd
MCU CONTROL INSTRUCTIONS
NOP
No Operation
Sleep
None
None
None
None
1
1
SLEEP
WDR
(see specific descr. for Sleep function)
(see specific descr. for WDR/Timer)
For On-chip Debug Only
Watchdog Reset
Break
1
BREAK
N/A
10
ATtiny261A/461A/861A
8197CS–AVR–05/11
ATtiny261A/461A/861A
6. Ordering Information
6.1
ATtiny261A
Speed (MHz)
Power Supply
Ordering Code (1)
Package (2)
Operational Range
ATtiny261A-MU
ATtiny261A-MUR
ATtiny261A-PU
ATtiny261A-SU
ATtiny261A-SUR
ATtiny261A-XU
ATtiny261A-XUR
32M1-A
32M1-A
20P3
20S2
20S2
20X
Industrial
(-40°C to +85°C) (3)
20
1.8 – 5.5V
20X
Industrial
(-40°C to +105°C) (4)
ATtiny261A-MN
ATtiny261A-MNR
32M1-A
32M1-A
20
1.8 – 5.5V
Notes: 1. Code indicators:
– N or U: matte tin
– R: tape & reel
2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazard-
ous Substances (RoHS).
3. These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering informa-
tion and minimum quantities.
4. For typical and electrical characteristics of this device please consult “Appendix A – ATtiny261A Specification at 105°C”.
Package Type
32M1-A
32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm, Micro Lead Frame Package (MLF)
20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
20P3
20S2
20X
20-lead, 0.300" Wide, Plastic Gull Wing Small Outline Package (SOIC)
20-lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline Package (TSSOP)
11
8197CS–AVR–05/11
6.2
ATtiny461A
Speed (MHz)
Power Supply
Ordering Code (1)
Package (2)
Operational Range
ATtiny461A-MU
ATtiny461A-MUR
ATtiny461A-PU
ATtiny461A-SU
ATtiny461A-SUR
ATtiny461A-XU
ATtiny461A-XUR
32M1-A
32M1-A
20P3
20S2
20S2
20X
Industrial
(-40°C to +85°C) (3)
20
1.8 – 5.5V
20X
Notes: 1. Code indicators:
– U: matte tin
– R: tape & reel
2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazard-
ous Substances (RoHS).
3. These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering informa-
tion and minimum quantities.
Package Type
32M1-A
32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm, Micro Lead Frame Package (MLF)
20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
20P3
20S2
20X
20-lead, 0.300" Wide, Plastic Gull Wing Small Outline Package (SOIC)
20-lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline Package (TSSOP)
12
ATtiny261A/461A/861A
8197CS–AVR–05/11
ATtiny261A/461A/861A
6.3
ATtiny861A
Speed (MHz)
Power Supply
Ordering Code (1)
Package (2)
Operational Range
ATtiny861A-MU
ATtiny861A-MUR
ATtiny861A-PU
ATtiny861A-SU
ATtiny861A-SUR
ATtiny861A-XU
ATtiny861A-XUR
32M1-A
32M1-A
20P3
20S2
20S2
20X
Industrial
(-40°C to +85°C) (3)
20
1.8 – 5.5V
20X
Notes: 1. Code indicators:
– U: matte tin
– R: tape & reel
2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazard-
ous Substances (RoHS).
3. These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering informa-
tion and minimum quantities.
Package Type
32M1-A
32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm, Micro Lead Frame Package (MLF)
20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
20P3
20S2
20X
20-lead, 0.300" Wide, Plastic Gull Wing Small Outline Package (SOIC)
20-lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline Package (TSSOP)
13
8197CS–AVR–05/11
7. Packaging Information
7.1
32M1-A
D
D1
1
2
3
0
Pin 1 ID
SIDE VIEW
E1
E
TOP VIEW
A3
A1
A2
A
K
COMMON DIMENSIONS
(Unit of Measure = mm)
0.08
C
P
D2
MIN
0.80
–
MAX
1.00
0.05
1.00
NOM
0.90
0.02
0.65
0.20 REF
0.23
5.00
4.75
3.10
5.00
4.75
3.10
0.50 BSC
0.40
–
NOTE
SYMBOL
A
A1
A2
A3
b
1
2
3
P
–
Pin #1 Notch
(0.20 R)
E2
0.18
4.90
4.70
2.95
4.90
4.70
2.95
0.30
5.10
4.80
3.25
5.10
4.80
3.25
D
K
D1
D2
E
e
b
L
E1
E2
e
BOTTOM VIEW
L
0.30
–
0.50
0.60
P
o
–
–
12
0
Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2.
K
0.20
–
–
5/25/06
DRAWING NO. REV.
32M1-A
TITLE
2325 Orchard Parkway
San Jose, CA 95131
32M1-A, 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm,
3.10 mm Exposed Pad, Micro Lead Frame Package (MLF)
E
R
14
ATtiny261A/461A/861A
8197CS–AVR–05/11
ATtiny261A/461A/861A
7.2
20P3
D
PIN
1
E1
A
SEATING PLANE
A1
L
B
B1
e
E
COMMON DIMENSIONS
(Unit of Measure = mm)
C
MIN
–
MAX
5.334
–
NOM
NOTE
SYMBOL
eC
A
–
–
–
–
–
–
–
–
–
–
–
eB
A1
D
0.381
25.493
7.620
6.096
0.356
1.270
2.921
0.203
–
25.984 Note 2
8.255
E
E1
B
7.112 Note 2
0.559
B1
L
1.551
3.810
C
0.356
Notes:
eB
eC
e
10.922
1. This package conforms to JEDEC reference MS-001, Variation AD.
2. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
0.000
1.524
2.540 TYP
2010-10-19
DRAWING NO. REV.
20P3
TITLE
2325 Orchard Parkway
San Jose, CA 95131
20P3, 20-lead (0.300"/7.62 mm Wide) Plastic Dual
Inline Package (PDIP)
D
R
15
8197CS–AVR–05/11
7.3
20S2
16
ATtiny261A/461A/861A
8197CS–AVR–05/11
ATtiny261A/461A/861A
7.4
20X
Dimensions in Millimeters and (Inches).
Controlling dimension: Millimeters.
JEDEC Standard MO-153 AC
INDEX MARK
PIN
1
6.50 (0.256)
6.25 (0.246)
4.50 (0.177)
4.30 (0.169)
6.60 (.260)
6.40 (.252)
1.20 (0.047) MAX
0.65 (.0256) BSC
0.15 (0.006)
0.05 (0.002)
SEATING
PLANE
0.30 (0.012)
0.19 (0.007)
0.20 (0.008)
0.09 (0.004)
0º ~ 8º
0.75 (0.030)
0.45 (0.018)
10/23/03
TITLE
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
20X, (Formerly 20T), 20-lead, 4.4 mm Body Width,
Plastic Thin Shrink Small Outline Package (TSSOP)
20X
C
R
17
8197CS–AVR–05/11
8. Errata
8.1
Errata ATtiny261A
The revision letter in this section refers to the revision of the ATtiny261A device.
8.1.1
8.1.2
Rev D
Rev C
No known errata.
Not sampled.
8.2
Errata ATtiny461A
The revision letter in this section refers to the revision of the ATtiny461A device.
8.2.1
Rev C
No known errata.
8.3
Errata ATtiny861A
The revision letter in this section refers to the revision of the ATtiny861A device.
8.3.1
8.3.2
Rev D
Rev C
No known errata.
Not sampled.
18
ATtiny261A/461A/861A
8197CS–AVR–05/11
ATtiny261A/461A/861A
9. Datasheet Revision History
9.1
Rev. 8197C – 05/11
1. Added:
– Section 3.3 “Capacitive Touch Sensing” on page 6
– Section 4. “CPU Core” on page 7
– Table 6-10, “Capacitance of Low-Frequency Crystal Oscillator,” on page 29
– Table 15-5 on page 157
– Section 19.7 “Analog Comparator Characteristics” on page 193
– Table 19-8 on page 191
– Table 19-9 on page 192
– Tape & reel part numbers in Section 23. “Ordering Information” on page 281
– Ordering codes for ATtiny261A with extended temperature, on page 281
2. Updated:
– Section 6.4 “Clock Output Buffer” on page 32 (CLKO)
– Figure 15-1 on page 142, “Analog to Digital Converter Block Schematic”, changed
INTERNAL 1.18V REFERENCE to 1.1V
– Table 18-8 on page 171, No. of Pages in the EEPROM from 64 to 32 for ATtiny261A
– Table 19-1 on page 185
– Section 19.3 “Speed” on page 187
– Characteristic plots Figure 20-3 on page 200, Figure 20-8 on page 202, Figure 20-
54 on page 226, Figure 20-59 on page 228, Figure 20-105 on page 252, and Figure
20-110 on page 254
– Bit syntax throughout the datasheet, e.g. from CS02:0 to CS0[2:0]
3. Deleted:
– “Preliminary” status. All devices now final and in production.
– “Disclaimer” on page 6.
9.2
9.3
Rev. 8197B – 01/10
1. Updated 32M1-A drawing in Section 24. “Packaging Information” on page 284.
Rev. 8197A – 10/09
1. Initial revision created from document 2588C (ATtiny261/461/861)
2. Updated "Ordering Information" on page 281, page 282 and page 283. Pb-plated pack-
ages are no longer offered and there are no separate ordering codes for commercial
operation range, the only available option now is industrial. Also, added new package
options
3. Added sections:
– “Software BOD Disable” on page 36
– “ATtiny461A” on page 225
– “ATtiny861A” on page 251
4. Updated sections:
– “Stack Pointer” on page 11
19
8197CS–AVR–05/11
– “OSCCAL – Oscillator Calibration Register” on page 32
– “MCUCR – MCU Control Register” on page 38
– “MCUCR – MCU Control Register” on page 51
– “MCUCR – MCU Control Register” on page 68
– “Speed” on page 187
– “Enhanced Power-On Reset” on page 189
– “ATtiny261A” on page 199
– “Register Summary” on page 277
5. Updated tables:
– “DC Characteristics. TA = -40°C to +85°C, VCC = 1.8V to 5.5V (unless otherwise
noted).” on page 185
– “Additional Current Consumption for the different I/O modules (absolute values).” on
page 197
– “Additional Current Consumption (percentage) in Active and Idle mode.” on page
198
20
ATtiny261A/461A/861A
8197CS–AVR–05/11
ATtiny261A/461A/861A
21
8197CS–AVR–05/11
Headquarters
International
Atmel Corporation
2325 Orchard Parkway
San Jose, CA 95131
USA
Tel: (+1)(408) 441-0311
Fax: (+1)(408) 487-2600
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Tel: (+852) 2245-6100
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Product Contact
Web Site
Technical Support
Sales Contact
www.atmel.com
avr@atmel.com
www.atmel.com/contacts
Literature Requests
www.atmel.com/literature
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8197CS–AVR–05/11
相关型号：
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