ATSAM4LS4BA-AU [MICROCHIP]
IC MCU 32BIT 256KB FLASH 64TQFP;
| 型号： | ATSAM4LS4BA-AU |
| 厂家： | 
MICROCHIP |
| 描述： | IC MCU 32BIT 256KB FLASH 64TQFP 时钟 微控制器 外围集成电路 |
| 文件： | 总176页 (文件大小：1827K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Summary
Atmel's SAM4L series is a member of a family of Flash microcontrollers based
on the high performance 32-bit ARM Cortex-M4 RISC processor running at fre-
quencies up to 48MHz.
The SAM4L series embeds state-of-the-art picoPower technology for ultra-low
power consumption. Combined power control techniques are used to bring
active current consumption down to 90μA/MHz. The device allows a wide range
of options between functionality and power consumption, giving the user the
ability to reach the lowest possible power consumption with the feature set
required for the application. The WAIT and RETENTION modes provide full logic
and RAM retention, associated with fast wake-up capability (<1.5μs) and a very
low consumption of, respectively, 3 μA and 1.5 μA. In addition, WAIT mode sup-
ports SleepWalking features. In BACKUP mode, CPU, peripherals and RAM are
powered off and, while consuming less than 0.9μA with external interrupt wake-
up supported.
ATSAM---e
ARM-based
Flash MCU
SAM4L Series
The SAM4L series offers a wide range of peripherals such as segment LCD con-
troller, embedded hardware capacitive touch (QTouch), USB device &
embedded host, 128-bit AES and audio interfaces in addition to high speed
serial peripherals such as USART, SPI and I2C. Additionally the Peripheral Event
System and SleepWalking allows the peripherals to communicate directly with
each other and make intelligent decisions and decide to wake-up the system on
a qualified events on a peripheral level; such as I2C address match or and ADC
threshold.
Features
• Core
Summary
– ARM® CortexTM-M4 running at up to 48MHz
– Memory Protection Unit (MPU)
– Thumb®-2 instruction set
• picoPower® Technology for Ultra-low Power Consumption
– Active mode downto 90µA/MHz with configurable voltage scaling
– High performance and efficiency: 28 coremark/mA
– Wait mode downto 3µA with fast wake-up time (<1.5µs) supporting SleepWalking
– Full RAM and Logic Retention mode downto 1.5µA with fast wake-up time (<1.5µs)
– Ultra low power Backup mode with/without RTC downto 1,5/0.9µA
• Memories
– From 128 to 512Kbytes embedded Flash, 64-bit wide access,
• 0 wait-state capability up to 24MHz
– up to 64Kbytes embedded SRAM
• System Functions
– Embedded voltage linear and switching regulator for single supply operation
– Two Power-on-Reset and Two Brown-out Detectors (BOD)
– Quartz or ceramic resonator oscillators: 0.6 to 30MHz main power with Failure
Detection and low power 32.768 kHz for RTC or device clock
– High precision 4/8/12MHz factory trimmed internal RC oscillator
– Slow Clock Internal RC oscillator as permanent low-power mode device clock
– High speed 80MHz internal RC oscillator
42023HS–11/2016
– Low power 32kHz internal RC oscillator
ATSAM4L8/L4/L2
– PLL up to 240MHz for device clock and for USB
– Digital Frequency Locked Loop (DFLL) with wide input range
– Up to 16 peripheral DMA (PDCA) channels
• Peripherals
– USB 2.0 Device and Embedded Host: 12 Mbps, up to 8 bidirectional Endpoints and Multi-packet Ping-pong Mode. On-
Chip Transceiver
– Liquid Crystal Display (LCD) Module with Capacity up to 40 Segments and up to 4 Common Terminals
– One USART with ISO7816, IrDA®, RS-485, SPI, Manchester and LIN Mode
– Three USART with SPI Mode
– One PicoUART for extended UART wake-up capabilities in all sleep modes
– Windowed Watchdog Timer (WDT)
– Asynchronous Timer (AST) with Real-time Clock Capability, Counter or Calendar Mode Supported
– Frequency Meter (FREQM) for Accurate Measuring of Clock Frequency
– Six 16-bit Timer/Counter (TC) Channels with capture, waveform, compare and PWM mode
– One Master/Slave Serial Peripheral Interface (SPI) with Chip Select Signals
– Four Master and Two Slave Two-wire Interfaces (TWI), up to 3.4Mbit/s I2C-compatible
– One Advanced Encryption System (AES) with 128-bit key length
– One 16-channel ADC 300Ksps (ADC) with up to 12 Bits Resolution
– One DAC 500Ksps (DACC) with up to 10 Bits Resolution
– Four Analog Comparators (ACIFC) with Optional Window Detection
– Capacitive Touch Module (CATB) supporting up to 32 buttons
– Audio Bitstream DAC (ABDACB) Suitable for Stereo Audio
– Inter-IC Sound (IISC) Controller, Compliant with Inter-IC Sound (I2S) Specification
– Peripheral Event System for Direct Peripheral to Peripheral Communication
– 32-bit Cyclic Redundancy Check Calculation Unit (CRCCU)
– Random generator (TRNG)
– Parallel Capture Module (PARC)
– Glue Logic Controller (GLOC)
• I/O
– Up to 75 I/O lines with external interrupt capability (edge or level sensitivity), debouncing, glitch filtering and slew-rate
control
– Up to Six High-drive I/O Pins
• Single 1.68-3.6V Power Supply
• Packages
– 100-lead LQFP, 14 x 14 mm, pitch 0.5 mm/100-ball VFBGA, 7x7 mm, pitch 0.65 mm
– 64-lead LQFP, 10 x 10 mm, pitch 0.5 mm/64-pad QFN 9x9 mm, pitch 0.5 mm
– 64-ball WLCSP, 4,314x4,434 mm, pitch 0.5 mm for SAM4LC4/2 and SAM4LS4/2 series
– 64-ball WLCSP, 5,270x5,194 mm, pitch 0.5 mm for SAM4LC8 and SAM4LS8 series
– 48-lead LQFP, 7 x 7 mm, pitch 0.5 mm/48-pad QFN 7x7 mm, pitch 0.5 mm
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1. Description
Atmel's SAM4L series is a member of a family of Flash microcontrollers based on the high per-
formance 32-bit ARM Cortex-M4 RISC processor running at frequencies up to 48MHz.
The processor implements a Memory Protection Unit (MPU) and a fast and flexible interrupt con-
troller for supporting modern and real-time operating systems.
The ATSAM4L8/L4/L2 embeds state-of-the-art picoPower technology for ultra-low power con-
sumption. Combined power control techniques are used to bring active current consumption
down to 90µA/MHz. The device allows a wide range of options between functionality and power
consumption, giving the user the ability to reach the lowest possible power consumption with the
feature set required for the application. On-chip regulator improves power efficiency when used
in swichting mode with an external inductor or can be used in linear mode if application is noise
sensitive.
The ATSAM4L8/L4/L2 supports 4 power saving strategies. The SLEEP mode put the CPU in
idle mode and offers different sub-modes which automatically switch off/on bus clocks, PLL,
oscillators. The WAIT and RETENTION modes provide full logic and RAM retention, associated
with fast wake-up capability (<1.5µs) and a very low consumption of, respectively, 3 µA and 1.5
µA. In addition, WAIT mode supports SleepWalking features. In BACKUP mode, CPU, peripher-
als and RAM are powered off and, while consuming less than 0.5µA, the device is able to wake-
up from external interrupts.
The ATSAM4L8/L4/L2 incorporates on-chip Flash tightly coupled to a low power cache
(LPCACHE) for active consumption optimization and SRAM memories for fast access.
The LCD controller is intended for monochrome passive liquid crystal display (LCD) with up to 4
Common terminals and up to 40 Segments terminals. Dedicated Low Power Waveform, Con-
trast Control, Extended Interrupt Mode, Selectable Frame Frequency and Blink functionality are
supported to offload the CPU, reduce interrupts and reduce power consumption. The controller
includes integrated LCD buffers and integrated power supply voltage.
The low-power and high performance capacitive touch module (CATB) is introduced to meet the
demand for a low power capacitive touch solution that could be used to handle buttons, sliders
and wheels. The CATB provides excellent signal performance, as well as autonomous touch
and proximity detection for up to 32 sensors. This solution includes an advanced sequencer in
addition to an hardware filtering unit.
The Advanced Encryption Standard module (AESA) is compliant with the FIPS (Federal Infor-
mation Processing Standard) Publication 197, Advanced Encryption Standard (AES), which
specifies a symmetric block cipher that is used to encrypt and decrypt electronic data. Encryp-
tion is the transformation of a usable message, called the plaintext, into an unreadable form,
called the ciphertext. On the other hand, decryption is the transformation that recovers the plain-
text from the ciphertext. AESA supports 128 bits cryptographic key sizes.
The Peripheral Direct Memory Access (DMA) controller enables data transfers between periph-
erals and memories without processor involvement. The Peripheral DMA controller drastically
reduces processing overhead when transferring continuous and large data streams.
The Peripheral Event System (PES) allows peripherals to receive, react to, and send peripheral
events without CPU intervention. Asynchronous interrupts allow advanced peripheral operation
in low power modes.
The Power Manager (PM) improves design flexibility and security. The Power Manager supports
SleepWalking functionality, by which a module can be selectively activated based on peripheral
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42023HS–SAM–11/2016
ATSAM4L8/L4/L2
events, even in sleep modes where the module clock is stopped. Power monitoring is supported
by on-chip Power-on Reset (POR18, POR33), Brown-out Detectors (BOD18, BOD33). The
device features several oscillators, such as Phase Locked Loop (PLL), Digital Frequency
Locked Loop (DFLL), Oscillator 0 (OSC0), Internal RC 4,8,12MHz oscillator (RCFAST), system
RC oscillator (RCSYS), Internal RC 80MHz, Internal 32kHz RC and 32kHz Crystal Oscillator.
Either of these oscillators can be used as source for the system clock. The DFLL is a program-
mable internal oscillator from 40 to 150MHz. It can be tuned to a high accuracy if an accurate
reference clock is running, e.g. the 32kHz crystal oscillator.
The Watchdog Timer (WDT) will reset the device unless it is periodically serviced by the soft-
ware. This allows the device to recover from a condition that has caused the system to be
unstable.
The Asynchronous Timer (AST) combined with the 32kHz crystal oscillator supports powerful
real-time clock capabilities, with a maximum timeout of up to 136 years. The AST can operate in
counter or calendar mode.
The Frequency Meter (FREQM) allows accurate measuring of a clock frequency by comparing it
to a known reference clock.
The Full-speed USB 2.0 device and embedded host interface (USBC) supports several USB
classes at the same time utilizing the rich end-point configuration.
The device includes six identical 16-bit Timer/Counter (TC) channels. Each channel can be inde-
pendently programmed to perform frequency measurement, event counting, interval
measurement, pulse generation, delay timing, and pulse width modulation.
The ATSAM4L8/L4/L2 also features many communication interfaces, like USART, SPI, or TWI,
for communication intensive applications. The USART supports different communication modes,
like SPI Mode and LIN Mode.
A general purpose 16-channel ADC is provided, as well as four analog comparators (ACIFC).
The ADC can operate in 12-bit mode at full speed. The analog comparators can be paired to
detect when the sensing voltage is within or outside the defined reference window.
Atmel offers the QTouch Library for embedding capacitive touch buttons, sliders, and wheels
functionality. The patented charge-transfer signal acquisition offers robust sensing and includes
fully debounced reporting of touch keys as well as Adjacent Key Suppression® (AKS®) technol-
ogy for unambiguous detection of key events. The easy-to-use QTouch Suite toolchain allows
you to explore, develop, and debug your own touch applications.
The Audio Bitstream DAC (ABDACB) converts a 16-bit sample value to a digital bitstream with
an average value proportional to the sample value. Two channels are supported, making the
ABDAC particularly suitable for stereo audio.
The Inter-IC Sound Controller (IISC) provides a 5-bit wide, bidirectional, synchronous, digital
audio link with external audio devices. The controller is compliant with the Inter-IC Sound (I2S)
bus specification.
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42023HS–SAM–11/2016
ATSAM4L8/L4/L2
2. Overview
2.1
Block Diagram
Figure 2-1. Block Diagram
System
TAP
In-Circuit
Emulator
ARM Cortex-M4 Processor
Fmax 48 MHz
TCK
TDO
TDI
JTAG &
Serial Wire
TMS
System
Management
Access Port
MEMORY PROTECTION UNIT
Instruction/
Data
System
M
M
HRAM
CONTROLLER
64/32 KB
RAM
M
S
S
128-bit
AES
HIGH SPEED
BUS MATRIX
S
FLASH
CONTROLLER
LOW POWER CACHE
512/256/128 KB
FLASH
DP
S
S
USBC
8 EndPoints
S
S
S
M
CONFIGURATION
REGISTERS BUS
PERIPHERAL
DMA
CONTROLLER
VDDIN
VDDOUT
VDDCORE
HSB-PB
BRIDGE B
HSB-PB
BRIDGE D
HSB-PB
BRIDGE C
HSB-PB
BRIDGE A
LDO/
SWITCHING
REGULATOR
USART0
USART1
USART2
USART3
RXD
TXD
CLK
BACKUP
SYSTEM
CONTROL
INTERFACE
RC32K
RTS, CTS
XIN32
XOUT32
SCK
MISO, MOSI
NPCS[3..0]
OSC32
SPI
BACKUP
POWER MANAGER
TWI MASTER 0
TWI MASTER 1
TWI MASTER 2
TWI MASTER 3
TWCK
TWD
BACKUP
REGISTERS
PA
PB
PC
TWCK
TWD
TWI SLAVE 0
TWI SLAVE 1
EXTINT[8..1]
NMI
EXTERNAL INTERRUPT
CONTROLLER
SEG[39..0]
COM[3..0]
ASYNCHRONOUS
TIMER
LCD
CONTROLLER
BIASL,BIASH
CAPH,CAPL
WATCHDOG
TIMER
ISCK
IWS
ISDI
ISDO
IMCK
PA
PB
PC
INTER-IC SOUND
CONTROLLER
RXD
PICOUART
CLK
BACKUP DOMAIN
POWER MANAGER
AUDIO BITSTREAM
DAC
ABDAC[1..0]
ABDACN[1..0]
RESETN
16-CHANNEL
12-bit ADC
INTERFACE
TRIGGER
CLOCK
CONTROLLER
AD[14..0]
ADVREFP
RESET
SLEEP
CONTROLLER
CONTROLLER
10-bit DAC
DACOUT
INTERFACE
GCLK_IN[1:0]
GCLK[3:0]
SENSE[69..0]
DIS
CAPACITIVE TOUCH
MODULE
RCSYS
RCFAST
RC80M
OSC0
DFLL
PCCK
PCEN1,PCEN2
PARALLEL CAPTURE
CONTROLLER
SYSTEM CONTROL
INTERFACE
PCDATA[7..0]
XIN0
XOUT0
IN[7..0]
GLUE LOGIC
CONTROLLER
GENERIC
CLOCK
OUT[1..0]
CLK[2..0]
B[2..0]
PLL
TIMER/COUNTER 0
TIMER/COUNTER 1
A[2..0]
FREQUENCY METER
ACAP[3..0]
ACAN[3..0]
ACREFN
AC INTERFACE
PAD_EVT[3..0]
TRUE RANDOM
GENERATOR
32-BIT CRC
CALCULATION UNIT
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42023HS–SAM–11/2016
ATSAM4L8/L4/L2
2.2
Configuration Summary
Table 2-1.
Feature
Sub Series Summary
ATSAM4LC
Yes
ATSAM4LS
No
SEGMENT LCD
AESA
Yes
No
USB
Device + Host
Device Only
Table 2-2.
Feature
ATSAM4LC Configuration Summary
ATSAM4LC8/4/2C
ATSAM4LC8/4/2B
ATSAM4LC8/4/2A
Number of Pins
Max Frequency
Flash
100
64
48MHz
512/256/128KB
64/32/32KB
4x23
48
SRAM
SEGMENT LCD
GPIO
4x40
75
4x13
27
43
High-drive pins
External Interrupts
6
3
1
8 + 1 NMI
1 Master + 1
Master/Slave
TWI
2 Masters + 2 Masters/Slaves
4
3 in LC sub series
4 in LS sub series
USART
PICOUART
1
0
Peripheral DMA Channels
AESA
16
1
Peripheral Event System
SPI
1
1
Asynchronous Timers
Timer/Counter Channels
Parallel Capture Inputs
Frequency Meter
Watchdog Timer
Power Manager
Glue Logic LUT
1
6
8
1
1
1
2
3
1
6
42023HS–SAM–11/2016
ATSAM4L8/L4/L2
Table 2-2.
Feature
ATSAM4LC Configuration Summary
ATSAM4LC8/4/2C
ATSAM4LC8/4/2B
ATSAM4LC8/4/2A
Digital Frequency Locked Loop 20-150MHz (DFLL)
Phase Locked Loop 48-240MHz (PLL)
Crystal Oscillator 0.6-30MHz (OSC0)
Crystal Oscillator 32kHz (OSC32K)
RC Oscillator 80MHz (RC80M)
Oscillators
RC Oscillator 4,8,12MHz (RCFAST)
RC Oscillator 115kHz (RCSYS)
RC Oscillator 32kHz (RC32K)
ADC
15-channel
7-channel
3-channel
DAC
1-channel
Analog Comparators
CATB Sensors
USB
4
2
32
1
1
32
26
Audio Bitstream DAC
IIS Controller
1
1
TQFP/QFN/
WLCSP
Packages
.
TQFP/VFBGA
TQFP/QFN
Table 2-3.
Feature
ATSAM4LS Configuration Summary
ATSAM4LS8/4/2C
ATSAM4LS8/4/2B
ATSAM4LS8/4/2A
Number of Pins
Max Frequency
Flash
100
64
48MHz
512/256/128KB
64/32/32KB
NA
48
SRAM
SEGMENT LCD
GPIO
80
6
48
32
1
High-drive pins
External Interrupts
3
8 + 1 NMI
1 Master + 1
Master/Slave
TWI
2 Masters + 2 Masters/Slaves
4
3 in LC sub series
4 in LS sub series
USART
PICOUART
1
0
Peripheral DMA Channels
AESA
16
NA
1
Peripheral Event System
SPI
1
Asynchronous Timers
1
7
42023HS–SAM–11/2016
ATSAM4L8/L4/L2
Table 2-3.
Feature
ATSAM4LS Configuration Summary
ATSAM4LS8/4/2C
ATSAM4LS8/4/2B
ATSAM4LS8/4/2A
Timer/Counter Channels
Parallel Capture Inputs
Frequency Meter
Watchdog Timer
6
3
8
1
1
1
Power Manager
Glue Logic LUT
2
1
Digital Frequency Locked Loop 20-150MHz (DFLL)
Phase Locked Loop 48-240MHz (PLL)
Crystal Oscillator 0.6-30MHz (OSC0)
Crystal Oscillator 32kHz (OSC32K)
RC Oscillator 80MHz (RC80M)
Oscillators
RC Oscillator 4,8,12MHz (RCFAST)
RC Oscillator 115kHz (RCSYS)
RC Oscillator 32kHz (RC32K)
ADC
15-channel
7-channel
3-channel
DAC
1-channel
Analog Comparators
CATB Sensors
USB
4
2
32
1
1
32
26
Audio Bitstream DAC
IIS Controller
1
1
TQFP/QFN/
WLCSP
Packages
TQFP/VFBGA
TQFP/QFN
8
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ATSAM4L8/L4/L2
3. Package and Pinout
3.1
Package
The device pins are multiplexed with peripheral functions as described in Section 3.2 ”Peripheral
Multiplexing on I/O lines” on page 19.
3.1.1
ATSAM4LCx Pinout
Figure 3-1. ATSAM4LC TQFP100 Pinout
PA18
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
PA12
PA11
PA10
PA09
PB07
PB06
PA08
PC14
PC13
PC12
PC11
PC10
PC09
PC08
PC07
VDDANA
ADVREFP
GNDANA
ADVREFN
PA07
PA06
PB05
PB04
XOUT32
XIN32
PA19
PA20
PC24
PC25
PC26
PC27
PC28
PC29
PC30
PC31
VDDIO
VDDIO
PB12
PB13
PA21
PA22
PB14
PB15
PA23
PA24
VDDIO
PA25
PA26
GND
9
42023HS–SAM–11/2016
ATSAM4L8/L4/L2
Figure 3-2. ATSAM4LC VFBGA100 Pinout
2 3
5 6 7 8 9 10
1
4
VDD
CORE
VDDOUT
RESET_N
PC04
PA05
PA04
GND
VDDIN
PA02
PC03
PC02
PB14
PB12
PC29
PB09
PC20
PA16
PA14
VDDIO
PA01
PC01
PB15
PB13
PC30
PB10
PC23
PC22
PC21
GND
PA00
PA26
PA25
PA21
PC31
PC26
PC25
PC24
PB11
PC00
A
B
C
D
E
F
PB05
XIN32
PA03
TCK
PB03
PC10
PC11
PC13
PC19
PC17
BIASL
GND
PC06
GND
PB04 XOUT32 PA06
PC05
PA23
VDDIO
PC27
PB08
PA17
PC16
VDDIO
PA24
PA22
VDDIO
PC28
PA20
PA19
PA18
AD
VREFN
GNDANA
PA07
PC08
PC12
PB06
PA11
PB00
BIASH
PB01
AD
VREFP
VDDANA
PB02
PC09
PC14
PB07
CAPL
CAPH
PC07
PA08
PA10
PA12
VLCD
PA09
PA15
G
H
J
PA13
PC15
VLCDIN PC18
K
10
42023HS–SAM–11/2016
ATSAM4L8/L4/L2
Figure 3-3. ATSAM4LC WLCSP64 Pinout
2 3
5 6 7 8
1
4
AD
VREFP
GNDANA
VDDANA
PB04
PA09
PB06
PA07
PB12
PB13
PA22
PA01
PA21
CAPL
PA10
PB07
PB08
PB09
PB10
PA19
VDDIO
CAPH
PA11
PA13
PA14
PA15
PA12
VLCD
BIASH
BIASL
GND
A
B
C
D
E
F
PB03
VDDIN
VDDOUT
GND
XIN32 XOUT32 PA08
PB01
PB00
PA03
TCK
PA05
PA04
PB02
PA02
PA24
PA23
PA06
PB05
RESET_N
PB14
VDD
CORE
PA16 VLCDIN
GND
PA26
PA25
PA00
PA18
PA20
PA17
PB11
G
H
VDDIO
PB15
11
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ATSAM4L8/L4/L2
Figure 3-4. ATSAM4LC TQFP64/QFN64 Pinout
PA18
PA19
PA20
VDDIO
PB12
PB13
PA21
PA22
PB14
PB15
PA23
PA24
VDDIO
PA25
PA26
GND
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PA12
PA11
PA10
PA09
PB07
PB06
PA08
VDDANA
ADVREFP
GNDANA
PA07
PA06
PB05
PB04
XOUT32
XIN32
12
42023HS–SAM–11/2016
ATSAM4L8/L4/L2
Figure 3-5. ATSAM4LC TQFP48/QFN48 Pinout
PA18
PA19
PA20
VDDIO
PA21
PA22
PA23
PA24
VDDIO
PA25
PA26
GND
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
PA12
PA11
PA10
PA09
PA08
VDDANA
ADVREFP
GNDANA
PA07
PA06
XOUT32
XIN32
13
42023HS–SAM–11/2016
ATSAM4L8/L4/L2
3.1.2
ATSAM4LSx Pinout
Figure 3-6. ATSAM4LS TQFP100 Pinout
PA18
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
PA12
PA11
PA10
PA09
PB07
PB06
PA08
PC14
PC13
PC12
PC11
PC10
PC09
PC08
PC07
VDDANA
ADVREFP
GNDANA
ADVREFN
PA07
PA06
PB05
PB04
XOUT32
XIN32
PA19
PA20
PC24
PC25
PC26
PC27
PC28
PC29
PC30
PC31
VDDIO
VDDIO
PB12
PB13
PA21
PA22
PB14
PB15
PA23
PA24
VDDIO
PA25
PA26
GND
14
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ATSAM4L8/L4/L2
Figure 3-7. ATSAM4LS VFBGA100 Pinout
2 3
5 6 7 8 9 10
1
4
VDD
CORE
VDDOUT
RESET_N
PC04
PB01
PA05
PA04
GND
VDDIN
PA02
PC03
PC02
PB14
PB12
PC29
PB09
PC20
PA16
PA14
VDDIO
PA01
PC01
PB15
PB13
PC30
PB10
PC23
PC22
PC21
GND
PA00
PA26
PA25
PA21
PC31
PC26
PC25
PC24
PB11
PC00
A
B
C
D
E
F
PB05
XIN32
PA03
TCK
PB03
PC10
PC11
PC13
PC19
PC17
VDDIO
PA30
PC06
GND
PB04 XOUT32 PA06
PC05
PA23
VDDIO
PC27
PB08
PA17
PC16
PC18
VDDIO
PA24
PA22
VDDIO
PC28
PA20
PA19
PA18
AD
VREFN
GNDANA
PA07
PC08
PC12
PB06
PA11
PB00
GND
AD
VREFP
VDDANA
PB02
PC09
PC14
PB07
PA28
PA27
PC07
PA08
PA10
PA12
PA29
PA09
PA15
G
H
J
PA13
PC15
PA31
K
15
42023HS–SAM–11/2016
ATSAM4L8/L4/L2
Figure 3-8. ATSAM4LS WLCSP64 Pinout
2 3
5 6 7 8
1
4
AD
VREFP
GNDANA
VDDANA
PB04
PA09
PB06
PA07
PB12
PB13
PA22
PA01
PA21
PA28
PA10
PB07
PB08
PB09
PB10
PA19
VDDIO
PA27
PA11
PA13
PA14
PA15
PA16
PA18
PA20
PA12
PA29
GND
A
B
C
D
E
F
PB03
VDDIN
VDDOUT
GND
XIN32 XOUT32 PA08
PB01
PB00
PA03
TCK
PA05
PA04
PB02
PA02
PA24
PA23
PA06
PB05
VDDIO
PA30
PA31
PA17
PB11
RESET_N
PB14
VDD
CORE
GND
PA26
PA25
PA00
G
H
VDDIO
PB15
16
42023HS–SAM–11/2016
ATSAM4L8/L4/L2
Figure 3-9. ATSAM4LS TQFP64/QFN64 Pinout
PA18
PA19
PA20
VDDIO
PB12
PB13
PA21
PA22
PB14
PB15
PA23
PA24
VDDIO
PA25
PA26
GND
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PA12
PA11
PA10
PA09
PB07
PB06
PA08
VDDANA
ADVREFP
GNDANA
PA07
PA06
PB05
PB04
XOUT32
XIN32
17
42023HS–SAM–11/2016
ATSAM4L8/L4/L2
Figure 3-10. ATSAM4LS TQFP48/QFN48 Pinout
PA18
PA19
PA20
VDDIO
PA21
PA22
PA23
PA24
VDDIO
PA25
PA26
GND
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
PA12
PA11
PA10
PA09
PA08
VDDANA
ADVREFP
GNDANA
PA07
PA06
XOUT32
XIN32
See Section 3.3 ”Signals Description” on page 31 for a description of the various peripheral
signals.
Refer to ”Electrical Characteristics” on page 99 for a description of the electrical properties of the
pin types used.
18
42023HS–SAM–11/2016
ATSAM4L8/L4/L2
3.2
Peripheral Multiplexing on I/O lines
3.2.1
Multiplexed Signals
Each GPIO line can be assigned to one of the peripheral functions. The following tables (Section
3-1 ”100-pin GPIO Controller Function Multiplexing” on page 19 to Section 3-4 ”48-pin GPIO
Controller Function Multiplexing” on page 28) describes the peripheral signals multiplexed to the
GPIO lines.
Peripheral functions that are not relevant in some parts of the family are grey-shaded.
For description of differents Supply voltage source, refer to the Section 6. ”Power and Startup
Considerations” on page 46.
Table 3-1.
100-pin GPIO Controller Function Multiplexing (Sheet 1 of 4)
GPIO Functions
QFN VFBGA QFN VFBGA
A
B
C
D
E
F
G
5
6
B9
B8
5
6
B9
B8
PA00
PA01
0
1
VDDIO
VDDIO
S C I F
GCLK0
S P I
NPCS0
C AT B
DIS
12
19
24
25
30
31
44
47
48
49
50
63
64
65
A7
B3
A2
A1
C3
D3
G2
F5
H2
H3
J2
12
19
24
25
30
31
44
47
48
49
50
63
64
65
A7
B3
A2
A1
C3
D3
G2
F5
H2
H3
J2
PA02
PA03
PA04
PA05
PA06
PA07
PA08
PA09
PA10
PA11
PA12
PA13
PA14
PA15
2
3
VDDIN
VDDIN
VDDANA
VDDANA
VDDANA
VDDANA
LCDA
S P I
MISO
A D C I F E
AD0
U S A R T 0
CLK
E I C
EXTINT2
G L O C
IN1
C AT B
SENSE0
4
A D C I F E
AD1
U S A R T 0
RXD
E I C
EXTINT3
G L O C
IN2
A D C I F E
TRIGGER
C AT B
SENSE1
5
DACC
VOUT
U S A R T 0
RTS
E I C
EXTINT1
G L O C
IN0
A C I F C
ACAN0
C AT B
SENSE2
6
A D C I F E
AD2
U S A R T 0
TXD
E I C
EXTINT4
G L O C
IN3
A C I F C
ACAP0
C AT B
SENSE3
7
U S A R T 0
RTS
T C 0
A0
PEVC
PAD EVT0
G L O C
OUT0
LCDCA
SEG23
C AT B
SENSE4
8
U S A R T 0
CTS
T C 0
B0
PEVC
PA R C
LCDCA
COM3
C AT B
SENSE5
9
LCDA
PAD EVT1 PCDATA0
PEVC PA R C
PAD EVT2 PCDATA1
PEVC PA R C
U S A R T 0
CLK
T C 0
A1
LCDCA
COM2
C AT B
SENSE6
10
11
12
13
14
15
LCDA
U S A R T 0
RXD
T C 0
B1
LCDCA
COM1
C AT B
SENSE7
LCDA
PAD EVT3 PCDATA2
U S A R T 0
TXD
T C 0
A2
PA R C
PCDATA3
LCDCA
COM0
C AT B
DIS
LCDA
U S A R T 1
RTS
T C 0
B2
S P I
NPCS1
PA R C
PCDATA4
LCDCA
SEG5
C AT B
SENSE8
H5
K7
G5
H5
K7
G5
LCDA
U S A R T 1
CLK
T C 0
CLK0
S P I
NPCS2
PA R C
PCDATA5
LCDCA
SEG6
C AT B
SENSE9
LCDA
U S A R T 1
RXD
T C 0
CLK1
S P I
NPCS3
PA R C
PCDATA6
LCDCA
SEG7
C AT B
SENSE10
LCDA
19
42023HS–SAM–11/2016
ATSAM4L8/L4/L2
Table 3-1.
100-pin GPIO Controller Function Multiplexing (Sheet 2 of 4)
GPIO Functions
QFN VFBGA QFN VFBGA
A
B
C
D
E
F
G
U S A R T 1
TXD
T C 0
CLK2
E I C
PA R C
LCDCA
SEG8
C AT B
SENSE11
66
67
76
77
78
91
92
95
96
98
99
J7
H6
66
67
76
77
78
91
92
95
96
98
99
51
52
53
56
57
20
21
22
23
28
29
45
46
J7
H6
K10
J10
H10
E9
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
PB00
PB01
PB02
PB03
PB04
PB05
PB06
PB07
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
LCDA
LCDA
LCDA
LCDA
LCDA
LCDC
LCDC
LCDC
LCDC
VDDIO
VDDIO
LCDA
LCDA
LCDA
LCDA
LCDA
VDDIN
VDDIN
EXTINT1 PCDATA7
U S A R T 2
RTS
ABDACB
DAC0
E I C
EXTINT2
PA R C
PCCK
LCDCA
SEG9
C AT B
SENSE12
U S A R T 2
CLK
ABDACB
DACN0
E I C
EXTINT3
PA R C
PCEN1
LCDCA
SEG18
C AT B
SENSE13
K10
J10
H10
E9
U S A R T 2
RXD
ABDACB
DAC1
E I C
EXTINT4
PA R C
PCEN2
S C I F
GCLK0
LCDCA
SEG19
C AT B
SENSE14
U S A R T 2
TXD
ABDACB
DACN1
E I C
EXTINT5
G L O C
IN0
S C I F
GCLK1
LCDCA
SEG20
C AT B
SENSE15
S P I
MISO
U S A R T 1
CTS
E I C
EXTINT6
G L O C
IN1
T W I M 2
TWD
LCDCA
SEG34
C AT B
SENSE16
S P I
MOSI
U S A R T 2
CTS
E I C
EXTINT7
G L O C
IN2
T W I M 2
TWCK
LCDCA
SEG35
C AT B
SENSE17
E10
D6
E10
D6
D10
D9
C9
K1
J1
S P I
SCK
T W I M S 0
TWD
E I C
EXTINT8
G L O C
IN3
S C I F
GCLK IN0
LCDCA
SEG38
C AT B
DIS
S P I
NPCS0
T W I M S 0
TWCK
G L O C
OUT0
S C I F
GCLK IN1
LCDCA
SEG39
C AT B
SENSE18
D10
D9
U S B C
DM
U S A R T 2
RXD
C AT B
SENSE19
U S B C
DP
U S A R T 2
TXD
C AT B
SENSE20
C9
S P I
MISO
I I S C
ISCK
ABDACB
DAC0
G L O C
IN4
U S A R T 3
RTS
C AT B
SENSE0
S P I
MOSI
I I S C
ISDI
ABDACB
DACN0
G L O C
IN5
U S A R T 3
CTS
C AT B
SENSE1
S P I
SCK
I I S C
IWS
ABDACB
DAC1
G L O C
IN6
U S A R T 3
CLK
C AT B
SENSE2
K2
K4
K5
J3
S P I
NPCS0
I I S C
ISDO
ABDACB
DACN1
G L O C
IN7
U S A R T 3
RXD
C AT B
SENSE3
S P I
NPCS1
I I S C
IMCK
ABDACB
CLK
G L O C
OUT1
U S A R T 3
TXD
C AT B
DIS
T W I M S 1
TWD
U S A R T 0
RXD
C AT B
SENSE21
20
21
22
23
28
29
45
46
J3
D5
E5
C4
C1
B1
G3
H1
T W I M S 1
TWCK
U S A R T 0
TXD
E I C
EXTINT0
C AT B
SENSE22
D5
E5
A D C I F E
AD3
U S A R T 1 ABDACB
RTS DAC0
I I S C
ISCK
A C I F C
ACBN0
C AT B
SENSE23
34 VDDANA
35 VDDANA
36 VDDANA
37 VDDANA
A D C I F E
AD4
U S A R T 1 ABDACB
CLK DACN0
I I S C
ISDI
A C I F C
ACBP0
C AT B
DIS
C4
C1
B1
G3
H1
A D C I F E
AD5
U S A R T 1 ABDACB
RXD DAC1
I I S C
ISDO
DACC
EXT TRIG0
C AT B
SENSE24
A D C I F E
AD6
U S A R T 1 ABDACB
TXD
I I S C
IMCK
C AT B
SENSE25
DACN1
U S A R T 3
RTS
G L O C
IN4
I I S C
IWS
LCDCA
SEG22
C AT B
SENSE26
38
39
LCDA
LCDA
U S A R T 3
CTS
G L O C
IN5
T C 0
A0
LCDCA
SEG21
C AT B
SENSE27
20
42023HS–SAM–11/2016
ATSAM4L8/L4/L2
Table 3-1.
100-pin GPIO Controller Function Multiplexing (Sheet 3 of 4)
GPIO Functions
QFN VFBGA QFN VFBGA
A
B
C
D
E
F
G
U S A R T 3
CLK
G L O C
IN6
T C 0
B0
LCDCA
SEG14
C AT B
SENSE28
72
73
74
75
89
90
93
94
1
G6
G7
G8
K9
E7
E8
D7
D8
A10
C8
C7
B7
C5
C6
B6
F2
72
73
74
75
89
90
93
94
1
G6
G7
G8
K9
E7
E8
D7
D8
A10
C8
C7
B7
C5
C6
B6
F2
PB08
PB09
PB10
PB11
PB12
PB13
PB14
PB15
PC00
PC01
PC02
PC03
PC04
PC05
PC06
PC07
PC08
PC09
PC10
PC11
PC12
PC13
PC14
PC15
40
41
42
43
44
45
46
47
64
65
66
67
68
69
70
LCDA
LCDA
LCDA
LCDA
LCDC
LCDC
LCDC
LCDC
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
U S A R T 3
RXD
P E V C
PAD EVT2
G L O C
IN7
T C 0
A1
LCDCA
SEG15
C AT B
SENSE29
U S A R T 3
TXD
P E V C
PAD EVT3
G L O C
OUT1
T C 0
B1
S C I F
GCLK0
LCDCA
SEG16
C AT B
SENSE30
U S A R T 0
CTS
S P I
NPCS2
T C 0
A2
S C I F
GCLK1
LCDCA
SEG17
C AT B
SENSE31
U S A R T 0
RTS
S P I
NPCS3
PEVC
PAD EVT0
T C 0
B2
S C I F
GCLK2
LCDCA
SEG32
C AT B
DIS
U S A R T 0
CLK
S P I
NPCS1
PEVC
PAD EVT1
T C 0
CLK0
S C I F
GCLK3
LCDCA
SEG33
C AT B
SENSE0
U S A R T 0
RXD
S P I
MISO
T W I M 3
TWD
T C 0
CLK1
S C I F
GCLK IN0
LCDCA
SEG36
C AT B
SENSE1
U S A R T 0
TXD
S P I
MOSI
T W I M 3
TWCK
T C 0
CLK2
S C I F
GCLK IN1
LCDCA
SEG37
C AT B
SENSE2
S P I
NPCS2
U S A R T 0
CLK
T C 1
A0
C AT B
SENSE3
S P I
NPCS3
U S A R T 0
RTS
T C 1
B0
C AT B
SENSE4
2
2
S P I
NPCS1
U S A R T 0
CTS
U S A R T 0
RXD
T C 1
A1
C AT B
SENSE5
3
3
S P I
NPCS0
E I C
EXTINT5
U S A R T 0
TXD
T C 1
B1
C AT B
SENSE6
4
4
S P I
MISO
E I C
EXTINT6
T C 1
A2
C AT B
SENSE7
9
9
S P I
MOSI
E I C
EXTINT7
T C 1
B2
C AT B
DIS
10
11
36
37
38
39
40
41
42
43
58
10
11
36
37
38
39
40
41
42
43
58
S P I
SCK
E I C
EXTINT8
T C 1
CLK0
C AT B
SENSE8
A D C I F E
AD7
U S A R T 2
RTS
PEVC
PAD EVT0
T C 1
CLK1
C AT B
SENSE9
71 VDDANA
72 VDDANA
73 VDDANA
74 VDDANA
75 VDDANA
76 VDDANA
77 VDDANA
78 VDDANA
A D C I F E
AD8
U S A R T 2
CLK
PEVC
PAD EVT1
T C 1
CLK2
U S A R T 2
CTS
C AT B
SENSE10
E3
F1
E3
F1
A D C I F E
AD9
U S A R T 3 ABDACB
RXD DAC0
I I S C
ISCK
A C I F C
ACAN1
C AT B
SENSE11
A D C I F E
AD10
U S A R T 3 ABDACB
I I S C
ISDI
A C I F C
ACAP1
C AT B
SENSE12
D4
E4
F3
D4
E4
F3
TXD
DACN0
A D C I F E
AD11
U S A R T 2
RXD
PEVC
PAD EVT2
C AT B
SENSE13
A D C I F E
AD12
U S A R T 2 ABDACB
TXD CLK
I I S C
IWS
C AT B
SENSE14
A D C I F E
AD13
U S A R T 3 ABDACB
RTS DAC1
I I S C
ISDO
A C I F C
ACBN1
C AT B
SENSE15
F4
F4
A D C I F E
AD14
U S A R T 3 ABDACB
CLK DACN1
I I S C
IMCK
A C I F C
ACBP1
C AT B
DIS
G1
J5
G1
J5
T C 1
A0
G L O C
IN4
LCDCA
SEG0
C AT B
SENSE16
79
LCDA
21
42023HS–SAM–11/2016
ATSAM4L8/L4/L2
Table 3-1.
100-pin GPIO Controller Function Multiplexing (Sheet 4 of 4)
GPIO Functions
QFN VFBGA QFN VFBGA
A
B
C
D
E
F
G
T C 1
B0
G L O C
IN5
LCDCA
SEG1
C AT B
SENSE17
59
60
61
62
68
69
70
71
79
80
81
82
83
84
85
86
J6
H4
K6
G4
H7
K8
J8
59
60
61
62
68
69
70
71
79
80
81
82
83
84
85
86
J6
H4
K6
G4
H7
K8
J8
PC16
PC17
PC18
PC19
PC20
PC21
PC22
PC23
PC24
PC25
PC26
PC27
PC28
PC29
PC30
PC31
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
LCDA
LCDA
LCDA
LCDA
LCDA
LCDA
LCDA
LCDA
LCDB
LCDB
LCDB
LCDB
LCDB
LCDB
LCDB
LCDB
T C 1
A1
G L O C
IN6
LCDCA
SEG2
C AT B
SENSE18
T C 1
B1
G L O C
IN7
LCDCA
SEG3
C AT B
SENSE19
T C 1
A2
G L O C
OUT1
LCDCA
SEG4
C AT B
SENSE20
T C 1
B2
LCDCA
SEG10
C AT B
SENSE21
T C 1
CLK0
PA R C
PCCK
LCDCA
SEG11
C AT B
SENSE22
T C 1
CLK1
PA R C
PCEN1
LCDCA
SEG12
C AT B
SENSE23
T C 1
CLK2
PA R C
PCEN2
LCDCA
SEG13
C AT B
DIS
H8
J9
H8
J9
U S A R T 1
RTS
E I C
PEVC
PA R C
LCDCA
SEG24
C AT B
SENSE24
EXTINT1 PAD EVT0 PCDATA0
E I C PEVC PA R C
EXTINT2 PAD EVT1 PCDATA1
E I C PEVC PA R C
EXTINT3 PAD EVT2 PCDATA2
E I C PEVC PA R C
EXTINT4 PAD EVT3 PCDATA3
U S A R T 1
CLK
LCDCA
SEG25
C AT B
SENSE25
H9
G9
F6
H9
G9
F6
U S A R T 1
RXD
S C I F
GCLK0
LCDCA
SEG26
C AT B
SENSE26
U S A R T 1
TXD
S C I F
GCLK1
LCDCA
SEG27
C AT B
SENSE27
U S A R T 3
RXD
S P I
MISO
G L O C
IN4
PA R C
PCDATA4
S C I F
GCLK2
LCDCA
SEG28
C AT B
SENSE28
G10
F7
G10
F7
U S A R T 3
TXD
S P I
MOSI
G L O C
IN5
PA R C
PCDATA5
S C I F
GCLK3
LCDCA
SEG29
C AT B
SENSE29
U S A R T 3
RTS
S P I
SCK
G L O C
IN6
PA R C
S C I F
LCDCA
SEG30
C AT B
SENSE30
F8
F8
PCDATA6 GCLK IN0
PA R C S C I F
PCDATA7 GCLK IN1
U S A R T 3
CLK
S P I
NPCS0
G L O C
OUT1
LCDCA
SEG31
C AT B
SENSE31
F9
F9
Table 3-2.
64-pin GPIO Controller Function Multiplexing (Sheet 1 of 3)
GPIO Functions
QFP QFP
QFN QFN
A
B
C
D
E
F
G
1
2
1
2
PA00
PA01
0
1
VDDIO
VDDIO
S C I F
GCLK0
S P I
NPCS0
C AT B
DIS
3
3
PA02
PA03
2
3
VDDIN
VDDIN
S P I
MISO
10
10
22
42023HS–SAM–11/2016
ATSAM4L8/L4/L2
Table 3-2.
64-pin GPIO Controller Function Multiplexing (Sheet 2 of 3)
GPIO Functions
QFP QFP
QFN QFN
A
B
C
D
E
F
G
A D C I F E
AD0
U S A R T 0
CLK
E I C
EXTINT2
G L O C
IN1
C AT B
SENSE0
15
16
21
22
26
29
30
31
32
40
41
42
43
44
49
50
51
55
56
59
60
62
63
15
16
21
22
26
29
30
31
32
40
41
42
43
44
49
50
51
55
56
59
60
62
63
PA04
PA05
PA06
PA07
PA08
PA09
PA10
PA11
PA12
PA13
PA14
PA15
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
4
VDDANA
VDDANA
VDDANA
VDDANA
LCDA
A D C I F E
AD1
U S A R T 0
RXD
E I C
EXTINT3
G L O C
IN2
ADCIFE
TRIGGER
C AT B
SENSE1
5
D A C C
VOUT
U S A R T 0
RTS
E I C
EXTINT1
G L O C
IN0
A C I F C
ACAN0
C AT B
SENSE2
6
A D C I F E
AD2
U S A R T 0
TXD
E I C
EXTINT4
G L O C
IN3
A C I F C
ACAP0
C AT B
SENSE3
7
U S A R T 0
RTS
T C 0
A0
P E V C
PAD EVT0
G L O C
OUT0
LCDCA
SEG23
C AT B
SENSE4
8
U S A R T 0
CTS
T C 0
B0
P E V C
PARC
LCDCA
COM3
C AT B
SENSE5
9
LCDA
PAD EVT1 PCDATA0
P E V C PARC
PAD EVT2 PCDATA1
P E V C PARC
U S A R T 0
CLK
T C 0
A1
LCDCA
COM2
C AT B
SENSE6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
LCDA
U S A R T 0
RXD
T C 0
B1
LCDCA
COM1
C AT B
SENSE7
LCDA
PAD EVT3 PCDATA2
U S A R T 0
TXD
T C 0
A2
PARC
PCDATA3
LCDCA
COM0
C AT B
DIS
LCDA
U S A R T 1
RTS
T C 0
B2
S P I
NPCS1
PARC
PCDATA4
LCDCA
SEG5
C AT B
SENSE8
LCDA
U S A R T 1
CLK
T C 0
CLK0
S P I
NPCS2
PARC
PCDATA5
LCDCA
SEG6
C AT B
SENSE9
LCDA
U S A R T 1
RXD
T C 0
CLK1
S P I
NPCS3
PARC
PCDATA6
LCDCA
SEG7
C AT B
SENSE10
LCDA
U S A R T 1
TXD
T C 0
CLK2
E I C
PARC
LCDCA
SEG8
C AT B
SENSE11
LCDA
EXTINT1 PCDATA7
U S A R T 2 ABDACB
RTS DAC0
E I C
EXTINT2
PARC
PCCK
LCDCA
SEG9
C AT B
SENSE12
LCDA
U S A R T 2 ABDACB
CLK DACN0
E I C
EXTINT3
PARC
PCEN1
LCDCA
SEG18
C AT B
SENSE13
LCDA
U S A R T 2 ABDACB
RXD DAC1
E I C
EXTINT4
PARC
PCEN2
S C I F
GCLK0
LCDCA
SEG19
C AT B
SENSE14
LCDA
U S A R T 2 ABDACB
TXD
E I C
EXTINT5
G L O C
IN0
S C I F
GCLK1
LCDCA
SEG20
C AT B
SENSE15
LCDA
DACN1
S P I
MISO
U S A R T 1
CTS
E I C
EXTINT6
G L O C
IN1
T W I M 2
TWD
LCDCA
SEG34
C AT B
SENSE16
LCDC
S P I
MOSI
U S A R T 2
CTS
E I C
EXTINT7
G L O C
IN2
T W I M 2
TWCK
LCDCA
SEG35
C AT B
SENSE17
LCDC
S P I
SCK
T W I M S 0
TWD
E I C
EXTINT8
G L O C
IN3
S C I F
GCLK IN0
LCDCA
SEG38
C AT B
DIS
LCDC
S P I
NPCS0
T W I M S 0
TWCK
G L O C
OUT0
S C I F
GCLK IN1
LCDCA
SEG39
C AT B
SENSE18
LCDC
U S B C
DM
U S A R T 2
RXD
C AT B
SENSE19
VDDIO
VDDIO
U S B C
DP
U S A R T 2
TXD
C AT B
SENSE20
23
42023HS–SAM–11/2016
ATSAM4L8/L4/L2
Table 3-2.
64-pin GPIO Controller Function Multiplexing (Sheet 3 of 3)
GPIO Functions
QFP QFP
QFN QFN
A
B
C
D
E
F
G
S P I
MISO
I I S C
ISCK
ABDACB
DAC0
G L O C
IN4
U S A R T 3
RTS
C AT B
SENSE0
33
34
35
38
39
PA27
PA28
PA29
PA30
PA31
PB00
PB01
PB02
PB03
PB04
PB05
PB06
PB07
PB08
PB09
PB10
PB11
PB12
PB13
PB14
PB15
27
28
29
30
31
32
33
LCDA
LCDA
LCDA
LCDA
LCDA
VDDIN
VDDIN
S P I
MOSI
I I S C
ISDI
ABDACB
DACN0
G L O C
IN5
U S A R T 3
CTS
C AT B
SENSE1
S P I
SCK
I I S C
IWS
ABDACB
DAC1
G L O C
IN6
U S A R T 3
CLK
C AT B
SENSE2
S P I
NPCS0
I I S C
ISDO
ABDACB
DACN1
G L O C
IN7
U S A R T 3
RXD
C AT B
SENSE3
S P I
NPCS1
I I S C
IMCK
ABDACB
CLK
G L O C
OUT1
U S A R T 3
TXD
C AT B
DIS
T W I M S 1
TWD
U S A R T 0
RXD
C AT B
SENSE21
11
12
13
14
19
20
27
28
45
46
47
48
53
54
57
58
11
12
13
14
19
20
27
28
45
46
47
48
53
54
57
58
T W I M S 1
TWCK
U S A R T 0
TXD
E I C
EXTINT0
C AT B
SENSE22
A D C I F E
AD3
U S A R T 1
RTS
ABDACB
DAC0
I I S C
ISCK
A C I F C
ACBN0
C AT B
SENSE23
34 VDDANA
35 VDDANA
36 VDDANA
37 VDDANA
A D C I F E
AD4
U S A R T 1
CLK
ABDACB
DACN0
I I S C
ISDI
A C I F C
ACBP0
C AT B
DIS
A D C I F E
AD5
U S A R T 1
RXD
ABDACB
DAC1
I I S C
ISDO
DACC
EXT TRIG0
C AT B
SENSE24
A D C I F E
AD6
U S A R T 1
TXD
ABDACB
DACN1
I I S C
IMCK
C AT B
SENSE25
U S A R T 3
RTS
G L O C
IN4
I I S C
IWS
LCDCA
SEG22
C AT B
SENSE26
38
39
40
41
42
43
44
45
46
47
LCDA
LCDA
LCDA
LCDA
LCDA
LCDA
LCDC
LCDC
LCDC
LCDC
U S A R T 3
CTS
G L O C
IN5
T C 0
A0
LCDCA
SEG21
C AT B
SENSE27
U S A R T 3
CLK
G L O C
IN6
T C 0
B0
LCDCA
SEG14
C AT B
SENSE28
U S A R T 3
RXD
PEVC
PAD EVT2
G L O C
IN7
T C 0
A1
LCDCA
SEG15
C AT B
SENSE29
U S A R T 3
TXD
PEVC
PAD EVT3
G L O C
OUT1
T C 0
B1
S C I F
GCLK0
LCDCA
SEG16
C AT B
SENSE30
U S A R T 0
CTS
S P I
NPCS2
T C 0
A2
S C I F
GCLK1
LCDCA
SEG17
C AT B
SENSE31
U S A R T 0
RTS
S P I
NPCS3
P E V C
PAD EVT0
T C 0
B2
S C I F
GCLK2
LCDCA
SEG32
C AT B
DIS
U S A R T 0
CLK
S P I
NPCS1
P E V C
PAD EVT1
T C 0
CLK0
S C I F
GCLK3
LCDCA
SEG33
C AT B
SENSE0
U S A R T 0
RXD
S P I
MISO
T W I M 3
TWD
T C 0
CLK1
S C I F
GCLK IN0
LCDCA
SEG36
C AT B
SENSE1
U S A R T 0
TXD
S P I
MOSI
T W I M 3
TWCK
T C 0
CLK2
S C I F
GCLK IN1
LCDCA
SEG37
C AT B
SENSE2
24
42023HS–SAM–11/2016
ATSAM4L8/L4/L2
Table 3-3.
64-pin GPIO Controller Function Multiplexing for WLCSP package (Sheet 1 of 3)
GPIO Functions
D
WLCSP WLCSP
A
B
C
E
F
G
G4
G5
G4
G5
PA00
PA01
0
1
VDDIO
VDDIO
S C I F
GCLK0
S P I
NPCS0
C AT B
DIS
F3
E2
D3
C3
C4
C5
B4
A5
B6
B7
A8
C7
D7
E7
F7
G8
G7
G6
H7
H5
F5
F3
E2
D3
C3
C4
C5
B4
A5
B6
B7
A8
C7
D7
E7
F7
G8
G7
G6
H7
H5
F5
PA02
PA03
PA04
PA05
PA06
PA07
PA08
PA09
PA10
PA11
PA12
PA13
PA14
PA15
PA16
PA17
PA18
PA19
PA20
PA21
PA22
2
3
VDDIN
VDDIN
VDDANA
VDDANA
VDDANA
VDDANA
LCDA
S P I
MISO
A D C I F E
AD0
U S A R T 0
CLK
E I C
EXTINT2
G L O C
IN1
C AT B
SENSE0
4
A D C I F E
AD1
U S A R T 0
RXD
E I C
EXTINT3
G L O C
IN2
A D C I F E
TRIGGER
C AT B
SENSE1
5
DACC
VOUT
U S A R T 0
RTS
E I C
EXTINT1
G L O C
IN0
A C I F C
ACAN0
C AT B
SENSE2
6
A D C I F E
AD2
U S A R T 0
TXD
E I C
EXTINT4
G L O C
IN3
A C I F C
ACAP0
C AT B
SENSE3
7
U S A R T 0
RTS
T C 0
A0
PEVC
PAD EVT0
G L O C
OUT0
LCDCA
SEG23
C AT B
SENSE4
8
U S A R T 0
CTS
T C 0
B0
PEVC
PA R C
LCDCA
COM3
C AT B
SENSE5
9
LCDA
PAD EVT1 PCDATA0
PEVC PA R C
PAD EVT2 PCDATA1
PEVC PA R C
U S A R T 0
CLK
T C 0
A1
LCDCA
COM2
C AT B
SENSE6
10
11
12
13
14
15
16
17
18
19
20
21
22
LCDA
U S A R T 0
RXD
T C 0
B1
LCDCA
COM1
C AT B
SENSE7
LCDA
PAD EVT3 PCDATA2
U S A R T 0
TXD
T C 0
A2
PA R C
PCDATA3
LCDCA
COM0
C AT B
DIS
LCDA
U S A R T 1
RTS
T C 0
B2
S P I
NPCS1
PA R C
PCDATA4
LCDCA
SEG5
C AT B
SENSE8
LCDA
U S A R T 1
CLK
T C 0
CLK0
S P I
NPCS2
PA R C
PCDATA5
LCDCA
SEG6
C AT B
SENSE9
LCDA
U S A R T 1
RXD
T C 0
CLK1
S P I
NPCS3
PA R C
PCDATA6
LCDCA
SEG7
C AT B
SENSE10
LCDA
U S A R T 1
TXD
T C 0
CLK2
E I C
PA R C
LCDCA
SEG8
C AT B
SENSE11
LCDA
EXTINT1 PCDATA7
U S A R T 2
RTS
ABDACB
DAC0
E I C
EXTINT2
PA R C
PCCK
LCDCA
SEG9
C AT B
SENSE12
LCDA
U S A R T 2
CLK
ABDACB
DACN0
E I C
EXTINT3
PA R C
PCEN1
LCDCA
SEG18
C AT B
SENSE13
LCDA
U S A R T 2
RXD
ABDACB
DAC1
E I C
EXTINT4
PA R C
PCEN2
S C I F
GCLK0
LCDCA
SEG19
C AT B
SENSE14
LCDA
U S A R T 2
TXD
ABDACB
DACN1
E I C
EXTINT5
G L O C
IN0
S C I F
GCLK1
LCDCA
SEG20
C AT B
SENSE15
LCDA
S P I
MISO
U S A R T 1
CTS
E I C
EXTINT6
G L O C
IN1
T W I M 2
TWD
LCDCA
SEG34
C AT B
SENSE16
LCDC
S P I
MOSI
U S A R T 2
CTS
E I C
EXTINT7
G L O C
IN2
T W I M 2
TWCK
LCDCA
SEG35
C AT B
SENSE17
LCDC
25
42023HS–SAM–11/2016
ATSAM4L8/L4/L2
Table 3-3.
64-pin GPIO Controller Function Multiplexing for WLCSP package (Sheet 2 of 3)
GPIO Functions
WLCSP WLCSP
A
B
C
D
E
F
G
S P I
SCK
T W I M S 0
TWD
E I C
EXTINT8
G L O C
IN3
S C I F
GCLK IN0
LCDCA
SEG38
C AT B
DIS
H3
G3
H2
G2
H3
G3
H2
G2
A7
A6
B8
E8
F8
D2
C2
E3
B1
A1
D4
B5
C6
D6
E6
F6
H8
D5
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
PB00
PB01
PB02
PB03
PB04
PB05
PB06
PB07
PB08
PB09
PB10
PB11
PB12
23
24
25
26
27
28
29
30
31
32
33
LCDC
LCDC
VDDIO
VDDIO
LCDA
LCDA
LCDA
LCDA
LCDA
VDDIN
VDDIN
S P I
NPCS0
T W I M S 0
TWCK
G L O C
OUT0
S C I F
GCLK IN1
LCDCA
SEG39
C AT B
SENSE18
U S B C
DM
U S A R T 2
RXD
C AT B
SENSE19
U S B C
DP
U S A R T 2
TXD
C AT B
SENSE20
S P I
MISO
I I S C
ISCK
ABDACB
DAC0
G L O C
IN4
U S A R T 3
RTS
C AT B
SENSE0
S P I
MOSI
I I S C
ISDI
ABDACB
DACN0
G L O C
IN5
U S A R T 3
CTS
C AT B
SENSE1
S P I
SCK
I I S C
IWS
ABDACB
DAC1
G L O C
IN6
U S A R T 3
CLK
C AT B
SENSE2
S P I
NPCS0
I I S C
ISDO
ABDACB
DACN1
G L O C
IN7
U S A R T 3
RXD
C AT B
SENSE3
S P I
NPCS1
I I S C
IMCK
ABDACB
CLK
G L O C
OUT1
U S A R T 3
TXD
C AT B
DIS
T W I M S 1
TWD
U S A R T 0
RXD
C AT B
SENSE21
D2
C2
E3
B1
A1
D4
B5
C6
D6
E6
F6
H8
D5
T W I M S 1
TWCK
U S A R T 0
TXD
E I C
EXTINT0
C AT B
SENSE22
A D C I F E
AD3
U S A R T 1 ABDACB
RTS DAC0
I I S C
ISCK
A C I F C
ACBN0
C AT B
SENSE23
34 VDDANA
35 VDDANA
36 VDDANA
37 VDDANA
A D C I F E
AD4
U S A R T 1 ABDACB
CLK DACN0
I I S C
ISDI
A C I F C
ACBP0
C AT B
DIS
A D C I F E
AD5
U S A R T 1 ABDACB
RXD DAC1
I I S C
ISDO
DACC
EXT TRIG0
C AT B
SENSE24
A D C I F E
AD6
U S A R T 1 ABDACB
TXD
I I S C
IMCK
C AT B
SENSE25
DACN1
U S A R T 3
RTS
G L O C
IN4
I I S C
IWS
LCDCA
SEG22
C AT B
SENSE26
38
39
40
41
42
43
44
LCDA
LCDA
LCDA
LCDA
LCDA
LCDA
LCDC
U S A R T 3
CTS
G L O C
IN5
T C 0
A0
LCDCA
SEG21
C AT B
SENSE27
U S A R T 3
CLK
G L O C
IN6
T C 0
B0
LCDCA
SEG14
C AT B
SENSE28
U S A R T 3
RXD
P E V C
PAD EVT2
G L O C
IN7
T C 0
A1
LCDCA
SEG15
C AT B
SENSE29
U S A R T 3
TXD
P E V C
PAD EVT3
G L O C
OUT1
T C 0
B1
S C I F
GCLK0
LCDCA
SEG16
C AT B
SENSE30
U S A R T 0
CTS
S P I
NPCS2
T C 0
A2
S C I F
GCLK1
LCDCA
SEG17
C AT B
SENSE31
U S A R T 0
RTS
S P I
NPCS3
PEVC
PAD EVT0
T C 0
B2
S C I F
GCLK2
LCDCA
SEG32
C AT B
DIS
26
42023HS–SAM–11/2016
ATSAM4L8/L4/L2
Table 3-3.
64-pin GPIO Controller Function Multiplexing for WLCSP package (Sheet 3 of 3)
GPIO Functions
WLCSP WLCSP
A
B
C
D
E
F
G
U S A R T 0
CLK
S P I
NPCS1
PEVC
PAD EVT1
T C 0
CLK0
S C I F
GCLK3
LCDCA
SEG33
C AT B
SENSE0
E5
F4
H4
E5
F4
H4
PB13
PB14
PB15
45
46
47
LCDC
LCDC
LCDC
U S A R T 0
RXD
S P I
MISO
T W I M 3
TWD
T C 0
CLK1
S C I F
GCLK IN0
LCDCA
SEG36
C AT B
SENSE1
U S A R T 0
TXD
S P I
MOSI
T W I M 3
TWCK
T C 0
CLK2
S C I F
GCLK IN1
LCDCA
SEG37
C AT B
SENSE2
27
42023HS–SAM–11/2016
ATSAM4L8/L4/L2
Table 3-4.
48-pin GPIO Controller Function Multiplexing (Sheet 1 of 2)
GPIO Functions
A
B
C
D
E
F
G
1
2
1
2
PA00
PA01
0
1
VDDIO
VDDIO
S C I F
GCLK0
S P I
NPCS0
C AT B
DIS
3
3
PA02
PA03
PA04
PA05
PA06
PA07
PA08
PA09
PA10
PA11
PA12
PA13
PA14
PA15
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
2
VDDIN
VDDIN
VDDANA
VDDANA
VDDANA
VDDANA
LCDA
S P I
MISO
10
11
12
15
16
20
21
22
23
24
32
33
34
35
36
37
38
39
41
42
43
10
11
12
15
16
20
21
22
23
24
32
33
34
35
36
37
38
39
41
42
43
3
A D C I F E
AD0
U S A R T 0
CLK
E I C
EXTINT2
G L O C
IN1
C AT B
SENSE0
4
A D C I F E
AD1
U S A R T 0
RXD
E I C
EXTINT3
G L O C
IN2
A D C I F E
TRIGGER
C AT B
SENSE1
5
DACC
VOUT
U S A R T 0
RTS
E I C
EXTINT1
G L O C
IN0
A C I F C
ACAN0
C AT B
SENSE2
6
A D C I F E
AD2
U S A R T 0
TXD
E I C
EXTINT4
G L O C
IN3
A C I F C
ACAP0
C AT B
SENSE3
7
U S A R T 0
RTS
T C 0
A0
PEVC
PAD EVT0
G L O C
OUT0
L C D C A
SEG23
C AT B
SENSE4
8
U S A R T 0
CTS
T C 0
B0
PEVC
PA R C
L C D C A
COM3
C AT B
SENSE5
9
LCDA
PAD EVT1 PCDATA0
PEVC PA R C
PAD EVT2 PCDATA1
PEVC PA R C
U S A R T 0
CLK
T C 0
A1
L C D C A
COM2
C AT B
SENSE6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
LCDA
U S A R T 0
RXD
T C 0
B1
L C D C A
COM1
C AT B
SENSE7
LCDA
PAD EVT3 PCDATA2
U S A R T 0
TXD
T C 0
A2
PA R C
PCDATA3
L C D C A
COM0
C AT B
DIS
LCDA
U S A R T 1
RTS
T C 0
B2
S P I
NPCS1
PA R C
PCDATA4
L C D C A
SEG5
C AT B
SENSE8
LCDA
U S A R T 1
CLK
T C 0
CLK0
S P I
NPCS2
PA R C
PCDATA5
L C D C A
SEG6
C AT B
SENSE9
LCDA
U S A R T 1
RXD
T C 0
CLK1
S P I
NPCS3
PA R C
PCDATA6
L C D C A
SEG7
C AT B
SENSE10
LCDA
U S A R T 1
TXD
T C 0
CLK2
E I C
PA R C
L C D C A
SEG8
C AT B
SENSE11
LCDA
EXTINT1 PCDATA7
U S A R T 2 ABDACB
RTS DAC0
E I C
EXTINT2
PA R C
PCCK
L C D C A
SEG9
C AT B
SENSE12
LCDA
U S A R T 2 ABDACB
CLK DACN0
E I C
EXTINT3
PA R C
PCEN1
L C D C A
SEG18
C AT B
SENSE13
LCDA
U S A R T 2 ABDACB
RXD DAC1
E I C
EXTINT4
PA R C
PCEN2
S C I F
GCLK0
L C D C A
SEG19
C AT B
SENSE14
LCDA
U S A R T 2 ABDACB
E I C
EXTINT5
G L O C
IN0
S C I F
GCLK1
L C D C A
SEG20
C AT B
SENSE15
LCDA
TXD
DACN1
S P I
MISO
U S A R T 1
CTS
E I C
EXTINT6
G L O C
IN1
T W I M 2
TWD
L C D C A
SEG34
C AT B
SENSE16
LCDC
S P I
MOSI
U S A R T 2
CTS
E I C
EXTINT7
G L O C
IN2
T W I M 2
TWCK
L C D C A
SEG35
C AT B
SENSE17
LCDC
S P I
SCK
T W I M S 0
TWD
E I C
EXTINT8
G L O C
IN3
S C I F
GCLK IN0
L C D C A
SEG38
C AT B
DIS
LCDC
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Table 3-4.
48-pin GPIO Controller Function Multiplexing (Sheet 2 of 2)
GPIO Functions
A
B
C
D
E
F
G
S P I
NPCS0
T W I M S 0
TWCK
G L O C
OUT0
S C I F
GCLK IN1
L C D C A
SEG39
C AT B
SENSE18
44
46
47
44
46
47
25
26
27
30
31
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
24
25
26
27
28
29
30
31
LCDC
VDDIO
VDDIO
LCDA
LCDA
LCDA
LCDA
LCDA
U S B C
DM
U S A R T 2
RXD
C AT B
SENSE19
U S B C
DP
U S A R T 2
TXD
C AT B
SENSE20
S P I
MISO
I I S C
ISCK
ABDACB
DAC0
G L O C
IN4
U S A R T 3
RTS
C AT B
SENSE0
S P I
MOSI
I I S C
ISDI
ABDACB
DACN0
G L O C
IN5
U S A R T 3
CTS
C AT B
SENSE1
S P I
SCK
I I S C
IWS
ABDACB
DAC1
G L O C
IN6
U S A R T 3
CLK
C AT B
SENSE2
S P I
NPCS0
I I S C
ISDO
ABDACB
DACN1
G L O C
IN7
U S A R T 3
RXD
C AT B
SENSE3
S P I
NPCS1
I I S C
IMCK
ABDACB
CLK
G L O C
OUT1
U S A R T 3
TXD
C AT B
DIS
3.2.2
Peripheral Functions
Each GPIO line can be assigned to one of several peripheral functions. The following table
describes how the various peripheral functions are selected. The last listed function has priority
in case multiple functions are enabled on the same pin.
Table 3-5.
Function
Peripheral Functions
Description
GPIO Controller Function multiplexing
JTAG port connections
Oscillators
GPIO and GPIO peripheral selection A to H
JTAG debug port
OSC0
3.2.3
JTAG Port Connections
If the JTAG is enabled, the JTAG will take control over a number of pins, irrespectively of the I/O
Controller configuration.
Table 3-6.
JTAG Pinout
48-pin
64-pin
64-pin
100-pin
QFN
100-ball
VFBGA
Pin
JTAG
Pin
Packages
QFP/QFN
WLSCP
Name
10
43
44
9
10
59
60
9
E2
19
95
96
18
B3
D6
PA03
PA23
PA24
TCK
TMS
TDO
TDI
H3
G3
D10
B4
F2
TCK
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3.2.4
3.2.5
ITM Trace Connections
If the ITM trace is enabled, the ITM will take control over the pin PA23, irrespectively of the I/O
Controller configuration. The Serial Wire Trace signal is available on pin PA23
Oscillator Pinout
The oscillators are not mapped to the normal GPIO functions and their muxings are controlled
by registers in the System Control Interface (SCIF) or Backup System Control Interface (BSCIF).
Refer to the Section 15. ”System Control Interface (SCIF)” on page 308 and Section 15. ”Backup
System Control Interface (BSCIF)” on page 308 for more information about this.
Table 3-7.
Oscillator Pinout
Pin Name
PA00
Oscillator Pin
XIN0
1
13
2
1
G4
B2
G5
B3
5
26
6
B9
B2
B8
C2
17
2
XIN32
XIN32
PA01
XOUT0
14
18
27
XOUT32
XOUT32
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3.3
Signals Description
The following table gives details on signal names classified by peripheral.
Table 3-8.
Signal Descriptions List (Sheet 1 of 4)
Active
Level
Signal Name
Function
Type
Comments
Audio Bitstream DAC - ABDACB
CLK
D/A clock output
Output
Output
DAC1 - DAC0
DACN1 - DACN0
D/A bitstream outputs
D/A inverted bitstream outputs
Output
Analog Comparator Interface - ACIFC
ACAN1 - ACAN0
ACAP1 - ACAP0
ACBN1 - ACBN0
ACBP1 - ACBP0
Analog Comparator A negative references
Analog
Analog
Analog
Analog
Analog Comparator A positive references
Analog Comparator B negative references
Analog Comparator B positive references
ADC controller interface - ADCIFE
AD14 - AD0
ADVREFP
TRIGGER
Analog inputs
Analog
Positive voltage reference
External trigger
Analog
Input
Backup System Control Interface - BSCIF
Analog/
Digital
XIN32
32 kHz Crystal Oscillator Input
32 kHz Crystal Oscillator Output
XOUT32
Analog
Capacitive Touch Module B - CATB
DIS
Capacitive discharge line
Output
I/O
SENSE31 - SENSE0
Capacitive sense lines
DAC Controller - DACC
DAC external trigger
DAC voltage output
DAC external trigger
DAC voltage output
Input
Analog
Enhanced Debug Port For ARM Products - EDP
TCK/SWCLK
TDI
JTAG / SW Debug Clock
Input
Input
Output
I/O
JTAG Debug Data In
TDO/TRACESWO
TMS/SWDIO
JTAG Debug Data Out / SW Trace Out
JTAG Debug Mode Select / SW Data
External Interrupt Controller - EIC
EXTINT8 - EXTINT0
External interrupts
Input
Glue Logic Controller - GLOC
Input
IN7 - IN0
Lookup Tables Inputs
OUT1 - OUT0
Lookup Tables Outputs
Output
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Table 3-8.
Signal Descriptions List (Sheet 2 of 4)
Active
Level
Signal Name
Function
Type
Comments
Inter-IC Sound (I2S) Controller - IISC
IMCK
ISCK
ISDI
I2S Master Clock
I2S Serial Clock
I2S Serial Data In
I2S Serial Data Out
I2S Word Select
Output
I/O
Input
ISDO
IWS
Output
I/O
LCD Controller - LCDCA
BIASL
Bias voltage (1/3 VLCD)
Bias voltage (2/3 VLCD)
High voltage end of flying capacitor
Low voltage end of flying capacitor
Common terminals
Analog
Analog
Analog
Analog
Analog
Analog
Analog
BIASH
CAPH
CAPL
COM3 - COM0
SEG39 - SEG0
VLCD
Segment terminals
Bias voltage
Parallel Capture - PARC
PCCK
Clock
Input
PCDATA7 - PCDATA0
PCEN1
Data lines
Data enable 1
Data enable 2
Input
Input
Input
PCEN2
Peripheral Event Controller - PEVC
PAD_EVT3 -
PAD_EVT0
Event Inputs
Reset
Input
Power Manager - PM
Input
RESET_N
Low
System Control Interface - SCIF
GCLK3 - GCLK0
Generic Clock Outputs
Output
Input
GCLK_IN1 - GCLK_IN0 Generic Clock Inputs
Analog/
Digital
XIN0
Crystal 0 Input
XOUT0
Crystal 0 Output
Analog
Serial Peripheral Interface - SPI
MISO
Master In Slave Out
Master Out Slave In
I/O
I/O
MOSI
NPCS3 - NPCS0
SCK
SPI Peripheral Chip Selects
Clock
I/O
I/O
Low
Timer/Counter - TC0, TC1
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Table 3-8.
Signal Descriptions List (Sheet 3 of 4)
Active
Level
Signal Name
Function
Type
I/O
Comments
A0
Channel 0 Line A
A1
Channel 1 Line A
I/O
A2
Channel 2 Line A
I/O
B0
Channel 0 Line B
I/O
B1
Channel 1 Line B
I/O
B2
Channel 2 Line B
I/O
CLK0
CLK1
CLK2
Channel 0 External Clock Input
Channel 1 External Clock Input
Channel 2 External Clock Input
Input
Input
Input
Two-wire Interface - TWIMS0, TWIMS1, TWIM2, TWIM3
TWCK
TWD
Two-wire Serial Clock
Two-wire Serial Data
I/O
I/O
Universal Synchronous Asynchronous Receiver Transmitter - USART0, USART1, USART2, USART3
CLK
CTS
RTS
RXD
TXD
Clock
I/O
Clear To Send
Request To Send
Receive Data
Transmit Data
Input
Low
Low
Output
Input
Output
USB 2.0 Interface - USBC
DM
DP
USB Full Speed Interface Data -
USB Full Speed Interface Data +
I/O
I/O
Power
GND
Ground
Ground
Ground
GNDANA
Analog Ground
Power
Input
VDDANA
VDDCORE
VDDIN
Analog Power Supply
Core Power Supply
1.68V to 3.6V
1.68V to 1.98V
1.68V to 3.6V
Power
Input
Power
Input
Voltage Regulator Input
1.68V to 3.6V. VDDIO must
always be equal to or lower than
VDDIN.
Power
Input
VDDIO
I/O Pads Power Supply
Voltage Regulator Output
Power
Output
VDDOUT
1.08V to 1.98V
General Purpose I/O
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Table 3-8.
Signal Descriptions List (Sheet 4 of 4)
Active
Level
Signal Name
PA31 - PA00
PB15 - PB00
PC31 - PC00
Function
Type
I/O
Comments
Parallel I/O Controller I/O Port A
Parallel I/O Controller I/O Port B
Parallel I/O Controller I/O Port C
I/O
I/O
Note:
1. See “Power and Startup Considerations” section.
3.4
I/O Line Considerations
3.4.1
SW/JTAG Pins
The JTAG pins switch to the JTAG functions if a rising edge is detected on TCK low after the
RESET_N pin has been released. The TMS, and TDI pins have pull-up resistors when used as
JTAG pins. The TCK pin always has pull-up enabled during reset. The JTAG pins can be used
as GPIO pins and multiplexed with peripherals when the JTAG is disabled. Refer to Section
3.2.3 ”JTAG Port Connections” on page 29 for the JTAG port connections.
For more details, refer to Section 1.1 ”Enhanced Debug Port (EDP)” on page 3.
3.4.2
3.4.3
RESET_N Pin
TWI Pins
The RESET_N pin is a schmitt input and integrates a permanent pull-up resistor to VDDIN. As
the product integrates a power-on reset detector, the RESET_N pin can be left unconnected in
case no reset from the system needs to be applied to the product.
When these pins are used for TWI, the pins are open-drain outputs with slew-rate limitation and-
inputs with inputs with spike-filtering. When used as GPIO-pins or used for other peripherals, the
pins have the same characteristics as GPIO pins.
3.4.4
GPIO Pins
All the I/O lines integrate a pull-up/pull-down resistor and slew rate controller. Programming
these features is performed independently for each I/O line through the GPIO Controllers. After
reset, I/O lines default as inputs with pull-up and pull-down resistors disabled and slew rate
enabled.
3.4.5
3.4.6
High-drive Pins
The six pins PA02, PB00, PB01, PC04, PC05 and PC06 have high-drive output capabilities.
Refer to Section 9.6.2 ”High-drive I/O Pin : PA02, PC04, PC05, PC06” on page 115 for electrical
characteristics.
USB Pins
When these pins are used for USB, the pins are behaving according to the USB specification.
When used as GPIO pins or used for other peripherals, the pins have the same behavior as
other normal I/O pins, but the characteristics are different. Refer to Section 9.6.3 ”USB I/O Pin :
PA25, PA26” on page 116 for electrical characteristics.
These pins are compliant to USB standard only when VDDIO power supply is 3.3V nominal.
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3.4.7
ADC Input Pins
These pins are regular I/O pins powered from the VDDANA.
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4. Cortex-M4 processor and core peripherals
4.1
Cortex-M4
The Cortex-M4 processor is a high performance 32-bit processor designed for the microcon-
troller market. It offers significant benefits to developers, including:
• outstanding processing performance combined with fast interrupt handling
• enhanced system debug with extensive breakpoint and trace capabilities
• efficient processor core, system and memories
• ultra-low power consumption with integrated sleep modes
• platform security robustness, with integrated memory protection unit (MPU).
Cortex-M4
processor
NVIC
Processor
core
Debug
Access
Port
Serial
Wire
viewer
Memory
protection unit
Flash
patch
Data
watchpoints
Bus matrix
Code
interface
SRAM and
peripheral interface
The Cortex-M4 processor is built on a high-performance processor core, with a 3-stage pipeline
Harvard architecture, making it ideal for demanding embedded applications. The processor
delivers exceptional power efficiency through an efficient instruction set and extensively opti-
mized design, providing high-end processing hardware including a range of single-cycle and
SIMD multiplication and multiply-with-accumulate capabilities, saturating arithmetic and dedi-
cated hardware division.
To facilitate the design of cost-sensitive devices, the Cortex-M4 processor implements tightly-
coupled system components that reduce processor area while significantly improving interrupt
handling and system debug capabilities. The Cortex-M4 processor implements a version of the
Thumb® instruction set based on Thumb-2 technology, ensuring high code density and reduced
program memory requirements. The Cortex-M4 instruction set provides the exceptional perfor-
mance expected of a modern 32-bit architecture, with the high code density of 8-bit and 16-bit
microcontrollers.
The Cortex-M4 processor closely integrates a configurable Nested Vectored Interrupt Controller
(NVIC), to deliver industry-leading interrupt performance. The NVIC includes a non-maskable
interrupt (NMI), and provides up to 80 interrupt priority levels. The tight integration of the proces-
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sor core and NVIC provides fast execution of interrupt service routines (ISRs), dramatically
reducing the interrupt latency. This is achieved through the hardware stacking of registers, and
the ability to suspend load-multiple and store-multiple operations. Interrupt handlers do not
require wrapping in assembler code, removing any code overhead from the ISRs. A tail-chain
optimization also significantly reduces the overhead when switching from one ISR to another.
To optimize low-power designs, the NVIC integrates with the sleep modes, that include a deep
sleep function enabling the entire device to be rapidly powered down while still retaining pro-
gram state.
4.2
System level interface
The Cortex-M4 processor provides multiple interfaces using AMBA® technology to provide high
speed, low latency memory accesses. It supports unaligned data accesses and implements
atomic bit manipulation that enables faster peripheral controls, system spinlocks and thread-safe
Boolean data handling.
The Cortex-M4 processor has an memory protection unit (MPU) that provides fine grain memory
control, enabling applications to utilize multiple privilege levels, separating and protecting code,
data and stack on a task-by-task basis. Such requirements are becoming critical in many
embedded applications such as automotive.
4.3
Integrated configurable debug
The Cortex-M4 processor implements a complete hardware debug solution. This provides high
system visibility of the processor and memory through either a traditional JTAG port or a 2-pin
Serial Wire Debug (SWD) port that is ideal for microcontrollers and other small package devices.
For system trace the processor integrates an Instrumentation Trace Macrocell (ITM) alongside
data watchpoints and a profiling unit. To enable simple and cost-effective profiling of the system
events these generate, a Serial Wire Viewer (SWV) can export a stream of software-generated
messages, data trace, and profiling information through a single pin.
The Flash Patch and Breakpoint Unit (FPB) provides 8 hardware breakpoint comparators that
debuggers can use. The comparators in the FPB also provide remap functions of up to 8 words
in the program code in the CODE memory region. This enables applications stored on a non-
erasable, ROM-based microcontroller to be patched if a small programmable memory, for exam-
ple flash, is available in the device. During initialization, the application in ROM detects, from the
programmable memory, whether a patch is required. If a patch is required, the application pro-
grams the FPB to remap a number of addresses. When those addresses are accessed, the
accesses are redirected to a remap table specified in the FPB configuration, which means the
program in the non-modifiable ROM can be patched.
A specific Peripheral Debug (PDBG) register is implemented in the Private Peripheral Bus
address map. This register allows the user to configure the behavior of some modules in debug
mode.
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4.4
Cortex-M4 processor features and benefits summary
• tight integration of system peripherals reduces area and development costs
• Thumb instruction set combines high code density with 32-bit performance
• code-patch ability for ROM system updates
• power control optimization of system components
• integrated sleep modes for low power consumption
• fast code execution permits slower processor clock or increases sleep mode time
• hardware division and fast digital-signal-processing orientated multiply accumulate
• saturating arithmetic for signal processing
• deterministic, high-performance interrupt handling for time-critical applications
• memory protection unit (MPU) for safety-critical applications
• extensive debug and trace capabilities:
– Serial Wire Debug and Serial Wire Trace reduce the number of pins required for debugging,
tracing, and code profiling.
4.5
Cortex-M4 core peripherals
These are:
Nested Vectored Interrupt Controller
The NVIC is an embedded interrupt controller that supports low latency interrupt processing.
System control block
The System control block (SCB) is the programmers model interface to the processor. It pro-
vides system implementation information and system control, including configuration, control,
and reporting of system exceptions.
System timer
The system timer, SysTick, is a 24-bit count-down timer. Use this as a Real Time Operating Sys-
tem (RTOS) tick timer or as a simple counter.
Memory protection unit
The Memory protection unit (MPU) improves system reliability by defining the memory attributes
for different memory regions. It provides up to eight different regions, and an optional predefined
background region.
The complete Cortex-M4 User Guide can be found on the ARM web site:
http://infocenter.arm.com/help/topic/com.arm.doc.dui0553a/DUI0553A_cortex_m4_dgug.pdf
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4.6
Cortex-M4 implementations options
This table provides the specific configuration options implemented in the SAM4L series
Option
Inclusion of MPU
Inclusion of FPU
Implementation
yes
No
80
4
Number of interrupts
Number of priority bits
Inclusion of the WIC
Embedded Trace Macrocell
Sleep mode instruction
Endianness
No
No
Only WFI supported
Little Endian
Bit-banding
No
Yes
No
SysTick timer
Register reset values
Table 4-1.
Cortex-M4 implementation options
4.7
Cortex-M4 Interrupts map
The table below shows how the interrupt request signals are connected to the NVIC.
Table 4-2.
Interrupt Request Signal Map (Sheet 1 of 3)
Module
Line
0
Signal
HFLASHC
PDCA 0
PDCA 1
PDCA 2
PDCA 3
PDCA 4
PDCA 5
PDCA 6
PDCA 7
PDCA 8
PDCA 9
PDCA 10
Flash Controller
1
Peripheral DMA Controller
Peripheral DMA Controller
Peripheral DMA Controller
Peripheral DMA Controller
Peripheral DMA Controller
Peripheral DMA Controller
Peripheral DMA Controller
Peripheral DMA Controller
Peripheral DMA Controller
Peripheral DMA Controller
Peripheral DMA Controller
2
3
4
5
6
7
8
9
10
11
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Table 4-2.
Line
12
Interrupt Request Signal Map (Sheet 2 of 3)
Module
Signal
PDCA 11
PDCA 12
PDCA 13
PDCA 14
PDCA 15
CRCCU
USBC
Peripheral DMA Controller
13
Peripheral DMA Controller
14
Peripheral DMA Controller
15
Peripheral DMA Controller
16
Peripheral DMA Controller
17
CRC Calculation Unit
18
USB 2.0 Interface
19
Peripheral Event Controller
Peripheral Event Controller
Advanced Encryption Standard
Power Manager
PEVC TR
PEVC OV
AESA
20
21
22
PM
23
System Control Interface
SCIF
24
Frequency Meter
FREQM
GPIO 0
GPIO 1
GPIO 2
GPIO 3
GPIO 4
GPIO 5
GPIO 6
GPIO 7
GPIO 8
GPIO 9
GPIO 10
GPIO 11
BPM
25
General-Purpose Input/Output Controller
General-Purpose Input/Output Controller
General-Purpose Input/Output Controller
General-Purpose Input/Output Controller
General-Purpose Input/Output Controller
General-Purpose Input/Output Controller
General-Purpose Input/Output Controller
General-Purpose Input/Output Controller
General-Purpose Input/Output Controller
General-Purpose Input/Output Controller
General-Purpose Input/Output Controller
General-Purpose Input/Output Controller
Backup Power Manager
26
27
28
29
30
31
32
33
34
35
36
37
38
Backup System Control Interface
Asynchronous Timer
BSCIF
39
AST ALARM
AST PER
AST OVF
AST READY
AST CLKREADY
WDT
40
Asynchronous Timer
41
Asynchronous Timer
42
Asynchronous Timer
43
Asynchronous Timer
44
Watchdog Timer
45
External Interrupt Controller
External Interrupt Controller
External Interrupt Controller
EIC 1
46
EIC 2
47
EIC 3
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Table 4-2.
Interrupt Request Signal Map (Sheet 3 of 3)
Module
Line
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Signal
EIC 4
EIC 5
EIC 6
EIC 7
EIC 8
IISC
External Interrupt Controller
External Interrupt Controller
External Interrupt Controller
External Interrupt Controller
External Interrupt Controller
Inter-IC Sound (I2S) Controller
Serial Peripheral Interface
Timer/Counter
SPI
TC00
TC01
TC02
TC10
TC11
TC12
TWIM0
TWIS0
TWIM1
TWIS1
Timer/Counter
Timer/Counter
Timer/Counter
Timer/Counter
Timer/Counter
Two-wire Master Interface
Two-wire Slave Interface
Two-wire Master Interface
Two-wire Slave Interface
Universal Synchronous Asynchronous
Receiver Transmitter
65
66
67
68
USART0
USART1
USART2
USART3
Universal Synchronous Asynchronous
Receiver Transmitter
Universal Synchronous Asynchronous
Receiver Transmitter
Universal Synchronous Asynchronous
Receiver Transmitter
69
70
71
72
73
74
75
77
78
79
ADC controller interface
DAC Controller
ADCIFE
DACC
Analog Comparator Interface
Audio Bitstream DAC
ACIFC
ABDACB
TRNG
True Random Number Generator
Parallel Capture
PARC
Capacitive Touch Module B
Two-wire Master Interface
Two-wire Master Interface
LCD Controller A
CATB
TWIM2
TWIM3
LCDCA
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4.8
Peripheral Debug
The PDBG register controls the behavior of asynchronous peripherals when the device is in
debug mode.When the corresponding bit is set, that peripheral will be in a frozenstate in debug
mode.
4.8.1
Peripheral Debug
Name:
PDBG
Access Type:
Address:
Read/Write
0xE0042000
0x00000000
Reset Value:
31
-
30
29
-
28
-
27
-
26
-
25
-
24
-
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
-
3
-
2
1
0
PEVC
AST
WDT
• WDT: Watchdog PDBG bit
WDT = 0: The WDT counter is not frozen during debug operation.
WDT = 1: The WDT counter is frozen during debug operation when Core is halted
• AST: Asynchronous Timer PDBG bit
AST = 0: The AST prescaler and counter is not frozen during debug operation.
AST = 1: The AST prescaler and counter is frozen during debug operation when Core is halted.
• PEVC: PEVC PDBG bit
PEVC= 0: PEVC is not frozen during debug operation.
PEVC= 1: PEVC is frozen during debug operation when Core is halted.
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5. Memories
5.1
Product Mapping
Figure 5-1. ATSAM4L8/L4/L2 Product Mapping
Global Memory Space
Code
0x00000000
0x00800000
0x1FFFFFFF
0x00000000
0x20000000
0x22000000
Code
Internal Flash
Reserved
Peripheral Bridge A
Peripheral Bridge B
0x400A0000
0x40000000
SRAM
Reserved
I2SC
FLASHCALW
0x400A0400
0x40004000
0x40008000
PICOCACHE
0x400A1000
HMATRIX
SPI
0x400A2000
Undefined
0x4000C000
0x40010000
0x40014000
0x40018000
SRAM
PDCA
0x400A3000
Reserved
TC0
0x20000000
0x20010000
SMAP
0x40000000
0x60000000
HRAMC0
0x400A4000
CRCCU
Peripherals
Reserved
System
TC1
0x400A5000
Reserved
HRAMC1
Reserved
USBC
TWIMS0
TWIMS1
Reserved
USART0
USART1
USART2
USART3
Reserved
ADCIFE
DACC
0x400A6000
0x4001C000
0x40020000
0x40024000
0x40028000
0x21000000
0x210007FF
PEVC
0x400A6400
0xE0000000
0xFFFFFFFF
Reserved
0x400AFFFF
0x21FFFFFF
0x4002C000
0x40030000
0x40034000
0x40038000
Peripheral Bridge C
Peripherals
System
0x400E0000
0xE0000000
0xE0001000
0xE0002000
0xE0003000
0x40000000
0x400A0000
PM
0x400E0740
ITM
DWT
FPB
Peripheral
Bridge A
CHIPID
0x400E0800
SCIF
0x4003C000
0x40040000
0x40044000
0x40060000
Peripheral
Bridge B
0x400E0C00
FREQM
0x400B0000
0x400B0100
0x400E0000
0x400F0000
0x40100000
0x400E1000
GPIO
ACIFC
Reserved
SCS
AESA
0x400E1800
Reserved
GLOC
0xE000E000
0xE000F000
Reserved
0x400EFFFF
Reserved
0x40064000
0x40068000
0x4006C000
0x40070000
ABDACB
TRNG
Reserved
Peripheral Bridge D
Peripheral
Bridge C
0xE0040000
0xE0041000
0xE0042000
0x400F0000
BPM
TPIU
PARC
Peripheral
Bridge D
0x400F0400
Reserved
BSCIF
CATB
0x400F0800
0x40074000
0x40078000
0x4007C000
0x40080000
AST
Reserved
TWIM2
TWIM3
LCDCA
Reserved
External PPB
ROM Table
0x400F0C00
WDT
0xE00FF000
0xE0100000
0x400F1000
EIC
Reserved
0x400F1400
PICOUART
0x400F1800
Reserved
0x40084000
0x4009FFFF
Reserved
0x5FFFFFFF
0x400FFFFF
0xFFFFFFFF
System Controller
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5.2
Embedded Memories
• Internal high-speed flash
– 512Kbytes (ATSAM4Lx8)
– 256Kbytes (ATSAM4Lx4)
– 128Kbytes (ATSAM4Lx2)
• Pipelined flash architecture, allowing burst reads from sequential flash locations, hiding
penalty of 1 wait state access
• Pipelined flash architecture typically reduces the cycle penalty of 1 wait state operation
compared to 0 wait state operation
• 100 000 write cycles, 15-year data retention capability
• Sector lock capabilities, bootloader protection, security bit
• 32 fuses, erased during chip erase
• User page for data to be preserved during chip erase
• Internal high-speed SRAM, single-cycle access at full speed
– 64Kbytes (ATSAM4Lx8)
– 32Kbytes (ATSAM4Lx4, ATSAM4Lx2)
5.3
Physical Memory Map
The system bus is implemented as a bus matrix. All system bus addresses are fixed, and they
are never remapped in any way, not even during boot. The 32-bit physical address space is
mapped as follows:
Table 5-1.
ATSAM4L8/L4/L2 Physical Memory Map
Start Address
Size
Size
Memory
ATSAM4Lx4
256Kbytes
32Kbytes
4Kbytes
ATSAM4Lx2
128Kbytes
32Kbytes
4Kbytes
Embedded Flash
Embedded SRAM
Cache SRAM
0x00000000
0x20000000
0x21000000
0x40000000
0x400A0000
0x400B0000
0x400E0000
0x400F0000
Peripheral Bridge A
Peripheral Bridge B
AESA
64Kbytes
64Kbytes
256 bytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
256 bytes
64Kbytes
64Kbytes
Peripheral Bridge C
Peripheral Bridge D
Start Address
Size
Memory
ATSAM4Lx8
512Kbytes
64Kbytes
4Kbytes
Embedded Flash
Embedded SRAM
Cache SRAM
0x00000000
0x20000000
0x21000000
0x40000000
0x400A0000
Peripheral Bridge A
Peripheral Bridge B
64Kbytes
64Kbytes
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ATSAM4L8/L4/L2
Start Address
Size
Memory
ATSAM4Lx8
256 bytes
64Kbytes
64Kbytes
AESA
0x400B0000
0x400E0000
0x400F0000
Peripheral Bridge C
Peripheral Bridge D
Table 5-2.
Flash Memory Parameters
Device
ATSAM4Lx8
Flash Size (FLASH_PW)
Number of Pages (FLASH_P)
Page Size (FLASH_W)
512 bytes
512Kbytes
256Kbytes
128Kbytes
1024
512
ATSAM4Lx4
ATSAM4Lx2
512 bytes
256
512 bytes
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6. Power and Startup Considerations
6.1
Power Domain Overview
Figure 6-1. ATSAM4LS Power Domain Diagram
CORE DOMAIN
DUAL OUTPUT
TRIMMABLE
VOLTAGE
CORTEX M4
CPU
PDCA
USBC
RAM
FLASH
REGULATOR
BUS MATRIX
VDDANA DOMAIN
PERIPHERAL BRIDGE A
PERIPHERALS
PERIPHERAL BRIDGE B
AHB PERIPHERALS
AD0-AD14
ADVREF
ADC
AC0A-AC3A
AC0B-AC3B
ANALOG
COMPARATORS
PERIPHERAL BRIDGE C
GPIO
DAC
DACOUT
POWER MANAGER
FREQUENCY
METER
STARTUP
LOGIC
PLL
VDDIO DOMAIN
POR33
BOD33
BOD18
DFLL
SYSTEM
CONTROL INTERFACE
USB
PADS
RCSYS
RCFAST
MPOSC
PERIPHERAL BRIDGE D
GPIOs
RC80M
BACKUP
POWER MANAGER
RC32K
BACKUP SYSTEM
XIN32
CONTROL INTERFACE
OSC32K
VDDIO
GND
POR18
XOUT32
EXTERNAL INTERRUPT
CONTROLLER
WATCHDOG
TIMER
EXTINT0-EXTINT8
BACKUP
REGISTERS
ASYNCHRONOUS TIMER
VDDANA
GNDANA
BACKUP DOMAIN
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Figure 6-2. ATSAM4LC Power Domain Diagram
GND
VLCDIN
LCDA DOMAIN
CAPH
CAPL
BIASH
BIASL
CORE DOMAIN
DUAL OUTPUT
TRIMMABLE
VOLTAGE
LCD
VPUMP
CORTEX M4
CPU
PDCA
USBC
RAM
FLASH
REGULATOR
VLCD
BUS MATRIX
GPIOs
VDDANA DOMAIN
PERIPHERAL BRIDGE A
PERIPHERALS
PERIPHERAL BRIDGE B
AHB PERIPHERALS
AD0-AD14
ADVREF
LCDB DOMAIN
ADC
VDDIO
VDDIO
AC0A-AC3A
AC0B-AC3B
ANALOG
COMPARATORS
GPIOs
LCDC DOMAIN
GPIOs
PERIPHERAL BRIDGE C
GPIO
DAC
DACOUT
POWER MANAGER
FREQUENCY
METER
STARTUP
LOGIC
PLL
VDDIO DOMAIN
POR33
BOD33
BOD18
DFLL
SYSTEM
CONTROL INTERFACE
USB
PADS
RCSYS
RCFAST
MPOSC
PERIPHERAL BRIDGE D
GPIOs
RC80M
BACKUP
POWER MANAGER
RC32K
BACKUP SYSTEM
CONTROL INTERFACE
XIN32
OSC32K
VDDIO
GND
POR18
XOUT32
EXTERNAL INTERRUPT
CONTROLLER
WATCHDOG
TIMER
EXTINT0-EXTINT8
BACKUP
REGISTERS
ASYNCHRONOUS TIMER
VDDANA
GNDANA
BACKUP DOMAIN
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6.2
Power Supplies
The ATSAM4L8/L4/L2 has several types of power supply pins:
• VDDIO: Powers I/O lines, the general purpose oscillator (OSC), the 80MHz integrated RC
oscillator (RC80M) . Voltage is 1.68V to 3.6V.
• VLCDIN: (ATSAM4LC only) Powers the LCD voltage pump. Voltage is 1.68V to 3.6V.
• VDDIN: Powers the internal voltage regulator. Voltage is 1.68V to 3.6V.
• VDDANA: Powers the ADC, the DAC, the Analog Comparators, the 32kHz oscillator
(OSC32K), the 32kHz integrated RC oscillator (RC32K)and the Brown-out detectors (BOD18
and BOD33). Voltage is 1.68V to 3.6V nominal.
• VDDCORE: Powers the core, memories, peripherals, the PLL, the DFLL, the 4MHz
integrated RC oscillator (RCFAST) and the 115kHz integrated RC oscillator (RCSYS).
– VDDOUT is the output voltage of the regulator and must be connected with or
without an inductor to VDDCORE.
The ground pins GND are common to VDDCORE, VDDIO, and VDDIN. The ground pin for
VDDANA is GNDANA.
For decoupling recommendations for the different power supplies, refer to the schematic
document.
6.2.1
Voltage Regulator
An embedded voltage regulator supplies all the digital logic in the Core and the Backup power
domains.
The regulator has two functionnal mode depending of BUCK/LDOn (PA02) pin value. When this
pin is low, the regulator is in linear mode and VDDOUT must be connected to VDDCORE exter-
nally. When this pin is high, it behaves as a switching regulator and an inductor must be placed
between VDDOUT and VDDCORE. The value of this pin is sampled during the power-up phase
when the Power On Reset 33 reaches VPOT+ (Section 9.9 ”Analog Characteristics” on page 129)
Its output voltages in the Core domain (VCORE) and in the Backup domain (VBKUP) are always
equal except in Backup mode where the Core domain is not powered (VCORE=0). The Backup
domain is always powered. The voltage regulator features three different modes:
• Normal mode: the regulator is configured as linear or switching regulator. It can support all
different Run and Sleep modes.
• Low Power (LP) mode: the regulator consumes little static current. It can be used in Wait
modes.
• Ultra Low Power (ULP) mode: the regulator consumes very little static current . It is dedicated
to Retention and Backup modes. In Backup mode, the regulator only supplies the backup
domain.
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6.2.2
Typical Powering Schematics
The ATSAM4L8/L4/L2 supports the Single supply mode from 1.68V to 3.6V. Depending on the
input voltage range and on the final application frequency, it is recommended to use the follow-
ing table in order to choose the most efficient power strategy
Figure 6-3. Efficient power strategy:
VDDIN Voltage
2.30V
3.60V
1.68V 1.80V
N/A
2.00V
Switching Mode
(BUCK/LDOn
(PA02) =1)
Possible but
not efficient
Optimal power efficiency
Possible but not efficient
Linear Mode
(BUCK/LDOn
(PA02) =0)
Optimal power efficiency
Up to 36MHz In PS0
Up to 12MHz in PS1
Up to 48MHz in PS2
FCPUMAX
12MHz
PS1(1)
PowerScaling
ALL
Typical power
consumption in
RUN mode
ℵ
ℵ
212µA/MHz @ FCPU=12MHz(PS1)
306µA/MHz @ FCPU= 48MHz(PS2)
ℵ
ℵ
100µA/MHz @ FCPU=12MHz(PS1) @ VVDDIN=3.3V
180µA/MHz @ FCPU=48MHz(PS2) @ VVDDIN=3.3V
Typical power
consumption in
RET mode
1.5µA
Note 1. The SAM4L boots in PS0 on RCSYS(115kHz), then the application must switch to
PS1 before running on higher frequency (<12MHz)
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The internal regulator is connected to the VDDIN pin and its output VDDOUT feeds VDDCORE
in linear mode or through an inductor in switching mode. Figure 6-4 shows the power schematics
to be used. All I/O lines will be powered by the same power (VVDDIN=VVDDIO=VVDDANA).
Figure 6-4. Single Supply Mode
VLCDIN
LCD VPUMP
VDDIO
RC80M, OSC,
Main Supply
(1.68V-3.6V)
ADC, DAC, AC0/1,
RC32K, OSC32K,
BOD18, BOD33
VDDANA
BUCK/LDOn
(PA02)
Core domain: CPU,
Peripherals, RAM, Flash,
RCSYS, PLL, DFLL,
RCFAST
VDDIN
REGULATOR
VDDOUT
VDDCORE
Backup domain:
AST, WDT, EIC,
BPM, BSCIF
6.2.3
LCD Power Modes
6.2.3.1
Principle
LCD lines is powered using the device internal voltage sources provided by the LCDPWR block.
When enabled, the LCDPWR blocks will generate the VLCD, BIASL, BIASH voltages.
LCD pads are splitted into three clusters that can be powered independently namely clusters A,
B and C. A cluster can either be in GPIO mode or in LCD mode.
When a cluster is in GPIO mode, its VDDIO pin must be powered externally. None of its GPIO
pin can be used as a LCD line
When a cluster is in LCD mode, each clusters VDDIO pin can be either forced externally (1.8-
3.6V) or unconnected (nc). GPIOs in a cluster are not available when it is in LCD mode. A clus-
ter is set in LCD mode by the LCDCA controller when it is enabled depending on the number of
segments configured. The LCDPWR block is powered by the VLCDIN pin inside cluster A
When LCD feature is not used, VLCDIN must be always powered (1.8-3.6V). VLCD, CAPH,
CAPL, BIASH, BIASL can be left unconnected in this case
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Figure 6-5. LCD clusters in the device
SEG18
SEG19
SEG20
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
VDDIO
VDDIO
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
COM0
COM1
COM2
COM3
SEG21
SEG22
SEG23
SEG9
SEG10
SEG11
VDDIO
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
COM0
COM1
COM2
COM3
SEG12
SEG13
SEG14
VDDANA
SEG5
SEG6
SEG7
VDDIO
SEG9
SEG10
SEG11
SEG12
VDDIO
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
COM0
COM1
COM2
COM3
SEG8
SEG15
SEG16
SEG17
SEG18
SEG19
VDDANA
TQFP48/QFN48
GNDANA
SEG20
SEG21
SEG22
VDDIO
GNDANA
GND
VDDANA
GNDANA
GND
TQFP64/QFN64
GND
TQFP100
6.2.3.2
Internal LCD Voltage
In this mode the LCD voltages are internally generated. Depending of the number of segments
required by the application, LCDB and LDCC clusters VDDIO pin must be unconnected (nc) or
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ATSAM4L8/L4/L2
connected to an external voltage source (1.8-3.6V). LCDB cluster is not available in 64 and 48
pin packages
Table 6-1.
LCD powering when using the internal voltage pump
VDDIO
LCDB
VDDIO
LCDC
Segments
in use
Package
[1,24]
[1, 32]
[1, 40]
[1,15]
[1, 23]
[1,9]
1.8-3.6V
1.8-3.6V
1.8-3.6V
nc
nc
nc
-
100-pin packages
1.8-3.6V
nc
64-pin packages
48-pin packages
-
-
1.8-3.6V
nc
[1,13]
-
Up to 4x24 segments
Up to 16 GPIOs in
LCDB & LCDC
clusters
Up to 4x40 segments
No GPIO in LCD
clusters
Up to 4x32 segments
Up to 8 GPIOs in
LCDC clusters
1.8–3.6V
GND
1.8–3.6V
GND
1.8–3.6V
GND
LCDA DOMAIN
LCDA DOMAIN
LCDA DOMAIN
CAPH
CAPH
CAPH
CAPL
BIASH
BIASL
CAPL
BIASH
BIASL
CAPL
LCD
VPUMP
LCD
VPUMP
LCD
VPUMP
BIASH
BIASL
VLCD
VLCD
VLCD
GPIOs
GPIOs
GPIOs
1.8–3.6V
LCDB DOMAIN
GPIOs
LCDB DOMAIN
GPIOs
LCDB DOMAIN
GPIOs
VDDIO
nc
VDDIO
nc
VDDIO
LCDC DOMAIN
GPIOs
LCDC DOMAIN
GPIOs
LCDC DOMAIN
GPIOs
1.8–3.6V
VDDIO
VDDIO
nc
VDDIO
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6.2.4
Power-up Sequence
6.2.4.1
Maximum Rise Rate
To avoid risk of latch-up, the rise rate of the power supplies must not exceed the values
described in Table 9-3 on page 100.
6.2.4.2
Minimum Rise Rate
The integrated Power-on Reset (POR33) circuitry monitoring the VDDIN powering supply
requires a minimum rise rate for the VDDIN power supply.
See Table 9-3 on page 100 for the minimum rise rate value.
If the application can not ensure that the minimum rise rate condition for the VDDIN power sup-
ply is met, the following configuration can be used:
• A logic “0” value is applied during power-up on pin RESET_N until VDDIN rises above 1.6 V.
6.3
Startup Considerations
This section summarizes the boot sequence of the ATSAM4L8/L4/L2. The behavior after power-
up is controlled by the Power Manager. For specific details, refer to Section 9. ”Power Manager
(PM)” on page 677.
6.3.1
Starting of Clocks
After power-up, the device will be held in a reset state by the power-up circuitry for a short time
to allow the power to stabilize throughout the device. After reset, the device will use the System
RC Oscillator (RCSYS) as clock source. Refer to Section 9. ”Electrical Characteristics” on page
99 for the frequency for this oscillator.
On system start-up, the DFLL and the PLLs are disabled. Only the necessary clocks are active
allowing software execution. Refer to Section 3-6 ”Maskable Module Clocks in AT32UC3B.” on
page 24 to know the list of peripheral clock running.. No clocks have a divided frequency; all
parts of the system receive a clock with the same frequency as the System RC Oscillator.
6.3.2
Fetching of Initial Instructions
After reset has been released, the Cortex M4 CPU starts fetching PC and SP values from the
reset address, which is 0x00000000. Refer to the ARM Architecture Reference Manual for more
information on CPU startup. This address points to the first address in the internal Flash.
The code read from the internal flash is free to configure the clock system and clock sources.
6.4
Power-on-Reset, Brownout and Supply Monitor
The SAM4L embeds four features to monitor, warm, and/or reset the device:
• POR33: Power-on-Reset on VDDANA
• BOD33: Brownout detector on VDDANA
• POR18: Power-on-Reset on VDDCORE
• BOD18: Brownout detector on VDDCORE
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Figure 6-6. Supply Monitor Schematic
DUAL OUTPUT
TRIMMABLE
VOLTAGE
VDDCORE
REGULATOR
VDDANA
POR33
BOD33
POR18
BOD18
VDDANA
GNDANA
6.4.1
6.4.2
6.4.3
6.4.4
Power-on-Reset on VDDANA
POR33 monitors VDDANA. It is always activated and monitors voltage at startup but also during
all the Power Save Mode. If VDDANA goes below the threshold voltage, the entire chip is reset.
Brownout Detector on VDDANA
BOD33 monitors VDDANA. Refer to Section 15. ”Backup System Control Interface (BSCIF)” on
page 308to get more details.
Power-on-Reset on VDDCORE
POR18 monitors the internal VDDCORE. Refer to Section 15. ”Backup System Control Interface
(BSCIF)” on page 308 to get more details.
Brownout Detector on VDDCORE
Once the device is startup, the BOD18 monitors the internal VDDCORE. Refer to Section 15.
”Backup System Control Interface (BSCIF)” on page 308 to get more details.
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7. Low Power Techniques
The ATSAM4L8/L4/L2 supports multiple power configurations to allow the user to optimize its
power consumption in different use cases. The Backup Power Manager (BPM) implements dif-
ferent solutions to reduce the power consumption:
• The Power Save modes intended to reduce the logic activity and to adapt the power
configuration. See ”Power Save Modes” on page 55.
• The Power Scaling intended to scale the power configuration (voltage scaling of the
regulator). See ”Power Scaling” on page 60.
These two techniques can be combined together.
Figure 7-1. Power Scaling and Power Save Mode Overview
POWER SCALING
Max frequency = 36Mhz Max frequency = 12Mhz Max frequency = 48Mhz
Normal Speed Flash
Nominal Voltage
Normal Speed Flash
Reduced Voltage
High Speed Flash
Nominal Voltage
RESET
BPM.PMCON.PS=0
BPM.PMCON.PS=1
BPM.PMCON.PS=2
RUN
RUN0
SLEEP0
WAIT0
RET0
RUN1
SLEEP1
WAIT1
RET1
RUN2
SLEEP2
WAIT2
RET2
SLEEP
CPU Clock OFF
4 sub-modes
WAIT
All Clocks OFF
SleepWalking
RETENTION
All Clocks OFF
Full chip retention
BACKUP
BKUP0
BKUP1
BKUP2
Core Domain OFF
7.1
Power Save Modes
Refer to Section 6. ”Power and Startup Considerations” on page 46 to get definition of the core
and the backup domains.
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At power-up or after a reset, the ATSAM4L8/L4/L2 is in the RUN0 mode. Only the necessary
clocks are enabled allowing software execution. The Power Manager (PM) can be used to adjust
the clock frequencies and to enable and disable the peripheral clocks.
When the CPU is entering a Power Save Mode, the CPU stops executing code. The user can
choose between four Power Save Modes to optimize power consumption:
• SLEEP mode: the Cortex-M4 core is stopped, optionally some clocks are stopped,
peripherals are kept running if enabled by the user.
• WAIT mode: all clock sources are stopped, the core and all the peripherals are stopped
except the modules running with the 32kHz clock if enabled. This is the lowest power
configuration where SleepWalking is supported.
• RETENTION mode: similar to the WAIT mode in terms of clock activity. This is the lowest
power configuration where the logic is retained.
• BACKUP mode: the Core domain is powered off, the Backup domain is kept powered.
A wake up source exits the system to the RUN mode from which the Power Save Mode was
entered.
A reset source always exits the system from the Power Save Mode to the RUN0 mode.
The configuration of the I/O lines are maintained in all Power Save Modes. Refer to Section 9.
”Backup Power Manager (BPM)” on page 677.
7.1.1
SLEEP mode
The SLEEP mode allows power optimization with the fastest wake up time.
The CPU is stopped. To further reduce power consumption, the user can switch off modules-
clocks and synchronous clock sources through the BPM.PMCON.SLEEP field (See Table 7-1).
The required modules will be halted regardless of the bit settings of the mask registers in the
Power Manager (PM.AHBMASK, PM.APBxMASK).
Table 7-1.
SLEEP mode Configuration
Clock sources:
OSC, RCFAST,
RC80M, PLL,
DFLL
APB clocks
GCLK
OSC32K
CPU
clock
AHB
clocks
BPM.PSAVE.SLEEP
RCSYS RC32K(2)
Wake up Sources
Any interrupt
0
1
2
3
Stop
Stop
Stop
Stop
Run
Stop
Stop
Stop
Run
Run
Stop
Stop
Run
Run
Run
Stop
Run
Run
Run
Run
Run
Run
Run
Run
Any interrupt(1)
Any interrupt(1)
Any interrupt(1)
Notes: 1. from modules with clock running.
2. OSC32K and RC32K will only remain operational if pre-enabled.
7.1.1.1
Entering SLEEP mode
The SLEEP mode is entered by executing the WFI instruction.
Additionally, if the SLEEPONEXIT bit in the Cortex-M4 System Control Register (SCR) is set,
the SLEEP mode will also be entered when the Cortex-M4 exits the lowest priority ISR. This
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mechanism can be useful for applications that only require the processor to run when an inter-
rupt occurs.
Before entering the SLEEP mode, the user must configure:
• the SLEEP mode configuration field (BPM.PMCON.SLEEP), Refer to Table 7-1.
• the SCR.SLEEPDEEP bit to 0. (See the Power Management section in the ARM Cortex-M4
Processor chapter).
• the BPM.PMCON.RET bit to 0.
• the BPM.PMCON.BKUP bit to 0.
7.1.1.2
Exiting SLEEP mode
The NVIC wakes the system up when it detects any non-masked interrupt with sufficient priority
to cause exception entry. The system goes back to the RUN mode from which the SLEEP mode
was entered. The CPU and affected modules are restarted. Note that even if an interrupt is
enabled in SLEEP mode, it will not trigger if the source module is not clocked.
7.1.2
WAIT Mode and RETENTION Mode
The WAIT and RETENTION modes allow achieving very low power consumption while main-
taining the Core domain powered-on. Internal SRAM and registers contents of the Core domain
are preserved.
In these modes, all clocks are stopped except the 32kHz clocks (OSC32K, RC32K) which are
kept running if enabled.
In RETENTION mode, the SleepWalking feature is not supported and must not be used.
7.1.2.1
Entering WAIT or RETENTION Mode
The WAIT or RETENTION modes are entered by executing the WFI instruction with the follow-
ing settings:
• set the SCR.SLEEPDEEP bit to 1. (See the Power Management section in the ARM Cortex-
M4 Processor chapter).
• set the BPM.PSAVE.BKUP bit to 0.
• set the BPM.PMCON.RET bit to RETENTION or WAIT mode.
SLEEPONEXIT feature is also available. See ”Entering SLEEP mode” on page 56.
7.1.2.2
Exiting WAIT or RETENTION Mode
In WAIT or RETENTION modes, synchronous clocks are stopped preventing interrupt sources
from triggering. To wakeup the system, asynchronous wake up sources (AST, EIC, USBC ...)
should be enabled in the peripheral (refer to the documentation of the peripheral). The
PM.AWEN (Asynchronous Wake Up Enable) register should also be enabled for all peripheral
except for EIC and AST.
When the enabled asynchronous wake up event occurs and the system is waken-up, it will gen-
erate either:
• an interrupt on the PM WAKE interrupt line if enabled (Refer to Section 9. ”Power Manager
(PM)” on page 677). In that case, the PM.WCAUSE register indicates the wakeup source.
• or an interrupt directly from the peripheral if enabled (Refer to the section of the peripheral).
When waking up, the system goes back to the RUN mode mode from which the WAIT or
RETENTION mode was entered.
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7.1.3
BACKUP Mode
The BACKUP mode allows achieving the lowest power consumption possible in a system which
is performing periodic wake-ups to perform tasks but not requiring fast startup time.
The Core domain is powered-off. The internal SRAM and register contents of the Core domain
are lost. The Backup domain is kept powered-on. The 32kHz clock (RC32K or OSC32K) is kept
running if enabled to feed modules that require clocking.
In BACKUP mode, the configuration of the I/O lines is preserved. Refer to Section 9. ”Backup
Power Manager (BPM)” on page 677 to have more details.
7.1.3.1
7.1.3.2
Entering BACKUP Mode
The Backup mode is entered by using the WFI instruction with the following settings:
• set the SCR.SLEEPDEEP bit to 1. (See the Power Management section in the ARM Cortex-
M4 Processor chapter).
• set the BPM.PSAVE.BKUP bit to 1.
Exiting BACKUP Mode
Exit from BACKUP mode happens if a reset occurs or if an enabled wake up event occurs.
The reset sources are:
• BOD33 reset
• BOD18 reset
• WDT reset
• External reset in RESET_N pin
The wake up sources are:
• EIC lines (level transition only)
• BOD33 interrupt
• BOD18 interrupt
• AST alarm, periodic, overflow
• WDT interrupt
The RC32K or OSC32K should be used as clock source for modules if required. The
PMCON.CK32S is used to select one of these two 32kHz clock sources.
Exiting the BACKUP mode is triggered by:
• a reset source: an internal reset sequence is performed according to the reset source. Once
VDDCORE is stable and has the correct value according to RUN0 mode, the internal reset is
released and program execution starts. The corresponding reset source is flagged in the
Reset Cause register (RCAUSE) of the PM.
• a wake up source: the Backup domain is not reset. An internal reset is generated to the Core
domain, and the system switches back to the previous RUN mode. Once VDDCORE is
stable and has the correct value, the internal reset in the Core domain is released and
program execution starts. The BKUP bit is set in the Reset Cause register (RCAUSE) of the
PM. It allows the user to discriminate between the reset cause and a wake up cause from the
BACKUP mode. The wake up cause can be found in the Backup Wake up Cause register
(BPM.BKUPWCAUSE).
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7.1.4
Wakeup Time
7.1.4.1
Wakeup Time From SLEEP Mode
The latency depends on the clock sources wake up time. If the clock sources are not stopped,
there is no latency to wake the clocks up.
7.1.4.2
Wakeup Time From WAIT or RETENTION Mode
The wake up latency consists of:
• the switching time from the low power configuration to the RUN mode power configuration.
By default, the switching time is completed when all the voltage regulation system is ready.
To speed-up the startup time, the user can set the Fast Wakeup bit in BPM.PMCON register.
• the wake up time of the RC oscillator used to start the system up. By default, the RCSYS
oscillator is used to startup the system. The user can use another clock source (RCFAST for
example) to speed up the startup time by configuring the PM.FASTWKUP register. Refer to
Section 9. ”Power Manager (PM)” on page 677.
• the Flash memory wake up time.
To have the shortest wakeup time, the user should:
- set the BPM.PMCON.FASTWKUP bit.
- configure the PM.FASTSLEEP.FASTRCOSC field to use the RCFAST main clock.
- enter the WAIT or RETENTION mode
Upon a wakeup, this is required to keep the main clock connected to RCFAST until the voltage
regulation system is fully ready (when BPM.ISR.PSOK bit is one). During this wakeup period,
the FLASHCALW module is automatically configured to operate in “1 wait state mode”.
7.1.4.3
Wake time from BACKUP mode
It is equal to the Core domain logic reset latency (similar to the reset latency caused by an exter-
nal reset in RESET_N pin) added to the time required for the voltage regulation system to be
stabilized.
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7.1.5
Power Save Mode Summary Table
The following table shows a summary of the main Power Save modes:
Table 7-2.
Mode
Power Save mode Configuration Summary
Core
Backup
domain
Mode Entry
Wake up sources
domain
CPU clock OFF
Clocks OFF depending on
the BPM.PMCON.SLEEP
field
Other clocks OFF depending
on the BPM.PMCON.SLEEP
field
WFI
SLEEP
SCR.SLEEPDEEP bit = 0
BPM.PMCON.BKUP bit = 0
Any interrupt
see ”SLEEP mode” on page
56
see ”SLEEP mode” on page
56
WFI
All clocks are OFF except
RC32K or OSC32K if
running
SCR.SLEEPDEEP bit = 1
BPM.PMCON.RET bit = 0
BPM.PMCON.BKUP bit = 0
All clocks are OFF
WAIT
PM WAKE interrupt
Core domain is retained
WFI
All clocks are OFF except
RC32K or OSC32K if
running
SCR.SLEEPDEEP bit = 1
BPM.PMCON.RET bit = 1
BPM.PMCON.BKUP bit = 0
All clocks are OFF
RETENTION
PM WAKE interrupt
EIC interrupt
Core domain is retained
BOD33, BOD18 interrupt
and reset
WFI
All clocks are OFF except
RC32K or OSC32K if
running
AST alarm, periodic,
overflow
BACKUP
+ SCR.SLEEPDEEP bit = 1
+ BPM.PMCON.BKUP bit = 1
OFF (not powered)
WDT interrupt and reset
external reset on RESET_N
pin
7.2
Power Scaling
The Power Scaling technique consists of adjusting the internal regulator output voltage (voltage
scaling) to reduce the power consumption. According to the requirements in terms of perfor-
mance, operating modes, and current consumption, the user can select the Power Scaling
configuration that fits the best with its application.
The Power Scaling configuration field (PMCON.PS) is provided in the Backup Power Manager
(BPM) module.
In RUN mode, the user can adjust on the fly the Power Scaling configuration
The Figure 7.1 summarizes the different combination of the Power Scaling configuration which
can be applied according to the Power Save Mode.
Power scaling from a current power configuration to a new power configuration is done by halt-
ing the CPU execution
Power scaling occurs after a WFI instruction. The system is halted until the new power configu-
ration is stabilized. After handling the PM interrupt, the system resumes from WFI.
To scale the power, the following sequence is required:
• Check the BPM.SR.PSOK bit to make sure the current power configuration is stabilized.
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• Set the clock frequency to be supported in both power configurations.
• Set the high speed read mode of the FLASH to be supported in both power scaling
configurations
– Only relevant when entering or exiting BPM.PMCON.PS=2
• Configure the BPM.PMCON.PS field to the new power configuration.
• Set the BPM.PMCON.PSCREQ bit to one.
• Disable all the interrupts except the PM WCAUSE interrupt and enable only the PSOK
asynchronous event in the AWEN register of PM.
• Execute the WFI instruction.
• WAIT for PM interrupt.
The new power configuration is reached when the system is waken up by the PM interrupt
thanks to the PSOK event.
By default, all features are available in all Power Scaling modes. However some specific fea-
tures are not available in PS1 (BPM.PMCON.PS=1) mode :
– USB
– DFLL
– PLL
– Programming/Erasing in Flash
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8. Debug and Test
8.1
Features
• IEEE1149.1 compliant JTAG Debug Port
• Serial Wire Debug Port
• Boundary-Scan chain on all digital pins for board-level testing
• Direct memory access and programming capabilities through debug ports
• Flash Patch and Breakpoint (FPB) unit for implementing breakpoints and code patches
• Data Watchpoint and Trace (DWT) unit for implementing watchpoints, data tracing, and system
profiling
• Instrumentation Trace Macrocell (ITM) for support of printf style debugging
• Chip Erase command and status
• Unlimited Flash User page read access
• Cortex-M4 core reset source
• CRC32 of any memory accessible through the bus matrix
• Debugger Hot Plugging
8.2
Overview
Debug and test features are made available to external tools by:
• The Enhanced Debug Port (EDP) embedding:
– a Serial Wire Debug Port (SW-DP) part of the ARM coresight architecture
– an IEEE 1149.1 JTAG Debug Debug Port (JTAG-DP) part of the ARM coresight
architecture
– a supplementary IEEE 1149.1 JTAG TAP machine that implements the boundary
scan feature
• The System Manager Acces Port (SMAP) providing unlimited flash User page read access,
CRC32 of any memory accessible through the bus matrix and Cortex-M4 core reset services
• The AHB Access Port (AHB-AP) providing Direct memory access, programming capabilities
and standard debugging functions
• The Instrumentation Trace macrocell part of the ARM coresight architecture
For more information on ARM debug components, please refer to:
• ARMv7-M Architecture Reference Manual
• ARM Debug Interface v5.1 Architecture Specification document
• ARM CoreSight Architecture Specification
• ARM ETM Architecture Specification v3.5
• ARM Cortex-M4 Technical Reference Manual
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8.3
Block diagram
Figure 8-1. Debug and Test Block Diagram
CORTEX-M4
ENHANCED
DEBUG PORT
TPIU
TMS
TDI
PORT
Core
Data
MUXING
AHB-AP
TDO
Instr
DAP Bus
SWJ-DP
TCK
Boundary
FPB
DWT
NVIC
ITM
BSCAN-TAP
scan
Hot_plugging
JTAG-FILTER
RESET_N
Private peripheral Bus (PPB)
M
EDP Core reset request
AHB
APB
HTOP
S
SMAP
SMAP Core reset request
Chip Erase
M
AHB
AHB
System Bus Matrix
RESET
CONTROLLER
POR
Cortex-M4 Core reset
note: Boxes with a plain corner are SAM4L specific.
8.4
I/O Lines Description
Refer to Section 1.1.4 ”I/O Lines Description” on page 4.
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8.5
Product dependencies
8.5.1
I/O Lines
Refer to Section 1.1.5.1 ”I/O Lines” on page 5.
8.5.2
8.5.3
Power management
Refer to Section 1.1.5.2 ”Power Management” on page 5.
Clocks
Refer to Section 1.1.5.3 ”Clocks” on page 5.
8.6
Core debug
Figure 8-2 shows the Debug Architecture used in the SAM4L. The Cortex-M4 embeds four func-
tional units for debug:
• FPB (Flash Patch Breakpoint)
• DWT (Data Watchpoint and Trace)
• ITM (Instrumentation Trace Macrocell)
• TPIU (Trace Port Interface Unit)
The debug architecture information that follows is mainly dedicated to developers of SWJ-DP
Emulators/Probes and debugging tool vendors for Cortex-M4 based microcontrollers. For further
details on SWJ-DP see the Cortex-M4 technical reference manual.
Figure 8-2. Debug Architecture
DWT
4 watchpoints
PC sampler
FPB
SWJ-DP
6 breakpoints
data address sampler
SWD/JTAG
SWO trace
ITM
data sampler
interrupt trace
CPU statistics
software trace
32 channels
TPIU
time stamping
8.6.1
FPB (Flash Patch Breakpoint)
The FPB:
• Implements hardware breakpoints
• Patches (on the fly) code and data being fetched by the Cortex-M4 core from code space
with data in the system space. Definition of code and system spaces can be found in the
System Address Map section of the ARMv7-M Architecture Reference Manual.
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The FPB unit contains:
• Two literal comparators for matching against literal loads from Code space, and remapping to
a corresponding area in System space.
• Six instruction comparators for matching against instruction fetches from Code space and
remapping to a corresponding area in System space.
• Alternatively, comparators can also be configured to generate a Breakpoint instruction to the
processor core on a match.
8.6.2
DWT (Data Watchpoint and Trace)
The DWT contains four comparators which can be configured to generate the following:
• PC sampling packets at set intervals
• PC or Data watchpoint packets
• Watchpoint event to halt core
The DWT contains counters for the items that follow:
• Clock cycle (CYCCNT)
• Folded instructions
• Load Store Unit (LSU) operations
• Sleep Cycles
• CPI (all instruction cycles except for the first cycle)
• Interrupt overhead
8.6.3
ITM (Instrumentation Trace Macrocell)
The ITM is an application driven trace source that supports printf style debugging to trace Oper-
ating System (OS) and application events, and emits diagnostic system information. The ITM
emits trace information as packets which can be generated by three different sources with sev-
eral priority levels:
• Software trace: This can be done thanks to the printf style debugging. For more information,
refer to Section “How to Configure the ITM:”.
• Hardware trace: The ITM emits packets generated by the DWT.
• Time stamping: Timestamps are emitted relative to packets. The ITM contains a 21-bit
counter to generate the timestamp.
How to Configure the ITM:
The following example describes how to output trace data in asynchronous trace mode.
• Configure the TPIU for asynchronous trace mode (refer to Section “5.4.3. How to Configure
the TPIU”)
• Enable the write accesses into the ITM registers by writing “0xC5ACCE55” into the
Lock Access Register (Address: 0xE0000FB0)
• Write 0x00010015 into the Trace Control Register:
– Enable ITM
– Enable Synchronization packets
– Enable SWO behavior
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– Fix the ATB ID to 1
• Write 0x1 into the Trace Enable Register:
– Enable the Stimulus port 0
• Write 0x1 into the Trace Privilege Register:
– Stimulus port 0 only accessed in privileged mode (Clearing a bit in this register will
result in the corresponding stimulus port being accessible in user mode.)
• Write into the Stimulus port 0 register: TPIU (Trace Port Interface Unit)
The TPIU acts as a bridge between the on-chip trace data and the Instruction Trace Macro-
cell (ITM).
The TPIU formats and transmits trace data off-chip at frequencies asynchronous to the core.
Asynchronous Mode:
The TPIU is configured in asynchronous mode, trace data are output using the single TRAC-
ESWO pin. The TRACESWO signal is multiplexed with the TDO signal of the JTAG Debug Port.
As a consequence, asynchronous trace mode is only available when the Serial Wire Debug
mode is selected since TDO signal is used in JTAG debug mode.
Two encoding formats are available for the single pin output:
• Manchester encoded stream. This is the reset value.
• NRZ_based UART byte structure
5.4.3. How to Configure the TPIU
This example only concerns the asynchronous trace mode.
• Set the TRCENA bit to 1 into the Debug Exception and Monitor Register (0xE000EDFC) to
enable the use of trace and debug blocks.
• Write 0x2 into the Selected Pin Protocol Register
– Select the Serial Wire Output – NRZ
• Write 0x100 into the Formatter and Flush Control Register
• Set the suitable clock prescaler value into the Async Clock Prescaler Register to scale the
baud rate of the asynchronous output (this can be done automatically by the debugging tool).
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8.7
Enhanced Debug Port (EDP)
Rev.: 1.0.0.0
8.7.1
Features
• IEEE1149.1 compliant JTAG debug port
• Serial Wire Debug Port
• Boundary-Scan chain on all digital pins for board-level testing
• Debugger Hot-Plugging
• SMAP core reset request source
8.7.2
Overview
The enhanced debug port embeds a standard ARM debug port plus some specific hardware
intended for testability and activation of the debug port features. All the information related to the
ARM Debug Interface implementation can be found in the ARM Debug Interface v5.1 Architec-
ture Specification document.
It features:
• A single Debug Port (SWJ-DP), that provides the external physical connection to the
interface and supports two DP implementations:
– the JTAG Debug Port (JTAG-DP)
– the Serial Wire Debug Port (SW-DP)
• A supplementary JTAG TAP (BSCAN-TAP) connected in parallel with the JTAG-DP that
implements the boundary scan instructions detailed in
• A JTAG-FILTER module that monitors TCK and RESET_N pins to handle specific features
like the detection of a debugger hot-plugging and the request of reset of the Cortex-M4 at
startup.
The JTAG-FILTER module detects the presence of a debugger. When present, JTAG pins are
automatically assigned to the Enhanced Debug Port(EDP). If the SWJ-DP is switched to the SW
mode, then TDI and TDO alternate functions are released. The JTAG-FILTER also implements a
CPU halt mechanism. When triggered, the Cortex-M4 is maintained under reset after the exter-
nal reset is released to prevent any system corruption during later programmation operations.
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8.7.3
Figure 8-3. Enhanced Debug Port Block Diagram
ENHANCED DEBUG PORT
Block Diagram
SWJ-DP
swdio
TMS
TDI
traceswo
SW-DP
TDO
swclk
TCK
DAP Bus
tms
tdi
JTAG-DP
tdo
tck
test_tap_sel
tms
tdi
BSCAN-TAP
boundary_scan
tdo
tck
tck
JTAG-FILTER
EDP Core reset request
reset_n
RESET_N
8.7.4
I/O Lines Description
Table 8-1.
Name
I/O Lines Description
JTAG Debug Port
Type Description
SWD Debug Port
Type Description
TCK/SWCLK
TDI
I
I
Debug Clock
I
-
Serial Wire Clock
NA
Debug Data in
Debug Data Out
Debug Mode Select
Reset
TDO/TRACESWO
TMS/SWDIO
RESET_N
O
I
O
I/O
I
Trace asynchronous Data Out
Serial Wire Input/Output
Reset
I
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8.7.5
Product Dependencies
8.7.5.1
I/O Lines
The TCK pin is dedicated to the EDP. The other debug port pins default after reset to their GPIO
functionality and are automatically reassigned to the JTAG functionalities on detection of a
debugger. In serial wire mode, TDI and TDO can be used as GPIO functions. Note that in serial
wire mode TDO can be used as a single pin trace output.
8.7.5.2
8.7.5.3
Power Management
When a debugger is present, the connection is kept alive allowing debug operations. As a side
effect, the power is never turned off. The hot plugging functionality is always available except
when the system is in BACKUP Power Save Mode.
Clocks
The SWJ-DP uses the external TCK pin as its clock source. This clock must be provided by the
external JTAG master device.
Some of the JTAG Instructions are used to access an Access Port (SMAP or AHB-AP). These
instructions require the CPU clock to be running.
If the CPU clock is not present because the CPU is in a Power Save Mode where this clock is
not provided, the Power Manager(PM) will automatically restore the CPU clock on detection of a
debug access.
The RCSYS clock is used as CPU clock when the external reset is applied to ensure correct
Access Port operations.
8.7.6
Module Initialization
This module is enabled as soon as a TCK falling edge is detected when RESET_N is not
asserted (refer to Section 8.7.7 below). Moreover, the module is synchronously reseted as long
as the TAP machine is in the TEST_LOGIC_RESET (TLR) state. It is advised asserting TMS at
least 5 TCK clock periods after the debugger has been detected to ensure the module is in the
TLR state prior to any operation. This module also has the ability to maintain the Cortex-M4
under reset (refer to the Section 8.7.8 ”SMAP Core Reset Request Source” on page 70).
8.7.7
Debugger Hot Plugging
The TCK pin is dedicated to the EDP. After reset has been released, the EDP detects that a
debugger has been attached when a TCK falling edge arises.
Figure 8-4. Debugger Hot Plugging Detection Timings Diagram
TCK
RESET_N
Hot Plugging
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The Debug Port pins assignation is then forced to the EDP function even if they were already
assigned to another module. This allows to connect a debugger at any time without reseting the
device. The connection is non-intrusive meaning that the chip will continue its execution without
being disturbed. The CPU can of course be halted later on by issuing Cortex-M4 OCD features.
8.7.8
SMAP Core Reset Request Source
The EDP has the ability to send a request to the SMAP for a Cortex-M4 Core reset. The proce-
dure to do so is to hold TCK low until RESET_N is released. This mechanism aims at halting the
CPU to prevent it from changing the system configuration while the SMAP is operating.
Figure 8-5. SMAP Core Reset Request Timings Diagram
T C K
R E S E T _ N
EDP
C o re re se t re q u e st
The SMAP can de-assert the core reset request for this operation, refer to Section 2.8.8 ”Cortex-
M4 Core Reset Source” on page 57.
8.7.9
SWJ-DP
The Cortex-M4 embeds a SWJ-DP Debug port which is the standard CoreSight™ debug port. It
combines Serial Wire Debug Port (SW-DP), from 2 to 3 pins and JTAG debug Port(JTAG-DP), 5
pins.
By default, the JTAG Debug Port is active. If the host debugger wants to switch to the Serial
Wire Debug Port, it must provide a dedicated JTAG sequence on TMS/SWDIO and
TCK/SWCLK which disables JTAG-DP and enables SW-DP.
When the EDP has been switched to Serial Wire mode, TDO/TRACESWO can be used for trace
(for more information refer to the section below). The asynchronous TRACE output (TRAC-
ESWO) is multiplexed with TDO. So the asynchronous trace can only be used with SW-DP, not
JTAG-DP.
The SWJ-DP provides access to the AHB-AP and SMAP access ports which have the following
APSEL value:
Figure 8-6. Access Ports APSEL
Acces Port (AP)
AHB-AP
APSEL
0
1
SMAP
Refer to the ARM Debug Interface v5.1 Architecture Specification for more details on SWJ-DP.
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8.7.10
SW-DP and JTAG-DP Selection Mechanism
After reset, the SWJ-DP is in JTAG mode but it can be switched to the Serial Wire mode. Debug
port selection mechanism is done by sending specific SWDIOTMS sequence. The JTAG-DP is
selected by default after reset.
• Switch from JTAG-DP to SW-DP. The sequence is:
– Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1
– Send the 16-bit sequence on SWDIOTMS = 0111100111100111 (0x79E7 MSB first)
– Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1
• Switch from SWD to JTAG. The sequence is:
– Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1
– Send the 16-bit sequence on SWDIOTMS = 0011110011100111 (0x3CE7 MSB first)
Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1
Note that the BSCAN-TAP is not available when the debug port is switched to Serial Mode.
Boundary scan instructions are not available.
8.7.11
JTAG-DP and BSCAN-TAP Selection Mechanism
After the DP has been enabled, the BSCAN-TAP and the JTAG-DP run simultaneously has long
as the SWJ-DP remains in JTAG mode. Each TAP captures simultaneously the JTAG instruc-
tions that are shifted. If an instruction is recognized by the BSCAN-TAP, then the BSCAN-TAP
TDO is selected instead of the SWJ-DP TDO. TDO selection changes dynamically depending on
the current instruction held in the BSCAN-TAP instruction register.
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8.7.12
JTAG Instructions Summary
The implemented JTAG instructions are shown in the table below.
Table 8-2.
Implemented JTAG instructions list
availability
when
protected
IR instruction
Instruction
Description
Component
value
Select boundary-scan chain as data register for
testing circuitry external to
b0000
EXTEST
yes
the device.
Take a snapshot of external pin values without
affecting system operation.
b0001
b0100
b0101
SAMPLE_PRELOAD
INTEST
yes
yes
yes
Select boundary-scan chain for internal testing of the
device.
Bypass device through Bypass register, while driving
outputs from boundary-scan register.
CLAMP
BSCAN-TAP
b1000
b1010
b1011
b1100
b1101
b1110
b1111
ABORT
DPACC
APACC
-
ARM JTAG-DP Instruction
ARM JTAG-DP Instruction
ARM JTAG-DP Instruction
Reserved
yes
yes
yes
yes
yes
yes
yes
SWJ-DP
(in JTAG mode)
-
Reserved
IDCODE
BYPASS
ARM JTAG-DP Instruction
Bypass this device through the bypass register.
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8.7.13
Security Restrictions
The SAM4L provide a security restrictions mechanism to lock access to the device. The device
in the protected state when the Flash Security Bit is set. Refer to section Flash Controller for
more details.
When the device is in the protected state the AHB-AP is locked. Full access to the AHB-AP is re-
enabled when the protected state is released by issuing a Chip Erase command. Note that the
protected state will read as programmed only after the system has been reseted.
8.7.13.1
Notation
Table 8-4 on page 73 shows bit patterns to be shifted in a format like "p01". Each character cor-
responds to one bit, and eight bits are grouped together for readability. The least significant bit is
always shifted first, and the most significant bit shifted last. The symbols used are shown in
Table 8-3.
Table 8-3.
Symbol Description
Symbol
Description
0
1
p
x
e
b
s
Constant low value - always reads as zero.
Constant high value - always reads as one.
The chip protected state.
A don’t care bit. Any value can be shifted in, and output data should be ignored.
An error bit. Read as one if an error occurred, or zero if not.
A busy bit. Read as one if the SMAP was busy, or zero if it was not.
Startup done bit. Read as one if the system has started-up correctly.
In many cases, it is not required to shift all bits through the data register. Bit patterns are shown
using the full width of the shift register, but the suggested or required bits are emphasized using
bold text. I.e. given the pattern "01010101 xxxxxxxx xxxxxxxx xxxxxxxx", the shift register is 32
bits, but the test or debug unit may choose to shift only 8 bits "01010101".
The following describes how to interpret the fields in the instruction description tables:
Table 8-4.
Instruction
Instruction Description
Description
Shows the bit pattern to shift into IR in the Shift-IR state in order to select this
instruction. The pattern is show both in binary and in hexadecimal form for
convenience.
IR input value
Example: 1000 (0x8)
Shows the bit pattern shifted out of IR in the Shift-IR state when this instruction is
active.
IR output value
Example: p00s
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Table 8-4.
Instruction
Instruction Description (Continued)
Description
Shows the number of bits in the data register chain when this instruction is active.
Example: 32 bits
DR Size
Shows which bit pattern to shift into the data register in the Shift-DR state when this
instruction is active.
DR input value
DR output value
Shows the bit pattern shifted out of the data register in the Shift-DR state when this
instruction is active.
8.7.14
JTAG Instructions
Refer to the ARM Debug Interface v5.1 Architecture Specification for more details on ABORT,
DPACC, APACC and IDCODE instructions.
8.7.14.1
EXTEST
This instruction selects the boundary-scan chain as Data Register for testing circuitry external to
the chip package. The contents of the latched outputs of the boundary-scan chain is driven out
as soon as the JTAG IR-register is loaded with the EXTEST instruction.
Starting in Run-Test/Idle, the EXTEST instruction is accessed the following way:
1. Select the IR Scan path.
2. In Capture-IR: The IR output value is latched into the shift register.
3. In Shift-IR: The instruction register is shifted by the TCK input.
4. In Update-IR: The data from the boundary-scan chain is applied to the output pins.
5. Return to Run-Test/Idle.
6. Select the DR Scan path.
7. In Capture-DR: The data on the external pins is sampled into the boundary-scan chain.
8. In Shift-DR: The boundary-scan chain is shifted by the TCK input.
9. In Update-DR: The data from the scan chain is applied to the output pins.
10. Return to Run-Test/Idle.
Table 8-5.
EXTEST Details
Instructions
IR input value
IR output value
DR Size
Details
0000 (0x0)
p00s
Depending on boundary-scan chain, see BSDL-file.
Depending on boundary-scan chain, see BSDL-file.
Depending on boundary-scan chain, see BSDL-file.
DR input value
DR output value
SAMPLE_PRELOAD
8.7.14.2
This instruction takes a snap-shot of the input/output pins without affecting the system operation,
and pre-loading the scan chain without updating the DR-latch. The boundary-scan chain is
selected as Data Register.
Starting in Run-Test/Idle, the Device Identification register is accessed in the following way:
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1. Select the IR Scan path.
2. In Capture-IR: The IR output value is latched into the shift register.
3. In Shift-IR: The instruction register is shifted by the TCK input.
4. Return to Run-Test/Idle.
5. Select the DR Scan path.
6. In Capture-DR: The Data on the external pins are sampled into the boundary-scan
chain.
7. In Shift-DR: The boundary-scan chain is shifted by the TCK input.
8. Return to Run-Test/Idle.
Table 8-6.
SAMPLE_PRELOAD Details
Instructions
IR input value
IR output value
DR Size
Details
0001 (0x1)
p00s
Depending on boundary-scan chain, see BSDL-file.
Depending on boundary-scan chain, see BSDL-file.
Depending on boundary-scan chain, see BSDL-file.
DR input value
DR output value
8.7.14.3
INTEST
This instruction selects the boundary-scan chain as Data Register for testing internal logic in the
device. The logic inputs are determined by the boundary-scan chain, and the logic outputs are
captured by the boundary-scan chain. The device output pins are driven from the boundary-scan
chain.
Starting in Run-Test/Idle, the INTEST instruction is accessed the following way:
1. Select the IR Scan path.
2. In Capture-IR: The IR output value is latched into the shift register.
3. In Shift-IR: The instruction register is shifted by the TCK input.
4. In Update-IR: The data from the boundary-scan chain is applied to the internal logic
inputs.
5. Return to Run-Test/Idle.
6. Select the DR Scan path.
7. In Capture-DR: The data on the internal logic is sampled into the boundary-scan chain.
8. In Shift-DR: The boundary-scan chain is shifted by the TCK input.
9. In Update-DR: The data from the boundary-scan chain is applied to internal logic inputs.
10. Return to Run-Test/Idle.
Table 8-7.
INTEST Details
Instructions
IR input value
IR output value
DR Size
Details
0100 (0x4)
p001
Depending on boundary-scan chain, see BSDL-file.
Depending on boundary-scan chain, see BSDL-file.
Depending on boundary-scan chain, see BSDL-file.
DR input value
DR output value
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8.7.14.4
CLAMP
This instruction selects the Bypass register as Data Register. The device output pins are driven
from the boundary-scan chain.
Starting in Run-Test/Idle, the CLAMP instruction is accessed the following way:
1. Select the IR Scan path.
2. In Capture-IR: The IR output value is latched into the shift register.
3. In Shift-IR: The instruction register is shifted by the TCK input.
4. In Update-IR: The data from the boundary-scan chain is applied to the output pins.
5. Return to Run-Test/Idle.
6. Select the DR Scan path.
7. In Capture-DR: A logic ‘0’ is loaded into the Bypass Register.
8. In Shift-DR: Data is scanned from TDI to TDO through the Bypass register.
9. Return to Run-Test/Idle.
Table 8-8.
CLAMP Details
Instructions
IR input value
IR output value
DR Size
Details
0101 (0x5)
p00s
1
x
x
DR input value
DR output value
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8.8
AHB-AP Access Port
The AHB-AP is a Memory Access Port (MEM-AP) as defined in the ARM Debug Interface v5
Architecture Specification. The AHB-AP provides access to all memory and registers in the sys-
tem, including processor registers through the System Control Space (SCS). System access is
independent of the processor status. Either SW-DP or SWJ-DP is used to access the AHB-AP.
The AHB-AP is a master into the Bus Matrix. Transactions are made using the AHB-AP pro-
grammers model (please refer to the ARM Cortex-M4 Technical Reference Manual), which
generates AHB-Lite transactions into the Bus Matrix. The AHB-AP does not perform back-to-
back transactions on the bus, so all transactions are non-sequential. The AHB-AP can perform
unaligned and bit-band transactions. The Bus Matrix handles these. The AHB-AP transactions
are not subject to MPU lookups. AHB-AP transactions bypass the FPB, and so the FPB cannot
remap AHB-AP transactions. AHB-AP transactions are little-endian.
Note that while an external reset is applied, AHB-AP accesses are not possible. In addition,
access is denied when the protected state is set. In order to discard the protected state, a chip
erase operation is necessary.
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8.9
System Manager Access Port (SMAP)
Rev.: 1.0.0.0
8.9.1
Features
• Chip Erase command and status
• Cortex-M4 core reset source
• 32-bit Cyclic Redundancy check of any memory accessible through the bus matrix
• Unlimited Flash User page read access
• Chip identification register
8.9.2
8.9.3
Overview
The SMAP provides memory-related services and also Cortex-M4 core reset control to a debug-
ger through the Debug Port. This makes possible to halt the CPU and program the device after
reset.
Block Diagram
Figure 8-7. SMAP Block Diagram
SMAP
System
Bus Matrix
AHB
Ahb_Master
AHB
Flash
Controller
chip_erase
DAP
Interface
DAP Bus
Core
PM
SMAP Core reset request
Reset
Controller
Cortex-M4 core reset
System reset
8.9.4
Initializing the Module
The SMAP can be accessed only if the CPU clock is running and the SWJ-DP has been acti-
vated by issuing a CDBGPWRUP request. For more details, refer to the ARM Debug Interface
v5.1 Architecture Specification.
Then it must be enabled by writing a one to the EN bit of the CR register (CR.EN) before writing
or reading other registers. If the SMAP is not enabled it will discard any read or write operation.
8.9.5
Stopping the Module
To stop the module, the user must write a one to the DIS bit of the CR register (CR.DIS). All the
user interface and internal registers will be cleared and the internal clock will be stopped.
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8.9.6
Security Considerations
In protected state this module may access sensible information located in the device memories.
To avoid any risk of sensible data extraction from the module registers, all operations are non
interruptible except by a disable command triggered by writing a one to CR.DIS. Issuing this
command clears all the interface and internal registers.
Some registers have some special protection:
• It is not possible to read or write the LENGTH register when the part is protected.
• In addition, when the part is protected and an operation is ongoing, it is not possible to read
the ADDR and DATA registers. Once an operation has started, the user has to wait until it
has terminated by polling the DONE field in the Status Register (SR.DONE).
8.9.7
Chip Erase
The Chip erase operation consists in:
1. clearing all the volatile memories in the system
2. clearing the whole flash array
3. clearing the protected state
No proprietary or sensitive information is left in volatile memories once the protected state is
disabled.
This feature is operated by writing a one to the CE bit of the Control Register (CR.CE). When the
operation completes, SR.DONE is asserted.
8.9.8
Cortex-M4 Core Reset Source
The SMAP processes the EDP Core hold reset requests (Refer to Section 1.1.8 ”SMAP Core
Reset Request Source” on page 6). When requested, it instructs the Power Manager to hold the
Cortex-M4 core under reset.
The SMAP can de-assert the core reset request if a one is written to the Hold Core Reset bit in
the Status Clear Register (SCR.HCR). This has the effect of releasing the CPU from its reset
state. To assert again this signal, a new reset sequence with TCK tied low must be issued.
Note that clearing HCR with this module is only possible when it is enabled, for more information
refer to Section 8.9.4 ”Initializing the Module” on page 78. Also note that asserting RESET_N
automatically clears HCR.
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8.9.9
Unlimited Flash User Page Read Access
The SMAP can access the User page even if the protected state is set. Prior to operate such an
access, the user should check that the module is not busy by checking that SR.STATE is equal
to zerp. Once the offset of the word to access inside the page is written in ADDR.ADDR, the
read operation can be initiated by writing a one in CR.FSPR. The SR.STATE field will indicate
the FSPR state. Addresses written to ADDR.ADDR must be world aligned. Failing to do so will
result in unpredictable behavior. The result can be read in the DATA register as soon as
SR.DONE rises. The ADDR field is used as an offset in the page, bits outside a page boundary
will be silently discarded. The ADDR register is automatically incremented at the end of the read
operation making possible to dump consecutive words without writing the next offset into
ADDR.ADDR.
8.9.10
32-bit Cyclic Redundancy Check (CRC)
The SMAP unit provides support for calculating a Cyclic Redundancy Check (CRC) value for a
memory area. The algorithm used is the industry standard CRC32 algorithm using the generator
polynomial 0xEDB88320.
8.9.10.1
Starting CRC Calculation
To calculate CRC for a memory range, the start address must be written into the ADDR register,
and the size of the memory range into the LENGTH register. Both the start address and the
length must be word aligned.
The initial value used for the CRC calculation must be written to the DATA register. This value
will usually be 0xFFFFFFFF, but can be e.g. the result of a previous CRC calculation if generat-
ing a common CRC of separate memory blocks.
Once completed, the calculated CRC value can be read out of the DATA register. The read
value must be inverted to match standard CRC32 implementations, or kept non-inverted if used
as starting point for subsequent CRC calculations.
If the device is in protected state, it is only possible to calculate the CRC of the whole flash array.
In most cases this area will be the entire onboard nonvolatile memory. The ADDR, LENGTH,
and DATA registers will be forced to predefined values once the CRC operation is started, and
user-written values are ignored. This allows the user to verify the contents of a protected device.
The actual test is started by writing a one in CR.CRC. A running CRC operation can be can-
celled by disabling the module (write a one in CR.DIS). This has the effect of resetting the
module. The module has to be restarted by issuing an enable command (write a one in CR.EN).
8.9.10.2
Interpreting the Results
The user should monitor the SR register (Refer to Section 8.9.11.2 ”Status Register” on page
83). When the operation is completed SR.DONE is set. Then the SR.BERR and SR.FAIL must
be read to ensure that no bus error nor functional error occured.
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8.9.11
SMAP User Interface
Table 8-9.
SMAP Register Memory Map
Access
Access
Offset
Register
Control Register
Register Name
CR
(unprotected)
(protected)
Write-Only (partial)(2)
Read-Only
Reset
0x0000
0x0004
0x0008
0x000C
0x0010
0x0014
0x0028
0x00F0
0x00F4
0x00FC
Write-Only
Read-Only
Write-Only
Read/Write
Read/Write
Read/Write
Read-Only
Read-Only
Read-Only
Read-Only
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
Status Register
SR
Status Clear Register
Address Register
Length Register
SCR
Write-Only (partial)(3)
Read/Write (partial)(4)
denied
ADDR
LENGTH
DATA
Data Register
Read/Write (partial)(4)
Read-Only
(1)
VERSION Register
Chip ID Register
VERSION
CIDR
-
(1)
Read-Only
-
(1)
Chip ID Extension Register
AP Identification register
EXID
Read-Only
-
IDR
Read-Only
0x003E0000
Note:
1. The reset value for this register is device specific. Refer to the Module Configuration section at the end of this chapter.
2. CR.MBIST is ignored
3. SCR.HCR is ignored
4. Access is not allowed when an operation is ongoing
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8.9.11.1
Control Register
Name:
CR
Access Type:
Offset:
Write-Only
0x00
Reset Value:
0x00000000
31
-
30
29
-
28
-
27
-
26
-
25
-
24
-
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
3
2
1
0
CE
FSPR
CRC
DIS
EN
Writing a zero to a bit in this register has no effect.
• CE: Chip Erase
Writing a one to this bit triggers the FLASH Erase All (EA) operation which clears all volatile memories, the whole flash array,
the general purpose fuses and the protected state. The Status register DONE field indicates the completion of the operation.
Reading this bit always returns 0
• FSPR: Flash User Page Read
Writing a one to this bit triggers a read operation in the User page. The word pointed by the ADDR register in the page is read
and written to the DATA register. ADDR is post incremented allowing a burst of reads without modifying ADDR. SR.DONE must
be read high prior to reading the DATA register.
Reading this bit always returns 0
• CRC: Cyclic Redundancy Code
Writing a one triggers a CRC calculation over a memory area defined by the ADDR and LENGTH registers. Reading this bit
always returns 0
Note: This feature is restricted while in protected state
• DIS: Disable
Writing a one to this bit disables the module. Disabling the module resets the whole module immediately.
• EN: Enable
Writing a one to this bit enables the module.
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8.9.11.2
Status Register
Name:
SR
Access Type:
Offset:
Read-Only
0x04
Reset Value:
0x00000000
31
-
30
29
-
28
-
27
-
26
25
24
-
STATE
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
9
8
DBGP
PROT
EN
7
-
6
-
5
-
4
3
2
1
0
LCK
FAIL
BERR
HCR
DONE
• STATE: State
Value
State
Description
0
IDLE
CE
Idle state
1
Chip erase operation is ongoing
2
CRC32
FSPR
-
CRC32 operation is ongoing
Flash User Page Read
reserved
3
4-7
• DBGP: Debugger present
1: A debugger is present (TCK falling edge detected)
0: No debugger is present
• PROT: Protected
1: The protected state is set. The only way to overcome this is to issue a Chip Erase command.
0: The protected state is not set
• EN: Enabled
1: The block is in ready for operation
0: the block is disabled. Write operations are not possible until the block is enabled by writing a one in CR.EN.
• LCK: Lock
1: An operation could not be performed because chip protected state is on.
0: No security issues have been detected sincle last clear of this bit
• FAIL: Failure
1: The requested operation failed
0: No failure has been detected sincle last clear of this bit
• BERR: Bus Error
1: A bus error occured due to the unability to access part of the requested memory area.
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0: No bus error has been detected sincle last clear of this bit
• HCR: Hold Core reset
1: The Cortex-M4 core is held under reset
0: The Cortex-M4 core is not held under reset
• DONE: Operation done
1: At least one operation has terminated since last clear of this field
0: No operation has terminated since last clear of this field
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8.9.11.3
Status Clear Register
Name:
SCR
Access Type:
Offset:
Write-Only
0x08
Reset Value:
0x00000000
31
-
30
29
-
28
-
27
-
26
-
25
-
24
-
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
3
2
1
0
LCK
FAIL
BERR
HCR
DONE
Writing a zero to a bit in this register has no effect.
Writing a one to a bit clears the corresponding SR bit
Note: Writing a one to bit HCR while the chip is in protected state has no effect
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8.9.11.4
Address Register
Name:
ADDR
Access Type:
Offset:
Read/Write
0x0C
Reset Value:
0x00000000
31
23
15
7
30
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
ADDR
ADDR
ADDR
22
14
6
1
-
0
-
ADDR
• ADDR: Address Value
Addess values are always world aligned
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8.9.11.5
Length Register
Name:
LENGTH
Access Type:
Offset:
Read/Write
0x10
Reset Value:
0x00000000
31
23
15
7
30
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
LENGTH
LENGTH
LENGTH
22
14
6
1
-
0
-
LENGTH
• LENGTH: Length Value, Bits 1-0 are always zero
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8.9.11.6
Data Register
Name:
DATA
Access Type:
Offset:
Read/Write
0x14
Reset Value:
0x00000000
31
23
15
7
30
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
DATA
DATA
DATA
DATA
22
14
6
1
0
• DATA: Generic data register
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8.9.11.7
Module Version
Name:
VERSION
Read-Only
0x28
Access Type:
Offset:
Reset Value:
-
31
-
30
29
-
28
-
27
-
26
-
25
-
24
-
-
23
-
22
-
21
-
20
-
19
11
3
18
10
2
17
9
16
8
VARIANT
VERSION
15
-
14
-
13
-
12
-
7
6
5
4
1
0
VERSION
• VARIANT: Variant number
Reserved. No functionality associated.
• VERSION: Version number
Version number of the module. No functionality associated.
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8.9.11.8
Chip Identification Register
Name:
CIDR
Access Type:
Offset:
Read-Only
0xF0
-
Reset Value:
31
30
29
28
20
12
4
27
19
11
3
26
25
17
9
24
16
8
EXT
NVPTYP
ARCH
23
15
7
22
21
13
5
18
ARCH
SRAMSIZ
14
10
NVPSIZ2
NVPSIZ
6
2
1
0
EPROC
VERSION
Note:
Refer to section CHIPID for more information on this register.
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8.9.11.9
Chip Identification Extension Register
Name:
EXID
Access Type:
Offset:
Read-Only
0xF4
-
Reset Value:
31
23
15
7
30
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
EXID
EXID
EXID
EXID
22
14
6
1
0
Note:
Refer to section CHIPID for more information on this register.
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8.9.11.10
Identification Register
Name:
IDR
Access Type:
Offset:
Read-Only
0xFC
-
Reset Value:
31
23
15
30
29
21
13
5
28
27
19
11
3
26
18
10
2
25
17
9
24
REVISION
CC
22
14
6
20
IC
16
CLSS
12
4
8
0
Reserved
7
1
APID
APIDV
• REVISION: Revision
• CC: JEP-106 Continuation Code
Atmel continuation code is 0x0
• IC: JEP-106 Identity Code
Atmel identification code is 0x1F
• CLSS: Class
0: This AP is not a Memory Access Port
1: This AP is a Memory Access Port
• APID: AP Identification
• APIDV: AP Identification Variant
For more information about this register, refer to the ARM Debug Interface v5.1 Architecture
Specification document.
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8.10 Available Features in Protected State
Table 8-10. Features availablility when in protected state
Feature
Provider
EDP
Availability when protected
Hot plugging
yes
System bus R/W Access
Flash User Page read access
Core Hold Reset clear from the SMAP interface
AHB-AP
SMAP
SMAP
no
yes
no
CRC32 of any memory accessible through the bus matrix SMAP
restricted (limited to the entire flash array)
Chip Erase
IDCODE
SMAP
SMAP
yes
yes
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8.11 Functional Description
8.11.1
Debug Environment
Figure 8-8 shows a complete debug environment example. The SWJ-DP interface is used for
standard debugging functions, such as downloading code and single-stepping through the pro-
gram and viewing core and peripheral registers.
Figure 8-8. Application Debug Environment Example
Host Debugger
PC
SWJ-DP
Emulator/Probe
SWJ-DP
Connector
SAM4
SAM4-based Application Board
8.11.2
Test Environment
Figure 8-9 shows a test environment example (JTAG Boundary scan). Test vectors are sent and
interpreted by the tester. In this example, the “board in test” is designed using a number of
JTAG-compliant devices. These devices can be connected to form a single scan chain.
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Figure 8-9. Application Test Environment Example
Test Adaptor
Tester
JTAG
Probe
JTAG
Connector
Chip n
Chip 2
Chip 1
SAM4
SAM4-based Application Board In Test
8.11.3
How to initialize test and debug features
To enable the JTAG pins a falling edge event must be detected on the TCK pin at any time after
the RESET_N pin is released.
Certain operations requires that the system is prevented from running code after reset is
released. This is done by holding low the TCK pin after the RESET_N is released. This makes
the SMAP assert the core_hold_reset signal that hold the Cortex-M4 core under reset.
To make the CPU run again, clear the CHR bit in the Status Register (SR.CHR) to de-assert the
core_hold_reset signal. Independent of the initial state of the TAP Controller, the Test-Logic-
Reset state can always be entered by holding TMS high for 5 TCK clock periods. This sequence
should always be applied at the start of a JTAG session and after enabling the JTAG pins to
bring the TAP Controller into a defined state before applying JTAG commands. Applying a 0 on
TMS for 1 TCK period brings the TAP Controller to the Run-Test/Idle state, which is the starting
point for JTAG operations.
8.11.4
8.11.5
8.11.5.1
How to disable test and debug features
To disable the JTAG pins the TCK pin must be held high while RESET_N pin is released.
Typical JTAG sequence
Assuming Run-Test/Idle is the present state, a typical scenario for using the JTAG interface is:
Scanning in JTAG instruction
At the TMS input, apply the sequence 1, 1, 0, 0 at the rising edges of TCK to enter the Shift
Instruction Register - Shift-IR state. While in this state, shift the 4 bits of the JTAG instructions
into the JTAG instruction register from the TDI input at the rising edge of TCK. The TMS input
must be held low during input of the 4 LSBs in order to remain in the Shift-IR state. The JTAG
Instruction selects a particular Data Register as path between TDI and TDO and controls the cir-
cuitry surrounding the selected Data Register.
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Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction is latched
onto the parallel output from the shift register path in the Update-IR state. The Exit-IR, Pause-IR,
and Exit2-IR states are only used for navigating the state machine.
Figure 8-10. Scanning in JTAG instruction
TCK
TAP State
TMS
TLR
RTI SelDR SelIR CapIR ShIR
Ex1IR UpdIR RTI
TDI
Instruction
TDO
ImplDefined
8.11.5.2
Scanning in/out data
At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the Shift Data
Register - Shift-DR state. While in this state, upload the selected Data Register (selected by the
present JTAG instruction in the JTAG Instruction Register) from the TDI input at the rising edge
of TCK. In order to remain in the Shift-DR state, the TMS input must be held low. While the Data
Register is shifted in from the TDI pin, the parallel inputs to the Data Register captured in the
Capture-DR state is shifted out on the TDO pin.
Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. If the selected Data Register
has a latched parallel-output, the latching takes place in the Update-DR state. The Exit-DR,
Pause-DR, and Exit2-DR states are only used for navigating the state machine.
As shown in the state diagram, the Run-Test/Idle state need not be entered between selecting
JTAG instruction and using Data Registers.
8.11.6
Boundary-Scan
The Boundary-Scan chain has the capability of driving and observing the logic levels on the dig-
ital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having
off-chip connections. At system level, all ICs having JTAG capabilities are connected serially by
the TDI/TDO signals to form a long shift register. An external controller sets up the devices to
drive values at their output pins, and observe the input values received from other devices. The
controller compares the received data with the expected result. In this way, Boundary-Scan pro-
vides a mechanism for testing interconnections and integrity of components on Printed Circuits
Boards by using the 4 TAP signals only.
The four IEEE 1149.1 defined mandatory JTAG instructions IDCODE, BYPASS, SAMPLE/PRE-
LOAD, and EXTEST can be used for testing the Printed Circuit Board. Initial scanning of the
data register path will show the ID-code of the device, since IDCODE is the default JTAG
instruction. It may be desirable to have the device in reset during test mode. If not reset, inputs
to the device may be determined by the scan operations, and the internal software may be in an
undetermined state when exiting the test mode. Entering reset, the outputs of any Port Pin will
instantly enter the high impedance state, making the HIGHZ instruction redundant. If needed,
the BYPASS instruction can be issued to make the shortest possible scan chain through the
device. The device can be set in the reset state by pulling the external RESET_N pin low.
The EXTEST instruction is used for sampling external pins and loading output pins with data.
The data from the output latch will be driven out on the pins as soon as the EXTEST instruction
is loaded into the JTAG IR-register. Therefore, the SAMPLE/PRELOAD should also be used for
setting initial values to the scan ring, to avoid damaging the board when issuing the EXTEST
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instruction for the first time. SAMPLE/PRELOAD can also be used for taking a snapshot of the
external pins during normal operation of the part.
When using the JTAG interface for Boundary-Scan, the JTAG TCK clock is independent of the
internal chip clock, which is not required to run.
NOTE: For pins connected to 5V lines care should be taken to not drive the pins to a logic one
using boundary scan, as this will create a current flowing from the 3,3V driver to the 5V pullup on
the line. Optionally a series resistor can be added between the line and the pin to reduce the
current.
8.11.7
Flash Programming typical procedure
Flash programming is performed by operating Flash controller commands. The Flash controller
is connected to the system bus matrix and is then controllable from the AHP-AP. The AHB-AP
cannot write the FLASH page buffer while the core_hold_reset is asserted. The AHB-AP cannot
be accessed when the device is in protected state. It is important to ensure that the CPU is
halted prior to operating any flash programming operation to prevent it from corrupting the sys-
tem configuration. The recommended sequence is shown below:
1. At power up, RESET_N is driven low by a debugger. The on-chip regulator holds the
system in a POR state until the input supply is above the POR threshold. The system
continues to be held in this static state until the internally regulated supplies have
reached a safe operating.
2. PM starts, clocks are switched to the slow clock (Core Clock, System Clock, Flash
Clock, and any Bus Clocks that do not have clock gate control). Internal resets are
maintained due to the external reset.
– The Debug Port (DP) and Access Ports (AP) receives a clock and leave the reset
state,
3. The debugger maintains a low level on TCK and release RESET_N.
– The SMAP asserts the core_hold_reset signal
4. The Cortex-M4 core remains in reset state, meanwhile the rest of the system is
released.
5. The debugger then configures the NVIC to catch the Cortex-M4 core reset vector fetch.
For more information on how to program the NVIC, refer to the ARMv7-M Architecture
Reference Manual.
6. The debugger writes a one in the SMAP SCR.HCR to release the Cortex-M4 core reset
to make the system bus matrix accessible from the AHB-AP.
7. The Cortex-M4 core initializes the SP, then read the exception vector and stalls
8. Programming is available through the AHB-AP
9. After operation is completed, the chip can be restarted either by asserting RESET_N or
switching power off/on or clearing SCR.HCR. Make sure that the TCK pin is high when
releasing RESET_N not to halt the core.
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8.11.8
Chip erase typical procedure
The chip erase operation is triggered by writing a one in the CE bit in the Control Register
(CR.CE). This clears first all volatile memories in the system and second the whole flash array.
Note that the User page is not erased in this process. To ensure that the chip erase operation is
completed, check the DONE bit in the Status Register (SR.DONE). Also note that the chip erase
operation depends on clocks and power management features that can be altered by the CPU.
It is important to ensure that it is stopped. The recommended sequence is shown below:
1. At power up, RESET_N is driven low by a debugger. The on-chip regulator holds the
system in a POR state until the input supply is above the POR threshold. The system
continues to be held in this static state until the internally regulated supplies have
reached a safe operating.
2. PM starts, clocks are switched to the slow clock (Core Clock, System Clock, Flash
Clock, and any Bus Clocks that do not have clock gate control). Internal resets are
maintained due to the external reset.
– The debug port and access ports receives a clock and leave the reset state
3. The debugger maintains a low level on TCK and release RESET_N.
– The SMAP asserts the core_hold_reset signal
4. The Cortex-M4 core remains in reset state, meanwhile the rest of the system is
released.
5. The Chip erase operation can be performed by issuing the SMAP Chip Erase com-
mand. In this case:
– volatile memories are cleared first
– followed by the clearing of the flash array
– followed by the clearing of the protected state
6. After operation is completed, the chip must be restarted by either controling RESET_N
or switching power off/on. Make sure that the TCK pin is high when releasing
RESET_N not to halt the core.
8.11.9
Setting the protected state
This is done by issuing a specific flash controller command, for more information, refer to the
Flash Controller chapter and to section 8.11.7Flash Programming typical procedure97. The pro-
tected state is defined by a highly secure Flash builtin mechanism. Note that for this
programmation to propagate, it is required to reset the chip.
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9. Electrical Characteristics
9.1
Absolute Maximum Ratings*
Table 9-1.
Absolute Maximum Ratings
*NOTICE:
Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or other conditions
beyond those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
Operating temperature .................................... -40°C to +85°C
Storage temperature...................................... -60°C to +150°C
Voltage on input pins
with respect to ground ..........................-0.3V to VVDD (1)+0.3V
Total DC output current on all I/O pins
VDDIO ......................................................................... 120 mA
Total DC output current on all I/O pins
VDDIN ........................................................................ 100 mA
Total DC output current on all I/O pins
VDDANA........................................................................ 50 mA
Maximum operating voltage VDDIO, VDDIN.................... 3.6V
1.
VVDD corresponds to either VVDDIN or VVDDIO, depending on the supply for the pin. Refer to Section 3-5 on page 13 for details
9.2
Operating Conditions
All the electrical characteristics are applicable to the following conditions unless otherwise spec-
ified :
– operating voltage range 1,68V to 3,6V for VDDIN, VDDIO & VDDANA
– Power Scaling 0 and 2 modes
– operating temperature range: TA = -40°C to 85°C and for a junction temperature up
to TJ = 100°C.
Typical values are base on TA = 25°c and VDDIN,VDDIO,VDDANA = 3,3V unless otherwise
specified
9.3
Supply Characteristics
Table 9-2.
Supply Characteristics
Voltage
Max
Symbol
Conditions
Min
Unit
PS1 (FCPU<=12MHz)
Linear mode
1.68
VVDDIO,
VVDDIN,
VVDDANA
PS0 & PS2 (FCPU>12MHz)
Linear mode
3.6
V
1.8
Switching mode
2.0 (1)
1.
Below 2.3V, linear mode is more power efficient than switching mode.
Refer to Section 6. ”Power and Startup Considerations” on page 46 for details about Power
Supply
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Table 9-3.
Supply Rise Rates and Order (1)
VDDIO, VDDIN and VDDANA must be connected together and as a consequence, rise
synchronously
Rise Rate
Symbol
Parameter
Min
Max
Unit
Comment
VVDDIO
DC supply peripheral I/Os
0.0001
2.5
V/µs
DC supply peripheral I/Os
and internal regulator
VVDDIN
0.0001
0.0001
2.5
2.5
V/µs
V/µs
VVDDANA
Analog supply voltage
1.
These values are based on characterization. These values are not covered by test limits in
production.
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9.4
Maximum Clock Frequencies
Table 9-4.
Maximum Clock Frequencies in Power Scaling Mode 0/2 and RUN Mode
Symbol Parameter
Description
Max
48
Units
fCPU
fPBA
CPU clock frequency
PBA clock frequency
PBB clock frequency
PBC clock frequency
PBD clock frequency
48
fPBB
48
fPBC
fPBD
fGCLK0
48
48
GCLK0 clock frequency DFLLIF main reference, GCLK0 pin
50
DFLLIF dithering and SSG reference,
fGCLK1
GCLK1 clock frequency
GCLK1 pin
50
fGCLK2
fGCLK3
fGCLK4
fGCLK5
fGCLK6
fGCLK7
fGCLK8
fGCLK9
GCLK2 clock frequency AST, GCLK2 pin
GCLK3 clock frequency CATB, GCLK3 pin
GCLK4 clock frequency FLO and AESA
GCLK5 clock frequency GLOC, TC0 and RC32KIFB_REF
GCLK6 clock frequency ABDACB and IISC
GCLK7 clock frequency USBC
20
50
50
80
50
50
50
50
MHz
GCLK8 clock frequency TC1 and PEVC[0]
GCLK9 clock frequency PLL0 and PEVC[1]
GCLK10 clock
ADCIFE
fGCLK10
fGCLK11
50
frequency
GCLK11 clock
frequency
Master generic clock. Can be used as
source for other generic clocks
150
Oscillator 0 in crystal mode
Oscillator 0 in digital clock mode
Phase Locked Loop
30
50
fOSC0
OSC0 output frequency
fPLL
PLL output frequency
DFLL output frequency
240
220
fDFLL
Digital Frequency Locked Loop
RC80M output
frequency
fRC80M
Internal 80MHz RC Oscillator
80
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Table 9-5.
Symbol Parameter
fCPU CPU clock frequency
fPBA
Maximum Clock Frequencies in Power Scaling Mode 1 and RUN Mode
Description
Max
12
Units
PBA clock frequency
PBB clock frequency
PBC clock frequency
PBD clock frequency
12
fPBB
12
fPBC
fPBD
fGCLK0
12
12
GCLK0 clock frequency DFLLIF main reference, GCLK0 pin
16.6
DFLLIF dithering and SSGreference,
fGCLK1
GCLK1 clock frequency
GCLK1 pin
16.6
fGCLK2
fGCLK3
fGCLK4
fGCLK5
fGCLK6
fGCLK7
fGCLK8
fGCLK9
GCLK2 clock frequency AST, GCLK2 pin
GCLK3 clock frequency CATB, GCLK3 pin
GCLK4 clock frequency FLO and AESA
GCLK5 clock frequency GLOC, TC0 and RC32KIFB_REF
GCLK6 clock frequency ABDACB and IISC
GCLK7 clock frequency USBC
6.6
17.3
16.6
26.6
16.6
16.6
16.6
16.6
MHz
GCLK8 clock frequency TC1 and PEVC[0]
GCLK9 clock frequency PLL0 and PEVC[1]
GCLK10 clock
ADCIFE
fGCLK10
fGCLK11
16.6
51.2
frequency
GCLK11 clock
frequency
Master generic clock. Can be used as
source for other generic clocks
Oscillator 0 in crystal mode
Oscillator 0 in digital clock mode
Phase Locked Loop
16
16
fOSC0
OSC0 output frequency
fPLL
PLL output frequency
DFLL output frequency
N/A
N/A
fDFLL
Digital Frequency Locked Loop
RC80M output
frequency
fRC80M
Internal 80MHz RC Oscillator
N/A
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9.5
Power Consumption
9.5.1
Power Scaling 0 and 2
The values in Table 9-6 are measured values of power consumption under the following condi-
tions, except where noted:
• Operating conditions for power scaling mode 0 and 2
– VVDDIN = 3.3V
– Power Scaling mode 0 is used for CPU frequencies under 36MHz
– Power Scaling mode 2 is used for CPU frequencies above 36MHz
• Wake up time from low power modes is measured from the edge of the wakeup signal to the
first instruction fetched in flash.
• Oscillators
– OSC0 (crystal oscillator) stopped
– OSC32K (32kHz crystal oscillator) running with external 32kHz crystal
– DFLL using OSC32K as reference and running at 48MHz
• Clocks
– DFLL used as main clock source
– CPU, AHB clocks undivided
– APBC and APBD clocks divided by 4
– APBA and APBB bridges off
– The following peripheral clocks running
• PM, SCIF, AST, FLASHCALW, APBC and APBD bridges
– All other peripheral clocks stopped
• I/Os are inactive with internal pull-up
• CPU is running on flash with 1 wait state
• Low power cache enabled
• BOD18 and BOD33 disabled
Table 9-6.
Mode
ATSAM4L4/2 Current consumption and Wakeup time for power scaling mode 0 and 2
Typical
Conditions
TA
Wakeup Time
Typ
296
300
320
326
177
179
186
195
Max (1)
326
332
377
380
198
200
232
239
Unit
25°C
85°C
25°C
85°C
25°C
85°C
25°C
85°C
CPU running a Fibonacci algorithm
Linear mode
N/A
N/A
CPU running a CoreMark algorithm
Linear mode
RUN
µA/MHz
N/A
N/A
CPU running a Fibonacci algorithm
Switching mode
CPU running a CoreMark algorithm
Switching mode
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Table 9-6.
ATSAM4L4/2 Current consumption and Wakeup time for power scaling mode 0 and 2
Typical
Mode
Conditions
TA
Wakeup Time
Typ
3817
3934
2341
2437
1758
1847
51
Max (1)
4033
4174
2477
2585
1862
1971
60
Unit
25°C
85°C
25°C
85°C
25°C
85°C
9 * Main clock
cycles
SLEEP0
Switching mode
9 * Main clock
cycles + 500ns
SLEEP1
Switching mode
9 * Main clock
cycles + 500ns
SLEEP2
SLEEP3
Switching mode
Linear mode
OSC32K and AST running
Fast wake-up enable
5.9
4.7
8.7
7.6
µA
WAIT
1.5µs
1.5µs
OSC32K and AST stopped
Fast wake-up enable
25°C
OSC32K running
3.1
2.2
1.5
0.9
5.1
4.2
3.1
1.7
AST running at 1kHz
RETENTION
BACKUP
AST and OSC32K stopped
OSC32K running
AST running at 1kHz
AST and OSC32K stopped
1.
These values are based on characterization. These values are not covered by test limits in production.
Table 9-7.
Mode
ATSAM4L8 Current consumption and Wakeup time for power scaling mode 0 and 2
Typical
Conditions
TA
Wakeup Time
Typ
319
326
343
351
181
186
192
202
Max (1)
343
350
387
416
198
203
232
239
Unit
25°C
85°C
25°C
85°C
25°C
85°C
25°C
85°C
CPU running a Fibonacci algorithm
Linear mode
N/A
N/A
CPU running a CoreMark algorithm
Linear mode
RUN
µA/MHz
N/A
N/A
CPU running a Fibonacci algorithm
Switching mode
CPU running a CoreMark algorithm
Switching mode
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Table 9-7.
ATSAM4L8 Current consumption and Wakeup time for power scaling mode 0 and 2
Typical
Mode
Conditions
TA
Wakeup Time
Typ
3817
4050
2341
2525
1758
1925
51
Max (1)
4033
4507
2477
2832
1862
1971
60
Unit
25°C
85°C
25°C
85°C
25°C
85°C
9 * Main clock
cycles
SLEEP0
Switching mode
9 * Main clock
cycles + 500ns
SLEEP1
Switching mode
9 * Main clock
cycles + 500ns
SLEEP2
SLEEP3
Switching mode
Linear mode
OSC32K and AST running
Fast wake-up enable
6.7
5.5
µA
WAIT
1.5µs
1.5µs
OSC32K and AST stopped
Fast wake-up enable
25°C
OSC32K running
3.9
3.0
1.5
0.9
AST running at 1kHz
RETENTION
BACKUP
AST and OSC32K stopped
OSC32K running
3.1
1.7
AST running at 1kHz
AST and OSC32K stopped
1.
These values are based on characterization. These values are not covered by test limits in production.
9.5.2
Power Scaling 1
The values in Table 34-7 are measured values of power consumption under the following condi-
tions, except where noted:
• Operating conditions for power scaling mode 1
– VVDDIN = 3.3V
• Wake up time from low power modes is measured from the edge of the wakeup signal to the
first instruction fetched in flash.
• Oscillators
– OSC0 (crystal oscillator) and OSC32K (32kHz crystal oscillator) stopped
– RCFAST Running at 12MHz
• Clocks
– RCFAST used as main clock source
– CPU, AHB clocks undivided
– APBC and APBD clocks divided by 4
– APBA and APBB bridges off
– The following peripheral clocks running
• PM, SCIF, AST, FLASHCALW, APBC and APBD bridges
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– All other peripheral clocks stopped
• I/Os are inactive with internal pull-up
• CPU is running on flash with 1 wait state
• Low power cache enabled
• BOD18 and BOD33 disabled
Table 9-8.
Mode
ATSAM4L4/2 Current consumption and Wakeup time for power scaling mode 1
Typical
Conditions
TA
Wakeup Time
Typ
205
212
213
230
95
Max (1)
224
231
244
270
112
119
128
138
627
739
445
564
381
442
55
Unit
25°C
85°C
25°C
85°C
25°C
85°C
25°C
85°C
25°C
85°C
25°C
85°C
25°C
85°C
CPU running a Fibonacci algorithm
Linear mode
N/A
N/A
CPU running a CoreMark algorithm
Linear mode
RUN
µA/MHz
N/A
N/A
CPU running a Fibonacci algorithm
Switching mode
100
100
107
527
579
369
404
305
334
46
CPU running a CoreMark algorithm
Switching mode
9 * Main clock
cycles
SLEEP0
SLEEP1
Switching mode
Switching mode
9 * Main clock
cycles + 500ns
9 * Main clock
cycles + 500ns
SLEEP2
SLEEP3
Switching mode
Linear mode
OSC32K and AST running
Fast wake-up enable
4.7
3.5
7.5
6.3
µA
WAIT
1.5µs
1.5µs
OSC32K and AST stopped
Fast wake-up enable
OSC32K running
25°C
2.6
1.5
1.5
0.9
4.8
4
AST running at 1kHz
RETENTION
BACKUP
AST and OSC32K stopped
OSC32K running
3.1
1.7
AST running at 1kHz
AST and OSC32K stopped
1.
These values are based on characterization. These values are not covered by test limits in production.
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Table 9-9.
Mode
ATSAM4L8 Current consumption and Wakeup time for power scaling mode 1
Typical
Conditions
TA
Wakeup Time
Typ
222
233
233
230
100
100
104
107
527
579
369
404
305
334
46
Max (1)
240
276
276
270
112
119
128
138
627
739
445
564
381
442
55
Unit
25°C
85°C
25°C
85°C
25°C
85°C
25°C
85°C
25°C
85°C
25°C
85°C
25°C
85°C
CPU running a Fibonacci algorithm
Linear mode
N/A
N/A
CPU running a CoreMark algorithm
Linear mode
RUN
µA/MHz
N/A
N/A
CPU running a Fibonacci algorithm
Switching mode
CPU running a CoreMark algorithm
Switching mode
9 * Main clock
cycles
SLEEP0
SLEEP1
Switching mode
Switching mode
9 * Main clock
cycles + 500ns
9 * Main clock
cycles + 500ns
SLEEP2
SLEEP3
Switching mode
Linear mode
OSC32K and AST running
Fast wake-up enable
5.5
4.3
µA
WAIT
1.5µs
1.5µs
OSC32K and AST stopped
Fast wake-up enable
OSC32K running
25°C
3.4
2.3
1.5
0.9
AST running at 1kHz
RETENTION
BACKUP
AST and OSC32K stopped
OSC32K running
3.1
1.7
AST running at 1kHz
AST and OSC32K stopped
1.
These values are based on characterization. These values are not covered by test limits in production.
Table 9-10. Typical Power Consumption running CoreMark on CPU clock sources (1)
Frequency
Clock Source Conditions
Regulator
(MHz)
Typ
Unit
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Table 9-10. Typical Power Consumption running CoreMark on CPU clock sources (1)
RCSYS
Power scaling mode 1
(MCSEL = 0)
0.115
978
0.5
12
12
30
0.6
12
12
50
40
50
354
114
228
219
292
111
193
194
188
185
Power scaling mode 1
OSC0
(MCSEL = 1)
Power scaling mode 0
OSC0
Power scaling mode 1
(MCSEL = 1)
External Clock
(MODE=0)
Power scaling mode 0
Power scaling mode 2
Switching
Mode
PLL
Power scaling mode 2
µA/MHz
(MCSEL = 2)
Input Freq = 4MHz from OSC0
Power scaling mode 0
20
50
1
214
195
267
Input Freq = 32kHz from OSC32K
DFLL
(MCSEL = 3)
Power scaling mode 2
Input Freq = 32kHz from OSC32K
RC1M
Power scaling mode 1
(MCSEL = 4)
4
153
114
RCFAST
Power scaling mode 1
(MCSEL = 5)
RCFAST frequency is configurable from 4 to 12MHz
12
RC80M
Power scaling mode 2
40
211
(MCSEL = 6)
fCPU = RC80M / 2 = 40MHz
1.
These values are based on characterization. These values are not covered by test limits in production.
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Figure 9-1. Typical Power Consumption running Coremark (from above table)
Note:
For variable frequency oscillators, linear interpolation between high and low settings
Figure 9-2. Measurement Schematic, Switching Mode
VDDIN
VDDANA
VDDIO
VDDOUT
Amp 0
VDDCORE
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9.5.3
Peripheral Power Consumption in Power Scaling mode 0 and 2
The values in Table 9-11 are measured values of power consumption under the following
conditions:
• Operating conditions, internal core supply (Figure 9-2)
– VVDDIN = 3.3V
– VVDDCORE supplied by the internal regulator in switching mode
• TA = 25°C
• Oscillators
– OSC0 (crystal oscillator) stopped
– OSC32K (32KHz crystal oscillator) running with external 32KHz crystal
– DFLL running at 48MHz with OSC32K as reference clock
• Clocks
– DFLL used as main clock source
– CPU, AHB, and PB clocks undivided
• I/Os are inactive with internal pull-up
• Flash enabled in high speed mode
• CPU in SLEEP0 mode
• BOD18 and BOD33 disabled
Consumption active is the added current consumption when the module clock is turned on.
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Table 9-11. Typical Current Consumption by Peripheral in Power Scaling Mode 0 and 2 (1)
Peripheral
IISC
Typ Consumption Active
Unit
1.0
1.9
6.3
1.5
1.2
8.5
3.1
1.3
3.1
0.4
0.7
0.9
0.7
3.0
4.4
1.0
0.3
1.5
5.6
0.1
6.4
0.5
7.1
0.9
4.6
1.5
1.4
0.6
0.3
SPI
TC
TWIM
TWIS
USART
ADCIFE(2)
DACC
ACIFC (2)
GLOC
ABDACB
TRNG
PARC
CATB
LCDCA
PDCA
CRCCU
USBC
PEVC
CHIPID
SCIF
µA/MHz
FREQM
GPIO
BPM
BSCIF
AST
WDT
EIC
PICOUART
1.
2.
These numbers are valid for the measured condition only and must not be extrapolated to other
frequencies
Includes the current consumption on VDDANA and ADVREFP.
9.5.4
.Peripheral Power Consumption in Power Scaling mode 1
The values in Table 9-13 are measured values of power consumption under the following
conditions:
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• Operating conditions, internal core supply (Figure 9-2)
– VVDDIN = 3.3V
– VVDDCORE = 1.2 V, supplied by the internal regulator in switching mode
• TA = 25°C
• Oscillators
– OSC0 (crystal oscillator) stopped
– OSC32K (32KHz crystal oscillator) running with external 32KHz crystal
– RCFAST running @ 12MHz
• Clocks
– RCFAST used as main clock source
– CPU, AHB, and PB clocks undivided
• I/Os are inactive with internal pull-up
• Flash enabled in normal mode
• CPU in SLEEP0 mode
• BOD18 and BOD33 disabled
Consumption active is the added current consumption when the module clock is turned on
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Table 9-12. Typical Current Consumption by Peripheral in Power Scaling Mode 1 (1)
Peripheral
IISC
Typ Consumption Active
Unit
0.5
1.1
3.1
0.8
0.7
4.4
1.6
0.6
1.6
0.1
0.3
0.3
0.3
1.5
2.2
0.4
0.3
0.9
2.8
0.1
3.1
0.2
3.4
0.4
2.3
0.8
0.8
0.3
0.2
SPI
TC
TWIM
TWIS
USART
ADCIFE(2)
DACC
ACIFC (2)
GLOC
ABDACB
TRNG
PARC
CATB
LCDCA
PDCA
CRCCU
USBC
PEVC
CHIPID
SCIF
µA/MHz
FREQM
GPIO
BPM
BSCIF
AST
WDT
EIC
PICOUART
1.
2.
These numbers are valid for the measured condition only and must not be extrapolated to other
frequencies
Includes the current consumption on VDDANA and ADVREFP.
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9.6
I/O Pin Characteristics
9.6.1
Normal I/O Pin
Table 9-13. Normal I/O Pin Characteristics (1)
Symbol
RPULLUP
RPULLDOWN
VIL
Parameter
Conditions
Min
Typ
40
Max
Units
kΩ
Pull-up resistance (2)
Pull-down resistance(2)
Input low-level voltage
Input high-level voltage
Output low-level voltage
Output high-level voltage
40
kΩ
-0.3
0.2 * VVDD
VVDD + 0.3
0.4
VIH
0.8 * VVDD
V
VOL
VOH
VVDD - 0.4
1.68V<VVDD<2.7V
2.7V<VVDD<3.6V
1.68V<VVDD<2.7V
2.7V<VVDD<3.6V
1.68V<VVDD<2.7V
2.7V<VVDD<3.6V
1.68V<VVDD<2.7V
2.7V<VVDD<3.6V
0.8
1.6
1.6
3.2
0.8
1.6
1.6
3.2
35
ODCR0=0
ODCR0=1
ODCR0=0
ODCR0=1
mA
mA
mA
mA
IOL
Output low-level current (3)
Output high-level current(3)
IOH
OSRR0=0
OSRR0=1
OSRR0=0
OSRR0=1
OSRR0=0
OSRR0=1
OSRR0=0
OSRR0=1
ODCR0=0
1.68V<VVDD<2.7V,
load = 25pF
ns
ns
ns
ns
45
19
23
36
47
20
24
tRISE
Rise time(2)
ODCR0=0
2.7V<VVDD<3.6V,
load = 25pF
ODCR0=0
1.68V<VVDD<2.7V,
load = 25pF
tFALL
Fall time(2)
ODCR0=0
2.7V<VVDD<3.6V,
load = 25pF
OSRR0=0
OSRR0=1
OSRR0=0
OSRR0=1
17
15
27
23
MHz
MHz
MHz
MHz
ODCR0=0, VVDD>2.7V
load = 25pF
FPINMAX
Output frequency(2)
ODCR0=1, VVDD>2.7V
load = 25pF
Pull-up resistors
disabled
ILEAK
CIN
Input leakage current(3)
Input capacitance(2)
0.01
5
1
µA
pF
1.
2.
VVDD corresponds to either VVDDIN or VVDDIO, depending on the supply for the pin. Refer to Section 3-5 on page 13 for details
These values are based on simulation. These values are not covered by test limits in production or characterization
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3.
These values are based on characterization. These values are not covered by test limits in production
High-drive I/O Pin : PA02, PC04, PC05, PC06
9.6.2
Table 9-14. High-drive I/O Pin Characteristics (1)
Symbol
RPULLUP
RPULLDOWN
VIL
Parameter
Conditions
Min
Typ
40
Max
Units
kΩ
Pull-up resistance (2)
Pull-down resistance(2)
Input low-level voltage
Input high-level voltage
Output low-level voltage
Output high-level voltage
40
kΩ
-0.3
0.2 * VVDD
VVDD + 0.3
0.4
VIH
0.8 * VVDD
V
VOL
VOH
VVDD - 0.4
1.68V<VVDD<2.7V
2.7V<VVDD<3.6V
1.68V<VVDD<2.7V
2.7V<VVDD<3.6V
1.68V<VVDD<2.7V
2.7V<VVDD<3.6V
1.68V<VVDD<2.7V
2.7V<VVDD<3.6V
1.8
3.2
3.2
6
ODCR0=0
ODCR0=1
ODCR0=0
ODCR0=1
mA
mA
mA
mA
IOL
Output low-level current (3)
Output high-level current(3)
1.6
3.2
3.2
6
IOH
OSRR0=0
OSRR0=1
OSRR0=0
OSRR0=1
OSRR0=0
OSRR0=1
OSRR0=0
OSRR0=1
ODCR0=0
20
1.68V<VVDD<2.7V,
Cload = 25pF
ns
ns
ns
ns
40
11
18
20
40
11
18
tRISE
Rise time(2)
ODCR0=0
2.7V<VVDD<3.6V,
Cload = 25pF
ODCR0=0
1.68V<VVDD<2.7V,
Cload = 25pF
tFALL
Fall time(2)
ODCR0=0
2.7V<VVDD<3.6V,
Cload = 25pF
OSRR0=0
OSRR0=1
OSRR0=0
OSRR0=1
22
17
35
26
2
MHz
MHz
MHz
MHz
µA
ODCR0=0, VVDD>2.7V
load = 25pF
FPINMAX
Output frequency(2)
ODCR0=1, VVDD>2.7V
load = 25pF
ILEAK
CIN
Input leakage current(3)
Input capacitance(2)
Pull-up resistors disabled
0.01
10
pF
1.
2.
3.
VVDD corresponds to either VVDDIN or VVDDIO, depending on the supply for the pin. Refer to Section 3-5 on page 13 for details
These values are based on simulation. These values are not covered by test limits in production or characterization
These values are based on characterization. These values are not covered by test limits in production
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9.6.3
USB I/O Pin : PA25, PA26
Table 9-15. USB I/O Pin Characteristics in GPIO configuration (1)
Symbol
RPULLUP
RPULLDOWN
VIL
Parameter
Conditions
Min
Typ
40
Max
Units
kΩ
Pull-up resistance (2)
Pull-down resistance(2)
Input low-level voltage
Input high-level voltage
Output low-level voltage
Output high-level voltage
40
kΩ
-0.3
0.2 * VVDD
VVDD + 0.3
0.4
VIH
0.8 * VVDD
V
VOL
VOH
VVDD - 0.4
1.68V<VVDD<2.7V
2.7V<VVDD<3.6V
1.68V<VVDD<2.7V
2.7V<VVDD<3.6V
20
30
20
30
IOL
Output low-level current (3)
ODCR0=0
mA
IOH
Output high-level current(3) ODCR0=0
mA
ODCR0=0
Maximum frequency(2)
OSRR0=0
FPINMAX
20
1
MHz
load = 25pF
ILEAK
CIN
Input leakage current(3)
Input capacitance(2)
Pull-up resistors disabled
0.01
5
µA
pF
1.
2.
3.
VVDD corresponds to either VVDDIN or VVDDIO, depending on the supply for the pin. Refer to Section 3-5 on page 13 for details
These values are based on simulation. These values are not covered by test limits in production or characterization
These values are based on characterization. These values are not covered by test limits in production
9.6.4
TWI Pin : PA21, PA22, PA23, PA24, PB14, PB15
Table 9-16. TWI Pin Characteristics in TWI configuration (1)
Symbol
RPULLUP
RPULLDOWN
VIL
Parameter
Conditions
Min
Typ
40
Max
Units
kΩ
kΩ
V
Pull-up resistance (2)
Pull-down resistance(2)
Input low-level voltage
Input high-level voltage
Output low-level voltage
40
-0.3
0.3 * VVDD
VVDD + 0.3
0.4
VIH
0.7 * VVDD
V
VOL
V
DRIVEL=0
DRIVEL=1
DRIVEL=2
DRIVEL=3
DRIVEL=4
DRIVEL=5
DRIVEL=6
DRIVEL=7
0.5
1.0
1.6
3.1
IOL
Output low-level current (3)
mA
6.2
9.3
15.5
21.8
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Table 9-16. TWI Pin Characteristics in TWI configuration (1)
Symbol
Parameter
Conditions
DRIVEH=0
DRIVEH=1
DRIVEH=2
DRIVEH=3
Min
Typ
0.5
1
Max
Units
ICS
Current Source(3)
mA
1.5
3
HsMode with Current source;
DRIVEx=3, SLEW=0
fMAX
Max frequency(2)
Rise time(2)
3.5
6.4
28
50
50
MHz
ns
Cbus = 400pF, VVDD = 1.68V
HsMode Mode, DRIVEx=3, SLEW=0
Cbus = 400pF, Rp = 440Ohm,
tRISE
38
95
95
VVDD = 1.68V
Standard Mode, DRIVEx=3, SLEW=0
Cbus = 400pF, Rp = 440Ohm,
VVDD = 1.68V
tFALL
Fall time(2)
ns
HsMode Mode, DRIVEx=3, SLEW=0
Cbus = 400pF, Rp = 440Ohm,
VVDD = 1.68V
1.
2.
3.
VVDD corresponds to either VVDDIN or VVDDIO, depending on the supply for the pin. Refer to Section 3-5 on page 13 for details
These values are based on simulation. These values are not covered by test limits in production or characterization
These values are based on characterization. These values are not covered by test limits in production
Table 9-17. TWI Pin Characteristics in GPIO configuration (1)
Symbol
RPULLUP
RPULLDOWN
VIL
Parameter
Conditions
Min
Typ
40
Max
Units
kΩ
kΩ
V
Pull-up resistance (2)
Pull-up resistance(2)
Input low-level voltage
Input high-level voltage
Output low-level voltage
Output high-level voltage
40
-0.3
0.2 * VVDD
VVDD + 0.3
0.4
VIH
0.8 * VVDD
V
VOL
V
VOH
VVDD - 0.4
1.68V<VVDD<2.7V
2.7V<VVDD<3.6V
1.68V<VVDD<2.7V
2.7V<VVDD<3.6V
1.68V<VVDD<2.7V
2.7V<VVDD<3.6V
1.68V<VVDD<2.7V
2.7V<VVDD<3.6V
1.8
3.5
3.6
6.8
1.8
3.5
3.6
6.8
ODCR0=0
ODCR0=1
ODCR0=0
ODCR0=1
IOL
Output low-level current (3)
Output high-level current(3)
mA
mA
IOH
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Table 9-17. TWI Pin Characteristics in GPIO configuration (1)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
OSRR0=0
ODCR0=0
18
1.68V<VVDD<2.7V,
Cload = 25pF
ns
OSRR0=1
OSRR0=0
OSRR0=1
OSRR0=0
OSRR0=1
OSRR0=0
OSRR0=1
110
10
tRISE
Rise time(2)
ODCR0=0
2.7V<VVDD<3.6V,
Cload = 25pF
ns
ns
ns
50
ODCR0=0
19
1.68V<VVDD<2.7V,
Cload = 25pF
140
12
tFALL
Fall time(2)
ODCR0=0
2.7V<VVDD<3.6V,
Cload = 25pF
63
1.
2.
3.
VVDD corresponds to either VVDDIN or VVDDIO, depending on the supply for the pin. Refer to Section 3-5 on page 13 for details
These values are based on simulation. These values are not covered by test limits in production or characterization
These values are based on characterization. These values are not covered by test limits in production
Table 9-18. Common TWI Pin Characteristics
Symbol
ILEAK
Parameter
Conditions
Min
Typ
0.01
5
Max
Units
µA
Input leakage current (1)
Input capacitance(2)
Pull-up resistors disabled
1
CIN
pF
1.
These values are based on simulation. These values are not covered by test limits in production or characterization
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9.6.5
High Drive TWI Pin : PB00, PB01
Table 9-19. High Drive TWI Pin Characteristics in TWI configuration (1)
Symbol
RPULLUP
RPULLDOWN
VIL
Parameter
Conditions
Min
Typ
40
Max
Units
kΩ
Pull-up resistance (2)
Pull-down resistance(2)
Input low-level voltage
Input high-level voltage
Output low-level voltage
Output high-level voltage
PB00, PB01
40
kΩ
-0.3
0.3 * VVDD
VVDD + 0.3
0.4
VIH
0.7 * VVDD
V
VOL
VOH
VVDD - 0.4
DRIVEL=0
DRIVEL=1
DRIVEL=2
DRIVEL=3
DRIVEL=4
DRIVEL=5
DRIVEL=6
DRIVEL=7
DRIVEH=0
DRIVEH=1
DRIVEH=2
DRIVEH=3
0.5
1.0
1.6
3.1
IOL
Output low-level current (3)
mA
6.2
9.3
15.5
21.8
0.5
1
ICS
Current Source(2)
mA
1.5
3
HsMode with Current source;
DRIVEx=3, SLEW=0
fMAX
Max frequency(2)
Rise time(2)
3.5
6.4
28
50
50
MHz
ns
Cbus = 400pF, VVDD = 1.68V
HsMode Mode, DRIVEx=3, SLEW=0
Cbus = 400pF, Rp = 440Ohm,
VVDD = 1.68V
tRISE
38
95
95
Standard Mode, DRIVEx=3, SLEW=0
Cbus = 400pF, Rp = 440Ohm,
VVDD = 1.68V
tFALL
Fall time(2)
ns
HsMode Mode, DRIVEx=3, SLEW=0
Cbus = 400pF, Rp = 440Ohm,
VVDD = 1.68V
1.
2.
3.
VVDD corresponds to either VVDDIN or VVDDIO, depending on the supply for the pin. Refer to Section 3-5 on page 13 for details
These values are based on simulation. These values are not covered by test limits in production or characterization
These values are based on characterization. These values are not covered by test limits in production
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Table 9-20. High Drive TWI Pin Characteristics in GPIO configuration (1)
Symbol
RPULLUP
RPULLDOWN
VIL
Parameter
Conditions
Min
Typ
40
Max
Units
kΩ
Pull-up resistance (2)
Pull-up resistance(2)
Input low-level voltage
Input high-level voltage
Output low-level voltage
Output high-level voltage
40
kΩ
-0.3
0.2 * VVDD
VVDD + 0.3
0.4
VIH
0.8 * VVDD
V
VOL
VOH
VVDD - 0.4
1.68V<VVDD<2.7V
2.7V<VVDD<3.6V
1.68V<VVDD<2.7V
2.7V<VVDD<3.6V
1.68V<VVDD<2.7V
2.7V<VVDD<3.6V
1.68V<VVDD<2.7V
2.7V<VVDD<3.6V
3.4
6
ODCR0=0
ODCR0=1
ODCR0=0
ODCR0=1
mA
mA
mA
mA
IOL
Output low-level current (3)
Output high-level current(3)
5.2
8
3.4
6
IOH
5.2
8
OSRR0=0
OSRR0=1
OSRR0=0
OSRR0=1
OSRR0=0
OSRR0=1
OSRR0=0
OSRR0=1
ODCR0=0
18
110
10
1.68V<VVDD<2.7V,
Cload = 25pF
ns
ns
ns
ns
tRISE
Rise time(2)
ODCR0=0
2.7V<VVDD<3.6V,
Cload = 25pF
50
ODCR0=0
19
1.68V<VVDD<2.7V,
Cload = 25pF
140
12
tFALL
Fall time(2)
ODCR0=0
2.7V<VVDD<3.6V,
Cload = 25pF
63
1.
2.
3.
VVDD corresponds to either VVDDIN or VVDDIO, depending on the supply for the pin. Refer to Section 3-5 on page 13 for details
These values are based on simulation. These values are not covered by test limits in production or characterization
These values are based on characterization. These values are not covered by test limits in production
Table 9-21. Common High Drive TWI Pin Characteristics
Symbol
ILEAK
Parameter
Conditions
Min
Typ
0.01
10
Max
Units
µA
Input leakage current (1)
Input capacitance(1)
Pull-up resistors disabled
2
CIN
pF
1.
These values are based on simulation. These values are not covered by test limits in production or characterization
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9.7
Oscillator Characteristics
Oscillator 0 (OSC0) Characteristics
Digital Clock Characteristics
9.7.1
9.7.1.1
The following table describes the characteristics for the oscillator when a digital clock is applied
on XIN.
Table 9-22. Digital Clock Characteristics
Symbol
fCPXIN
Parameter
Conditions
Min
Typ
Max
50
Units
MHz
%
XIN clock frequency (1)
XIN clock duty cycle(1)
Startup time
tCPXIN
40
60
tSTARTUP
N/A
cycles
1.
These values are based on simulation. These values are not covered by test limits in production or characterization.
9.7.1.2
Crystal Oscillator Characteristics
The following table describes the characteristics for the oscillator when a crystal is connected
between XIN and XOUT as shown in Figure 9-3. The user must choose a crystal oscillator
where the crystal load capacitance CL is within the range given in the table. The exact value of CL
can be found in the crystal datasheet. The capacitance of the external capacitors (CLEXT) can
then be computed as follows:
CLEXT = 2(CL – CSTRAY–CSHUNT
)
where CSTRAY is the capacitance of the pins and PCB, CSHUNT is the shunt capacitance of the
crystal.
Table 9-23. Crystal Oscillator Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fOUT
Crystal oscillator frequency (1)
0.6
30
MHz
f = 0.455MHz, CLEXT = 100pF
SCIF.OSCCTRL.GAIN = 0
17000
2000
1500
300
f = 2MHz, CLEXT = 20pF
SCIF.OSCCTRL.GAIN = 0
f = 4MHz, CLEXT = 20pF
SCIF.OSCCTRL.GAIN = 1
ESR
Crystal Equivalent Series Resistance (2)
Ω
f = 8MHz, CLEXT = 20pF
SCIF.OSCCTRL.GAIN = 2
f = 16MHz, CLEXT = 20pF
SCIF.OSCCTRL.GAIN = 3
350
f = 30MHz, CLEXT = 18pF
SCIF.OSCCTRL.GAIN = 4
45
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Table 9-23. Crystal Oscillator Characteristics
Symbol
CL
Parameter
Conditions
Min
Typ
Max
18
7
Unit
pF
Crystal load capacitance(1)
Crystal shunt capacitance(1)
Parasitic capacitor load(2)
Parasitic capacitor load(2)
Startup time(1)
6
CSHUNT
CXIN
CXOUT
tSTARTUP
4.91
3.22
TQFP100 package
SCIF.OSCCTRL.GAIN = 2
30000(3)
cycles
Active mode, f = 0.6MHz,
SCIF.OSCCTRL.GAIN = 0
30
Active mode, f = 4MHz,
130
260
590
960
SCIF.OSCCTRL.GAIN = 1
Active mode, f = 8MHz,
IOSC
Current consumption(1)
µA
SCIF.OSCCTRL.GAIN = 2
Active mode, f = 16MHz,
SCIF.OSCCTRL.GAIN = 3
Active mode, f = 30MHz,
SCIF.OSCCTRL.GAIN = 4
1.
2.
3.
These values are based on simulation. These values are not covered by test limits in production or characterization.
These values are based on characterization. These values are not covered by test limits in production.
Nominal crystal cycles.
Figure 9-3. Oscillator Connection
Xin
CLEXT
Crystal
LM
CSHUNT
RM
CSTRAY
CM
Xout
CLEXT
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9.7.2
32kHz Crystal Oscillator (OSC32K) Characteristics
Figure 9-3 and the equation above also applies to the 32kHz oscillator connection. The user
must choose a crystal oscillator where the crystal load capacitance CL is within the range given
in the table. The exact value of CL can then be found in the crystal datasheet.
Table 9-24. Digital Clock Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
6
Units
MHz
%
fCPXIN32
XIN32 clock frequency (1)
XIN32 clock duty cycle(1)
Startup time
40
60
tSTARTUP
N/A
cycles
1.
These values are based on simulation. These values are not covered by test limits in production or characterization.
Table 9-25. 32 kHz Crystal Oscillator Characteristics
Symbol
fOUT
Parameter
Conditions
Min
Typ
Max
Unit
Hz
Crystal oscillator frequency
Startup time (1)
32 768
30000(2)
tSTARTUP
CL
CSHUNT
CXIN
CXOUT
IOSC32K
Rm = 100kΩ, CL = 12.5pF
cycles
Crystal load capacitance(1)
Crystal shunt capacitance(1)
Parasitic capacitor load (3)
Parasitic capacitor load(3)
Current consumption(1)
6
12.5
1.7
0.8
pF
nA
kΩ
3.4
2.72
350
TQFP100 package
OSCCTRL32.SELCURR=0
OSCCTRL32.SELCURR=4
OSCCTRL32.SELCURR=8
OSCCTRL32.SELCURR=15
OSCCTRL32.SELCURR=0
OSCCTRL32.SELCURR=4
OSCCTRL32.SELCURR=8
OSCCTRL32.SELCURR=15
OSCCTRL32.SELCURR=4
OSCCTRL32.SELCURR=6
OSCCTRL32.SELCURR=8
OSCCTRL32.SELCURR=10
OSCCTRL32.SELCURR=15
28
72
CL=6pF
CL=9pF
Crystal equivalent series
resistance(1)
114
313
14
f=32.768kHz
OSCCTRL32.MODE=1
Safety Factor = 3
36
kΩ
kΩ
ESRXTAL
100
170
15.2
61.8
101.8
138.5
228.5
Crystal equivalent series
resistance(3)
f=32.768kHz
CL=12.5pF
OSCCTRL32.MODE=1
Safety Factor = 3
1.
2.
3.
These values are based on simulation. These values are not covered by test limits in production or characterization.
Nominal crystal cycles.
These values are based on characterization. These values are not covered by test limits in production.
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9.7.3
Phase Locked Loop (PLL) Characteristics
Table 9-26. Phase Locked Loop Characteristics
Symbol
fOUT
Parameter
Conditions
Min
48
4
Typ
Max
240
16
Unit
Output frequency (1)
Input frequency(1)
PLL is not availabe in PS1
MHz
fIN
fout=80MHz
200
500
8
IPLL
Current consumption(1)
µA
µs
fout=240MHz
Startup time, from enabling
the PLL until the PLL is
locked(1)
Wide Bandwidth mode disabled
tSTARTUP
Wide Bandwidth mode enabled
30
1.
These values are based on simulation. These values are not covered by test limits in production or characterization.
9.7.4
Digital Frequency Locked Loop (DFLL) Characteristics
Table 9-27. Digital Frequency Locked Loop Characteristics
Symbol
fOUT
Parameter
Conditions
Min
20
8
Typ
Max
150
150
0.5
Unit
MHz
kHz
Output frequency (1)
Reference frequency(1)
DFLL is not availabe in PS1
fREF
FINE lock, fREF = 32kHz, SSG disabled(2)
0.1
ACCURATE lock, fREF = 32kHz, dither
clk RCSYS/2, SSG disabled(2)
0.06
0.5
1
Accuracy(1)
%
FINE lock, fREF = 8-150kHz, SSG
disabled(2)
0.2
0.1
509
ACCURATE lock, fREF = 8-150kHz,
dither clk RCSYS/2, SSG disabled(2)
1
RANGE 0 96 to 220MHz
430
1545
218
704
140
365
122
288
545
COARSE=0, FINE=0, DIV=0
RANGE 0 96 to 220MHz
1858
271
827
187
441
174
354
1919
308
862
226
477
219
391
COARSE=31, FINE=255, DIV=0
RANGE 1 50 to 110MHz
COARSE=0, FINE=0, DIV=0
RANGE 1 50 to 110MHz
COARSE=31, FINE=255, DIV=0
IDFLL
Power consumption(1)
µA
RANGE 2 25 to 55MHz
COARSE=0, FINE=0, DIV=1
RANGE 2 25 to 55MHz
COARSE=31, FINE=255, DIV=1
RANGE 3 20 to 30MHz
COARSE=0, FINE=0, DIV=1
RANGE 3 20 to 30MHz
COARSE=31, FINE=255, DIV=1
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Table 9-27. Digital Frequency Locked Loop Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tSTARTUP
Startup time(1)
Within 90% of final values
fREF = 32kHz, FINE lock, SSG disabled(2)
100
µs
600
tLOCK
Lock time(1)
f
REF = 32kHz, ACCURATE lock, dithering
1100
clock = RCSYS/2, SSG disabled(2)
1.
2.
These values are based on simulation. These values are not covered by test limits in production or characterization.
Spread Spectrum Generator (SSG) is disabled by writing a zero to the EN bit in the SCIF.DFLL0SSG register.
9.7.5
32kHz RC Oscillator (RC32K) Characteristics
Table 9-28. 32kHz RC Oscillator Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Calibrated against a 32.768kHz
reference
fOUT
Output frequency (1)
20
32.768
44
kHz
Temperature compensation disabled
Without temperature compensation
Temperature compensation enabled
0.5
2
µA
µA
IRC32K
Current consumption (2)
Startup time(1)
tSTARTUP
1
cycle
1.
2.
These values are based on characterization. These values are not covered by test limits in production.
These values are based on simulation. These values are not covered by test limits in production or characterization.
9.7.6
System RC Oscillator (RCSYS) Characteristics
Table 9-29. System RC Oscillator Characteristics
Symbol
fOUT
Parameter
Conditions
Min
Typ
Max
116
12
Unit
kHz
µA
Output frequency (1)
Current consumption (2)
Startup time(1)
Calibrated at 85°C
110
113.6
IRCSYS
tSTARTUP
Duty
25
38
50
63
µs
Duty cycle(1)
49.6
50.3
%
1.
2.
These values are based on characterization. These values are not covered by test limits in production.
These values are based on simulation. These values are not covered by test limits in production or characterization.
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9.7.7
1MHz RC Oscillator (RC1M) Characteristics
Table 9-30. RC1M Oscillator Characteristics
Symbol
fOUT
Parameter
Conditions
Min
Typ
1
Max
Unit
MHz
µA
Output frequency (1)
Current consumption (2)
Duty cycle(1)
0.91
1.12
IRC1M
Duty
35
48.6
49.9
54.4
%
1.
2.
These values are based on characterization. These values are not covered by test limits in production.
These values are based on simulation. These values are not covered by test limits in production or characterization.
9.7.8
4/8/12MHz RC Oscillator (RCFAST) Characteristics
Table 9-31. RCFAST Oscillator Characteristics
Symbol
Parameter
Conditions
Min
4
Typ
4.3
Max
4.6
Unit
Calibrated, FRANGE=0
Calibrated, FRANGE=1
Calibrated, FRANGE=2
Calibrated, FRANGE=0
Calibrated, FRANGE=1
Calibrated, FRANGE=2
Calibrated, FRANGE=0
Calibrated, FRANGE=1
Calibrated, FRANGE=2
Calibrated, FRANGE=2
fOUT
Output frequency (1)
7.8
11.3
8.2
8.5
MHz
12
12.3
110
90
IRCFAST
Current consumption (2)
130
180
49.6
49.2
48.8
0.31
150
205
50.1
50.1
50.0
0.71
µA
48.8
47.8
46.7
0.1
Duty
Duty cycle(1)
%
tSTARTUP
Startup time(1)
µs
1.
2.
These values are based on characterization. These values are not covered by test limits in production.
These values are based on simulation. These values are not covered by test limits in production or characterization.
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9.7.9
80MHz RC Oscillator (RC80M) Characteristics
Table 9-32. Internal 80MHz RC Oscillator Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
After calibration
fOUT
Output frequency (1)
60
80
100
MHz
Note that RC80M is not available in PS1
IRC80M
tSTARTUP
Duty
Current consumption (2)
Startup time(1)
330
1.72
50
µA
µs
%
0.57
45
3.2
55
Duty cycle(2)
1.
2.
These values are based on characterization. These values are not covered by test limits in production.
These values are based on simulation. These values are not covered by test limits in production or characterization.
9.8
Flash Characteristics
Table 9-33 gives the device maximum operating frequency depending on the number of flash
wait states and the flash read mode. The FWS bit in the FLASHCALW FCR register controls the
number of wait states used when accessing the flash memory.
Table 9-33. Maximum Operating Frequency (1)
Flash Wait
States
Maximum Operating
Frequency
PowerScaling Mode
Flash Read Mode
Unit
Low power (HSDIS) +
Flash internal reference:
BPM.PMCON.FASTWKUP=1
1
12
0
0
1
18
36
Low power(HSDIS)
Low power (HSDIS) +
Flash internal reference:
BPM.PMCON.FASTWKUP=1
MHz
1
12
1
2
0
1
0
1
8
Low power (HSDIS)
High speed (HSEN)
12
24
48
1.
These values are based on simulation. These values are not covered by test limits in production or characterization.
Table 9-34. Flash Characteristics (1)
Symbol
tFPP
Parameter
Conditions
Min
Typ
4.38
4.38
0.63
5.66
304
Max
Unit
Page programming time
Page erase time
tFPE
fCLK_AHB = 48MHz
tFFP
Fuse programming time
Full chip erase time (EA)
JTAG chip erase time (CHIP_ERASE)
ms
tFEA
tFCE
fCLK_AHB = 115kHz
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1.
These values are based on simulation. These values are not covered by test limits in production or characterization.
Table 9-35. Flash Endurance and Data Retention (1)
Symbol
NFARRAY
NFFUSE
tRET
Parameter
Conditions
Min
100k
10k
15
Typ
Max
Unit
cycles
years
Array endurance (write/page)
General Purpose fuses endurance (write/bit)
Data retention
fCLK_AHB > 10MHz
fCLK_AHB > 10MHz
1.
These values are based on simulation. These values are not covered by test limits in production or characterization.
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9.9
Analog Characteristics
9.9.1
Voltage Regulator Characteristics
Table 9-36. VREG Electrical Characteristics in Linear and Switching Modes
Symbol
Parameter
Conditions
Min
Typ
Max
Units
µA
Low power mode (WAIT)
2000
3600
5600
DC output current (1)
Ultra Low power mode
(RETENTION)
Power scaling mode 0 & 2
100
4000
200
180
7000
350
300
10000
600
IOUT
Low power mode (WAIT)
DC output current(1)
Ultra Low power mode
(RETENTION)
Power scaling mode 1
VVDDCORE DC output voltage
1.
Table 9-37. VREG Electrical Characteristics in Linear mode
All modes
1.9
V
These values are based on simulation. These values are not covered by test limits in production.
Symbol
Parameter
Conditions
Min
1.68
1.8
Typ
Max
3.6
Units
I
I
OUT=10mA
OUT=50mA
VVDDIN
Input voltage range
3.6
V
DC output voltage (1)
IOUT = 0 mA
OUT = 50 mA
1.777
1.75
1.814
1.79
1.854
1.83
100
VVDDCORE
IOUT
Power scaling mode 0 & 2
I
DC output current(1)
VVDDCORE > 1.65V
IOUT = 0 to 80mA,
mA
mV
Output DC load regulation(1)
Transient load regulation
-34
10
88
-27
28
-19
48
V
VDDIN = 3V
IOUT = 80 mA,
VDDIN = 2V to 3.6V
Output DC regulation(1)
Quescient current(1)
mV
µA
V
IOUT = 0 mA
IQ
107
128
RUN and SLEEPx modes
1.
These values are based on characterization. These values are not covered by test limits in production.
Table 9-38. External components requirements in Linear Mode
Symbol
CIN1
Parameter
Technology
Typ
33
Units
Input regulator capacitor 1
Input regulator capacitor 2
Input regulator capacitor 3
Output regulator capacitor 1
nF
CIN2
100
10
CIN3
µF
nF
COUT1
100
Tantalum or MLCC
COUT2
Output regulator capacitor 2
4.7
µF
0.5<ESR<10Ω
Table 9-39. VREG Electrical Characteristics in Switching mode
Symbol
Parameter
Conditions
Min
2.0
Typ
Max
3.6
Units
VVDDIN
Input voltage range
VVDDCORE = 1.65V, IOUT=50mA
IOUT = 0 mA
DC output voltage (1)
1.75
1.66
1.82
1.71
1.87
1.79
V
VVDDCORE
Power scaling mode 0 & 2
I
OUT = 50 mA
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Table 9-39. VREG Electrical Characteristics in Switching mode
Symbol
Parameter
Conditions
Min
Typ
Max
Units
IOUT
DC output current(1)
VVDDCORE > 1.65V
IOUT = 0 to 50mA,
55
mA
Output DC load regulation(1)
Transient load regulation
-136
-20
-101
38
-82
99
mV
mV
V
VDDIN = 3V
IOUT = 50 mA,
VDDIN = 2V to 3.6V
Output DC regulation(1)
Quescient current(1)
Power efficiency(1)
V
VVDDIN = 2V, IOUT = 0 mA
VVDDIN > 2.2V, IOUT = 0 mA
97
97
186
111
546
147
IQ
µA
%
IOUT = 5mA, 50mA
PEFF
82.7
88.3
95
Reference power not included
1.
These values are based on characterization. These values are not covered by test limits in production.
Table 9-40. Decoupling Requirements in Switching Mode
Symbol
CIN1
Parameter
Technology
Typ
Units
Input regulator capacitor 1
Input regulator capacitor 2
Input regulator capacitor 3
Output regulator capacitor 1
Output regulator capacitor 2
External inductance
33
100
10
nF
CIN2
CIN3
µF
nF
µF
µH
Ω
COUT1
COUT2
LEXT
X7R MLCC
100
4.7
22
X7R MLCC (ex : GRM31CR71A475)
(ex: Murata LQH3NPN220MJ0)
RDCLEXT
ISATLEXT
Serial resistance of LEXT
Saturation current of LEXT
0.7
300
mA
Note:
1. Refer to Section 6. on page 46.
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9.9.2
Power-on Reset 33 Characteristics
Table 9-41. POR33 Characteristics (1)
Symbol
VPOT+
Parameter
Conditions
Min
1.25
0.95
Typ
Max
1.55
1.30
Units
Voltage threshold on VVDDIN rising
Voltage threshold on VVDDIN falling
V
VPOT-
1.
These values are based on characterization. These values are not covered by test limits in production.
Figure 9-4. POR33 Operating Principle
VPOT+
VPOT-
Time
9.9.3
Brown Out Detectors Characteristics
Table 9-42. BOD18 Characteristics (1)
Symbol
Parameter
Conditions
Min
Typ
10.1
Max
Units
Step size, between adjacent values
in BSCIF.BOD18LEVEL(1)
mV
VHYST
tDET
BOD hysteresis(1)
T = 25°C
3
40
Time with VVDDCORE
BOD18.LEVEL necessary to
generate a reset signal
<
Detection time(1)
1.2
µs
on VDDIN
7.4
14
7
IBOD
Current consumption(1)
Startup time(1)
µA
µs
on VDDCORE
tSTARTUP
4.5
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1.
These values are based on simulation. These values are not covered by test limits in production or characterization.
The values in Table 9-43 describe the values of the BOD33.LEVEL in the flash User Page fuses.
Table 9-43. BOD33.LEVEL Values
BOD33.LEVEL Value
Min
Typ
Max
Units
16
20
24
28
32
36
40
44
48
2.08
2.18
2.33
2.48
2.62
2.77
2.92
3.06
3.21
V
Table 9-44. BOD33 Characteristics (1)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Step size, between adjacent
34.4
values in BSCIF.BOD33LEVEL(1)
mV
VHYST
tDET
Hysteresis(1)
45
170
Time with VDDIN < VTH necessary
to generate a reset signal
Detection time(1)
µs
IBOD33
Current consumption(1)
Startup time(1)
Normal mode
Normal mode
36
6
µA
µs
tSTARTUP
1.
These values are based on simulation. These values are not covered by test limits in production or characterization.
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9.9.4
Analog- to Digital Converter Characteristics
Table 9-45. Operating conditions
Symbol
Parameter
Conditions
Min
Typ
Max
+85
12 (2)
300
250
1.8
Units
°C
Temperature range
Resolution (1)
-40
Max
12
Bit
Differential modes, Gain=1X
Unipolar modes, Gain=1X
Differential modes
Unipolar modes
5
Sampling clock (3)
kHz
MHz
µs
5
0.03
0.03
16.5
16.5
fADC
ADC clock frequency(3)
1.5
Differential modes
Unipolar modes
277
333
300
TSAMPLEHOLD
Sampling time(3)
Conversion rate(1)
1X gain, differential
kSps
kSps
Internal channel conversion
rate(3)
VVDD/10, Bandgap and
Temperature channels
125
1X gain, (resolution/2)+gain (4)
6
7
2X and 4X gain
Conversion time (latency)
8X and 16X gain
8
Cycles
Differential mode (no windowing)
32X and 64X gain
9
64X gain and unipolar
10
1.
2.
3.
4.
These values are based on characterization. These values are not covered by test limits in production
Single ended or using divide by two max resolution: 11 bits
These values are based on simulation. These values are not covered by test limits in production
See Figure 9-5
Figure 9-5. Maximum input common mode voltage
MAX input comm on m ode voltage
3
2.5
2
vc m _vref= 3V
vc m _vref= 1V
1.5
1
0.5
0
1.6
3.6
V cc
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Table 9-46. DC Characteristics
Symbol Parameter
Conditions
Min
Typ
Max
Units
VDDANA Supply voltage (1)
1.6
3.6
V
VDDANA
-0.6
Differential mode
1.0
1.0
2.0
Reference range (2)
Unipolar and Window modes
1.0
V
Using divide by two function
(differential)
VDDANA
VDDANA
+0.1
Absolute min, max input voltage(2)
-0,1
V
Cycles
µs
ADC with reference already
enabled
12
24
5
No gain compensation
Reference buffer
Start up time(2)
Gain compensation
Reference buffer
60
Cycles
RSAMPLE
CSAMPLE
Input channel source resistance(2)
Sampling capacitance(2)
0.5
4.3
2
kΩ
pF
2.9
3.6
5
Gain compensation
kΩ
MΩ
Reference input source resistance(2)
ADC reference settling time(2)
No gain compensation
1
After changing
60
Cycles
reference/mode (3)
1.
2.
3.
These values are based on characterization. These values are not covered by test limits in production
These values are based on simulation. These values are not covered by test limits in production
Requires refresh/flush otherwise conversion time (latency) + 1
Table 9-47. Differential mode, gain=1
Symbol
Parameter
Conditions
Min
Typ
Max
Units
ENOB
ENOB
Accuracy without compensation (1)
Accuracy after compensation(1)
7
(INL, gain and offset)
11
After calibration,
INL
Integral Non Linearity (2)
1.2
1.7
LSBs
LSBs
Gain compensation
DNL
Differential Non Linearity(2)
After calibration
0.7
1.0
5.0
40
40
30
2
External reference
VDDANA/1.6
-5.0
-40
-40
-30
-2
-1.0
Gain error (2)
mV
VDDANA/2.0
Bandgap After calibration
External reference
Gain error drift vs voltage(1)
mV/V
After calibration + bandgap drift
If using onchip bandgap
Gain error drift vs temperature(1)
0.08
mV/°K
External reference
VDDANA/1.6
-5.0
-10
-10
-10
-4
5.0
10
10
10
4
Offset error (2)
mV
VDDANA/2.0
Bandgap After calibration
Offset error drift vs voltage(1)
mV/V
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Table 9-47. Differential mode, gain=1
Offset error drift vs temperature(1)
Conversion range (2)
0.04
Vref
mV/°K
V
Vin-Vip
-Vref
see
Figure
9-5
ICMR(1)
fvdd=1Hz, ext ADVREFP=3.0V
VVDD=3.6V
100
50
PSRR(1)
dB
fvdd=2MHz, ext
ADVREFP=3.0V VVDD=3.6
VDDANA=3.6V,
ADVREFP=3.0V
1.2
0.6
DC supply current (2)
mA
VDDANA=1.6V,
ADVREFP=1.0V
1.
2.
These values are based on simulation only. These values are not covered by test limits in production or characterization
These values are based on characterization and not tested in production, and valid for an input voltage between 10% to 90% of
reference voltage.
Table 9-48. Unipolar mode, gain=1
Symbol
Parameter
Conditions
Min
Typ
Max
Units
ENOB
ENOB
Accuracy without compensation (1)
Accuracy after compensation(1)
7
11
±3
After calibration Dynamic tests
No gain compensation
INL
Integral Non Linearity (2)
LSBs
LSBs
After calibration Dynamic tests
Gain compensation
±3
DNL
Differential Non Linearity(2)
After calibration
±2.8
15
50
30
10
8
External reference
VDDANA/1.6
-15
-50
-30
-10
-8
Gain error(2)
mV
VDDANA/2.0
Bandgap After calibration
External reference
Gain error drift vs voltage(1)
Gain error drift temperature(1)
mV/V
+ bandgap drift If using
bandgap
0.08
mV/°K
External reference
VDDANA/1.6
-15
-15
-15
-10
-4
15
15
Offset error(2)
mV
VDDANA/2.0
15
Bandgap After calibration
10
Offset error drift(1)
Offset error drift temperature(1)
Conversion range(1)
4
mV/V
mV/°K
V
0
0.04
Vref
Vin-Vip
-Vref
see
Figure
9-5
ICMR(1)
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Table 9-48. Unipolar mode, gain=1
fVdd=100kHz, VDDIO=3.6V
fVdd=1MHz, VDDIO=3.6V
VDDANA=3.6V
62
dB
49
PSRR(1)
1
2
DC supply current(1)
mA
VDDANA=1.6V,
ADVREFP=1.0V
1
1.3
1.
2.
These values are based on simulation. These values are not covered by test limits in production or characterization.
These values are based on characterization and not tested in production, and valid for an input voltage between 10% to 90% of
reference voltage.
9.9.4.1
Inputs and Sample and Hold Acquisition Times
The analog voltage source must be able to charge the sample and hold (S/H) capacitor in the
ADC in order to achieve maximum accuracy. Seen externally the ADC input consists of a resis-
tor (RSAMPLE ) and a capacitor (CSAMPLE ). In addition, the source resistance (RSOURCE ) must be
taken into account when calculating the required sample and hold time. Figure 9-6 shows the
ADC input channel equivalent circuit.
Figure 9-6. ADC Input
VDDANA/2
Analog Input
CSAMPLE
RSOURCE
ADx
RSAMPLE
VIN
To achieve n bits of accuracy, the CSAMPLE capacitor must be charged at least to a voltage of
VCSAMPLE ≥ VIN × (1 – 2–(n + 1)
)
The minimum sampling time tSAMPLEHOLD for a given RSOURCE can be found using this formula:
tSAMPLEHOLD ≥ (RSAMPLE + RSOURCE) × (CSAMPLE) × (n + 1) × ln(2)
for a 12 bits accuracy :
tSAMPLEHOLD ≥ (RSAMPLE + RSOURCE) × (CSAMPLE) × 9, 02
where
1
tSAMPLEHOLD = -----------------------
2 × fADC
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9.9.5
Digital to Analog Converter Characteristics
Table 9-49. Operating conditions
Symbol
Parameter
Conditions
on VDDANA
on VDDCORE
Min
2.4
Typ
3
Max
3.6
Units
V
Analog Supply Voltage (1)
Digital Supply Voltage(1)
Resolution (2)
1.62
1.8
10
1.98
V
bits
kHz
pF
Clock frequency(1)
Cload = 50pF ; Rload = 5kΩ
CLoad
500
50
Load(1)
RLoad
5
kΩ
INL
Integral Non Linearity (1)
Differential Non Linearity (1)
Zero Error (offset) (1)
Gain Error (1)
Best fit-line method
Best fit-line method
CDR[9:0] = 0
±2
+1
5
LSBs
LSBs
mV
mV
DNL
-0.9
1
5
CDR[9:0] = 1023
10
80% of VDDANA @ fin =
70kHz
Total Harmonic Distortion(1)
-56
7
dB
CDR[9:0] = 512/ Cload = 50 pF
/ Rload = 5 kΩ
Delay to vout (1)
Startup time(1)
2
5
0
µs
µs
V
CDR[9:0] = 512
9
(ADVREFP < VDDANA –
100mV) is mandatory
ADVREFP
Output Voltage Range
(ADVREFP < VDDANA –
100mV) is mandatory
ADVREFP Voltage Range(1)
ADVREFN Voltage Range(1)
2.3
3.5
V
V
ADVREFP = GND
On VDDANA
0
500
100
660
Standby Current(1)
nA
On VDDCORE
On VDDANA (no Rload)
485
250
DC Current consumption(1)
µA
On ADVREFP
295
(CDR[9:0] = 512)
1.
2.
These values are based on simulation. These values are not covered by test limits in production or characterization
These values are based on characterization. These values are not covered by test limits in production
9.9.6
Analog Comparator Characteristics
Table 9-50. Analog Comparator Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Positive input voltage
range
0.1
VDDIO-0.1
V
Negative input voltage
range
0.1
-12
VDDIO-0.1
13
VACREFN =0.1V to VDDIO-0.1V,
hysteresis = 0 (2)
mV
mV
Fast mode
Offset (1)
V
ACREFN =0.1V to VDDIO-0.1V,
hysteresis = 0(2)
-11
12
Low power mode
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Table 9-50. Analog Comparator Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VACREFN =0.1V to VDDIO-0.1V,
hysteresis = 1(2)
10
55
mV
Fast mode
VACREFN =0.1V to VDDIO-0.1V,
hysteresis = 1(2)
10
26
19
43
32
68
83
mV
mV
mV
mV
mV
ns
Low power mode
VACREFN =0.1V to VDDIO-0.1V,
hysteresis = 2(2)
Fast mode
Hysteresis(1)
VACREFN =0.1V to VDDIO-0.1V,
hysteresis = 2(2)
91
Low power mode
VACREFN =0.1V to VDDIO-0.1V,
hysteresis = 3(2)
106
136
67
Fast mode
VACREFN =0.1V to VDDIO-0.1V,
hysteresis = 3(2)
Low power mode
Changes for VACM=VDDIO/2
100mV Overdrive
Fast mode
Propagation delay(1)
Changes for VACM=VDDIO/2
100mV Overdrive
315
ns
Low power mode
Enable to ready delay
Fast mode
1.19
3.61
µs
µs
tSTARTUP
Startup time(1)
Enable to ready delay
Low power mode
Low power mode, no hysteresis
Fast mode, no hysteresis
4.9
63
8.7
Channel current
consumption (3)
IAC
µA
127
1.
2.
3.
These values are based on characterization. These values are not covered by test limits in production
HYSTAC.CONFn.HYS field, refer to the Analog Comparator Interface chapter
These values are based on simulation. These values are not covered by test limits in production or characterization
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9.9.7
Liquid Crystal Display Controler characteristics
Table 9-51. Liquid Crystal Display Controler characteristics
Symbol
SEG
Parameter
Conditions
Min
Typ
Max
40
Units
Segment Terminal Pins
Common Terminal Pins
LCD Frame Frequency
Flying Capacitor
COM
4
fFrame
FCLKLCD
31.25
512
Hz
nF
CFlying
VLCD
100
3
LCD Regulated Voltages (1)
CFG.FCST=0
C
Flying = 100nF
BIAS2
BIAS1
2*VLCD/3
V
100nF on VLCD, BIAS2 and BIAS1 pins
VLCD/3
1.
These values are based on simulation. These values are not covered by test limits in production or characterization
9.9.7.1
Liquid Crystal Controler supply current
The values in Table 9-52 are measured values of power consumption under the following condi-
tions, except where noted:
• T=25°C, WAIT mode, Low power waveform, Frame Rate = 32Hz from OSC32K
• Configuration: 4COMx40SEG, 1/4 Duty, 1/3 Bias, No animation
• All segments on, Load = 160 x 22pF between each COM and each SEG.
• LCDCA current based on ILCD = IWAIT(Lcd On) - IWAIT(Lcd Off)
Table 9-52. Liquid Crystal Display Controler supply current
Symbol
Conditions
Min
Typ
8.85
6.16
0.98
1.17
Max
Units
VVDDIN = 3.6V
VVDDIN = 1.8V
VVDDIN = 3.3V
VVDDIN = 1.8V
Internal voltage generation
CFG.FCST=0
ILCD
µA
External bias
VLCD=3.0V
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9.10 Timing Characteristics
9.10.1
RESET_N Timing
Table 9-53. RESET_N Waveform Parameters (1)
Symbol
Parameter
Conditions
Min
Max
Units
tRESET
RESET_N minimum pulse length
10
ns
1.
These values are based on simulation. These values are not covered by test limits in production.
9.10.2
USART in SPI Mode Timing
9.10.2.1
Master mode
Figure 9-7. USART in SPI Master Mode with (CPOL= CPHA= 0) or (CPOL= CPHA= 1)
SPCK
MISO
USPI0
USPI1
MOSI
USPI2
Figure 9-8. USART in SPI Master Mode with (CPOL= 0 and CPHA= 1) or (CPOL= 1 and
CPHA= 0)
SPCK
MISO
USPI3
USPI4
MOSI
USPI5
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Table 9-54. USART0 in SPI Mode Timing, Master Mode(1)
Symbol
USPI0
USPI1
USPI2
USPI3
USPI4
USPI5
Parameter
Conditions
Min
Max
Units
(2)
MISO setup time before SPCK rises
MISO hold time after SPCK rises
SPCK rising to MOSI delay
MISO setup time before SPCK falls
MISO hold time after SPCK falls
SPCK falling to MOSI delay
123.2 + tSAMPLE
(2)
VVDDIO from
24.74 -tSAMPLE
3.0V to 3.6V,
maximum
external
capacitor =
40pF
513.56
ns
(2)
125.99 + tSAMPLE
(2)
24.74 -tSAMPLE
516.55
Table 9-55. USART1 in SPI Mode Timing, Master Mode(1)
Symbol
USPI0
USPI1
USPI2
USPI3
USPI4
USPI5
Parameter
Conditions
Min
Max
Units
(2)
MISO setup time before SPCK rises
MISO hold time after SPCK rises
SPCK rising to MOSI delay
MISO setup time before SPCK falls
MISO hold time after SPCK falls
SPCK falling to MOSI delay
69.28 + tSAMPLE
(2)
VVDDIO from
25.75 -tSAMPLE
3.0V to 3.6V,
maximum
external
capacitor =
40pF
99.66
ns
(2)
73.12 + tSAMPLE
(2)
28.10 -tSAMPLE
102.01
Table 9-56. USART2 in SPI Mode Timing, Master Mode(1)
Symbol
USPI0
USPI1
USPI2
USPI3
USPI4
USPI5
Parameter
Conditions
Min
Max
Units
(2)
(2)
MISO setup time before SPCK rises
MISO hold time after SPCK rises
SPCK rising to MOSI delay
MISO setup time before SPCK falls
MISO hold time after SPCK falls
SPCK falling to MOSI delay
69.09 + tSAMPLE
(2)
VVDDIO from
26.52 -tSAMPLE
3.0V to 3.6V,
maximum
external
capacitor =
40pF
542.96
ns
72.55 + tSAMPLE
(2)
28.37 -tSAMPLE
544.80
Table 9-57. USART3 in SPI Mode Timing, Master Mode(1)
Symbol
USPI0
USPI1
USPI2
USPI3
USPI4
USPI5
Parameter
Conditions
Min
Max
Units
(2)
MISO setup time before SPCK rises
MISO hold time after SPCK rises
SPCK rising to MOSI delay
MISO setup time before SPCK falls
MISO hold time after SPCK falls
SPCK falling to MOSI delay
147.24 + tSAMPLE
(2)
VVDDIO from
25.80 -tSAMPLE
3.0V to 3.6V,
maximum
external
capacitor =
40pF
88.23
89.32
ns
(2)
(2)
154.9 + tSAMPLE
26.89 -tSAMPLE
Notes: 1. These values are based on simulation. These values are not covered by test limits in production.
tSPCK
1
⎛
⎞
2. Where: tSAMPLE = tSPCK
–
-- × tCLKUSART
------------------------------------
⎝
⎠
2
2 × tCLKUSART
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Maximum SPI Frequency, Master Output
The maximum SPI master output frequency is given by the following formula:
× 2
f
1
SPIn
CLKSPI
f
= MIN(f
,------------ , ----------------------------)
PINMAX
SPCKMAX
9
Where SPIn is the MOSI delay, USPI2 or USPI5 depending on CPOL and NCPHA. fPINMAX is
the maximum frequency of the SPI pins. refer to the I/O Pin Characteristics section for the maxi-
mum frequency of the pins. fCLKSPI is the maximum frequency of the CLK_SPI. Refer to the SPI
chapter for a description of this clock.
Maximum SPI Frequency, Master Input
The maximum SPI master input frequency is given by the following formula:
f
× 2
1
CLKSPI
f
= MIN(-----------------------------------,----------------------------)
SPCKMAX
SPIn + t
9
VALID
Where SPIn is the MISO setup and hold time, USPI0 + USPI1 or USPI3 + USPI4 depending on
CPOL and NCPHA.TVALID is the SPI slave response time. refer to the SPI slave datasheet for
TVALID .fCLKSPI is the maximum frequency of the CLK_SPI. Refer to the SPI chapter for a
description of this clock.
9.10.2.2
Slave mode
Figure 9-9. USART in SPI Slave Mode with (CPOL= 0 and CPHA= 1) or (CPOL= 1 and
CPHA= 0)
SPCK
MISO
USPI6
MOSI
USPI7
USPI8
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Figure 9-10. USART in SPI Slave Mode with (CPOL= CPHA= 0) or (CPOL= CPHA= 1)
SPCK
MISO
USPI9
MOSI
USPI10
USPI11
Figure 9-11. USART in SPI Slave Mode, NPCS Timing
USPI12
USPI13
USPI15
SPCK, CPOL=0
SPCK, CPOL=1
USPI14
NSS
Table 9-58. USART0 in SPI mode Timing, Slave Mode(1)
Symbol
Parameter
Conditions
Min
Max
Units
USPI6
SPCK falling to MISO delay
740.67
(2)
56.73 + tSAMPLE
tCLK_USART
+
+
USPI7
MOSI setup time before SPCK rises
(2)
45.18 -( tSAMPLE
tCLK_USART )
USPI8
USPI9
USPI10
MOSI hold time after SPCK rises
SPCK rising to MISO delay
V
VDDIO from
670.18
3.0V to 3.6V,
maximum
external
capacitor =
40pF
(2)
56.73 +( tSAMPLE
tCLK_USART )
+
+
MOSI setup time before SPCK falls
ns
(2)
45.18 -( tSAMPLE
tCLK_USART )
USPI11
MOSI hold time after SPCK falls
USPI12
USPI13
USPI14
USPI15
NSS setup time before SPCK rises
NSS hold time after SPCK falls
NSS setup time before SPCK falls
NSS hold time after SPCK rises
688.71
-2.25
688.71
-2.25
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Table 9-59. USART1 in SPI mode Timing, Slave Mode(1)
Symbol
Parameter
Conditions
Min
Max
Units
USPI6
SPCK falling to MISO delay
373.58
(2)
4.16 + tSAMPLE
tCLK_USART
+
USPI7
MOSI setup time before SPCK rises
(2)
46.69 -( tSAMPLE
tCLK_USART )
+
USPI8
USPI9
USPI10
MOSI hold time after SPCK rises
SPCK rising to MISO delay
V
VDDIO from
373.54
3.0V to 3.6V,
maximum
external
(2)
4.16 +( tSAMPLE
tCLK_USART )
+
MOSI setup time before SPCK falls
ns
(2)
capacitor =
40pF
46.69 -( tSAMPLE
tCLK_USART )
+
USPI11
MOSI hold time after SPCK falls
USPI12
USPI13
USPI14
USPI15
NSS setup time before SPCK rises
NSS hold time after SPCK falls
NSS setup time before SPCK falls
NSS hold time after SPCK rises
200.43
-16.5
200.43
-16.5
Table 9-60. USART2 in SPI mode Timing, Slave Mode(1)
Symbol
Parameter
Conditions
Min
Max
Units
USPI6
SPCK falling to MISO delay
770.02
(2)
136.56 + tSAMPLE
tCLK_USART
+
+
USPI7
MOSI setup time before SPCK rises
(2)
47.9 -( tSAMPLE
tCLK_USART )
+
USPI8
USPI9
USPI10
MOSI hold time after SPCK rises
SPCK rising to MISO delay
V
VDDIO from
570.19
3.0V to 3.6V,
maximum
external
(2)
136.73 +( tSAMPLE
tCLK_USART )
MOSI setup time before SPCK falls
ns
(2)
capacitor =
40pF
47.9 -( tSAMPLE
tCLK_USART )
+
USPI11
MOSI hold time after SPCK falls
USPI12
USPI13
USPI14
USPI15
NSS setup time before SPCK rises
NSS hold time after SPCK falls
NSS setup time before SPCK falls
NSS hold time after SPCK rises
519.87
-1.83
519.87
-1.83
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Table 9-61. USART3 in SPI mode Timing, Slave Mode(1)
Symbol
Parameter
Conditions
Min
Max
Units
USPI6
SPCK falling to MISO delay
593.9
(2)
(2)
45.93 + tSAMPLE
tCLK_USART
+
+
USPI7
MOSI setup time before SPCK rises
47.03 -( tSAMPLE
tCLK_USART )
USPI8
USPI9
USPI10
MOSI hold time after SPCK rises
SPCK rising to MISO delay
V
VDDIO from
593.38
3.0V to 3.6V,
maximum
external
capacitor =
40pF
(2)
45.93 +( tSAMPLE
tCLK_USART )
+
+
MOSI setup time before SPCK falls
ns
(2)
47.03 -( tSAMPLE
tCLK_USART )
USPI11
MOSI hold time after SPCK falls
USPI12
USPI13
USPI14
USPI15
NSS setup time before SPCK rises
NSS hold time after SPCK falls
NSS setup time before SPCK falls
NSS hold time after SPCK rises
237.5
-1.81
237.5
-1.81
Notes: 1. These values are based on simulation. These values are not covered by test limits in production.
tSPCK
1
⎛
⎞
2. Where: tSAMPLE = tSPCK
–
+ -- × tCLKUSART
------------------------------------
⎝
⎠
2
2 × tCLKUSART
Maximum SPI Frequency, Slave Input Mode
The maximum SPI slave input frequency is given by the following formula:
f
× 2
1
SPIn
CLKSPI
f
= MIN(----------------------------,------------ )
SPCKMAX
9
Where SPIn is the MOSI setup and hold time, USPI7 + USPI8 or USPI10 + USPI11 depending
on CPOL and NCPHA. fCLKSPI is the maximum frequency of the CLK_SPI. Refer to the SPI
chapter for a description of this clock.
Maximum SPI Frequency, Slave Output Mode
The maximum SPI slave output frequency is given by the following formula:
f
× 2
1
CLKSPI
f
= MIN(----------------------------, f
,------------------------------------ )
SPCKMAX
PINMAX
9
SPIn + t
SETUP
Where SPIn is the MISO delay, USPI6 or USPI9 depending on CPOL and NCPHA. TSETUP is
the SPI master setup time. refer to the SPI master datasheet for TSETUP . fCLKSPI is the maxi-
mum frequency of the CLK_SPI. Refer to the SPI chapter for a description of this clock.fPINMAX
is the maximum frequency of the SPI pins. refer to the I/O Pin Characteristics section for the
maximum frequency of the pins.
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9.10.3
SPI Timing
9.10.3.1
Master mode
Figure 9-12. SPI Master Mode with (CPOL= NCPHA= 0) or (CPOL= NCPHA= 1)
SPCK
MISO
SPI0
SPI1
MOSI
SPI2
Figure 9-13. SPI Master Mode with (CPOL= 0 and NCPHA= 1) or (CPOL= 1 and NCPHA= 0)
SPCK
MISO
SPI3
SPI4
MOSI
SPI5
Table 9-62. SPI Timing, Master Mode(1)
Symbol
SPI0
SPI1
SPI2
SPI3
SPI4
SPI5
Parameter
Conditions
Min
9
Max
21
Units
MISO setup time before SPCK rises
MISO hold time after SPCK rises
SPCK rising to MOSI delay
VVDDIO from
0
2.85V to 3.6V,
maximum
external
capacitor =
40pF
9
ns
MISO setup time before SPCK falls
MISO hold time after SPCK falls
SPCK falling to MOSI delay
7.3
0
9
22
Note:
1. These values are based on simulation. These values are not covered by test limits in production.
Maximum SPI Frequency, Master Output
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The maximum SPI master output frequency is given by the following formula:
1
f
= MIN(f
,------------ )
SPIn
SPCKMAX
PINMAX
Where SPIn is the MOSI delay, SPI2 or SPI5 depending on CPOL and NCPHA. fPINMAX is the
maximum frequency of the SPI pins. refer to the I/O Pin Characteristics section for the maximum
frequency of the pins.
Maximum SPI Frequency, Master Input
The maximum SPI master input frequency is given by the following formula:
1
f
= -----------------------------------
SPCKMAX
SPIn + t
VALID
Where SPIn is the MISO setup and hold time, SPI0 + SPI1 or SPI3 + SPI4 depending on
CPOL and NCPHA. tVALID is the SPI slave response time. refer to the SPI slave datasheet for
tVALID
.
9.10.3.2
Slave mode
Figure 9-14. SPI Slave Mode with (CPOL= 0 and NCPHA= 1) or (CPOL= 1 and NCPHA= 0)
SPCK
MISO
SPI6
MOSI
SPI7
SPI8
Figure 9-15. SPI Slave Mode with (CPOL= NCPHA= 0) or (CPOL= NCPHA= 1)
SPCK
MISO
SPI9
MOSI
SPI10
SPI11
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Figure 9-16. SPI Slave Mode, NPCS Timing
SPI12
SPI13
SPI15
SPCK, CPOL=0
SPCK, CPOL=1
SPI14
NPCS
Table 9-63. SPI Timing, Slave Mode(1)
Symbol
SPI6
Parameter
Conditions
Min
19
0
Max
Units
SPCK falling to MISO delay
47
SPI7
MOSI setup time before SPCK rises
MOSI hold time after SPCK rises
SPCK rising to MISO delay
SPI8
5.4
19
0
VVDDIO from
SPI9
46
2.85V to 3.6V,
maximum
external
capacitor =
40pF
SPI10
SPI11
SPI12
SPI13
SPI14
SPI15
MOSI setup time before SPCK falls
MOSI hold time after SPCK falls
NPCS setup time before SPCK rises
NPCS hold time after SPCK falls
NPCS setup time before SPCK falls
NPCS hold time after SPCK rises
ns
5.3
4
2.5
6
1.1
Note:
1. These values are based on simulation. These values are not covered by test limits in production.
Maximum SPI Frequency, Slave Input Mode
The maximum SPI slave input frequency is given by the following formula:
1
SPIn
f
= MIN(f
,------------ )
CLKSPI
SPCKMAX
Where SPIn is the MOSI setup and hold time, SPI7 + SPI8 or SPI10 + SPI11 depending on
CPOL and NCPHA. fCLKSPI is the maximum frequency of the CLK_SPI. Refer to the SPI chap-
ter for a description of this clock.
Maximum SPI Frequency, Slave Output Mode
The maximum SPI slave output frequency is given by the following formula:
1
f
= MIN(f
,------------------------------------ )
PINMAX
SPCKMAX
SPIn + t
SETUP
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Where SPIn is the MISO delay, SPI6 or SPI9 depending on CPOL and NCPHA. tSETUP is the
SPI master setup time. refer to the SPI master datasheet for tSETUP .fPINMAX is the maximum
frequency of the SPI pins. refer to the I/O Pin Characteristics section for the maximum frequency
of the pins.
9.10.4
TWIM/TWIS Timing
Figure 9-64 shows the TWI-bus timing requirements and the compliance of the device with
them. Some of these requirements (tr and tf) are met by the device without requiring user inter-
vention. Compliance with the other requirements (tHD-STA, tSU-STA, tSU-STO, tHD-DAT, tSU-DAT-TWI
,
tLOW-TWI, tHIGH, and fTWCK) requires user intervention through appropriate programming of the rel-
evant TWIM and TWIS user interface registers. refer to the TWIM and TWIS sections for more
information.
Table 9-64. TWI-Bus Timing Requirements
Minimum
Requirement
Maximum
Requirement
Symbol
tr
Parameter
Mode
Standard(1)
Fast(1)
Standard
Fast
Device
Device
Unit
-
1000
300
300
300
TWCK and TWD rise time
ns
20 + 0.1Cb
-
tf
TWCK and TWD fall time
(Repeated) START hold time
(Repeated) START set-up time
STOP set-up time
ns
μs
μs
μs
20 + 0.1Cb
Standard
Fast
4
tHD-STA
tSU-STA
tSU-STO
tHD-DAT
tclkpb
-
-
-
0.6
4.7
0.6
4.0
0.6
Standard
Fast
tclkpb
Standard
Fast
4tclkpb
Standard
Fast
3.45()
0.9()
Data hold time
0.3(2)
2tclkpb
15tprescaled + tclkpb μs
Standard
Fast
250
100
-
tSU-DAT-TWI Data set-up time
tSU-DAT
tLOW-TWI
tLOW
2tclkpb
tclkpb
4tclkpb
tclkpb
-
-
-
-
-
ns
-
-
Standard
Fast
4.7
1.3
-
TWCK LOW period
μs
-
-
Standard
Fast
4.0
0.6
tHIGH
TWCK HIGH period
TWCK frequency
8tclkpb
μs
Standard
Fast
100
400
1
fTWCK
-
-----------------------
kHz
12t
clkpb
Notes: 1. Standard mode: fTWCK ≤ 100 kHz ; fast mode: fTWCK > 100 kHz .
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2. A device must internally provide a hold time of at least 300 ns for TWD with reference to the falling edge of TWCK.
Notations:
Cb = total capacitance of one bus line in pF
tclkpb = period of TWI peripheral bus clock
tprescaled = period of TWI internal prescaled clock (see chapters on TWIM and TWIS)
The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW-TWI
of TWCK.
)
9.10.5
JTAG Timing
Figure 9-17. JTAG Interface Signals
JTAG2
TCK
JTAG0
JTAG1
TMS/TDI
TDO
JTAG3
JTAG4
JTAG5
JTAG6
Boundary
Scan Inputs
JTAG7
JTAG8
Boundary
Scan Outputs
JTAG9
JTAG10
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Table 9-65. JTAG Timings(1)
Symbol
JTAG0
JTAG1
JTAG2
JTAG3
JTAG4
JTAG5
JTAG6
JTAG7
JTAG8
JTAG9
JTAG10
Parameter
Conditions
Min
21.8
8.6
Max
Units
TCK Low Half-period
TCK High Half-period
TCK Period
30.3
2.0
TDI, TMS Setup before TCK High
TDI, TMS Hold after TCK High
TDO Hold Time
VVDDIO from
2.3
3.0V to 3.6V,
maximum
external
capacitor =
40pF
9.5
ns
TCK Low to TDO Valid
21.8
32.2
Boundary Scan Inputs Setup Time
Boundary Scan Inputs Hold Time
Boundary Scan Outputs Hold Time
TCK to Boundary Scan Outputs Valid
0.6
6.9
9.3
Note:
1. These values are based on simulation. These values are not covered by test limits in production.
9.10.6
SWD Timing
Figure 9-18. SWD Interface Signals
Read Cycle
From debugger to
SWDIO pin
Stop
Park
Tri State
Data
Data
Parity
Start
Thigh
Tos
Tlow
From debugger to
SWDCLK pin
SWDIO pin to
debugger
Tri State
Acknowledge
Tri State
Write Cycle
From debugger to
SWDIO pin
Stop
Park
Tri State
Start
Tis
Tih
From debugger to
SWDCLK pin
SWDIO pin to
debugger
Tri State
Acknowledge
Data
Data
Parity
Tri State
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Table 9-66. SWD Timings(1)
Symbol
Thigh
Tlow
Tos
Parameter
Conditions
Min
10
10
-5
Max
Units
SWDCLK High period
500 000
VVDDIO from
3.0V to 3.6V,
maximum
external
capacitor =
40pF
SWDCLK Low period
500 000
SWDIO output skew to falling edge SWDCLK
Input Setup time required between SWDIO
5
-
ns
Tis
4
Input Hold time required between SWDIO and
rising edge SWDCLK
Tih
1
-
Note:
1. These values are based on simulation. These values are not covered by test limits in production or characterization.
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10. Mechanical Characteristics
10.1 Thermal Considerations
10.1.1
Thermal Data
Table 10-1 summarizes the thermal resistance data depending on the package.
Table 10-1. Thermal Resistance Data
Symbol
θJA
Parameter
Condition
Package
TQFP100
TQFP100
VFBGA100
VFBGA100
WLCSP64
WLCSP64
TQFP64
TQFP64
QFN64
Typ
48.1
13.3
31.1
6.9
Unit
Junction-to-ambient thermal resistance Still Air
Junction-to-case thermal resistance
⋅C/W
θJC
θJA
Junction-to-ambient thermal resistance Still Air
Junction-to-case thermal resistance
⋅C/W
⋅C/W
⋅C/W
⋅C/W
⋅C/W
⋅C/W
θJC
θJA
Junction-to-ambient thermal resistance Still Air
Junction-to-case thermal resistance
26.9
0.2
θJC
θJA
Junction-to-ambient thermal resistance Still Air
Junction-to-case thermal resistance
49.6
13.5
22.0
1.3
θJC
θJA
Junction-to-ambient thermal resistance Still Air
Junction-to-case thermal resistance
θJC
θJA
QFN64
Junction-to-ambient thermal resistance Still Air
Junction-to-case thermal resistance
TQFP48
TQFP48
QFN48
51.1
13.7
24.9
1.3
θJC
θJA
Junction-to-ambient thermal resistance Still Air
Junction-to-case thermal resistance
θJC
QFN48
10.1.2
Junction Temperature
The average chip-junction temperature, TJ, in °C can be obtained from the following:
1. T = T + (P × θ
)
JA
J
A
D
2. TJ = TA + (PD × (θHEATSINK + θJC ))
where:
• θJA = package thermal resistance, Junction-to-ambient (°C/W), provided in Table 10-1.
• θJC = package thermal resistance, Junction-to-case thermal resistance (°C/W), provided in
Table 10-1.
• θHEAT SINK = cooling device thermal resistance (°C/W), provided in the device datasheet.
• PD = device power consumption (W) estimated from data provided in Section 9.5 on page 103.
• TA = ambient temperature (°C).
From the first equation, the user can derive the estimated lifetime of the chip and decide if a
cooling device is necessary or not. If a cooling device is to be fitted on the chip, the second
equation should be used to compute the resulting average chip-junction temperature TJ in °C.
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10.2 Package Drawings
Figure 10-1. VFBGA-100 package drawing
Table 10-2. Device and Package Maximum Weight
120
mg
Table 10-3. Package Characteristics
Moisture Sensitivity Level
MSL3
Table 10-4. Package Reference
JEDEC Drawing Reference
JESD97 Classification
N/A
E1
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Figure 10-2. TQFP-100 Package Drawing
Table 10-5. Device and Package Maximum Weight
500
mg
Table 10-6. Package Characteristics
Moisture Sensitivity Level
MSL3
Table 10-7. Package Reference
JEDEC Drawing Reference
JESD97 Classification
MS-026
E3
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Figure 10-3. WLCSP64 SAM4LC4/2 Package Drawing
Table 10-8. Device and Package Maximum Weight
14.8
mg
Table 10-9. Package Characteristics
Moisture Sensitivity Level
MSL3
Table 10-10. Package Reference
JEDEC Drawing Reference
JESD97 Classification
MS-026
E1
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Figure 10-4. WLCSP64 SAM4LS4/2 Package Drawing
Table 10-11. Device and Package Maximum Weight
14.8
mg
Table 10-12. Package Characteristics
Moisture Sensitivity Level
MSL3
Table 10-13. Package Reference
JEDEC Drawing Reference
JESD97 Classification
MS-026
E1
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Figure 10-5. WLCSP64 SAM4LC8 Package Drawing
Table 10-14. Device and Package Maximum Weight
14.8
mg
Table 10-15. Package Characteristics
Moisture Sensitivity Level
MSL3
Table 10-16. Package Reference
JEDEC Drawing Reference
JESD97 Classification
MS-026
E1
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Figure 10-6. WLCSP64 SAM4LS8 Package Drawing
Table 10-17. Device and Package Maximum Weight
14.8
mg
Table 10-18. Package Characteristics
Moisture Sensitivity Level
MSL3
Table 10-19. Package Reference
JEDEC Drawing Reference
JESD97 Classification
MS-026
E1
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Figure 10-7. TQFP-64 Package Drawing
Table 10-20. Device and Package Maximum Weight
300
mg
Table 10-21. Package Characteristics
Moisture Sensitivity Level
MSL3
Table 10-22. Package Reference
JEDEC Drawing Reference
JESD97 Classification
MS-026
E3
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Figure 10-8. QFN-64 Package Drawing
Note:
The exposed pad is not connected to anything internally, but should be soldered to ground to increase board level reliability.
Table 10-23. Device and Package Maximum Weight
200
mg
Table 10-24. Package Characteristics
Moisture Sensitivity Level
MSL3
Table 10-25. Package Reference
JEDEC Drawing Reference
JESD97 Classification
MO-220
E3
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Figure 10-9. TQFP-48 (ATSAM4LC4/2 and ATSAM4LS4/2 Only) Package Drawing
Table 10-26. Device and Package Maximum Weight
140
mg
Table 10-27. Package Characteristics
Moisture Sensitivity Level
MSL3
Table 10-28. Package Reference
JEDEC Drawing Reference
JESD97 Classification
MS-026
E3
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Figure 10-10. QFN-48 Package Drawing for ATSAM4LC4/2 and ATSAM4LS4/2
Note:
The exposed pad is not connected to anything internally, but should be soldered to ground to increase board level reliability.
Table 10-29. Device and Package Maximum Weight
140
mg
Table 10-30. Package Characteristics
Moisture Sensitivity Level
MSL3
Table 10-31. Package Reference
JEDEC Drawing Reference
JESD97 Classification
MO-220
E3
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Figure 10-11. QFN-48 Package Drawing for ATSAM4LC8 and ATSAM4LS8
Note:
The exposed pad is not connected to anything internally, but should be soldered to ground to increase board level reliability.
Table 10-32. Device and Package Maximum Weight
140
mg
Table 10-33. Package Characteristics
Moisture Sensitivity Level
MSL3
Table 10-34. Package Reference
JEDEC Drawing Reference
JESD97 Classification
MO-220
E3
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10.3 Soldering Profile
Table 10-35 gives the recommended soldering profile from J-STD-20.
Table 10-35. Soldering Profile
Profile Feature
Green Package
3°C/s max
150-200°C
60-150 s
Average Ramp-up Rate (217°C to Peak)
Preheat Temperature 175°C ±25°C
Time Maintained Above 217°C
Time within 5⋅C of Actual Peak Temperature
Peak Temperature Range
30 s
260°C
Ramp-down Rate
6°C/s max
8 minutes max
Time 25⋅C to Peak Temperature
A maximum of three reflow passes is allowed per component.
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11. Ordering Information
Table 11-1. ATSAM4LC8 Sub Serie Ordering Information
Flash
RAM
Package
Type
Temperature Operating
Range
Ordering Code
(Kbytes)
(Kbytes)
Package
Conditioning
Tray
ATSAM4LC8CA-AU
ATSAM4LC8CA-AUR
ATSAM4LC8CA-CFU
ATSAM4LC8CA-CFUR
ATSAM4LC8BA-AU
ATSAM4LC8BA-AUR
ATSAM4LC8BA-MU
ATSAM4LC8BA-MUR
ATSAM4LC8BA-UUR
ATSAM4LC8AA-MU
ATSAM4LC8AA-MUR
TQFP100
Reel
Tray
VFBGA100
TQFP64
Reel
Tray
512
64
Reel
Green
Industrial -40°C to 85°C
Tray
QFN64
WLCSP64
QFN48
Reel
Reel
Tray
Reel
Table 11-2. ATSAM4LC4 Sub Serie Ordering Information
Flash
RAM
Package
Type
Temperature Operating
Range
Ordering Code
(Kbytes)
(Kbytes)
Package
Conditioning
ES
ATSAM4LC4CA-AU-ES
ATSAM4LC4CA-AU
ATSAM4LC4CA-AUR
ATSAM4LC4CA-CFU
ATSAM4LC4CA-CFUR
ATSAM4LC4BA-AU-ES
ATSAM4LC4BA-AU
ATSAM4LC4BA-AUR
ATSAM4LC4BA-MU-ES
ATSAM4LC4BA-MU
ATSAM4LC4BA-MUR
ATSAM4LC4BA-UUR
ATSAM4LC4AA-AU-ES
ATSAM4LC4AA-AU
ATSAM4LC4AA-AUR
ATSAM4LC4AA-MU-ES
ATSAM4LC4AA-MU
ATSAM4LC4AA-MUR
N/A
TQFP100
Tray
Reel
Tray
Reel
ES
Industrial -40°C to 85°C
VFBGA100
TQFP64
Industrial -40°C to 85°C
N/A
Tray
Reel
ES
Industrial -40°C to 85°C
N/A
256
32
Green
QFN64
WLCSP64
TQFP48
Tray
Reel
Reel
ES
Industrial -40°C to 85°C
Industrial -40°C to 85°C
N/A
Tray
Reel
ES
Industrial -40°C to 85°C
N/A
QFN48
Tray
Reel
Industrial -40°C to 85°C
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Table 11-3. ATSAM4LC2 Sub Serie Ordering Information
Flash
RAM
Package
Type
Temperature Operating
Range
Ordering Code
(Kbytes)
(Kbytes)
Package
Conditioning
Tray
ATSAM4LC2CA-AU
ATSAM4LC2CA-AUR
ATSAM4LC2CA-CFU
ATSAM4LC2CA-CFUR
ATSAM4LC2BA-AU
ATSAM4LC2BA-AUR
ATSAM4LC2BA-MU
ATSAM4LC2BA-MUR
ATSAM4LC2BA-UUR
ATSAM4LC2AA-AU
ATSAM4LC2AA-AUR
ATSAM4LC2AA-MU
ATSAM4LC2AA-MUR
TQFP100
Reel
Tray
VFBGA100
TQFP64
Reel
Tray
Reel
128
32
Tray
Green
Industrial -40°C to 85°C
QFN64
WLCSP64
TQFP48
Reel
Reel
Tray
Reel
Tray
QFN48
Reel
Table 11-4. ATSAM4LS8 Sub Serie Ordering Information
Flash
RAM
Package
Type
Temperature Operating
Range
Ordering Code
(Kbytes)
(Kbytes)
Package
Conditioning
Tray
ATSAM4LS8CA-AU
ATSAM4LS8CA-AUR
ATSAM4LS8CA-CFU
ATSAM4LS8CA-CFUR
ATSAM4LS8BA-AU
ATSAM4LS8BA-AUR
ATSAM4LS8BA-MU
ATSAM4LS8BA-MUR
ATSAM4LS8BA-UUR
ATSAM4LS8AA-MU
ATSAM4LS8AA-MUR
TQFP100
Reel
Tray
VFBGA100
TQFP64
Reel
Tray
512
64
Reel
Green
Industrial -40°C to 85°C
Tray
QFN64
WLCSP64
QFN48
Reel
Reel
Tray
Reel
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Table 11-5. ATSAM4LS4 Sub Serie Ordering Information
Flash
RAM
Package
Type
Temperature Operating
Range
Ordering Code
(Kbytes)
(Kbytes)
Package
Conditioning
ES
ATSAM4LS4CA-AU-ES
ATSAM4LS4CA-AU
ATSAM4LS4CA-AUR
ATSAM4LS4CA-CFU
ATSAM4LS4CA-CFUR
ATSAM4LS4BA-AU-ES
ATSAM4LS4BA-AU
ATSAM4LS4BA-AUR
ATSAM4LS4BA-MU-ES
ATSAM4LS4BA-MU
ATSAM4LS4BA-MUR
ATSAM4LS4BA-UUR
ATSAM4LS4AA-AU-ES
ATSAM4LS4AA-AU
ATSAM4LS4AA-AUR
ATSAM4LS4AA-MU-ES
ATSAM4LS4AA-MU
ATSAM4LS4AA-MUR
N/A
TQFP100
Tray
Reel
Tray
Reel
ES
Industrial -40°C to 85°C
VFBGA100
TQFP64
Industrial -40°C to 85°C
N/A
Tray
Reel
ES
Industrial -40°C to 85°C
N/A
256
32
Green
QFN64
WLCSP64
TQFP48
Tray
Reel
Reel
ES
Industrial -40°C to 85°C
Industrial -40°C to 85°C
N/A
Tray
Reel
ES
Industrial -40°C to 85°C
N/A
QFN48
Tray
Reel
Industrial -40°C to 85°C
Table 11-6. ATSAM4LS2 Sub Serie Ordering Information
Flash
RAM
Package
Type
Temperature Operating
Range
Ordering Code
(Kbytes)
(Kbytes)
Package
Conditioning
Tray
ATSAM4LS2CA-AU
ATSAM4LS2CA-AUR
ATSAM4LS2CA-CFU
ATSAM4LS2CA-CFUR
ATSAM4LS2BA-AU
ATSAM4LS2BA-AUR
ATSAM4LS2BA-MU
ATSAM4LS2BA-MUR
ATSAM4LS2BA-UUR
ATSAM4LS2AA-AU
ATSAM4LS2AA-AUR
ATSAM4LS2AA-MU
ATSAM4LS2AA-MUR
TQFP100
Reel
Tray
VFBGA100
TQFP64
Reel
Tray
Reel
128
32
Tray
Green
Industrial -40°C to 85°C
QFN64
WLCSP64
TQFP48
Reel
Reel
Tray
Reel
Tray
QFN48
Reel
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12. Errata
12.1 ATSAM4L4 /2 Rev. B & ATSAM4L8 Rev. A
12.1.1
General
PS2 mode is not supported by Engineering Samples
PS2 mode support is supported only by parts with calibration version higher than 0.
Fix/Workaround
The calibration version can be checked by reading a 32-bit word at address 0x0080020C.
The calibration version bitfield is 4-bit wide and located from bit 4 to bit 7 in this word. Any
value higher than 0 ensures that the part supports the PS2 mode
12.1.2
SCIF
PLLCOUNT value larger than zero can cause PLLEN glitch
Initializing the PLLCOUNT with a value greater than zero creates a glitch on the PLLEN sig-
nal during asynchronous wake up.
Fix/Workaround
The lock-masking mechanism for the PLL should not be used.
The PLLCOUNT field of the PLL Control Register should always be written to zero.
12.1.3
WDT
WDT Control Register does not have synchronization feedback
When writing to the Timeout Prescale Select (PSEL), Time Ban Prescale Select (TBAN),
Enable (EN), or WDT Mode (MODE) fieldss of the WDT Control Register (CTRL), a synchro-
nizer is started to propagate the values to the WDT clcok domain. This synchronization
takes a finite amount of time, but only the status of the synchronization of the EN bit is
reflected back to the user. Writing to the synchronized fields during synchronization can lead
to undefined behavior.
Fix/Workaround
-When writing to the affected fields, the user must ensure a wait corresponding to 2 clock
cycles of both the WDT peripheral bus clock and the selected WDT clock source.
-When doing writes that changes the EN bit, the EN bit can be read back until it reflects the
written value.
12.1.4
SPI
SPI data transfer hangs with CSR0.CSAAT==1 and MR.MODFDIS==0
When CSR0.CSAAT==1 and mode fault detection is enabled (MR.MODFDIS==0), the SPI
module will not start a data transfer.
Fix/Workaround
Disable mode fault detection by writing a one to MR.MODFDIS.
SPI disable does not work in SLAVE mode
SPI disable does not work in SLAVE mode.
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Fix/Workaround
Read the last received data, then perform a software reset by writing a one to the Software
Reset bit in the Control Register (CR.SWRST).
Disabling SPI has no effect on the SR.TDRE bit
Disabling SPI has no effect on the SR.TDRE bit whereas the write data command is filtered
when SPI is disabled. Writing to TDR when SPI is disabled will not clear SR.TDRE. If SPI is
disabled during a PDCA transfer, the PDCA will continue to write data to TDR until its buffer
is empty, and this data will be lost.
Fix/Workaround
Disable the PDCA, add two NOPs, and disable the SPI. To continue the transfer, enable the
SPI and PDCA.
SPI bad serial clock generation on 2nd chip_select when SCBR=1, CPOL=1, and
NCPHA=0
When multiple chip selects (CS) are in use, if one of the baudrates equal 1 while one
(CSRn.SCBR=1) of the others do not equal 1, and CSRn.CPOL=1 and CSRn.NCPHA=0,
then an additional pulse will be generated on SCK.
Fix/Workaround
When multiple CS are in use, if one of the baudrates equals 1, the others must also equal 1
if CSRn.CPOL=1 and CSRn.NCPHA=0.
12.1.5
TC
Channel chaining skips first pulse for upper channel
When chaining two channels using the Block Mode Register, the first pulse of the clock
between the channels is skipped.
Fix/Workaround
Configure the lower channel with RA = 0x1 and RC = 0x2 to produce a dummy clock cycle
for the upper channel. After the dummy cycle has been generated, indicated by the
SR.CPCS bit, reconfigure the RA and RC registers for the lower channel with the real
values.
12.1.6
USBC
In USB host mode, entering suspend mode for low speed device can fail when the
USB freeze (USBCON.FRZCLK=1) is done just after UHCON.SOFE=0.
Fix/Workaround
When entering suspend mode (UHCON.SOFE is cleared), check that USBFSM.DRDSTATE
is not equal to three before freezing the clock (USBCON.FRZCLK=1).
In USB host mode, the asynchronous attach detection (UDINT.HWUPI) can fail when
the USB clock freeze (USBCON.FRZCLK=1) is done just after setting the USB-
STA.VBUSRQ bit.
Fix/Workaround
After setting USBSTA.VBUSRQ bit, wait until the USBFSM register value is
‘A_WAIT_BCON’ before setting the USBCON.FRZCLK bit.
170
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12.1.7
FLASHCALW
Corrupted data in flash may happen after flash page write operations.
After a flash page write operation, reading (data read or code fetch) in flash may fail. This
may lead to an expecption or to others errors derived from this corrupted read access.
Fix/Workaround
Before any flash page write operation, each 64-bit doublewords write in the page buffer must
preceded by a 64-bit doublewords write in the page buffer with 0xFFFFFFFF_FFFFFFFF
content at any address in the page. Note that special care is required when loading page
buffer, refer to Section 2.5.9 ”Page Buffer Operations” on page 11.
171
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13. Datasheet Revision History
Note that the referring page numbers in this section are referred to this document. The referring
revision in this section are referring to the document revision.
13.1 Rev. A – 09/12
13.2 Rev. B – 10/12
1.
Initial revision.
1.
2.
Fixed ordering code
Changed BOD18CTRL and BOD33CTRL ACTION field from “Reserved” to ‘No action”
13.3 Rev. C – 02/13
1.
2.
3.
4.
5.
6.
7.
Fixed ball pitch for VFBGA100 package
Added VFBGA100 and WLCSP64 pinouts
Added Power Scaling Mode 2 for high frequency support
Minor update on several modules chapters
Major update on Electrical characteristics
Updated errata
Fixed GPIO multiplexing pin numbers
13.4 Rev. D – 03/13
1.
2.
3.
4.
5.
6.
Removed WLCSP package information
Added errata text for detecting whether a part supports PS2 mode or not
Removed temperature sensor feature (not supported by production flow)
Fixed MUX selection on Positive ADC input channel table
Added information about TWI instances capabilities
Added some details on errata Corrupted data in flash may happen after flash page write
operations.171
172
42023HS–SAM–11/2016
ATSAM4L8/L4/L2
13.5 Rev. E – 07/13
1.
2.
3.
4.
5.
6.
7.
8.
9.
Added ATSAM4L8 derivatives and WLCSP packages for ATSAM4L4/2
Added operating conditions details in Electrical Characteristics Chapter
Fixed “Supply Rise Rates and Order”
Added number of USART available in sub-series
Fixed IO line considerations for USB pins
Removed useless information about CPU local bus which is not implemented
Removed useless information about Modem support which is not implemented
Added information about unsupported features in Power Scaling mode 1
Fixed SPI timings
13.6 Rev. F– 12/13
1.
2.
Fixed table 3-6 - TDI is connected to pin G3 in WLCSP package
Changed table 42-48 -ADCIFE Electricals in unipolar mode : PSRR & DC supply current
typical values
3.
4.
Fixed SPI timing characteristics
Fixed BOD33 typical step size value
13.7 Rev. G– 03/14
1.
2.
3.
Added WLCSP64 packages for SAM4LC8 and SAM4LS8 sub-series
Removed unsuppported SWAP feature in LCD module
Added mnimal value for ADC Reference range
13.8 Rev. H– 11/16
1.
Fixed AESA configuration in Overview chapter for SAM4LS sub-series
173
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ATSAM4L8/L4/L2
Table of Contents
Summary.................................................................................................... 1
Features..................................................................................................... 1
Description ............................................................................................... 3
Overview ................................................................................................... 5
1
2
2.1
2.2
Block Diagram ...................................................................................................5
Configuration Summary .....................................................................................6
3
4
Package and Pinout ................................................................................. 9
3.1
3.2
3.3
3.4
Package .............................................................................................................9
Peripheral Multiplexing on I/O lines .................................................................19
Signals Description ..........................................................................................31
I/O Line Considerations ...................................................................................34
Cortex-M4 processor and core peripherals ......................................... 36
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
Cortex-M4 ........................................................................................................36
System level interface .....................................................................................37
Integrated configurable debug .........................................................................37
Cortex-M4 processor features and benefits summary .....................................38
Cortex-M4 core peripherals .............................................................................38
Cortex-M4 implementations options ................................................................39
Cortex-M4 Interrupts map ................................................................................39
Peripheral Debug .............................................................................................42
5
6
Memories ................................................................................................ 43
5.1
5.2
5.3
Product Mapping .............................................................................................43
Embedded Memories ......................................................................................44
Physical Memory Map .....................................................................................44
Power and Startup Considerations ...................................................... 46
6.1
6.2
6.3
6.4
Power Domain Overview .................................................................................46
Power Supplies ................................................................................................48
Startup Considerations ....................................................................................53
Power-on-Reset, Brownout and Supply Monitor .............................................53
7
Low Power Techniques ......................................................................... 55
7.1
7.2
Power Save Modes .........................................................................................55
Power Scaling ..................................................................................................60
174
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ATSAM4L8/L4/L2
8
Debug and Test ...................................................................................... 62
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
8.11
Features ..........................................................................................................62
Overview ..........................................................................................................62
Block diagram ..................................................................................................63
I/O Lines Description .......................................................................................63
Product dependencies .....................................................................................64
Core debug ......................................................................................................64
Enhanced Debug Port (EDP) ..........................................................................67
AHB-AP Access Port .......................................................................................77
System Manager Access Port (SMAP) ............................................................78
Available Features in Protected State .............................................................93
Functional Description .....................................................................................94
9
Electrical Characteristics ...................................................................... 99
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
Absolute Maximum Ratings* ...........................................................................99
Operating Conditions .......................................................................................99
Supply Characteristics .....................................................................................99
Maximum Clock Frequencies ........................................................................101
Power Consumption ......................................................................................103
I/O Pin Characteristics ...................................................................................114
Oscillator Characteristics ...............................................................................121
Flash Characteristics .....................................................................................127
Analog Characteristics ...................................................................................129
Timing Characteristics ...................................................................................140
10 Mechanical Characteristics ................................................................. 153
10.1
10.2
10.3
Thermal Considerations ................................................................................153
Package Drawings .........................................................................................154
Soldering Profile ............................................................................................165
11 Ordering Information ........................................................................... 166
12 Errata ..................................................................................................... 169
12.1
ATSAM4L4 /2 Rev. B & ATSAM4L8 Rev. A ..................................................169
13 Datasheet Revision History ................................................................ 172
13.1
13.2
13.3
Rev. A – 09/12 ...............................................................................................172
Rev. B – 10/12 ...............................................................................................172
Rev. C – 02/13 ...............................................................................................172
175
42023HS–SAM–11/2016
13.4
13.5
13.6
13.7
13.8
Rev. D – 03/13 ...............................................................................................172
Rev. E – 07/13 ...............................................................................................173
Rev. F– 12/13 ................................................................................................173
Rev. G– 03/14 ...............................................................................................173
Rev. H– 11/16 ................................................................................................173
Table of Contents.................................................................................. 174
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42023HS–SAM–11/2016
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