ATSAM3S8BA-MU_技术文档

Features

• Core

– ARM^®Cortex^®-M3 revision 2.0 running at up to 64 MHz

– Memory Protection Unit (MPU)

– Thumb^®-2 instruction set

• Pin-to-pin compatible with AT91SAM7S legacy products (64-pin versions), SAM3S4/2/1

products

• Memories

– 512 Kbytes Single Plane (SAM3S8) embedded Flash, 128-bit wide access, memory

accelerator

– 512 Kbytes Dual Plane (SAM3SD8) embedded Flash, 128-bit wide access, memory

accelerator

– 64 Kbytes embedded SRAM

– 16 Kbytes ROM with embedded boot loader routines (UART, USB) and IAP routines

– 8-bit Static Memory Controller (SMC): SRAM, PSRAM, NOR and NAND Flash

support

AT91SAM

ARM-based

Flash MCU

• System

– Embedded voltage regulator for single supply operation

– Power-on-Reset (POR), Brown-out Detector (BOD) and Watchdog for safe operation

– Quartz or ceramic resonator oscillators: 3 to 20 MHz main power with Failure

Detection and optional low-power 32.768 kHz for RTC or device clock

– RTC with Gregorian and Persian Calendar mode, waveform generation in low-

power modes

– RTC clock calibration circuitry for 32.768 kHz crystal frequency compensation

– High precision 8/12 MHz factory trimmed internal RC oscillator with 4 MHz default

frequency for device startup. In-application trimming access for frequency

adjustment

SAM3S8/SD8

Series

– Slow Clock Internal RC oscillator as permanent low-power mode device clock

– Two PLLs up to 130 MHz for device clock and for USB

– Temperature Sensor

Summary

– Up to 24 peripheral DMA (PDC) channels

• Low Power Modes

– Sleep and Backup modes, down to 1 µA in Backup mode

– Ultra low-power RTC

• Peripherals

– USB 2.0 Device: 12 Mbps, 2668 byte FIFO, up to 8 bidirectional Endpoints. On-Chip

Transceiver

– Up to 3 USARTs with ISO7816, IrDA^®, RS-485, SPI, Manchester and Modem Mode

– Two 2-wire UARTs

– Up to 2 Two Wire Interface (I2C compatible), 1 SPI, 1 Serial Synchronous Controller

(I2S), 1 High Speed Multimedia Card Interface (SDIO/SD Card/MMC)

– 6 Three-Channel 16-bit Timer/Counter with capture, waveform, compare and PWM

mode. Quadrature Decoder Logic and 2-bit Gray Up/Down Counter for Stepper

Motor

– 4-channel 16-bit PWM with Complementary Output, Fault Input, 12-bit Dead Time

Generator Counter for Motor Control

– 32-bit Real-time Timer and RTC with calendar and alarm features

– Up to 15-channel, 1Msps ADC with differential input mode and programmable gain

stage and auto calibration

– One 2-channel 12-bit 1Msps DAC

– One Analog Comparator with flexible input selection, Selectable input hysteresis

– 32-bit Cyclic Redundancy Check Calculation Unit (CRCCU)

• I/O

– Up to 79 I/O lines with external interrupt capability (edge or level sensitivity),

debouncing, glitch filtering and on-die Series Resistor Termination

– Three 32-bit Parallel Input/Output Controllers, Peripheral DMA assisted Parallel

Capture Mode

• Packages

– 100-lead LQFP, 14 x 14 mm, pitch 0.5 mm/100-ball TFBGA, 9 x 9 mm, pitch 0.8 mm

– 64-lead LQFP, 10 x 10 mm, pitch 0.5 mm/64-pad QFN 9x9 mm, pitch 0.5 mm

11090BS–ATARM–22-Oct-13

1. Description

The Atmel SAM3S8/SD8 series is a member of a family of Flash microcontrollers based on the

high performance 32-bit ARM Cortex-M3 RISC processor. It operates at a maximum speed of

64 MHz and features up to 512 Kbytes of Flash (dual plane on SAM3SD8) and up to 64 Kbytes

of SRAM. The peripheral set includes a Full Speed USB Device port with embedded transceiver,

a High Speed MCI for SDIO/SD/MMC, an External Bus Interface featuring a Static Memory Con-

troller providing connection to SRAM, PSRAM, NOR Flash, LCD Module and NAND Flash, 2(3)x

USARTs, (3 on SAM3SD8C) 2x UARTs, 2x TWIs, 3x SPI, an I2S, as well as 1 PWM timer, 6x

general-purpose 16-bit timers (with stepper motor and quadrature decoder logic support), an

RTC, a 12-bit ADC, a 12-bit DAC and an analog comparator.

The SAM3S8/SD8 series is ready for capacitive touch thanks to the QTouch^®library, offering an

easy way to implement buttons, wheels and sliders.

The SAM3S8/SD8 device is a medium range general purpose microcontroller with the best ratio

in terms of reduced power consumption, processing power and peripheral set. This enables the

SAM3S8/SD8 to sustain a wide range of applications including consumer, industrial control, and

PC peripherals.

It operates from 1.62V to 3.6V and is available in 64- and 100-pin QFP, 64-pin QFN, and 100-pin

BGA packages.

The SAM3S8/SD8 series is the ideal migration path from the SAM7S series for applications that

require more performance. The SAM3S8/SD8 series is pin-to-pin compatible with the SAM7S

series.

1.1

Configuration Summary

The SAM3S8/SD8 series devices differ in memory size, package and features. Table 1-1 sum-

marizes the configurations of the device family.

Table 1-1.

Configuration Summary

SAM3S8B

Feature

SAM3S8C

512 Kbytes

64 Kbytes

SAM3SD8B

512 Kbytes

64 Kbytes

SAM3SD8C

512 Kbytes

64 Kbytes

Flash

512 Kbytes

SRAM

64 Kbytes

LQFP64

QFN64

LQFP100

BGA100

LQFP64

QFN64

LQFP100

BGA100

Package

Number of PIOs

12-bit ADC

47

79

47

79

11 channels⁽²⁾

16 channels⁽²⁾

11 channels⁽²⁾

16 channels⁽²⁾

12-bit DAC

2 channels

Timer Counter

Channels

6

PDC Channels

USART/UART

HSMCI

22

2/2⁽¹⁾

22

2/2⁽¹⁾

24

2/2⁽¹⁾

24

3/2⁽¹⁾

1 port/4 bits

8-bit data,

4 chip selects,

24-bit address

8-bit data,

4 chip selects,

24-bit address

External Bus

Interface

-

Notes: 1. Full Modem support on USART1.

2. One channel is reserved for internal temperature sensor.

2

SAM3S8/SD8 Summary

11090BS–ATARM–22-Oct-13

SAM3S8/SD8 Summary

2. Block Diagram

Figure 2-1. SAM3S8/SD8 100-pin version Block Diagram

SystemController

TST

Voltage

Regulator

PCK0-PCK2

PLLA

PMC

JTAG & Serial Wire

PLLB

Flash

Unique

Identifier

RC Osc

12/8/4 MHz

In-Circuit Emulator

24-Bit

SysTick Counter

N

V

I

XIN

XOUT

3-20 MHz

Osc

Cortex M-3 Processor

Fmax 64 MHz

512 KBytes FLASH

SRAM

64 KBytes 16 KBytes

ROM

C

SAM3S8 Single Bank

SAM3SD8 Dual Bank

SUPC

MPU

I/D

XIN32

XOUT32

Osc 32 kHz

RC 32 kHz

S

ERASE

3-layer AHB Bus Matrix Fmax 64 MHz

8 GPBREG

VDDIO

VDDCORE

VDDPLL

RTT

POR

RTCOUT0

RTCOUT1

RTC

RSTC

SM

NRST

2668 USB 2.0

Bytes Full

FIFO Speed

Peripheral

Bridge

DDP

DDM

WDT

PIOA / PIOB / PIOC

D[7:0]

A[0:23]

A21/NANDALE

A22/NANDCLE

NCS0

NCS1

NCS2

NCS3

NRD

TWCK0

TWD0

External Bus

Interface

TWI0

TWI1

PDC

TWCK1

TWD1

NAND Flash

Logic

URXD0

UTXD0

URXD1

UTXD1

RXD0

TXD0

SCK0

RTS0

CTS0

UART0

UART1

PDC

Static Memory

Controller

NWE

USART0

NANDOE

NANDWE

NWAIT

PDC

RXD1

TXD1

SCK1

RTS1

CTS1

DSR1

DTR1

RI1

PDC

PIODC[7:0]

USART1

USART2

PIODCEN1

PIODCEN2

PIODCCLK

PIO

PDC

DCD1

RXD2

TXD2

SCK2

RTS2

CTS2

NPCS0

NPCS1

NPCS2

NPCS3

MISO

PDC

(SAM3SD8 Only)

PDC

SPI

TCLK[0:2]

Timer Counter B

TC[0..2]

MOSI

SPCK

TIOA[0:2]

TIOB[0:2]

PDC

TF

TK

TD

RD

RK

RF

SSC

TCLK[3:5]

Timer Counter B

TC[3..5]

TIOA[3:5]

TIOB[3:5]

MCCK

MCCDA

MCDA[0..3]

High Speed MCI

PWMH[0:3]

PWML[0:3]

PWMFI0

ADTRG

PWM

Analog

Comparator

ADVREF

PDC

ADC Ch.

Temp. Sensor

CRC Unit

AD[0..14]

12-bit ADC

12-bit DAC

PDC

ADVREF

DAC0

DAC1

DATRG

3

11090BS–ATARM–22-Oct-13

Figure 2-2. SAM3S8/SD8 64-pin version Block Diagram

SystemController

TST

Voltage

Regulator

PCK0-PCK2

PLLA

PMC

JTAG & Serial Wire

PLLB

Flash

Unique

Identifier

RC Osc

12/8/4 MHz

In-Circuit Emulator

24-Bit

SysTick Counter

N

V

I

XIN

XOUT

3-20 MHz

Osc

Cortex M-3 Processor

Fmax 64 MHz

512 KBytes FLASH

SRAM

64 KBytes 16 KBytes

ROM

C

SAM3S8 Single Bank

SAM3SD8 Dual Bank

SUPC

MPU

I/D

XIN32

XOUT32

Osc 32 kHz

RC 32 kHz

S

ERASE

3-layer AHB Bus Matrix Fmax 64 MHz

8 GPBREG

VDDIO

VDDCORE

VDDPLL

RTT

POR

RTCOUT0

RTCOUT1

RTC

RSTC

SM

NRST

2668 USB 2.0

Bytes Full

FIFO Speed

Peripheral

Bridge

DDP

DDM

WDT

PIOA / PIOB

TWCK0

TWD0

TWI0

TWI1

PDC

TWCK1

TWD1

URXD0

UTXD0

UART0

UART1

PDC

PIODC[7:0]

PIODCEN1

PIODCEN2

PIODCCLK

URXD1

UTXD1

PIO

PDC

RXD0

TXD0

SCK0

RTS0

CTS0

USART0

USART1

NPCS0

NPCS1

NPCS2

NPCS3

MISO

PDC

RXD1

TXD1

SCK1

RTS1

CTS1

DSR1

DTR1

RI1

SPI

MOSI

SPCK

PDC

DCD1

PDC

TF

TK

TD

RD

RK

RF

TCLK[0:2]

TIOA[0:2]

Timer Counter A

TC[0..2]

SSC

TIOB[0:2]

PWMH[0:3]

MCCK

PWM

PWML[0:3]

PWMFI0

MCCDA

MCDA[0..3]

High Speed MCI

PDC

ADTRG

Temp. Sensor

AD[0..14]

Analog

Comparator

ADVREF

12-bit ADC

PDC

ADC Ch.

ADVREF

DAC0

DAC1

DATRG

12-bit DAC

CRC Unit

4

SAM3S8/SD8 Summary

11090BS–ATARM–22-Oct-13

SAM3S8/SD8 Summary

3. Signal Description

Table 3-1 gives details on signal names classified by peripheral.

Table 3-1.

Signal Description List

Active

Level

Voltage

reference Comments

Signal Name

Function

Type

Power Supplies

Peripherals I/O Lines and USB transceiver

Power Supply

VDDIO

VDDIN

Power

1.62V to 3.6V

1.8V to 3.6V⁽⁴⁾

Voltage Regulator Input, ADC, DAC and

Analog Comparator Power Supply

VDDOUT

VDDPLL

Voltage Regulator Output

Power

1.8V Output

Oscillator and PLL Power Supply

1.62 V to 1.95V

1.62V to 1.95V

Power the core, the embedded memories

and the peripherals

VDDCORE

GND

Power

Ground

Clocks, Oscillators and PLLs

XIN

Main Oscillator Input

Input

Output

Input

Reset State:

- PIO Input

XOUT

XIN32

XOUT32

Main Oscillator Output

- Internal Pull-up disabled

- Schmitt Trigger enabled⁽¹⁾

Slow Clock Oscillator Input

Slow Clock Oscillator Output

Output

VDDIO

Reset State:

- PIO Input

PCK0 - PCK2

Programmable Clock Output

Output

- Internal Pull-up enabled

- Schmitt Trigger enabled⁽¹⁾

Real Time Clock

RTCOUT0

RTCOUT1

Programmable RTC waveform output

Output

Reset State:

- PIO Input

VDDIO

- Internal Pull-up disabled

- Schmitt Trigger enabled⁽¹⁾

Programmable RTC waveform output

Output

Serial Wire/JTAG Debug Port - SWJ-DP

TCK/SWCLK

TDI

Test Clock/Serial Wire Clock

Input

Reset State:

Test Data In

- SWJ-DP Mode

- Internal pull-up disabled⁽⁵⁾

- Schmitt Trigger enabled⁽¹⁾

Test Data Out / Trace Asynchronous Data

Out

TDO/TRACESWO

TMS/SWDIO

JTAGSEL

Output

VDDIO

Test Mode Select /Serial Wire Input/Output Input / I/O

JTAG Selection Input

Permanent Internal

pull-down

High

5

11090BS–ATARM–22-Oct-13

Table 3-1.

Signal Description List (Continued)

Active

Level

Voltage

reference Comments

Signal Name

Function

Type

Flash Memory

Reset State:

- Erase Input

VDDIO

Flash and NVM Configuration Bits Erase

Command

ERASE

Input

High

Low

- Internal pull-down enabled

- Schmitt Trigger enabled⁽¹⁾

Reset/Test

Permanent Internal

pull-up

NRST

TST

Synchronous Microcontroller Reset

Test Select

I/O

VDDIO

Permanent Internal

pull-down

Input

Universal Asynchronous Receiver Transceiver - UARTx

URXDx

UTXDx

UART Receive Data

Input

UART Transmit Data

Output

PIO Controller - PIOA - PIOB - PIOC

PA0 - PA31

PB0 - PB14

Parallel IO Controller A

Parallel IO Controller B

I/O

Reset State:

- PIO or System IOs⁽²⁾

- Internal pull-up enabled

- Schmitt Trigger enabled⁽¹⁾

VDDIO

PC0 - PC31

Parallel IO Controller C

I/O

PIO Controller - Parallel Capture Mode

PIODC0-PIODC7

PIODCCLK

Parallel Capture Mode Data

Parallel Capture Mode Clock

Parallel Capture Mode Enable

Input

PIODCEN1-2

Input

External Bus Interface

D0 - D7

A0 - A23

NWAIT

Data Bus

I/O

Address Bus

Output

Input

External Wait Signal

Low

Static Memory Controller - SMC

NCS0 - NCS3

NRD

Chip Select Lines

Read Signal

Output

Low

NWE

Write Enable

Output

NAND Flash Logic

Output

NANDOE

NANDWE

NAND Flash Output Enable

NAND Flash Write Enable

Low

Output

High Speed Multimedia Card Interface - HSMCI

MCCK

Multimedia Card Clock

I/O

MCCDA

Multimedia Card Slot A Command

Multimedia Card Slot A Data

MCDA0 - MCDA3

6

SAM3S8/SD8 Summary

11090BS–ATARM–22-Oct-13

SAM3S8/SD8 Summary

Table 3-1.

Signal Description List (Continued)

Active

Level

Voltage

reference Comments

Signal Name

Function

Type

Universal Synchronous Asynchronous Receiver Transmitter USARTx

SCKx

TXDx

RXDx

RTSx

CTSx

DTR1

DSR1

DCD1

RI1

USARTx Serial Clock

I/O

USARTx Transmit Data

USARTx Receive Data

Input

Output

Input

I/O

USARTx Request To Send

USARTx Clear To Send

USART1 Data Terminal Ready

USART1 Data Set Ready

USART1 Data Carrier Detect

USART1 Ring Indicator

Input

Output

Input

Synchronous Serial Controller - SSC

TD

RD

TK

RK

TF

RF

SSC Transmit Data

SSC Receive Data

SSC Transmit Clock

SSC Receive Clock

Output

Input

I/O

SSC Transmit Frame Sync

SSC Receive Frame Sync

I/O

Timer/Counter - TC

TCLKx

TIOAx

TIOBx

TC Channel x External Clock Input

TC Channel x I/O Line A

Input

I/O

TC Channel x I/O Line B

I/O

Pulse Width Modulation Controller- PWMC

PWMHx

PWMLx

PWMFI0

PWM Waveform Output High for channel x

Output

Input

only output in

complementary mode

when dead time insertion

is enabled.

PWM Waveform Output Low for channel x

PWM Fault Input

Serial Peripheral Interface - SPI

MISO

Master In Slave Out

Master Out Slave In

SPI Serial Clock

I/O

MOSI

SPCK

SPI_NPCS0

SPI Peripheral Chip Select 0

SPI Peripheral Chip Select

I/O

Low

SPI_NPCS1 -

SPI_NPCS3

Output

7

11090BS–ATARM–22-Oct-13

Table 3-1.

Signal Description List (Continued)

Active

Level

Voltage

reference Comments

Signal Name

Function

Type

Two-Wire Interface- TWI

TWDx

TWIx Two-wire Serial Data

TWIx Two-wire Serial Clock

I/O

TWCKx

Analog

ADC, DAC and Analog Comparator

Reference

ADVREF

Analog

12-bit Analog-to-Digital Converter - ADC

Analog,

Digital

AD0-AD14

ADTRG

Analog Inputs

ADC Trigger

Input

VDDIO

12-bit Digital-to-Analog Converter - DAC

Analog,

Digital

DAC0 - DAC1

DACTRG

Analog output

DAC Trigger

Input

VDDIO

Fast Flash Programming Interface - FFPI

PGMEN0-

PGMEN2

Programming Enabling

Input

PGMM0-PGMM3

PGMD0-PGMD15

PGMRDY

Programming Mode

Programming Data

Programming Ready

Data Direction

Input

I/O

Output

High

Low

PGMNVALID

PGMNOE

Output

VDDIO

Programming Read

Programming Clock

Programming Command

Input

PGMCK

PGMNCMD

Input

Low

USB Full Speed Device

DDM

DDP

USB Full Speed Data -

USB Full Speed Data +

Reset State:

Analog,

Digital

VDDIO

- USB Mode

- Internal Pull-down⁽³⁾

Note:

1. Schmitt Triggers can be disabled through PIO registers.

2. Some PIO lines are shared with System I/Os.

3. Refer to USB Section of the product Electrical Characteristics for information on Pull-down value in USB Mode.

4. See “Typical Powering Schematics” Section for restrictions on voltage range of Analog Cells.

5. TDO pin is set in input mode when the Cortex-M3 Core is not in debug mode. Thus the internal pull-up corresponding to this

PIO line must be enabled to avoid current consumption due to floating input.

8

SAM3S8/SD8 Summary

11090BS–ATARM–22-Oct-13

SAM3S8/SD8 Summary

4. Package and Pinout

SAM3S8/SD8 devices are pin-to-pin compatible with AT91SAM7S legacy products for 64-pin

version. Furthermore, SAM3S8/SD8 products have new functionalities referenced in italic in

Table 4-1, Table 4-3.

4.1

SAM3S8C/8DC Package and Pinout

4.1.1

100-Lead LQFP Package Outline

Figure 4-1. Orientation of the 100-lead LQFP Package

75

51

76

50

100

26

1

25

4.1.2

100-ball TFBGA Package Outline

The 100-Ball TFBGA package has a 0.8 mm ball pitch and respects Green Standards. Its

dimensions are 9 x 9 x 1.1 mm. Figure 4-2 shows the orientation of the 100-ball TFBGA

Package.

Figure 4-2. Orientation of the 100-ball TFBGA Package

TOP VIEW

10

9

8

7

6

5

4

3

2

1

A

B

C

D

E

F

G

H

J

K

BALL A1

9

11090BS–ATARM–22-Oct-13

4.1.3

100-Lead LQFP Pinout

Table 4-1.

SAM3S8C/SD8C 100-lead LQFP pinout

TDO/TRACESWO/

PB5

1

ADVREF

26

GND

51

TDI/PB4

76

2

3

GND

PB0/AD4

PC29/AD13

PB1/AD5

PC30/AD14

PB2/AD6

PC31

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

VDDIO

PA16/PGMD4

PC7

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

PA6/PGMNOE

PA5/PGMRDY

PC28

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

JTAGSEL

PC18

4

TMS/SWDIO/PB6

PC19

5

PA15/PGMD3

PA14/PGMD2

PC6

PA4/PGMNCMD

VDDCORE

PA27/PGMD15

PC8

6

PA31

7

PC20

8

PA13/PGMD1

PA24/PGMD12

PC5

TCK/SWCLK/PB7

PC21

9

PB3/AD7

VDDIN

PA28

10

11

NRST

VDDCORE

PC22

VDDOUT

VDDCORE

PC4

TST

12

13

14

15

16

17

18

19

PA17/PGMD5/AD0

PC26

PC9

ERASE/PB12

DDM/PB10

DDP/PB11

PC23

PA25/PGMD13

PA26/PGMD14

PC3

PA29

PA18/PGMD6/AD1

PA21/PGMD9/AD8

VDDCORE

PA30

PC10

PA12/PGMD0

PA11/PGMM3

PC2

PA3

VDDIO

PC27

PA2/PGMEN2

PC11

PC24

PA19/PGMD7/AD2

PC15/AD11

PB13/DAC0

PC25

PA10/PGMM2

VDDIO

PA22/PGMD10/AD

9

20

45

GND

70

GND

95

GND

21

22

PC13/AD10

46

47

PA9/PGMM1

PC1

71

72

PC14

96

97

PB8/XOUT

PA23/PGMD11

PA1/PGMEN1

PB9/PGMCK/XIN

PA8/XOUT32/

PGMM0

23

PC12/AD12

48

73

PC16

98

VDDIO

PA7/XIN32/

24

25

PA20/PGMD8/AD3

PC0

49

50

74

75

PA0/PGMEN0

PC17

99

PB14/DAC1

VDDPLL

PGMNVALID

VDDIO

100

10

SAM3S8/SD8 Summary

11090BS–ATARM–22-Oct-13

SAM3S8/SD8 Summary

4.1.4

100-Ball TFBGA Pinout

Table 4-2.

SAM3S8C/SD8C 100-ball TFBGA pinout

A1

A2

A3

PB1/AD5

PC29

C6

C7

C8

C9

C10

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

TCK/SWCLK/PB7

PC16

F1

F2

F3

F4

F5

F6

F7

F8

F9

F10

G1

G2

G3

G4

G5

PA18/PGMD6/AD1

PC26

H6

H7

H8

H9

H10

J1

PC4

PA11/PGMM3

PC1

VDDIO

PA1/PGMEN1

PC17

VDDOUT

GND

A4

A5

A6

A7

A8

A9

A10

B1

B2

B3

B4

B5

PB9/PGMCK/XIN

PB8/XOUT

PB13/DAC0

DDP/PB11

DDM/PB10

TMS/SWDIO/PB6

JTAGSEL

PA6/PGMNOE

TDI/PB4

PA0/PGMEN0

PB3/AD7

PB0/AD4

PC24

VDDIO

PA27/PGMD15

PC8

PC15/AD11

PC0

J2

PA28

J3

PA16/PGMD4

PC6

PC22

TST

J4

GND

PC9

J5

PA24/PGMD12

PA25/PGMD13

PA10/PGMM2

GND

PC30

GND

PA21/PGMD9/AD8

PC27

J6

ADVREF

VDDCORE

PA2/PGMEN2

PC11

J7

GNDANA

PA15/PGMD3

VDDCORE

J8

PB14/DAC1

PC21

J9

VDDCORE

VDDIO

PC14

J10

PA17/PGMD5/AD

0

PA22/PGMD10/AD

9

B6

PC20

E1

G6

PA26/PGMD14

K1

B7

B8

B9

PA31

PC19

PC18

E2

E3

E4

PC31

VDDIN

GND

G7

G8

G9

PA12/PGMD0

PC28

K2

K3

K4

PC13/AD10

PC12/AD12

PA4/PGMNCMD

PA20/PGMD8/AD3

TDO/TRACESWO/

PB5

B10

E5

GND

G10

PA5/PGMRDY

K5

PC5

C1

C2

C3

PB2/AD6

VDDPLL

PC25

E6

E7

E8

NRST

H1

H2

H3

PA19/PGMD7/AD2

PA23/PGMD11

PC7

K6

K7

K8

PC3

PC2

PA29/AD13

PA30/AD14

PA9/PGMM1

PA8/XOUT32/PGM

M0

C4

C5

PC23

E9

PC10

PA3

H4

H5

PA14/PGMD2

PA13/PGMD1

K9

PA7/XIN32/

PGMNVALID

ERASE/PB12

E10

K10

11

11090BS–ATARM–22-Oct-13

4.2

SAM3S8B/D8B Package and Pinout

4.2.1

64-Lead LQFP Package Outline

Figure 4-3. Orientation of the 64-lead LQFP Package

33

48

49

32

17

64

16

1

4.2.2

64-lead QFN Package Outline

Figure 4-4. Orientation of the 64-lead QFN Package

64

1

49

48

16

33

32

17

TOP VIEW

12

SAM3S8/SD8 Summary

11090BS–ATARM–22-Oct-13

SAM3S8/SD8 Summary

4.2.3

64-Lead LQFP and QFN Pinout

Table 4-3.

64-pin SAM3S8B/D8B pinout

TDO/TRACESWO/

1

ADVREF

17

GND

33

TDI/PB4

49

PB5

2

3

4

5

6

7

8

GND

18

19

20

21

22

23

24

VDDIO

34

35

36

37

38

39

40

PA6/PGMNOE

PA5/PGMRDY

PA4/PGMNCMD

PA27/PGMD15

PA28

50

51

52

53

54

55

56

JTAGSEL

PB0/AD4

PB1/AD5

PB2/AD6

PB3/AD7

VDDIN

PA16/PGMD4

PA15/PGMD3

PA14/PGMD2

PA13/PGMD1

PA24/PGMD12

VDDCORE

TMS/SWDIO/PB6

PA31

TCK/SWCLK/PB7

VDDCORE

ERASE/PB12

DDM/PB10

NRST

VDDOUT

TST

PA17/PGMD5/

9

25

26

PA25/PGMD13

PA26/PGMD14

41

42

PA29

PA30

57

58

DDP/PB11

VDDIO

AD0

PA18/PGMD6/

AD1

10

PA21/PGMD9/

AD8

11

12

13

27

28

29

PA12/PGMD0

PA11/PGMM3

PA10/PGMM2

43

44

45

PA3

59

60

61

PB13/DAC0

GND

VDDCORE

PA2/PGMEN2

VDDIO

PA19/PGMD7/

AD2

XOUT/PB8

PA22/PGMD10/

AD9

14

15

16

30

31

32

PA9/PGMM1

46

47

48

GND

62

63

64

XIN/PGMCK/PB9

PB14/DAC1

VDDPLL

PA8/XOUT32/

PA23/PGMD11

PA1/PGMEN1

PA0/PGMEN0

PGMM0

PA20/PGMD8/

AD3

PA7/XIN32/

PGMNVALID

Note:

The bottom pad of the QFN package must be connected to ground.

13

11090BS–ATARM–22-Oct-13

5. Power Considerations

5.1

Power Supplies

The SAM3S8/SD8 has several types of power supply pins:

• VDDCORE pins: Power the core, the embedded memories and the peripherals. Voltage

ranges from 1.62V to 1.95V.

• VDDIO pins: Power the Peripherals I/O lines (Input/Output Buffers), USB transceiver, Backup

part, 32 kHz crystal oscillator and oscillator pads. Voltage ranges from 1.62V to 3.6V.

• VDDIN pin: Voltage Regulator Input, ADC, DAC and Analog Comparator Power Supply.

Voltage ranges from 1.8V to 3.6V.

• VDDPLL pin: Powers the PLLA, PLLB, the Fast RC and the 3 to 20 MHz oscillator. Voltage

ranges from 1.62V to 1.95V.

5.2

Voltage Regulator

The SAM3S8/SD8 embeds a voltage regulator that is managed by the Supply Controller.

This internal regulator is designed to supply the internal core of SAM3S8/SD8. It features two

operating modes:

• In Normal mode, the voltage regulator consumes less than 700 µA static current and draws

80 mA of output current. Internal adaptive biasing adjusts the regulator quiescent current

depending on the required load current. In Wait Mode quiescent current is only 7 µA.

• In Backup mode, the voltage regulator consumes less than 1 µA while its output (VDDOUT)

is driven internally to GND. The default output voltage is 1.80V and the start-up time to reach

Normal mode is less than 100 µs.

For adequate input and output power supply decoupling/bypassing, refer to the “Voltage Regula-

tor” section in the “Electrical Characteristics” section of the datasheet.

5.3

Typical Powering Schematics

The SAM3S8/SD8 supports a 1.62V-3.6V single supply mode. The internal regulator input con-

nected to the source and its output feeds VDDCORE. Figure 5-1 below shows the power

schematics.

As VDDIN powers the voltage regulator, the ADC, DAC and the analog comparator, when the

user does not want to use the embedded voltage regulator, it can be disabled by software via

the SUPC (note that this is different from Backup mode).

14

SAM3S8/SD8 Summary

11090BS–ATARM–22-Oct-13

SAM3S8/SD8 Summary

Figure 5-1. Single Supply

VDDIO

USB

Transceivers.

Main Supply

(1.8V-3.6V)

ADC, DAC

Analog Comp.

VDDIN

VDDOUT

Voltage

Regulator

VDDCORE

VDDPLL

Note:

Restrictions

With Main Supply < 2.0 V, USB and ADC/DAC and Analog comparator are not usable.

With Main Supply ≥ 2.0V and < 3V, USB is not usable.

With Main Supply ≥ 3V, all peripherals are usable.

Figure 5-2. Core Externally Supplied

Main Supply

(1.62V-3.6V)

VDDIO

VDDIN

USB

Transceivers.

Can be the

same supply

ADC, DAC

Analog Comp.

ADC, DAC, Analog

Comparator Supply

(2.0V-3.6V)

VDDOUT

Voltage

Regulator

VDDCORE

VDDCORE Supply

(1.62V-1.95V)

VDDPLL

Note:

Restrictions

With Main Supply < 2.0V, USB is not usable.

With VDDIN < 2.0V, ADC, DAC and Analog comparator are not usable.

With Main Supply ≥ 2.0V and < 3V, USB is not usable.

With Main Supply and VDDIN ≥ 3V, all peripherals are usable.

Figure 5-3 below provides an example of the powering scheme when using a backup battery.

Since the PIO state is preserved when in backup mode, any free PIO line can be used to switch

off the external regulator by driving the PIO line at low level (PIO is input, pull-up enabled after

backup reset). External wake-up of the system can be from a push button or any signal. See

Section 5.6 “Wake-up Sources” for further details.

15

11090BS–ATARM–22-Oct-13

Figure 5-3. Backup Battery

ADC, DAC, Analog

Comparator Supply

(2.0V-3.6V)

VDDIO

USB

Transceivers.

Backup

Battery

+

-

ADC, DAC

Analog Comp.

VDDIN

Main Supply

VDDOUT

IN

OUT

Voltage

Regulator

3.3V

LDO

VDDCORE

VDDPLL

ON/OFF

PIOx (Output)

WAKEUPx

External wakeup signal

Note: The two diodes provide a “switchover circuit” (for illustration purpose)

between the backup battery and the main supply when the system is put in

backup mode.

5.4

Active Mode

Active mode is the normal running mode with the core clock running from the fast RC oscillator,

the main crystal oscillator or the PLLA. The power management controller can be used to adapt

the frequency and to disable the peripheral clocks.

5.5

Low-power Modes

The various low-power modes of the SAM3S8/SD8 are described below:

5.5.1

Backup Mode

The purpose of backup mode is to achieve the lowest power consumption possible in a system

which is performing periodic wake-ups to perform tasks but not requiring fast startup time

(<0.1ms). Total current consumption is 1.5 µA typical.

The Supply Controller, zero-power power-on reset, RTT, RTC, Backup registers and 32 kHz

oscillator (RC or crystal oscillator selected by software in the Supply Controller) are running. The

regulator and the core supply are off.

Backup mode is based on the Cortex-M3 deep sleep mode with the voltage regulator disabled.

The SAM3S8/SD8 can be awakened from this mode through WUP0-15 pins, the supply monitor

(SM), the RTT or RTC wake-up event.

Backup mode is entered by using WFE instructions with the SLEEPDEEP bit in the Cortex-M3

System Control Register set to 1. (See the Power management description in The ARM Cortex-

M3 Processor section of the product datasheet).

Exit from Backup mode happens if one of the following enable wake up events occurs:

• WKUPEN0-15 pins (level transition, configurable debouncing)

16

SAM3S8/SD8 Summary

11090BS–ATARM–22-Oct-13

SAM3S8/SD8 Summary

• Supply Monitor alarm

• RTC alarm

• RTT alarm

5.5.2

Wait Mode

The purpose of the wait mode is to achieve very low power consumption while maintaining the

whole device in a powered state for a startup time of less than 10 µs. Current Consumption in

Wait mode is typically 15 µA (total current consumption) if the internal voltage regulator is used

or 8 µA if an external regulator is used.

In this mode, the clocks of the core, peripherals and memories are stopped. However, the core,

peripherals and memories power supplies are still powered. From this mode, a fast start up is

available.

This mode is entered via Wait for Event (WFE) instructions with LPM = 1 (Low Power Mode bit in

PMC_FSMR). The Cortex-M3 is able to handle external events or internal events in order to

wake-up the core (WFE). This is done by configuring the external lines WUP0-15 as fast startup

wake-up pins (refer to Section 5.7 “Fast Startup”). RTC or RTT Alarm and USB wake-up events

can be used to wake up the CPU (exit from WFE).

Entering Wait Mode:

• Select the 4/8/12 MHz fast RC oscillator as Main Clock

• Set the LPM bit in the PMC Fast Startup Mode Register (PMC_FSMR)

• Execute the Wait-For-Event (WFE) instruction of the processor

Note:

Internal Main clock resynchronization cycles are necessary between the writing of MOSCRCEN

bit and the effective entry in Wait mode. Depending on the user application, waiting for

MOSCRCEN bit to be cleared is recommended to ensure that the core will not execute undesired

instructions.

5.5.3

Sleep Mode

The purpose of sleep mode is to optimize power consumption of the device versus response

time. In this mode, only the core clock is stopped. The peripheral clocks can be enabled. The

current consumption in this mode is application dependent.

This mode is entered via Wait for Interrupt (WFI) or Wait for Event (WFE) instructions with

LPM = 0 in PMC_FSMR.

The processor can be awakened from an interrupt if WFI instruction of the Cortex M3 is used, or

from an event if the WFE instruction is used to enter this mode.

17

11090BS–ATARM–22-Oct-13

5.5.4

Low Power Mode Summary Table

The modes detailed above are the main low-power modes. Each part can be set to on or off sep-

arately and wake up sources can be individually configured. Table 5-1 below shows a summary

of the configurations of the low-power modes.

Table 5-1.

Low-power Mode Configuration Summary

SUPC,

32 kHz

Oscillator,

RTC, RTT

Backup

Registers,

POR

Core

PIO State

Memory

(Backup

Region)

Potential Wake Up Core at while in Low PIO State Consumption Wake-up

(2) (3)

Mode

Regulator Peripherals Mode Entry

Sources

Wake Up Power Mode at Wake Up

Time⁽¹⁾

PIOA &

PIOB &

PIOC

Inputs with

pull ups

WUP0-15 pins

SM alarm

RTC alarm

RTT alarm

WFE

OFF

Backup

Mode

ON

OFF

Reset

1.5 µA typ⁽⁴⁾< 0.1 ms

+SLEEPDEEP

(Not powered)

bit = 1

Any Event from: Fast

startup through

WFE

Powered

Wait

Mode

+SLEEPDEEP WUP0-15 pins

Clocked Previous

back state saved

ON

Unchanged 5 µA/15 µA ⁽⁵⁾< 10 µs

bit = 0

RTC alarm

RTT alarm

USB wake-up

(Not clocked)

+LPM bit = 1

Entry mode =WFI

Interrupt Only; Entry

mode =WFE Any

Enabled Interrupt

and/or Any Event

from: Fast start-up

through WUP0-15

pins

WFE or WFI

Powered⁽⁷⁾

Sleep

Mode

+SLEEPDEEP

bit = 0

Clocked Previous

back state saved

(6)

ON

Unchanged

(Not clocked)

+LPM bit = 0

RTC alarm

RTT alarm

USB wake-up

Notes: 1. When considering wake-up time, the time required to start the PLL is not taken into account. Once started, the device works

with the 4/8/12 MHz fast RC oscillator. The user has to add the PLL start-up time if it is needed in the system. The wake-up

time is defined as the time taken for wake up until the first instruction is fetched.

2. The external loads on PIOs are not taken into account in the calculation.

3. Supply Monitor current consumption is not included.

4. Total Current consumption.

5. 5 µA on VDDCORE, 15 µA for total current consumption (using internal voltage regulator), 8 µA for total current consumption

(without using internal voltage regulator).

6. Depends on MCK frequency.

7. In this mode the core is supplied and not clocked but some peripherals can be clocked.

18

SAM3S8/SD8 Summary

11090BS–ATARM–22-Oct-13

SAM3S8/SD8 Summary

5.6

Wake-up Sources

The wake-up events allow the device to exit the backup mode. When a wake-up event is

detected, the Supply Controller performs a sequence which automatically reenables the core

power supply and the SRAM power supply, if they are not already enabled.

Figure 5-4. Wake-up Source

SMEN

sm_out

RTCEN

RTTEN

rtc_alarm

Core

Supply

Restart

rtt_alarm

WKUPT0

WKUPEN0

WKUPEN1

WKUPIS0

WKUPIS1

Falling/Rising

Edge

Detector

WKUP0

WKUP1

WKUPDBC

Debouncer

SLCK

WKUPS

WKUPT1

Falling/Rising

Edge

Detector

WKUPT15

WKUPEN15

WKUPIS15

Falling/Rising

Edge

WKUP15

Detector

19

11090BS–ATARM–22-Oct-13

5.7

Fast Startup

The SAM3S8/SD8 allows the processor to restart in a few microseconds while the processor is

in wait mode or in sleep mode. A fast start up can occur upon detection of a low level on one of

the 19 wake-up inputs (WKUP0 to 15 + SM + RTC + RTT).

The fast restart circuitry, as shown in Figure 5-5, is fully asynchronous and provides a fast start-

up signal to the Power Management Controller. As soon as the fast start-up signal is asserted,

the PMC automatically restarts the embedded 4 MHz Fast RC oscillator, switches the master

clock on this 4MHz clock and reenables the processor clock.

Figure 5-5. Fast Start-Up Sources

USBEN

usb_wakeup

RTCEN

rtc_alarm

RTTEN

rtt_alarm

FSTT0

Falling/Rising

Edge

Detector

WKUP0

fast_restart

FSTT1

Falling/Rising

Edge

Detector

WKUP1

FSTT15

Falling/Rising

Edge

WKUP15

Detector

20

SAM3S8/SD8 Summary

11090BS–ATARM–22-Oct-13

SAM3S8/SD8 Summary

6. Input/Output Lines

The SAM3S8/SD8 has several kinds of input/output (I/O) lines such as general purpose I/Os

(GPIO) and system I/Os. GPIOs can have alternate functionality due to multiplexing capabilities

of the PIO controllers. The same PIO line can be used whether in I/O mode or by the multiplexed

peripheral. System I/Os include pins such as test pins, oscillators, erase or analog inputs.

6.1

General Purpose I/O Lines

GPIO Lines are managed by PIO Controllers. All I/Os have several input or output modes such

as pull-up or pull-down, input Schmitt triggers, multi-drive (open-drain), glitch filters, debouncing

or input change interrupt. Programming of these modes is performed independently for each I/O

line through the PIO controller user interface. For more details, refer to the product “PIO Control-

ler” section.

The input/output buffers of the PIO lines are supplied through VDDIO power supply rail.

The SAM3S8/SD8 embeds high speed pads able to handle up to 32 MHz for HSMCI (MCK/2),

45 MHz for SPI clock lines and 35 MHz on other lines. See AC Characteristics Section of the

datasheet for more details. Typical pull-up and pull-down value is 100 kΩ for all I/Os.

Each I/O line also embeds an ODT (On-Die Termination), (see Figure 6-1 below). It consists of

an internal series resistor termination scheme for impedance matching between the driver out-

put (SAM3S8/SD8) and the PCB trace impedance preventing signal reflection. The series

resistor helps to reduce IOs switching current (di/dt) thereby reducing in turn, EMI. It also

decreases overshoot and undershoot (ringing) due to inductance of interconnect between

devices or between boards. In conclusion ODT helps diminish signal integrity issues.

Figure 6-1. On-Die Termination

Z0 ~ Zout + Rodt

ODT

36 Ohms Typ.

Rodt

Receiver

SAM3 Driver with

PCB Trace

Zout ~ 10 Ohms

Z0 ~ 50 Ohms

6.2

System I/O Lines

System I/O lines are pins used by oscillators, test mode, reset and JTAG to name but a few.

Described below in Table 6-1are the SAM3S8/SD8 system I/O lines shared with PIO lines.

These pins are software configurable as general purpose I/O or system pins. At startup the

default function of these pins is always used.

21

11090BS–ATARM–22-Oct-13

Table 6-1.

System I/O Configuration Pin List.

SYSTEM_IO

bit number

Default function

after reset

Constraints for

normal start

Other function

PB12

Configuration

12

10

11

7

ERASE

DDM

Low Level at startup⁽¹⁾

PB10

-

In Matrix User Interface Registers

DDP

PB11

(Refer to the System I/O

Configuration Register in the “Bus

Matrix” section of the datasheet.)

TCK/SWCLK

TMS/SWDIO

TDO/TRACESWO

TDI

PB7

6

PB6

5

PB5

4

PB4

-

PA7

XIN32

XOUT32

XIN

See footnote ⁽²⁾below

See footnote ⁽³⁾below

-

PA8

-

PB9

-

PB8

XOUT

Notes: 1. If PB12 is used as PIO input in user applications, a low level must be ensured at startup to prevent Flash erase before the

user application sets PB12 into PIO mode,

2. In the product Datasheet Refer to: “Slow Clock Generator” of the “Supply Controller” section.

3. In the product Datasheet Refer to: “3 to 20 MHZ Crystal Oscillator” information in the “PMC” section.

6.2.1

Serial Wire JTAG Debug Port (SWJ-DP) Pins

The SWJ-DP pins are TCK/SWCLK, TMS/SWDIO, TDO/SWO, TDI and commonly provided on

a standard 20-pin JTAG connector defined by ARM. For more details about voltage reference

and reset state, refer to Table 3-1 on page 5.

At startup, SWJ-DP pins are configured in SWJ-DP mode to allow connection with debugging

probe. Please refer to the “Debug and Test” Section of the product datasheet.

SWJ-DP pins can be used as standard I/Os to provide users more general input/output pins

when the debug port is not needed in the end application. Mode selection between SWJ-DP

mode (System IO mode) and general IO mode is performed through the AHB Matrix Special

Function Registers (MATRIX_SFR). Configuration of the pad for pull-up, triggers, debouncing

and glitch filters is possible regardless of the mode.

The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It

integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left uncon-

nected for normal operations.

By default, the JTAG Debug Port is active. If the debugger host wants to switch to the Serial

Wire Debug Port, it must provide a dedicated JTAG sequence on TMS/SWDIO and

TCK/SWCLK which disables the JTAG-DP and enables the SW-DP. When the Serial Wire

Debug Port is active, TDO/TRACESWO can be used for trace.

The asynchronous TRACE output (TRACESWO) is multiplexed with TDO. So the asynchronous

trace can only be used with SW-DP, not JTAG-DP. For more information about SW-DP and

JTAG-DP switching, please refer to the “Debug and Test” Section.

22

SAM3S8/SD8 Summary

11090BS–ATARM–22-Oct-13

SAM3S8/SD8 Summary

6.3

6.4

Test Pin

The TST pin is used for JTAG Boundary Scan Manufacturing Test or Fast Flash programming

mode of the SAM3S8/SD8 series. The TST pin integrates a permanent pull-down resistor of

about 15 kΩ to GND, so that it can be left unconnected for normal operations. To enter fast pro-

gramming mode, see the Fast Flash Programming Interface (FFPI) section. For more on the

manufacturing and test mode, refer to the “Debug and Test” section of the product datasheet.

NRST Pin

The NRST pin is bidirectional. It is handled by the on-chip reset controller and can be driven low

to provide a reset signal to the external components or asserted low externally to reset the

microcontroller. It will reset the Core and the peripherals except the Backup region (RTC, RTT

and Supply Controller). There is no constraint on the length of the reset pulse and the reset con-

troller can guarantee a minimum pulse length. The NRST pin integrates a permanent pull-up

resistor to VDDIO of about 100 kΩ. By default, the NRST pin is configured as an input.

6.5

ERASE Pin

The ERASE pin is used to reinitialize the Flash content (and some of its NVM bits) to an erased

state (all bits read as logic level 1). It integrates a pull-down resistor of about 100 kΩ to GND, so

that it can be left unconnected for normal operations.

This pin is debounced by SCLK to improve the glitch tolerance. When the ERASE pin is tied high

during less than 100 ms, it is not taken into account. The pin must be tied high during more than

220 ms to perform a Flash erase operation.

The ERASE pin is a system I/O pin and can be used as a standard I/O. At startup, the ERASE

pin is not configured as a PIO pin. If the ERASE pin is used as a standard I/O, startup level of

this pin must be low to prevent unwanted erasing. Refer to Section 10.17 “Peripheral Signal Mul-

tiplexing on I/O Lines” on page 40. Also, if the ERASE pin is used as a standard I/O output,

asserting the pin to low does not erase the Flash.

23

11090BS–ATARM–22-Oct-13

7. Processor and Architecture

7.1

ARM Cortex-M3 Processor

• Version 2.0

• Thumb-2 (ISA) subset consisting of all base Thumb-2 instructions, 16-bit and 32-bit.

• Harvard processor architecture enabling simultaneous instruction fetch with data load/store.

• Three-stage pipeline.

• Single cycle 32-bit multiply.

• Hardware divide.

• Thumb and Debug states.

• Handler and Thread modes.

• Low latency ISR entry and exit.

7.2

7.3

APB/AHB bridge

The SAM3S8/SD8 embeds One Peripheral bridge:

The peripherals of the bridge are clocked by MCK.

Matrix Masters

The Bus Matrix of the SAM3S8/SD8 manages 4 masters, which means that each master can

perform an access concurrently with others, to an available slave.

Each master has its own decoder, which is defined specifically for each master. In order to sim-

plify the addressing, all the masters have the same decodings.

Table 7-1.

List of Bus Matrix Masters

Master 0

Master 1

Master 2

Master 3

Cortex-M3 Instruction/Data

Cortex-M3 System

Peripheral DMA Controller (PDC)

CRC Calculation Unit

7.4

Matrix Slaves

The Bus Matrix of the SAM3S8/SD8 manages 5 slaves. Each slave has its own arbiter, allowing

a different arbitration per slave.

Table 7-2.

Slave 0

Slave 1

Slave 2

Slave 3

Slave 4

List of Bus Matrix Slaves

Internal SRAM

Internal ROM

Internal Flash

External Bus Interface

Peripheral Bridge

24

SAM3S8/SD8 Summary

11090BS–ATARM–22-Oct-13

SAM3S8/SD8 Summary

7.5

Master to Slave Access

All the Masters can normally access all the Slaves. However, some paths do not make sense,

for example allowing access from the Cortex-M3 S Bus to the Internal ROM. Thus, these paths

are forbidden or simply not wired, and shown as “-” in the following table.

Table 7-3.

SAM3S8_SD8 Master to Slave Access

Masters

0

1

2

3

Cortex-M3 I/D

Bus

Cortex-M3 S

Bus

Slaves

PDC

CRCCU

0

1

2

3

4

Internal SRAM

Internal ROM

Internal Flash

-

X

-

X

-

X

-

X

-

External Bus Interface

Peripheral Bridge

X

-

7.6

Peripheral DMA Controller

• Handles data transfer between peripherals and memories

• Low bus arbitration overhead

– One Master Clock cycle needed for a transfer from memory to peripheral

– Two Master Clock cycles needed for a transfer from peripheral to memory

• Next Pointer management for reducing interrupt latency requirement

The Peripheral DMA Controller handles transfer requests from the channel according to the fol-

lowing priorities (Low to High priorities):

Table 7-4.

Peripheral DMA Controller

Instance name

USART2

PWM

Channel T/R

Transmit

Receive

Transmit

TWI1

TWI0

UART1

UART0

USART1

USART0

DACC

SPI

25

11090BS–ATARM–22-Oct-13

Table 7-4.

Peripheral DMA Controller

Instance name

SSC

Channel T/R

Transmit

Receive

HSMCI

PIOA

TWI1

TWI0

UART1

UART0

USART1

USART0

ADC

SPI

SSC

HSMCI

7.7

Debug and Test Features

• Debug access to all memory and registers in the system, including Cortex-M3 register bank

when the core is running, halted, or held in reset.

• Serial Wire Debug Port (SW-DP) and Serial Wire JTAG Debug Port (SWJ-DP) debug access

• Flash Patch and Breakpoint (FPB) unit for implementing breakpoints and code patches

• Data Watchpoint and Trace (DWT) unit for implementing watch points, data tracing, and

system profiling

• Instrumentation Trace Macrocell (ITM) for support of printf style debugging

• IEEE^®1149.1 JTAG Boundary scan on All Digital Pins

26

SAM3S8/SD8 Summary

11090BS–ATARM–22-Oct-13

SAM3S8/SD8 Summary

8. Product Mapping

Figure 8-1. SAM3S8/SD8 Product Mapping

Address memory space

Code

Peripherals

Code

0x40000000

0x00000000

0x00400000

0x00800000

0x00C00000

0x1FFFFFFF

HSMCI

SSC

Boot Memory

18

22

21

0x40004000

0x40008000

0x4000C000

0x40010000

+0x40

1 MByte

bit band

regiion

Internal Flash

Internal ROM

Reserved

0x20000000

0x20100000

SRAM

SPI

0x22000000

Reserved

TC0

Undefined

TC0

TC1

0x24000000

0x40000000

32 MBytes

bit band alias

23

24

25

26

27

28

19

20

31

14

15

16

TC1

+0x80

Peripherals

TC2

External RAM

0x60000000

0x61000000

0x60000000

0xA0000000

0x40014000

+0x40

TC3

SMC Chip Select 0

SMC Chip Select 1

SMC Chip Select 2

External SRAM

TC4

0x62000000

0x63000000

0x64000000

+0x80

Reserved

System

TC5

0x40018000

0x4001C000

0x40020000

0x40024000

0x40028000

0x4002C000

0x40030000

0x40034000

0x40038000

0x4003C000

0x40040000

0x40044000

0x40048000

0x400E0000

0xE0000000

0xFFFFFFFF

SMC Chip Select 3

Reserved

TWI0

0x9FFFFFFF

TWI1

1 MByte

bit band

regiion

System Controller

PWM

0x400E0000

0x400E0200

0x400E0400

0x400E0600

0x400E0740

0x400E0800

0x400E0A00

0x400E0C00

0x400E0E00

0x400E1000

0x400E1200

0x400E1400

SMC

USART0

USART1

USART2

Reserved

UDP

10

MATRIX

offset

block

peripheral

ID

PMC

5

UART0

8

CHIPID

33

29

30

34

35

UART1

ADC

9

EFC

DACC

ACC

6

Reserved

PIOA

CRCCU

Reserved

11

PIOB

12

PIOC

System Controller

Reserved

13

0x400E2600

0x40100000

RSTC

1

+0x10

+0x30

+0x50

+0x60

+0x90

SUPC

Reserved

0x40200000

0x40400000

RTT

32 MBytes

bit band alias

3

WDT

Reserved

4

0x60000000

RTC

2

GPBR

0x400E1600

0x4007FFFF

Reserved

27

11090BS–ATARM–22-Oct-13

9. Memories

9.1

Embedded Memories

9.1.1

Internal SRAM

The SAM3S8 device (512-Kbytes, single bank flash) embeds a total of 64-Kbytes high-speed

SRAM.

The SAM3SD8 device (512-Kbytes, dual bank flash) embeds a total of 64-Kbytes high-speed

SRAM.

The SRAM is accessible over System Cortex-M3 bus at address 0x2000 0000.

The SRAM is in the bit band region. The bit band alias region is from 0x2200 0000 and

0x23FF FFFF.

9.1.2

Internal ROM

The SAM3S8/SD8 embeds an Internal ROM, which contains the SAM Boot Assistant

(SAM-BA^®), In Application Programming routines (IAP) and Fast Flash Programming Interface

(FFPI).

At any time, the ROM is mapped at address 0x0080 0000.

9.1.3

Embedded Flash

9.1.3.1

Flash Overview

The Flash of the SAM3S8 (512-Kbytes single bank flash) is organized in one bank of 2048

pages of 256 bytes.

The Flash of the SAM3SD8 (512-Kbytes, dual bank flash) is organized in two banks of 1024

pages of 256 bytes each.

The Flash contains a 128-byte write buffer, accessible through a 32-bit interface.

9.1.3.2

9.1.3.3

Flash Power Supply

The Flash is supplied by VDDCORE.

Enhanced Embedded Flash Controller

The Enhanced Embedded Flash Controller (EEFC) manages accesses performed by the mas-

ters of the system. It enables reading the Flash and writing the write buffer. It also contains a

User Interface, mapped on the APB.

The Enhanced Embedded Flash Controller ensures the interface of the Flash block with the 32-

bit internal bus. Its 128-bit wide memory interface increases performance.

The user can choose between high performance or lower current consumption by selecting

either 128-bit or 64-bit access. It also manages the programming, erasing, locking and unlocking

sequences of the Flash using a full set of commands.

One of the commands returns the embedded Flash descriptor definition that informs the system

about the Flash organization, thus making the software generic.

28

SAM3S8/SD8 Summary

11090BS–ATARM–22-Oct-13

SAM3S8/SD8 Summary

9.1.3.4

9.1.3.5

Flash Speed

Lock Regions

The user needs to set the number of wait states depending on the frequency used:

For more details, refer to the “AC Characteristics” sub-section of the product “Electrical

Characteristics”.

Several lock bits are used to protect write and erase operations on lock regions. A lock region is

composed of several consecutive pages, and each lock region has its associated lock bit.

Table 9-1.

Lock bit number

Product

SAM3S8/SD8

Number of lock bits

Lock region size

16

32 kbytes (128 pages)

If a locked-region’s erase or program command occurs, the command is aborted and the EEFC

triggers an interrupt.

The lock bits are software programmable through the EEFC User Interface. The command “Set

Lock Bit” enables the protection. The command “Clear Lock Bit” unlocks the lock region.

Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.

9.1.3.6

Security Bit Feature

The SAM3S8/SD8 features a security bit, based on a specific General Purpose NVM bit

(GPNVM bit 0). When the security is enabled, any access to the Flash, SRAM, Core Registers

and Internal Peripherals either through the ICE interface or through the Fast Flash Programming

Interface, is forbidden. This ensures the confidentiality of the code programmed in the Flash.

This security bit can only be enabled, through the command “Set General Purpose NVM Bit 0” of

the EEFC User Interface. Disabling the security bit can only be achieved by asserting the

ERASE pin at 1, and after a full Flash erase is performed. When the security bit is deactivated,

all accesses to the Flash, SRAM, Core registers, Internal Peripherals are permitted.

It is important to note that the assertion of the ERASE pin should always be longer than 200 ms.

As the ERASE pin integrates a permanent pull-down, it can be left unconnected during normal

operation. However, it is safer to connect it directly to GND for the final application.

9.1.3.7

Calibration Bits

NVM bits are used to calibrate the brownout detector and the voltage regulator. These bits are

factory configured and cannot be changed by the user. The ERASE pin has no effect on the cal-

ibration bits.

9.1.3.8

9.1.3.9

Unique Identifier

Each device integrates its own 128-bit unique identifier. These bits are factory configured and

cannot be changed by the user. The ERASE pin has no effect on the unique identifier.

Fast Flash Programming Interface

The Fast Flash Programming Interface allows programming the device through either a serial

JTAG interface or through a multiplexed fully-handshaked parallel port. It allows gang program-

ming with market-standard industrial programmers.

29

11090BS–ATARM–22-Oct-13

The FFPI supports read, page program, page erase, full erase, lock, unlock and protect

commands.

9.1.3.10

SAM-BA Boot

The SAM-BA Boot is a default Boot Program which provides an easy way to program in-situ the

on-chip Flash memory.

The SAM-BA Boot Assistant supports serial communication via the UART and USB.

The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI).

The SAM-BA Boot is in ROM and is mapped in Flash at address 0x0 when GPNVM bit 1 is

set to 0.

9.1.3.11

GPNVM Bits

The SAM3S8 features two GPNVM bits, whereas SAM3SD8 features three GPNVM bits. These

bits can be cleared or set respectively through the commands “Clear GPNVM Bit” and “Set

GPNVM Bit” of the EEFC User Interface.

The Flash of the SAM3S8 is composed of 512 Kbytes in a single bank, while the SAM3SD8

Flash is composed of dual banks, each containing 256 Kbytes. The dual-bank function enables

programming one bank while the other one is read (typically while the application code is run-

ning). Only one EEFC (Flash controller) controls the two banks. Note that it is not possible to

program simultaneously, or read simultaneously, the dual banks of the Flash.

The first bank of 256 Kbytes is called Bank 0 and the second bank of 256 Kbytes, Bank 1.

The SAM3SD8 embeds an additional GPNVM bit: GPNVM2.

Table 9-2.

General-purpose Non volatile Memory Bits

GPNVMBit[#]

Function

0

1

2

Security bit

Boot mode selection

Bank selection (Bank 0 or Bank 1) Only on SAM3SD8

9.1.4

Boot Strategies

The system always boots at address 0x0. To ensure maximum boot possibilities, the memory

layout can be changed via GPNVM.

A general purpose NVM (GPNVM) bit is used to boot either on the ROM (default) or from the

Flash.

The GPNVM bit can be cleared or set respectively through the commands “Clear General-pur-

pose NVM Bit” and “Set General-purpose NVM Bit” of the EEFC User Interface.

Setting GPNVM Bit 1 selects the boot from the Flash, clearing it selects the boot from the ROM.

Asserting ERASE clears the GPNVM Bit 1 and thus selects the boot from the ROM by default.

Setting the GPNVM Bit 2 selects bank 1, clearing it selects the boot from bank 0. Asserting

ERASE clears the GPNVM Bit 2 and thus selects the boot from bank 0 by default.

30

SAM3S8/SD8 Summary

11090BS–ATARM–22-Oct-13

SAM3S8/SD8 Summary

9.2

External Memories

The SAM3S8/SD8 features one External Bus Interface to provide an interface to a wide range of

external memories and to any parallel peripheral.

9.2.1

Static Memory Controller

• 16-Mbyte Address Space per Chip Select

• 8- bit Data Bus

• Word, Halfword, Byte Transfers

• Programmable Setup, Pulse And Hold Time for Read Signals per Chip Select

• Programmable Setup, Pulse And Hold Time for Write Signals per Chip Select

• Programmable Data Float Time per Chip Select

• External Wait Request

• Automatic Switch to Slow Clock Mode

• Asynchronous Read in Page Mode Supported: Page Size Ranges from 4 to 32 Bytes

• NAND Flash additional logic supporting NAND Flash with Multiplexed Data/Address buses

• Hardware Configurable number of chip selects from 1 to 4

• Programmable timing on a per chip select basis

10. System Controller

The System Controller is a set of peripherals, which allow handling of key elements of the sys-

tem, such as power, resets, clocks, time, interrupts, watchdog, etc...

See the system controller block diagram in Figure 10-1 on page 32.

31

11090BS–ATARM–22-Oct-13

Figure 10-1. System Controller Block Diagram

VDDIO

VDDOUT

vr_on

vr_mode

Software Controlled

Voltage Regulator

VDDIN

VDDIO

Supply

Zero-Power

Power-on Reset

Controller

PIOA/B/C

Input/Output Buffers

PIOx

ON

Supply

Monitor

(Backup)

out

Analog

Comparator

WKUP0 - WKUP15

ADx

General Purpose

Backup Registers

ADC Analog

Circuitry

ADVREF

DACx

rtc_nreset

DAC Analog

Circuitry

SLCK

RTC

rtc_alarm

VDDIO

rtt_nreset

rtt_alarm

RTT

DDP

DDM

USB

Transeivers

osc32k_xtal_en

XTALSEL

vddcore_nreset

XIN32

Xtal 32 kHz

Slow Clock

SLCK

bod_core_on

Brownout

Detector

(Core)

Oscillator

XOUT32

lcore_brown_out

VDDCORE

Embedded

32 kHz RC

Oscillator

osc32k_rc_en

SRAM

vddcore_nreset

Backup Power Supply

Peripherals

proc_nreset

periph_nreset

ice_nreset

Reset

Controller

Matrix

Peripheral

Bridge

NRST

Cortex-M3

Flash

FSTT0 - FSTT15

SLCK

Main Clock

Embedded

12 / 8 / 4 MHz

RC

Oscillator

MAINCK

Power

Management

Controller

Master Clock

MCK

XIN

3 - 20 MHz

XTAL Oscillator

XOUT

PLLACK

PLLBCK

MAINCK

PLLA

PLLB

Watchdog

Timer

SLCK

VDDIO

Core Power Supply

FSTT0 - FSTT15 are possible Fast Startup sources, generated by WKUP0 - WKUP15 pins,

but are not physical pins.

32

SAM3S8/SD8 Summary

11090BS–ATARM–22-Oct-13

SAM3S8/SD8 Summary

10.1 System Controller and Peripherals Mapping

Please refer to Section 8-1 “SAM3S8/SD8 Product Mapping” on page 27.

All the peripherals are in the bit band region and are mapped in the bit band alias region.

10.2 Power-on-Reset, Brownout and Supply Monitor

The SAM3S8/SD8 embeds three features to monitor, warn and/or reset the chip:

• Power-on-Reset on VDDIO

• Brownout Detector on VDDCORE

• Supply Monitor on VDDIO

10.2.1

10.2.2

Power-on-Reset

The Power-on-Reset monitors VDDIO. It is always activated and monitors voltage at start up but

also during power down. If VDDIO goes below the threshold voltage, the entire chip is reset. For

more information, refer to the Electrical Characteristics section of the datasheet.

Brownout Detector on VDDCORE

The Brownout Detector monitors VDDCORE. It is active by default. It can be deactivated by soft-

ware through the Supply Controller (SUPC_MR). It is especially recommended to disable it

during low-power modes such as wait or sleep modes.

If VDDCORE goes below the threshold voltage, the reset of the core is asserted. For more infor-

mation, refer to the Supply Controller (SUPC) and Electrical Characteristics sections of the

datasheet.

10.2.3

Supply Monitor on VDDIO

The Supply Monitor monitors VDDIO. It is not active by default. It can be activated by software

and is fully programmable with 16 steps for the threshold (between 1.9V to 3.4V). It is controlled

by the Supply Controller (SUPC). A sample mode is possible. It allows to divide the supply mon-

itor power consumption by a factor of up to 2048. For more information, refer to the SUPC and

Electrical Characteristics sections of the datasheet.

10.3 Reset Controller

The Reset Controller is based on a Power-on-Reset cell, and a Supply Monitor on VDDCORE.

The Reset Controller is capable to return to the software the source of the last reset, either a

general reset, a wake-up reset, a software reset, a user reset or a watchdog reset.

The Reset Controller controls the internal resets of the system and the NRST pin input/output. It

is capable to shape a reset signal for the external devices, simplifying to a minimum connection

of a push-button on the NRST pin to implement a manual reset.

The configuration of the Reset Controller is saved as supplied on VDDIO.

10.4 Supply Controller (SUPC)

The Supply Controller controls the power supplies of each section of the processor and the

peripherals (via Voltage regulator control)

The Supply Controller has its own reset circuitry and is clocked by the 32 kHz Slow clock

generator.

33

11090BS–ATARM–22-Oct-13

The reset circuitry is based on a zero-power power-on reset cell and a brownout detector cell.

The zero-power power-on reset allows the Supply Controller to start properly, while the soft-

ware-programmable brownout detector allows detection of either a battery discharge or main

voltage loss.

The Slow Clock generator is based on a 32 kHz crystal oscillator and an embedded 32 kHz RC

oscillator. The Slow Clock defaults to the RC oscillator, but the software can enable the crystal

oscillator and select it as the Slow Clock source.

The Supply Controller starts up the device by sequentially enabling the internal power switches

and the Voltage Regulator, then it generates the proper reset signals to the core power supply.

It also enables to set the system in different low-power modes and to wake it up from a wide

range of events.

10.5 Clock Generator

The Clock Generator is made up of:

• One Low-power 32768Hz Slow Clock Oscillator with bypass mode

• One Low-power RC Oscillator

• One 3-20 MHz Crystal Oscillator, which can be bypassed

• One Fast RC Oscillator, factory programmed. Three output frequencies can be selected: 4, 8

or 12 MHz. By default 4 MHz is selected.

• One 60 to 130 MHz PLL (PLLB) providing a clock for the USB Full Speed Controller

• One 60 to 130 MHz programmable PLL (PLLA), provides the clock, MCK to the processor

and peripherals. The PLLA input frequency is from 3.5 MHz to 20 MHz.

34

SAM3S8/SD8 Summary

11090BS–ATARM–22-Oct-13

SAM3S8/SD8 Summary

Figure 10-2. Clock Generator Block Diagram

Clock Generator

XTALSEL

On Chip

32k RC OSC

Slow Clock

SLCK

XIN32

Slow Clock

Oscillator

XOUT32

XIN

12M Main

Oscillator

Main Clock

MAINCK

XOUT

On Chip

12/8/4 MHz

RC OSC

MAINSEL

PLLB Clock

PLLBCK

PLL and

Divider B

PLL and

Divider A

PLLA Clock

PLLACK

Status

Power

Control

Management

Controller

10.6 Power Management Controller

The Power Management Controller provides all the clock signals to the system. It provides:

• the Processor Clock, HCLK

• the Free running processor clock, FCLK

• the Cortex SysTick external clock

• the Master Clock, MCK, in particular to the Matrix and the memory interfaces

• the USB Clock, UDPCK

• independent peripheral clocks, typically at the frequency of MCK

• three programmable clock outputs: PCK0, PCK1 and PCK2

The Supply Controller selects between the 32 kHz RC oscillator or the crystal oscillator. The

unused oscillator is disabled automatically so that power consumption is optimized.

By default, at startup the chip runs out of the Master Clock using the fast RC oscillator running at

4 MHz.

The user can trim the 8 and 12 MHz RC Oscillator frequency by software.

35

11090BS–ATARM–22-Oct-13

Figure 10-3. Power Management Controller Block Diagram

Processor

Clock

Controller

HCK

int

Sleep Mode

Divider

/8

SystTick

FCLK

Master Clock Controller

SLCK

MAINCK

PLLACK

PLLBCK

Prescaler

/1,/2,/4,...,/64

MCK

Peripherals

Clock Controller

periph_clk[..]

ON/OFF

Programmable Clock Controller

SLCK

MAINCK

PLLACK

PLLBCK

ON/OFF

Prescaler

/1,/2,/4,...,/64

pck[..]

USB Clock Controller

ON/OFF

PLLBCK

UDPCK

The SysTick calibration value is fixed at 8000, which allows the generation of a time base of 1

ms with SysTick clock at 8 MHz (max HCLK/8 = 64 MHz/8)

10.7 Watchdog Timer

• 16-bit key-protected only-once Programmable Counter

• Windowed, prevents the processor to be in a deadlock on the watchdog access

10.8 SysTick Timer

• 24-bit down counter

• Self-reload capability

• Flexible System timer

36

SAM3S8/SD8 Summary

11090BS–ATARM–22-Oct-13

SAM3S8/SD8 Summary

10.9 Real-Time Timer

10.10 Real Time Clock

• Real-Time Timer, allowing backup of time with different accuracies

– 32-bit Free-running backup Counter

– Integrates a 16-bit programmable prescaler running on slow clock

– Alarm Register capable to generate a wake-up of the system through the Shut Down

Controller

• Low power consumption

• Full asynchronous design

• Two hundred year Gregorian and Persian calendar

• Programmable Periodic Interrupt

• Trimmable 32.7682 kHz crystal oscillator clock source

• Alarm and update parallel load

• Control of alarm and update Time/Calendar Data In

• Waveform output capability on GPIO pins in low power modes

10.11 General-Purpose Backed-up Registers

• Eight 32-bit backup general-purpose registers

10.12 Nested Vectored Interrupt Controller

• Thirty maskable external interrupts

• Sixteen priority levels

• Processor state automatically saved on interrupt entry, and restored on

• Dynamic reprioritizing of interrupts

• Priority grouping.

– selection of pre-empting interrupt levels and non pre-empting interrupt levels.

• Support for tail-chaining and late arrival of interrupts.

– back-to-back interrupt processing without the overhead of state saving and

restoration between interrupts.

• Processor state automatically saved on interrupt entry, and restored on interrupt exit, with no

instruction overhead.

37

11090BS–ATARM–22-Oct-13

10.13 Chip Identification

• Chip Identifier (CHIPID) registers permit recognition of the device and its revision.

Table 10-1. SAM3S8/SD8 Hip IDs Register

Flash Size

Chip Name

(KBytes)

Pin Count

CHIPID_CIDR

0x289B0A60

0x28AB0A60

0x299B0A60

0x29AB0A60

CHIPID_EXID

SAM3S8B (Rev A)

512

64

100

64

0x0

SAM3S8C (Rev A)

512

SAM3SD8B (Rev A)

SAM3SD8C (Rev A)

• JTAG ID: 0x05B2D03F

512

100

10.14 UART

• Two-pin UART

– Implemented features are 100% compatible with the standard Atmel USART

– Independent receiver and transmitter with a common programmable Baud Rate

Generator

– Even, Odd, Mark or Space Parity Generation

– Parity, Framing and Overrun Error Detection

– Automatic Echo, Local Loopback and Remote Loopback Channel Modes

– Support for two PDC channels with connection to receiver and transmitter

10.15 PIO Controllers

• 3 PIO Controllers, PIOA, PIOB and PIOC (100-pin version only) controlling a maximum of 79

I/O Lines

• Each PIO Controller controls up to 32 programmable I/O Lines

• Fully programmable through Set/Clear Registers

Table 10-2. PIO available according to pin count

Version

PIOA

64 pin

100 pin

32

15

-

PIOB

15

PIOC

32

• Multiplexing of four peripheral functions per I/O Line

• For each I/O Line (whether assigned to a peripheral or used as general purpose I/O)

– Input change interrupt

– Programmable Glitch filter

– Programmable debouncing filter

– Multi-drive option enables driving in open drain

– Programmable pull-up on each I/O line

– Pin data status register, supplies visibility of the level on the pin at any time

– Additional interrupt modes on a programmable event: rising edge, falling edge, low

level or high level

38

SAM3S8/SD8 Summary

11090BS–ATARM–22-Oct-13

SAM3S8/SD8 Summary

– Lock of the configuration by the connected peripheral

• Synchronous output, provides set and clear of several I/O lines in a single write

• Write Protect Registers

• Programmable Schmitt trigger inputs

• Parallel capture mode

– Can be used to interface a CMOS digital image sensor, an ADC....

– One clock, 8-bit parallel data and two data enable on I/O lines

– Data can be sampled one time out of two (for chrominance sampling only)

– Supports connection of one Peripheral DMA Controller channel (PDC) which offers

buffer reception without processor intervention

10.16 Peripheral Identifiers

Table 10-3 defines the Peripheral Identifiers of the SAM3S8/SD8. A peripheral identifier is

required for the control of the peripheral interrupt with the Nested Vectored Interrupt Controller

and control of the peripheral clock with the Power Management Controller.

Table 10-3. Peripheral Identifiers

PMC

Instance ID

Instance Name

SUPC

RSTC

RTC

NVIC Interrupt

Clock Control

Instance Description

Supply Controller

0

1

X

-

Reset Controller

2

Real Time Clock

3

RTT

Real Time Timer

4

WDT

Watchdog Timer

5

PMC

Power Management Controller

Enhanced Embedded Flash Controller

Reserved

6

EEFC

-

7

8

UART0

UART1

SMC

X

-

X

-

UART 0

9

UART 1

10

11

12

13

14

15

16

17

18

19

20

21

Static Memory Controller

Parallel I/O Controller A

Parallel I/O Controller B

Parallel I/O Controller C

USART 0

PIOA

PIOB

PIOC

USART0

USART1

USART2

-

USART 1

USART 2 (SAM3SD8 100 pins only)

Reserved

HSMCI

TWI0

X

Multimedia Card Interface

Two Wire Interface 0

Two Wire Interface 1

Serial Peripheral Interface

TWI1

SPI

39

11090BS–ATARM–22-Oct-13

Table 10-3. Peripheral Identifiers (Continued)

PMC

Instance ID

Instance Name

SSC

NVIC Interrupt

Clock Control

Instance Description

Synchronous Serial Controller

Timer/Counter 0

22

23

24

25

26

27

28

29

30

31

32

33

34

X

TC0

TC1

Timer/Counter 1

TC2

Timer/Counter 2

TC3

Timer/Counter 3

TC4

Timer/Counter 4

TC5

Timer/Counter 5

ADC

Analog To Digital Converter

Digital To Analog Converter

Pulse Width Modulation

CRC Calculation Unit

Analog Comparator

USB Device Port

DACC

PWM

CRCCU

ACC

UDP

10.17 Peripheral Signal Multiplexing on I/O Lines

The SAM3S8/SD8 features 2 PIO controllers on 64-pin versions (PIOA and PIOB) or 3 PIO con-

trollers on the 100-pin version (PIOA, PIOB and PIOC), that multiplex the I/O lines of the

peripheral set.

The SAM3S8/SD8 64-pin and 100-pin PIO Controllers control up to 32 lines. Each line can be

assigned to one of three peripheral functions: A, B or C. The multiplexing tables in the following

paragraphs define how the I/O lines of the peripherals A, B and C are multiplexed on the PIO

Controllers. The column “Comments” has been inserted in this table for the user’s own com-

ments; it may be used to track how pins are defined in an application.

Note that some peripheral functions which are output only, might be duplicated within the tables.

40

SAM3S8/SD8 Summary

11090BS–ATARM–22-Oct-13

SAM3S8/SD8 Summary

10.17.1 PIO Controller A Multiplexing

Table 10-4. Multiplexing on PIO Controller A (PIOA)

I/O Line Peripheral A Peripheral B Peripheral C Peripheral D Extra Function System Function

Comments

PA0

PA1

PWMH0

PWMH1

PWMH2

TWD0

TWCK0

RXD0

TXD0

RTS0

CTS0

URXD0

UTXD0

NPCS0

MISO

MOSI

SPCK

TF

TIOA0

TIOB0

A17

A18

WKUP0

WKUP1

WKUP2

PA2

SCK0

DATRG

PA3

NPCS3

TCLK0

NPCS3

PCK0

PA4

WKUP3

WKUP4

PA5

PA6

PA7

PWMH3

ADTRG

NPCS1

NPCS2

PWMH0

PWMH1

PWMH2

PWMH3

TIOA1

XIN32

PA8

WKUP5

WKUP6

XOUT32

PA9

PWMFI0

PA10

PA11

PA12

PA13

PA14

PA15

PA16

PA17

PA18

PA19

PA20

PA21

PA22

PA23

PA24

PA25

PA26

PA27

PA28

PA29

PA30

PA31

WKUP7

WKUP8

WKUP14

WKUP15

AD0

PWML3

PWML2

PWMH3

A14

PIODCEN1

PIODCEN2

TK

TIOB1

TD

PCK1

RD

PCK2

AD1

RK

PWML0

PWML1

PCK1

A15

AD2/WKUP9

AD3/WKUP10

AD8

RF

A16

RXD1

TXD1

SCK1

RTS1

CTS1

DCD1

DTR1

DSR1

RI1

64/100 pins versions

NPCS3

PWMH0

PWMH1

PWMH2

TIOA2

NCS2

A19

AD9

PIODCCLK

PIODC0

PIODC1

PIODC2

PIODC3

PIODC4

PIODC5

PIODC6

PIODC7

A20

A23

MCDA2

MCDA3

MCCDA

MCCK

MCDA0

MCDA1

TIOB2

TCLK1

TCLK2

NPCS2

PCK2

PWML2

NPCS1

WKUP11

41

11090BS–ATARM–22-Oct-13

10.17.2 PIO Controller B Multiplexing

Table 10-5. Multiplexing on PIO Controller B (PIOB)

I/O

Line

Peripheral A

PWMH0

PWMH1

URXD1

Peripheral B

Peripheral C

Extra Function

AD4/RTCOUT0

AD5/RTCOUT1

AD6/WKUP12

AD7

System Function

Comments

PB0

PB1

PB2

NPCS2

PCK2

PB3

UTXD1

PB4

TWD1

PWMH2

PWML0

TDI

TDO/TRACESWO

TMS/SWDIO

TCK/SWCLK

XOUT

PB5

TWCK1

WKUP13

PB6

PB7

PB8

PB9

XIN

PB10

PB11

PB12

PB13

PB14

DDM

DDP

PWML1

PWML2

NPCS1

ERASE

PCK0

DAC0

DAC1

64/00 pins versions

64/100 pins versions

PWMH3

42

SAM3S8/SD8 Summary

11090BS–ATARM–22-Oct-13

SAM3S8/SD8 Summary

10.17.3 PIO Controller C Multiplexing

Table 10-6. Multiplexing on PIO Controller C (PIOC)

Extra

System

I/O Line

PC0

Peripheral A

Peripheral B

PWML0

PWML1

PWML2

PWML3

NPCS1

Peripheral C

Function

Comments

D0

100 pin version

PC1

D1

PC2

D2

PC3

D3

PC4

D4

PC5

D5

PC6

D6

PC7

D7

PC8

NWE

PC9

NANDOE

RXD2⁽¹⁾

TXD2⁽¹⁾

PC10

PC11

PC12

PC13

PC14

PC15

PC16

PC17

PC18

PC19

PC20

PC21

PC22

PC23

PC24

PC25

PC26

PC27

PC28

PC29

PC30

PC31

NANDWE

NRD

NCS3

AD12

AD10

NWAIT

PWML0

SCK2⁽¹⁾

PWML1

RTS2⁽¹⁾

CTS2⁽¹⁾

PWMH0

PWMH1

PWMH2

PWMH3

PWML3

TIOA3

NCS0

NCS1

AD11

A21/NANDALE

A22/NANDCLE

A0

A1

A2

A3

A4

A5

A6

TIOB3

A7

TCLK3

TIOA4

A8

A9

TIOB4

A10

A11

A12

A13

TCLK4

TIOA5

AD13

AD14

TIOB5

TCLK5

Note:

1. USART2 only on SAM3SD8 in 100 pin package.

43

11090BS–ATARM–22-Oct-13

11. Embedded Peripherals Overview

11.1 Serial Peripheral Interface (SPI)

• Supports communication with serial external devices

– Four chip selects with external decoder support allow communication with up to 15

peripherals

– Serial memories, such as DataFlash^®and 3-wire EEPROMs

– Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and

Sensors

– External co-processors

• Master or slave serial peripheral bus interface

– 8- to 16-bit programmable data length per chip select

– Programmable phase and polarity per chip select

– Programmable transfer delays between consecutive transfers and between clock

and data per chip select

– Programmable delay between consecutive transfers

– Selectable mode fault detection

• Connection to PDC channel capabilities optimizes data transfers

– One channel for the receiver, one channel for the transmitter

– Next buffer support

11.2 Two Wire Interface (TWI)

• Master, Multi-Master and Slave Mode Operation

• Compatibility with Atmel two-wire interface, serial memory and I²C compatible devices

• One, two or three bytes for slave address

• Sequential read/write operations

• Bit Rate: Up to 400 kbit/s

• General Call Supported in Slave Mode

• Connecting to PDC channel capabilities optimizes data transfers in Master Mode only

– One channel for the receiver, one channel for the transmitter

– Next buffer support

11.3 Universal Asynchronous Receiver Transceiver (UART)

• Two-pin UART

– Independent receiver and transmitter with a common programmable Baud Rate

Generator

– Even, Odd, Mark or Space Parity Generation

– Parity, Framing and Overrun Error Detection

– Automatic Echo, Local Loopback and Remote Loopback Channel Modes

– Support for two PDC channels with connection to receiver and transmitter

44

SAM3S8/SD8 Summary

11090BS–ATARM–22-Oct-13

SAM3S8/SD8 Summary

11.4 USART

• Programmable Baud Rate Generator

• 5- to 9-bit full-duplex synchronous or asynchronous serial communications

– 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode

– Parity generation and error detection

– Framing error detection, overrun error detection

– MSB- or LSB-first

– Optional break generation and detection

– By 8 or by-16 over-sampling receiver frequency

– Hardware handshaking RTS-CTS

– Receiver time-out and transmitter timeguard

– Optional Multi-drop Mode with address generation and detection

– Optional Manchester Encoding

– Full modem line support on USART1 (DCD-DSR-DTR-RI)

• RS485 with driver control signal

• ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards

– NACK handling, error counter with repetition and iteration limit

• SPI Mode

– Master or Slave

– Serial Clock programmable Phase and Polarity

– SPI Serial Clock (SCK) Frequency up to MCK/4

• IrDA modulation and demodulation

– Communication at up to 115.2 Kbps

• Test Modes

– Remote Loopback, Local Loopback, Automatic Echo

11.5 Synchronous Serial Controller (SSC)

• Provides serial synchronous communication links used in audio and telecom applications

(with CODECs in Master or Slave Modes, I²S, TDM Buses, Magnetic Card Reader)

• Contains an independent receiver and transmitter and a common clock divider

• Offers configurable frame sync and data length

• Receiver and transmitter can be programmed to start automatically or on detection of

different event on the frame sync signal

• Receiver and transmitter include a data signal, a clock signal and a frame synchronization

signal

11.6 Timer Counter (TC)

• Six 16-bit Timer Counter Channels

• Wide range of functions including:

– Frequency Measurement

– Event Counting

45

11090BS–ATARM–22-Oct-13

– Interval Measurement

– Pulse Generation

– Delay Timing

– Pulse Width Modulation

– Up/down Capabilities

• Each channel is user-configurable and contains:

– Three external clock inputs

– Five internal clock inputs

– Two multi-purpose input/output signals

• Two global registers that act on all three TC Channels

• Quadrature decoder

– Advanced line filtering

– Position / revolution / speed

• 2-bit Gray Up/Down Counter for Stepper Motor

11.7 Pulse Width Modulation Controller (PWM)

• One Four-channel 16-bit PWM Controller, 16-bit counter per channel

• Common clock generator, providing Thirteen Different Clocks

– A Modulo n counter providing eleven clocks

– Two independent Linear Dividers working on modulo n counter outputs

– High Frequency Asynchronous clocking mode

• Independent channel programming

– Independent Enable Disable Commands

– Independent Clock Selection

– Independent Period and Duty Cycle, with Double Buffering

– Programmable selection of the output waveform polarity

– Programmable center or left aligned output waveform

– Independent Output Override for each channel

– Independent complementary Outputs with 12-bit dead time generator for each

channel

– Independent Enable Disable Commands

– Independent Clock Selection

– Independent Period and Duty Cycle, with Double Buffering

• Synchronous Channel mode

– Synchronous Channels share the same counter

– Mode to update the synchronous channels registers after a programmable number

of periods

• Connection to one PDC channel

– Provides Buffer transfer without processor intervention, to update duty cycle of

synchronous channels

• Two independent event lines which can send up to 4 triggers on ADC within a period

46

SAM3S8/SD8 Summary

11090BS–ATARM–22-Oct-13

SAM3S8/SD8 Summary

• One programmable Fault Input providing an asynchronous protection of outputs

• Stepper motor control (2 Channels)

11.8 High Speed Multimedia Card Interface (HSMCI)

• 4-bit or 1-bit Interface

• Compatibility with MultiMedia Card Specification Version 4.3

• Compatibility with SD and SDHC Memory Card Specification Version 2.0

• Compatibility with SDIO Specification Version V1.1.

• Compatibility with CE-ATA Specification 1.1

• Cards clock rate up to Master Clock divided by 2

• Boot Operation Mode support

• High Speed mode support

• Embedded power management to slow down clock rate when not used

• MCI has one slot supporting

– One MultiMediaCard bus (up to 30 cards) or

– One SD Memory Card

– One SDIO Card

• Support for stream, block and multi-block data read and write

11.9 USB Device Port (UDP)

• USB V2.0 full-speed compliant,12 Mbits per second.

• Embedded USB V2.0 full-speed transceiver

• Embedded 2688-byte dual-port RAM for endpoints

• Eight endpoints

– Endpoint 0: 64bytes

– Endpoint 1 and 2: 64 bytes ping-pong

– Endpoint 3: 64 bytes

– Endpoint 4 and 5: 512 bytes ping-pong

– Endpoint 6 and 7: 64 bytes ping-pong

– Ping-pong Mode (two memory banks) for Isochronous and bulk endpoints

• Suspend/resume logic

• Integrated Pull-up on DDP

• Pull-down resistor on DDM and DDP when disabled

11.10 Analog-to-Digital Converter (ADC12B)

• up to 16 Channels, 12-bit ADC

• 10/12-bit resolution

• up to 1 MSample/s

• Programmable conversion sequence conversion on each channel

• Integrated temperature sensor

• Automatic calibration mode

47

11090BS–ATARM–22-Oct-13

• Single ended/differential conversion

• Programmable gain: 1, 2, 4

11.11 Digital-to-Analog Converter (DAC)

• Up to 2 channel 12-bit DAC

• Up to 2 mega-samples conversion rate in single channel mode

• Flexible conversion range

• Multiple trigger sources for each channel

• 2 Sample/Hold (S/H) outputs

• Built-in offset and gain calibration

• Possible to drive output to ground

• Possible to use as input to analog comparator or ADC (as an internal wire and without S/H

stage)

• Two PDC channels

• Power reduction mode

11.12 Static Memory Controller

• 16-Mbyte Address Space per Chip Select

• 8- bit Data Bus

• Word, Halfword, Byte Transfers

• Byte Write or Byte Select Lines

• Programmable Setup, Pulse And Hold Time for Read Signals per Chip Select

• Programmable Setup, Pulse And Hold Time for Write Signals per Chip Select

• Programmable Data Float Time per Chip Select

• Compliant with LCD Module

• External Wait Request

• Automatic Switch to Slow Clock Mode

• Asynchronous Read in Page Mode Supported: Page Size Ranges from 4 to 32 Bytes

• NAND Flash additional logic supporting NAND Flash with Multiplexed Data/Address buses

• Hardware Configurable number of chip select from 1 to 4

• Programmable timing on a per chip select basis

11.13 Analog Comparator

• One analog comparator

• High speed option vs. low-power option

– 170 µA/xx ns active current consumption/propagation delay

– 20 µA/xx ns active current consumption/propagation delay

• Selectable input hysteresis

– 0, 20 mV, 50 mV

• Minus input selection:

– DAC outputs

48

SAM3S8/SD8 Summary

11090BS–ATARM–22-Oct-13

SAM3S8/SD8 Summary

– Temperature Sensor

– ADVREF

– AD0 to AD3 ADC channels

• Plus input selection:

– All analog inputs

• output selection:

– Internal signal

– external pin

– selectable inverter

• window function

• Interrupt on:

– Rising edge, Falling edge, toggle

– Signal above/below window, signal inside/outside window

11.14 Cyclic Redundancy Check Calculation Unit (CRCCU)

• 32-bit cyclic redundancy check automatic calculation

• CRC calculation between two addresses of the memory

49

11090BS–ATARM–22-Oct-13

12. Package Drawings

The SAM3S8/SD8 series devices are available in LQFP, QFN and TFBGA packages.

Figure 12-1. 100-lead LQFP Package Mechanical Drawing

Note : 1. This drawing is for general information only. Refer to JEDEC Drawing MS-026 for additional information.

50

SAM3S8/SD8 Summary

11090BS–ATARM–22-Oct-13

SAM3S8/SD8 Summary

Figure 12-2. 100-ball TFBGA Package Mechanical Drawing

51

11090BS–ATARM–22-Oct-13

Figure 12-3. 64-lead LQFP Package Mechanical Drawing

Table 12-1. 64-lead LQFP Package Dimensions (in mm)

Millimeter

Inch

Symbol

Min

–

Nom

Max

1.60

0.15

1.45

Min

–

Nom

Max

0.063

0.006

0.057

A

A1

A2

D

–

0.05

1.35

–

0.002

0.053

–

1.40

0.055

12.00 BSC

0.472 BSC

D1

E

10.00 BSC

0.383 BSC

12.00 BSC

0.472 BSC

E1

R2

R1

q

10.00 BSC

0.383 BSC

0.08

0°

–

0.20

–

0.003

0°

–

0.008

–

3.5°

–

3.5°

7°

θ₁

θ₂

θ₃

c

0°

–

0°

–

11°

0.09

0.45

12°

13°

0.20

0.75

11°

12°

13°

0.008

0.030

12°

11°

12°

–

0.004

0.018

–

L

0.60

1.00 REF

0.024

0.039 REF

L1

52

SAM3S8/SD8 Summary

11090BS–ATARM–22-Oct-13

SAM3S8/SD8 Summary

Table 12-1. 64-lead LQFP Package Dimensions (in mm) (Continued)

Millimeter

Nom

–

Inch

Nom

Symbol

Min

0.20

0.17

Max

–

Min

0.008

0.007

Max

–

S

b

–

0.20

0.27

0.008

0.011

e

0.50 BSC.

7.50

0.020 BSC.

0.285

D2

E2

7.50

0.285

Tolerances of Form and Position

0.20

aaa

bbb

ccc

ddd

0.008

0.003

0.20

0.08

53

11090BS–ATARM–22-Oct-13

Figure 12-4. 64-lead QFN Package Mechanical Drawing

54

SAM3S8/SD8 Summary

11090BS–ATARM–22-Oct-13

SAM3S8/SD8 Summary

13. Ordering Information

Table 13-1. Ordering Codes for SAM3S8/SD8 Devices

Flash

Temperature

Ordering Code

MRL

(Kbytes)

Package (Kbytes)

Package Type

Operating Range

Industrial

-40°C to 85°C

ATSAM3S8CA-AU

A

512

QFP100

Green

Industrial

-40°C to 85°C

ATSAM3S8CA-CU

ATSAM3S8BA-AU

ATSAM3S8BA-MU

ATSAM3SD8CA-AU

ATSAM3SD8CA-CU

ATSAM3SD8BA-AU

ATSAM3SD8BA-MU

A

512

BGA100

QFP64

QFN64

QFP100

BGA100

QFP64

QFN64

Green

Industrial

-40°C to 85°C

Industrial

-40°C to 85°C

Industrial

-40°C to 85°C

Industrial

-40°C to 85°C

Industrial

-40°C to 85°C

Industrial

-40°C to 85°C

55

11090BS–ATARM–22-Oct-13

Revision History

In the information that follows, the most recent version of the document is referenced first.

Change

Request

Ref.

Doc. Rev

Comments

Corrected Figure 12-3 “64-lead LQFP Package Mechanical Drawing” and inserted Table 12-1 “64-lead

LQFP Package Dimensions (in mm)”.

11090BS

9389

Change

Request

Ref.

Doc. Rev

Comments

11090AS

First issue

56

SAM3S8/SD8 Summary

11090BS–ATARM–22-Oct-13

Atmel Corporation

Atmel Asia Limited

Atmel Munich GmbH

Atmel Japan G.K.

1600 Technology Drive

Unit 01-5 & 16, 19F

Business Campus

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San Jose, CA 95110

USA

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Tel: (+1) (408) 441-0311

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www.atmel.com

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Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this

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trademarks of others.

11090BS–ATARM–22-Oct-13


型号：	ATSAM3S8BA-MU
厂家：	MICROCHIP
描述：	IC MCU 32BIT 512KB FLASH 64QFN 时钟微控制器外围集成电路
文件：	总57页 (文件大小：302K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ATSAM3S8BA-MU [MICROCHIP]

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