ATSAM3S1AB-AU [MICROCHIP]
IC MCU 32BIT 64KB FLASH 48LQFP;型号: | ATSAM3S1AB-AU |
厂家: | MICROCHIP |
描述: | IC MCU 32BIT 64KB FLASH 48LQFP |
文件: | 总60页 (文件大小:1946K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
AT91SAM ARM-based Flash MCU
SAM3S
SUMMARY
Description
Atmel's SAM3S series is a member of a family of 32-bit Flash microcontrollers based on the high performance ARM
Cortex-M3 processor. It operates at a maximum speed of 64 MHz and features up to 256 Kbytes of Flash and up to 48
Kbytes of SRAM. The peripheral set includes a Full Speed USB Device port with embedded transceiver, a High Speed MCI
for SDIO/SD/MMC, an External Bus Interface featuring a Static Memory Controller providing connection to SRAM,
PSRAM, NOR Flash, LCD Module and NAND Flash, 2x USARTs, 2x UARTs, 2x TWIs, 3x SPI, an I2S, as well as 1 PWM
timer, 6x general-purpose 16-bit timers, an RTC, an ADC, a 12-bit DAC and an analog comparator.
The SAM3S series is ready for capacitive touch thanks to the QTouch library, offering an easy way to implement buttons,
wheels and sliders
The SAM3S device is a medium range general purpose microcontroller with the best ratio in terms of reduced power
consumption, processing power and peripheral set. This enables the SAM3S to sustain a wide range of applications
including consumer, industrial control, and PC peripherals.
It operates from 1.62V to 3.6V and is available in 48-, 64- and 100-pin QFP, 48- and 64-pin QFN, and 100-pin BGA
packages.
The SAM3S series is the ideal migration path from the SAM7S series for applications that require more performance. The
SAM3S series is pin-to-pin compatible with the SAM7S series.
This is a summary document.
The complete document is
available on the Atmel website
at www.atmel.com.
6500ES–ATARM–11-Feb-13
1.
Features
• Core
®
– ARM® Cortex-M3 revision 2.0 running at up to 64 MHz
– Memory Protection Unit (MPU)
– Thumb®-2 instruction set
• Pin-to-pin compatible wAithT91SAM7S series (48- and 6v4e-rpsinons)
• Memories
– From 64 to 256 Kebmybteesdded Flash, 128-bit wide acmcemsso,ry accelerator, single plane
– From 16 toKb4y8tes embedded SRAM
– 16 Kbytes ROM with embedded bootloraoduetrines (UART, USB) and IAP routines
– 8-bit Static Memory Controller (SMC): SRAM, PSRAM, NOR andsuNppAoNrDt Flash
– Memory Protection Unit (MPU)
• System
– Embedded voltage regulatfor singlesupply operation
– Power-on-Reset (POR)B, rown-out Detector (BOD) Wanatdchdog for safe operation
– Quartz or ceramic resonator oscillators:
kHz foRr TC odrevice clock
3
to 20powMeHrz wmithain Failure Detection and olopwtionpaol wer 32.768
– High precision 8/12 fMacHtzory trimmed internal RC oscillator with
application trimming accefsosr frequency adjustment
– Slow Clock Internal RC oscillator as perlmowan-peonwt er modedevice clock
– Two PLLs up to 130 dMeHvzicefcolrock andfor USB
– Temperature Sensor
4
MfrHezquednecfyaufoltr device startup. In-
– Up to 22 peripheral DMA (PDC) channels
• Low Power Modes
– Sleep and Backup modes, down to 1.8 µA in Backup mode
– Ultra low poweRr TC
• Peripherals
– USB 2.0Device: 12 Mbps, 2668 FIbFyOt,e up to
8
bidirectional Endpoints. TOrann-sCcheiipver
– Up to US2ARTs with ISO781Ir6D,A®, RS-485, SPI, Manchester and Modem Mode
– Two 2-wireUARTs
– Up to Tw2o Wire Interface (I2C compatible),
Interface (SDIO/SD Card/MMC)
1
SPSI,yn1chroSneoriuasl Controller (I2S),
1
High Speed MCualtrimd edia
– Up to
6
Three-Channel 16-bit Timer/Counctearptuwreit,h waveform, compare and PWM mode. Quadrature Decoder
Logic and 2-Gbirtay Up/Down Countefror Stepper Motor
– 4-channel 16-bit PWM Cwoitmhplementary Output, Fault Input, 12-bit Dead Time Generatfoorr CMooutonrterControl
– 32-bit Real-time Timer RaTnCd with calendar and alarm features
– Up to 15-channel, 1Msps ADC with differential inputpromgroadmemaabnlde gainstage
– One 2-channel 12-bit 1MDsApCs
– One Analog Comparator fwleixthible input selection, Selectable input hysteresis
– 32-bit Cyclic Redundancy Check Calculation Unit (CRCCU)
– Write Protected Registers
• I/O
– Up to 79 I/O lines with external interrup(tedgcaepaoblrielivtyel sensitivity), debouncinggli,tch filtering and on-die
Series Resistor Termination
– Three 32-biPtarallel Input/Output ControllePrse,ripheral DMA assistPeadrallel Capture Mode
• Packages
– 100-lead LQFP, 14
– 64-lead LQFP, 10
– 48-lead LQFP,
x
x
14 pimtcmh , 0.5 mm/100-ball TFBGA,
10 pimtcmh , 0.5 mm/64-pad QFN 9xp9itcmh m,0.5 mm
7 pimtcmh , 0.5 mm/48-pad QFN 7xp7itcmhm,0.5 mm
9
xpitc9h m0.m8 , mm
7
x
SAM3S [SUMMARY]
2
6500ES–ATARM–11-Feb-13
1.1
Configuration Summary
The SAM3S microcontrollers differ in memory size, package and features list. Table 1-1 below summarizes the
configurations of the device family
Table 1-1. Configuration Summary
Timer
Counter
Channels
12-bit
DAC
Output
UART/
USARTs
External Bus
Interface
Device
Flash
SRAM
GPIOs
ADC
HSMCI
Package
8-bit data,
4 chip selects,
24-bit address
256 Kbytes
single plane
1 port
4 bits
LQFP100
BGA100
SAM3S4C
48 Kbytes
6
79
2/2(1)
15 ch.
2
256 Kbytes
single plane
1 port
4 bits
LQFP64
QFN 64
SAM3S4B
SAM3S4A
48 Kbytes
48 Kbytes
3
3
47
34
2/2(1)
2/1
10 ch.
8 ch.
2
-
-
-
256 Kbytes
single plane
LQFP48
QFN 48
-
8-bit data,
4 chip selects,
24-bit address
128 Kbytes
single plane
1 port
4 bits
LQFP100
BGA100
SAM3S2C
32 Kbytes
6
79
2/2(1)
15 ch.
2
128 Kbytes
single plane
1 port
4 bits
LQFP64
QFN 64
SAM3S2B
SAM3S2A
32 Kbytes
32 Kbytes
3
3
47
34
2/2(1)
2/1
10 ch.
8 ch.
2
-
-
-
128 Kbytes
single plane
LQFP48
QFN 48
-
8-bit data,
4 chip selects,
24-bit address
64 Kbytes
single plane
1 port
4 bits
LQFP100
BGA100
SAM3S1C
16 Kbytes
6
79
2/2(1)
15 ch.
2
64 Kbytes
single plane
1 port
4 bits
LQFP64
QFN 64
SAM3S1B
SAM3S1A
16 Kbytes
16 Kbytes
3
3
47
34
2/2(1)
2/1
10 ch.
8 ch.
2
-
-
-
64 Kbytes
single plane
LQFP48
QFN 48
-
Note: 1. Full Modem support on USART1.
SAM3S [SUMMARY]
3
6500ES–ATARM–11-Feb-13
2.
SAM3S Block Diagram
Figure 2-1. SAM3S 100-pin Version Block Diagram
SystemController
TS T
Voltage
Regulator
PCK0-PCK2
PLLA
PMC
JTAG & Serial Wire
PLLB
Flash
Unique
Identifier
RC
12/8/4 M
In-Circuit Emulator
24-Bit
SysTick Counter
N
V
I
3-20 MHz
Osc.
XIN
Cortex-M3 Processor
Fmax 64 MHz
XOUT
FLASH
SRAM
ROM
16 KBytes
256 KBytes
128 KBytes
64 KBytes
48 KBytes
32 KBytes
16 KBytes
C
SUPC
MPU
I/D
XIN32
XOUT32
OSC 32k
RC 32k
8 GPBREG
RTT
S
ERASE
4-layer AHB Bus Matrix Fmax 64 MHz
VDDIO
VDDCORE
VDDPLL
RTC
POR
RSTC
NRST
2668
Bytes
FIFO
USB 2.0
Full
Speed
Peripheral
Bridge
DDP
DDM
WDT
SM
PIOA / PIOB / PIOC
D[7:0]
A[0:23]
TWCK0
TWD0
External Bus
Interface
TWI0
TWI1
PDC
PDC
PDC
PDC
TWCK1
TWD1
A21/NANDALE
A22/NANDCLE
NCS0
NAND Flash
Logic
URXD0
UTXD0
UART0
NCS1
NCS2
URXD1
UTXD1
RXD0
TXD0
SCK0
RTS0
CTS0
UART1
NCS3
NRD
Static Memory
Controller
NWE
USART0
NANDOE
NANDWE
NWAIT
PDC
RXD1
TXD1
SCK1
RTS 1
CTS1
DSR1
DTR1
RI1
PDC
PIODC[7:0]
PIODCEN1
PIODCEN2
USART1
PIO
PIODCCLK
PDC
DCD1
TCLK[0:2]
Timer Counter A
TC[0..2]
NPCS0
NPCS1
NPCS2
NPCS3
MISO
PDC
TIOA[0:2]
TIOB[0:2]
SPI
MOSI
SPCK
TCLK[3:5]
Timer Counter B
TC[3..5]
PDC
PDC
TF
TK
TD
RD
RK
RF
TIOA[3:5]
TIOB[3:5]
SSC
PWMH[0:3]
PWM
PWML[0:3]
PWMFI0
ADTRG
MCCK
MCCDA
MCDA[0..3]
PDC
High Speed MCI
Temp. Sensor
AD[0..14]
ADC
DAC
Temp Sensor
ADVREF
Analog
ADC
PDC
ADVREF
DAC0
DAC1
DATRG
Comparator
DAC
PDC
CRC Unit
SAM3S [SUMMARY]
4
6500ES–ATARM–11-Feb-13
Figure 2-2. SAM3S 64-pin Version Block Diagram
SystemController
TS T
Voltage
Regulator
PCK0-PCK2
PLLA
PMC
JTAG & Serial Wire
In-Circuit Emulator
PLLB
Flash
Unique
Identifier
RC
12/8/4 M
24-Bit
SysTick Counter
N
V
I
Cortex-M3 Processor
Fmax 64 MHz
3-20 MHz
Osc.
XIN
XOUT
FLASH
SRAM
256 KBytes
128 KBytes
64 KBytes
48 KBytes
32 KBytes
16 KBytes
ROM
16 KBytes
C
SUPC
MPU
I/D
XIN32
XOUT32
OSC 32K
RC 32k
8 GPBREG
RTT
S
ERASE
4-layer AHB Bus Matrix Fmax 64 MHz
VDDIO
VDDCORE
VDDPLL
RTC
POR
USB 2.0
Full
2668
Bytes
FIFO
Peripheral
Bridge
DDP
DDM
RSTC
NRST
Speed
WDT
SM
PIOA / PIOB
TWCK0
TWD0
TWI0
TWI1
PDC
PDC
PDC
PDC
PDC
PIODC[7:0]
TWCK1
TWD1
PIODCEN1
PIODCEN2
PIODCCLK
PIO
SPI
SSC
URXD0
UTXD0
UART0
UART1
URXD1
UTXD1
RXD0
TXD0
SCK0
RTS0
CTS0
NPCS0
NPCS1
NPCS2
PDC
USART0
NPCS3
PDC
MISO
MOSI
SPCK
RXD1
TXD1
SCK1
RTS1
CTS1
DSR1
DTR1
RI1
TF
TK
TD
RD
PDC
USART1
PDC
DCD1
RK
RF
TCLK[0:2]
TIOA[0:2]
TIOB[0:2]
Timer Counter A
TC[0..2]
PDC
MCCK
MCCDA
High Speed MCI
PWMH[0:3]
PWML[0:3]
PWMFI0
PWM
MCDA[0..3]
PDC
ADC
DAC
Temp Sensor
ADVREF
ADTRG
AD[0..9]
Temp. Sensor
Analog
Comparator
ADC
PDC
ADVREF
DAC0
CRC Unit
DAC1
DATRG
DAC
PDC
SAM3S [SUMMARY]
5
6500ES–ATARM–11-Feb-13
Figure 2-3. SAM3S 48-pin Version Block Diagram
SystemController
TST
Voltage
Regulator
PCK0-PCK2
PLLA
PMC
JTAG & Serial Wire
In-Circuit Emulator
PLLB
Flash
Unique
Identifier
RC
12/8/4 M
24-Bit
SysTick Counter
N
V
I
XIN
XOUT
3-20 MHz
Osc.
Cortex-M3 Processor
Fmax 64 MHz
FLASH
SRAM
256 KBytes
128 KBytes
64 KBytes
48 KBytes
32 KBytes
16 KBytes
ROM
16 KBytes
C
SUPC
MPU
I/D
XIN32
OSC
32K
XOUT32
S
RC 32k
8 GPBREG
RTT
ERASE
4-layer AHB Bus Matrix Fmax 64 MHz
VDDIO
RTC
POR
VDDCORE
VDDPLL
USB 2.0
Full
Speed
2668
Bytes
FIFO
Peripheral
Bridge
DDP
DDM
RSTC
WDT
SM
PIOA / PIOB
TWCK0
TWD0
TWI0
TWI1
PDC
PDC
PDC
NPCS0
NPCS1
NPCS2
PDC
TWCK1
TWD1
NPCS3
SPI
URXD0
UTXD0
MISO
MOSI
SPCK
UART0
URXD1
UTXD1
UART1
PDC
RXD0
TXD0
SCK0
TF
TK
TD
RD
RK
RF
PDC
USART0
SSC
RTS0
CTS0
PDC
Timer Counter A
TC[0..2]
TCLK[0:2]
TIOA[0:2]
TIOB[0:2]
Analog
ADC
Comparator
Temp Sensor
ADVREF
PWMH[0:3]
PWML[0:3]
PWMFI0
PWM
PDC
CRC Unit
ADTRG
AD[0..7]
Temp. Sensor
ADC
PDC
ADVREF
SAM3S [SUMMARY]
6
6500ES–ATARM–11-Feb-13
3.
Signal Description
Table 3-1 gives details on the signal names classified by peripheral.
Table 3-1. Signal Description List
Active
Level
Voltage
reference Comments
Signal Name
Function
Type
Power Supplies
Peripherals I/O Lines and USB transceiver
Power Supply
VDDIO
VDDIN
Power
Power
1.62V to 3.6V
1.8V to 3.6V(4)
Voltage Regulator Input, ADC, DAC and
Analog Comparator Power Supply
VDDOUT
VDDPLL
Voltage Regulator Output
Power
Power
1.8V Output
Oscillator and PLL Power Supply
1.62 V to 1.95V
1.62V to 1.95V
Power the core, the embedded memories
and the peripherals
VDDCORE
GND
Power
Ground
Ground
Clocks, Oscillators and PLLs
XIN
Main Oscillator Input
Input
Output
Input
Reset State:
- PIO Input
XOUT
XIN32
XOUT32
Main Oscillator Output
- Internal Pull-up disabled
- Schmitt Trigger enabled(1)
Slow Clock Oscillator Input
Slow Clock Oscillator Output
Output
VDDIO
Reset State:
- PIO Input
PCK0 - PCK2
Programmable Clock Output
Output
- Internal Pull-up enabled
- Schmitt Trigger enabled(1)
Serial Wire/JTAG Debug Port - SWJ-DP
TCK/SWCLK
TDI
Test Clock/Serial Wire Clock
Input
Input
Reset State:
Test Data In
- SWJ-DP Mode
Test Data Out / Trace Asynchronous Data
Out
- Internal pull-up disabled(5)
- Schmitt Trigger enabled(1)
TDO/TRACESWO
TMS/SWDIO
JTAGSEL
Output
Input / I/O
Input
VDDIO
Test Mode Select /Serial Wire Input/Output
JTAG Selection
Permanent Internal
pull-down
High
High
Flash Memory
Reset State:
- Erase Input
Flash and NVM Configuration Bits Erase
Command
ERASE
Input
VDDIO
VDDIO
- Internal pull-down enabled
- Schmitt Trigger enabled(1)
Reset/Test
Permanent Internal
pull-up
NRST
TST
Synchronous Microcontroller Reset
Test Select
I/O
Low
Permanent Internal
pull-down
Input
SAM3S [SUMMARY]
7
6500ES–ATARM–11-Feb-13
Table 3-1. Signal Description List (Continued)
Active
Level
Voltage
reference Comments
Signal Name
Function
Type
Universal Asynchronous Receiver Transmitter - UARTx
URXDx
UTXDx
UART Receive Data
UART Transmit Data
Input
Output
PIO Controller - PIOA - PIOB - PIOC
PA0 - PA31
PB0 - PB14
Parallel IO Controller A
Parallel IO Controller B
I/O
I/O
Reset State:
- PIO or System IOs(2)
- Internal pull-up enabled
- Schmitt Trigger enabled(1)
VDDIO
VDDIO
PC0 - PC31
Parallel IO Controller C
I/O
PIO Controller - Parallel Capture Mode (PIOA Only)
PIODC0-PIODC7
PIODCCLK
Parallel Capture Mode Data
Input
Parallel Capture Mode Clock
Parallel Capture Mode Enable
Input
PIODCEN1-2
Input
External Bus Interface
D0 - D7
A0 - A23
NWAIT
Data Bus
I/O
Address Bus
Output
Input
External Wait Signal
Low
Static Memory Controller - SMC
NCS0 - NCS3
NRD
Chip Select Lines
Read Signal
Output
Output
Low
Low
Low
NWE
Write Enable
Output
NAND Flash Logic
Output
NANDOE
NANDWE
NAND Flash Output Enable
NAND Flash Write Enable
Low
Low
Output
High Speed Multimedia Card Interface - HSMCI
MCCK
Multimedia Card Clock
I/O
I/O
I/O
MCCDA
Multimedia Card Slot A Command
Multimedia Card Slot A Data
MCDA0 - MCDA3
Universal Synchronous Asynchronous Receiver Transmitter USARTx
SCKx
TXDx
RXDx
RTSx
CTSx
DTR1
DSR1
DCD1
RI1
USARTx Serial Clock
I/O
I/O
USARTx Transmit Data
USARTx Receive Data
Input
Output
Input
I/O
USARTx Request To Send
USARTx Clear To Send
USART1 Data Terminal Ready
USART1 Data Set Ready
USART1 Data Carrier Detect
USART1 Ring Indicator
Input
Input
Input
SAM3S [SUMMARY]
8
6500ES–ATARM–11-Feb-13
Table 3-1. Signal Description List (Continued)
Active
Level
Voltage
reference Comments
Signal Name
Function
Type
Synchronous Serial Controller - SSC
TD
RD
TK
RK
TF
RF
SSC Transmit Data
SSC Receive Data
SSC Transmit Clock
SSC Receive Clock
Output
Input
I/O
I/O
SSC Transmit Frame Sync
SSC Receive Frame Sync
I/O
I/O
Timer/Counter - TC
TCLKx
TIOAx
TIOBx
TC Channel x External Clock Input
TC Channel x I/O Line A
Input
I/O
TC Channel x I/O Line B
I/O
Pulse Width Modulation Controller- PWMC
PWMHx
PWMLx
PWMFI0
PWM Waveform Output High for channel x
Output
Output
Input
only output in
complementary mode when
dead time insertion is
enabled
PWM Waveform Output Low for channel x
PWM Fault Input
Serial Peripheral Interface - SPI
MISO
Master In Slave Out
Master Out Slave In
SPI Serial Clock
I/O
I/O
I/O
I/O
MOSI
SPCK
SPI_NPCS0
SPI Peripheral Chip Select 0
Low
Low
SPI_NPCS1 -
SPI_NPCS3
SPI Peripheral Chip Select
Output
Two-Wire Interface- TWI
TWDx
TWIx Two-wire Serial Data
TWIx Two-wire Serial Clock
I/O
I/O
TWCKx
Analog
ADC, DAC and Analog Comparator
Reference
ADVREF
Analog
Analog-to-Digital Converter - ADC
Analog,
Digital
AD0 - AD14
ADTRG
Analog Inputs
ADC Trigger
Input
VDDIO
VDDIO
12-bit Digital-to-Analog Converter - DAC
Analog,
Digital
DAC0 - DAC1
DACTRG
Analog output
DAC Trigger
Input
SAM3S [SUMMARY]
9
6500ES–ATARM–11-Feb-13
Table 3-1. Signal Description List (Continued)
Signal Name Function
Active
Level
Voltage
reference Comments
Type
Fast Flash Programming Interface - FFPI
PGMEN0-PGMEN2 Programming Enabling
Input
Input
I/O
VDDIO
VDDIO
PGMM0-PGMM3
PGMD0-PGMD15
PGMRDY
Programming Mode
Programming Data
Programming Ready
Data Direction
Output
High
Low
Low
PGMNVALID
PGMNOE
Output
Programming Read
Programming Clock
Programming Command
Input
Input
PGMCK
PGMNCMD
Input
Low
USB Full Speed Device
DDM
DDP
USB Full Speed Data -
USB Full Speed Data +
Reset State:
Analog,
Digital
VDDIO
- USB Mode
- Internal Pull-down(3)
Notes: 1. Schmitt Triggers can be disabled through PIO registers.
2. Some PIO lines are shared with System IOs.
3. Refer to the USB sub section in the product Electrical Characteristics Section for Pull-down value in USB Mode.
4. See Section 5.3 “Typical Powering Schematics” for restriction on voltage range of Analog Cells.
5. TDO pin is set in input mode when the Cortex-M3 Core is not in debug mode. Thus the internal pull-up corresponding
to this PIO line must be enabled to avoid current consumption due to floating input.
SAM3S [SUMMARY]
10
6500ES–ATARM–11-Feb-13
4.
Package and Pinout
4.1
SAM3S4/2/1C Package and Pinout
Figure 4-2 shows the orientation of the 100-ball TFBGA Package
4.1.1 100-lead LQFP Package Outline
Figure 4-1. Orientation of the 100-lead LQFP Package
75
51
76
50
100
26
1
25
4.1.2 100-ball TFBGA Package Outline
The 100-Ball TFBGA package has a 0.8 mm ball pitch and respects Green Standards. Its dimensions are 9 x 9 x 1.1 mm.
Figure 4-2. Orientation of the 100-BALL TFBGA Package
TOP VIEW
10
9
8
7
6
5
4
3
2
1
A B C D E F G H J K
BALL A1
SAM3S [SUMMARY]
11
6500ES–ATARM–11-Feb-13
4.1.3 100-Lead LQFP Pinout
Table 4-1. 100-lead LQFP SAM3S4/2/1C Pinout
TDO/TRACESWO/PB
5
1
ADVREF
26
GND
51
TDI/PB4
76
2
3
GND
PB0/AD4
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
VDDIO
PA16/PGMD4
PC7
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
PA6/PGMNOE
PA5/PGMRDY
PC28
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
JTAGSEL
PC18
4
PC29/AD13
PB1/AD5
TMS/SWDIO/PB6
PC19
5
PA15/PGMD3
PA14/PGMD2
PC6
PA4/PGMNCMD
VDDCORE
PA27/PGMD15
PC8
6
PC30/AD14
PB2/AD6
PA31
7
PC20
8
PC31
PA13/PGMD1
PA24/PGMD12
PC5
TCK/SWCLK/PB7
PC21
9
PB3/AD7
PA28
10
11
12
13
14
15
16
17
18
19
20
21
22
VDDIN
NRST
VDDCORE
PC22
VDDOUT
VDDCORE
PC4
TST
PA17/PGMD5/AD0
PC26
PC9
ERASE/PB12
DDM/PB10
DDP/PB11
PC23
PA25/PGMD13
PA26/PGMD14
PC3
PA29
PA18/PGMD6/AD1
PA21/PGMD9/AD8
VDDCORE
PC27
PA30
PC10
PA12/PGMD0
PA11/PGMM3
PC2
PA3
VDDIO
PA2/PGMEN2
PC11
PC24
PA19/PGMD7/AD2
PC15/AD11
PA22/PGMD10/AD9
PC13/AD10
PA23/PGMD11
PB13/DAC0
PC25
PA10/PGMM2
GND
VDDIO
GND
GND
PA9/PGMM1
PC1
PC14
PB8/XOUT
PB9/PGMCK/XIN
PA1/PGMEN1
PA8/XOUT32/
PGMM0
23
PC12/AD12
48
73
PC16
98
VDDIO
PA7/XIN32/
24
25
PA20/PGMD8/AD3
PC0
49
50
74
75
PA0/PGMEN0
PC17
99
PB14/DAC1
VDDPLL
PGMNVALID
VDDIO
100
SAM3S [SUMMARY]
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6500ES–ATARM–11-Feb-13
4.1.4 100-ball TFBGA Pinout
Table 4-2. 100-ball TFBGA SAM3S4/2/1C Pinout
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
B1
B2
B3
B4
B5
B6
B7
B8
B9
PB1/AD5
PC29
C6
C7
C8
C9
C10
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
E1
E2
E3
E4
TCK/SWCLK/PB7
PC16
F1
F2
PA18/PGMD6/AD1
PC26
H6
H7
H8
H9
H10
J1
PC4
PA11/PGMM3
PC1
VDDIO
PA1/PGMEN1
PC17
F3
VDDOUT
GND
PB9/PGMCK/XIN
PB8/XOUT
PB13/DAC0
DDP/PB11
DDM/PB10
TMS/SWDIO/PB6
JTAGSEL
PC30
F4
PA6/PGMNOE
TDI/PB4
PA0/PGMEN0
PB3/AD7
PB0/AD4
PC24
F5
VDDIO
F6
PA27/PGMD15
PC8
PC15/AD11
PC0
F7
J2
F8
PA28
J3
PA16/PGMD4
PC6
PC22
F9
TST
J4
GND
F10
G1
G2
G3
G4
G5
G6
G7
G8
G9
PC9
J5
PA24/PGMD12
PA25/PGMD13
PA10/PGMM2
GND
GND
PA21/PGMD9/AD8
PC27
J6
ADVREF
GNDANA
PB14/DAC1
PC21
VDDCORE
PA2/PGMEN2
PC11
J7
PA15/PGMD3
VDDCORE
VDDCORE
PA26/PGMD14
PA12/PGMD0
PC28
J8
J9
VDDCORE
VDDIO
PC14
J10
K1
K2
K3
K4
PC20
PA17/PGMD5/AD0
PC31
PA22/PGMD10/AD9
PC13/AD10
PC12/AD12
PA20/PGMD8/AD3
PA31
PC19
VDDIN
PC18
GND
PA4/PGMNCMD
TDO/TRACESWO/
PB5
B10
E5
GND
G10
PA5/PGMRDY
K5
PC5
C1
C2
C3
C4
PB2/AD6
VDDPLL
PC25
E6
E7
E8
E9
NRST
PA29/AD13
PA30/AD14
PC10
H1
H2
H3
H4
PA19/PGMD7/AD2
PA23/PGMD11
PC7
K6
K7
K8
PC3
PC2
PA9/PGMM1
PC23
PA14/PGMD2
K9 PA8/XOUT32/PGMM0
PA7/XIN32/
K10
C5
ERASE/PB12
E10
PA3
H5
PA13/PGMD1
PGMNVALID
SAM3S [SUMMARY]
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6500ES–ATARM–11-Feb-13
4.2
SAM3S4/2/1B Package and Pinout
Figure 4-3. Orientation of the 64-pad QFN Package
64
1
49
48
16
17
33
32
TOP VIEW
Figure 4-4. Orientation of the 64-lead LQFP Package
48
33
49
32
64
17
1
16
SAM3S [SUMMARY]
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6500ES–ATARM–11-Feb-13
4.2.1 64-Lead LQFP and QFN Pinout
64-pin version SAM3S devices are pin-to-pin compatible with AT91SAM7S legacy products. Furthermore, SAM3S
products have new functionalities shown in italic in Table 4-3.
Table 4-3.
64-pin SAM3S4/2/1B Pinout
1
2
3
4
5
6
7
8
ADVREF
GND
17
18
19
20
21
22
23
24
GND
33
34
35
36
37
38
39
40
TDI/PB4
PA6/PGMNOE
PA5/PGMRDY
PA4/PGMNCMD
PA27/PGMD15
PA28
49
50
51
52
53
54
55
56
TDO/TRACESWO/PB5
JTAGSEL
VDDIO
PB0/AD4
PB1/AD5
PB2/AD6
PB3/AD7
VDDIN
PA16/PGMD4
PA15/PGMD3
PA14/PGMD2
PA13/PGMD1
PA24/PGMD12
VDDCORE
TMS/SWDIO/PB6
PA31
TCK/SWCLK/PB7
VDDCORE
NRST
ERASE/PB12
DDM/PB10
VDDOUT
TST
PA17/PGMD5/
9
25
26
PA25/PGMD13
PA26/PGMD14
41
42
PA29
PA30
57
58
DDP/PB11
VDDIO
AD0
PA18/PGMD6/
AD1
10
PA21/PGMD9/
AD8
11
12
13
27
28
29
PA12/PGMD0
PA11/PGMM3
PA10/PGMM2
43
44
45
PA3
59
60
61
PB13/DAC0
GND
VDDCORE
PA2/PGMEN2
VDDIO
PA19/PGMD7/
AD2
XOUT/PB8
PA22/PGMD10/
AD9
14
15
30
31
32
PA9/PGMM1
46
47
48
GND
62
63
64
XIN/PGMCK/PB9
PB14/DAC1
VDDPLL
PA8/XOUT32/
PA23/PGMD11
PA1/PGMEN1
PA0/PGMEN0
PGMM0
PA20/PGMD8/
AD3
PA7/XIN32/
16
PGMNVALID
Note:
The bottom pad of the QFN package must be connected to ground.
SAM3S [SUMMARY]
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6500ES–ATARM–11-Feb-13
4.3
SAM3S4/2/1A Package and Pinout
Figure 4-5. Orientation of the 48-pad QFN Package
48
37
1
36
25
12
13
24
TOP VIEW
Figure 4-6. Orientation of the 48-lead LQFP Package
36
25
37
24
13
48
1
12
SAM3S [SUMMARY]
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6500ES–ATARM–11-Feb-13
4.3.1 48-Lead LQFP and QFN Pinout
Table 4-4.
48-pin SAM3S4/2/1A Pinout
TDO/TRACESWO/
PB5
1
ADVREF
13
VDDIO
25
TDI/PB4
37
2
3
4
5
6
7
8
GND
14
15
16
17
18
19
20
PA16/PGMD4
PA15/PGMD3
PA14/PGMD2
PA13/PGMD1
VDDCORE
26
27
28
29
30
31
32
PA6/PGMNOE
PA5/PGMRDY
PA4/PGMNCMD
NRST
38
39
40
41
42
43
44
JTAGSEL
TMS/SWDIO/PB6
TCK/SWCLK/PB7
VDDCORE
PB0/AD4
PB1/AD5
PB2/AD6
PB3/AD7
VDDIN
TST
ERASE/PB12
DDM/PB10
PA12/PGMD0
PA11/PGMM3
PA3
VDDOUT
PA2/PGMEN2
DDP/PB11
PA17/PGMD5/
AD0
9
21
22
23
24
PA10/PGMM2
PA9/PGMM1
33
34
35
36
VDDIO
GND
45
46
47
48
XOUT/PB8
XIN/PB9/PGMCK
VDDIO
PA18/PGMD6/
AD1
10
11
PA19/PGMD7/
AD2
PA8/XOUT32/
PA1/PGMEN1
PA0/PGMEN0
PGMM0
PA7/XIN32/
12
PA20/AD3
VDDPLL
PGMNVALID
Note:
The bottom pad of the QFN package must be connected to ground.
SAM3S [SUMMARY]
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6500ES–ATARM–11-Feb-13
5.
Power Considerations
5.1
Power Supplies
The SAM3S product has several types of power supply pins:
z
z
z
z
VDDCORE pins: Power the core, the embedded memories and the peripherals; voltage ranges from 1.62V and
1.95V.
VDDIO pins: Power the Peripherals I/O lines (Input/Output Buffers); USB transceiver; Backup part, 32kHz crystal
oscillator and oscillator pads; ranges from 1.62V and 3.6V
VDDIN pin: Voltage Regulator Input, ADC, DAC and Analog Comparator Power Supply; Voltage ranges from 1.8V
to 3.6V
VDDPLL pin: Powers the PLLA, PLLB, the Fast RC and the 3 to 20 MHz oscillator; voltage ranges from 1.62V and
1.95V.
5.2
Voltage Regulator
The SAM3S embeds a voltage regulator that is managed by the Supply Controller.
This internal regulator is intended to supply the internal core of SAM3S. It features two different operating modes:
z
In Normal mode, the voltage regulator consumes less than 700 μA static current and draws 80 mA of output
current. Internal adaptive biasing adjusts the regulator quiescent current depending on the required load current.
In Wait Mode quiescent current is only 7 μA.
• In Backup mode, the voltage regulator consumes less than 1 μA while its output (VDDOUT) is driven internally to GND.
The default output voltage is 1.80V and the start-up time to reach Normal mode is inferior to 100 μs.
For adequate input and output power supply decoupling/bypassing, refer to the Voltage Regulator section in the
Electrical Characteristics section of the datasheet.
5.3
Typical Powering Schematics
The SAM3S supports a 1.62V-3.6V single supply mode. The internal regulator input connected to the source and its
output feeds VDDCORE. Figure 5-1 shows the power schematics.
As VDDIN powers the voltage regulator, the ADC/DAC and the analog comparator, when the user does not want to use
the embedded voltage regulator, it can be disabled by software via the SUPC (note that it is different from Backup mode).
Figure 5-1. Single Supply
VDDIO
USB
Transceivers.
Main Supply
(1.8V-3.6V)
ADC, DAC
Analog Comp.
VDDIN
VDDOUT
Voltage
Regulator
VDDCORE
VDDPLL
Note: For USB, VDDIO needs to be greater than 3.0V.
For ADC, VDDIN needs to be greater than 2.0V.
For DAC, VDDIN needs to be greater than 2.4V.
SAM3S [SUMMARY]
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6500ES–ATARM–11-Feb-13
Figure 5-2. Core Externally Supplied
Main Supply
(1.62V-3.6V)
VDDIO
VDDIN
USB
Transceivers.
Can be the
same supply
ADC, DAC
Analog Comp.
ADC, DAC, Analog
Comparator Supply
(2.0V-3.6V)
VDDOUT
Voltage
Regulator
VDDCORE
VDDCORE Supply
(1.62V-1.95V)
VDDPLL
Note: For USB, VDDIO needs to be greater than 3.0V.
For ADC, VDDIN needs to be greater than 2.0V
For DAC, VDDIN needs to be greater than 2.4V.
Figure 5-3 below provides an example of the powering scheme when using a backup battery. Since the PIO state is
preserved when in backup mode, any free PIO line can be used to switch off the external regulator by driving the PIO line
at low level (PIO is input, pull-up enabled after backup reset). External wake-up of the system can be from a push button
or any signal. See Section 5.6 “Wake-up Sources” for further details.
Figure 5-3. Backup Battery
ADC, DAC, Analog
Comparator Supply
(2.0V-3.6V)
VDDIO
USB
Transceivers.
Backup
Battery
ADC, DAC
Analog Comp.
-
VDDIN
Main Supply
VDDOUT
IN
OUT
Voltage
Regulator
3.3V
LDO
VDDCORE
VDDPLL
ON/OFF
PIOx (Output)
WAKEUPx
External wakeup signal
Note: The two diodes provide a “switchover circuit” (for illustration purpose)
between the backup battery and the main supply when the system is put in
backup mode.
SAM3S [SUMMARY]
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6500ES–ATARM–11-Feb-13
5.4
Active Mode
Active mode is the normal running mode with the core clock running from the fast RC oscillator, the main crystal oscillator
or the PLLA. The power management controller can be used to adapt the frequency and to disable the peripheral clocks.
5.5
Low Power Modes
The various low power modes of the SAM3S are described below:
5.5.1 Backup Mode
The purpose of backup mode is to achieve the lowest power consumption possible in a system which is performing
periodic wake-ups to perform tasks but not requiring fast startup time (<0.1ms). Total current consumption is 3 μA typical.
The Supply Controller, zero-power power-on reset, RTT, RTC, Backup registers and 32 kHz oscillator (RC or crystal
oscillator selected by software in the Supply Controller) are running. The regulator and the core supply are off.
Backup mode is based on the Cortex-M3 deepsleep mode with the voltage regulator disabled.
The SAM3S can be awakened from this mode through WUP0-15 pins, the supply monitor (SM), the RTT or RTC wake-
up event.
Backup mode is entered by using WFE instructions with the SLEEPDEEP bit in the System Control Register of the
Cortex-M3 set to 1. (See the Power management description in The ARM Cortex M3 Processor section of the
product datasheet).
Exit from Backup mode happens if one of the following enable wake up events occurs:
• WKUPEN0-15 pins (level transition, configurable debouncing)
• Supply Monitor alarm
• RTC alarm
• RTT alarm
5.5.2 Wait Mode
The purpose of the wait mode is to achieve very low power consumption while maintaining the whole device in a
powered state for a startup time of less than 10 µs. Current Consumption in Wait mode is typically 15 µA (total cur-
rent consumption) if the internal voltage regulator is used or 8 µA if an external regulator is used.
In this mode, the clocks of the core, peripherals and memories are stopped. However, the core, peripherals and
memories power supplies are still powered. From this mode, a fast start up is available.
This mode is entered via Wait for Event (WFE) instructions with LPM = 1 (Low Power Mode bit in PMC_FSMR).
The Cortex-M3 is able to handle external events or internal events in order to wake-up the core (WFE). This is
done by configuring the external lines WUP0-15 as fast startup wake-up pins (refer to Section 5.7 “Fast Startup”).
RTC or RTT Alarm and USB wake-up events can be used to wake up the CPU (exit from WFE).
Entering Wait Mode:
• Select the 4/8/12 MHz fast RC oscillator as Main Clock
• Set the LPM bit in the PMC Fast Startup Mode Register (PMC_FSMR)
• Execute the Wait-For-Event (WFE) instruction of the processor
Note: Internal Main clock resynchronization cycles are necessary between the writing of MOSCRCEN bit and the
effective entry in Wait mode. Depending on the user application, Waiting for MOSCRCEN bit to be cleared is
recommended to ensure that the core will not execute undesired instructions.
The bit MOSCRCEN should be automatically set to '0'. So you have to add after this instruction the following: while
(MOSCRCEN ==0); so that you are sure to stay in the loop until you awake from the wait mode. In that case you are sure
the core will not continue to fetch the code but once you have exited the wait mode (in that case MOSCRCEN will be
automatically set to '1').
SAM3S [SUMMARY]
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6500ES–ATARM–11-Feb-13
5.5.3 Sleep Mode
The purpose of sleep mode is to optimize power consumption of the device versus response time. In this mode,
only the core clock is stopped. The peripheral clocks can be enabled. The current consumption in this mode is
application dependent.
This mode is entered via Wait for Interrupt (WFI) or Wait for Event (WFE) instructions with LPM = 0 in PMC_FSMR.
The processor can be woke up from an interrupt if WFI instruction of the Cortex M3 is used, or from an event if the
WFE instruction is used to enter this mode.
5.5.4 Low Power Mode Summary Table
The modes detailed above are the main low power modes. Each part can be set to on or off separately and wake
up sources can be individually configured. Table 5-1 below shows a summary of the configurations of the low
power modes.
Table 5-1. Low Power Mode Configuration Summary
SUPC,
32 kHz
Oscillator
RTC RTT
Backup
Registers,
Core
POR
(Backup
Region)
PIO State
Memory
Potential Wake Up Core at while in Low PIOStateat Consumption Wake-up
(2) (3)
Mode
Regulator Peripherals Mode Entry
Sources
Wake Up Power Mode Wake Up
Time(1)
PIOA &
PIOB &
PIOC
Inputs with
pull ups
WUP0-15 pins
SM alarm
RTC alarm
RTT alarm
WFE
OFF
Backup
Mode
Previous
state saved
ON
ON
OFF
Reset
3 μA typ(4)
< 0.1 ms
+SLEEPDEEP
(Not powered)
bit = 1
Any Event from:
Fast startup through
+SLEEPDEEP WUP0-15 pins
WFE
Powered
Wait
Mode
Clocked Previous
back state saved
ON
Unchanged 5 μA/15 μA (5) < 10 μs
bit = 0
RTC alarm
RTT alarm
USB wake-up
(Not clocked)
+LPM bit = 1
Entry mode =WFI
Interrupt Only; Entry
mode =WFE Any
Enabled Interrupt
and/or Any Event
from: Fast start-up
through WUP0-15
pins
WFE or WFI
Powered(7)
Sleep
Mode
+SLEEPDEEP
bit = 0
Clocked Previous
back state saved
(6)
(6)
ON
ON
Unchanged
(Not clocked)
+LPM bit = 0
RTC alarm
RTT alarm
USB wake-up
Notes: 1. When considering wake-up time, the time required to start the PLL is not taken into account. Once started, the device
works with the 4/8/12 MHz fast RC oscillator. The user has to add the PLL start-up time if it is needed in the system.
The wake-up time is defined as the time taken for wake up until the first instruction is fetched.
2. The external loads on PIOs are not taken into account in the calculation.
3. Supply Monitor current consumption is not included.
4. Total Current consumption.
5. 5 μA on VDDCORE, 15 μA for total current consumption (using internal voltage regulator), 8 μA for total current con-
sumption (without using internal voltage regulator).
6. Depends on MCK frequency.
7. In this mode the core is supplied and not clocked but some peripherals can be clocked.
SAM3S [SUMMARY]
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6500ES–ATARM–11-Feb-13
5.6
Wake-up Sources
The wake-up events allow the device to exit the backup mode. When a wake-up event is detected, the Supply Controller
performs a sequence which automatically reenables the core power supply and the SRAM power supply, if they are not
already enabled.
Figure 5-4. Wake-up Source
SMEN
sm_out
RTCEN
rtc_alarm
Core
Supply
Restart
RTTEN
rtt_alarm
WKUPT0
WKUPEN0
WKUPEN1
WKUPIS0
WKUPIS1
Falling/Rising
Edge
Detector
WKUP0
WKUP1
WKUPDBC
Debouncer
SLCK
WKUPS
WKUPT1
Falling/Rising
Edge
Detector
WKUPT15
WKUPEN15
WKUPIS15
Falling/Rising
Edge
WKUP15
Detector
SAM3S [SUMMARY]
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6500ES–ATARM–11-Feb-13
5.7
Fast Startup
The device allows the processor to restart in a few microseconds while the processor is in wait mode. A fast start up can
occur upon detection of a low level on one of the 19 wake-up inputs (WKUP0 to 15 + SM + RTC + RTT).
The fast restart circuitry, as shown in Figure 5-5, is fully asynchronous and provides a fast start-up signal to the Power
Management Controller. As soon as the fast start-up signal is asserted, the PMC automatically restarts the embedded
4/8/12 MHz fast RC oscillator, switches the master clock on this 4MHz clock and reenables the processor clock.
Figure 5-5. Fast Start-Up Circuitry
FSTT0
WKUP0
FSTP0
FSTP1
FSTT1
WKUP1
FSTT15
WKUP15
fast_restart
FSTP15
RTTAL
RTCAL
USBAL
RTT Alarm
RTC Alarm
USB Alarm
SAM3S [SUMMARY]
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6500ES–ATARM–11-Feb-13
6.
Input/Output Lines
The SAM3S has several kinds of input/output (I/O) lines such as general purpose I/Os (GPIO) and system I/Os. GPIOs
can have alternate functionality due to multiplexing capabilities of the PIO controllers. The same PIO line can be used
whether in IO mode or by the multiplexed peripheral. System I/Os include pins such as test pins, oscillators, erase or
analog inputs.
6.1
General Purpose I/O Lines
GPIO Lines are managed by PIO Controllers. All I/Os have several input or output modes such as pull-up or pull-down,
input Schmitt triggers, multi-drive (open-drain), glitch filters, debouncing or input change interrupt. Programming of these
modes is performed independently for each I/O line through the PIO controller user interface. For more details, refer to
the product PIO controller section.
The input output buffers of the PIO lines are supplied through VDDIO power supply rail.
The SAM3S embeds high speed pads able to handle up to 32 MHz for HSMCI (MCK/2), 45 MHz for SPI clock lines and
35 MHz on other lines. See AC Characteristics Section in the Electrical Characteristics Section of the datasheet for more
details. Typical pull-up and pull-down value is 100 kΩ for all I/Os.
Each I/O line also embeds an ODT (On-Die Termination), see Figure 6-1. It consists of an internal series resistor
termination scheme for impedance matching between the driver output (SAM3S) and the PCB trace impedance
preventing signal reflection. The series resistor helps to reduce IOs switching current (di/dt) thereby reducing in turn,
EMI. It also decreases overshoot and undershoot (ringing) due to inductance of interconnect between devices or
between boards. In conclusion ODT helps diminish signal integrity issues.
Figure 6-1. On-Die Termination
Z0 ~ Zout + Rodt
ODT
36 Ohms Typ.
Rodt
Receiver
SAM3 Driver with
PCB Trace
Zout ~ 10 Ohms
Z0 ~ 50 Ohms
6.2
System I/O Lines
System I/O lines are pins used by oscillators, test mode, reset and JTAG to name but a few. Described below are the
SAM3S system I/O lines shared with PIO lines:
These pins are software configurable as general purpose I/O or system pins. At startup the default function of these pins
is always used.
SAM3S [SUMMARY]
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6500ES–ATARM–11-Feb-13
Table 6-1. System I/O Configuration List
SYSTEM_IO
bit number
Default function
after reset
Constraints for
normal start
Other function
Configuration
Low Level at
startup(1)
12
ERASE
PB12
10
11
7
6
5
4
-
DDM
DDP
PB10
PB11
PB7
-
-
-
-
-
-
-
-
-
-
In Matrix User Interface Registers
(Refer to the SystemIO
Configuration Register in the Bus
Matrix section of the product
datasheet.)
TCK/SWCLK
TMS/SWDIO
TDO/TRACESWO
TDI
PB6
PB5
PB4
PA7
XIN32
XOUT32
XIN
See footnote (2) below
See footnote (3) below
-
PA8
-
PB9
-
PB8
XOUT
Notes: 1. If PB12 is used as PIO input in user applications, a low level must be ensured at startup to prevent Flash erase before
the user application sets PB12 into PIO mode,
2. In the product Datasheet Refer to: Slow Clock Generator of the Supply Controller section.
3. In the product Datasheet Refer to: 3 to 20 MHZ Crystal Oscillator information in PMC section.
6.2.1 Serial Wire JTAG Debug Port (SWJ-DP) Pins
The SWJ-DP pins are TCK/SWCLK, TMS/SWDIO, TDO/SWO, TDI and commonly provided on a standard 20-pin JTAG
connector defined by ARM. For more details about voltage reference and reset state, refer to Table 3-1 on page 7.
At startup, SWJ-DP pins are configured in SWJ-DP mode to allow connection with debugging probe. Please refer to the
Debug and Test Section of the product datasheet.
SWJ-DP pins can be used as standard I/Os to provide users more general input/output pins when the debug port is not
needed in the end application. Mode selection between SWJ-DP mode (System IO mode) and general IO mode is
performed through the AHB Matrix Special Function Registers (MATRIX_SFR). Configuration of the pad for pull-up,
triggers, debouncing and glitch filters is possible regardless of the mode.
The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It integrates a permanent
pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations.
By default, the JTAG Debug Port is active. If the debugger host wants to switch to the Serial Wire Debug Port, it must
provide a dedicated JTAG sequence on TMS/SWDIO and TCK/SWCLK which disables the JTAG-DP and enables the
SW-DP. When the Serial Wire Debug Port is active, TDO/TRACESWO can be used for trace.
The asynchronous TRACE output (TRACESWO) is multiplexed with TDO. So the asynchronous trace can only be used
with SW-DP, not JTAG-DP. For more information about SW-DP and JTAG-DP switching, please refer to the Debug and
Test Section.
6.3
Test Pin
The TST pin is used for JTAG Boundary Scan Manufacturing Test or Fast Flash programming mode of the SAM3S
series. The TST pin integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left uncon-
nected for normal operations. To enter fast programming mode, see the Fast Flash Programming Interface (FFPI)
section. For more on the manufacturing and test mode, refer to the “Debug and Test” section of the product
datasheet.
SAM3S [SUMMARY]
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6500ES–ATARM–11-Feb-13
6.4
6.5
NRST Pin
The NRST pin is bidirectional. It is handled by the on-chip reset controller and can be driven low to provide a reset signal
to the external components or asserted low externally to reset the microcontroller. It will reset the Core and the
peripherals except the Backup region (RTC, RTT and Supply Controller). There is no constraint on the length of the reset
pulse and the reset controller can guarantee a minimum pulse length. The NRST pin integrates a permanent pull-up
resistor to VDDIO of about 100 kΩ. By default, the NRST pin is configured as an input.
ERASE Pin
The ERASE pin is used to reinitialize the Flash content (and some of its NVM bits) to an erased state (all bits read as
logic level 1). It integrates a pull-down resistor of about 100 kΩ to GND, so that it can be left unconnected for normal
operations.
This pin is debounced by SCLK to improve the glitch tolerance. When the ERASE pin is tied high during less than 100
ms, it is not taken into account. The pin must be tied high during more than 220 ms to perform a Flash erase operation.
The ERASE pin is a system I/O pin and can be used as a standard I/O. At startup, the ERASE pin is not configured as a
PIO pin. If the ERASE pin is used as a standard I/O, startup level of this pin must be low to prevent unwanted erasing.
Please refer to Section 11.2 “Peripheral Signal Multiplexing on I/O Lines” on page 41. Also, if the ERASE pin is used as
a standard I/O output, asserting the pin to low does not erase the Flash.
SAM3S [SUMMARY]
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6500ES–ATARM–11-Feb-13
7.
Processor and Architecture
7.1
ARM Cortex-M3 Processor
z
z
z
z
z
z
z
z
z
Version 2.0
Thumb-2 (ISA) subset consisting of all base Thumb-2 instructions, 16-bit and 32-bit
Harvard processor architecture enabling simultaneous instruction fetch with data load/store
Three-stage pipeline
Single cycle 32-bit multiply
Hardware divide
Thumb and Debug states
Handler and Thread modes
Low latency ISR entry and exit
7.2
7.3
APB/AHB bridge
The SAM3S product embeds one peripheral bridge:
The peripherals of the bridge are clocked by MCK.
Matrix Masters
The Bus Matrix of the SAM3S product manages 4 masters, which means that each master can perform an access
concurrently with others, to an available slave.
Each master has its own decoder, which is defined specifically for each master. In order to simplify the addressing, all the
masters have the same decodings.
Table 7-1. List of Bus Matrix Masters
Master 0
Master 1
Master 2
Master 3
Cortex-M3 Instruction/Data
Cortex-M3 System
Peripheral DMA Controller (PDC)
CRC Calculation Unit
7.4
Matrix Slaves
The Bus Matrix of the SAM3S product manages 5 slaves. Each slave has its own arbiter, allowing a different arbitration
per slave.
Table 7-2. List of Bus Matrix Slaves
Slave 0
Slave 1
Slave 2
Slave 3
Slave 4
Internal SRAM
Internal ROM
Internal Flash
External Bus Interface
Peripheral Bridge
SAM3S [SUMMARY]
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6500ES–ATARM–11-Feb-13
7.5
Master to Slave Access
All the Masters can normally access all the Slaves. However, some paths do not make sense, for example allowing
access from the Cortex-M3 S Bus to the Internal ROM. Thus, these paths are forbidden or simply not wired and shown
as “-” in the following table.
Table 7-3. SAM3S Master to Slave Access
Masters
0
1
2
3
Cortex-M3 I/D
Bus
Cortex-M3 S
Bus
PDC
CRCCU
Slaves
0
1
2
3
4
Internal SRAM
Internal ROM
Internal Flash
-
X
X
-
X
-
X
X
-
X
X
X
X
-
-
External Bus Interface
Peripheral Bridge
X
X
X
X
-
7.6
Peripheral DMA Controller
z
Handles data transfer between peripherals and memories
z
Low bus arbitration overhead
z
z
One Master Clock cycle needed for a transfer from memory to peripheral
Two Master Clock cycles needed for a transfer from peripheral to memory
z
Next Pointer management for reducing interrupt latency requirement
The Peripheral DMA Controller handles transfer requests from the channel according to the following priorities (Low to
High priorities):
Table 7-4. Peripheral DMA Controller
Instance Name
PWM
Channel T/R
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Receive
Receive
Receive
Receive
100 & 64 Pins
48 Pins
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
TWI1
TWI0
x
UART1
UART0
USART1
USART0
DAC
x
x
N/A
x
N/A
x
SPI
SSC
x
HSMCI
PIOA
N/A
x
TWI1
x
TWI0
x
UART1
UART0
N/A
x
SAM3S [SUMMARY]
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6500ES–ATARM–11-Feb-13
Table 7-4. Peripheral DMA Controller (Continued)
Instance Name
USART1
USART0
ADC
Channel T/R
Receive
Receive
Receive
Receive
Receive
Receive
Receive
100 & 64 Pins
48 Pins
x
x
x
x
x
x
x
x
x
x
SPI
x
SSC
x
HSMCI
PIOA
N/A
x
7.7
Debug and Test Features
z
Debug access to all memory and registers in the system, including Cortex-M3 register bank when the core is
running, halted, or held in reset.
z
z
z
z
z
Serial Wire Debug Port (SW-DP) and Serial Wire JTAG Debug Port (SWJ-DP) debug access
Flash Patch and Breakpoint (FPB) unit for implementing breakpoints and code patches
Data Watchpoint and Trace (DWT) unit for implementing watchpoints, data tracing, and system profiling
Instrumentation Trace Macrocell (ITM) for support of printf style debugging
IEEE1149.1 JTAG Boundary-can on All Digital Pins
SAM3S [SUMMARY]
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6500ES–ATARM–11-Feb-13
8.
Product Mapping
Figure 8-1. SAM3S Product Mapping
Address memory space
Code
Peripherals
HSMCI
Code
0x40000000
0x40004000
0x40008000
0x4000C000
0x40010000
+0x40
0x00000000
0x20000000
0x00000000
Boot Memory
18
22
21
0x00400000
SSC
SPI
Internal Flash
0x00800000
SRAM
Internal ROM
1 MByte
bit band
region
0x22000000
0x23FFFFFF
0x00C00000
0x1FFFFFFF
Reserved
TC0
Reserved
Undefined
TC0
TC0
TC0
TC1
TC1
TC1
0x24000000
0x40000000
32 MBytes
bit band alias
23
24
25
26
27
28
19
20
31
14
15
TC1
+0x80
Peripherals
TC2
External RAM
0x60000000
0x61000000
0x60000000
0xA0000000
0x40014000
+0x40
TC3
SMC Chip Select 0
SMC Chip Select 1
External SRAM
TC4
0x62000000
0x63000000
0x64000000
+0x80
Reserved
System
SMC Chip Select 2
TC5
0x40018000
0x4001C000
0x40020000
0x40024000
0x40028000
0x4002C000
0x40030000
0x40034000
0x40038000
0x4003C000
0x40040000
0x40044000
0x40048000
0x400E0000
0xE0000000
0xFFFFFFFF
SMC Chip Select 3
Reserved
TWI0
0x9FFFFFFF
TWI1
1 MByte
bit band
regiion
System Controller
PWM
0x400E0000
0x400E0200
0x400E0400
0x400E0600
0x400E0740
0x400E0800
0x400E0A00
0x400E0C00
0x400E0E00
0x400E1000
0x400E1200
0x400E1400
SMC
USART0
USART1
Reserved
Reserved
UDP
10
MATRIX
offset
block
peripheral
ID
PMC
5
UART0
8
CHIPID
33
29
30
34
35
UART1
ADC
9
EFC
DACC
ACC
6
Reserved
PIOA
CRCCU
Reserved
11
PIOB
12
PIOC
System Controller
Reserved
13
0x400E2600
0x40100000
RSTC
1
+0x10
+0x30
+0x50
+0x60
+0x90
SUPC
Reserved
0x40200000
0x40400000
RTT
32 MBytes
bit band alias
3
WDT
Reserved
4
0x60000000
RTC
2
GPBR
0x400E1600
0x4007FFFF
Reserved
SAM3S [SUMMARY]
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6500ES–ATARM–11-Feb-13
9.
Memories
9.1
Embedded Memories
9.1.1 Internal SRAM
The ATSAM3S4 product (256-Kbyte internal Flash version) embeds a total of 48 Kbytes high-speed SRAM.
The ATSAM3S2 product (128-Kbyte internal Flash version) embeds a total of 32 Kbytes high-speed SRAM.
The ATSAM3S1 product (64-Kbyte internal Flash version) embeds a total of 16 Kbytes high-speed SRAM.
The SRAM is accessible over System Cortex-M3 bus at address 0x2000 0000.
The SRAM is in the bit band region. The bit band alias region is mapped from 0x2200 0000 to 0x23FF FFFF.
9.1.2 Internal ROM
The SAM3S product embeds an Internal ROM, which contains the SAM Boot Assistant (SAM-BA), In Application
Programming routines (IAP) and Fast Flash Programming Interface (FFPI).
At any time, the ROM is mapped at address 0x0080 0000.
9.1.3 Embedded Flash
9.1.3.1 Flash Overview
The Flash of the ATSAM3S4 (256-Kbytes internal Flash version) is organized in one bank of 1024 pages (Single plane)
of 256 bytes.
The Flash of the ATSAM3S2 (128-Kbytes internal Flash version) is organized in one bank of 512 pages (Single plane) of
256 bytes.
The Flash of the ATSAM3S1 (64-Kbytes internal Flash version) is organized in one bank of 256 pages (Single plane) of
256 bytes.
The Flash contains a 128-byte write buffer, accessible through a 32-bit interface.
9.1.3.2 Flash Power Supply
The Flash is supplied by VDDCORE.
9.1.3.3 Enhanced Embedded Flash Controller
The Enhanced Embedded Flash Controller (EEFC) manages accesses performed by the masters of the system. It
enables reading the Flash and writing the write buffer. It also contains a User Interface, mapped on the APB.
The Enhanced Embedded Flash Controller ensures the interface of the Flash block with the 32-bit internal bus. Its 128-bit
wide memory interface increases performance.
The user can choose between high performance or lower current consumption by selecting either 128-bit or 64-bit
access. It also manages the programming, erasing, locking and unlocking sequences of the Flash using a full set of
commands.
One of the commands returns the embedded Flash descriptor definition that informs the system about the Flash
organization, thus making the software generic.
9.1.3.4 Flash Speed
The user needs to set the number of wait states depending on the frequency used.
For more details, refer to the AC Characteristics sub section in the product Electrical Characteristics Section.
SAM3S [SUMMARY]
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6500ES–ATARM–11-Feb-13
9.1.3.5 Lock Regions
Several lock bits used to protect write and erase operations on lock regions. A lock region is composed of several
consecutive pages, and each lock region has its associated lock bit.
Table 9-1. Number of Lock Bits
Product
Number of Lock Bits
Lock Region Size
16 kbytes (64 pages)
16 kbytes (64 pages)
16 kbytes (64 pages)
ATSAM3S4
ATSAM3S2
ATSAM3S1
16
8
4
If a locked-region’s erase or program command occurs, the command is aborted and the EEFC triggers an interrupt.
The lock bits are software programmable through the EEFC User Interface. The command “Set Lock Bit” enables the
protection. The command “Clear Lock Bit” unlocks the lock region.
Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.
9.1.3.6 Security Bit Feature
The SAM3S features a security bit, based on a specific General Purpose NVM bit (GPNVM bit 0). When the security is
enabled, any access to the Flash, SRAM, Core Registers and Internal Peripherals either through the ICE interface or
through the Fast Flash Programming Interface, is forbidden. This ensures the confidentiality of the code programmed in
the Flash.
This security bit can only be enabled, through the command “Set General Purpose NVM Bit 0” of the EEFC User
Interface. Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and after a full Flash erase is
performed. When the security bit is deactivated, all accesses to the Flash, SRAM, Core registers, Internal Peripherals
are permitted.
It is important to note that the assertion of the ERASE pin should always be longer than 200 ms.
As the ERASE pin integrates a permanent pull-down, it can be left unconnected during normal operation. However, it is
safer to connect it directly to GND for the final application.
9.1.3.7 Calibration Bits
NVM bits are used to calibrate the brownout detector and the voltage regulator. These bits are factory configured and
cannot be changed by the user. The ERASE pin has no effect on the calibration bits.
9.1.3.8 Unique Identifier
Each device integrates its own 128-bit unique identifier. These bits are factory configured and cannot be changed by the
user. The ERASE pin has no effect on the unique identifier.
9.1.3.9 Fast Flash Programming Interface
The Fast Flash Programming Interface allows programming the device through a multiplexed fully-handshaked parallel
port. It allows gang programming with market-standard industrial programmers.
The FFPI supports read, page program, page erase, full erase, lock, unlock and protect commands.
The Fast Flash Programming Interface is enabled and the Fast Programming Mode is entered when TST is tied high and
PA0 and PA1 are tied low.
9.1.3.10 SAM-BA® Boot
The SAM-BA Boot is a default Boot Program which provides an easy way to program in-situ the on-chip Flash memory.
The SAM-BA Boot Assistant supports serial communication via the UART and USB.
The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI).
SAM3S [SUMMARY]
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6500ES–ATARM–11-Feb-13
9.1.3.11 GPNVM Bits
The SAM3S features two GPNVM bits that can be cleared or set respectively through the commands “Clear GPNVM Bit”
and “Set GPNVM Bit” of the EEFC User Interface.
Table 9-2. General Purpose Non-volatile Memory Bits
GPNVMBit[#]
Function
0
1
Security bit
Boot mode selection
9.1.4 Boot Strategies
The system always boots at address 0x0. To ensure maximum boot possibilities, the memory layout can be changed via
GPNVM.
A general-purpose NVM (GPNVM) bit is used to boot either on the ROM (default) or from the Flash.
The GPNVM bit can be cleared or set respectively through the commands “Clear General-purpose NVM Bit” and “Set
General-purpose NVM Bit” of the EEFC User Interface.
Setting GPNVM Bit 1 selects the boot from the Flash, clearing it selects the boot from the ROM. Asserting ERASE clears
the GPNVM Bit 1 and thus selects the boot from the ROM by default.
9.2
External Memories
The SAM3S features an External Bus Interface to provide the interface to a wide range of external memories and to any
parallel peripheral.
9.2.1 Static Memory Controller
z
z
z
z
8-bit Data Bus
Up to 24-bit Address Bus (up to 16 MBytes linear per chip select)
Up to 4 chip selects, Configurable Assignment
Multiple Access Modes supported
z
z
Chip Select, Write enable or Read enable Control Mode
Asynchronous read in Page Mode supported (4- up to 32-byte page size)
z
z
Multiple device adaptability
Control signals programmable setup, pulse and hold time for each Memory Bank
Multiple Wait State Management
z
z
z
z
Programmable Wait State Generation
External Wait Request
Programmable Data Float Time
z
z
Slow Clock mode supported
Additional Logic for NAND Flash
SAM3S [SUMMARY]
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6500ES–ATARM–11-Feb-13
10. System Controller
The System Controller is a set of peripherals, which allow handling of key elements of the system, such as power, resets,
clocks, time, interrupts, watchdog, etc...
See the system controller block diagram in Figure 10-1 on page 34.
Figure 10-1. System Controller Block Diagram
VDDIO
VDDOUT
vr_on
vr_mode
Software Controlled
Voltage Regulator
VDDIN
VDDIO
Supply
Controller
Zero-Power
Power-on Reset
PIOA/B/C
Input/Output Buffers
PIOx
ON
out
Supply
Monitor
(Backup)
Analog
Comparator
WKUP0 - WKUP15
ADx
General Purpose
Backup Registers
ADC Analog
Circuitry
ADVREF
DACx
rtc_nreset
rtc_alarm
DAC Analog
Circuitry
SLCK
SLCK
RTC
VDDIO
rtt_nreset
rtt_alarm
RTT
DDP
DDM
USB
Transeivers
osc32k_xtal_en
XTALSEL
vddcore_nreset
XIN32
Xtal 32 kHz
Slow Clock
SLCK
bod_core_on
Brownout
Detector
(Core)
Oscillator
XOUT32
lcore_brown_out
VDDCORE
Embedded
32 kHz RC
Oscillator
osc32k_rc_en
SRAM
vddcore_nreset
Backup Power Supply
Peripherals
proc_nreset
periph_nreset
ice_nreset
Reset
Controller
Matrix
Peripheral
Bridge
NRST
Cortex-M3
Flash
FSTT0 - FSTT15
SLCK
Main Clock
Embedded
12 / 8 / 4 MHz
RC
Oscillator
MAINCK
Power
Management
Controller
Master Clock
MCK
XIN
3 - 20 MHz
XTAL Oscillator
XOUT
PLLACK
PLLBCK
MAINCK
MAINCK
PLLA
PLLB
Watchdog
Timer
SLCK
VDDIO
Core Power Supply
FSTT0 - FSTT15 are possible Fast Startup Sources, generated by WKUP0-WKUP15 Pins,
but are not physical pins.
SAM3S [SUMMARY]
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6500ES–ATARM–11-Feb-13
10.1 System Controller and Peripheral Mapping
Please refer to Section 8-1 “SAM3S Product Mapping” on page 30.
All the peripherals are in the bit band region and are mapped in the bit band alias region.
10.2 Power-on-Reset, Brownout and Supply Monitor
The SAM3S embeds three features to monitor, warn and/or reset the chip:
• Power-on-Reset on VDDIO
• Brownout Detector on VDDCORE
• Supply Monitor on VDDIO
10.2.1 Power-on-Reset
The Power-on-Reset monitors VDDIO. It is always activated and monitors voltage at start up but also during power down.
If VDDIO goes below the threshold voltage, the entire chip is reset. For more information, refer to the Electrical
Characteristics section of the datasheet.
10.2.2 Brownout Detector on VDDCORE
The Brownout Detector monitors VDDCORE. It is active by default. It can be deactivated by software through the Supply
Controller (SUPC_MR). It is especially recommended to disable it during low-power modes such as wait or sleep modes.
If VDDCORE goes below the threshold voltage, the reset of the core is asserted. For more information, refer to the
Supply Controller (SUPC) and Electrical Characteristics sections of the datasheet.
10.2.3 Supply Monitor on VDDIO
The Supply Monitor monitors VDDIO. It is not active by default. It can be activated by software and is fully programmable
with 16 steps for the threshold (between 1.9V to 3.4V). It is controlled by the Supply Controller (SUPC). A sample mode
is possible. It allows to divide the supply monitor power consumption by a factor of up to 2048. For more information,
refer to the SUPC and Electrical Characteristics sections of the datasheet.
10.3 Reset Controller
The Reset Controller is based on a Power-on-Reset cell, and a Supply Monitor on VDDCORE.
The Reset Controller is capable to return to the software the source of the last reset, either a general reset, a wake-up
reset, a software reset, a user reset or a watchdog reset.
The Reset Controller controls the internal resets of the system and the NRST pin input/output. It is capable to shape a
reset signal for the external devices, simplifying to a minimum connection of a push-button on the NRST pin to implement
a manual reset.
The configuration of the Reset Controller is saved as supplied on VDDIO.
10.4 Supply Controller (SUPC)
The Supply Controller controls the power supplies of each section of the processor and the peripherals (via Voltage
regulator control)
The Supply Controller has its own reset circuitry and is clocked by the 32 kHz Slow clock generator.
The reset circuitry is based on a zero-power power-on reset cell and a brownout detector cell. The zero-power power-on
reset allows the Supply Controller to start properly, while the software-programmable brownout detector allows detection
of either a battery discharge or main voltage loss.
The Slow Clock generator is based on a 32 kHz crystal oscillator and an embedded 32 kHz RC oscillator. The Slow Clock
defaults to the RC oscillator, but the software can enable the crystal oscillator and select it as the Slow Clock source.
SAM3S [SUMMARY]
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6500ES–ATARM–11-Feb-13
The Supply Controller starts up the device by sequentially enabling the internal power switches and the Voltage
Regulator, then it generates the proper reset signals to the core power supply.
It also enables to set the system in different low power modes and to wake it up from a wide range of events.
10.5 Clock Generator
The Clock Generator is made up of:
z
z
z
z
One Low Power 32768Hz Slow Clock oscillator with bypass mode
One Low-Power RC oscillator
One 3-20 MHz Crystal Oscillator, which can be bypassed
One Fast RC oscillator factory programmed, 3 output frequencies can be selected: 4, 8 or 12 MHz. By default 4
MHz is selected.
z
z
One 60 to 130 MHz PLL (PLLB) providing a clock for the USB Full Speed Controller
One 60 to 130 MHz programmable PLL (PLLA), capable to provide the clock MCK to the processor and to the
peripherals. The PLLA input frequency is from 3.5 to 20 MHz.
Figure 10-2. Clock Generator Block Diagram
Clock Generator
XTALSEL
On Chip
32 kHz
RC OSC
Slow Clock
SLCK
XIN32
Slow Clock
Oscillator
XOUT32
XIN
3-20 MHz
Main
Oscillator
Main Clock
MAINCK
XOUT
On Chip
12/8/4 MHz
RC OSC
MAINSEL
PLLB Clock
PLLBCK
PLL and
Divider B
PLL and
Divider A
PLLA Clock
PLLACK
Status Control
Power
Management
Controller
10.6 Power Management Controller
The Power Management Controller provides all the clock signals to the system. It provides:
z
z
z
z
z
the Processor Clock, HCLK
the Free running processor clock, FCLK
the Cortex SysTick external clock
the Master Clock, MCK, in particular to the Matrix and the memory interfaces
the USB Clock, UDPCK
SAM3S [SUMMARY]
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6500ES–ATARM–11-Feb-13
z
z
independent peripheral clocks, typically at the frequency of MCK
three programmable clock outputs: PCK0, PCK1 and PCK2
The Supply Controller selects between the 32 kHz RC oscillator or the crystal oscillator. The unused oscillator is disabled
automatically so that power consumption is optimized.
By default, at startup the chip runs out of the Master Clock using the fast RC oscillator running at 4 MHz.
The user can trim the 8 and 12 MHz RC Oscillator frequency by software.
Figure 10-3. SAM3S Power Management Controller Block Diagram
Processor
Clock
Controller
HCK
int
Sleep Mode
Divider
/8
SystTick
FCLK
Master Clock Controller
SLCK
MAINCK
PLLACK
PLLBCK
Prescaler
/1,/2,/4,...,/64
MCK
Peripherals
Clock Controller
periph_clk[..]
ON/OFF
Programmable Clock Controller
SLCK
MAINCK
PLLACK
PLLBCK
ON/OFF
Prescaler
/1,/2,/4,...,/64
pck[..]
USB Clock Controller
ON/OFF
PLLBCK
UDPCK
The SysTick calibration value is fixed at 8000 which allows the generation of a time base of 1 ms with SystTick clock at 8
MHz (max HCLK/8 = 64 MHz/8).
10.7 Watchdog Timer
z
16-bit key-protected only-once-Programmable Counter
z
Windowed, prevents the processor to be in a dead-lock on the watchdog access.
10.8 SysTick Timer
z
z
z
24-bit down counter
Self-reload capability
Flexible System timer
SAM3S [SUMMARY]
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6500ES–ATARM–11-Feb-13
10.9 Real Time Timer
z
Real Time Timer, allowing backup of time with different accuracies
z
z
z
32-bit free-running back-up counter
Integrates a 16-bit programmable prescaler running on slow clock
Alarm register capable to generate a wake-up of the system through the Shut Down Controller
10.10 Real Time Clock
z
z
z
z
z
z
Low power consumption
Full asynchronous design
Two hundred year calendar
Programmable Periodic Interrupt
Alarm and update parallel load
Control of alarm and update Time/Calendar Data In
10.11 General Purpose Backup Registers
z
Eight 32-bit general-purpose backup registers
10.12 Nested Vectored Interrupt Controller
z
z
z
z
z
Thirty maskable external interrupts
Sixteen priority levels
Processor state automatically saved on interrupt entry, and restored on
Dynamic reprioritization of interrupts
Priority grouping.
z
selection of preempting interrupt levels and non-preempting interrupt levels.
Support for tail-chaining and late arrival of interrupts.
back-to-back interrupt processing without the overhead of state saving and restoration between interrupts.
Processor state automatically saved on interrupt entry, and restored on interrupt exit, with no instruction overhead.
z
z
z
10.13 Chip Identification
z
Chip Identifier (CHIPID) registers permit recognition of the device and its revision.
Table 10-1. SAM3S Chip IDs Register
Flash Size
Chip Name
(KBytes)
256
128
64
Pin Count
48
DBGU_CIDR
0x28800960
0x288A0760
0x28890560
0x28900960
0x289A0760
0x28990560
0x28A00960
0x28AA0760
0x28A90560
CHIPID_EXID
ATSAM3S4A (Rev A)
ATSAM3S2A (Rev A)
ATSAM3S1A (Rev A)
ATSAM3S4B (Rev A)
ATSAM3S2B (Rev A)
ATSAM3S1B (Rev A)
ATSAM3S4C (Rev A)
ATSAM3S2C (Rev A)
ATSAM3S1C (Rev A)
JTAG ID: 0x05B2D03F
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
48
48
256
128
64
64
64
64
256
128
64
100
100
100
z
SAM3S [SUMMARY]
38
6500ES–ATARM–11-Feb-13
10.14 UART
z
Two-pin UART
z
z
z
z
z
z
Implemented features are 100% compatible with the standard Atmel USART
Independent receiver and transmitter with a common programmable Baud Rate Generator
Even, Odd, Mark or Space Parity Generation
Parity, Framing and Overrun Error Detection
Automatic Echo, Local Loopback and Remote Loopback Channel Modes
Support for two PDC channels with connection to receiver and transmitter
10.15 PIO Controllers
z
3 PIO Controllers, PIOA, PIOB and PIOC (100-pin version only) controlling a maximum of 79 I/O Lines
z
Fully programmable through Set/Clear Registers
Table 10-2. PIO available according to pin count
Version
PIOA
48 pin
64 pin
100 pin
32
21
13
-
32
15
-
PIOB
15
PIOC
32
z
z
Multiplexing of four peripheral functions per I/O Line
For each I/O Line (whether assigned to a peripheral or used as general purpose I/O)
z
z
z
z
z
Input change, rising edge, falling edge, low level and level interrupt
Debouncing and Glitch filter
Multi-drive option enables driving in open drain
Programmable pull-up or pull-down on each I/O line
Pin data status register, supplies visibility of the level on the pin at any time
z
Synchronous output, provides Set and Clear of several I/O lines in a single write
SAM3S [SUMMARY]
39
6500ES–ATARM–11-Feb-13
11. Peripherals
11.1 Peripheral Identifiers
Table 11-1 defines the Peripheral Identifiers of the SAM3S. A peripheral identifier is required for the control of the
peripheral interrupt with the Nested Vectored Interrupt Controller and for the control of the peripheral clock with the
Power Management Controller.
Table 11-1. Peripheral Identifiers
PMC Clock
Instance ID
Instance Name
SUPC
RSTC
RTC
NVIC Interrupt
Control
Instance Description
Supply Controller
Reset Controller
0
X
X
X
X
X
X
X
-
1
2
Real Time Clock
3
RTT
Real Time Timer
4
WDT
PMC
EEFC
-
Watchdog Timer
5
Power Management Controller
Enhanced Embedded Flash Controller
Reserved
6
7
8
UART0
UART1
SMC
PIOA
PIOB
PIOC
USART0
USART1
-
X
X
X
X
X
X
X
X
-
X
X
X
X
X
X
X
X
-
UART 0
9
UART 1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
SMC
Parallel I/O Controller A
Parallel I/O Controller B
Parallel I/O Controller C
USART 0
USART 1
Reserved
-
-
-
Reserved
HSMCI
TWI0
TWI1
SPI
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
High Speed Multimedia Card Interface
Two Wire Interface 0
Two Wire Interface 1
Serial Peripheral Interface
Synchronous Serial Controller
Timer/Counter 0
SSC
TC0
TC1
Timer/Counter 1
TC2
Timer/Counter 2
TC3
Timer/Counter 3
TC4
Timer/Counter 4
TC5
Timer/Counter 5
ADC
Analog-to-Digital Converter
Digital-to-Analog Converter
Pulse Width Modulation
CRC Calculation Unit
Analog Comparator
USB Device Port
DACC
PWM
CRCCU
ACC
UDP
SAM3S [SUMMARY]
40
6500ES–ATARM–11-Feb-13
11.2 Peripheral Signal Multiplexing on I/O Lines
The SAM3S product features 2 PIO controllers on 48-pin and 64-pin versions (PIOA, PIOB) or 3 PIO controllers on the
100-pin version, (PIOA, PIOB, PIOC), that multiplex the I/O lines of the peripheral set.
The SAM3S 64-pin and 100-pin PIO Controllers control up to 32 lines. (See, Table 10-2.) Each line can be assigned to
one of three peripheral functions: A, B or C. The multiplexing tables in the following pages define how the I/O lines of the
peripherals A, B and C are multiplexed on the PIO Controllers. The column “Comments” has been inserted in this table
for the user’s own comments; it may be used to track how pins are defined in an application.
Note that some peripheral functions which are output only, might be duplicated within the tables.
SAM3S [SUMMARY]
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6500ES–ATARM–11-Feb-13
11.2.1 PIO Controller A Multiplexing
Table 11-2. Multiplexing on PIO Controller A (PIOA)
I/O Line
PA0
Peripheral A
PWMH0
PWMH1
PWMH2
TWD0
Peripheral B
TIOA0
Peripheral C
A17
Extra Function
WKUP0
System Function
Comments
High drive
High drive
High drive
High drive
PA1
TIOB0
A18
WKUP1
PA2
SCK0
DATRG
WKUP2
PA3
NPCS3
TCLK0
PA4
TWCK0
RXD0
WKUP3
WKUP4
PA5
NPCS3
PCK0
PA6
TXD0
PA7
RTS0
PWMH3
ADTRG
NPCS1
NPCS2
PWMH0
PWMH1
PWMH2
PWMH3
XIN32
PA8
CTS0
WKUP5
WKUP6
XOUT32
PA9
URXD0
UTXD0
NPCS0
MISO
PWMFI0
PA10
PA11
PA12
PA13
PA14
WKUP7
MOSI
SPCK
WKUP8
WKUP14/PIODCEN1
PA15
TF
TIOA1
PWML3
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
TK
TD
TIOB1
PCK1
PWML2
PWMH3
A14
WKUP15/PIODCEN2
AD0
RD
PCK2
AD1
RK
PWML0
PWML1
PCK1
A15
AD2/WKUP9
AD3/WKUP10
AD8
RF
A16
RXD1
TXD1
SCK1
RTS1
CTS1
DCD1
DTR1
DSR1
RI1
64/100-pin versions
64/100-pin versions
64/100-pin versions
64/100-pin versions
64/100-pin versions
64/100-pin versions
64/100-pin versions
64/100-pin versions
64/100-pin versions
64/100-pin versions
64/100-pin versions
NPCS3
PWMH0
PWMH1
PWMH2
TIOA2
TIOB2
TCLK1
TCLK2
NPCS2
PCK2
NCS2
A19
AD9
PIODCCLK
PIODC0
A20
A23
PIODC1
MCDA2
MCDA3
MCCDA
MCCK
MCDA0
MCDA1
PIODC2
PIODC3
PIODC4
PIODC5
PWML2
NPCS1
WKUP11/PIODC6
PIODC7
SAM3S [SUMMARY]
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6500ES–ATARM–11-Feb-13
11.2.2 PIO Controller B Multiplexing
Table 11-3. Multiplexing on PIO Controller B (PIOB)
I/O Line
PB0
Peripheral A
PWMH0
PWMH1
URXD1
Peripheral B
Peripheral C
Extra Function
AD4
System Function
Comments
PB1
AD5
PB2
NPCS2
PCK2
AD6/ WKUP12
AD7
PB3
UTXD1
PB4
TWD1
PWMH2
PWML0
TDI
TDO/TRACESWO
TMS/SWDIO
TCK/SWCLK
XOUT
PB5
TWCK1
WKUP13
PB6
PB7
PB8
PB9
XIN
PB10
PB11
PB12
PB13
PB14
DDM
DDP
PWML1
PWML2
NPCS1
ERASE
PCK0
DAC0
DAC1
64/100-pin versions
64/100-pin versions
PWMH3
SAM3S [SUMMARY]
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6500ES–ATARM–11-Feb-13
11.2.3 PIO Controller C Multiplexing
Table 11-4. Multiplexing on PIO Controller C (PIOC)
I/O Line
PC0
Peripheral A
Peripheral B
PWML0
PWML1
PWML2
PWML3
NPCS1
Peripheral C
Extra Function System Function
Comments
D0
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
100-pin version
PC1
D1
PC2
D2
PC3
D3
PC4
D4
PC5
D5
PC6
D6
PC7
D7
PC8
NWE
PC9
NANDOE
PC10
PC11
PC12
PC13
PC14
PC15
PC16
PC17
PC18
PC19
PC20
PC21
PC22
PC23
PC24
PC25
PC26
PC27
PC28
PC29
PC30
PC31
NANDWE
NRD
NCS3
AD12
AD10
NWAIT
PWML0
PWML1
NCS0
NCS1
AD11
A21/NANDALE
A22/NANDCLE
A0
A1
PWMH0
PWMH1
PWMH2
PWMH3
PWML3
TIOA3
A2
A3
A4
A5
A6
TIOB3
A7
TCLK3
TIOA4
A8
A9
TIOB4
A10
A11
A12
A13
TCLK4
TIOA5
AD13
AD14
TIOB5
TCLK5
SAM3S [SUMMARY]
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6500ES–ATARM–11-Feb-13
12. Embedded Peripherals Overview
12.1 Serial Peripheral Interface (SPI)
z
Supports communication with serial external devices
z
z
z
z
Four chip selects with external decoder support allow communication with up to 15 peripherals
Serial memories, such as DataFlash and 3-wire EEPROMs
Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors
External co-processors
z
Master or slave serial peripheral bus interface
z
z
z
z
z
8- to 16-bit programmable data length per chip select
Programmable phase and polarity per chip select
Programmable transfer delays between consecutive transfers and between clock and data per chip select
Programmable delay between consecutive transfers
Selectable mode fault detection
z
Very fast transfers supported
z
z
Transfers with baud rates up to MCK
The chip select line may be left active to speed up transfers on the same device
12.2 Two Wire Interface (TWI)
z
z
z
z
z
z
z
Master, Multi-Master and Slave Mode Operation
Compatibility with Atmel two-wire interface, serial memory and I2C compatible devices
One, two or three bytes for slave address
Sequential read/write operations
Bit Rate: Up to 400 kbit/s
General Call Supported in Slave Mode
Connecting to PDC channel capabilities optimizes data transfers in Master Mode only
z
z
One channel for the receiver, one channel for the transmitter
Next buffer support
12.3 Universal Asynchronous Receiver Transceiver (UART)
z
Two-pin UART
z
z
z
z
z
Independent receiver and transmitter with a common programmable Baud Rate Generator
Even, Odd, Mark or Space Parity Generation
Parity, Framing and Overrun Error Detection
Automatic Echo, Local Loopback and Remote Loopback Channel Modes
Support for two PDC channels with connection to receiver and transmitter
12.4 Universal Synchronous Asynchronous Receiver Transceiver (USART)
z
Programmable Baud Rate Generator with Fractional Baud rate support
z
5- to 9-bit full-duplex synchronous or asynchronous serial communications
z
z
z
z
z
1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode
Parity generation and error detection
Framing error detection, overrun error detection
MSB- or LSB-first
Optional break generation and detection
SAM3S [SUMMARY]
45
6500ES–ATARM–11-Feb-13
z
z
z
z
z
z
By 8 or by-16 over-sampling receiver frequency
Hardware handshaking RTS-CTS
Receiver time-out and transmitter timeguard
Optional Multi-drop Mode with address generation and detection
Optional Manchester Encoding
Full modem line support on USART1 (DCD-DSR-DTR-RI)
z
z
RS485 with driver control signal
ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards
z
NACK handling, error counter with repetition and iteration limit
z
SPI Mode
z
z
z
Master or Slave
Serial Clock programmable Phase and Polarity
SPI Serial Clock (SCK) Frequency up to MCK/4
z
z
IrDA modulation and demodulation
Communication at up to 115.2 Kbps
Test Modes
Remote Loopback, Local Loopback, Automatic Echo
z
z
12.5 Synchronous Serial Controller (SSC)
z
Provides serial synchronous communication links used in audio and telecom applications (with CODECs in Master
or Slave Modes, I2S, TDM Buses, Magnetic Card Reader)
Contains an independent receiver and transmitter and a common clock divider
Offers configurable frame sync and data length
z
z
z
Receiver and transmitter can be programmed to start automatically or on detection of different event on the frame
sync signal
z
Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal
12.6 Timer Counter (TC)
z
Six 16-bit Timer Counter Channels
z
Wide range of functions including:
z
z
z
z
z
z
z
Frequency Measurement
Event Counting
Interval Measurement
Pulse Generation
Delay Timing
Pulse Width Modulation
Up/down Capabilities
z
Each channel is user-configurable and contains:
z
z
z
Three external clock inputs
Five internal clock inputs
Two multi-purpose input/output signals
z
z
Two global registers that act on all three TC Channels
Quadrature decoder
z
z
Advanced line filtering
Position / revolution / speed
z
2-bit Gray Up/Down Counter for Stepper Motor
SAM3S [SUMMARY]
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6500ES–ATARM–11-Feb-13
12.7 Pulse Width Modulation Controller (PWM)
z
One Four-channel 16-bit PWM Controller, 16-bit counter per channel
z
Common clock generator, providing Thirteen Different Clocks
z
z
A Modulo n counter providing eleven clocks
Two independent Linear Dividers working on modulo n counter outputs
z
Independent channel programming
z
z
z
z
z
z
z
z
z
z
Independent Enable Disable Commands
Independent Clock Selection
Independent Period and Duty Cycle, with Double Buffering
Programmable selection of the output waveform polarity
Programmable center or left aligned output waveform
Independent Output Override for each channel
Independent complementary Outputs with 12-bit dead time generator for each channel
Independent Enable Disable Commands
Independent Clock Selection
Independent Period and Duty Cycle, with Double Buffering
z
z
Synchronous Channel mode
z
z
Synchronous Channels share the same counter
Mode to update the synchronous channels registers after a programmable number of periods
Connection to one PDC channel
Offers Buffer transfer without Processor Intervention, to update duty cycle of synchronous channels
z
z
z
z
independent event lines which can send up to 4 triggers on ADC within a period
Programmable Fault Input providing an asynchronous protection of outputs
Stepper motor control (2 Channels)
12.8 High Speed Multimedia Card Interface (HSMCI)
z
z
z
z
z
z
z
z
z
z
4-bit or 1-bit Interface
Compatibility with MultiMedia Card Specification Version 4.3
Compatibility with SD and SDHC Memory Card Specification Version 2.0
Compatibility with SDIO Specification Version V1.1.
Compatibility with CE-ATA Specification 1.1
Cards clock rate up to Master Clock divided by 2
Boot Operation Mode support
High Speed mode support
Embedded power management to slow down clock rate when not used
HSMCI has one slot supporting
z
z
z
One MultiMediaCard bus (up to 30 cards) or
One SD Memory Card
One SDIO Card
z
Support for stream, block and multi-block data read and write
12.9 USB Device Port (UDP)
z
z
z
USB V2.0 full-speed compliant,12 Mbits per second.
Embedded USB V2.0 full-speed transceiver
Embedded 2688-byte dual-port RAM for endpoints
SAM3S [SUMMARY]
47
6500ES–ATARM–11-Feb-13
z
Eight endpoints
z
z
z
z
z
z
Endpoint 0: 64 bytes
Endpoint 1 and 2: 64 bytes ping-pong
Endpoint 3: 64 bytes
Endpoint 4 and 5: 512 bytes ping-pong
Endpoint 6 and 7: 64 bytes ping-pong
Ping-pong Mode (two memory banks) for Isochronous and bulk endpoints
z
z
z
Suspend/resume logic
Integrated Pull-up on DDP
Pull-down resistor on DDM and DDP when disabled
12.10 Analog-to-Digital Converter (ADC)
z
z
z
z
z
z
z
up to 16 Channels,
10/12-bit resolution
up to 1 MSample/s
programmable sequence of conversion on each channel
Integrated temperature sensor
Single ended/differential conversion
Programmable gain: 1, 2, 4
12.11 Digital-to-Analog Converter (DAC)
z
z
z
z
z
z
z
z
z
z
Up to 2 channel 12-bit DAC
Up to 2 mega-samples conversion rate in single channel mode
Flexible conversion range
Multiple trigger sources for each channel
2 Sample/Hold (S/H) outputs
Built-in offset and gain calibration
Possibility to drive output to ground
Possibility to use as input to analog comparator or ADC (as an internal wire and without S/H stage)
Two PDC channels
Power reduction mode
12.12 Static Memory Controller
z
z
z
z
z
z
z
z
z
z
z
z
16-Mbyte Address Space per Chip Select
8- bit Data Bus
Word, Halfword, Byte Transfers
Programmable Setup, Pulse And Hold Time for Read Signals per Chip Select
Programmable Setup, Pulse And Hold Time for Write Signals per Chip Select
Programmable Data Float Time per Chip Select
External Wait Request
Automatic Switch to Slow Clock Mode
Asynchronous Read in Page Mode Supported: Page Size Ranges from 4 to 32 Bytes
NAND FLASH additional logic supporting NAND Flash with Multiplexed Data/Address buses
Hardware Configurable number of chip select from 1 to 4
Programmable timing on a per chip select basis
SAM3S [SUMMARY]
48
6500ES–ATARM–11-Feb-13
12.13 Analog Comparator
z
z
z
One analog comparator
High speed option vs. low power option
Selectable input hysteresis:
z
0, 20 mV, 50 mV
z
Minus input selection:
z
z
z
z
DAC outputs
Temperature Sensor
ADVREF
AD0 to AD3 ADC channels
z
z
Plus input selection:
All analog inputs
output selection:
z
z
z
z
Internal signal
external pin
selectable inverter
z
Interrupt on:
Rising edge, Falling edge, toggle
z
12.14 Cyclic Redundancy Check Calculation Unit (CRCCU)
z
32-bit cyclic redundancy check automatic calculation
z
CRC calculation between two addresses of the memory
SAM3S [SUMMARY]
49
6500ES–ATARM–11-Feb-13
13. Package Drawings
The SAM3S series devices are available in LQFP, QFN and TFBGA packages.
Figure 13-1. 100-lead LQFP Package Mechanical Drawing
Note : 1. This drawing is for general information only. Refer to JEDEC Drawing MS-026 for additional information.
SAM3S [SUMMARY]
50
6500ES–ATARM–11-Feb-13
Figure 13-2. 100-ball TFBGA Package Drawing
SAM3S [SUMMARY]
51
6500ES–ATARM–11-Feb-13
Figure 13-3. 64- and 48-lead LQFP Package Drawing
SAM3S [SUMMARY]
52
6500ES–ATARM–11-Feb-13
Table 13-1. 48-lead LQFP Package Dimensions (in mm)
Millimeter
Inch
Symbol
Min
–
Nom
Max
1.60
0.15
1.45
Min
–
Nom
Max
0.063
0.006
0.057
A
A1
A2
D
–
–
0.05
1.35
–
1.40
0.002
0.053
–
0.055
0.354 BSC
0.276 BSC
0.354 BSC
0.276 BSC
–
9.00 BSC
7.00 BSC
9.00 BSC
7.00 BSC
–
D1
E
E1
R2
R1
q
0.08
0.08
0°
0.20
–
0.003
0.003
0°
0.008
–
–
–
3.5°
7°
3.5°
7°
θ1
θ2
θ3
c
0°
–
–
0°
–
–
11°
11°
0.09
0.45
12°
13°
13°
0.20
0.75
11°
12°
13°
13°
0.008
0.030
12°
11°
12°
–
0.004
0.018
–
L
0.60
0.024
0.039 REF
–
L1
S
1.00 REF
–
0.20
0.17
–
0.008
0.007
–
b
0.20
0.27
0.008
0.020 BSC.
0.217
0.217
0.011
e
0.50 BSC.
5.50
D2
E2
5.50
Tolerances of Form and Position
aaa
bbb
ccc
ddd
0.20
0.20
0.08
0.08
0.008
0.008
0.003
0.003
SAM3S [SUMMARY]
53
6500ES–ATARM–11-Feb-13
Table 13-2. 64-lead LQFP Package Dimensions (in mm)
Millimeter
Inch
Symbol
Min
–
Nom
Max
1.60
0.15
1.45
Min
–
Nom
Max
0.063
0.006
0.057
A
A1
A2
D
–
–
0.05
1.35
–
0.002
0.053
–
0.055
0.472 BSC
0.383 BSC
0.472 BSC
0.383 BSC
–
1.40
12.00 BSC
D1
E
10.00 BSC
12.00 BSC
E1
R2
R1
q
10.00 BSC
0.08
0.08
0°
–
–
0.20
–
0.003
0.003
0°
0.008
–
–
3.5°
–
7°
3.5°
7°
θ1
θ2
θ3
c
0°
–
0°
–
–
11°
11°
0.09
0.45
12°
13°
13°
0.20
0.75
11°
12°
13°
13°
0.008
0.030
12°
11°
12°
–
0.004
0.018
–
L
0.60
1.00 REF
–
0.024
0.039 REF
–
L1
S
0.20
0.17
–
0.008
0.007
–
b
0.20
0.50 BSC.
7.50
7.50
0.27
0.008
0.020 BSC.
0.285
0.285
0.011
e
D2
E2
Tolerances of Form and Position
aaa
bbb
ccc
ddd
0.20
0.20
0.08
0.08
0.008
0.008
0.003
0.003
SAM3S [SUMMARY]
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6500ES–ATARM–11-Feb-13
Figure 13-4. 48-pad QFN Package
SAM3S [SUMMARY]
55
6500ES–ATARM–11-Feb-13
Table 13-3. 48-pad QFN Package Dimensions (in mm)
Millimeter
Inch
Nom
Symbol
Min
–
Nom
–
Max
090
Min
–
Max
0.035
0.002
0.028
A
A1
A2
A3
b
–
–
–
0.050
0.70
–
–
–
0.65
–
0.026
0.008 REF
0.008
0.276 bsc
0.220
0.276 bsc
0.220
0.016
0.020 bsc
–
0.20 REF
0.20
0.18
5.45
0.23
5.75
0.007
0.215
0.009
0.226
D
7.00 bsc
5.60
D2
E
7.00 bsc
5.60
E2
L
5.45
0.35
5.75
0.45
0.215
0.014
0.226
0.018
0.40
e
0.50 bsc
–
R
0.09
–
0.004
–
Tolerances of Form and Position
aaa
bbb
ccc
0.10
0.10
0.05
0.004
0.004
0.002
SAM3S [SUMMARY]
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6500ES–ATARM–11-Feb-13
Figure 13-5. 64-pad QFN Package Drawing
SAM3S [SUMMARY]
57
6500ES–ATARM–11-Feb-13
14. Ordering Information
Table 14-1. Ordering Codes for SAM3S Series Devices
Flash
(Kbytes)
Package
(Kbytes)
Package
Type
Temperature
Operating Range
Ordering Code
MRL A
MRL B
Industrial
-40°C to 85°C
ATSAM3S4CA-AU
A
–
256
QFP100
BGA100
QFP64
QFN64
QFP48
QFN48
QFP100
BGA100
QFP64
QFN64
QFP48
QFN48
QFP100
BGA100
QFP64
QFN64
QFP48
QFN48
QFP100
BGA100
QFP64
QFN64
QFP48
QFN48
Green
Green
Green
Green
Green
Green
Green
Green
Green
Green
Green
Green
Green
Green
Green
Green
Green
Green
Green
Green
Green
Green
Green
Green
Industrial
-40°C to 85°C
ATSAM3S4CA-CU
ATSAM3S4BA-AU
ATSAM3S4BA-MU
ATSAM3S4AA-AU
ATSAM3S4AA-MU
ATSAM3S2CA-AU
ATSAM3S2CA-CU
ATSAM3S2BA-AU
ATSAM3S2BA-MU
ATSAM3S2AA-AU
ATSAM3S2AA-MU
ATSAM3S1CA-AU
ATSAM3S1CA-CU
ATSAM3S1BA-AU
ATSAM3S1BA-MU
ATSAM3S1AA-AU
ATSAM3S1AA-MU
ATSAM3S1CB-AU
ATSAM3S1CB-CU
ATSAM3S1BB-AU
ATSAM3S1BB-MU
ATSAM3S1AB-AU
ATSAM3S1AB-MU
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
B
B
B
B
B
B
256
256
256
256
256
128
128
128
128
128
128
64
Industrial
-40°C to 85°C
Industrial
-40°C to 85°C
Industrial
-40°C to 85°C
Industrial
-40°C to 85°C
Industrial
-40°C to 85°C
Industrial
-40°C to 85°C
Industrial
-40°C to 85°C
Industrial
-40°C to 85°C
Industrial
-40°C to 85°C
Industrial
-40°C to 85°C
Industrial
-40°C to 85°C
Industrial
-40°C to 85°C
64
Industrial
-40°C to 85°C
64
Industrial
-40°C to 85°C
64
Industrial
-40°C to 85°C
64
Industrial
-40°C to 85°C
64
Industrial
-40°C to 85°C
64
Industrial
-40°C to 85°C
–
64
Industrial
-40°C to 85°C
–
64
Industrial
-40°C to 85°C
–
64
Industrial
-40°C to 85°C
–
64
Industrial
-40°C to 85°C
–
64
SAM3S [SUMMARY]
58
6500ES–ATARM–11-Feb-13
Revision History
Change
Doc. Rev
Comments
Request Ref.
Section 1. “Features”updated, “Low Power Modes” , Sleep and Backup modes, down to 1.8 µA in
rfo
Backup mode
Figure 8-1, "SAM3S Product Mapping", SRAM associated 1 MByte bit band region mapping changed:
0x22000000 to 0x23FFFFFF.
6500ES
Document format updated, subsequently pagination changed
8545
Section 14. “Ordering Information” Introduced MRL B for SAM3S1 parts..
8044
Replace all mention to 100-ball LFBGA into 100-ball TFBGA.
7632
Add table note 5 in Table 3-1, “Signal Description List”.
7639
Add MOSCRCEN bit details in Section 5.5.2 “Wait Mode”.
7668-7901
7887
Section 9.1.3.9 “Fast Flash Programming Interface” updated.
Notes under Figure 5-1, "Single Supply" and Figure 5-2, "Core Externally Supplied" modified.
Cross-References (1) added for 64-pin packages in table Table 1-1, “Configuration Summary”.
Pin 22 value changed for PA23/PGMD11 in Table 4-1, “100-lead LQFP SAM3S4/2/1C Pinout”.
6500DS
8033
8093
8095
"High Frequency Asynchronous clocking mode" removed from Section 12.7 “Pulse Width Modulation
Controller (PWM)”
“Write Protected Registers” added in “Description” , in Peripherals list.
ADC column values updated in Table 1-1, “Configuration Summary”.
8213
rfo
Missing PGMD8 to 15 added to Table 4-1, “100-lead LQFP SAM3S4/2/1C Pinout” and Table 4-2,
“100-ball TFBGA SAM3S4/2/1C Pinout”.
rfo
Section 5.7 “Fast Startup” updated.
7536
7524
Typo fixed on back page: ‘techincal’ --> ‘technical’.
Typos fixed in Section 1. “Features”.
Missing title added to Table 14-1.
6500CS
7494
7492
7428
PLLA input frequency range updated in Section 10.5 “Clock Generator”.
A sentence completed in Section 5.5.2 “Wait Mode”.
Last sentence removed from Section 9.1.3.10 “SAM-BA® Boot”.
‘three GPNVM bits’ replaced by ‘two GPNVM bits’ in Section 9.1.3.11 “GPNVM Bits”.
Leftover sentence removed from Section 4.1 “SAM3S4/2/1C Package and Pinout”.
7394
“Packages” on page 2, package size or pitch updated.
7214
Table 1-1, “Configuration Summary”, ADC column updated, footnote gives precision on reserved
channel.
6981
Table 4-2, “100-ball TFBGA SAM3S4/2/1C Pinout”, pinout information is available.
7201
Figure 5-1, "Single Supply",Figure 5-2, "Core Externally Supplied" , updated notes below figures.
7243/rfo
6500BS
6500AS
Figure 5-2, "Core Externally Supplied", Figure 5-3, "Backup Battery", ADC, DAC, Analog Comparator
supply is 2.0V-3.6V.
Section 12.13 “Analog Comparator”, “Peripherals” on page 2, reference to “window function”
removed.
7103
7307
Section 9.1.3.8 “Unique Identifier”, Each device integrates its own 128-bit unique identifier.
First issue
SAM3S [SUMMARY]
59
6500ES–ATARM–11-Feb-13
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