ATMXT3432S-S-CUR034_技术文档

Features

• Chipset Configuration

– One master Atmel^®mXT3432S-M device

– Two Atmel mXT3432S1-S devices

• maXTouch^™Touchscreen

– True 12-bit multiple touch reporting and real-time XY tracking for up to

16 concurrent touches per touchscreen

– Screen sizes up to 17.3 inches diagonal, supported at 5 mm electrode pitch

• Number of Channels

maXTouch

– Electrode grid configurations of up to 44 X and 78 Y lines supported

– Touchscreens up to 3432 channels (subject to other configurations)

• Signal Processing

3432-channel

Touchscreen

Controller

– Advanced digital filtering using both hardware engine and firmware

– Self-calibration

– Auto drift compensation

– Grip and palm suppression algorithms to remove unintentional touches

– Reports one-touch and two-touch gestures

– Down-scaling and clipping support to match LCD resolution

– Ultra-fast start-up and calibration for best user experience

– Supports axis flipping and axis switch-over for portrait and landscape modes

– Supports Factory reference for better calibration

– Supports Lens Bending algorithms to restore signal distortions

• Scan Speed

– Maximum single touch >200 Hz, subject to configuration

– Configurable to allow power/speed optimization

– Programmable timeout for automatic transition from active to idle states

• Response Times

mXT3432S1

Revision 2.0

– Initial latency <20 ms for first touch from idle, subject to configuration

• Sensors

– Works with PET or glass sensors

– Works with all proprietary sensor patterns recommended by Atmel

– Supports passive and active stylus

• Panel Thickness

– Glass up to 2.5 mm, screen size dependent

– Plastic up to 1.2 mm, screen size dependent

• Interfaces

– I²C-compatible slave mode, 400 kHz

– USB 2.0-compliant composite device, full speed (12 Mbps)

– HID-I²C interface for Microsoft^®Windows^®8

• Power

– Digital 3.3 V nominal

– Analog 2.7 V – 3.3 V nominal

– High voltage X-line drive 10.0 V nominal

• Master Package

– 64-pin QFN 9 × 9 × 1 mm, 0.5 mm pin pitch

– 64-ball UFBGA 6 × 6 × 0.6 mm, 0.65 mm ball pitch

• Slave Packages

– 128-ball VFBGA 7 × 7 × 1 mm, 0.5 ball pitch

9853BX–AT42–03/13

1. Overview of the mXT3432S1

1.1

Introduction

The Atmel mXT3432S-M, together with its two associated mXT3432S1-S slave devices, is part

of the maXTouch^™family of touchscreen controllers. This chipset builds on the success of the

maXTouch family to provide a greatly improved user experience:

• Patented capacitive sensing method – The mXT3432S1 uses a unique charge-transfer

acquisition engine to implement the QMatrix^®capacitive sensing method patented by Atmel.

This allows the measurement of up to 3432 mutual capacitance nodes. Coupled with a

state-of-the-art CPU, the entire touchscreen sensing solution can measure, classify and track

finger touches with a high degree of accuracy.

• Capacitive Touch Engine (CTE) – The acquisition engine uses an optimal measurement

approach to ensure almost complete immunity from parasitic capacitance on the receiver

inputs (Y lines). The engine includes sufficient dynamic range to cope with touchscreen

mutual capacitances spanning 0.63 pF to 5 pF. This allows great flexibility for use with the

Atmel proprietary ITO pattern designs. One and two layer ITO sensors are possible using

glass or PET substrates.

• Processing power – The master mXT3432S-M combines with its slave mXT3432S1-S

devices to allow the signal acquisition, preprocessing, postprocessing and housekeeping to

be partitioned in an efficient and flexible way. This gives ample scope for sensing algorithms,

touch tracking or advanced shape-based filtering.

• Noise filtering – The mXT3432S1 makes use of the noise filtering algorithms found on the

maXTouch solution and copes well with LCD noise and RF noise, but operational

enhancements allow the mXT3432S-M to cope even better with severe noise.

• User experience – The mXT3432S1 makes use of the Atmel mutual capacitance method to

provide unambiguous multitouch performance and a responsive user experience. Hysteresis

algorithms ensure that where a light touch is applied this is reported as a continuous touch,

even when close to the touch threshold level, to prevent jitter on the screen. Algorithms also

ensure that an on-screen cursor is stationary after the touch is removed, or remains on the

edge of the visible area after a drag gesture.

• Interpreting user intention – The mXT3432S1 Object Protocol provides enhanced signal

processing capabilities. Stylus support allows stylus touches to be detected and

distinguished from other touches, such as finger touches. The suppression of unintentional

touches from the user’s gripping fingers, a resting palm, or a touching cheek or ear also help

ensure that the user’s intentions are correctly interpreted.

2

mXT3432S1

9853BX–AT42–03/13

mXT3432S1

1.2

Chipset Architecture

The master mXT3432S-M device controls two slave mXT3432S1-S devices, as shown in

Figure 1-1.

Figure 1-1. System Block Diagram

VDD

AVDD

RESET

SDA

SCL

CHG

X0 TO Xn

Slave A

(mXT3432S1-S)

VBUS

DP

Y0, ...Yn-1

Master

(mXT3432S-M)

DM

Xn+1 TO Xm

Slave B

(mXT3432S1-S)

DEBUG_CLK

DEBUG_DATA

Y1, ...Yn

A0

A1

SYNC

XT1

XT2

Each of the two mXT3432S1-S slave devices controls up to 32 X lines and 39 Y lines, with a

total of 44 X lines and 78 Y lines available for use.

The X lines are distributed across the two slave devices in two sequential blocks. The Y lines,

however, are distributed across the two slave devices in an interleaved manner, such that Y0

connects to Slave A, Y1 connects to Slave B, and so on.

Table 1-1.

Sense Lines

Controls Sense Lines...

Slave Device

X

Y

Slave A

Slave B

X0 to X31

X32 to X43

Y0, Y2, Y4, …Y76

Y1, Y3, Y5, …Y77

The host interfaces with the single master device only; it never needs to deal with the slave

devices. It is the responsibility of the master chip to ensure that the configuration and use of the

slaves is carried out in a uniform and consistent manner. Communication with the host is

achieved using the USB or I²C-compatible interface.

3

9853BX–AT42–03/13

2. Pinouts

2.1

Pinout Configurations

2.1.1

Master mXT3432S-M – 64-pin QFN

63 62 61

58

56 55

53 52 51 50 49

54

64

60 59

57

GND

VDD_INPUT

CHRG_IN

I2CMODE

NC

1

48

VDD

2

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

NC

3

NC

4

NC

5

SCK_B

NC

6

SS_C

SLV_RST

VDD_1V8

SLV_CLOCK

NC

7

MOSI_D

NC

mXT3432S-M

8

9

XT2

10

11

12

13

14

15

16

XT1

BUSY_A

BUSY_B

REQ_A

DEBUG_CLK

SCK_D

DEBUG_DATA

SCK_C

NC

REQ_B

GPIO0

GPIO1

SCK_A

18 19 20

23

25 26

28 29 30 31 32

27

17

21 22

24

Top View

4

mXT3432S1

9853BX–AT42–03/13

mXT3432S1

2.1.2

Master mXT3432S-M – 64-ball UFBGA

H

VDD_1V8 VDD_1V8

SCK_A

NC

GND

SS_B

NC

SCL

SDA

NC

SS_A

G

MISO_B

GPIO0

GPIO1

VDD

GND

VDD

GPIO2

NC

VDD

F

REQ_B

MOSI_B

CHG

DEBUG_

DATA

SCK_D

E

BUSY_A

REQ_A

BUSY_B

SCK_C DEBUG_CLK XT2

D

VDD_1V8 SLV_CLK

NC

VDD_1V8 VDD_1V8

NC

MOSI_D

SCK_B

NC

XT1

NC

C

B

A

SS_C

SLV_

RESET

WAKE

I2C_MODE

VBUS

A1

CHRG_IN VDD_INPUT VDD

MISO_A

GND

VDD

MOSI_C

MOSI_A

GND

RESET

SS_D

A0

DM

DP

8

1

2

3

4

5

6

7

Bottom View

5

9853BX–AT42–03/13

2.1.3

Slave mXT3432S1-S – 128-ball VFBGA

Slave A connections:

X4

N

X31

X28

X26

VDD

GND

RESET

SCK_C

SS_A

VDD

SCK_A VDDCORE

GND

BUSY_A

MOSI_C

MOSI_A

CTE2

X15

X14

X4

M

L

X29

X30

X27

GND

VDD

SS_C

REQ_A

NC

X13

X10

X12

X4

XVDD

CTE1 VDD_INPUT SLV_CLK MISO_A

X11

XVDD

CTE0

K

J

GND

X22

X24

X21

X23

X9

X7

X8

X6

GND

X5

GND

X4

H

G

F

X20

X17

X19

X18

X16

NC

CTE3

GND

X4

X1

X3

X2

X0

XVDD

X25

XVDD

X4

Y76

Y70

Y74

Y68

Y72

Y66

NC

Y44

Y20

Y26

Y18

Y24

Y16

Y22

E

D

C

GND

Y64

Y56

Y62

Y50

Y30

Y10

AVDD

GND

Y28

Y0

X4

AVDD

GND

NC

Y38

Y40

Y36

Y32

SLV_SYNC0

SLV_SYNC1

SLV_SYNC4

SLV_SYNC5

X4

B

A

Y60

Y54

Y48

AVDD

NC

GND

AVDD

Y12

Y6

Y2

X4

Y58

Y52

Y46 SLV_SYNC2 SLV_SYNC3 NC

NC

Y42

NC

Y34

Y14

Y8

Y4

1

2

3

4

5

6

7

8

9

10

11

12

13

Bottom View

For Slave B:

• Add 32 to X-line numbers

• Add 1 to Y-line numbers

• Change all balls with suffix _A to _B and change _C to _D

• See Table 2-3 on page 11 for these and other changes.

6

mXT3432S1

9853BX–AT42–03/13

mXT3432S1

2.2

Pinout Descriptions

2.2.1

Master mXT3432S-M – 64-pin QFN

Table 2-1.

Pin Listing mXT3432S-M –64-pin QFN

1

Name

GND

Type

P

Comments

If Unused, Connect To...

Ground

–

2

VDD_INPUT

CHRG_IN

I2CMODE ⁽¹⁾

NC

I

Inter-chip signal; for factory use only

Charger present input

I²C-compatible protocol select – I²C or HID-I²C

No connection

–

3

I

GND

4

I

Leave open ⁽²⁾

5

–

Leave open

6

SS_C

I

Inter-chip signal

No connection

–

7

SLV_RST

VDD_1V8 ⁽³⁾

SLV_CLOCK

NC

O

P

–

8

–

9

O

–

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

Leave open

BUSY_A

BUSY_B

REQ_A

REQ_B

GPIO0

I

Inter-chip signal

General purpose IO

Ground

–

I

–

O

I/O

P

–

Leave open

GPIO1

Leave open

GND

–

GND_INPUT

VDD

I

Inter-chip signal; for factory use only

Power

–

P

–

VDD_1V8 ⁽³⁾

P

Inter-chip signal

Power

–

VDD

P

–

VDD_1V8 ⁽³⁾

GND

P

Inter-chip signal

Ground

–

P

–

MISO_B

MOSI_B

SS_B

O

I

Inter-chip signal

No connection

–

I

–

NC

–

Leave open

SCL ⁽¹⁾

OD

Serial Interface Clock

Serial Interface Data

State change interrupt

SDA ⁽¹⁾

(4)

CHG

7

9853BX–AT42–03/13

Table 2-1.

31

Pin Listing mXT3432S-M –64-pin QFN (Continued)

Name

SS_A

Type

Comments

If Unused, Connect To...

I

Inter-chip signal

Power

–

32

VDD

P

–

33

SCK_A

NC

I

Inter-chip signal

No connection

–

34

–

Leave open

35

SCK_C

DEBUG_DATA

SCK_D

DEBUG_CLK

XT1

I

Inter-chip signal

Debug port data

Inter-chip signal

Debug port clock

External oscillator – 16 MHz

No connection

–

36

I/O

Leave open

37

I

–

38

I/O

Leave open

39

I

–

40

XT2

O

–

41

NC

–

Leave open

42

MOSI_D

NC

I

Inter-chip signal

No connection

–

43

–

Leave open

44

SCK_B

NC

I

Inter-chip signal

No connection

–

45

–

Leave open

46

NC

–

No connection

Leave open

47

NC

–

No connection

Leave open

48

VDD

P

Power

–

49

GND

P

Ground

–

50

DP ⁽¹⁾

USB

USB device port data +

USB device port data -

USB VBUS monitor

Inter-chip signal

I²C-compatible address select

Inter-chip signal

GND

51

DM ⁽¹⁾

VBUS ⁽¹⁾

VDD_1V8 ⁽³⁾

A0

USB

GND

52

USB

GND

53

P

I

–

54

Leave open

55

A1

I

Leave open

56

VDD_1V8 ⁽³⁾

MOSI_A

MISO_A

SS_D

P

I

–

57

58

O

I

59

External wake-up. Typically connected to SCL pin.

See Section 5.8 on page 35 for more information.

60

WAKE

I

Vdd if USB used

8

mXT3432S1

9853BX–AT42–03/13

mXT3432S1

Table 2-1.

Pin Listing mXT3432S-M –64-pin QFN (Continued)

61

62

63

64

Name

GPIO2

MOSI_C

RESET

VDD

Type

Comments

General purpose IO

Inter-chip signal

Reset low

If Unused, Connect To...

I/O

Leave open

I

–

Vdd ⁽⁵⁾

–

P

Power

1. Only one interface (I²C, USB, or HID-I²C) can be used in any one design.

2. Leave open for standard Atmel object protocol, or connect to GND for Microsoft Windows 8 HID-I²C protocol.

3. The mXT3432S-M has an internal 1.8 V regulator. The host system only needs to supply the VDD rail.

4. CHG is momentarily set (approximately 100 ms) as an input after power-up or reset for diagnostic purposes.

5. It is recommend that RESET is connected to the host system.

I

Input only

OD

Open drain output

O

Output only, push-pull

P

Ground or power

USB USB communications

2.2.2

Master mXT3432S-M – 64-ball UFBGA

Pin Listing mXT3432S-M –64-ball UFBGA

Table 2-2.

A1

Name

GND

Type

Comments

Ground

If Unused, Connect To...

P

–

A2

RESET

MOSI_C

SS_D

I

Reset low

Vdd ⁽¹⁾

A3

I

Inter-chip signal

–

A4

I

–

A5

MOSI_A

A0

I

–

A6

I

I²C-compatible address select

USB device port data -

USB device port data +

Charger present input

Leave open

A7

DM ⁽¹⁾

USB

GND

A8

DP ⁽¹⁾

USB

GND

B1

CHRG_IN

VDD_INPUT

VDD

I

GND

B2

Inter-chip signal; for factory use only

–

B3

P

O

I

Power

–

B4

MISO_A

A1

Inter-chip signal

–

B5

I²C-compatible address select

Leave open

B6

GND

P

–

I

Ground

–

B7

VDD

Power

–

B8

NC

No connection

Leave open

C1

SS_C

Inter-chip signal

–

C2

SLV_RST

I2CMODE ⁽²⁾

O

I

Inter-chip signal

–

C3

I²C-compatible protocol select – I²C or HID-I²C

Leave open ⁽³⁾

External wake-up. Typically connected to SCL pin.

See Section 5.8 on page 35 for more information.

C4

WAKE

I

Vdd if USB used

C5

C6

VBUS ⁽¹⁾

NC

USB

–

USB VBUS monitor

No connection

GND

Leave open

9

9853BX–AT42–03/13

Table 2-2.

C7

C8

D1

D2

D3

D4

D5

D6

D7

D8

E1

Pin Listing mXT3432S-M –64-ball UFBGA (Continued)

Name

NC

Type

–

Comments

If Unused, Connect To...

No connection

Leave open

SCK_B

VDD_1V8 ⁽⁴⁾

SLV_CLOCK

NC

I

Inter-chip signal

No connection

–

P

–

O

–

Leave open

VDD_1V8 ⁽⁴⁾

XT1

P

Inter-chip signal

External oscillator – 16 MHz

No connection

–

P

–

I

–

NC

–

Leave open

MOSI_D

BUSY_A

REQ_A

NC

I

Inter-chip signal

No connection

–

I

–

E2

O

–

E3

Leave open

E4

BUSY_B

I

Inter-chip signal

State change interrupt

Inter-chip signal

Debug port clock

External oscillator – 16 MHz

Inter-chip signal

Ground

–

(5)

E5

CHG

OD

I

Leave open

E6

SCK_C

DEBUG_CLK

XT2

–

E7

I/O

O

P

Leave open

E8

–

F1

REQ_B

GND

–

F2

–

F3

GPIO2

GPIO0

MOSI_B

NC

I/O

I

General purpose IO

Inter-chip signal

No connection

Leave open

F4

Leave open

F5

–

F6

–

Leave open

F7

DEBUG_DATA

SCK_D

GPIO1

VDD

I/O

I

Debug port data

Inter-chip signal

General purpose IO

Power

Leave open

F8

–

G1

G2

G3

G4

G5

G6

G7

G8

H1

H2

I/O

P

Leave open

–

VDD

P

Power

–

MISO_B

NC

O

–

Inter-chip signal

No connection

–

Leave open

SDA ⁽¹⁾

OD

P

Serial Interface Data

Power

Leave open

VDD

–

NC

–

No connection

Leave open

GND_INPUT

VDD_1V8 ⁽⁴⁾

I

Inter-chip signal; for factory use only

Inter-chip signal

–

P

10

mXT3432S1

9853BX–AT42–03/13

mXT3432S1

Table 2-2.

Pin Listing mXT3432S-M –64-ball UFBGA (Continued)

H3

H4

H5

H6

H7

H8

Name

VDD_1V8 ⁽⁴⁾

GND

Type

Comments

If Unused, Connect To...

P

Inter-chip signal

Ground

–

P

–

SS_B

I

Inter-chip signal

Serial Interface Clock

Inter-chip signal

–

SCL ⁽¹⁾

OD

Leave open

SS_A

I

–

SCK_A

1. It is recommend that RESET is connected to the host system.

2. Only one interface (I²C, USB, or HID-I²C) can be used in any one design.

3. Leave open for standard Atmel object protocol, or connect to GND for Microsoft Windows 8 HID-I²C protocol.

4. The mXT3432S-M has an internal 1.8 V regulator. The host system only needs to supply the VDD rail.

5. CHG is momentarily set (approximately 100 ms) as an input after power-up or reset for diagnostic purposes.

I

Input only

OD

Open drain output

O

Output only, push-pull

P

Ground or power

USB USB communications

2.2.3

Slaves mXT3432S1-S – 128-ball VFBGA

Table 2-3.

Ball

Pin Listing mXT3432S1-S Slaves

Name

Type

If Unused, Connect

To...

Comments

Slave A

Y58

Slave B

A1

A2

Y59

I

Y line connection

Slave Sync 2

Leave open

–

Y52

Y53

A3

Y46

Y47

I

A4

SLV_SYNC2

SLV_SYNC3

NC

SLV_SYNC2

SLV_SYNC3

NC

I

A5

I

Slave Sync 3

A6

–

I

No connection

Y line connection

No connection

Y line connection

Slave Sync 1

A7

NC

–

A8

Y42

Y43

Leave open

–

A9

NC

–

I

A10

A11

A12

A13

B1

Y34

Y35

Leave open

–

Y14

Y15

I

Y8

Y9

I

Y4

Y5

I

Y60

Y61

I

B2

Y54

Y55

I

B3

Y48

Y49

I

B4

SLV_SYNC1

AVDD

SLV_SYNC5

SLV_SYNC1

AVDD

SLV_SYNC5

I

B5

P

I

Analog power

B6

Slave Sync 5

Leave open

11

9853BX–AT42–03/13

Table 2-3.

Ball

Pin Listing mXT3432S1-S Slaves (Continued)

Name

If Unused, Connect

To...

Type

Comments

Slave A

NC

Slave B

NC

B7

B8

–

I

No connection

Y line connection

Ground

–

Y40

Y41

Leave open

–

B9

GND

AVDD

Y12

GND

AVDD

Y13

P

I

B10

B11

B12

B13

C1

Analog power

–

Y line connection

Analog power

Leave open

–

Y6

Y7

I

Y2

Y3

I

AVDD

Y56

AVDD

Y57

P

I

C2

Y line connection

Slave Sync 0

Leave open

–

C3

Y50

Y51

I

C4

SLV_SYNC0

GND

SLV_SYNC4

NC

SLV_SYNC0

GND

SLV_SYNC4

NC

I

C5

P

I

Ground

C6

Slave Sync 4

Leave open

–

C7

–

I

No connection

Y line connection

Ground

C8

Y38

Y39

Leave open

–

C9

Y36

Y37

I

C10

C11

C12

C13

D1

Y32

Y33

I

Y10

Y11

I

GND

Y0

GND

Y1

P

I

Y line connection

Ground

Leave open

–

GND

Y64

GND

Y65

P

I

D2

Y line connection

Analog power

Leave open

–

D3

Y62

Y63

I

D11

D12

D13

E1

Y30

Y31

I

AVDD

Y28

AVDD

Y29

P

I

Y line connection

Leave open

Y70

Y71

I

E2

Y68

Y69

I

E3

Y66

Y67

I

E11

E12

E13

F1

Y26

Y27

I

Y24

Y25

I

Y22

Y23

I

Y76

Y77

I

F2

Y74

Y75

I

F3

Y72

Y73

I

12

mXT3432S1

9853BX–AT42–03/13

mXT3432S1

Table 2-3.

Ball

Pin Listing mXT3432S1-S Slaves (Continued)

Name

If Unused, Connect

To...

Type

Comments

Slave A

NC

Slave B

NC

F6

F7

–

I

No connection

–

NC

No connection

–

F8

Y44

Y20

Y18

Y16

X17

Y45

Y21

Y19

Y17

X49

Y line connection

X matrix drive line

Leave open

F11

F12

F13

G1

I

O

X line drive voltage – see schematics in

Section 2.3 on page 16

G2

XVDD

P

Leave open

G3

G6

X16

X25

GND

X1

X48

X57

GND

X33

O

P

X matrix drive line

Ground

Leave open

–

G8

G11

O

X matrix drive line

Leave open

X line drive voltage – see schematics in

Section 2.3 on page 16

G12

XVDD

P

Leave open

G13

H1

X0

X20

X19

X18

NC

X32

X52

X51

X50

NC

O

–

X matrix drive line

No connection

Leave open

–

H2

H3

H6

H7

NC

–

No connection

–

H8 ⁽¹⁾

H11

H12

H13

J1

CTE3A

X4

CTE3B

X36

X35

X34

X54

X53

GND

X39

X38

X37

GND

X56

X55

X41

X40

I/O

O

P

Inter-Slave connection

X matrix drive line

Ground

–

Leave open

–

X3

X2

X22

X21

GND

X7

J2

J3

J11

J12

J13

K1

O

P

X matrix drive line

Ground

Leave open

–

X6

X5

GND

X24

X23

X9

K2

O

X matrix drive line

Leave open

K3

K11

K12

X8

13

9853BX–AT42–03/13

Table 2-3.

Ball

Pin Listing mXT3432S1-S Slaves (Continued)

Name

If Unused, Connect

To...

Type

Comments

Slave A

GND

Slave B

GND

K13

L1

P

Ground

–

X26

X58

O

X matrix drive line

Leave open

X line drive voltage – see schematics in

Section 2.3 on page 16

L2

XVDD

P

Leave open

L3

L4

X27

VDD

X59

VDD

O

P

X matrix drive line

Leave open

Digital power

–

L5 ⁽¹⁾

L6 ⁽¹⁾

L7

CTE0A

CTE1A

VDD_INPUT

SLV_CLK

MISO_A

MOSI_A

X11

CTE0B

CTE1B

VDD_INPUT

SLV_CLK

MISO_B

MOSI_B

X43

I/O

I

Inter-Slave connection

Inter-chip signal; for factory use only

Inter-chipset clock

Inter-chip signal

–

L8

–

L9

I

–

L10

L11

L12

O

Inter-chip signal

–

X matrix drive line

Leave open

X10

X42

X matrix drive line

X line drive voltage – see schematics in

Section 2.3 on page 16

L13

XVDD

P

Leave open

M1

M2

M3

M4

M5

M6

M7

M8

M9

M10

M11

M12

M13

N1

X28

X29

X60

X61

O

P

O

I

X matrix drive line

Ground

Leave open

X30

X62

Leave open

GND

VDD

GND

VDD

–

Digital power

–

VDD

Digital power

–

SS_C

REQ_A

GND

MOSI_C

NC

SS_D

REQ_B

GND

MOSI_D

NC

Inter-chip signal

Ground

–

P

O

–

Inter-chip signal

Reserved for future use

X matrix drive line

Digital power

–

X13

X45

O

P

I

Leave open

X12

X44

Leave open

X31

X63

Leave open

N2

VDD

–

N3

GND

RESET

SCK_C

SS_A

SCK_A

GND

RESET

SCK_D

SS_B

SCK_B

Ground

N4

Inter-chip signal

N5

O

N6

N7

14

mXT3432S1

9853BX–AT42–03/13

mXT3432S1

Table 2-3.

Ball

Pin Listing mXT3432S1-S Slaves (Continued)

Name

If Unused, Connect

To...

Type

Comments

Slave A

Slave B

Digital core power. Must be connected as in

schematics (see Section 2.3 on page 16)

N8

VDDCORE

P

–

N9

N10

GND

BUSY_A

CTE2A

X15

GND

BUSY_B

CTE2B

X47

P

O

Ground

–

Inter-chip signal

Inter-Slave connection

X matrix drive line

–

N11 ⁽¹⁾

I/O

O

–

N12

Leave open

N13

X14

X46

O

1. Balls H8, L5, L6, and N11 are used to interconnect the two slave devices – see See “Slave Devices” on page 18.

I

Input only Output only, push-pull Ground or power

O

P

15

9853BX–AT42–03/13

2.3

Schematics

2.3.1

Master Device (mXT3432S-M) – 64-pin QFN

Notes:

1. Capacitors C1 – C10 and C36 must be X7R or X5R and track lengths must be <5 mm.

V D D _ 3 V 3

C 5

C 6

C 7

C 8

C 9

C 3 6

C

1

C

2

C

3

C

4

C

1

0

C

1

3

1

0

n

F

1

0

n

F

1

0

n

F

1

0

n

F

1

0

n

F

4

u

7

1

0

n

F

1

0

n

F

1

0

n

F

1

0

n

F

1

0

n

F

4

u

7

G

N

D

G

N

D

G

N

D

V

D

_

3

V

3

R

4

R

9

1

0

k

3

R

9

S

L

V

_

C

L

K

S LV _ C LK

S LV _ R ST

N C

V

D

_

3

V

3

R

E

S

E

T

6

3

R

E

S

E

T

7

S

L

V

_

R

E

S

E

T

These pull-up resis-

R

7

2

3

4

5

4

7

V D D _ IN P U T

C H RG _ IN

1 2 C _ M O D E

N C

tors can be mounted on

the main PCB

1

0

k

C

H

R

G

_

I

N

I

2

C

M

O

D

E

1 1

1 3

3 1

3 3

5 7

5 8

BUS Y _ A

RE Q_ A

S S_ A

B U SY _ A

R E Q _ A

S S_ A

V

D

_

3

V

3

R 1 8

1 0 k

R 5

2 k2 0

R3

2 k2 0

6 0

2 7

2 8

2 9

3 0

SCK _A

MO SI_A

MIS O_ A

WAK E

N C

SCK _ A

M O SI_ A

M ISO _ A

S CL

S DA

C H G

S

C

L

S DA

C H G

1 2

1 4

2 6

4 4

2 5

2 4

BUS Y _ B

RE Q_ B

S S_ B

B U SY _ B

R E Q _ B

S S_ B

V

B

U

S

_

U

S

B

5 2

3 9R 5 1

3 9R 5 0

mXT3432S-M

V B US

D M

C 2 1

+

DM

DP

R 6 2

R1

SCK _B

MO SI_B

MIS O_ B

C 2 0

SCK _ B

M O SI_ B

M ISO _ B

1 0 0 n F

2 u 2F T AN T

D P

GN D

R7 3 4 7 R

DB G_DA T

DBG _C LK

3 6

3 8

3 4

4 6

6

D E B UG_ D AT A

D E B UG_ C LK

N C

R 7 4 4 7 R

SS_ C

S S_ C

5 4

5 5

3 5

6 2

4 5

SC K_C

MOS I_ C

A 0

A 1

SCK _ C

M O SI_ C

N C

GN D

C 2 8 1 5 p

3 9

4 0

X T 1

X T 2

1 0

4 3

5 9

3 7

4 1

4 2

X T 1

N C

16M Hz

GN D C 3 0 1 5 p

S

_

D

S

_

D

6 1

1 6

1 5

S

C

K

_

D

G P IO 2

G P IO 1

G P IO 0

SCK _ D

N C

MOS I_ D

M

O

S

I

_

D

G

N

D

16

mXT3432S1

9853BX–AT42–03/13

mXT3432S1

2.3.2

Master Device Schematic – UFBGA

Notes:

1. Capacitors C1 – C10 and C36 must be X7R or X5R and track lengths must be <5 mm.

V D D _ 3 V 3

C 5

C 6

C 7

C 8

C 9

C 3 6

C 1

C 2

C 3

C

4

C 1 0

C

1

3

1

0

n

F

1 0 0 n F

4 u 7

1

0

n

F

1 0 0 n F

1

0

n

F

1

0

n

F

4 u 7

G

N

D

G N D

G

N

D

V D D _ 3 V 3

R4

R

9

1

0

k

3

R

D 2

C 2

B 8

S

L

V

_

C

L

K

S LV _ C LK

S LV _ R ST

N C

V D D _ 3 V 3

RES ET

A 2

R E SE T

S LV _ RE SE T

These pull-up resis-

R7

B 2

B 1

C 3

E 3

V D D _ IN P U T

C H RG _ IN

1 2 C _ M O D E

N C

tors can be mounted on

the main PCB

1 0 k

CHRG _I N

I 2 CMOD E

E 1

E 2

H 7

H 8

A 5

B 4

BUS Y _ A

RE Q_ A

S S_ A

B U SY _ A

R E Q _ A

S S_ A

V D D _ 3 V 3

R 1 8

1 0 k

R5

2k2 0

R3

2 k2 0

C 4

SCK _A

MO SI_A

MIS O_ A

WAK E

SCK _ A

M O SI_ A

M ISO _ A

S CL

S DA

C H G

H 6

G6

E 5

S C L

S DA

C H G

E 4

F 1

BUS Y _ B

RE Q_ B

S S_ B

B U SY _ B

R E Q _ B

S S_ B

V B U S_ U SB

C 5

3 9R A 7

3 9R A 8

G5

H 5

C 8

F 5

V B US

D M

D P

mXT3432S-M

C

2

1

+

DM

DP

R 6 2

R1

SCK _B

MO SI_B

MIS O_ B

C

2

0

SCK _ B

M O SI_ B

M ISO _ B

1

0

n

F

2

u

2

F

T

A

N

T

G

4

N

C

G

N

D

R

7

3

4

7

R

DB G_DA T

DBG _C LK

F

7

G 8

C 6

C 1

E 6

A 3

F 6

D E B UG_ D AT A

D E B UG_ C LK

N C

E

7

R

7

4

7

R

S

_

C

S

_

C

A 6

B 5

SC K_C

MOS I_ C

A 0

A 1

SCK _ C

M O SI_ C

N C

G

N

D

C

2

8

1

5

p

D 6

E 8

X T 1

X T 2

D 3

C 7

A 4

F 8

X T 1

16M Hz

N C

G

N

D

C

3

0

1

5

p

SS_ D

S

_

D

F 3

F 4

S

C

K

_

D

G P IO 2

G P IO 0

G P IO 1

SCK _ D

N C

D 7

D 8

G

1

M

O

S

I

_

D

M

O

S

I

_

D

G

N

D

17

9853BX–AT42–03/13

2.3.3

Slave Devices

2.3.3.1

Slave Devices (2 × mXT3432S1-S) – 128-ball VFBGA

Note: Instance Slave A only is shown; Slave B is omitted for simplicity.

V D D C O R E

V D D 3 V 3

Optional 1.2 Ωresistor for

noisy AVdd lines

R2 2

0R

A V D D

R1 7

0 R

2 .2 uF /6 .3

V

C1 8

C1 9

10 0n F

G N D

X V D D

R 4 5

0 R

GN D

G

N

D

NOTE: Bypass capacitors must be

X7R or X5R and placed <5 mm away

from device.

L

1

X 1 1

X 1 2

X 1 3

X 1 4

X 1 5

X 1 6

X 1 7

X 1 8

X 1 9

X 2 0

X 1 1

X 1 2

X 1 3

X 1 4

X 1 5

X 1 6

X 1 7

X 1 8

X 1 9

X 2 0

X 2 1

X 2 2

X 2 3

X 2 4

X 2 5

X 2 6

X 2 7

X 2 8

X 2 9

X 3 0

X 3 1

M 1 3

M 1 2

N 1 3

N 1 2

G3

G1

H 3

H 2

H 1

J 2

G

N

D

S LV_ R ES ET N 4

RE SE T_ A

R

E

S

E

T

SC K_C

S S _C

N 5

M 7

L 9

S CK _ C

S S_ C

MATRIX X DRIVE

X

2

1

MIS O _A

CT E3A

J

1

X 2 2

X 2 3

X 2 4

X 2 5

X 2 6

X 2 7

X 2 8

X 2 9

X 3 0

X 3 1

MI SO _ A

C T E 3 A

K3

K2

G6

L1

CONNECTIONS TO

MASTER DEVICE

H

8

L

3

MOS I _ A

N C

M 1

M 2

M 3

N 1

L

1

0

M O SI_ A

N C

M

1

C 4 SLV_S YN C0

B 4 SLV_S YN C1

A4 SLV_S YN C2

A5 SLV_S YN C3

C 6 SLV_S YN C4

B 6 SLV_S YN C5

SLV _ SY N C 0

SLV _ SY N C 1

SLV _ SY N C 2

SLV _ SY N C 3

SLV _ SY N C 4

SLV _ SY N C 5

S

L

V

_

S

C

L

K

L

8

S

L

V

_

C

L

K

R

7

0

C 7

B 7

A6

A7

A9

N

C

D

N

F

N C

N

C

G

N

D

N

C

mXT3432S1-S

R

E

Q

_

A

M 8

L 6

L 5

NC

R E Q _ A

C T E 1 A

C T E 0 A

CT E1A

CT E0A

F

1

Y 7 6

Y 7 4

Y 7 2

Y 7 0

Y 6 8

Y 6 6

Y 6 4

Y 6 2

Y 6 0

Y 5 8

Y 5 6

Y 5 4

Y 5 2

Y 5 0

Y 4 8

Y 4 6

Y 4 4

Y 4 2

Y 4 0

Y 3 8

Y 3 6

Y 3 4

Y 3 2

Y 3 0

Y 2 8

Y 2 6

Y 2 4

Y 2 2

Y 7 6

Y 7 4

Y 7 2

Y 7 0

Y 6 8

Y 6 6

Y 6 4

Y 6 2

Y 6 0

Y 5 8

Y 5 6

Y 5 4

Y 5 2

Y 5 0

Y 4 8

Y 4 6

Y 4 4

Y 4 2

Y 4 0

Y 3 8

Y 3 6

Y 3 4

Y 3 2

Y 3 0

Y 2 8

Y 2 6

Y 2 4

Y 2 2

F

2

F

3

MATRIX Y

SCAN IN

E

1

E

2

V

D

E

3

L

7

D 2

D 3

B 1

A1

C 2

B 2

A2

C 3

B 3

A3

F8

V

D

_

I

N

P

U

T

N C

H 7

H 6

N C

NOTE: See

Section 1.2 on page 3

for details on how the

Y lines are distributed

across the slave

devices.

N C

F 6

F 7

N C

A8

B 8

C 8

C 9

A1 0

C 1 0

D 1 1

D 1 3

E 1 1

E 1 2

E 1 3

S

_

A

N 6

N 7

S

_

A

S

C

K

_

A

For Slave B

S CK _ A

M O SI_ C

B U SY _ A

C T E 2 A

MO SI _C

BUS Y _A

M 1 0

N 1 0

N 1 1

X lines: Add 32 to each line number

Y lines: Add 1 to each line number

For CTE pins:

CT E2A

CTE0A is connected to CTE1B

CTE1A is connected to CTE0B

CTE2A is connected to CTE3B

CTE3A is connected to CTE2B

For other pins:

G

N

D

Change _A to _B and

_C to _D

18

mXT3432S1

9853BX–AT42–03/13

mXT3432S1

3. Touchscreen Basics

3.1

Sensor Construction

A touchscreen is usually constructed from a number of transparent electrodes. These are typically on a

glass or plastic substrate. They can also be made using non-transparent electrodes, such as copper

or carbon. Electrodes are normally formed by etching a material called Indium Tin Oxide (ITO). This is

a brittle ceramic material, of high optical clarity and varying sheet resistance. Thicker ITO yields lower

levels of resistance (perhaps tens to hundreds of Ω/square) at the expense of reduced optical clarity.

Lower levels of resistance are generally more compatible with capacitive sensing. Thinner ITO leads

to higher levels of resistance (perhaps hundreds to thousands of Ω/square) with some of the best

optical characteristics.

Interconnecting tracks formed in ITO can cause problems. The excessive RC time constants formed

between the resistance of the track and the capacitance of the electrode to ground can inhibit the

capacitive sensing function. In such cases, ITO tracks should be replaced by screen printed

conductive inks (non-transparent) outside the touchscreen’s viewing area.

A range of trade-offs also exist with regard to the number of layers used for construction. Atmel has

pioneered single-layer ITO capacitive touchscreens. For many applications these offer a near-

optimum cost/performance balance. With a single layer screen, the electrodes are all connected

using ITO out to the edges of the sensor. From there the connection is picked up with printed silver

tracks. Sometimes two overprinted silver tracking layers are used to reduce the margins between the

edge of the substrate and the active area of the sensor.

Two-layer designs can have a strong technical appeal where ultra-narrow edge margins are required.

They are also an advantage where the capacitive sensing function needs to have a very precise cut-off

as a touch is moved to just off the active sensor area. With a two-layer design the QMatrix transmitter

electrodes are normally placed nearest the bottom and the receiver electrodes nearest the top. The

separation between layers can range from hundreds of nanometers to hundreds of microns, with the

right electrode design and considerations of the sensing environment.

3.2

Electrode Configuration

The specific electrode designs used in Atmel touchscreens are the subject of various patents

and patent applications. Further information is available on request.

The chipset supports various configurations of electrodes as summarized below:

Touchscreens:

1 Touchscreens allowed

3X x 3Y minimum (depends on screen resolution)

44X x 78Y maximum (subject to other configurations)

19

9853BX–AT42–03/13

3.3

Scanning Sequence

All channels are scanned in sequence by the chipset. There is a full parallelism in the scanning

sequence to improve overall response time. The channels are scanned by measuring capacitive

changes at the intersections formed between the first X line and all the Y lines. Then the intersections

between the next X line and all the Y lines are scanned, and so on, until all X and Y combinations have

been measured.

The chipset can be configured in various ways. It is possible to disable some channels so that they

are not scanned at all. This can be used to improve overall scanning time.

3.4

Touchscreen Sensitivity

3.4.1

Adjustment

Sensitivity of touchscreens can vary across the extents of the electrode pattern due to natural

differences in the parasitics of the interconnections, control chip, and so on. An important factor

in the uniformity of sensitivity is the electrode design itself. It is a natural consequence of a

touchscreen pattern that the edges form a discontinuity and hence tend to have a different

sensitivity. The electrodes at the far edges do not have a neighboring electrode on one side and

this affects the electric field distribution in that region.

A sensitivity adjustment is available for the whole touchscreen. This adjustment is a basic

algorithmic threshold that defines when a channel is considered to have enough signal change

to qualify as being in detect.

3.4.2

Mechanical Stackup

The mechanical stackup refers to the arrangement of material layers that exist above and below

a touchscreen. The arrangement of the touchscreen in relation to other parts of the mechanical

stackup has an effect on the overall sensitivity of the screen. QMatrix technology has an

excellent ability to operate in the presence of ground planes close to the sensor. QMatrix

sensitivity is attributed more to the interaction of the electric fields between the transmitting (X)

and receiving (Y) electrodes than to the surface area of these electrodes. For this reason, stray

capacitance on the X or Y electrodes does not strongly reduce sensitivity

Front panel dielectric material has a direct bearing on sensitivity. Plastic front panels are usually

suitable up to about 1.2 mm, and glass up to about 2.5 mm (dependent upon the screen size

and layout). The thicker the front panel, the lower the signal-to-noise ratio of the measured

capacitive changes and hence the lower the resolution of the touchscreen. In general, glass

front panels are near optimal because they conduct electric fields almost twice as easily as

plastic panels.

Note: Care should be taken using ultra-thin glass panels as retransmission effects can occur.

20

mXT3432S1

9853BX–AT42–03/13

mXT3432S1

4. Detailed Operation

4.1

Power-up/Reset

There is an internal Power-on Reset (POR) in the devices.

The device must be held in RESET (active low) while the power supplies (Vdd and AVdd) are

powering up. If a slope or slew is applied to the digital or analog supplies (Vdd, AVdd and XVdd)

must reach their nominal values before the RESET signal is de-asserted (that is, goes high).

This is shown in Figure 4-1. See Section 9.2 on page 63 for nominal values for Vdd, AVdd and

XVdd. Please note that the XVdd rail has a maximum rate of rise specification (see

Section 9.3.3 on page 64), that is, a soft-start XVdd supply must be used.

Figure 4-1. Power Sequencing on the mXT3432S1

AVdd

XVdd

>0 ns

Vdd

(Vdd)

RESET

>90 ns

Note:

1) Vdd and AVdd can be powered up in any order

2) XVdd must not be powered up until after Vdd and

must obey the rate-of-rise specification

The digital or analog (AVdd) supplies can be applied independently and in any order on the

mXT3432S1 during power-up. Vdd must be applied to the device before XVdd to ensure that the

different power domains in the device are initialized correctly. Typically this can be done by

connecting the enable pin of the Switched Mode Power Supply (SMPS) supplying XVdd to a

10 kΩ pull-up resistor connected to the Vdd, but the XVdd can be controlled separately by the

host, if required.

After power-up, the device takes <100 ms before it is ready to start communications. Vdd must

drop to below 1.45 V in order to effect a proper POR. See Section 3 on page 19 for further

specifications.

21

9853BX–AT42–03/13

If the RESET line is released before the AVDD and /or XVDD supplies have reached their

nominal voltage (see Figure 4-2), then some additional operations need to be carried out by the

host. There are two options open to the host controller:

• Start the part in deep sleep mode and then send the command sequence to set the cycle

time to wake the part and allow it to run normally. Note that in this case a calibration

command is also needed.

• Send a reset command.

Figure 4-2. Power Sequencing on the mXT3432S1 – Late rise on AVDD

RESET disasserted before AVdd/X

at nominal level

(Nom)

Avdd or

XVdd

(Nom)

Vdd

(Vdd)

RESET

The RESET pin can be used to reset the device whenever necessary. The RESET pin must be

asserted low for at least 90 ns to cause a reset. After releasing the RESET pin the device takes

~100 ms before it is ready to start communications. It is recommended to connect the RESET

pin to a host controller to allow it to initiate a full hardware reset without requiring a power-down.

Note that the voltage level on the RESET pin of the device must never exceed Vdd (digital

supply voltage).

A software reset command can be used to reset the chip (refer to the Command Processor

object in the mXT3432S 2.0 Protocol Guide). A software reset takes a maximum of

280 ms. After the chip has finished it asserts the CHG line to signal to the host that a message is

available. The reset flag is set in the Message Processor object to indicate to the host that it has

just completed a reset cycle. This bit can be used by the host to detect any unexpected

brownout events. This allows the host to take any necessary corrective actions, such as

reconfiguration.

A checksum check is performed on the configuration settings held in the nonvolatile memory. If

the checksum does not match a stored copy of the last checksum, then this indicates that the

settings have become corrupted. This is signaled to the host by setting the configuration error bit

in the message data for the Command Processor object (refer to the mXT3432S 2.0 Protocol

Guide for more information).

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mXT3432S1

Note that the CHG line is momentarily set (approximately 100 ms) as an input after power-up or

reset for diagnostic purposes. It is therefore particularly important that the line should be allowed

to float high via the CHG line pull-up resistor during this period. It should not be driven by the

host.

At power-on, the device performs a self-test routine to check for shorts which might cause

damage to the device. Refer to the Self Test T25 section of the mXT3432S 2.0 Protocol Guide

for more details about this process.

4.2

Calibration

Calibration is the process by which a sensor chip assesses the background capacitance on each

channel. Channels are only calibrated on power-up and when:

• The channel is enabled (that is, activated).

OR

• The channel is already enabled and one of the following applies:

– The channel is held in detect for longer than the Touch Automatic Calibration setting

(refer to the mXT3432S 2.0 Protocol Guide for more information on TCHAUTOCAL

setting in the Acquisition Configuration object).

– The signal delta on a channel is at least the touch threshold (TCHTHR) in the

anti-touch direction, while no other touches are present on the channel matrix (refer

to the mXT3432S 2.0 Protocol Guide for more information on the TCHTHR field in

the Multiple Touch Touchscreen object).

– The host issues a recalibrate command.

– Certain configuration settings are changed.

A status message is generated on the start and completion of a calibration.

Note that the chipset performs a global calibration; that is, all the channels are calibrated

together.

4.3

Operational Modes

The chipset operates in two modes: active (touch detected) and idle (no touches detected). Both

modes operate as a series of burst cycles. Each cycle consists of a short burst (during which

measurements are taken) followed by an inactive sleep period. The difference between these

modes is the length of the cycles. Those in idle mode typically have longer sleep periods. The

cycle length is configured using the IDLEACQINT and ACTVACQINT settings in the Power

Configuration object. In addition, an Active to Idle timeout (ACTV2IDLETO) setting is provided.

Refer to the mXT3432S 2.0 Protocol Guide for full information on how these modes operate, and

how to use the settings provided.

4.4

Touchscreen Layout

The mXT3432S1 support one Multiple Touch Touchscreen T9 object. Refer to the mXT3432S

2.0 Protocol Guide for more information on configuring the Multiple Touch Touchscreen T9

object.

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When designing the physical layout of the touch panel, obey the following rules:

– Each touch object should be in rectangular shape in terms of the lines it uses.

– The design of the touch object does not physically need to be on a strict XY grid

pattern.

4.5

Signal Processing

4.5.1

Detection Integrator

The chipset features a touch detection integration mechanism. This acts to confirm a detection

in a robust fashion. A counter is incremented each time a touch has exceeded its threshold and

has remained above the threshold for the current acquisition. When this counter reaches a

preset limit the sensor is finally declared to be touched. If, on any acquisition, the signal is not

seen to exceed the threshold level, the counter is cleared and the process has to start from the

beginning.

The detection integrator is configured using the appropriate touch object (Multiple Touch

Touchscreen T9). Refer to the mXT3432S 2.0 Protocol Guide for more information.

4.5.2

Digital Filtering and Noise Suppression

The mXT3432S1 supports the on-chip filtering of the acquisition data received from the sensor.

Specifically, the maXCharger T62 object provides an algorithm to suppress the effects of noise

(for example, from a noisy charger plugged into the user’s product). This algorithm can

automatically adjust some of the acquisition parameters on-the-fly to filter the analog-to-digital

conversions (ADCs) received from the sensor. The algorithm can make use of a Grass Cutter

(which rejects any samples outside a predetermined limit).

Noise suppression is triggered when a noise source is detected (typically when a charger is

turned on). A hardware trigger can be implemented using the CHRG_IN pin. Alternatively, the

host’s driver code can indicate when a noise source is present.

An alternative burst mode on the X lines, known as Dual X Drive, is provided. This improves the

signal-to-noise ratio (SNR) on a closely spaced X sensor matrix (when finger touches are likely

to cover more than one X line).

Refer to the mXT3432S 2.0 Protocol Guide for more information on the maXCharger T62 object.

4.5.3

4.5.4

24

Gestures

The chipset supports the on-chip processing of touches so that specific gestures can be

detected. These may be a one-touch gesture (such as a tap or a drag) or they may be a

two-touch gesture (such as a pinch or a rotate).

Gestures are configured using the One-touch Gesture Processor and the Two-touch Gesture

Processor objects. Refer to the mXT3432S 2.0 Protocol Guide for more information on gestures

and their configuration.

GPIO Pins

The mXT3432S1 has three GPIO pins. This can be set to be either an input or an output pin, as

required. The GPIO pin is configured using the GPIO/PWM Configuration T19 object.

mXT3432S1

9853BX–AT42–03/13

mXT3432S1

4.5.5

Grip Suppression

The mXT3432S1 has a grip suppression mechanism to suppress false detections when the user

grips a handheld device.

Grip suppression works by specifying a boundary around a touchscreen, within which touches

can be suppressed whilst still allowing touches in the center of the touchscreen. This ensures

that a “rolling” hand touch (such as when a user grips a mobile device) is suppressed. A “real”

(finger) touch towards the center of the screen is allowed.

Grip suppression is configured using the Grip Suppression T40 object. . Refer to the mXT3432S

2.0 Protocol Guide for more information.

4.5.6

Factory Reference

The mXT3432S1 supports using a set of known-good factory reference to eliminate problems

associated with calibrating in the presence of touches, moisture or foreign objects.

The maXStartup T66 object enables factory references to be generated and stored in a

controlled environment on the production line. These values can then be restored on calibration

instead of relying on current state of the screen which may be in contact with a touch, moisture

or foreign objects such as keys or coins. Supporting algorithms are used to compensate the

references for variations in different environments. Refer to the mXT3432S 2.0 Protocol Guide

for more information.

4.5.7

Lens Bending

The mXT3432S1 supports algorithms to eliminate disturbances from the measured signal and

also to measure the bend component.

When the sensor suffers from the screen deformation (lens bending) the signal values acquired

by normal procedure are corrupted by the disturbance component (bend). The amount of bend

depends on:

• the mechanical and electrical characteristics of the sensor

• the amount and location of the force applied by the user touch to the sensor

The Lens Bending T65 object measures the bend component and compensates for any

distortion caused by the bend. As the bend component is primarily influenced by the user touch

force, it can be used as a secondary source to identify the presence of a touch. The additional

benefit of the Lens Bending T65 object is that it will eliminate LCD noise as well. Refer to the

mXT3432S 2.0 Protocol Guide for more information.

4.5.8

Shieldless Support

The mXT3432S1 can support shieldless sensor design even with a noisy LCD. The Shieldless

T56 object provides a number of algorithms to suppress the effect of noise emitted by the

display.

The Shieldless T56 display noise suppression operates on a completely different mechanism to

the maXCharger T62 object. This allows the device to overcome display noise simultaneously

with charger noise.

The device can make use of the following mechanisms to overcome display noise:

• Optimal Integration is not filtering as such, instead it is a feature that enables the user to use

a shorter integration window. The integration window optimizes the amount of charge

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collected against the amount of noise collected, to ensure an optimal SNR. This feature also

benefits the system in the presence of an external noise source such as charger.

• The main noise suppression method for display noise is the noise canceller. The noise

canceller measures the noise generated by the display and subtracts it from the noise

cancellation feature measurement. When the noise canceller is enabled the maXCharger

T62 object cannot use the Grass Cut filter.

Refer to the mXT3432S 2.0 Protocol Guide Protocol Guide for more information on the

Shieldless T56 object.

4.5.9

Stylus Support

The mXT3432S1 allows for the particular characteristics of stylus touches, whilst still allowing

conventional finger touches to be detected. Stylus touches are configured by the Stylus T47

object..

The mXT3432S1 also supports active stylus through the Active Stylus T63 object.

For example, stylus support ensures that the small touch area of a stylus registers as a touch, as

this would otherwise by considered too small for the touchscreen. Additionally, there are controls

to distinguish a stylus touch from an unwanted approaching finger (such as on the hand holding

the stylus).

The touch sensitivity and threshold controls for stylus touches are configured separately from

those for conventional finger touches so that both types of touches can be accommodated.

4.5.10

Unintentional Touch Suppression

The Touch Suppression T42 object provides a mechanism to suppress false detections from

unintentional touches from a large body area, such as from a face, ear or palm. The Touch

Suppression T42 object also provides Maximum Touch Suppression to suppress all touches if

more than a specified number of touches has been detected. Refer to the mXT3432S 2.0

Protocol Guide for more information.

4.6

Circuit Components

4.6.1

XVdd Power Supply

The X line driver power supply XVdd can be used in two different modes:

• XVdd connected to AVdd. This mode limits the range of XVdd to 2.5 – 3.6V.

• XVdd connected to an external supply. In this configuration the external supply should be in

the range 2.5 – 10.0V. The higher voltages improve the SNR of the system.

• If XVdd < 4.75 V, please note restriction on minimum Cx in Section 9.2 on page 63.

4.6.2

Bypass Capacitors

Each power supply (Vdd, XVdd and AVdd) requires a 1 µF bypass capacitor. If the internal 1.8V

VDDCORE regulator is used, the Vdd 1 µF should be replaced with a 10 µF capacitor and a

2.2 µF capacitor should be added on the VDDCORE pin. In addition, there should be a 100 nF

bypass capacitor on each power trace. The capacitors should be ceramic X7R or X5R. See the

schematics in Section 2.3 on page 16 for more details.

The PCB traces connecting the bypass capacitors to the pins of the device must not exceed

5 mm in length. This limits any stray inductance that would reduce filtering effectiveness. See

also Section 9.12 on page 69.

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mXT3432S1

4.6.3

4.6.4

Supply Quality

While the chipset has good Power Supply Rejection Ratio properties, poorly regulated and/or

noisy power can significantly reduce performance. See Section 9.12 on page 69.

Always operate the chipset with a well-regulated and clean AVdd (and XVdd, if used) supply. It

supplies the sensitive analog stages in the chipset. See Figure 9-1 on page 78 for an example

XVdd supply.

Supply Sequencing

Vdd and AVdd can be powered independently of each other without damage to the chipset. Vdd

must be applied to the device before XVdd to ensure proper initialization of the device. All

voltage ranges should be used with in the limits specified in Section 9.2 on page 63.

Make sure that any lines connected to the chipset are below or equal to Vdd during power-up.

For example, if RESET is supplied from a different power domain to the mXT3432S1 VDD pin,

make sure that it is held low when Vdd is off. If this is not done, the RESET signal could

parasitically couple power via the mXT3432S1 RESET pin into the Vdd supply.

4.6.5

4.6.6

Decoupling Requirements

See also the schematics in Section 2.3 on page 16.

PCB Cleanliness

Modern no-clean-flux is generally compatible with capacitive sensing circuits.

CAUTION: If a PCB is reworked to correct soldering faults relating to any of

the chipset devices, or to any associated traces or components, be sure that you

fully understand the nature of the flux used during the rework process. Leakage

currents from hygroscopic ionic residues can stop capacitive sensors from

functioning. If you have any doubts, a thorough cleaning after rework may be the

only safe option.

4.7

4.8

PCB Layout

Debugging

See Appendix A on page 76 for general advice on PCB layout.

The chipset provides a mechanism for obtaining raw data for development and testing purposes

by reading data from the Diagnostic Debug T37 object. Refer to the mXT3432S 2.0 Protocol

Guide for more information on this object.

A second mechanism is provided that allows the host to read the real-time raw data using the

low-level debug port. This can be accessed via the SPI interface or the USB interface. Note that

if both (HID)I²C-compatible and USB interfaces are connected to the host at the same time, the

debug data is output on the USB interface. Refer to QTAN0050, Using the maXTouch Debug

Port, for more information on the debug port.

There is also a Self Test T25 object that runs self-test routines in the mXT3432S1 to find

hardware faults on the sense lines and the electrodes. This object also performs an initial pin

fault test on power-up to ensure that there is no X-to-Y short before the high-voltage supply is

enabled inside the chip. A high-voltage short into the analog circuitry would break the device.

Refer to the mXT3432S 2.0 Protocol Guide and QTAN0059, Using the maXTouch Self Test

Feature, for more information on the Self Test T25 object.

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4.9

Communications

Communication with the host is achieved using either the I²C-compatible interface (see

Section 5 on page 29), the HID-I²C-compatible interface (see Section 7 on page 50), or the USB

interface (see Section 6 on page 37). Any interface can be used, depending on the needs of the

user’s project, but only one interface should be used in any one design. The selection of the I²C

or the HID-I²C protocol of the I²C interface is determined by the I2CMODE pin.

The interface is selected using the COMMSEL pin. Connect COMMSEL to Vdd to select the

USB interface, or to GND to select one of the two I²C-compatible interfaces.

Note that you only need to connect those pins that are actually required for use with the chosen

communications interface. This ensures optimal power consumption and correct functioning.

See Section 2.2 on page 7 for details on what should be done with the unconnected pins.

4.10 Configuring the Chipset

The chipset has an object-based protocol that organizes the features of the chipset into objects

that can be controlled individually. This is configured using the Object Protocol common to many

of Atmel’s touch sensor devices. For more information on the Object Protocol and its

implementation on the chipset, refer to the mXT3432S 2.0 Protocol Guide.

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5. I²C-compatible Communications

5.1

Communications Protocol

The chipset can use an I²C-compatible interface for communication. See Appendix D on

page 84 for details of the I²C-compatible protocol.

The I²C-compatible interface is used in conjunction with the CHG line. The CHG line going

active signifies that a new data packet is available. This provides an interrupt-style interface and

allows the chipset to present data packets when internal changes have occurred.

5.2

I²C-compatible Addresses

The chipset supports four I²C-compatible device addresses. These are selected at start-up

using the A0 and A1 pins on the mXT3432S-M master device (see Table 5-1). The address pins

should be connected to GND to signal a logic “0”, and either left open or connected to VDD_3v3

to signal a logic 1 ⁽¹⁾

I²C-compatible Device Addresses

.

Table 5-1.

A1

0

A0

Address

0x4C

0

1

0

1

0

0x4D

1

0x5A

1

0x5B

The addresses are shifted left to form the SLA+W or SLA+R address when transmitted over the

I²C-compatible interface (see Table 5-2).

Table 5-2.

Format of SLA+W and SLA+R

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Address (see Table 5-1)

Read/write

5.3

Writing To the Chipset

A WRITE cycle to the chipset consists of a START condition followed by the I²C-compatible

address of the device (SLA+W). The next two bytes are the address of the location into which

the writing starts. The first byte is the Least Significant Byte (LSByte) of the address, and the

second byte is the Most Significant Byte (MSByte). This address is then stored as the address

pointer.

Subsequent bytes in a multi-byte transfer form the actual data. These are written to the location

of the address pointer, location of the address pointer +1, location of the address pointer + 2,

and so on. The address pointer returns to its starting value when the WRITE cycle’s STOP

condition is detected.

Figure 5-1 shows an example of writing four bytes of data to contiguous addresses starting at

0x1234.

1. No external pull-down resistors are required on the A0 and A1 pins.

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Figure 5-1. Example of a Four-byte Write Starting at Address 0x1234

0x12

START SLA+W

0x34

0x96

0x9B

0xA0

0xA5

STOP

Write Address

(LSB, MSB)

Write Data

5.4

I²C-compatible Writes in Checksum Mode

In I²C-compatible checksum mode an 8-bit CRC is added to all I²C-compatible writes. The CRC

is sent at the end of the data write as the last byte before the STOP condition. All the bytes sent

are included in the CRC, including the two address bytes. Any command or data sent to the

chipset is processed even if the CRC fails.

To indicate that a checksum is to be sent in the write, the most significant bit of the MSByte of

the address is set to 1. For example, the I²C-compatible command shown in Figure 5-2 writes a

value of 150 (0x96) to address 0x1234 with a checksum. The address is changed to 0x9234 to

indicate checksum mode.

Figure 5-2. Example of a Write To Address 0x1234 With a Checksum

Checksum

START SLA+W

0x34

0x92

0x96

STOP

Write Address

(LSB, MSB)

Write Data

5.5

Reading From the Chipset

Two I²C-compatible bus activities must take place to read from the chipset. The first activity is an

I²C-compatible write to set the address pointer (LSByte then MSByte). The second activity is the

actual I²C-compatible read to receive the data. The address pointer returns to its starting value

when the read cycle’s NACK is detected.

It is not necessary to set the address pointer before every read. The address pointer is updated

automatically after every read operation. The address pointer will be correct if the reads occur in

order. In particular, when reading multiple messages from the Message Processor T5 object, the

address pointer is automatically reset to allow continuous reads (see Section 5.6).

The WRITE and READ cycles consist of a START condition followed by the I²C-compatible

address of the device (SLA+W or SLA+R respectively).

Figure 6-10 shows the I²C-compatible commands to read four bytes starting at address 0x1234.

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Figure 5-3. Example of a Four-byte Read Starting at Address 0x1234

Set Address Pointer

START SLA+W

0x34

0x12

STOP

Read Address

(LSB, MSB)

Read Data

START SLA+R

0x96

0x9B

0xA0

0xA5

STOP

Read Data

5.6

Reading Status Messages with DMA

The device facilitates the easy reading of multiple messages using a single continuous read

operation. This allows the host hardware to use a direct memory access (DMA) controller for the

fast reading of messages, as follows:

1. The host uses a write operation to set the address pointer to the start of the Message

Count T44 object, if necessary. ⁽¹⁾If a checksum is required on each message, the most

significant bit of the MSByte of the read address must be set to 1.

2. The host starts the read operation of the message by sending a START condition.

3. The host reads the Message Count T44 object (one byte) to retrieve a count of the

pending messages (refer to the mXT3432S 2.0 Protocol Guide for details).

4. The host calculates the number of bytes to read by multiplying the message count by

the size of the Message Processor T5 object. ⁽²⁾

Note that the size of the Message Processor T5 object as recorded in the Object Table

includes a checksum byte. If a checksum has not been requested, one byte should be

deducted from the size of the object. That is: number of bytes = count x (size-1).

5. The host reads the calculated number of message bytes. It is important that the host

does not send a STOP condition during the message reads, as this will terminate the

continuous read operation and reset the address pointer. No START and STOP

conditions must be sent between the messages.

6. The host sends a STOP condition at the end of the read operation after the last

message has been read. The NACK condition immediately before the STOP condition

resets the address pointer to the start of Message Count T44 object.

Figure 5-4 on page 32 shows an example of using a continuous read operation to read three

messages from the device without a checksum. Figure 5-5 on page 33 shows the same

example with a checksum.

1. The STOP condition at the end of the read resets the address pointer to its initial location, so it may already be pointing

at the Message Count T44 object following a previous message read.

2. The host should have already read the size of the Message Processor T5 object in its initialization code.

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Figure 5-4. Continuous Message Read Example – No Checksum

Set Address Pointer

START SLA+W

LSB

MSB

STOP

Start Address of

Message Count Object

Read Message Count

Continuous

Read

START SLA+R Count = 3

Message Count Object

Read Message Data

(size – 1) bytes

Report ID

Data

Message Processor Object – Message # 1

Report ID

Data

Message Processor Object – Message # 2

Report ID

Data

STOP

Message Processor Object – Message # 3

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Figure 5-5. Continuous Message Read Example – I²C-compatible Checksum Mode

Set Address Pointer

MSB |

0x80

Checksum

START SLA+W

LSB

STOP

Start Address of

Message Count Object

Read Message Count

START SLA+R Count = 3

Continuous

Read

Message Count Object

Read Message Data

size bytes

Report ID

Checksum

Data

Message Processor Object – Message # 1

Report ID

Checksum

Data

Message Processor Object – Message # 2

Report ID

Checksum

Data

STOP

Message Processor Object – Message # 3

There are no checksums added on any other I²C-compatible reads. An 8-bit CRC can be added,

however, to all I²C-compatible writes, as described in Section 5.4 on page 30.

An alternative method of reading messages using the CHG line is given in Section 5.7.

5.7

CHG Line

The CHG line is an active-low, open-drain output that is used to alert the host that a new

message is available in the Message Processor T5 object. This provides the host with an

interrupt-style interface with the potential for fast response times. It reduces the need for

wasteful I²C-compatible communications.

The CHG line remains low as long as there are messages to be read. The host should be

configured so that the CHG line is connected to an interrupt line that is level-triggered. The host

should not use an edge-triggered interrupt as this means adding extra software precautions.

The CHG line should be allowed to float during normal usage. This is particularly important after

power-up or reset (see Section 4.1 on page 21).

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A pull-up resistor is required, typically 10 kΩ to Vdd.

The CHG line operates in two modes, as defined by the Communications Configuration T18

object (refer to the mXT3432S 2.0 Protocol Guide).

Mode 0

NA

CK

ACK

I²C-compatible Interface

.

STA

RT

SLA-

R

B

0

B

1

B

n

B

0

B

1

B

n

B

0

B

1

B

n

STO

P

Message

Message #1

Message #2

#m

CHG Line

.

CHG line high or low; see text

Mode 1

I²C-compatible Interface

ACK

.

STA

RT

SLA-

R

B

0

B

1

B

n

B

0

B

1

B

n

B

0

B

1

B

n

STO

P

Message

Message #1

Message #2

#m

CHG Line

.

CHG line high or low; see text

In Mode 0:

1. The CHG line goes low to indicate that a message is present.

2. The CHG line goes high when the first byte of the first message (that is, its report ID)

has been sent and acknowledged (ACK sent) and the next byte has been prepared in

the buffer.

3. The STOP condition at the end of an I²C-compatible transfer causes the CHG line to

stay high if there are no more messages. Otherwise the CHG line goes low to indicate a

further message.

Mode 0 allows the host to continually read messages. Messaging reading ends when a report ID

of 255 (“invalid message”) is received. Alternatively the host ends the transfer by sending a

NACK after receiving the last byte of a message, followed by a STOP condition. If and when

there is another message present, the CHG line goes low, as in step 1. In this mode the state of

the CHG line does not need to be checked during the I²C-compatible read.

In Mode 1:

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1. The CHG line goes low to indicate that a message is present.

2. The CHG line remains low while there are further messages to be sent after the current

message.

3. The CHG line goes high again only once the first byte of the last message (that is, its

report ID) has been sent and acknowledged (ACK sent) and the next byte has been

prepared in the output buffer.

Mode 1 allows the host to continually read the messages until the CHG line goes high, and the

state of the CHG line determines whether or not the host should continue receiving messages

from the chipset.

Note: The state of the CHG line should be checked only between messages and not between

the bytes of a message. The precise point at which the CHG line changes state cannot

be predicted and so the state of the CHG line cannot be guaranteed between bytes.

The Communications Configuration T18 object can be used to configure the behavior of the

CHG line. In addition to the CHG line operation modes described above, this object allows the

use of edge-based interrupts, as well as direct control over the state of the CHG line. Refer to

the mXT3432S 2.0 Protocol Guide for more information.

5.8

WAKE Line

The WAKE line is an active-low input that is used to wake the mXT3432S1 up from deep sleep

mode before communicating with it via the I²C-compatible interface. It can be used to minimize

current consumption when the mXT3432S1 is in deep sleep mode. Refer to the mXT3432S 2.0

Protocol Guide for information on deep sleep mode.

Note that the WAKE line is not used when the mXT3432S1 is not in deep sleep mode.

This pin must be connected in one of the following ways:

• It can be connected to the I²C-compatible SCL pin.

• It can be connected to a GPIO pin on the host.

• It can also be left permanently low (connected to GND), but at the expense of increased

power consumption in deep sleep mode.

The mXT3432S1 is ready to accept I²C-compatible communications 25 ms after the WAKE line

is asserted. This means that if the WAKE line is connected to a GPIO line, the line must be

asserted 25 ms before the host attempts to communicate with the mXT3432S1.

If the WAKE line is connected to the SCL pin, the mXT3432S1 will send a NACK on the first

attempt to address it; the host must then retry 25 ms later.

The mXT3432S1 remains ready to accept I²C-compatible communications for 2 seconds after

the WAKE line is asserted, after which time the chip will timeout and return to deep sleep mode.

This timeout period is reset every time there is an I²C-compatible communication with the

mXT3432S1, or if the WAKE line is held asserted.

Note that when the mXT3432S1 is sent into deep sleep mode, it goes to sleep immediately. In

this case the two-second timeout does not apply until the WAKE pin is asserted.

In USB mode, (that is, when the I²C-compatible interface is not being used), the WAKE pin

should be connected to Vdd.

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5.9

SDA, SCL

The I²C-compatible bus transmits data and clock with SDA and SCL, respectively. These are

open-drain. The device can only drive these lines low or leave them open. The termination

resistors (Rp) pull the line up to Vdd if no I²C-compatible device is pulling it down.

The termination resistors should be chosen so that the rise times on SDA and SCL meet the I²C-

compatible specifications for the interface speed being used, bearing in mind other loads on the

bus, (see Section 9.8 on page 68).

5.10 Clock Stretching

The chipset supports clock stretching in accordance with the I²C specification. It may also

instigate a clock stretch if a communications event happens during a period when the chipset is

busy internally.

The chipset has an internal bus monitor that can reset the internal I²C-compatible hardware if

SDA or SCL is stuck low for more than 200 ms. This means that if a prolonged clock stretch of

more than 200 ms is seen by the chipset, then any ongoing transfers with the chipset may be

corrupted. The bus monitor is enabled or disabled using the Communications Configuration T18

object. Refer to the mXT3432S 2.0 Protocol Guide for more information.

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6. USB Communications

6.1

Communications Protocol

The chipset is a composite USB device with two Human Interface Device (HID) interfaces:

• Interface 0 – This interface provides a Digitizer HID that supplies touch information to the

Host for passing on to a PC’s operating system. This interface is supported by Microsoft^®

Windows^®8 without the need for additional software. The HID identifier string is

“Atmel maXTouch Digitizer”.

• Interface 1 – This interface provides a Generic HID that allows the host to communicate with

the chipset using the Object Protocol. The HID identifier string is “Atmel maXTouch Control”.

The topography of the USB device is shown in Figure 6-1.

Figure 6-1. USB Topography

Endpoint 0

(Control)

Composite Device

Interface 0

“Atmel maXTouch Digitizer”

(Digitizer HID)

Interface 1

“Atmel maXTouch Control”

(Generic HID)

Endpoint 3

Endpoint 1

(In)

Endpoint 2

(Out)

(In)

Communication takes place using Full-speed USB at 12 Mbps.

For more information on the USB HID specifications visit www.usb.org.

6.2

Endpoint Addresses

The endpoint addresses are listed in Table 6-1.

Table 6-1.

Endpoint

Endpoint 0

Endpoint 1

Endpoint 2

Endpoint 3

Endpoint Addresses

Direction

Address

–

Bidirectional (control)

In

0x81

0x02

0x83

Out

In

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6.3

Composite Device

The composite device is a USB 2.0-compliant USB composite device running at full speed

(12 Mbps). It has the following specification:

Vendor ID:

Product ID:

Version:

0x03EB (Atmel)

0x2136 (mXT3432S1)

16-bit Version & Build Identifier in the form 0xVVBB, where:

VV = Version Major (Upper 4 bits) / Minor (Lower 4 bits)

BB = Build number in BCD format

The composite device has one bidirectional endpoint: the Control Endpoint (Endpoint 0). It is

used by the USB Host to interrogate the USB device for details on its configurations, interfaces

and report structures. It is also used to apply general device settings relating to USB

Implementation.

6.4

Interface 0 (Digitizer HID)

6.4.1

Normal Touch Report

Interface 0 is a Digitizer-class HID, compliant with HID specification 1.11 with amendments. ⁽¹⁾

This interface consists of a single interrupt-In endpoint (Endpoint 3).

The format of an input report is shown in Figure 6-3. Each input report start with a USB Report

ID ⁽²⁾(value 0x01). This is followed by 6 sets of data (11 bytes each) that describe the status of

up to 5 active touches. The input report is terminated by a single byte that contains the number

of active touches.

Figure 6-2. Input Report Packet

Touch 1

(11bytes)

Touch 2

(11bytes)

Touch 3

(11bytes)

Touch 4

(11bytes)

Touch 5

(11bytes)

Scan

Time

Count

0x01

USB

Active Touch Status Data

Report ID

Any unused touch data bytes are set to zero (for example, the data for one active touch would

be followed by 56 zeroed bytes). If there are more than five active touches to be reported, a

further input report is sent with the remaining touch data. In this case, the count (for all touches)

is sent in the last count byte and the count byte in the first report is zero. An example of the input

report packets for 7 active touches is shown in Figure 6-3 on page 39.

1. This is an implementation of Microsoft’s USB HID specification for Multitouch digitizers.

2. The term USB Report ID should not be confused with the term Report Id as used in the Object Protocol; the two are

entirely different concepts.

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Figure 6-3. Example Input Report Packets for 7 Active Touches

Touch 1

(11bytes)

Touch 2

(11bytes)

Touch 3

(11bytes)

Touch 4

(11bytes)

Touch 5

(11bytes)

Scan

Time

Count=7

0

0x01

Touch 6

(11bytes)

Touch 7

(11bytes)

0

Scan

Time

(11bytes)

USB

Active Touch Status Data

Report ID

The input report format depends on the geometry calculation field (TCHGEOMEN) of the

Digitizer HID Configuration T43 object. Table 6-3 and Table 6-3 gives the detailed format of an

input report packet..

Table 6-2.

Input Report Format when TCHGEOMEN is Enabled

Byte

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0

USB Report ID

1

Touch ID (first touch)

Reserved

Status

2

X Position LSByte (first touch)

X Position MSBits (first touch)

X’ Position LSByte (first touch)

3

0

4

5

0

X’ Position MSBits (first touch)

6

7

Y Position LSByte (first touch)

0

Y Position MSBits (first touch)

8

Y’ Position LSByte (first touch)

9

0

Y’ Position MSBits (first touch)

10

Touch width

Touch height

11

12 – 22

23 – 33

34 – 44

45 – 55

56 – 57

58

Touch data for second touch – same format as bytes 1 – 11

Touch data for third touch – same format as bytes 1 – 11

Touch data for fourth touch – same format as bytes 1 – 11

Touch data for fifth touch – same format as bytes 1 – 11

Scan time

Contact count

Table 6-3.

Input Report Format when TCHGEOMEN is Disabled

Byte

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0

1

USB Report ID

Touch ID (first touch)

Reserved

Status

2

X Position LSByte (first touch)

X Position MSBits (first touch)

3

0

4 – 5

Reserved

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Table 6-3.

Byte

Input Report Format when TCHGEOMEN is Disabled

Bit 7

Bit 6

Bit 5

Bit 4

Y Position LSByte (first touch)

Y Position MSBits (first touch)

Bit 3

Bit 2

Bit 1

Bit 0

6

7

0

8 – 9

Reserved

10 –11

12 – 22

23 – 33

34 – 44

45 – 55

56 – 57

58

Touch data for second touch – same format as bytes 1 – 11

Touch data for third touch – same format as bytes 1 – 11

Touch data for fourth touch – same format as bytes 1 – 11

Touch data for fifth touch – same format as bytes 1 – 11

Scan time

Contact count

In Table 6-3:

• Byte 1:

Status: 1 = In detect, 0 = Not in detect.

Touch ID: Identifies the touch for which this is a status report (starting from 1).

• Bytes 2 to 9:

X and Y positions: These are scaled to 12-bit resolution. This means that the upper

four bits of the MSByte will always be zero.

Bytes 4, 5, 8, 9, 10 and 11 are Reserved when TCHGEOMEN field is set to 0.

• Byte 10:

Touch Width: Reports the width of the detected touch.

• Byte 11:

Touch Height: Reports the height of the detected touch.

• Byte 56 to 57:

Scan Time: Timestamp associated with the current report frame with a 10 kHz

resolution.

Note that the scan time for each report packet of a single frame is same.

• Byte 58:

Contact Count: Non-zero value in the first report packet of a frame indicating the

total number of report packets in the frame. Zeros in the subsequent report packets

within the frame.

6.4.2

Active maXStylus Report

The format of an active maXStylus report is shown in Figure 6-4. Each input report start with a

USB Report ID ⁽¹⁾(value 0x03).

1. The term USB Report ID should not be confused with the term Report Id as used in the Object Protocol; the two are

entirely different concepts.

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Figure 6-4. Active maXStylus Report Packet

Touch 1

(10 bytes)

0x03

USB

Report ID

Active

maXStylus

Data

Table 6-4 gives the detailed format of an active stylus report packet

Table 6-4.

Active maXStylus Report Format

Byte

0

Bit 7

Bit 6

Bit 5

Bit 4

USB Report ID

In Range Reserved

Bit 3

Bit 2

Bit 1

Bit 0

1

Reserved

Eraser

Barrel

Tip

2

X Position

X Center Position

Y Position

3

4

5

6

7

8

Y Center Position

Tip Pressure

9

10

• Byte 1:

Tip: 1 = Contact of the stylus with the touch screen surface, 0 = No contact

Barrel: 1 = Barrel button on, 0 = Barrel button off

Eraser: 1 = Eraser function on, 0 = Eraser function off

In Range: 1 = Stylus approaching the touchscreen detected, 0 = No stylus

approaching the touchscreen detected.

• Byte 2 to 3:

X position

• Byte 4 to 5:

X center position

• Byte 6 to7:

Y position

• Byte 8 to 9:

Y center position

• Byte 10:

Tip Pressure: Force exerted against the touch screen surface by the stylus.

There are two update conditions:

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• Change: A change in status of any contact (touch) triggers a touch update message to be

sent to the host.

• Idle: The idle delay of the Digitizer Interface may be controlled via the Control Endpoint as

per the HID 1.11 specification (Set Idle command). By default this is set to a delay of

2 (8 ms).

6.5

Interface 1 (Generic HID)

Interface 1 is a Generic Human Interface Device, compliant with HID specification 1.11 with

amendments. ⁽¹⁾

It consists of two endpoints: an interrupt-In endpoint (Endpoint 1) and an interrupt-out endpoint

(Endpoint 2). The data packet in each case contains a 1-byte USB Report ID followed by 63

bytes of data, totalling 64 bytes (see Figure 6-5).

Figure 6-5. Data Packet for Interface 1

0x01

Data 0

Data 1

Data 62

USB

Packet Data

Report ID

Commands are sent by the application software over the Interrupt-out endpoint, Endpoint 2. The

command is sent as the first data byte of the packet data (data byte 0), followed by conditions

and/or data.

The supported commands are as follows:

• Read/write Memory Map

• Send Auto-return messages

• Start debug monitoring

• End debug monitoring

Responses from the device are sent via the interrupt-In endpoint, Endpoint 1.

6.5.1

Read/Write Memory Map

Introduction

6.5.1.1

This command is used to carry out a write/read operation on the memory map of the chipset.

The USB Report ID is 0x01.

The command packet has the generic format given in Figure 6-6. The following sections give

examples on using the command to write to the memory map and to read from the memory map.

1. This is an implementation of Microsoft’s USB HID specification for Multitouch digitizers.

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Figure 6-6. Generic Command Packet Form

0x51

Addr0

NumWx

NumRx

Addr1

Data 0

Data 57

0x01

USB

Report ID

Command

ID

Number of Bytes

to Write / Read

Address Pointer

(LSB, MSB)

Write Data

In Figure 6-6:

• NumWx is the number of data bytes to write to the memory map (may be zero). If the

address pointer is being sent, this must include the size of the address pointer.

• NumRx is the number of data bytes to read from the memory map (may be zero).

• Addr 0 and Addr 1 form the address pointer to the memory map (where necessary; may be

zero if not needed).

• Data 0 to Data 57 are the bytes of data to be written (in the case of a write). Note that data

locations beyond the number specified by NumWx will be ignored.

The response packet has the generic format given in Figure 6-7.

Figure 6-7. Response Packet Format

NumRx

0x01

Status

Data 0

Data 60

USB

Report ID

Result Number of

Bytes Read

Read Data

In Figure 6-7:

• Status indicates the result of the command:

0x00 = read and write completed; read data returned

0x04 = write completed; no read data requested

• NumRx is the number of bytes following that have been read from the memory map (in the

case of a read). This will be the same value as NumRx in the command packet.

• Data 0 to Data 60 are the data bytes read from the memory map.

6.5.1.2

Writing To the Chipset

A write operation cycle to the chipset consists of sending a packet that contains six header

bytes. These specify the USB report ID, the Command ID, the number of bytes to read, the

number of bytes to write, and the 16-bit address pointer.

Subsequent bytes in a multibyte transfer form the actual data. These are written to the location

of the address pointer, location of the address pointer +1, location of the address pointer + 2,

and so on.

Figure 6-8 shows an example command packet to write four bytes of data to contiguous

addresses starting at 0x1234.

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Figure 6-8. Example of a Four-byte Write Starting at Address 0x1234

0x01

0x06

0x00

0x34

0x12

0x96

0x9B

0xA0

0xA5

0x51

USB

Report ID

Number Number

of Bytes of Bytes

to Write to Read

Address Pointer

(LSB, MSB)

Write Data

Command

ID

In Figure 6-8:

• The number of bytes to read is set to zero as this is a write-only operation.

• The number of bytes to write is six: that is, four data bytes plus the two address pointer bytes.

Figure 6-9 shows the response to this command. Note that the result status returned is 0x04

(that is, the write operation was completed but no read data was requested).

Figure 6-9. Response to Example Four-byte Write

0x01

0x04

USB

Result

Report ID

6.5.1.3

Reading From the Chipset

A read operation consists of sending a packet that contains the six header bytes only and no

write data.

Figure 6-10 shows an example command packet to read four bytes starting at address 0x1234.

Note that the address pointer is included in the number of bytes to write, so the number of bytes

to write is set to 2 as there are no other data bytes to be written.

Figure 6-10. Example of a Four-byte Read Starting at Address 0x1234

0x01

0x51

0x02

0x04

0x34

0x12

USB Command

Number Number

of Bytes of Bytes

to Write to Read

Address Pointer

(LSB, MSB)

Report ID

ID

It is not necessary to set the address pointer before every read. The address pointer is updated

automatically after every read operation, so the address pointer will be correct if the reads occur

in order.

Figure 6-11 shows the response to this command. The result status returned is 0x00 (that is the

write operation was completed and the data was returned). The number of bytes returned will be

the same as the number requested (4 in this case).

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Figure 6-11. Response to Example Four-byte Read

0x01

0x00

0x04

0x96

0x9B

0xA0

0xA5

USB

Report ID

Result

Number

of Bytes

Read

Read Data

6.5.2

Send Auto-return Messages

6.5.2.1

Introduction

With this command the chipset can be configured to return new messages from the Message

Processor T5 object autonomously. The packet sequence to do this is shown in Figure 6-12.

Figure 6-12. Packet Sequence for “Send Auto-return” Command.

Host

Chipset

“Send Auto-return” Command Packet

Response Packet

Message Data Packet

:

Message Data Packet

Null Packet to Terminate

The USB Report ID is 0x01.

The command packet has the format given in Figure 6-13.

Figure 6-13. Command Packet Format

0x01

0x88

Res 0

Res 1

Res 2

Res 3

Res 4

Res 5

Command

ID

USB

Report ID

Reserved Bytes

(=0x00)

In Figure 6-13:

• Res 0 to Res 5 are reserved bytes with a value of 0x00.

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The response packet has the format given in Figure 6-14. Note that with this command, the

command packet does not include an address pointer as the chipset already knows the address

of the Message Processor T5 object.

Figure 6-14. Response Packet Format

0x88

0x00

0x01

Command

Received

USB

Report ID

Once the chipset has responded to the command, it starts sending message data. Each time a

message is generated in the Message Processor T5 object, the chipset automatically sends a

message packet to the host with the data. The message packets have the format given in

Figure 6-15.

Figure 6-15. Message Packet Format

0xFA

0x00

Rpt ID

Data 0

Data n

0x01

USB

Report ID

ID Bytes

Message

Report ID

Message Data

In Figure 6-15:

• ID Bytes identify the packet as an auto-return message packet.

• Rpt ID is the Report ID returned by the Message Processor T5 object. ⁽¹⁾

• Message Data bytes are the bytes of data returned by the Message Processor. The size of

the data depends on the source object for which this is the message data. Refer to the

mXT3432S 2.0 Protocol Guide for more information.

To stop the sending of the messages, the host can send a null command packet. This consists

of two bytes: a report ID of 0x01 and a command byte of 0x00 (see Figure 6-16).

Figure 6-16. Null Command Packet Format

0x01

0x00

Null

USB

Report Command

ID ID

Note that the “Start Debug Monitoring” command may also terminate any currently enabled

auto-return mode (see Section 6.5.3).

1. This is the Report ID used in the Object Protocol and should not be confused with the USB Report ID. Refer to the

mXT3432S 2.0 Protocol Guide for more information on the use of Report IDs in the Object Protocol.

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6.5.2.2

Reading Status Messages

Figure 6-10 shows an example sequence of packets to receive messages from the Message

Processor T5 object using the “Send Auto-return” command.

Figure 6-17. Example Auto-return Command Packet

Send Auto-return Command

0x88

0x00

0x01

Message Data

USB Command

Report

ID

Response From Chip Set

0x01

0x88

0x00

Command

Received

Read Message Data

0x01

0xFA

0x00

0x02

0x11

0xC0

0x03

0x1A

0x1E

0x06

0x00

0x4F

0x00

0x1C

0x10

0x01

0x1C

ID Bytes

Message

Report ID

Message Data

Send Null Command To Terminate

0x01

0x00

Null

6.5.3

Start Debug Monitoring

This command instructs the device to return debug-monitoring data packets using the debug

port, if this feature has been enabled in the Command Processor T6 object.

The USB Report ID can be either 0x01 or 0x02. This allows the source of the request to be

identified. The main difference is that a USB Report ID of 0x01 will terminate any currently

enabled auto-return mode (see Section 6.5.2 on page 45).

The command packet has the format given in Figure 6-18.

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Figure 6-18. Command Packet Format

0x01or

0x02

0xE1

USB

Report

ID

Command

ID

The response packet has the format given in Figure 6-19. Note that the USB Report ID will be

the same as that used in the command packet.

Figure 6-19. Response Packet Format

0x01 or

0x02

0xE1

USB

Report

ID

Command

Received

The debug data packet has the format given in Figure 6-20.

Figure 6-20. Debug Data Packet Format

Packet

Num

Packets

Frame

Num

Data 0

Data 59

0x02

USB

Debug Data

Report ID

In Figure 6-20:

• PacketNum is the number of this USB packet in the debug data frame (full set of debug

data). Refer to QTAN0050, Using the maXTouch Debug Port, for more information on the

format of the debug data.

• NumPackets is the total number of USB packets that make up a debug data frame.

• FrameNum is the ID number of this frame.

• Data 0 to Data 59 are 59 bytes of debug data.

6.5.4

Stop Debug monitoring

This command instructs the device to cease returning debug-monitoring data packets.

The command packet has the following format:

The USB Report ID is either 0x01 or 0x02.

The command packet has the format given in Figure 6-21.

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Figure 6-21. Command Packet Format

0x01 or

0x02

0xE2

USB

Report

ID

Command

ID

The response packet has the format given in Figure 6-22.

Figure 6-22. Response Packet Format

0x01 or

0x02

0xE2

USB

Report

ID

Command

Received

6.6

USB Suspend Mode

When the mXT3432S1 is used in USB configuration, the USB “System Suspend” event can be

used to minimize current consumption. Note that it is possible to put the mXT3432S1 into deep

sleep mode without also sending a “System Suspend” event on the USB bus, but the current

consumption is not as low. The USB controller must send a USB “System Wake Up” event on

the bus to bring the mXT3432S1 out of suspend mode.

The mXT3432S1 can also be configured to respond to USB “Remote Wakeup” requests. In this

case, if the operating system enables remote wakeup and the mXT3432S1 is suspended, the

chipset will continue to scan at a preset sensor refresh rate. Use of the remote wake up feature

and the sensor refresh rate are configured using the Digitizer HID Configuration T43 object

(refer to the mXT3432S 2.0 Protocol Guide for more information).

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7. HID-I²C-compatible Communications

7.1

Communications Protocol

The chipset is an HID-I²C DEVICE presenting two top-level collections (TLCs):

Interface 0 (Digitizer HID-I²C) – supplies touch information to the host. This interface is

supported by Microsoft Windows 8 without the need for additional software.

Interface 1 (Generic HID-I²C) – This interface provides a generic HID-I²C interface that allows

the host to communicate with the chipset using the object protocol.

To use the device in HID-I²C mode, the I2CMODE pin should be pulled low. Other features are

identical to standard I²C communication described in Section 5.2 on page 29.

7.2

7.3

I²C-compatible Addresses

See Section 5.2 on page 29.

Device

The device is compliant with HID-I²C specification V0.9. It has the following specification:

Vendor ID:

Product ID:

Version:

0x03EB (Atmel)

0x2136

16-bit Version & Build Identifier in the form 0xVVBB, where:

VV = Version Major (Upper 4 bits) / Minor (Lower 4 bits)

BB = Build number in BCD format

HID descriptor address:

0x0000.

7.4

Interface 0 (Digitizer HID-I²C)

Interface 0 is a digitizer class HID.

7.4.1

Normal Touch Report

The format of an input report is shown in Figure 7-1. Each input report starts with a report ID and

each input report message report contains data of one touch.

Figure 7-1. Input Report Packet

Touch 1

(14 bytes)

Scan Time

(2 bytes)

Count

0x01

HID-I²C

Report ID

Touch

Status

Data

An example of the input report packets for 3 active touches is shown in Figure 6-3 on page 39.

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Figure 7-2. Example Input Report Packets for 3 Active Touches

Touch 1

(14 bytes)

Scan Time

(2 bytes)

Count = 3

Count = 0

0x01

Touch 2

(14 bytes)

Scan Time

(2 bytes)

Touch 3

(14 bytes)

Scan Time

(2 bytes)

HID-I²C

Report ID

Touch

Status

Data

Each input report consists of a HID-I²C report ID followed by 17 bytes of that describe the status

of one active touch. The input report format depends on the geometry calculation field

(TCHGEOMEN) of the Digitizer HID Configuration T43 object. Table 7-2 and Table 7-2 explains

the detailed format of an input report packet.

Table 7-1.

Input Report Format when TCHGEOMEN = 1

Byte

0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

HID-I2C Report ID

Reserved

1

Status

2

Touch ID

3 – 4

5 – 6

7 – 8

9 – 10

11

X Position

X’ Position

Y Position

Y’ Position

Touch Width

Reserved

12

13

Touch Height

Reserved

14

15 – 16

17

Scan Time

Number of active touches to be sent in one package

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Table 7-2.

Input Report Format when TCHGEOMEN = 0

Byte

0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

HID-I2C Report ID

Reserved

1

Status

2

Touch ID

3 – 4

5 – 6

7 – 8

9 – 10

11

X Position

Reserved

Y Position

Reserved

12

Reserved

13

Reserved

14

Reserved

15 – 16

17

Scan Time

Contact Count

• Byte 2:

Touch ID: Identifies the touch for which this is a status report (starting from 0).

• Bytes 3 to 10:

X and Y positions: These are scaled to 12-bit resolution. This means that the upper

four bits of the MSByte will always be zero.

Bytes 5,6, 9, 10 are Reserved when TCHGEOMEN is set to 0.

• Byte 11:

Touch Width: Reports the width of the detected touch when TCHGEOMEN is set to

1.

• Byte 13:

Touch Height: Reports the height of the detected touch when TCHGEOMEN is set

to 1.

• Byte 15 to 16:

Scan Time: Timestamp associated with the current report packet with a 10 kHz

resolution.

• Byte 17:

Contact Count: Number of Active Touches to be sent.

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7.4.2

Active maXStylus Report

The format of an active maXStylus report packet is shown in Figure 7-3.

Figure 7-3. Example Active maXStylus Report

Touch 1

(10 bytes)

0x07

HID-I²C

Report ID

Active

maXStylus

Data

Each active maXStylus report start with a HID-I²C Report ID (value 0x06). Table 7-3 gives the

detailed format of an active stylus report packet.

Table 7-3.

Active maXStylus Report

Byte

0

Bit 7

Bit 6

Bit 5

Bit 4

HID-I²C Report ID = 0x07

In Range Reserved

Bit 3

Bit 2

Bit 1

Bit 0

1

Reserved

Eraser

Barrel

Tip

2

X Position

3

4

X Center Position

Y Position

5

6

7

8

Y Center Position

Tip Pressure

9

10

• Byte 1:

Tip: 1 = Contact of the stylus with the touch screen surface, 0 = No contact.

Barrel: 1 = Barrel button on, 0 = Barrel button off

Eraser: 1 = Eraser function on, 0 = Eraser function off.

In Range: 1 = Stylus approaching the touchscreen detected, 0 = No stylus

approaching the touchscreen detected.

• Byte 2 to 3:

X position

• Byte 4 to 5:

X center position

• Byte 6 t o7:

Y position

• Byte 8 to 9:

Y center position

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• Byte 10:

Tip Pressure: Force exerted against the touch screen surface by the stylus.

7.5

Interface 1 (Generic HID-I²C)

Interface 1 is a generic human interface device. It supports an input report for receiving data

from the device and an output report for sending data to the device.

Commands are sent by the host using the output reports. Responses from the device are sent

using input reports.

Supported commands are:

• Read/Write Memory Map

• Send Auto-return Messages

7.5.1

Read/Write Memory Map

7.5.1.1

Introduction

This command is used to carry out a write/read operation on the memory map of the chipset.

The HID-I²C Report ID is 0x06.

Note: This value may change.

The command packet has the generic format given in Figure 7-4. The following sections give

examples on using the command to write to the memory map and to read from the memory map.

Figure 7-4. Generic Command Packet Format

...

0x06

NumWx NumRx

Addr 0

Addr 1

Data 0

Data 11

0x51

HID-I²C Command

Number of Bytes

to Read/Write

Address Pointer

(LSB, MSB)

Write Data

Report ID

ID

In Figure 7-4:

• NumWx is the number of data bytes to write to the memory map (may be zero). If the

address pointer is being sent, this must include the size of the address pointer.

• NumRx is the number of data bytes to read from the memory map (may be zero).

• Addr 0 and Addr 1 form the address pointer to the memory map (where necessary; may be

zero if not needed).

• Data 0 to Data 11 are the bytes of data to be written (in the case of a write). Note that data

locations beyond the number specified by NumWx will be ignored.

The response packet has the generic format given in Figure 7-5.

Figure 7-5. Response Packet Format

...

0x06

NumRx

Data 0

Data 14

Status

HID-I²C

Report ID

Success/ Number of

Bytes Read

Read Data

Failure

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In Figure 7-5 on page 54:

• Status indicates the result of the command:

0x00 = read and write completed; read data returned

0x04 = write completed; no read data requested

• NumRx is the number of bytes following that have been read from the memory map (in the

case of a read). This will be the same value as NumRx in the command packet.

• Data 0 to Data 14 are the data bytes read from the memory map.

7.5.1.2

Writing To the Chipset

A write operation cycle to the chipset consists of sending a packet that contains six header

bytes. These specify the HID-I²C report ID, the Command ID, the number of bytes to read, the

number of bytes to write, and the 16-bit address pointer.

Subsequent bytes in a multibyte transfer form the actual data. These are written to the location

of the address pointer, location o

If the address pointer +1, location of the address pointer + 2, and so on.

Figure 7-6 shows an example command packet to write four bytes of data to contiguous

addresses starting at 0x1234.

Figure 7-6. Example of a Four-byte Write Starting at Address 0x1234

0x06

0x00

0x34

0x12

0x96

0x9B

0xA0

0xA5

0x51

2

HID-I C

Number Number

of Bytes of Bytes

to Write to Read

Address Pointer

(LSB, MSB)

Write Data

Command

ID

Report ID

In Figure 7-6:

• The number of bytes to read is set to zero as this is a write-only operation.

• The number of bytes to write is six: that is, four data bytes plus the two address pointer bytes.

Figure 7-7 shows the response to this command. Note that the result status returned is 0x04

(that is, the write operation was completed but no read data was requested).

Figure 7-7. Response to Example Four-byte Write

0x06

0x04

HID-I²C

Result

Report ID

7.5.1.3

Reading From the Chipset

A read operation consists of sending a packet that contains the six header bytes only and no

write data.

Figure 7-8 shows an example command packet to read four bytes starting at address 0x1234.

Note that the address pointer is included in the number of bytes to write, so the number of bytes

to write is set to 2 as there are no other data bytes to be written.

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Figure 7-8. Example of a Four-byte Read Starting at Address 0x1234

0x06 0x51 0x02 0x04 0x34 0x12

HID-I²C Command

Number Number

of Bytes of Bytes

to Write to Read

Address Pointer

(LSB, MSB)

Report ID

ID

It is not necessary to set the address pointer before every read. The address pointer is updated

automatically after every read operation, so the address pointer will be correct if the reads occur

in order.

Figure 7-9 shows the response to this command. The result status returned is 0x00 (that is the

write operation was completed and the data was returned). The number of bytes returned will be

the same as the number requested (4 in this case).

Figure 7-9. Response to Example Four-byte Read

0x06

0x00

0x04

0x96

0x9B

0xA0

0xA5

HID-I²C

Report ID

Result

Number

of Bytes

Read

Read Data

7.5.2

Send Auto-return Messages

7.5.2.1

Introduction

With this command the chipset can be configured to return new messages from the Message

Processor object autonomously. The packet sequence to do this is shown in Figure 7-10.

Figure 7-10. Packet Sequence for “Send Auto-return” Command.

Host

Chipset

“Send Auto-return” Command Packet

Response Packet

Message Data Packet

:

Message Data Packet

Null Packet to Terminate

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The HID-I²C Report ID is 0x06.

The command packet has the format given in Figure 7-11 on page 57.

Figure 7-11. Command Packet Format

0x06

Res 0

Res 1

Res 2

Res 3

Res 4

Res 5

0x88

HID-I²C Command

Reserved Bytes

(=0x00)

Report ID

ID

In Figure 7-11:

• Res 0 to Res 5 are reserved bytes with a value of 0x00.

The response packet has the format given in Figure 7-12. Note that with this command, the

command packet does not include an address pointer as the chipset already knows the address

of the Message Processor object.

Figure 7-12. Response Packet Format

0x06

0x00

0x88

HID-I²C

Report ID

Command

Received

Once the chipset has responded to the command, it starts sending message data. Each time a

message is generated in the Message Processor object, the chipset automatically sends a

message packet to the host with the data. The message packets have the format given in

Figure 7-13.

Figure 7-13. Message Packet Format

...

0x06

0x00

Rpt ID

Data 0

Data n

0xFA

HID-I²C

Report ID

ID Bytes

Message

Report ID

Message Data

In Figure 7-13:

• ID Bytes identify the packet as an auto-return message packet.

• Rpt ID is the Report ID returned by the Message Processor object. ⁽¹⁾

• Message Data bytes are the bytes of data returned by the Message Processor. The size of

the data depends on the source object for which this is the message data. Refer to the

mXT3432S 2.0 Protocol Guide for more information.

To stop the sending of the messages, the host can send a null command packet. This consists

of two bytes: a report ID of 0x01 and a command byte of 0x00 (see Figure 7-13).

1. This is the Report ID used in the Object Protocol and should not be confused with the USB Report ID. Refer to the

mXT3432S 2.0 Protocol Guide for more information on the use of Report IDs in the Object Protocol.

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Figure 7-14. Null Command Packet Format

0x06

0x00

HID-I²C

Report ID

Null

Command

ID

Note that any read or write will also terminate any currently enabled auto-return mode (see “Start

Debug Monitoring” on page 47).

7.5.2.2

Reading Status Messages

Figure 7-15 shows an example sequence of packets to receive messages from the Message

Processor object using the “Send Auto-return” command.

Figure 7-15. Example Auto-return Command Packet

Send Auto-return Command

0x06

0x88

0x00

HID-I²C Command

Reserved

Report

ID

Response From Chip Set

0x06 0x00

0x88

0x00

Command

Received

Reserved

Read Message Data

0x06

0xFA

0x00

0x02

0x11

0xC0

0x03

0x1C

0x1A

0x1E

0x1C

0x06

0x00

0x4F

0x00

0x10

0x06

ID Bytes

Message

Report ID

Message Data

Send Null Command To Terminate

0x06

0x00

Null

7.6

CHG Line

The CHG line is an active-low, open-drain output that is used to alert the host that a new

message is available in the Input Buffer. This provides the host with an interrupt-style interface

with the potential for fast response times. It reduces the need for wasteful I²C-compatible

communications.

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Further information on the CHG line is given in Section 5.7 on page 33.

Identical to standard I²C operation. Refer to Section 5.8 on page 35.

7.7

7.8

7.9

SDA, SCL

Clock Stretching

Identical to standard I²C operation. Refer to Section 5.10 on page 36.

Microsoft Windows 8 Compliance

The mXT3432S1 has algorithms within the Digitizer HID Configuration T43 and Multiple Touch

Touchscreen T9 specifically to ensure Microsoft Windows 8 compliance.

The mXT3432S1 also supports Microsoft Touch Hardware Quality Assurance (THQA) in the

Serial Data Command T68 object. Refer to the Microsoft whitepaper on “How to Design and Test

Multitouch Hardware Solutions for Windows 8”.

These, and other device features, may need specific tuning.

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8. Getting Started with mXT3432S1

8.1

Establishing Contact

8.1.1

Communication with the Host

The host can use either the I²C-compatible interface (see Section 5.1 on page 29), USB

interface (see Section 6.1 on page 37) or the HID-I²C interface ( see Section 7 on page 50) to

communicate with the chipset.

8.1.2

I²C-compatible Interface

On power-up, the CHG line goes low to indicate that there is new data to be read from the

Message Processor T5 object. If the CHG line does not go low, there is a problem with the

chipset.

The host should attempt to read any available messages to establish that the chipset is present

and running following power-up or a reset. Examples of messages include reset or calibration

messages. The host should also check that there are no configuration errors reported.

8.1.3

USB Interface

The host can establish contact with the chipset as specified in the USB 2.0 specification and the

USB HID specification (both available from www.usb.org).

8.1.4

HID-I²C Interface

The host can use the HID-I²C interface by connecting the I2CMODE pin to GND.

8.2

Using the Object Protocol

The chipset has an object-based protocol that is used to communicate with the chipset. Typical

communication includes configuring the chipset, sending commands to the chipset, and

receiving messages from the chipset. Refer to the mXT3432S 2.0 Protocol Guide for more

information.

The host must perform the following initialization so that it can communicate with the chipset:

1. Read the start positions of all the objects in the chipset from the Object Table and build

up a list of these addresses.

2. Use the Object Table to calculate the report IDs so that messages from the chipset can

be correctly interpreted.

8.3

Writing to the Chipset

There are three mechanisms for writing to the chipset:

• Using an I²C-compatible write operation (see Section 5.3 on page 29).

• Using the USB Generic HID write operation (see Section 6.5.1.2 on page 43).

• Using the Generic HID-I²C write operation (see Section 7.5.1.2 on page 55).

To communicate with the chipset, you write to the appropriate object:

• To send a command to the chipset, you write the appropriate command to the Command

Processor T6 object (refer to the mXT3432S 2.0 Protocol Guide).

• To configure the chipset, you write to an object. For example, to configure the chipset’s power

consumption you write to the global Power Configuration T7 object, and to set up a

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touchscreen you write to a Multiple Touch Touchscreen T9 object. Some objects are optional

and need to be enabled before use. Refer to the mXT3432S 2.0 Protocol Guide for more

information on the objects.

8.4

Reading from the Chipset

Status information is stored in the Message Processor T5 object. This object can be read to

receive any status information from the chipset. There are two mechanisms that provide an

interrupt-style interface for reading messages in the Message Processor T5 object:

• When using the I²C-compatible interface, the CHG line is asserted whenever a new message

is available in the Message Processor T5 object (see Section 5.7 on page 33). See

Section 6.5.1.3 on page 44 for information on the format of the I²C-compatible read

operation.

• When using the USB interface, the Generic HID interface provides an interrupt-driven

interface that sends the messages automatically (see Section 6.5.2 on page 45).

• When using the HID-I²C interface, the Generic HID-I²C interface provides an interrupt-driven

interface that sends the messages automatically (see Section 7.5.1.3 on page 55)

Note that in both cases the host should always wait to be notified of messages. The host should

not poll the chipset for messages.

The USB Digitizer HID provides a third alternative interrupt-style mechanism for reading a

subset of the touch data. See Section 6.4 on page 38 for more information.

8.5

Configuring the Chipset

The objects are designed such that a default value of zero in their fields is a “safe” value that

typically disables functionality. The objects must be configured before use and the settings

written to the nonvolatile memory using the Command Processor T6 object.

Perform the following actions for each object:

1. Enable the object, if the object requires it.

2. Configure the fields in the object, as required.

3. Enable reporting, if the object supports messages, to receive messages from the

object.

Refer to the mXT3432S 2.0 Protocol Guide for more information on configuring the objects.

The following objects are read-only and require no configuration:

• Debug Objects

– Diagnostic Debug T37

• General objects:

– Message Processor T5

• Support objects:

– User Data T38

– Message Count T44

The following objects must be configured before use:

• General objects

– Power Configuration T7

– Acquisition Configuration T8

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The following objects should be checked and configured as necessary:

• General objects:

– Command Processor T6

• Support objects:

– Communications Configuration T18

– CTE Configuration T46

The following objects should also be enabled and configured, as required:

• Touch objects:

– Multiple Touch Touchscreen T9

• Signal processing objects:

– Grip Suppression T40

– Stylus T47

– One-touch Gesture Processor T24

– Two-touch Gesture Processor T27

– Touch Suppression T42

– Shieldless T56

– Extra Touchscreen Data T57

– maXCharger T62

– Active Stylus T63

– Lens Bending T65

• Support objects:

– Digitizer HID Configuration T43

– Self Test T25

– Timer T61

– maXStartup T66

– Serial Data Command T68

– Dynamic Configuration Controller T70

– Dynamic Configuration Container T71

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9. Specifications

See Appendix B on page 80 for the reference configuration.

9.1

Absolute Maximum Specifications

Vdd

3.6 V

12 V

3.6 V

XVdd

AVdd

Max continuous pin current, any control or drive pin

Voltage forced onto any pin

20 mA

–0.3 V to (Vdd or AVdd) + 0.3 V

10,000

Configuration parameters maximum writes

CAUTION: Stresses beyond those listed under Absolute Maximum Specifications may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated

in the operational sections of this specification is not implied. Exposure to absolute maximum specification conditions for

extended periods may affect device reliability.

9.2

Recommended Operating Conditions

Operating temp

Storage temp

–40°C to +85°C

–60°C to +150°C

Vdd External

3.3 V 5ꢀ

AVdd

2.7 to 3.3 V 10ꢀ

XVdd

2.7 to 10.0 V 5ꢀ

Vdd vs AVdd power sequencing

Vdd vs XVdd power sequencing

Vdd supply ripple

No sequencing required

XVdd must not be powered before Vdd

50 mV 1 Hz to 1 MHz

25 mV 1 Hz to 1MHz

25 mV 1 Hz to 1 MHz

XVdd supply ripple

AVdd supply ripple (Noise suppression T48 disabled)

0.95 pF to 4.8 pF, when XVdd = 2.5 V to 4.75 V

0.5 pF to 4.8 pF, when XVdd = 4.75 V to 10 V

Cx transverse load capacitance per channel

Temperature slew rate

10°C/min

9.3

DC Characteristics

9.3.1

Digital Voltage Supply

Parameter

Vdd

Description

Operating limits

Rate of rise

Min

3.14

Typ

Max

3.47

2.5

Units

V

Notes

Common to Master and Slave

devices

3.3

Rate of rise

0.002

V/µs

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9.3.2

Parameter

AVdd

Rate of rise

Analog Voltage Supply

Description

Operating limits

Rate of rise

Min

2.5

Typ

Max

3.6

Units

V

Notes

See Section 4.6.3 on page 27

0.002

2.5

V/µs

9.3.3

XVdd Supply

Parameter

XVdd

Description

Min

2.5

2

Typ

Max

10.5

30

Units

V

Notes

Operating limits

Rate of rise

10.0

Rate of rise

V/ms

Note: The rate of rise values must be followed to avoid permanent damage to the

device.

9.3.4

Parameter

Input (RESET, SDA, SCL)

Input/Output Characteristics

Description

Min

Typ

Max

Units

Notes

Vil

Low input logic level

–0.3

0.3 × Vdd

Vdd + 0.3

1

V

Vdd = 2.5 V to 3.3 V

Pull-up resistors disabled

Vih

Iil

High input logic level

Input leakage current

0.7 × Vdd

µA

Output (CHG)

Vdd = 3 V, I_OL= 2.7 mA, High

Drive Enabled

Vdd = 3 V, I_OL= 1.35 mA

Vol

Low output voltage

High output voltage

0.2 × Vdd

V

Vdd = 3 V, I_OH= 2.7 mA, High

Drive Enabled

Voh

0.8 × Vdd

Vdd = 3 V, I_OH= 1.35 mA

9.4

ESD Information

Parameter

Electrostatic Discharge HBM

Value

2000 V

Reference standard

MIL– STD883 Method 3015.7

9.5

Supply Current

Master = 3.3 V, Slave: AVdd = 2.8 V, Vdd = 3.3 V and XVdd = 10 V

9.5.1

Analog Supply – I²C-compatible Interface

XSIZE = 41, YSIZE = 72, IDLESYNCPERX = ACTSYNCPERX = 16, CHRGTIME = 234, Shieldless T56 = On

Parameter

Description

Min

Typ

Max

Units

mA

Notes

Active average supply current

Idle average supply current

Sleep average supply current

86.46

14.32

0.005

100 Hz, 1 Touch

16 Hz, no touches

AIdd

mA

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9.5.2

Analog Supply – USB Bus

XSIZE = 41, YSIZE = 72, IDLESYNCPERX = ACTSYNCPERX = 16, CHRGTIME = 234, Shieldless T56 = On

Parameter

Description

Min

Typ

Max

Units

mA

Notes

Active average supply current

Idle average supply current

Sleep average supply current

65.44

80.32

0.006

100 Hz, 1 Touch

AIdd

mA

16 Hz, no touches

mA

9.5.3

Digital Supply – I²C-compatible Interface

XSIZE = 41, YSIZE = 72, IDLESYNCPERX = ACTSYNCPERX = 16, CHRGTIME = 234, Shieldless T56 = On

Parameter

Description

Min

Typ

65.31

7.59

0.65

Max

Units

mA

Notes

Active average supply current

Idle average supply current

Sleep average supply current

100 Hz, 1 Touch

16 Hz, no touches

DIdd

mA

9.5.4

Digital Supply – USB Bus

XSIZE = 41, YSIZE = 72, IDLESYNCPERX = ACTSYNCPERX = 16, CHRGTIME = 234, Shieldless T56 = On

Parameter

Description

Min

Typ

58.55

63.51

7.26

Max

Units

mA

Notes

Active average supply current

Idle average supply current

Sleep

100 Hz, 1 Touch

16 Hz, no touches

DIdd

mA

9.5.5

X Drive Supply – I²C-compatible Interface

XSIZE = 41, YSIZE = 72, IDLESYNCPERX = ACTSYNCPERX = 16, CHRGTIME = 234, Shieldless T56 = On

Parameter

Description

Min

Typ

1.56

Max

Units

mA

Notes

Active average supply current

Idle average supply current

Sleep average supply current

100 Hz, 1 Touch

16 Hz, no touches

XIdd

0.27

mA

0.0008

mA

9.5.6

X Drive Supply – USB Bus

XSIZE = 41, YSIZE = 72, IDLESYNCPERX = ACTSYNCPERX = 16, CHRGTIME = 234, Shieldless T56 = On

Parameter

Description

Min

Typ

1.20

Max

Units

mA

Notes

Active average supply current

Idle average supply current

Sleep

100 Hz, 1 Touch

16 Hz, no touches

XIdd

1.00

mA

0.0002

mA

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9.6

Power Consumption

Master = 3.3 V, Slave: AVdd = 2.8 V, Vdd = 3.3 V and XVdd = 10 V

9.6.1 USB Interface

XSIZE = 41, YSIZE = 72, IDLESYNCPERX = ACTSYNCPERX = 16, CHRGTIME = 234, Shieldless T56 = Off

0

AIdd No Touch

AIdd 1 Touch

0

5

3

6

8

9

0

5

AIdd 5 Touches

AIdd 10 Touches

DIdd No Touch

DIdd 1 Touch

DIdd 5 Touches

DIdd 10 Touches

XIdd No Touch

XIdd 1 Touch

XIdd 5 Touches

XIdd 10 Touches

A

i iti

I t

l (

)

XSIZE = 41, YSIZE = 72, IDLESYNCPERX = ACTSYNCPERX = 16, CHRGTIME = 234,

Shieldless T56 = On: Multicut Grass cutter, Noise cancellation and Optimal integration = On

00

50

25

13

56

78

39

20

10

AIdd No Touch

AIdd 1 Touch

AIdd 5 Touches

AIdd 10 Touches

DIdd No Touch

DIdd 1 Touch

DIdd 5 Touches

DIdd 10 Touches

XIdd No Touch

XIdd 1 Touch

XIdd 5 Touches

XIdd 10 Touches

Acquisition Interval (ms)

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9.6.2

I2C Mode

XSIZE = 41, YSIZE = 72, IDLESYNCPERX = ACTSYNCPERX = 16, CHRGTIME = 234, Shieldless T56 = Off

128.0000

64.0000

32.0000

16.0000

8.0000

4.0000

2.0000

1.0000

0.5000

0.2500

0.1250

0.0625

0.0313

0.0156

0.0078

0.0039

0.0020

0.0010

0.0005

AIdd No Touch

AIdd 1 Touch

AIdd 5 Touches

AIdd 10 Touches

DIdd No Touch

DIdd 1 Touch

DIdd 5 Touches

DIdd 10 Touches

XIdd No Touch

XIdd 1 Touch

XIdd 5 Touches

XIdd 10 Touches

Acquisition Interval (ms)

XSIZE = 41, YSIZE = 72, IDLESYNCPERX = ACTSYNCPERX = 16, CHRGTIME = 234

Shieldless T56 = On: Multicut Grass cutter, Noise cancellation and Optimal integration = On

128.0000

64.0000

32.0000

16.0000

8.0000

4.0000

2.0000

1.0000

0.5000

0.2500

0.1250

0.0625

0.0313

0.0156

0.0078

0.0039

0.0020

0.0010

0.0005

AIdd No Touch

AIdd 1 Touch

AIdd 5 Touches

AIdd 10 Touches

DIdd No Touch

DIdd 1 Touch

DIdd 5 Touches

DIdd 10 Touches

XIdd No Touch

XIdd 1 Touch

XIdd 5 Touches

XIdd 10 Touches

Acquisition Interval (ms)

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9.7

Timing Specifications

9.7.1

Touch Latency

Parameter

Tlatency

Description

Min

Typ

Max

Units

Notes

100 Hz

7.84

20.88

25.81

ms

9.7.2

Speed

XSIZE = 41, YSIZE = 72, IDLESYNCPERX = ACTSYNCPERX = 16, CHRGTIME = 234

220

200

180

160

140

120

100

Refresh Rate (Hz)

1

2

3

4

5

6

7

8

9

10

Number of Moving Touches

9.7.3

Reset Timings

The mXT3432S1 meets Microsoft Windows 8 requirements.

9.8

I²C-compatible Specifications

Parameter

Value

Addresses

0x4C, 0x4D, 0x5A or 0x5B

400 kHz

Maximum bus speed (SCL)

I²C specification

Version 2.1

Required pull-up resistance for standard mode (100 kHz)

Required pull-up resistance for fast mode (400 kHz)

1 kΩ to 10 kΩ

1 kΩ to 3 kΩ

68

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9.9

USB Specification

Parameter

Operation

0x81 (Endpoint 1)

0x02 (Endpoint 2)

0x83 (Endpoint 3)

Endpoint Addresses

Maximum bus speed

Vendor ID

12 Mbps

0x03EB (Atmel)

0x2136 (mXT3432S1)

USB 2.0

Product ID

USB specification

HID specification 1.11 with amendments for multitouch digitizers

9.10 HID-I²C Specification

Parameter

Operation

Vendor ID

0x03EB (Atmel)

0x2136 (mXT3432S1)

0.9

Product ID

HID-I²C specification

9.11 Touch Accuracy and Repeatability

Parameter

Linearity

Min

Typ

0.5

1

Max

Units

mm

ꢀ

Notes

Accuracy

Accuracy at edge

Repeatability

2

0.25

X axis with 12-bit resolution

9.12 Power Supply and Ripple Noise

Parameter

Min

Typ

Max

Units

Notes

Across frequency range

1 Hz to 1 MHz

Vdd

50

mV

Across frequency range

1 Hz to 1 MHz

XVdd and AVdd

25

40

mV

Across frequency range

1 Hz to 1 MHz, with Noise

Suppression enabled

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9.13 Thermal Packaging

9.13.1

Thermal Data

Parameter

Typ

33.7

5.0

Unit

°C/W

Condition

Package

Junction to ambient thermal resistance

Junction to case thermal resistance

Still air

VFBGA 128, 7 X 7 mm

9.13.2

Junction Temperature

The average chip junction temperature, T_Jin °C can be obtained from the following:

T

= T + (P × θ

)

JA

J

A

D

If a cooling device is required, use this equation:

= T + (P × (θ + θ ))

T

J

A

D

HEATSINK

JC

where:

• θ_JA= package thermal resistance, Junction to ambient (°C/W).

• θ_JC= package thermal resistance, Junction to case thermal resistance (°C/W).

• θ_HEATSINK= cooling device thermal resistance (°C/W), provided in the cooling device

datasheet.

• P_D= device power consumption (W).

• T_Ais the ambient temperature (°C).

9.14 Soldering Profile

Profile Feature

Green Package

3°C/s max

150 – 200°C

60 – 150 s

30 s

Average Ramp-up Rate (217°C to Peak)

Preheat Temperature 175°C 25°C

Time Maintained Above 217°C

Time within 5°C of Actual Peak Temperature

Peak Temperature Range

260°C

Ramp down Rate

6°C/s max

8 minutes max

Time 25°C to Peak Temperature

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9.15 Mechanical Dimensions

9.15.1

ATMXT3432S-M – 64-pin QFN

A

D

J

N

1

0.30

PIN 1

MARKING

E

SEATING PLANE

0.08

C

TOP VIEW

DRAWINGS NOT SCALED

SIDE VIEW

D2

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL

MIN

NOM

MAX

NOTE

A

0.08

–

1.00

J

0.00

3.25

1.05

7.50

D/E

9.00 BSC

–

D2/E2

E2

N

e

L

b

64

0.50 BSC

0.40

0.30

0.18

0.55

0.30

0.25

1

L

Option A

Option B

Option C

b

e/2

e

N

See Options

A, B, C

1

BOTTOM VIEW

N

Pin 1# Chamfer

(C 0.30)

Pin 1# Notch

(0.20 R)

Pin 1# Triangle

6/24/10

REV.

A

TITLE

DRAWING NO.

Package Drawing Contact:

64Z2, 64 Leads - body 9.0 x 9.0 mm - pitch 0.5 mm

touch@atmel.com

64Z2

Quad Flat No Lead Package (QFN)

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9.15.2

ATMXT3432S-M 64-ball UFBGA

Package Drawing Contact:

packagedrawings@atmel.com

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9.15.3

ATMXT3432S1-S – 128-ball VFBGA

Package Drawing Contact:

packagedrawings@atmel.com

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9.16 Part Marking

9.16.1

ATMXT3432S-M

64

Pin 1 ID

1

Abbreviation of Part

Number

MXT3432S-M

– U

YYWWR CC

LOTCODE

Date, Country

and Lot Code

or

Ball A1 ID

Abbreviation of Part

Number

MXT3432S

M-CU

YYWWA CC

LOTCODE

Date, Country

and Lot Code

9.16.2

ATMXT3432S1-S

128

Pin 1 ID

1

Abbreviation of Part

Number

MXT3432S1

S-CU

YYWWA CC

LOTCODE

Date, Country

and Lot Code

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9.17 Part Numbers

9.17.1

Orderable Individual Parts

Orderable Part Number

QS Number

Description

ATMXT3432S-M-Z2UR

(supplied in tape and reels)

QS717

64-pin 9 x 9 mm QFN RoHS compliant

64-ball 6 x 6 mm UFBGA RoHS compliant

ATMXT3432S-M-CCUR

(supplied in tape and reels)

QS717

QS754

ATMXT3432S1-S-CUR

(supplied in tape and reels)

128-ball 7 x 7 mm VFBGA RoHS

compliant

9.18 Moisture Sensitivity Level (MSL)

MSL Rating

Peak Body Temperature

Specifications

MSL3

260^oC

IPC/JEDEC J-STD-020

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Appendix A. PCB Design Considerations

A.1 Introduction

The following sections give the design considerations that should be adhered to when designing

a PCB layout for use with the mXT3432S1. Of these, power supply and ground tracking

considerations are the most critical.

By observing the following design rules, and with careful preparation for the PCB layout

exercise, designers will be assured of a far better chance of success and a correctly functioning

product.

A.2 Printed Circuit Board

Atmel recommends the use of a four layer printed circuit board for mXT3432S1 applications.

This, together with careful layout, will ensure that the board meets relevant EMC requirements

for both noise radiation and susceptibility, as laid down by the various national and international

standards agencies.

A.3 Supply Rails and Ground Tracking

Power supply and clock distribution are the most critical parts of any board layout. Because of

this, it is advisable that these be completed before any other tracking is undertaken. After these,

supply decoupling, and analog and high speed digital signals should be addressed. Track widths

for all signals, especially power rails should be kept as wide as possible in order to reduce

inductance.

The Power and Ground planes themselves can form a useful capacitor. Flood filling for either or

both of these supply rails, therefore, should be used where possible. It is important to ensure

that there are no floating copper areas remaining on the board: all such areas should be

connected to the 0 V plane. The flood filling should be done on the outside layers of the board.

In applications where the USB bus supplies power to the board, care should be taken to ensure

that suitable capacitive decoupling is provided close to the USB connector. The tracking to the

on-board regulators should also be kept as short as possible.

It should also be remembered that the screen of the USB cable is not intended to be connected

to the ground or 0V supply of a remote device. It should either be left open circuit (being

connected only at the host computer end) or decoupled with a suitable high voltage capacitor

(typically 4.7 nF – 250 V) and a parallel resistor (typically 1 MΩ). Note that these components

may not be required when the USB cabling is internal and permanently wired, and is routed

away from the noisier parts of the system.

A.4 Power Supply Decoupling

As a rule, a suitable decoupling capacitor should be placed on each and every supply pin on all

digital devices. It is important that these capacitors are placed as close to the chip’s supply pins

as possible (less than 5mm away). The ground connection of these capacitors should be tracked

to 0V by the shortest, heaviest traces possible.

Capacitors with a Type II dielectric, such as X5R or X7R and with a value of at least 100nF,

should be used for this purpose.

In addition, at least one ‘bulk’ tantalum decoupling capacitor, with a minimum value of 4.7 µF

should be placed on each power rail, close to where the supply enters the board.

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Surface mounting capacitors are preferred to wire leaded types due to their lower ESR and ESL.

It is often possible to fit these decoupling capacitors underneath and on the opposite side of the

PCB to the digital ICs. This will provide the shortest tracking, and most effective decoupling

possible.

Refer to the application note Selecting Decoupling Capacitors for Atmel’s PLDs (doc0484.pdf;

available on Atmel’s website) for further general information on decoupling capacitors.

A.5 Suggested Voltage Regulator Manufacturers

The AVdd supply stability is critical for the mXT3432S1 because this supply interacts directly

with the analog front end. Atmel therefore recommends that the supply for the analog section of

the board be supplied by a regulator that is separate from the logic supply regulator. This

reduces the amount of noise injected into the sensitive, low signal level parts of the design.

A single low value series resistor (around 1Ω) is required from the regulator output to the analog

supply input on the mXT3432S1 device. This, together with the regulator output capacitor, and

the capacitors at the DC input to the device, forms a simple filter on the supply rail.

A low noise device should be chosen for the regulator. If possible this should have provision for

adding a capacitor across the internal reference for further noise reduction. Reference should be

made to the manufacturer’s datasheet.

The voltage regulators listed in Table 9-1 have been tested and found to work well with the

mXT3432S1. They have compatible footprints and pin-out specifications, and are available in

the SOT-23 package.

Table 9-1.

Recommended Voltage Regulators

Manufacturer

Part Number

TLV70028

LT1761

Texas Instruments

Linear Technology

Micrel

AVdd

Vdd

MIC5255

LP2981

National Semiconductor

Torex

Vdd

XC6204

AS1340

AMS

XVdd

GMMT

G5126

Note some manufacturers claim that minimal or no capacitance is required for correct regulator

operation. However, in all cases, a minimum of a 1.0 µF ceramic, low ESR capacitor at the input

and output of these devices should be used. The manufacturers’ datasheets should always be

referred to when selecting capacitors for these devices and the typical recommended values,

types and dielectrics adhered to.

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Figure 9-1. Example Regulator Circuit

ELL4LG100MA

Vdd

Vbatt

XVdd

IN

LX

4u7

2n2

10uF

OVP

G5126

EN

FB

GND

Note that a “soft-start” regulator with excellent noise and load step regulation will be needed to

satisfy the XVdd supply requirements. 1ꢀ resistors should be used to define the nominal output

voltage. If 5ꢀ resistors are used, the nominal XVdd voltage must be reduced accordingly to

ensure that the recommended voltage range is adhered to. Figure 9-1 provides an example

circuit for the XVdd supply.

A.6 Crystal Oscillator

The placement of the crystal oscillator is critical to the performance of the design. The

connecting leads between the mXT3432S1 and the crystal should be as short as possible.

These tracks, together with the crystal itself, should be placed above a suitable ground plane. It

is also important that no other signal tracks are placed close to, or under, these tracks. The

crystal input pins are at a relatively high impedance and cross-talk from other signals will

seriously affect oscillator stability and accuracy. The crystal’s case should also be connected to

ground if possible.

If an oscillator module is used, care still needs to be taken when tracking to the mXT3432S1.

The clock signal should be kept as short as possible, with a solid ground return underneath the

clock output.

A.7 Analog I/O

In general, tracking for the analog I/O signals from the mXT3432S1 device should be kept as

short as possible. These normally go to a connector which interfaces directly to the touchscreen.

Ensure that adequate ground-planes are used. An analog ground plane should be used in

addition to a digital one. Care should be taken to ensure that both ground planes are kept

separate and are connected together only at the point of entry for the power to the PCB. This is

usually at the input connector.

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A.8 Component Placement

It is important to orient all devices so that the tracking for important signals (such as power and

clocks) are kept as short as possible. This simple point is often overlooked when initially

planning a PCB layout and can save hours of work at a later stage.

A.9 Digital Signals

In general, when tracking digital signals, it is advisable to avoid sharp directional changes,

sensitive signal tracks (such as analog I/O) and any clock or crystal tracking.

A good ground return path for all signals should be provided, where possible, to ensure that

there are no discontinuities in the ground return path.

A.10 EMC and Other Observations

The following recommendations are not mandatory, but may help in situations where particularly

difficult EMC or other problems are present:

• A small common mode choke is recommended on the differential USB data pair. This should

be placed directly at the USB connector, between the connector and the relevant

mXT3432S1 pins. Tracking lengths for the USB data pair should be kept as short as possible.

• Try to keep as many signals as possible on the inside layers of the board. If suitable ground

flood fills are used on the top and bottom layers, these will provide a good level of screening

for noisy signals, both into and out of the PCB.

• Ensure that the on-board regulators have sufficient tracking around and underneath the

devices to act as a heatsink. This heatsink will normally be connected to the 0V or ground

supply pin. Increasing the width of the copper tracking to any of the device pins will aid in

removing heat. There should be no solder mask over the copper track underneath the body

of the regulators.

• Ensure that the decoupling capacitors, especially tantalum, or high capacity ceramic types,

have the requisite low ESR, ESL and good stability/temperature properties. Refer to the

regulator manufacturer’s datasheet for more information.

Refer to the QTAN0096: mXT3432S1 PCB/FPC Layout Guidelines application note for more

details.

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Appendix B. Glossary of Terms

Channel

One of the capacitive measurement points at which the sensor controller can detect

capacitive change.

Jitter

The peak-to-peak variance in the reported location for an axis when a fixed touch is applied.

Typically jitter is random in nature and has a Gaussian ⁽¹⁾distribution, therefore measurement

of peak-to-peak jitter must be conducted over some period of time, typically a few seconds.

Jitter is typically measured as a percentage of the axis in question.

For example a 100 x 100 mm touchscreen that shows 0.5ꢀ jitter in X and 1ꢀ jitter in Y

would show a peak deviation from the average reported coordinate of 0.5 mm in X and

1 mm in Y. Note that by defining the jitter relative to the average reported coordinate, the

effects of linearity are ignored.

Linearity

The measurement of the peak-to-peak deviation of the reported touch coordinate in one axis

relative to the absolute position of touch on that axis. This is often referred to as the

nonlinearity. Non-linearities in either X or Y axes manifest themselves as regions where the

perceived touch motion along that axis (alone) is not reflected correctly in the reported

coordinate giving the sense of moving too fast or too slow. Linearity is measured as a

percentage of the axis in question.

For each axis, a plot of the true coordinate versus the reported coordinate should be a

perfect straight line at 45°. A non-linearity makes this plot deviate from this ideal line. It is

possible to correct modest non-linearities using on-chip linearization tables, but this

correction trades linearity for resolution in regions where stronger corrections are needed

(because there is a stretching or compressing effect to correct the nonlinearity, so altering

the resolution in these regions). Linearity is typically measured using data that has been

sufficiently filtered to remove the effects of jitter. For example, a 100 mm slider with a

nonlinearity of 1ꢀ reports a position that is, at most, 1 mm away in either direction from the

true position.

One-touch Gesture

A touch gesture that consists of a single touch. The combination of the duration of the touch

and any change in position (that is, movement) of the touch characterizes a specific gesture.

For example, a tap gesture is characterized by a short-duration touch followed by a release,

and no significant movement.

Resolution

The measure of the smallest movement on a slider or touchscreen in an axis that causes a

change in the reported coordinate for that axis. Resolution is normally expressed in bits and

tends to refer to resolution across the whole axis in question. For example, a resolution of

10 bits can resolve a movement of 0.0977 mm on a slider 100 mm long. Jitter in the reported

position degrades usable resolution.

1. Sometimes called Bell-shaped or Normal distribution.

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Touchscreen

A two-dimensional arrangement of electrodes whose capacitance changes when touched,

allowing the location of touch to be computed in both X and Y axes. The output from the XY

computation is a pair of numbers, typically 12-bits each, ranging from 0 to 4095, representing

the extents of the touchscreen active region.

Two-touch Gesture

A touch gesture that consists of two simultaneous touches. The change in position of the two

touches in relation to each other characterizes a specific gesture. For example, a pinch

gesture is characterized by two long-duration touches that have a decreasing distance

between them (that is, they are moving closer together).

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Appendix C. QMatrix Primer

C.1 Acquisition Technique

QMatrix capacitive acquisition uses a series of pulses to deposit charge into a sampling capacitor, Cs.

The pulses are driven on X lines from the controller. The rising edge of the pulse causes current to

flow in the mutual capacitance, Cx, formed between the X line and a neighboring receiver electrode or

Y line. While one X line is being pulsed, all others are grounded. This leads to excellent isolation of

the particular mutual capacitances being measured ⁽¹⁾, a feature that makes for good inherent

touchscreen performance.

After a fixed number of pulses (known as the burst length) the sampling capacitor's voltage is

measured to determine how much charge has accumulated. This charge is directly proportional to

Cx and therefore changes if Cx ⁽²⁾changes. The transmit-receive charge transfer process between

the X lines and Y lines causes an electric field to form that loops from X to Y. The field itself emanates

from X and terminates on Y. If the X and Y electrodes are fixed directly ⁽³⁾to a dielectric material like

plastic or glass, then this field tends to channel through the dielectric with very little leakage of the

field out into free-space (that is, above the panel). Some proportion of the field does escape the

surface of the dielectric, however, and so can be influenced during a touch.

When a finger is placed in close proximity (a few millimeters) or directly onto the dielectric's surface,

some of this stray field and some of the field that would otherwise have propagated via the dielectric

and terminated onto the Y electrode, is diverted into the finger and is conducted back to the controller

chip via the human body rather than via the Y line.

This means that less charge is accumulated in Cs, and hence the terminal voltage present on Cs,

after all the charge transfer pulses are complete, becomes less. In this way, the controller can

measure changes in Cx during touch. This means that the measured capacitance Cx goes down

during touch, because the coupled field is partly diverted by the touching object.

The spatial separation between the X and Y electrodes is significant to make the electric field to

propagate well in relation to the thickness of the dielectric panel.

C.2 Moisture Resistance

A useful side effect of the QMatrix acquisition method is that placing a floating conductive element

between the X and Y lines tends to increase the field coupling and so increases the capacitance Cx.

This is the opposite change direction to normal touch, and so can be quite easily ignored or

compensated for by the controller. An example of such floating conductive elements is the water

droplets caused by condensation.

As a result, QMatrix-based touchscreens tend not to go into false detect when they are covered in

small non-coalesced water droplets. Once the droplets start to merge, however, they can become

large enough to bridge the field across to nearby ground return paths (for example, other X lines not

currently driven, or ground paths in mechanical chassis components). When this happens, the

screen's behavior can become erratic.

1. A common problem with other types of capacitive acquisition technique when used for touchscreens, is that this

isolation is not so pronounced. This means that when touching one region of the screen, the capacitive signals also

tend to change slightly in nearby channels too, causing small but often significant errors in the reported touch position.

2. To a first approximation.

3. Air gaps in front of QMatrix sensors massively reduce this field propagation and kill sensitivity. Normal optically clear

adhesives work well to attach QMatrix touchscreens to their dielectric front panel.

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There are some measures used in these controllers to help with this situation, but in general there

comes a point where the screen is so contaminated by moisture that false detections become

inevitable. It should also be noted that uniform condensation soon becomes non-uniform once a

finger has spread it around. Finger grease renders the water highly conductive, making the situation

worse overall.

In general, QMatrix has industry-leading moisture tolerance but there comes a point when even the

best capacitive touchscreen suffers due to moisture on the dielectric surface.

C.3 Interference Sources

C.3.1

Power Supply

The chipset can tolerate short-term power supply fluctuations. If the power supply fluctuates

slowly with temperature, the chipset tracks and compensate for these changes automatically

with only minor changes in sensitivity. If the supply voltage drifts or shifts quickly, the drift

compensation mechanism is not able to keep up, causing sensitivity anomalies or false

detections.

The chipset itself uses the AVdd power supply as an analog reference, so the power should be

very clean and come from a separate regulator. A standard inexpensive Low Dropout (LDO)

type regulator should be used that is not also used to power other loads, such as LEDs, relays,

or other high current devices. Load shifts on the output of the LDO can cause AVdd to fluctuate

enough to cause false detection or sensitivity shifts. The digital Vdd supply is far more tolerant to

noise.

CAUTION: A regulator IC shared with other logic can result in erratic

operation and is not advised.

Noise on AVdd can appear directly in the measurement results. Vdd should be checked to

ensure that it stays within specification in terms of noise, across a whole range of product

operating conditions.

Ceramic bypass capacitors on AVdd and Vdd, placed very close (<5 mm) to the chip are

recommended. A bulk capacitor of at least 1 µF and a higher frequency capacitor of around

10 nF to 100 nF in parallel are recommended; both must be X7R or X5R dielectric capacitors.

C.3.2

Other Noise Sources

Refer to QTAN0079, Buttons, Sliders and Wheels Sensor Design Guide, for information

(downloadable from the Touch Technology area of the Atmel website).

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Appendix D. I²C Basics (I²C-compatible Operation)

9.19 Interface Bus

The device communicates with the host over an I²C bus. The following sections give an

overview of the bus; more detailed information is available from www.i2C-bus.org. Devices are

connected to the I²C bus as shown in Figure D-1. Both bus lines are connected to Vdd via pull-

up resistors. The bus drivers of all I²C devices must be open-drain type. This implements a wired

AND function that allows any and all devices to drive the bus, one at a time. A low level on the

bus is generated when a device outputs a zero.

Figure D-1. I²C Interface Bus

Vdd

Device 1

Device 2

Device 3

Device n

R1

R2

SDA

SCL

D.1 Transferring Data Bits

Each data bit transferred on the bus is accompanied by a pulse on the clock line. The level of the

data line must be stable when the clock line is high; the only exception to this rule is for

generating START and STOP conditions.

Figure D-2. Data Transfer

SDA

SCL

Data Stable

Data Change

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D.2 START and STOP Conditions

The host initiates and terminates a data transmission. The transmission is initiated when the

host issues a START condition on the bus, and is terminated when the host issues a STOP

condition. Between the START and STOP conditions, the bus is considered busy. As shown in

Figure D-3, START and STOP conditions are signaled by changing the level of the SDA line

when the SCL line is high.

Figure D-3. START and STOP Conditions

SDA

SCL

START

STOP

D.3 Address Byte Format

All address bytes are 9 bits long, consisting of 7 address bits, one READ/WRITE control bit and

an acknowledge bit. If the READ/WRITE bit is set, a read operation is performed, otherwise a

write operation is performed. When the device recognizes that it is being addressed, it will

acknowledge by pulling SDA low in the ninth SCL (ACK) cycle. An address byte consisting of a

slave address and a READ or a WRITE bit is called SLA+R or SLA+W, respectively.

The most significant bit of the address byte is transmitted first. The address sent by the host

must be consistent with that selected with the option jumpers.

Figure D-4. Address Byte Format

Addr MSB

Addr LSB

ACK

R/W

SDA

SCL

1

2

7

8

9

START

D.4 Data Byte Format

All data bytes are 9 bits long, consisting of 8 data bits and an acknowledge bit. During a data

transfer, the host generates the clock and the START and STOP conditions, while the receiver is

responsible for acknowledging the reception. An acknowledge (ACK) is signaled by the receiver

pulling the SDA line low during the ninth SCL cycle. If the receiver leaves the SDA line high, a

NACK is signaled.

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Figure D-5. Data Byte Format

Data LSB

Data MSB

ACK

Aggregate

SDA

SDA from

Transmitter

SDA from

Receiver

SCL from

Master

1

2

7

8

9

SLA+R/W

Data Byte

Stop or Next

Data Byte

D.5 Combining Address and Data Bytes into a Transmission

A transmission consists of a START condition, an SLA+R/W, one or more data bytes and a

STOP condition. The wired “ANDing” of the SCL line is used to implement handshaking between

the host and the device. The device extends the SCL low period by pulling the SCL line low

whenever it needs extra time for processing between the data transmissions.

Note: Each write or read cycle must end with a stop condition. The device may not respond

correctly if a cycle is terminated by a new start condition.

Figure D-6 shows a typical data transmission. Note that several data bytes can be transmitted

between the SLA+R/W and the STOP.

Figure D-6. Byte Transmission

Addr MSB

Addr LSB

Data MSB

Data LSB

ACK

R/W

SDA

SCL

1

2

7

8

9

1

2

7

8

9

START

SLA+RW

Data Byte

STOP

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Appendix E. Table of Contents

Features..................................................................................................... 1

1

2

Overview of the mXT3432S1 ................................................................... 2

1.1

1.2

Introduction ........................................................................................................2

Chipset Architecture ..........................................................................................3

Pinouts ...................................................................................................... 4

2.1

2.2

2.3

Pinout Configurations ........................................................................................4

Pinout Descriptions ............................................................................................7

Schematics ......................................................................................................16

3

4

Touchscreen Basics .............................................................................. 19

3.1

3.2

3.3

3.4

Sensor Construction ........................................................................................19

Electrode Configuration ...................................................................................19

Scanning Sequence ........................................................................................20

Touchscreen Sensitivity ...................................................................................20

Detailed Operation ................................................................................. 21

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.9

4.10

Power-up/Reset ...............................................................................................21

Calibration .......................................................................................................23

Operational Modes ..........................................................................................23

Touchscreen Layout ........................................................................................23

Signal Processing ............................................................................................24

Circuit Components .........................................................................................26

PCB Layout .....................................................................................................27

Debugging .......................................................................................................27

Communications ..............................................................................................28

Configuring the Chipset ...................................................................................28

5

I2C-compatible Communications ......................................................... 29

5.1

5.2

5.3

5.4

5.5

5.6

5.7

5.8

Communications Protocol ................................................................................29

I2C-compatible Addresses ..............................................................................29

Writing To the Chipset .....................................................................................29

I²C-compatible Writes in Checksum Mode ......................................................30

Reading From the Chipset ...............................................................................30

Reading Status Messages with DMA ..............................................................31

CHG Line .........................................................................................................33

WAKE Line ......................................................................................................35

87

9853BX–AT42–03/13

5.9

SDA, SCL ........................................................................................................36

Clock Stretching ..............................................................................................36

5.10

6

USB Communications ........................................................................... 37

6.1

6.2

6.3

6.4

6.5

6.6

Communications Protocol ................................................................................37

Endpoint Addresses ........................................................................................37

Composite Device ...........................................................................................38

Interface 0 (Digitizer HID) ................................................................................38

Interface 1 (Generic HID) ................................................................................42

USB Suspend Mode ........................................................................................49

7

HID-I2C-compatible Communications .................................................. 50

7.1

7.2

7.3

7.4

7.5

7.6

7.7

7.8

7.9

Communications Protocol ................................................................................50

I²C-compatible Addresses ...............................................................................50

Device ..............................................................................................................50

Interface 0 (Digitizer HID-I²C) ..........................................................................50

Interface 1 (Generic HID-I²C) ..........................................................................54

CHG Line .........................................................................................................58

SDA, SCL ........................................................................................................59

Clock Stretching ..............................................................................................59

Microsoft Windows 8 Compliance ...................................................................59

8

9

Getting Started with mXT3432S1 .......................................................... 60

8.1

8.2

8.3

8.4

8.5

Establishing Contact ........................................................................................60

Using the Object Protocol ................................................................................60

Writing to the Chipset ......................................................................................60

Reading from the Chipset ................................................................................61

Configuring the Chipset ...................................................................................61

Specifications ......................................................................................... 63

9.1

9.2

9.3

9.4

9.5

9.6

9.7

9.8

9.9

Absolute Maximum Specifications ...................................................................63

Recommended Operating Conditions .............................................................63

DC Characteristics ...........................................................................................63

ESD Information ..............................................................................................64

Supply Current .................................................................................................64

Power Consumption ........................................................................................66

Timing Specifications .......................................................................................68

I2C-compatible Specifications .........................................................................68

USB Specification ............................................................................................69

88

mXT3432S1

9853BX–AT42–03/13

mXT3432S1

9.10

9.11

9.12

9.13

9.14

9.15

9.16

9.17

9.18

HID-I²C Specification .......................................................................................69

Touch Accuracy and Repeatability ..................................................................69

Power Supply and Ripple Noise ......................................................................69

Thermal Packaging ..........................................................................................70

Soldering Profile ..............................................................................................70

Mechanical Dimensions ...................................................................................71

Part Marking ....................................................................................................74

Part Numbers ..................................................................................................75

Moisture Sensitivity Level (MSL) .....................................................................75

Appendix A

PCB Design Considerations ............................................ 76

Introduction ......................................................................................................76

Printed Circuit Board .......................................................................................76

Supply Rails and Ground Tracking ..................................................................76

Power Supply Decoupling ...............................................................................76

Suggested Voltage Regulator Manufacturers ..................................................77

Crystal Oscillator .............................................................................................78

Analog I/O ........................................................................................................78

Component Placement ....................................................................................79

Digital Signals ..................................................................................................79

EMC and Other Observations .........................................................................79

A.1

A.2

A.3

A.4

A.5

A.6

A.7

A.8

A.9

A.10

Appendix B

Glossary of Terms ............................................................ 80

Appendix C

QMatrix Primer .................................................................. 82

Acquisition Technique .....................................................................................82

Moisture Resistance ........................................................................................82

Interference Sources .......................................................................................83

C.1

C.2

C.3

Appendix D

I2C Basics (I2C-compatible Operation) .......................... 84

Interface Bus ...................................................................................................84

Transferring Data Bits ......................................................................................84

START and STOP Conditions .........................................................................85

Address Byte Format .......................................................................................85

Data Byte Format ............................................................................................85

Combining Address and Data Bytes into a Transmission ...............................86

9.19

D.1

D.2

D.3

D.4

D.5

Appendix E

Table of Contents ............................................................. 87

Revision History...................................................................................... 90

89

9853BX–AT42–03/13

Revision History

Revision Number

History

Revision AX – March 2013

Revision BX – March 2013

Initial release for firmware revision 2.0

Updated with QS number

90

mXT3432S1

9853BX–AT42–03/13

mXT3432S1

Notes

91

9853BX–AT42–03/13

Headquarters

International

Atmel Corporation

1600 Technology Drive

San Jose, CA 95110

USA

Tel: (+1) (408) 441-0311

Fax: (+1) (408) 436-4314

Atmel Asia

Atmel Munich GmbH

Business Campus

Parkring 4

D- 85748 Garching b.

MUNICH

Atmel Japan

16F Shin-Osaki Kangyo Building

1-6-4 Osaki

Shinagawa-ku, Tokyo 141-0032

JAPAN

Tel: (+81) (3) 6417-0300

Fax: (+81) (3) 6417-0370

Unit 01-05 & 16, 19F

BEA Tower, Millennium City 5

418 Kwun Tong Road

Kwun Tong

Kowloon

HONG KONG

Tel: (+49) 89-31970-111

Fax: (+49) 89-3194621

Tel: (+852) 2245-6100

Fax: (+852) 2722-1369

Touch Technology Division

1560 Parkway

Solent Business Park

Whiteley

Fareham

Hampshire

PO15 7AG

UNITED KINGDOM

Tel: (+44) (0) 844 894 1920

Fax: (+44) (0) 1489 557 066

Product Contact

Web Site

Technical Support

Sales Contact

www.atmel.com

touch@atmel.com

www.atmel.com/contacts

Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any

intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND

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9853BX–AT42–03/13


型号：	ATMXT3432S-S-CUR034
厂家：	MICROCHIP
描述：	Analog Circuit, 1 Func, PBGA128
文件：	总92页 (文件大小：2620K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ATMXT3432S-S-CUR034 [MICROCHIP]

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