ATMX150RHA-324 [MICROCHIP]
Rad-Hard 150 nm SOI CMOS Cell-based ASIC for Space Use;型号: | ATMX150RHA-324 |
厂家: | MICROCHIP |
描述: | Rad-Hard 150 nm SOI CMOS Cell-based ASIC for Space Use |
文件: | 总22页 (文件大小:224K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ATMX150RHA
Rad-Hard 150 nm SOI CMOS Cell-based ASIC for Space
Use
Introduction
ATMX150RHA is a mixed-signal ASIC offer that provides high-performance and high-density solutions for space
applications. With a set of pre-qualified analog IPs, such as DACs, ADCs, PLL, regulators, etc., ATMX150RHA eases
the design of mixed-signal ASICs.
ATMX150RHA covers the digital ATC18RHA ASIC offer and extends it up to 22 million gates. The availability of a
5V to 1.8V regulator and the 5V tolerant IO permits easy re-targeting of obsolete or end-of-life ASICs with 5V core
supply. In addition, the Physical Design Kit (PDK) enables customers to develop their own analog blocks and use the
Microchip Space Multi-Project Wafer (SMPW) foundry services.
ATMX150RHA is manufactured on a 150 nm, five-metal-layer and thick-metal-layer SOI CMOS process intended
for use with a supply voltage of 1.8V for core and 2.5/3.3/5V for periphery. This ASIC platform is supported by
®
®
®
a combination of state-of-the-art third-party and proprietary design tools from Synopsys , Mentor and Cadence .
These tools collectively form the reference tool flows for both the front and back ends.
ATMX150RHA ASICs are available in several quality assurance grades, such as MIL-PRF-38535, QML-Q , QML-V,
and ESCC 9000 for the digital domain:
•
•
ESCC DS: 9202/083
SMD: 5962-20B01
DS60001543C-page 1
Datasheet
© 2021 Microchip Technology Inc.
ATMX150RHA
Table of Contents
Introduction.....................................................................................................................................................1
1. Overview................................................................................................................................................. 4
2. Periphery.................................................................................................................................................5
2.1. Buffer Descriptions.......................................................................................................................5
2.2. I/O Clusters.................................................................................................................................. 5
2.3. Double Pad Ring.......................................................................................................................... 5
3. Core........................................................................................................................................................ 6
3.1. Standard Cell Library....................................................................................................................6
3.2. Memory Hard Blocks....................................................................................................................6
3.3. Analog Blocks...............................................................................................................................6
3.4. Array Organization....................................................................................................................... 7
4. Advanced Packaging.............................................................................................................................. 8
5. Space Multi-Project Wafer (SMPW)........................................................................................................9
6. Testability Techniques........................................................................................................................... 10
7. Radiation Hardness...............................................................................................................................11
8. Electrical Characteristics.......................................................................................................................12
8.1. Absolute Maximum Ratings........................................................................................................12
8.2. Recommended Operating Conditions........................................................................................ 12
8.3. Consumption.............................................................................................................................. 12
8.4. 2.5V I/O DC Characteristics....................................................................................................... 13
8.5. 3.3V I/O DC Characteristics....................................................................................................... 14
8.6. 5V I/O DC Characteristics.......................................................................................................... 14
8.7. PCI Characteristics.....................................................................................................................15
8.8. LVPECL Receiver Characteristics..............................................................................................16
8.9. LVDS Reference Characteristics................................................................................................16
8.10. LVDS Transmitter Characteristics.............................................................................................. 17
8.11. LVDS Receiver Characteristics.................................................................................................. 17
9. Support..................................................................................................................................................18
10. Revision History.................................................................................................................................... 19
The Microchip Web Site............................................................................................................................... 20
Customer Change Notification Service........................................................................................................ 20
Customer Support........................................................................................................................................ 20
Microchip Devices Code Protection Feature................................................................................................20
Legal Notice................................................................................................................................................. 21
Trademarks.................................................................................................................................................. 21
DS60001543C-page 2
Datasheet
© 2021 Microchip Technology Inc.
ATMX150RHA
Quality Management System Certified by DNV........................................................................................... 21
Worldwide Sales and Service.......................................................................................................................22
DS60001543C-page 3
Datasheet
© 2021 Microchip Technology Inc.
ATMX150RHA
Overview
1.
Overview
The ATMX150RHA Design Manual, available from your Microchip technical center, provides the information and
flows necessary to design a mixed-signal ASIC for space applications. Users can be trained on Microchip-specific or
standard commercial tool kits and methodological details for actual implementations.
This offering is CMOS-technology-based, specified with 5/3.3/2.5V and HV 25-45V ranges for the periphery. Core is
supplied at 1.8V.
ATMX150RHA is manufactured on a 150nm, five-metal-layers SOI CMOS with Thick Metal technology option -
AT77KRHA, a Microchip proprietary process. The digital ATMX150RHA is qualified under the QML-V, QML-Q, and
ESCC QML. The domain of qualification covers the main features as follows.
•
•
•
•
•
•
•
•
•
•
•
Comprehensive library of standard logic and I/O cells
Memory Cells Compiled (ROM, SRAM, DPRAM, and Register File Memory)
450 MHz PLL (PLL400MRHA)
Up to 22 usable Mgates (equivalent NAND2)
Operating voltage 1.8±0.15V for the core and 5V±0.5V, 3.3±0.3V, 2.5±0.2V for the periphery
High-speed LVDS buffers 655 Mbps in compliance with the TIA/EIA-644-A standard
PCI buffers
Set of analog blocks
No single event latch-up below an LET threshold of 78 MeV.cm2/mg at 125°C
SEU-hardened flip-flops
TID test up to 150 krads (Si) for 1.8V and 3.3V devices, and 90 krads (Si) for 5V according to MIL-STD 883
TM1019
•
CCGA, CLGA, and CQFP qualified package catalog
DS60001543C-page 4
Datasheet
© 2021 Microchip Technology Inc.
ATMX150RHA
Periphery
2.
Periphery
2.1
Buffer Descriptions
The peripheral I/O buffer is the electrical interface between the external signals (voltage range from 2.3V to 3.6V and
from 4.5V to 5.5V) and the internal core signals (from 1.65V to 1.95V).
I/O libraries are:
•
•
•
IO5V0 I/O – Powered at 5V
IO3V3 I/O – Powered at 3.3V
IO2V5 I/O – Powered at 2.5V, 3.3V tolerant
All I/O buffers are cold sparing and include:
•
•
•
•
Bidirectional I/O buffers
Tristate-output I/O buffers
Output-only I/O buffers
Input-only I/O buffers (inverting, non-inverting, Schmitt trigger)
Furthermore, the bidirectional, tristate-output and input-only I/O buffers are available with or without pull-up or
pull-down structures.
Specific I/O buffers have been developed in 3.3V and 2.5V:
•
•
•
LVDS transmitter and receiver differential I/O buffers.
LVPECL receiver differential I/O buffers
In 3.3V, PCI-compliant output buffer
I/O buffers are tolerant, that is, the pad signal can be higher than VCCB when it is high impedance (input or
bidirectional buffers, tristate buffers in HiZ and LVDS when disable).
I/O buffers are cold sparing, that is, the pad signal can be applied when VCCB is 0V. In both cases, tolerant or
cold sparing, there is no impact on core supply, buffer supply, and reliability, if the applied signal respects the
recommended operating conditions, and the leakage current is less than 1µA.
2.2
2.3
I/O Clusters
The periphery of the chip (pad ring) can be split into several I/O segments (I/O clusters). Some clusters can be
unpowered while others are active.
A specific power control line is distributed inside the cluster to force all the I/Os of the cluster in tristate mode
regardless of their initial state (i.e., an output-only buffer will also be turned to HiZ mode).
Double Pad Ring
In case of a large number of IOs, Microchip can provide a double pad ring configuration, where the inner ring is used
exclusively for core power supply pads.
DS60001543C-page 5
Datasheet
© 2021 Microchip Technology Inc.
ATMX150RHA
Core
3.
Core
3.1
Standard Cell Library
The Microchip Standard Cell Library contains a comprehensive set of logic and storage cells, including cells that
belong to the following categories:
•
•
•
•
•
Buffers and gates
Standard and SEU-hardened flip-flops
Standard and SEU-hardened scan flip-flops
Latches
Multiplexers, adders, subtractors
3.2
Memory Hard Blocks
The ATMX150RHA memory libraries are developed from Virage memory compilers. All these memories are
synchronous. Four types of memories can be generated on request:
•
•
•
•
Single-port synchronous SRAM
Dual-port memory with two-port read/write synchronous SRAM
Two-port synchronous register file with one read port and one write port
ROM with metal programming
For maximum block sizes, refer to ATMX150RHA Design Manual, available from your Microchip technical center.
3.3
Analog Blocks
MICROCHIP proposes a catalog of analog IPs qualified that can be delivered with a datasheet and qualpack.
The qualification includes:
•
•
•
Electrical characterization
TID and SEE characterization
HTOL tests
The analog IPs consist of Voltage regulators, a voltage reference and monitoring device, clock synthesizer and signal
conditioning IPs.
For more information on a complete list of available analog blocks, please contact the Microchip technical support
team in your region.
The following table lists the preliminary IP blocks and their features.
Table 3-1.ꢀAnalog Blocks Catalog
IP Block
Features
PLL400MRHA
ADC12RHA
DAC12RHA
MUX8RHA
40-450 MHz PLL
12-bit 1 Msps ADC
12-bit 1 Msps DAC
8-channel analog multiplexer, 10 MHz bandwidth
OSCRC10MRHA Programmable 4/8/10/12 MHZ RC oscillator, ±1% frequency variation over temperature
OSCRC32KRHA
BG1V2RHA
32 kHz RC oscillator
1.215V bandgap voltage reference, max temp. coef 90 ppm/°C
DS60001543C-page 6
Datasheet
© 2021 Microchip Technology Inc.
ATMX150RHA
Core
...........continued
IP Block
Features
REG200RHA
POR18RHA
Linear voltage regulator from 3-5.5V to 1.8V, 200 mA
Power-on Reset 1.8V
A Physical Design Kit (PDK), with a full set of basic devices, is also available to design custom analog blocks.
3.4
Array Organization
With the ATMX150RHA, the die size and the package are optimized for each mixed-signal ASIC.
However, for some digital designs, predefined matrix sizes and pad frames are available to ease the assembly of
each individual ASIC design by using available package cavity sizes and layouts.
Table 3-2.ꢀStandard Array Dimensions
Single Pad Ring
Double Pad Ring
Outer Ring
Pads
Area (mm2) Typical Usable
gates(*)
Inner Ring Typical Usable Gates(*)
Pads
Name
ATMX150RHA_216(D)
ATMX150RHA_324(D)
ATMX150RHA_404(D)
ATMX150RHA_504(D)
ATMX150RHA_544(D)
ATMX150RHA_604(D)
ATMX150RHA_644 (D)
ATMX150RHA_704(D)
38
1M
2.2M
3.5M
5.5M
6.5M
7.6M
8.7M
10.4M
216
324
404
504
544
604
644
704
88
0.8M
1.7M
2.8M
4.4M
5.4M
6.7M
7.7M
9.4M
77
140
180
232
252
284
304
332
114
170
199
237
267
316
(*) Based on NAND2 equivalent at 50% density, without memories
DS60001543C-page 7
Datasheet
© 2021 Microchip Technology Inc.
ATMX150RHA
Advanced Packaging
4.
Advanced Packaging
Microchip proposes advanced multilayer low-noise CQFP and CCGA packages with isolated power and ground
planes.
CQFP packages are available with up to 352 leads and CLGA/CCGA packages with up to 896 lands/columns. In
addition to the packages listed in the following table, Microchip offers custom package development.
Table 4-1.ꢀPackages
Package
CQFP
Leads/Columns
Up to 352
CLGA/CCGA
349, 472, 625, 896
DS60001543C-page 8
Datasheet
© 2021 Microchip Technology Inc.
ATMX150RHA
Space Multi-Project Wafer (SMPW)
5.
Space Multi-Project Wafer (SMPW)
Microchip offers a Space Multi-Project Wafer (SMPW) service, in order to decrease the cost of reticles and silicon
by sharing them over several designs. Specific milestones have been created to coordinate the activities and ensure
that there will be no interaction between customer designs.
Any questions related to the SMPW service can be addressed to your Microchip technical center.
DS60001543C-page 9
Datasheet
© 2021 Microchip Technology Inc.
ATMX150RHA
Testability Techniques
6.
Testability Techniques
For complex designs involving blocks of memory and/or cores, careful attention must be given to design-for-test
techniques. The chip size of complex designs, and the number of functional vectors that would need to be created
to exercise them fully, strongly suggests the use of more efficient techniques. Combinations of SCAN technique,
multiplexed access to memory and/or core blocks, and built-in-self-test logic must be employed, in addition to
functional test patterns, to provide both the user and Microchip the ability to test the finished product. Test at speed
and transition delay fault patterns are also needed to achieve a good sorting of the dies.
For further information, refer to the ATMX150RHA TOS Manual, available from your Microchip technical center.
DS60001543C-page 10
Datasheet
© 2021 Microchip Technology Inc.
ATMX150RHA
Radiation Hardness
7.
Radiation Hardness
The ATMX150RHA standard cell library encompasses all the specific functions and buffers necessary for space
designs, such as LVDS transmitters and receivers, PCI buffers, SEU-hardened DFFs and cold sparing buffers. Key
radiation-tolerance parameters are controlled and monitored. Reports are available upon request from your Microchip
technical center.
Table 7-1.ꢀRadiation Hardness
Parameter
Radiation Hardness Assurance
100 krads (Si) with 2.5V to 3.3V I/Os
50 krads (Si) with 5V and HV I/Os
TID(1)
Total Ionizing Dose
SEU(2)
Single Event Upset
Hardened DFF: < 3.22e-09 errors/bit/day
Virage memories with ECC: < 1.18e-10 errors/bit/day
SEL(3)
Standard results: LETth > 78 MeV.cm²/mg
Single Event Latch-up
With deep trench isolation LETth > 95 MeV.cm²/mg
Notes:ꢀ
1. Co-60 testing, in compliance with Mil-Std 883 TM 1019.5: Tested at 25°C, with a total dose rate of 300 rad/h
and a total dose up to 150 krads (Si) or 90 krads (Si).
2. Based on worst-case orbit condition (between GEO, ISS LEO, LEO POL, and MEO), at 1.65V for core and
25°C.
3. In worst-case conditions: 1.95V for core, 3.6V or 5.5V for I/Os at 125°C
DS60001543C-page 11
Datasheet
© 2021 Microchip Technology Inc.
ATMX150RHA
Electrical Characteristics
8.
Electrical Characteristics
8.1
Absolute Maximum Ratings
Symbol
TJ
Parameter
Min
–
Max
175
2
Unit
°C
V
Operating Temperature
Core Supply Voltage
2.5V IO Supply Voltage
3.3V IO Supply Voltage
5V IO Supply Voltage
Storage Temperature
VDD
VCC
VCC
VCC
Tstg
-0.3
-0.3
-0.3
-0.3
-65
3
V
4
V
6
V
150
°C
Note:ꢀ Stresses beyond the ones listed in this table may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
8.2
Recommended Operating Conditions
Symbol
TJ
Parameter
Min
-55
1.65
2.3
Typ
25
Max
145
1.95
2.7
Unit
°C
V
Test Conditions
Operating Temperature
Core Supply Voltage
2.5V IO Supply Voltage
3.3V IO Supply Voltage
5V IO Supply Voltage
–
–
–
–
–
VDD
VCC
VCC
VCC
1.8
2.5
3.3
5
V
3.0
3.6
V
4.5
5.5
V
Note:ꢀ Functional operations beyond those listed in this table are not guaranteed.
8.3
Consumption
Symbol
ICCSBA
ICCOPA(*)
Parameter
Min
–
Typ
0.003
40
Max
4.4
57
Unit
µA
Test Conditions
Leakage current per k gate
Dynamic current per k gate
–
–
–
µA/MHz
(*) Average on a mix of cells of different types (regular and hardened flip-flop, simple and complex boolean,
multiplexer, adder, buffer and inverter).
DS60001543C-page 12
Datasheet
© 2021 Microchip Technology Inc.
ATMX150RHA
Electrical Characteristics
8.4
2.5V I/O DC Characteristics
Symbol Parameter
Min
2.3
-1
Typ
2.5
–
Max
2.7
1
Unit
V
Test Conditions
VCC
IIL
Buffer Supply Voltage
Low-level Input Current
– With pull-up resistor
– With pull-down resistor
IOs
µA
µA
µA
60
-5
130
–
260
5
Vin=Vss
Vin=Vcc
High-level Input Current
– With pull-up resistor
– With pull-down resistor
-1
-5
–
–
1
5
µA
µA
µA
IIH
75
180
360
Vout=Vcc or Vss
No pull resistor
IOZ
High impedance state output current
-1
–
1
µA
VIL
Low-level input voltage
-0.3
2
–
0.7
Vcc+0.3
1.59
V
V
V
V
V
–
VIH
VT+
VT-
High-level input voltage
–
–
Positive-going Schmitt trigger threshold
Negative-going Schmitt trigger threshold
Schmitt trigger hysteresis
1.11
0.81
0.30
1.35
0.93
0.42
–
1.17
–
Vhyst
0.54
–
Vcc=Vss=0V
Vin=0 to Vcc
IICS
Cold sparing leakage input current
Cold sparing leakage output current
-1
-1
–
–
1
1
µA
µA
Vcc=Vss=0V
Vout=0 to Vcc
IOCS
VCSth
VOL
Supply threshold of cold sparing buffers
Low-level output voltage
High-level output voltage
Output short-circuit current
– IOSN (nn=1)
–
–
–
–
–
0.5
0.4V
–
V
V
V
IICS < 4 μA
IOL=1.5, 3, 6, 9, 12 mA
IOH=1.5, 3, 6, 9, 12 mA
VOH
VCC-0.4
14
14
mA
mA
Vout=Vcc
Vout=Vss
IOS(*)
Fmax
–
–
–
–
– IOSP (nn=1)
13
50
80
nn = 1
nn = 4
nn = 8
Maximum frequency, Cload = 30 pF
MHz
(*) Supplied as a design limit but not guaranteed or tested. No more than one output may be shorted at a time for a
maximum duration of 10 seconds.
IOSmax = 14, 28, 56, 84, 112 mA for nn = 1, 2, 4, 6, 8
DS60001543C-page 13
Datasheet
© 2021 Microchip Technology Inc.
ATMX150RHA
Electrical Characteristics
8.5
3.3V I/O DC Characteristics
Symbol Parameter
Min
3.0
-1
Typ
3.3
–
Max
3.6
1
Unit
V
Test Conditions
VCC
IIL
Buffer supply voltage
Low-level input current
– With pull-up resistor
– With pull-down resistor
IOs
µA
µA
µA
110
-5
220
–
400
5
Vin=Vss
Vin=Vcc
High-level input current
– With pull-up resistor
– With pull-down resistor
-1
-5
–
–
1
5
µA
µA
µA
IIH
140
320
600
Vout=Vcc or Vss
No pull resistor
IOZ
High impedance state output current
-1
–
1
µA
VIL
Low-level input voltage
-0.3
2
–
0.8
Vcc+0.3
1.95
V
V
V
V
V
–
–
–
–
–
VIH
VT+
VT-
High-level input voltage
–
Positive-going Schmitt trigger threshold
Negative-going Schmitt trigger threshold
Schmitt trigger hysteresis
1.47
1.05
0.36
1.73
1.25
0.48
1.53
Vhyst
0.54
Vcc=Vss=0V
Vin=0 to Vcc
IICS
Cold sparing leakage input current
Cold sparing leakage output current
-1
-1
–
–
1
1
µA
µA
Vcc=Vss=0V
Vout=0 to Vcc
IOCS
VCSth
VOL
Supply threshold of cold sparing buffers
Low-level output voltage
High-level output voltage
Output short-circuit current
IOSN (nn=1)
–
–
–
–
0.5
V
V
V
IICS < 4μA
0.4V
IOL=2, 4, 8, 12, 16 mA
IOH=2, 4, 8, 12, 16 mA
VOH
VCC-0.4
23
23
mA
mA
Vout=Vcc
Vout=Vss
IOS(*)
Fmax
–
–
–
–
IOSP (nn=1)
15
70
nn = 1
nn = 4
nn = 8
Maximum frequency, Cload = 30 pF
MHz
105
(*) Supplied as a design limit but not guaranteed or tested. No more than one output may be shorted at a time for a
maximum duration of 10 seconds.
IOSmax = 23, 46, 92, 138,184 mA for nn = 1, 2, 4 ,6, 8
8.6
5V I/O DC Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VCC
Buffer supply voltage
4.5
5.0
5.5
V
IOs
DS60001543C-page 14
Datasheet
© 2021 Microchip Technology Inc.
ATMX150RHA
Electrical Characteristics
...........continued
Symbol
Parameter
Min
-1
Typ
–
Max
1
Unit
µA
Test Conditions
Low-level input current
– With pull-up resistor
– With pull-down resistor
180
-5
340
–
590
5
µA
IIL
Vin=Vss
µA
High-level input current
– With pull-up resistor
– With pull-down resistor
-1
-5
–
–
1
5
µA
µA
µA
IIH
Vin=Vcc
160
490
1000
Vout=Vcc or Vss
No pull resistor
IOZ
High impedance state output current
-1
–
1
µA
VIL (TTL)
VIH (TTL)
Low-level input voltage
High-level input voltage
-0.3
2
–
–
0.8
Vcc+0.3
0.3*Vcc
Vcc+0.3
3.69
V
V
V
V
V
V
V
For TTL inputs
For TTL inputs
For CMOS inputs
For CMOS inputs
–
VIL (CMOS) Low-level input voltage
VIH (CMOS) High-level input voltage
-0.3
–
0.7*Vcc
2.69
1.81
0.77
–
VT+
VT-
Positive-going Schmitt trigger threshold
3.19
2.20
0.99
Negative-going Schmitt trigger threshold
Schmitt trigger hysteresis
2.70
–
Vhyst
1.1
–
Vcc=Vss=0V
Vin=0 to Vcc
IICS
Cold sparing leakage input current
Cold sparing leakage output current
-1
-1
–
–
1
1
µA
µA
Vcc=Vss=0V
Vout=0 to Vcc
IOCS
VCSth
VOL
Supply threshold of cold sparing buffers
Low-level output voltage
High-level output voltage
Output short-circuit current
IOSN (nn=1)
–
–
–
–
–
0.5
0.4V
–
V
V
V
IICS < 4 μA
IOL=2, 8, 16 mA
IOH=2, 8 ,16 mA
VOH
VCC-0.4
40
40
mA
mA
Vout=Vcc
Vout=Vss
IOS(*)
Fmax
–
–
–
–
IOSP (nn=1)
11
43
68
nn = 1
nn = 4
nn = 8
Maximum frequency, Cload = 30 pF
MHz
(*) Supplied as a design limit but not guaranteed or tested. No more than one output may be shorted at a time for a
maximum duration of 10 seconds.
IOSmax = 140, 420 mA for nn = 4 , 8
8.7
PCI Characteristics
Symbol Parameter
Min
Typ
Max
Unit
Test Conditions
VCC
Buffer supply voltage
3.0
3.3
3.6
V
IOs
DS60001543C-page 15
Datasheet
© 2021 Microchip Technology Inc.
ATMX150RHA
Electrical Characteristics
...........continued
Symbol Parameter
Min
0.5 Vcc
-0.3
16
Typ
–
Max
Vcc + 0.3
0.3 VCC
–
Unit
V
Test Conditions
–
VIH
High-level input voltage
VIL
Low-level input voltage
High-level current
–
V
–
IOH
32
32
112
–
mA
mA
mA
V
VOH=Vcc - 0.4V
VOL=0.4V
VOH=0; VOL=Vcc
IICS < 4 μA
IOL
Low-level current
16
–
IOS(*)
VCSTH
Output short current
–
184
Supply threshold of cold sparing buffers
–
0.5
(*) Supplied as a design limit but not guaranteed or tested. No more than one output may be shorted at a time for a
maximum duration of 10 seconds.
8.8
LVPECL Receiver Characteristics
DC Specifications
Applicable over recommended operating temperature and voltage ranges unless otherwise noted.
Symbol
VCC
Parameter
Min
3.0
2.3
-10
–
Typ
3.3
2.5
–
Max
3.6
2.7
10
Unit
V
Test Conditions
Buffer supply voltage
Buffer supply voltage
Input leakage
–
VCC
V
–
IIN
µA
mA
µA
mA
µA
–
ICCstat
ICCstdby
ICCstat
ICCstdby
Static consumption (ien=0)
Static consumption (ien=1)
Static consumption (ien=0)
Static consumption (ien=1)
2.5
–
4
VCC=3.3±0.3V
VCC=3.3±0.3V
VCC=2.5±0.2V
VCC=2.5±0.2V
–
10
–
1.5
–
2.3
5.8
–
8.9
LVDS Reference Characteristics
DC Specifications
Applicable over recommended operating temperature and voltage ranges unless otherwise noted.
Symbol
VCC
Parameter
Min
3.0
2.3
Typ
3.3
2.5
Max
3.6
Unit
V
Test Conditions
Buffer supply voltage
Buffer supply voltage
–
–
VCC
2.7
V
1.25
- 5%
Vref
Input voltage
1.25
1.25 + 5%
V
–
Rpd
Pull-down resistance
140
–
200
260
–
260
320
2
kOhm
µA
VIN=1.25V
ICCstat
ICCstdby
ICCstat
ICCstdby
Static consumption (ien=0)
Static consumption (ien=1)
Static consumption (ien=0)
Static consumption (ien=1)
VCC=3.3±0.3V
VCC=3.3±0.3V
VCC=2.5±0.25V
VCC=2.5±0.25V
–
µA
–
150
–
184
1.2
µA
–
µA
DS60001543C-page 16
Datasheet
© 2021 Microchip Technology Inc.
ATMX150RHA
Electrical Characteristics
8.10
LVDS Transmitter Characteristics
DC Specifications
Applicable over recommended operating temperature and voltage ranges unless otherwise noted.
Symbol
VCC
Parameter
Min Typ Max Unit
Test Conditions
–
Buffer supply voltage
Buffer supply voltage
Output differential voltage
Output offset voltage
3.0
2.3
247
3.3
2.5
350
3.6
2.7
454
V
V
VCC
–
VOD*
VOS*
mV
V
Rload = 100 ohms
Rload = 100 ohms
Rload = 100 ohms
1.125 1.25 1.375
|DVOD|* Change in |VOD|
–
–
50
50
Change in VOS - steady state
mV
mV
|DVOS|*
–
–
Rload = 100 ohms
Change in VOS - dynamic state
150
7
24
12
mA
mA
Drivers shortened to ground or VCC
Drivers shortened together
IOS*
Output short current
–
4.5
ICCstat
Static consumption (ien=0)
–
–
4
–
6
mA
µA
mA
µA
µA
VCC=3.3±0.3V
VCC=3.3±0.3V
VCC=2.5±0.25V
VCC=2.5±0.25V
Vout=Vcc or Vss
ICCstdby Static consumption (ien=1)
ICCstat Static consumption (ien=0)
ICCstdby Static consumption (ien=1)
IOZ High Impedance State Output
10
3.5
5.8
1
–
2.3
–
–
-1
–
Note:ꢀ *: Meet or exceed TIA/EIA-644-A standard.
8.11
LVDS Receiver Characteristics
DC Specifications
Applicable over recommended operating temperature and voltage ranges unless otherwise noted.
Symbol
VCC
Parameter
Min
3.0
2.3
100
0.05
-10
–
Typ
3.3
2.5
–
Max
3.6
2.7
600
2.35
10
Unit
V
Test Conditions
Buffer supply voltage
Buffer supply voltage
Input differential voltage
Common mode input voltage
Input leakage
–
VCC
V
–
VID*
mV
V
–
VCM*
–
–
IIN*
–
µA
mA
µA
mA
µA
–
ICCstat
ICCstdby
ICCstat
ICCstdby
Static consumption (ien=0)
Static consumption (ien=1)
Static consumption (ien=0)
Static consumption (ien=1)
3.5
–
6
VCC=3.3±0.3V
VCC=3.3±0.3V
VCC=2.5±0.25V
VCC=2.5±0.25V
–
10
–
2
3.5
5.8
–
–
Note:ꢀ *: Meet or exceed TIA/EIA-644-A standard.
DS60001543C-page 17
Datasheet
© 2021 Microchip Technology Inc.
ATMX150RHA
Support
9.
Support
Technical support is available by contacting aerospace@nto.atmel.com.
DS60001543C-page 18
Datasheet
© 2021 Microchip Technology Inc.
ATMX150RHA
Revision History
10.
Revision History
Table 10-1.ꢀRevision History
Doc Rev. Date
Comments
C
03/2021 Updated the following sections.
•
•
•
•
Radiation Hardness.
Absolute Maximum Ratings.
Recommended Operating Conditions.
LVDS Receiver Characteristics.
B
06/2020 Main content updates:
•
•
•
•
•
•
•
•
•
•
Introduction
Overview
Buffer Descriptions
Analog Blocks
Absolute Maximum Ratings
2.5V I/O DC Characteristics
3.3V I/O DC Characteristics
5V I/O DC Characteristics
LVDS Transmitter Characteristics
LVDS Receiver Characteristics
A
08/2018 Main content updates: operating conditions, analog blocks, IO DC characteristics, radiation.
Template update: Moved from Atmel to Microchip template.
The datasheet is assigned a new document number (DS60001543) and revision letter is reset
to A.
ISBN number assigned.
44059 1.1 08/2016 Details on LVDS High Speed LVDS Buffers 655 Mbps according to the TIA/EIA-644-A std.
44059 1.0 01/2015 First issue.
DS60001543C-page 19
Datasheet
© 2021 Microchip Technology Inc.
ATMX150RHA
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There are dishonest and possibly illegal methods used to breach the code protection feature. All of
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DS60001543C-page 20
Datasheet
© 2021 Microchip Technology Inc.
ATMX150RHA
Legal Notice
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ISBN: 978-1-5224-7889-8
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®
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Company’s quality system processes and procedures are for its PIC MCUs and dsPIC DSCs, KEELOQ
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DS60001543C-page 21
Datasheet
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