ATA5428C-PLQW_技术文档

ATA5428

UHF ASK/FSK Transceiver

DATASHEET

Features

● Multi channel half-duplex transceiver with approximately ±2.5MHz programmable

tuning range

● High FSK sensitivity: –106dBm at 20Kbit/s/–109.5dBm at 2.4Kbit/s (433.92MHz)

● High ASK sensitivity: –112.5dBm at 10Kbit/s/–116.5dBm at 2.4Kbit/s (433.92MHz)

● Low supply current: 10.5mA in RX and TX Mode (3V/TX with 5dBm)

● Data Rate: 1 to 20Kbit/s Manchester FSK, 1 to 10Kbit/s Manchester ASK

● ASK/FSK receiver uses a low-IF architecture with high selectivity, blocking, and low

intermodulation (typical blocking 55dB at ±750kHz/61dB at ±1.5MHz and

70dB at ±10MHz, system I1dBCP = –30dBm/system IIP3 = –20dBm)

● 226kHz/237kHz IF frequency with 30dB image rejection and 170kHz usable IF

bandwidth

● Transmitter uses closed loop fractional-N synthesizer for FSK modulation with a

high PLL bandwidth and an excellent isolation between PLL/VCO and PA

● Tolerances of XTAL compensated by fractional-N synthesizer with 800Hz RF

resolution

● Integrated RX/TX-switch, single-ended RF input and output

● RSSI (Received Signal Strength Indicator)

● Communication to microcontroller with SPI interface working at max.500kBit/s

● Configurable self polling and RX/TX protocol handling with FIFO-RAM buffering of

received and transmitted data

● Five push button inputs and one wake-up input are active in power-down mode

● integrated XTAL capacitors

● PA efficiency: up to 38% (433.92MHz/10dBm/3V)

● Low in-band sensitivity change of typically ±1.8dB within ±58kHz center frequency

change in the complete temperature and supply voltage range

● Supply voltage switch, supply voltage regulator, reset generation, clock/interrupt

generation and low battery indicator for microcontroller

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● Fully integrated PLL with low phase noise VCO, PLL loop filter and full support of multi-channel operation with arbitrary

channel distance due to fractional-N synthesizer

● Sophisticated threshold control and quasi-peak detector circuit in the data slicer

● Power management via different operation modes

● 433.92MHz and 868.3MHz without external VCO and PLL components

● Inductive supply with voltage regulator if battery is empty (AUX mode)

● Efficient XTO start-up circuit (> –1.5kΩ worst case real start-up impedance)

● Changing of modulation type ASK/FSK and data rate without component changes

● Minimal external circuitry requirements for complete system solution

● Adjustable output power: 0 to 10dBm adjusted and stabilized with external resistor

● ESD protection at all pins (1.5kV HBM, 200V MM, 1kV FCDM)

● Supply voltage range: 2.4V to 3.6V or 4.4V to 6.6V

● Temperature range: –40°C to +85°C

● Small 7 × 7mm QFN48 package

Applications

● Consumer industrial segment

● Access control systems

● Remote control systems

● Alarm and telemetry systems

● Energy metering

● Home automation

Benefits

● Low system cost due to very high system integration level

● Only one crystal needed in system

● Less demanding specification for the microcontroller due to handling of power-down mode, delivering of clock, reset, low

battery indication and complete handling of receive/transmit protocol and polling

● Single-ended design with high isolation of PLL/VCO from PA and the power supply allows a loop antenna in the remote

control unit to surround the whole application

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1.

General Description

The Atmel^®ATA5428 is a highly integrated UHF ASK/FSK multi-channel half-duplex transceiver with low power

consumption supplied in a small 7 x 7mm QFN48 package. The receive part is built as a fully integrated low-IF receiver,

whereas direct PLL modulation with the fractional-N synthesizer is used for FSK transmission and switching of the power

amplifier for ASK transmission.

The device supports data rates of 1Kbit/s to 20Kbit/s (FSK) and 1Kbit/s to 10Kbit/s (ASK) in Manchester, Bi-phase and other

codes in transparent mode. The ATA5428 can be used in the 431.5MHz to 436.5MHz and in the 862MHz to 872MHz bands.

The very high system integration level results in a small number of external components needed.

Due to its blocking and selectivity performance, together with the additional 15dB to 20dB loss and the narrow bandwidth of

a typical loop antenna in a remote control unit, a bulky blocking SAW is not needed in the remote control unit. Additionally,

the building blocks needed for a typical remote control and access control system on both sides (the base and the mobile

stations) are fully integrated.

Its digital control logic with self-polling and protocol generation enables a fast challenge-response system without using a

high-performance microcontroller. Therefore, the ATA5428 contains a FIFO buffer RAM and can compose and receive the

physical messages themselves. This provides more time for the microcontroller to carry out other functions such as

calculating crypto algorithms, composing the logical messages, and controlling other devices. Therefore, a standard 4-/8-bit

microcontroller without special periphery and clocked with the CLK output of about 4.5MHz is sufficient to control the

communication link. This is especially valid for passive entry and access control systems, where within less than 100ms

several challenge-response communications with arbitration of the communication partner have to be handled.

It is hence possible to design bi-directional remote control and access control systems with a fast challenge-response crypto

function, with the same PCB board size and with the same current consumption as uni-directional remote control systems.

Figure 1-1. System Block Diagram

ATA5428

RF Transceiver

Digital Control

Logic

Power

Supply

Antenna

ATmega

44/88/168

4 to 8

Matching/

RF Switch

Microcontroller

Interface

XTO

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Figure 1-2. Pinning QFN48

48 47 46 45 44 43 42 41 40 39 38 37

NC

1

2

3

4

5

6

7

8

9

36 RSSI

35 CS

34 DEM_OUT

33 SCK

32 SDI_TMDI

31 SDO_TMDO

30 CLK

RF_IN

NC

433_N868

NC

R_PWR

PWR_H

RF_OUT 10

NC 11

ATA5428

29 IRQ

28 N_RESET

27 VSINT

26 NC

NC 12

25 XTAL2

13 14 15 16 17 18 19 20 21 22 23 24

Table 1-1. Pin Description

1

Symbol

NC

Function

Not connected

RF input

2

NC

3

NC

4

RF_IN

NC

5

Not connected

6

433_N868

NC

Selects RF input/output frequency range

Not connected

7

8

R_PWR

PWR_H

RF_OUT

NC

Resistor to adjust output power

Pin to select output power

RF output

9

10

11

12

13

14

15

16

17

18

19

Not connected

NC

Not connected

NC

Not connected

NC

Not connected

NC

Not connected

AVCC

VS2

Blocking of the analog voltage supply

Power supply input for voltage range 4.4V to 6.6V

Power supply input for voltage range 2.4V to 3.6V

Auxiliary supply voltage input

VS1

VAUX

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Table 1-1. Pin Description (Continued)

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

Symbol

TEST1

DVCC

VSOUT

TEST2

XTAL1

XTAL2

NC

Function

Test input, at GND during operation

Blocking of the digital voltage supply

Output voltage power supply for external devices

Test input, at GND during operation

Reference crystal

Not connected

VSINT

N_RESET

IRQ

Microcontroller interface supply voltage

Output pin to reset a connected microcontroller

Interrupt request

CLK

Clock output to connect a microcontroller

Serial data out/transparent mode data out

Serial data in/transparent mode data in

Serial clock

SDO_TMDO

SDI_TMDI

SCK

DEM_OUT

CS

Demodulator open drain output signal

Chip select for serial interface

RSSI

Output of the RSSI amplifier

CDEM

RX_TX2

RX_TX1

PWR_ON

T5

Capacitor to adjust the lower cut-off frequency data filter

GND pin to decouple LNA in TX mode

Switch pin to decouple LNA in TX mode

Input to switch on the system (active high)

Key input 5 (can also be used to switch on the system (active low))

Key input 4 (can also be used to switch on the system (active low))

Key input 3 (can also be used to switch on the system (active low))

Key input 2 (can also be used to switch on the system (active low))

Key input 1 (can also be used to switch on the system (active low))

Indicates RX operation mode

T4

T3

T2

T1

RX_ACTIVE

NC

Not connected

NC

Not connected

GND

Ground/backplane

ATA5428 [DATASHEET]

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Figure 1-3. Block Diagram

AVCC

RX_ACTIVE

DVCC

433_N868

R_PWR

VS2

RF Transceiver

Digital Control Logic

Power

Supply

Frontend Enable

PA_Enable (ASK)

TX_DATA (FSK)

VS1

VAUX

VSOUT

RF_OUT

PWR_H

PA

Switches

Regulators

Wake-up

Reset

RX/TX

Fractional-N

13

FREQ

FREF

PWR_ON

Frequency

RX/TX

Switch

Synthesizer

RX_TX1

RX_TX2

T1

T2

T3

T4

T5

TX/RX - Data Buffer

Control Register

Status Register

Polling Circuit

Signal

Processing

(Mixer

IF Filter

Bit-check Logic

Demod_Out

IF Amplifier

FSK/ASK

Demodulator,

Data Filter

Data Slicer)

LNA

RF_IN

CDEM

RSSI

Reset

XTAL1

XTO

XTAL2

DEM_OUT

CLK

TEST1

TEST2

N_RESET

IRQ

Microcontroller

Interface

CS

SCK

SPI

SDI_TMDI

SDO_TMDO

VSINT

GND

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2.

Application Circuits

2.1

Typical Remote Control Unit Application with 1 Li Battery (3V)

Figure 2-1 shows a typical 433.92MHz Remote Control Unit application with one battery. The external components are

11 capacitors, 1 resistor, 2 inductors and a crystal. C₁to C₄are 68nF voltage supply blocking capacitors. C₅is a 10nF supply

blocking capacitor. C₆is a 15nF fixed capacitor used for the internal quasi-peak detector and for the high-pass frequency of

the data filter. C₇to C₁₁are RF matching capacitors in the range of 1pF to 33pF. L1 is a matching inductor of about 5.6nH to

56nH. L₂is a feed inductor of about 120nH. A load capacitor of 9pF for the crystal is integrated. R₁is typically 22kΩand sets

the output power to about 5.5dBm. The loop antenna’s quality factor is somewhat reduced by this application due to the

quality factor of L₂and the RX/TX switch. On the other hand, this lower quality factor is necessary to have a robust design

with a bandwidth that is broad enough for production tolerances. Due to the single-ended and ground-referenced design, the

loop antenna can be a free-form wire around the application as it is usually employed in remote control uni-directional

systems. The ATA5428 provides sufficient isolation and robust pulling behavior of internal circuits from the supply voltage as

well as an integrated VCO inductor to allow this. Since the efficiency of a loop antenna is proportional to the square of the

surrounded area it is beneficial to have a large loop around the application board with a lower quality factor in order to relax

the tolerance specification of the RF components and to get a high antenna efficiency in spite of their lower quality factor.

Figure 2-1. Typical Remote Control Unit Application, 433.92MHz, 1 Li Battery (3V)

C₁₁

L₁

C₇

C₆

Sensor

CDEM

RSSI

CS

NC

DEM_OUT

NC

RF_IN

NC

SCK

SDI_TMDI

SDO_TMDO

CLK

ATmega

C₅

AVCC

48/88/168

433_N868

NC

ATA5428

R₁

L₂

R_PWR

PWR_H

RF_OUT

IRQ

N_RESET

VCC

VSINT

NC

VSS

NC

C₈

C₉

C₁₀

XTAL2

Loop Antenna

C₁

C₄

13.25311MHz

C₃

C₂

+ Lithium Cell

ATA5428 [DATASHEET]

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2.2

Typical Base-station Application (5V)

Figure 2.2 shows a typical 433.92MHz V_CC= 4.75V to 5.25V Base-station Application (5V). The external components are

12 capacitors, 1 resistor, 4 inductors, a SAW filter, and a crystal. C₁and C₃to C₄are 68nF voltage supply blocking

capacitors. C₂and C₁₂are 2.2µF supply blocking capacitors for the internal voltage regulators. C₅is a 10nF supply blocking

capacitor. C₆is a 15 nF fixed capacitor used for the internal quasi-peak detector and for the high-pass frequency of the data

filter. C₇to C₁₁are RF matching capacitors in the range of 1pF to 33pF. L₂to L₄are matching inductors of about 5.6nH to

56nH. A load capacitor for the crystal of 9pF is integrated. R₁is typically 22kΩ and sets the output power at RF_OUT to

about 10dBm. Since a quarter wave or PCB antenna, which has high efficiency and wide band operation, is typically used

here, it is recommended to use a SAW filter to achieve high sensitivity in case of powerful out-of-band blockers. L₁, C₉and

C₁₀together form a low-pass filter, which is needed to filter out the harmonics in the transmitted signal to meet regulations.

An internally regulated voltage at pin VSOUT can be used in case the microcontroller only supports 3.3V operation, a

blocking capacitor with a value of C₁₂= 2.2µF has to be connected to VSOUT in any case.

Figure 2-2. Typical Base-station Application (5V), 433.92MHz

C₁₁

L₄

L₃

C₇

C₆

SAW-Filter

Sensor

CDEM

RSSI

CS

NC

DEM_OUT

NC

RF_IN

NC

SCK

SDI_TMDI

SDO_TMDO

CLK

ATmega

C₅

AVCC

48/88/168

433_N868

NC

ATA5428

R₁

L₂

R_PWR

PWR_H

RF_OUT

IRQ

N_RESET

VCC

VSINT

NC

VSS

50Ω

Connector

NC

C₈

C₉

L₁

C₁₀

XTAL2

RF_OUT

C₁₂

13.25311MHz

C₃

C₁C₂

C₄

V

= 4.75V to 5.25V

CC

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2.3

Typical Remote Control Unit Application, 2 Li Batteries (6V)

Figure 2-3 shows a typical 433.92Hz 2 Li battery Remote Control Unit application. The external components are

11 capacitors, 1 resistor, 2 inductors and a crystal. C₁and C₄are 68nF voltage supply blocking capacitors. C₂and C₃are

2.2µF supply blocking capacitors for the internal voltage regulators. C₅is a 10nF supply blocking capacitor. C₆is a 15nF

fixed capacitor used for the internal quasi-peak detector and for the high-pass frequency of the data filter. C₇to C₁₁are RF

matching capacitors in the range of 1pF to 33pF. L₁is a matching inductor of about 5.6nH to 56nH. L₂is a feed inductor of

about 120nH. A load capacitor for the crystal of 9pF is integrated. R₁is typically 22kΩ and sets the output power to about

5.5dBm.

Figure 2-3. Typical Remote Control Unit Application, 433.92MHz, 2 Li Batteries (6V)

C₁₁

L₁

C₇

C₆

Sensor

CDEM

RSSI

CS

NC

DEM_OUT

NC

RF_IN

NC

SCK

SDI_TMDI

SDO_TMDO

CLK

ATmega

C₅

AVCC

48/88/168

433_N868

NC

ATA5428

R₁

L₂

R_PWR

PWR_H

RF_OUT

IRQ

N_RESET

VCC

VSINT

NC

VSS

NC

C₈

C₉

C₁₀

XTAL2

Loop Antenna

C₁

C₂

C₄

13.25311MHz

C₃

+ Lithium Cell

ATA5428 [DATASHEET]

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3.

RF Transceiver

As seen in Figure 1-3 on page 6, the RF transceiver consists of an LNA (Low-noise Amplifier), PA (Power Amplifier), RX/TX

switch, fractional-N frequency synthesizer and the signal processing part with mixer, IF filter, IF amplifier with analog RSSI,

FSK/ASK demodulator, data filter, and data slicer.

In receive mode the LNA pre-amplifies the received signal which is converted down to 226kHz (ATA5428), filtered and

amplified before it is fed into an FSK/ASK demodulator, data filter, and data slicer. The RSSI (Received Signal Strength

Indicator) signal and the raw digital output signal of the demodulator are available at the pins RSSI and DEM_OUT. The

demodulated data signal Demod_Out is fed to the digital control logic where it is evaluated and buffered as described in

section “Digital Control Logic” on page 30.

In transmit mode, the fractional-N frequency synthesizer generates the TX frequency which is fed to the PA. In ASK mode

the PA is modulated by the signal PA_Enable. In FSK mode the PA is enabled and the signal TX_DATA (FSK) modulates

the fractional-N frequency synthesizer. The frequency deviation is digitally controlled and internally fixed to about ±16kHz

(see Table 4-1 on page 23 for exact values). The transmit data can also be buffered as described in section “Digital Control

Logic” on page 30. A lock detector within the synthesizer ensures that the transmission will start only if the synthesizer is

locked.

The RX/TX switch can be used to combine the LNA input and the PA output to a single antenna with a minimum of losses.

Transparent modes without buffering of RX and TX data are also available to allow protocols and coding schemes other than

the internally supported Manchester encoding.

3.1

Low-IF Receiver

The receive path consists of a fully integrated low-IF receiver. It fulfills the sensitivity, blocking, selectivity, supply voltage and

supply current specification needed to manufacture, for example, an automotive remote control unit without the use of SAW

blocking filter (see Figure 2-1 on page 7). In a Base-station Application (5V) the receiver can be used with an additional

blocking SAW front-end filter as shown in Figure 2.2 on page 8.

At 433.92MHz the receiver has a typical system noise figure of 7.0dB, a system I1dBCP of -30dBm and a system IIP3 of –

20dBm. There is no AGC or switching of the LNA needed; thus, a better blocking performance is achieved. This receiver

uses an IF (Intermediate Frequency) of 226kHz, the typical image rejection is 30dB and the typical 3dB IF filter bandwidth is

185kHz (f_IF= 226kHz ±92.5kHz, f_{lo_IF}= 133.5kHz and f_{hi_IF}= 318.5kHz). The demodulator needs a signal to Gaussian noise

ratio of 8dB for 20Kbit/s Manchester with ±16kHz frequency deviation in FSK mode; thus, the resulting sensitivity at

433.92MHz is typically –106dBm at 20Kbit/s Manchester.

Due to the low phase noise and spurious emissions of the synthesizer in receive mode⁽¹⁾together with the eighth order

integrated IF filter, the receiver has a better selectivity and blocking performance than more complex double superhet

receivers but without external components and without numerous spurious receiving frequencies.

A low-IF architecture is also less sensitive to second-order intermodulation (IIP2) than direct conversion receivers, where

every pulse or AM-modulated signal (especially the signals from TDMA systems like GSM) demodulates to the receiving

signal band at second-order non-linearities.

Note:

1. –120dBC/Hz at ±1MHz and –75dBC at ±FREF at 433.92MHz

3.2

Input Matching at RF_IN

The measured input impedances as well as the values of a parallel equivalent circuit of these impedances can be seen in the

Table 3-1. The highest sensitivity is achieved with power matching of these impedances to the source impedance of 50Ω.

Table 3-1. Measured Input Impedances of the RF_IN Pin

f_RF/MHz

433.92

868.3

Z(RF_IN)

(32-j169)Ω

(21-j78)Ω

R_p//C_p

925Ω//2.1pF

311Ω//2.2pF

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The matching of the LNA Input to 50Ωwas done with the circuit shown in Figure 3-1 and with the values given in Table 3-2 on

page 11. The reflection coefficients were always ≤ 10dB. Note that value changes of C₁and L₁may be necessary to

compensate for individual board layouts. The measured typical FSK and ASK Manchester code sensitivities with a Bit Error

Rate (BER) of 10^-3are shown in Table 3-3 on page 11 and Table 3-4 on page 11. These measurements were done with

inductors having a quality factor according to Table 3-2 on page 11, resulting in estimated matching losses of 0.7dB at

433.92MHz, 0.7dB at 868.3MHz. These losses can be estimated when calculating the parallel equivalent resistance of the

inductor with R_loss= 2 × π × f × L × Q_Land the matching loss with 10 log(1 + R_p/R_loss).

With an ideal inductor, for example, the sensitivity at 433.92MHz/FSK/20Kbit/s/±16kHz/Manchester can be improved from –

106dBm to –106.7dBm. The sensitivity depends on the control logic which examines the incoming data stream. The

examination limits must be programmed in control registers 5 and 6. The measurements in Table 3-3 on page 11 and Table

3-4 on page 11 are based on the values of registers 5 and 6 according to Table 9-3 on page 53.

Figure 3-1. Input Matching to 50Ω

ATA5428

C

1

4

RF_IN

L

1

Table 3-2. Input Matching to 50Ω

f_RF/MHz

433.92

868.3

C₁/pF

L₁/nH

27

Q_L1

70

1.8

1.2

6.8

50

Table 3-3. Measured Sensitivity FSK, ±16kHz, Manchester, dBm, BER = 10^–3

BR_Range_0

1.0Kbit/s

BR_Range_0

2.4Kbit/s

BR_Range_1

5.0Kbit/s

BR_Range_2

10Kbit/s

BR_Range_3

20Kbit/s

RF Frequency

433.92MHz

868.3MHz

–109.0dBm

–106.0dBm

–109.5dBm

–106.5dBm

–108.0dBm

–105.5dBm

–107.0dBm

–104.0dBm

–106.0dBm

–103.5dBm

Table 3-4. Measured Sensitivity 100% ASK, Manchester, dBm, BER = 10^–3

BR_Range_0

1.0Kbit/s

BR_Range_0

2.4Kbit/s

BR_Range_1

BR_Range_2

10Kbit/s

RF Frequency

433.92MHz

868.3MHz

5.0Kbit/s

–114.0dBm

–111.5dBm

–116.0dBm

–112.5dBm

–116.5dBm

–113.0dBm

–112.5dBm

–109.5dBm

ATA5428 [DATASHEET]

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3.3

Sensitivity versus Supply Voltage, Temperature and Frequency Offset

To calculate the behavior of a transmission system it is important to know the reduction of the sensitivity due to several

influences. The most important are frequency offset due to crystal oscillator (XTO) and crystal frequency (XTAL) errors,

temperature and supply voltage dependency of the noise figure and IF filter bandwidth of the receiver. Figure 3-2 shows the

typical sensitivity at 433.92MHz/FSK/20Kbit/s/±16kHz/Manchester versus the frequency offset between transmitter and

receiver with T_amb= –40°C, +25°C and +105°C and supply voltage VS1 = VS2 = 2.4V, 3.0V and 3.6V.

Figure 3-2. Measured Sensitivity 433.92MHz/FSK/20Kbit/s/±16kHz/Manchester versus Frequency Offset, Tempera-

ture and Supply Voltage

-110

-109

-108

-107

-106

-105

-104

-103

-102

-101

-100

-99

V

= 2.4V T

= 3.0V T

= 3.6V T

= 2.4V T

= 3.0V T

= 3.6V T

= 2.4V T

= 3.0V T

= 3.6V T

= -40°C

= +25°C

= +105°C

S

amb

-98

-97

-96

-95

-100

-80

-60

-40

-20

0

20

40

60

80

100

Frequency Offset (kHz)

As can be seen in Figure 3-2 on page 12 the supply voltage has almost no influence. The temperature has an influence of

about +1.5/–0.7dB, and a frequency offset of ±65kHz also influences by about ±1dB. All these influences, combined with the

sensitivity of a typical IC, are then within a range of –103.7dBm and –107.3dBm over temperature, supply voltage and

frequency offset which is –105.5dBm ±1.8dB. The integrated IF filter has an additional production tolerance of only ±7kHz,

hence, a frequency offset between the receiver and the transmitter of ±58kHz can be accepted for XTAL and XTO

tolerances.

This small sensitivity spread over supply voltage, frequency offset and temperature is very unusual in such a receiver. It is

achieved by an internal, very fast and automatic frequency correction in the FSK demodulator after the IF filter, which leads

to a higher system margin. This frequency correction tracks the input frequency very quickly; if, however, the input frequency

makes a larger step (for example, if the system changes between different communication partners), the receiver has to be

restarted. This can be done by switching back to IDLE mode and then again to RX mode. For that purpose, an automatic

mode is also available. This automatic mode switches to IDLE mode and back into RX mode every time a bit error occurs

(see Section 7. on page 30).

3.4

Frequency Accuracy of the Crystals

The XTO is an amplitude regulated Pierce oscillator with integrated load capacitors. The initial tolerances (due to the

frequency tolerance of the XTAL, the integrated capacitors on XTAL1, XTAL2 and the XTO’s initial transconductance gm)

can be compensated to a value within ±0.5ppm by measuring the CLK output frequency and programming the control

registers 2 and 3 (see Table 7-7 on page 32 and Table 7-10 on page 33). The XTO then has a remaining influence of less

than ±2ppm over temperature and supply voltage due to the band gap controlled gm of the XTO.

The needed frequency stability of the used crystals over temperature and aging is hence

±58kHz/433.92MHz – 2 × ±2.5ppm = ±128.6ppm for 433.92Mz,

±58kHz/868.3MHz – 2 × ±2.5ppm = ±61.8ppm for 868.3MHz.

Thus, the used crystals in receiver and transmitter each need to be better than ±64.3ppm for 433.92MHz, ±30.9ppm for

868.3MHz. In access control systems it may be advantageous to have a more tight tolerance at the Base-station in order to

relax the requirement for the remote control unit.

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3.5

RX Supply Current versus Temperature and Supply Voltage

Table 3-5 shows the typical supply current at 433.92MHz of the transceiver in RX mode versus supply voltage and

temperature with VS = VS1 = VS2. As can be seen, the supply current at 2.4V and –40°C is less than the typical supply

current; this is useful because this is also the operation point where a lithium cell has the worst performance. The typical

supply current at 868.3MHz in RX mode is about the same as for 433.92MHz.

Table 3-5. Measured 433.92 MHz Receive Supply Current in FSK Mode

VS = VS1 = VS2

T_amb= –40°C

T_amb= 25°C

2.4V

8.4mA

9.9mA

10.9mA

3.0V

3.6V

8.8mA

10.3mA

11.3mA

9.2mA

10.8mA

11.8mA

T_amb= 85°C

3.6

Blocking, Selectivity

As can be seen in Figure 3-3 and Figure 3-4 on page 13, the receiver can receive signals 3dB higher than the sensitivity

level in the presence of very large blockers of –47dBm/–34dBm with small frequency offsets of ±1/ ±10MHz.

Figure 3-3 shows narrow band blocking and Figure 3-4 wide band blocking characteristics. The measurements were done

with a signal of 433.92MHz/FSK/20Kbit/s/±16kHz/Manchester, and with a level of –106dBm + 3dB = –103dBm which is 3dB

above the sensitivity level. The figures show how much larger than –103dBm a continuous wave signal can be before the

BER is higher than 10^–3. The measurements were done at the 50Ω input according to Figure 3-1 on page 11. At 1MHz, for

example, the blocker can be 56dB higher than –103dBm which is -103dBm + 56dB = –47dBm. These values, together with

the good intermodulation performance, avoid the need for a SAW filter in the remote control unit application.

Figure 3-3. Narrow Band 3dB Blocking Characteristic at 433.92MHz

70

60

50

40

30

20

10

0

-10

-5

-4

-3

-2

-1

0

1

2

3

4

5

Distance of Interfering to Receiving Signal (MHz)

Figure 3-4. Wide Band 3dB Blocking Characteristic at 433.92MHz

80

70

60

50

40

30

20

10

0

-10

-50

-40

-30

-20

-10

0

10

20

30

40

50

Distance of Interfering to Receiving Signal (MHz)

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Figure 3-5 on page 14 shows the blocking measurement close to the received frequency to illustrate the selectivity and

image rejection. This measurement was done 6dB above the sensitivity level with a useful signal of

433.92MHz/FSK/20Kbit/s/±16kHz/Manchester with a level of –106dBm + 6dB = –100dBm. The figure shows to which extent

a continuous wave signal can surpass –100dBm until the BER is higher than 10^-3. For example, at 1MHz the blocker can

then be 59dB higher than –100dBm which is –100dBm + 59dB = –41dBm.

Table 3-6 on page 14 shows the blocking performance measured relative to –100dBm for some other frequencies. Note that

sometimes the blocking is measured relative to the sensitivity level (dBS) instead of the carrier (dBC).

Table 3-6. Blocking 6dB Above Sensitivity Level with BER < 10^–3

Frequency Offset

+0.75MHz

–0.75MHz

+1.5MHz

Blocker Level

–45dBm

Blocking

55dBC/61dBS

62dBC/68dBS

70dBC/76dBS

–45dBm

–38dBm

–1.5MHz

–38dBm

+10MHz

–30dBm

–10MHz

–30dBm

The ATA5428 can also receive FSK and ASK modulated signals if they are much higher than the I1dBCP. It can typically

receive useful signals at 10dBm. This is often referred to as the nonlinear dynamic range which is the maximum to minimum

receiving signal and is 116dB for 20Kbit/s Manchester. This value is useful if two transceivers have to communicate and are

very close to each other.

Figure 3-5. Close In 6dB Blocking Characteristic and Image Response at 433.92MHz

70

60

50

40

30

20

10

0

-10

-1.0 -0.8 -0.6 -0.4 -0.2

0

0.2

0.4

0.6

0.8

1.0

Distance of Interfering to Receiving Signal (MHz)

This high blocking performance even makes it possible for some applications using quarter wave whip antennas to use a

simple LC band-pass filter instead of a SAW filter in the receiver.

When designing such an LC filter take into account that the 3dB blocking at 433.92MHz/2 = 216.96MHz is 43dBC and at

433.92MHz/3 = 144.64MHz is 48dBC and at 2 × (433.92MHz + 226kHz) + –226kHz = 868.066MHz/868.518MHz is 56dBC.

And especially that at 3 × (433.92MHz + 226kHz) + 226kHz = 1302.664MHz the receiver has its second LO harmonic

receiving frequency with only 12dBC blocking.

3.7

In-band Disturbers, Data Filter, Quasi-peak Detector, Data Slicer

If a disturbing signal falls into the received band or a blocker is not continuous wave, the performance of a receiver strongly

depends on the circuits after the IF filter. The demodulator, data filter and data slicer are important, in that case.

The data filter of the ATA5428 implies a quasi-peak detector. This results in a good suppression of the above mentioned

disturbers and exhibits a good carrier to Gaussian noise performance. The required useful signal to disturbing signal ratio to

be received with a BER of 10^–3is less than 12dB in ASK mode and less than 3dB (BR_Range_0 to BR_Range_2)/6dB

(BR_Range_3) in FSK mode.

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Due to the many different waveforms possible these numbers are measured for signal as well as for disturbers with peak

amplitude values. Note that these values are worst case values and are valid for any type of modulation and modulating

frequency of the disturbing signal as well as the receiving signal. For many combinations, lower carrier to disturbing signal

ratios are needed.

3.8

3.9

DEM_OUT Output

The internal raw output signal of the demodulator Demod_Out is available at pin DEM_OUT. DEM_OUT is an open drain

output and must be connected to a pull-up resistor if it is used (typically 100kΩ) otherwise no signal is present at that pin.

RSSI Output

The output voltage of the pin RSSI is an analog voltage, proportional to the input power level. Using the RSSI output signal,

the signal strength of different transmitters can be distinguished. The usable dynamic range of the RSSI amplifier is 70dB,

the input power range P(RF_IN) is –115dBm to –45dBm and the gain is 8mV/dB. Figure 3-6 shows the RSSI characteristic of

a typical device at 433.92MHz with VS1 = VS2 = 2.4V to 3.6V and T_amb= –40°C to +85°C with a matched input according to

Table 3-2 on page 11 and Figure 3-1 on page 11. At 868.3MHz about 2.7dB more signal level is needed for the same RSSI

results.

Figure 3-6. Typical RSSI Characteristic versus Temperature and Supply Voltage

1100

1000

900

800

max.

700

typ.

min.

600

500

400

-120

-110

-100

-90

-80

-70

-60

-50

-40

P_{RF_IN}(dBm)

3.10 Frequency Synthesizer

The synthesizer is a fully integrated fractional-N design with internal loop filters for receive and transmit mode. The XTO

frequency f_XTOis the reference frequency FREF for the synthesizer. The bits FR0 to FR12 in control registers 2 and 3 (see

Table 7-7 on page 32 and Table 7-10 on page 33) are used to adjust the deviation of f_XTO. In transmit mode, at 433.92MHz,

the carrier has a phase noise of –111dBC/Hz at 1MHz and spurious emissions at FREF of –66dBC with a high PLL loop

bandwidth allowing the direct modulation of the carrier with 20Kbit/s Manchester data. Due to the closed loop modulation any

spurious emissions caused by this modulation are effectively filtered out as can be seen in Figure 3-9 on page 17. In RX

mode the synthesizer has a phase noise of –120dBC/Hz at 1MHz and spurious emissions of –75dBC.

The initial tolerances of the crystal oscillator due to crystal tolerances, internal capacitor tolerances and the parasitics of the

board have to be compensated at manufacturing setup with control registers 2 and 3 as can be seen in Table 4-1 on page

23. The other control words for the synthesizer needed for ASK, FSK and receive/transmit switching are calculated

internally. The RF (Radio Frequency) resolution is equal to the XTO frequency divided by 16384 which is 808.9Hz at

433.92MHz, 818.6Hz at 868.3MHz.

For the multi-channel system the frequency control word FREQ in control registers 2 and 3 can be programmed in the range

of 1000 to 6900, this is equivalent to a programmable tuning range of ±2.5MHz hence every frequency within the 433MHz,

868MHz ISM bands can be programmed as receive and as transmit frequency, and the position of channels within these

ISM bands can be chosen arbitrarily (see Table 4-1 on page 23).

Care must be taken as to the harmonics of the CLK output signal as well as to the harmonics produced by a microprocessor

clocked with it, since these harmonics can disturb the reception of signals. In a single-channel system, using FREQ = 3803

to 4053 ensures that harmonics of this signal do not disturb the receive mode.

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3.11 FSK/ASK Transmission

Due to the fast modulation capability of the synthesizer and the high resolution, the carrier can be internally FSK modulated,

which simplifies the application of the transceiver. The deviation of the transmitted signal is ±20 digital frequency steps of the

synthesizer which is equal to ±16.17kHz for 433.92MHz, ±16.37kHz for 868.3MHz.

Due to closed loop modulation with PLL filtering the modulated spectrum is very clean, meeting ETSI and CEPT regulations

when using a simple LC filter for the power amplifier harmonics as it is shown in Figure 2.2 on page 8. In ASK mode the

frequency is internally connected to the center of the FSK transmission and the power amplifier is switched on and off to

perform the modulation. Figure 3-7 to Figure 3-9 on page 17 show the spectrum of the FSK modulation with pseudo-random

data with 20Kbit/s/±16.17kHz/Manchester and 5dBm output power.

Figure 3-7. FSK-modulated TX Spectrum (433.92MHz/20Kbit/s/±16.17kHz/Manchester Code)

Atten 20dB

Ref 10dB

Samp

Log

10

dB/

VAvg

50

W1 S2

S3 FC

Center 433.92MHz

Res BW 100kHz

Span 30MHz

Sweep 7.5ms (401 pts)

VBW 100kHz

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Figure 3-8. Unmodulated TX Spectrum 433.92MHz – 16.17kHz (f_{FSK_L}

)

Atten 20dB

Ref 10dB

Samp

Log

10

dB/

VAvg

50

W1 S2

S3 FC

Center 433.92MHz

Span 1MHz

Res BW 10kHz

VBW 10kHz

Sweep 27.5ms (401 pts)

Figure 3-9. FSK-modulated TX Spectrum (433.92MHz/20Kbit/s/±16.17kHz/Manchester Code)

Atten 20dB

Ref 10dB

Samp

Log

10

dB/

VAvg

50

W1 S2

S3 FC

Center 433.92MHz

Res BW 10kHz

Span 1MHz

Sweep 27.5ms (401 pts)

VBW 10kHz

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3.12 Output Power Setting and PA Matching at RF_OUT

The Power Amplifier (PA) is a single-ended open collector stage which delivers a current pulse which is nearly independent

of supply voltage, temperature and tolerances due to band gap stabilization. Resistor R₁, see Figure 3-10, sets a reference

current which controls the current in the PA. A higher resistor value results in a lower reference current, a lower output power

and a lower current consumption of the PA. The usable range of R₁is 15kΩto 56kΩ. Pin PWR_H switches the output power

range between about 0dBm to 5dBm (PWR_H = GND) and 5dBm to 10dBm (PWR_H = AVCC) by multiplying this reference

current by a factor 1 (PWR_H = GND) and 2.5 (PWR_H = AVCC), which corresponds to about 5dB more output power.

If the PA is switched off in TX mode, the current consumption without output stage with VS1 = VS2 = 3V, T_amb= 25°C is

typically 6.5mA for 868.3MHz and 6.95mA for 433.92MHz.

The maximum output power is achieved with optimum load resistances R_Loptaccording to Table 3-7 on page 19 with

compensation of the 1.0pF output capacitance of the RF_OUT pin by absorbing it into the matching network consisting of L₁,

C₁, C₃as shown in Figure 3-10 on page 18. There must also be a low resistive DC path to AVCC to deliver the DC current of

the power amplifier's last stage. The matching of the PA output was done with the circuit shown in Figure 3-10 on page 18

with the values in Table 3-7 on page 19. Note that value changes of these elements may be necessary to compensate for

individual board layouts.

Example:

According to Table 3-7 on page 19, with a frequency of 433.92 MHz and output power of 11dBm the overall current

consumption is typically 17.8mA; hence, the PA needs 17.8mA - 6.95mA = 10.85mA in this mode, which corresponds to an

overall power amplifier efficiency of the PA of (10^(11dBm/10)× 1 mW)/(3V × 10.85mA) × 100% = 38.6% in this case.

Using a higher resistor in this example of R₁= 1.091 × 22kΩ = 24kΩresults in 9.1% less current in the PA of 10.85mA/1.091

= 9.95mA and 10 × log(1.091) = 0.38dB less output power if using a new load resistance of 300Ω × 1.091 = 327Ω. The

resulting output power is then 11dBm – 0.38dB = 10.6dBm and the overall current consumption is

6.95mA + 9.95mA = 16.9mA.

The values of Table 3-7 on page 19 were measured with standard multi-layer chip inductors with quality factors Q according

to Table 3-7 on page 19. Looking to the 433.92MHz/11dBm case with the quality factor of Q_L1= 43 the loss in this inductor is

estimated with the parallel equivalent resistance of the inductor R_loss= 2 × π × f × L × Q_L1and the matching loss with

10 log (1 + R_Lopt/R_loss) which is equal to 0.32dB losses in this inductor. Taking this into account, the PA efficiency is then

42% instead of 38.6%.

Be aware that the high power mode (PWR_H = AVCC) can only be used with a supply voltage higher than 2.7V, whereas

the low power mode (PWR_H = GND) can be used down to 2.4V as can be seen in the “Electrical Characteristics: General”

on page 58.

The supply blocking capacitor C₂(10nF) has to be placed close to the matching network because of the RF current flowing

through it.

Figure 3-10. Power Setting and Output Matching

AVCC

C₂

L₁

ATA5428

RF_OUT

C₁

10

RF_OUT

C₃

8

R_PWR

PWR_H

R₁

9

VPWR_H

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Table 3-7. Measured Output Power and Current Consumption with VS1 = VS2 = 3V, T_amb= 25°C

Frequency

(MHz)

TX Current

(mA)

Output Power

(dBm)

R1

(kΩ)

L1

(nH)

C1

(pF)

C3

(pF)

VPWR_H

GND

R_Lopt(Ω)

2300

890

Q_L1

40

38

43

58

54

57

433.92

868.3

8.6

11.2

17.8

9.3

0.1

6.2

11

56

22

33

15

22

56

47

33

12

15

10

0.75

1.5

2.7

1.0

1.5

0

GND

AVCC

GND

300

0

-0.3

5.4

9.5

1170

471

3.3

0

868.3

11.5

16.3

GND

868.3

AVCC

245

0

3.13 Output Power and TX Supply Current versus Supply Voltage and Temperature

Table 3-8 shows the measurement of the output power for a typical device with VS = VS1 = VS2 in the 433.92MHz and

6.2dBm case versus temperature and supply voltage measured according to Figure 3-10 on page 18 with components

according to Table 3-7. As opposed to the receiver sensitivity, the supply voltage has here the major impact on output power

variations because of the large signal behavior of a power amplifier. Thus, a two battery system with voltage regulator or a

5V system shows much less variation than a 2.4V to 3.6V one battery system because the supply voltage is then well within

3.0V and 3.6V.

The reason is that the amplitude at the output RF_OUT with optimum load resistance is AVCC – 0.4V and the power is

proportional to (AVCC – 0.4V)²if the load impedance is not changed. This means that the theoretical output power reduction

if reducing the supply voltage from 3.0V to 2.4V is 10 log ((3V – 0.4V)²/(2.4V – 0.4V)²) = 2.2dB. Table 3-8 shows that

principle behavior in the measurement. This is not the same case for higher voltages, since here increasing the supply

voltage from 3V to 3.6V should theoretical increase the power by 1.8dB; but a gain of only 0.8dB in the measurement shows

that the amplitude does not increase with the supply voltage because the load impedance is optimized for 3V and the output

amplitude stays more constant.

Table 3-8.

Measured Output Power and Supply Current at 433.92MHz, PWR_H = GND

VS =

2.4V

3.0V

3.6V

10.19mA

3.8dBm

10.19mA

5.5dBm

10.78mA

6.2dBm

T_amb= –40°C

T_amb= +25°C

T_amb= +85°C

10.62mA

4.6dBm

11.19mA

6.2dBm

11.79mA

7.1dBm

11.4mA

3.9dBm

12.02mA

5.5dBm

12.73mA

6.6dBm

Table 3-9 shows the relative changes of the output power of a typical device compared to 3.0V/25°C. As can be seen, a

temperature change to –40°C as well as to +85°C reduces the power by less than 1dB due to the band gap regulated output

current. Measurements of all the cases in Table 3-7 on page 19 over temperature and supply voltage have shown about the

same relative behavior as shown in Table 3-9.

Table 3-9. Measurements of Typical Output Power Relative to 3V/25°C

VS =

2.4V

3.0V

–0.7dB

0dB

3.6V

0dB

T_amb= –40°C

T_amb= +25°C

T_amb= +85°C

–2.4dB

–1.6dB

–2.3dB

+0.9dB

+0.4dB

–0.7dB

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3.14 RX/TX Switch

The RX/TX switch decouples the LNA from the PA in TX mode, and directs the received power to the LNA in RX mode. To

do this, it has a low impedance to GND in TX mode and a high impedance to GND in RX mode. To design a proper RX/TX

decoupling, a linear simulation tool for radio frequency design together with the measured device impedances of Table 3-1

on page 10, Table 3-7 on page 19, Table 3-10 and Table 3-11 on page 21 should be used, but the exact element values have

to be found on-board. Figure 3-11 shows an approximate equivalent circuit of the switch. The principal switching operation is

described here according to the application of Figure 2-1 on page 7. The application of Figure 2.2 on page 8 works similarly.

Table 3-10. Impedance of the RX/TX Switch RX_TX2 Shorted to GND

Frequency

433.92MHz

868.3MHz

Z(RX_TX1) TX Mode

(4.5 + j4.3)Ω

Z(RX_TX1) RX Mode

(10.3 – j153)Ω

(5 + j9)Ω

(8.9 – j73)Ω

Figure 3-11. Equivalent Circuit of the Switch

RX_TX1

1.6nH

2.5pF

TX

11Ω

5Ω

3.15 Matching Network in TX Mode

In TX mode the 20mm long and 0.4mm wide transmission line which is much shorter than λ/4 is approximately switched in

parallel to the capacitor C₉to GND. The antenna connection between C₈and C₉has an impedance of about 50Ω locking

from the transmission line into the loop antenna with pin RF_OUT, L₂, C₁₀, C₈and C₉connected (using a C₉without the

added 7.6pF as discussed later). The transmission line can be approximated with a 16nH inductor in series with a 1.5Ω

resistor, the closed switch can be approximated according to Table 3-10 with the series connection of 1.6nH and 5Ω in this

mode. To have a parallel resonant high impedance circuit with little RF power going into it looking from the loop antenna into

the transmission line a capacitor of about 7.6pF to GND is needed at the beginning of the transmission line (this capacitor is

later absorbed into C₉which is then higher, as needed for 50Ω transformation). To keep the 50Ω impedance in RX mode at

the end of this transmission line, C₇also has to be about 7.6pF. This reduces the TX power by about 0.5dB at 433.92MHz

compared to the case the where the LNA path is completely disconnected.

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3.16 Matching Network in RX Mode

In RX mode the RF_OUT pin has a high impedance of about 7kΩ in parallel with 1.0pF at 433.92MHz as can be seen in

Table 3-11. This, together with the losses of the inductor L₂with 120nH and Q_L2= 25, gives about 3.7kΩ loss impedance at

RF_OUT. Since the optimum load impedance in TX mode for the power amplifier at RF_OUT is 890Ω the loss associated

with the inductor L₂and the RF_OUT pin can be estimated to be 10 × log(1 + 890/3700) = 0.95dB compared to the optimum

matched loop antenna without L₂and RF_OUT. The switch represents, in this mode at 433.92MHz, approximately an

inductor of 1.6nH in series with the parallel connection of 2.5pF and 2.0kΩ. Since the impedance level at pin RX_TX1 in RX

mode is about 50Ω this only negligibly dampens the received signal (by about 0.1dB). When matching the LNA to the loop

antenna, the transmission line and the 7.6pF part of C₉have to be taken into account when choosing the values of C₁₁and

L₁so that the impedance seen from the loop antenna into the transmission line with the 7.6pF capacitor connected is 50Ω.

Since the loop antenna in RX mode is loaded by the LNA input impedance, the loaded Q of the loop antenna is lowered by

about a factor of 2 in RX mode; hence the antenna bandwidth is higher than in TX mode.

Table 3-11. Impedance RF_OUT Pin in RX Mode

Frequency

433.92MHz

868.3MHz

Z(RF_OUT)RX

19Ω – j 366Ω

2.8Ω – j 141Ω

R_P//C_P

7kΩ//1.0pF

7kΩ//1.3pF

Note that if matching to 50Ω, like in Figure 2.2 on page 8, a high Q wire-wound inductor with a Q > 70 should be used for L₂

to minimize its contribution to RX losses that will otherwise be dominant. The RX and TX losses will be in the range of 1.0dB

there.

4.

XTO

The XTO is an amplitude-regulated Pierce oscillator type with integrated load capacitances (2 × 18pF with a tolerance of

±17%) hence C_Lmin= 7.4pF and C_Lmax= 10.6pF. The XTO oscillation frequency f_XTOis the reference frequency FREF for the

fractional-N synthesizer. When designing the system in terms of receiving and transmitting frequency offset, the accuracy of

the crystal and XTO have to be considered.

The synthesizer can adjust the local oscillator frequency for the initial frequency error in f_XTO. This is done at nominal supply

voltage and temperature with the control registers 2 and 3 (see Table 7-7 on page 32 and Table 7-10 on page 33). The

remaining local oscillator tolerance at nominal supply voltage and temperature is then < ±0.5ppm. The XTO’s gm has very

low influence of less than ±2ppm on the frequency at nominal supply voltage and temperature.

In a single channel system less than ±150ppm should be corrected to avoid that harmonics of the CLK output disturb the

receive mode. If the CLK is not used or if it is carefully laid out on the application PCB (as needed for multi channel systems),

more than ±150ppm can be compensated.

Over temperature and supply voltage, the XTO's additional pulling is only ±2ppm. The XTAL versus temperature and its

aging is then the main source of frequency error in the local oscillator.

The XTO frequency depends on XTAL properties and the load capacitances C_{L1, 2}at pin XTAL1 and XTAL2. The pulling of

f

_XTOfrom the nominal f_XTALis calculated using the following formula:

C_m

------- -----------------------------------------------------------

× 10 ppm.

C

_LN– C_L

6

P =

×

2

(C₀+ C_LN) × (C₀+ C_L)

C_mis the crystal's motional, C₀the shunt and C_LNthe nominal load capacitance of the XTAL found in its data sheet. C_Lis the

total actual load capacitance of the crystal in the circuit and consists of C_L1and C_L2in series connection.

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Figure 4-1. XTAL with Load Capacitance

Crystal equivalent circuit

C₀

XTAL

L_m

R_m

C_m

C_L1

C_L2

C_L= C_L1x C_L2/ (C_L1+ C_L2

)

With C_m≤ 14fF, C₀≥ 1.5pF, C_LN= 9pF and C_L= 7.4pF to 10.6pF, the pulling amounts to P ≤ ±100ppm and with C_m≤ 7fF,

C₀≥ 1.5pF, C_LN= 9pF and C_L= 7.4pF to 10.6pF, the pulling is P ≤ ±50ppm.

Since typical crystals have less than ±50ppm tolerance at 25°C, the compensation is not critical, and can in both cases be

done with the ±150ppm.

C₀of the XTAL has to be lower than C_Lmin/2 = 3.7pF for a Pierce oscillator type in order to not enter the steep region of

pulling versus load capacitance where there is a risk of an unstable oscillation.

To ensure proper start-up behavior the small signal gain, and thus the negative resistance, provided by this XTO at start is

very large; for example, oscillation starts up even in worst case with a crystal series resistance of 1.5kΩat C₀≤2.2pF with this

XTO. The negative resistance is approximately given by

Z₁× Z₃+ Z₂× Z₃+ Z₁× Z₂× Z₃× g_m

---------------------------------------------------------------------------------------------------

Re{Z_XTOcore} = Re

Z₁+ Z₂+ Z₃+ Z₁× Z₂× g_m

with Z₁, Z₂as complex impedances at pin XTAL1 and XTAL2, hence

Z₁= –j/(2 × π × f_XTO× C_L1) + 5Ωand Z₂= –j/(2 × π × f_XTO× C_L2) + 5Ω.

Z₃consists of crystals C₀in parallel with an internal 110 kΩ resistor hence

Z₃= –j/(2 × π × f_XTO× C₀) /110kΩ, gm is the internal transconductance between XTAL1 and XTAL2 with typically 19mS at

25°C.

With f_XTO= 13.5MHz, gm = 19mS, C_L= 9pF, and C₀= 2.2pF, this results in a negative resistance of about 2kΩ. The worst

case for technological, temperature and supply voltage variations is then for C₀≤ 2.2pF always higher than 1.5kΩ.

Due to the large gain at startup, the XTO is able to meet a very low start-up time. The oscillation start-up time can be

estimated with the time constant τ .

2

τ = -------------------------------------------------------------------------------------------------------

4 × π²× f_m²× C_m× (Re(Z_XTOcore) + R_m)

After 10τ to 20τ an amplitude detector detects the oscillation amplitude and sets XTO_OK to High if the amplitude is large

enough. This sets N_RESET to High and activates the CLK output if CLK_ON in control register 3 is High (see Table 7-7 on

page 32). Note that the necessary conditions of the VSOUT and DVCC voltage also have to be fulfilled (see Figure 4-2 on

page 23 and Figure 5-1 on page 25).

To save current in IDLE and Sleep modes, the load capacitors are partially switched off in these modes with S1 and S2, as

seen in Figure 4-2 on page 23.

It is recommended to use a crystal with C_m= 3.0fF to 7.0fF, C_LN= 9pF, R_m< 120Ωand C₀= 1.0pF to 2.2pF.

Lower values of C_mcan be used, this increases the start-up time slightly. Lower values of C₀or higher values of C_m(up to

15fF) can also be used, this has only little influence on pulling.

22

ATA5428 [DATASHEET]

4841G–WIRE–03/14

Figure 4-2. XTO Block Diagram

XTAL1

XTAL2

CLK

&

f_XTO

DVCC_OK

(from power supply)

Divider

/3

CLK_ON

VSOUT_OK

(from power supply)

(control

register 3)

8pF

S1

10pF

8pF

S2

Amplitude

detector

C_L1

C_L2

XTO_OK

(to reset logic)

Divider

/16

f_DCLK

In IDLE mode and during Sleep mode (RX_Polling)

the switches S1 and S2 are open.

Divider

/1

/2

f_XDCLK

/4

/8

/16

Baud1

Baud0

XLim

To find the right values used in control registers 2 and 3 (see Table 7-7 on page 32 and Table 7-10 on page 33), the

relationship between f_XTOand the f_RFis shown in Table 4-1 on page 23. To determine the right content, the frequency at pin

CLK as well as the output frequency at RF_OUT in ASK mode can be measured, then the FREQ value can be calculated

according to Table 4-1 on page 23 so that f_RFis exactly the desired radio frequency.

Table 4-1. Calculation of f_RF

CREG1

Bit(4)

FS

Frequency

(MHz)

Pin 6

433_N868

Frequency

Resolution

f_XTO(MHz)

f_RF= f_{TX_ASK}= f_RX

f_{TX_FSK_L}

f_{TX_FSK_H}

f_RF

16.17kHz

–

f_RF

16.17kHz

+

FREQ + 20.5

433.92

868.3

AVCC

GND

0

13.25311

f_XTO

×

32.5 + -------------------------------

808.9Hz

818.6Hz

16384

f_RF

16.37kHz

–

f_RF

16.37kHz

+

FREQ + 20.5

13.41191

f_XTO

64.5 + -------------------------------

16384

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4841G–WIRE–03/14

The variable FREQ depends on FREQ2 and FREQ3, which are defined by the bits FR0 to FR12 in control register 2 and 3,

and is calculated as follows:

FREQ = FREQ2 + FREQ3

Care must be taken to the harmonics of the CLK output signal f_CLKas well as to the harmonics produced by an

microprocessor clocked with it, since these harmonics can disturb the reception of signals if they get to the RF input. In a

single channel system, using FREQ = 3803 to 4053 ensures that the harmonics of this signal do not disturb the receive

mode. In a multichannel system, the CLK signal can either be not used or carefully laid out on the application PCB. The

supply voltage of the microcontroller must also be carefully blocked in a multichannel system.

4.1

Pin CLK

Pin CLK is an output to clock a connected microcontroller. The clock frequency f_CLKis calculated as follows:

f_XTO

f_CLK= -----------

3

Because the enabling of pin CLK is asynchronous, the first clock cycle may be incomplete. The signal at CLK output has a

nominal 50% duty cycle.

Figure 4-3. Clock Timing

V

_{Thres_2}= 2.38V (typically)

V_{Thres_1}= 2.3V (typically)

VSOUT

CLK

N_RESET

CLK_ON

(Control register 3)

4.2

Basic Clock Cycle of the Digital Circuitry

The complete timing of the digital circuitry is derived from one clock. As shown in Figure 4-2 on page 23, this clock cycle

T

_DCLKis derived from the crystal oscillator (XTO) in combination with a divider.

f_XTO

f_DCLK= -----------

16

T_DCLKcontrols the following application relevant parameters:

●

Timing of the polling circuit including bit check

TX bit rate

The clock cycle of the bit check and the TX bit rate depends on the selected bit-rate range (BR_Range) which is defined in

control register 6 (see Table 7-20 on page 35) and XLim which is defined in control register 4 (see Table 7-13 on page 33).

This clock cycle T_XDCLKis defined by the following formulas for further reference:

BR_Range

BR_Range 0: T_XDCLK= 8 × T_DCLK× X_Lim

BR_Range 1: T_XDCLK= 4 × T_DCLK× X_Lim

BR_Range 2: T_XDCLK= 2 × T_DCLK× X_Lim

BR_Range 3: T_XDCLK= 1 × T_DCLK× X_Lim

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5.

Power Supply

Figure 5-1. Power Supply

VS1

SW_AVCC

IN

OUT

V_REG1

3.25V typ.

VS2

AVCC

VSINT

EN

(Control register 1)

AVCC_EN

PWR_ON

≥ 1

FF1

T1

to

T5

S

R

Q

SW_VSOUT

DVCC

DVCC_OK

OFFCMD

(Command via SPI)

≥ 1

S

0

1

R

0

1

0

1

Q

no change

SW_DVCC

0

1

DVCC_OK

(to XTO and

Reset Logic)

V_Monitor

(1.5V typ.)

and

VS1+

0.55V

typ.

VSOUT_OK

(to XTO and

Reset Logic)

-

+

P_On_Aux

(Status register)

V_Monitor

(2.3V/

2.38V typ.)

Low_Batt

(Status Register

and Reset Logic)

IN

OUT

V_REG2

3.25V typ.

VAUX

VSOUT

EN

VSOUT_EN

(Control register 3)

The supply voltage range of the ATA5428 is 2.4V to 3.6V or 4.4V to 6.6V.

Pin VS1 is the supply voltage input for the range 2.4V to 3.6V and is used in 1 Li battery applications (3V) using a single

lithium 3V cell. Pin VS2 is the voltage input for the range 4.4V to 6.6V (2 Li battery application (6V) and Base-station

Application (5V); in this case, the voltage regulator V_REG1 regulates VS1 to typically 3.25V. If the voltage regulator is

active, a blocking capacitor of 2.2µF has to be connected to VS1.

Pin VAUX is an input for an additional auxiliary voltage supply and can be connected, for example, to an inductive supply

(see Figure 5-6 on page 29). This input can only be used together with a rectifier or as in the application shown in Figure 2.2

on page 8 and must otherwise be left open.

Pin VSINT is the voltage input for the Microcontoller_Interface and must be connected to the power supply of the

microcontroller. The voltage range of V_VSINTis 2.4V to 5.25V (see Figure 5-5 on page 29 and Figure 5-6 on page 29).

AVCC is the internal operation voltage of the RF transceiver and is fed by VS1 via the switch SW_AVCC. AVCC must be

blocked with a 68nF capacitor (see Figure 2-1 on page 7, Figure 2.2 on page 8 and Figure 2-3 on page 9).

DVCC is the internal operation voltage of the digital control logic and is fed by VS1 or VSOUT via the switch SW_DVCC.

DVCC must be blocked on pin DVCC with 68 nF (see Figure 2-1 on page 7, Figure 2.2 on page 8 and Figure 2-3 on page 9).

Pin VSOUT is a power supply output voltage for external devices (for example, microcontrollers) and is fed by VS1 via the

switch SW_VSOUT, or by the auxiliary voltage supply VAUX via V_REG2. The voltage regulator V_REG2 regulates VSOUT

to typically 3.25V. If the voltage regulator is active, a blocking capacitor of 2.2µF has to be connected to VSOUT. VSOUT

can be switched off by the VSOUT_EN bit in control register 3 and is then reactivated by conditions found in Figure 5-2 on

page 26.

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Pin N_RESET is set to low if the voltage V_VSOUTat pin VSOUT drops below 2.3V (typically) and can be used as a reset signal

for a connected microcontroller (see Figure 5-3 on page 28 and Figure 5-4 on page 28).

Pin PWR_ON is an input to switch on the transceiver (active high).

Pin T1 to T5 are inputs for push buttons and can also be used to switch on the transceiver (active low).

For current consumption reasons it is recommended to set T1 to T5 to GND, or PWR_ON to VCC only temporarily.

Otherwise, an additional current flows because of a 50kΩ pull-up resistor.

There are two voltage monitors generating the following signals (see Figure 5-1 on page 25):

●

DVCC_OK if DVCC > 1.5V typically

VSOUT_OK if VSOUT > V_Thres1(2.3V typically)

Low_Batt if VSOUT < V_Thres2(2.38V typically)

Figure 5-2. Operation Modes Flow Chart

Bit AVCC_EN = 0 and OFF Command and

Pin PWR_ON = 0 and

OFF Mode

V_VAUX< 3.5V (typ)

Pin T1, T2, T3, T4 and T5 = 1

AVCC = OFF

DVCC = OFF

VSOUT = OFF

Pin PWR_ON = 1 or

Pin T1, T2, T3, T4 or

Pin T5

V_VAUX> 3.5V (typ)

Pin PWR_ON = 1 or

Pin T1, T2, T3, T4 or

Pin T5 or

V_VAUX< VS1 + 0.5V

Bit AVCC_EN = 1

IDLE Mode

AUX Mode

AVCC = VS1

DVCC = VS1

VSOUT = VS1

AVCC = VS1

DVCC = VS1

VSOUT = V_REG2

AVCC = OFF

DVCC = V_REG2

VSOUT = V_REG2

V_VAUX> VS1 + 0.5V

Bit AVCC_EN = 0 and

OFF Command and

Pin PWR_ON = 0 and

Pin T1, T2, T3, T4 and

T5 = 1

OPM1 OPM0

0

1

0

1

TX Mode

RX Polling Mode

RX Mode

VSOUT_EN = 0

IDLE Mode

AVCC = VS1

DVCC = VS1

VSOUT = OFF

Statusbit Power_On = 1

or

Event on Pin T1, T2, T3, T4 or T5

OPM1 = 0 and OPM0 = 1

TX Mode

RX Polling Mode

RX Mode

OPM1 = 0 and OPM0 = 1

OPM1 = 1 and OPM0 = 0

AVCC = VS1

DVCC = VS1

VSOUT = VS1

or V_REG2

AVCC = VS1

DVCC = VS1

VSOUT = VS1

or V_REG2

AVCC = VS1

DVCC = VS1

VSOUT = VS1

or V_REG2

OPM1 = 1 and OPM0 = 0

OPM1 = 1 and OPM0 = 1

or Bit check ok

OPM1 = 1 and OPM0 = 1

Status bit Power_On = 1

or

Event on Pin T1, T2, T3, T4 or T5

VSOUT_EN = 0

RX Polling Mode

Bit check ok

AVCC = VS1

DVCC = VS1

VSOUT = OFF

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5.1

5.2

OFF Mode

If the power supply (battery) is connected to pin VS1 and/or VS2, and if the voltage on pin VAUX V_VAUX< 3.5V (typically),

then the transceiver is in OFF mode. In OFF mode AVCC, DVCC and VSOUT are disabled, resulting in very low power

consumption (I_{S_OFF}is typically 10nA). In OFF mode the transceiver is not programmable via the 4-wire serial interface.

AUX Mode

The transceiver changes from OFF mode to AUX mode if the voltage at pin VAUX V_VAUX> 3.5V (typically). In AUX mode

DVCC and VSOUT are connected to the auxiliary power supply input (VAUX) via the voltage regulator V_REG2. In AUX

mode the transceiver is programmable via the 4-wire serial interface, but no RX or TX operations are possible because

AVCC = OFF.

The state transition OFF mode to AUX mode is indicated by an interrupt at pin IRQ and the status bit P_On_Aux = 1.

5.3

IDLE Mode

In IDLE mode AVCC and DVCC are connected to the battery voltage (VS1).

From OFF mode the transceiver changes to IDLE mode if pin PWR_ON is set to 1 or pin T1, T2, T3, T4 or T5 is set to “0”.

This state transition is indicated by an interrupt at pin IRQ and the status bits Power_On = 1 or ST1, ST2, ST3, ST4 or ST5 =

1.

From AUX mode the transceiver changes to IDLE mode by setting AVCC_EN = 1 in control register 1 via the 4-wire serial

interface or if pin PWR_ON is set to “1” or pin T1, T2, T3, T4 or T5 is set to “0”.

VSOUT is either connected to VS1 or to the auxiliary power supply (V_REG2).

If V_VAUX< VS1 + 0.5V, VSOUT is connected to VS1. If V_VAUX> V_S1+ 0.5V, VSOUT is connected to V_REG2 and the status

bit P_On_Aux is set to “1”.

In IDLE mode, the RF transceiver is disabled and the power consumption I_{S_IDLE}is about 230 µA (VSOUT OFF and CLK

output OFF and VS = VS1 = VS2 = 3V). The exact value of this current is strongly dependent on the application and the

exact operation mode, therefore check the section “Electrical Characteristics: General” on page 58 for the appropriate

application case.

Via the 4-wire serial interface a connected microcontroller can program the required parameter and enable the TX, RX

polling or RX mode.

The transceiver can be set back to OFF mode by an OFF command via the 4-wire serial interface (the bit AVCC_EN must be

set to “0”, the input level of pin PWR_ON must be “0” and pin T1, T2, T3, T4 and T5 = 1 before writing the OFF command).

Table 5-1. Control Register 1

OPM1

OPM0

Function

0

IDLE mode

5.4

Reset Timing and Reset Logic

If the transceiver is switched on (OFF mode to IDLE mode, OFF mode to AUX mode) DVCC and VSOUT ramp up as

illustrated in Figure 5-3 on page 28 (AVCC only ramps up if the transceiver is set to the IDLE mode). The internal signal

DVCC_RESET resets the digital control logic and sets the control register to default values.

A voltage monitor generates a low level at pin N_RESET until the voltage at pin VSOUT exceeds 2.38V (typically) and the

start-up time of the XTO has elapsed (amplitude detector, see Figure 4-2 on page 23). After the voltage at pin VSOUT

exceeds 2.3V (typically) and the start-up time of the XTO has elapsed, the output clock at pin CLK is available. Because the

enabling of pin CLK is asynchronous, the first clock cycle may be incomplete.

The status bit Low_Batt is set to “1” if the voltage at pin VSOUT V_VSOUTdrops below V_{Thres_2}(typically 2.38V). Low_Batt is

set to “0” if V_VSOUTexceeds V_{Thres_2}and the status register is read via the 4-wire serial interface or N_RESET is set to low.

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If V_VSOUTdrops below V_{Thres_1}(typically 2.3V), N_RESET is set to low. If bit VSOUT_EN in control register 3 is “1”, a

DVCC_RESET is also generated. If V_VSOUTwas already disabled by the connected microcontroller by setting bit

VSOUT_EN = 0, no DVCC_RESET is generated.

Note:

If VSOUT < V_{Thres_1}(typically 2.3 V) the output of the pin CLK is low, the Microcontroller_Interface is disabled

and the transceiver is not programmable via the 4-wire serial interface.

Figure 5-3. Reset Timing

V

_{Thres_2}= 2.38V (typ)

V

_{Thres_1}= 2.3V (typ)

VSOUT

1.5V (typically)

DVCC

(AVCC)

DVCC_RESET

N_RESET

V_SOUT> 2.38V and the XTO is running

LOW_Batt

(Status Register)

VSOUT_EN

(Control Register 3)

V_SOUT> 2.3V and the XTO is running

VSOUT

Figure 5-4. Reset Logic, SR Latch Generates the Hysteresis in the NRESET Signal

DVCC_OK

and

DVCC_RESET

N_RESET

XTO_OK

≥ 1

VSOUT_EN

and

S

R

Q

VSOUT_OK

LOW_BATT

S

R

Q

0

1

0

1

0

1

no change

0

1

no change

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5.5

1 Li Battery Application (3V)

The supply voltage range is 2.4V to 3.6V and VAUX is not used.

Figure 5-5. 1 Li Battery Application (3V)

ATA5428

ATmega

48/88/168

VS1

2.4V to 3.6V

VS2

VAUX

RF Transceiver

AVCC

DVCC

Digital Control

Logic

VSOUT

VSINT

VS

CS

OUT

IN

SCK

SDI_TMDI

SDO_TMDO

IRQ

IN

CLK

IN

NRESET

DEM_OUT

IN

5.6

2 Li Battery Application (6V)

The supply voltage range is 4.4V to 6.6V and VAUX is connected to an inductive supply.

Figure 5-6. 2 Li Battery Application (6V) with Inductive Emergency Supply

ATmega

48/88/168

ATA5428

VS1

VS2

4.4V to 6.6V

VAUX

RF Transceiver

AVCC

DVCC

Digital Control

Logic

VSOUT

VSINT

VS

CS

OUT

IN

SCK

SDI_TMDI

SDO_TMDO

IRQ

IN

CLK

IN

NRESET

DEM_OUT

IN

ATA5428 [DATASHEET]

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6.

Microcontroller Interface

The microcontroller interface is a level converter which converts all internal digital signals that are referred to the DVCC

voltage into the voltage used by the microcontroller. Therefore, the pin VSINT has to be connected to the supply voltage of

the microcontroller.

This makes it possible to use the internal voltage regulator/switch at pin VSOUT as in Figure 2-1 on page 7 and Figure 2-3

on page 9 or to connect the microcontroller and the pin VSINT directly to the supply voltage of the microcontroller as in

Figure 2.2 on page 8.

7.

Digital Control Logic

7.1

Register Structure

The configuration of the transceiver is stored in RAM cells. The RAM contains a 16 × 8-bit TX/RX data buffer and a 6 × 8-bit

control register and is writable and readable via a 4-wire serial interface (CS, SCK, SDI_TMDI, SDO_TMDO).

The 1 × 8-bit status register is not part of the RAM and is readable via the 4-wire serial interface.

The RAM and the status information are stored as long as the transceiver is in any active mode (DVCC = VS1 or DVCC =

V_REG2) and are lost when the transceiver switches to OFF mode (DVCC =OFF).

After the transceiver is turned on via pin PWR_ON = High, T1 = Low, T2 = Low, T3 = Low, T4 = Low or T5 = Low or the

voltage at pin VAUX V_VAUX> 3.5V (typically), the control registers are in the default state.

Figure 7-1. Register Structure

MSB

LSB

TX/RX Data Buffer:

16 x 8 Bit

AVCC

_EN

T_

IR1

IR0

FS

-

OPM1 OPM0

Control Register 1 (ADR 0)

Control Register 2 (ADR 1)

Control Register 3 (ADR 2)

Control Register 4 (ADR 3)

Control Register 5 (ADR 4)

Control Register 6 (ADR 5)

MODE

P_

MODE

FR6

FR5

FR4

FR3

FR9

FR2

FR8

FR1

FR7

FR0

VSOUT CLK_

_EN ON

FR12 FR11 FR10

ASK/ Sleep Sleep Sleep Sleep Sleep

XSleep XLim

NFSK

4

3

2

1

0

BitChk BitChk Lim_

min5

Lim_

min4

Lim_

min3

Lim_

min2

Lim_

min1

Lim_

min0

1

0

Baud Baud Lim_

Lim_

1

0

max5 max4 max3 max2 max1 max0

Power_ Low_ P_On

ST5

ST4

ST3

ST2

ST1

Status Register (ADR 8)

On

Batt

_Aux

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7.2

7.3

TX/RX Data Buffer

The TX/RX data buffer is used to handle the data transfer during RX and TX operations.

Control Register

To use the transceiver in different applications, it can be configured by a connected microcontroller via the 4-wire serial

interface.

7.3.1 Control Register 1 (ADR 0)

Table 7-1. Control Register 1 (Function of Bit 7 and Bit 6 in RX Mode)

IR1

0

IR0

0

Function (RX Mode)

Pin IRQ is set to “1” if 4 received bytes are in the TX/RX data buffer or a receiving error occurred

Pin IRQ is set to “1” if 8 received bytes are in the TX/RX data buffer or a receiving error occurred

0

1

Pin IRQ is set to “1” if 12 received bytes are in the TX/RX data buffer or a receiving error occurred

(default)

1

0

1

Pin IRQ is set to “1” if a receiving error occurred

Table 7-2. Control Register 1 (Function of Bit 7 and Bit 6 in TX Mode)

IR1

0

IR0

0

Function (TX Mode)

Pin IRQ is set to “1” if 4 bytes remain in the TX/RX data buffer or the TX data buffer is empty

Pin IRQ is set to “1” if 8 bytes remain in the TX/RX data buffer or the TX data buffer is empty

Pin IRQ is set to “1” if 12 bytes remain in the TX/RX data buffer or the TX data buffer is empty (default)

Pin IRQ is set to “1” if the TX data buffer is empty

0

1

0

1

Table 7-3. Control Register 1 (Function of Bit 5)

AVCC_EN

Function

0

(default)

Table 7-4. Control Register 1 (Function of Bit 4)

FS

Function (RX Mode, TX Mode)

0

Selected frequency 433/868MHz (default)

Table 7-5. Control Register 1 (Function of Bit 2 and Bit 1)

OPM1

OPM0

Function

0

1

0

1

0

1

IDLE mode (default)

TX mode

RX polling mode

RX mode

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Table 7-6. Control Register 1 (Function of Bit 0)

T_MODE

Function

0

TX and RX function via TX/RX data buffer (default)

Transparent mode, TX/RX data buffer disabled, TX modulation data stream via pin SDI_TMDI, RX

modulation data stream via pin SDO_TMDO

1

7.3.2 Control Register 2 (ADR 1)

Table 7-7. Control Register 2 (Function of Bit 7, Bit 6, Bit 5, Bit 4, Bit 3, Bit 2 and Bit 1)

FR6

2⁶

FR5

2⁵

FR4

2⁴

FR3

2³

FR2

2²

FR1

2¹

FR0

2⁰

Function

0

.

0

.

0

.

0

.

0

.

0

.

0

1

.

FREQ2 = 0

FREQ2 = 1

1

.

0

.

1

.

1

.

0

.

0

.

0

.

FREQ2 = 88 (default)

FREQ2 = 127

1

Note:

Tuning of f_RFLSBs (total 13 bits), frequency trimming resolution of f_RFis f_XTO/16384, which is approximately

800Hz (see section “XTO”, Table 4-1 on page 23)

Table 7-8. Control Register 2 (Function of Bit 0 in RX Mode)

P_MODE

Function (RX Mode)

0

1

Pin IRQ is set to “1” if the bit check is successful (default)

No effect on pin IRQ if the bit check is successful

Table 7-9. Control Register 2 (Function of Bit 0 in TX Mode)

P_MODE

Function (TX Mode)

0

1

Manchester modulator on (default)

Manchester modulator off (NRZ mode)

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7.3.3 Control Register 3 (ADR 2)

Table 7-10. Control Register 3 (Function of Bit 7, Bit 6, Bit 5, Bit 4, Bit 3 and Bit 2)

FR12

2¹²

FR11

2¹¹

FR10

2¹⁰

FR9

2⁹

FR8

2⁸

FR7

2⁷

Function

0

.

0

.

0

.

0

.

0

1

.

0

1

0

.

FREQ3 = 0

FREQ3 = 128

FREQ3 = 256

.

0

.

1

.

1

.

1

.

1

.

0

.

FREQ3 = 3840 (default)

.

1

0

1

FREQ3 = 7936

FREQ3 = 8064

Note:

Tuning of f_RFMSBs

Table 7-11. Control Register 3 (Function of Bit 1)

VSOUT_EN

Function

0

1

Output voltage power supply for external devices off (pin VSOUT)

Output voltage power supply for external devices on (default)

Note:

This bit is set to “1” if the bit check is OK (RX_Polling, RX mode), an event at pin T1, T2, T3, T4 or T5 occurs

or the bit Power_On in the status register is “1”.

Setting VSOUT_EN = 0 in AUX mode is not allowed

Table 7-12. Control Register_3 (Function of Bit 0)

CLK_ON

Function

0

1

Clock output off (pin CLK)

Clock output on (default)

Note:

This bit is set to “1” if the bit check is OK (RX_Polling, RX mode), an event at pin T1, T2, T3, T4 or T5 occurs

or the bit Power_On in the status register is “1”.

7.3.4 Control Register 4 (ADR 3)

Table 7-13. Control Register 4 (Function of Bit 7)

ASK_NFSK

Function (TX Mode, RX Mode)

FSK mode (default)

ASK mode

0

1

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Table 7-14. Control Register 4 (Function of Bit 6, Bit 5, Bit 4, Bit 3 and Bit 2)

Function (RX Mode)

Sleep4

2⁴

Sleep3

2³

Sleep2

2²

Sleep1

2¹

Sleep0

2⁰

Sleep

(T_Sleep= Sleep × 1024 × T_DCLK× X_Sleep

)

0

.

0

.

0

.

0

.

0

1

.

0

1

10

0

1

0

1

0

(T_Sleep= 10 × 1024 × T_DCLK× X_Sleep)

(default)

.

1

31

Table 7-15. Control Register 4 (Function of Bit 1)

XSleep

Function

0

1

X_Sleep= 1; extended T_Sleepoff (default)

X_Sleep= 8; extended T_Sleepon

Table 7-16. Control Register 4 (Function of Bit 0)

XLim

Function

0

1

X_Lim= 1; extended T_{Lim_min}, T_{Lim_max}off (default)

X_Lim= 2; extended T_{Lim_min}, T_{Lim_max}on

7.3.5 Control Register 5 (ADR 4)

Table 7-17. Control Register 5 (Function of Bit 7 and Bit 6)

BitChk1

BitChk0

Function

0

1

0

1

0

1

N_Bit-check= 0 (0 bits checked during bit check)

N_Bit-check= 3 (3 bits checked during bit check) (default)

N_Bit-check= 6 (6 bits checked during bit check)

N_Bit-check= 9 (9 bits checked during bit check)

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Table 7-18. Control Register 5 (Function of Bit 5, Bit 4, Bit 3, Bit 2, Bit 1 and Bit 0 in RX Mode)

Function (RX Mode)

Lim_min

(Lim_min < 10 are not applicable)

Lim_min5

Lim_min4

Lim_min3

Lim_min2

Lim_min1

Lim_min0

(T_{Lim_min}= Lim_min × T_XDCLK)

0

.

0

.

1

.

0

.

1

.

0

1

.

10

11

16

0

1

0

(T_{Lim_min}= 16 × T_XDCLK)

(default)

.

1

63

Table 7-19. Control Register 5 (Function of Bit 5, Bit 4, Bit 3, Bit 2, Bit 1 and Bit 0 in TX Mode)

Function (TX Mode) Lim_min

(Lim_min < 10 are not applicable)

(TX_Bitrate = 1/((Lim_min + 1) × T_XDCLK

×

Lim_min5

Lim_min4

Lim_min3

Lim_min2

Lim_min1

Lim_min0

2)

0

.

0

.

1

.

0

.

1

.

0

1

.

10

11

16

(TX_Bitrate = 1/((16 + 1) × T_XDCLK× 2)

(default)

0

1

0

.

1

63

7.3.6 Control Register 6 (ADR 5)

Table 7-20. Control Register 6 (Function of Bit 7 and Bit 6)

Baud1

Baud0

Function

Bit-rate range 0 (B0) 1.0 Kbit/s to 2.5 Kbit/s;

T_XDCLK= 8 × T_DCLK× X_Lim

0

Bit-rate range 1 (B1) 2.0 Kbit/s to 5.0 Kbit/s;

T_XDCLK= 4 × T_DCLK× X_Lim

0

1

0

Bit-rate range 2 (B2) 4.0 Kbit/s to 10.0 Kbit/s;

T_XDCLK= 2 × T_DCLK× X_Lim; (default)

Bit-rate range 3 (B3) 8.0 Kbit/s to 20.0 Kbit/s;

T_XDCLK= 1 × T_DCLK× X_Lim

1

Note that the receiver does not work with >10 Kbit/s in ASK mode

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Table 7-21. Control Register 6 (Function of Bit 5, Bit 4, Bit 3, Bit 2, Bit 1 and Bit 0)

Function Lim_max

(Lim_max < 12 is not Applicable)

(T_{Lim_max}= (Lim_max – 1) × T_XDCLK)

Lim_max5

Lim_max4

Lim_max3

Lim_max2

Lim_max1

Lim_max0

0

.

0

.

1

.

1

.

0

.

0

1

.

12

13

28

0

1

0

(T_{Lim_max}= (28 – 1) × T_XDCLK)

(default)

.

1

63

7.4

Status Register

The status register indicates the current status of the transceiver and is readable via the 4-wire serial interface. Setting

Power_On or P_On_Aux or an event on ST1, ST2, ST3, ST4 or ST5 is indicated by an IRQ.

Reading the status register resets the bits Power_On, Low_Batt, P_On_Aux and the IRQ.

7.4.1 Status Register (ADR 8)

Table 7-22. Status Register

Status Bit

Function

Status of pin T5

Pin T5 = 0 → ST5 = 1

Pin T5 = 1 → ST5 = 0

(see Figure 7-3 on page 38)

ST5

ST4

ST3

ST2

ST1

Status of pin T4

Pin T4 = 0 → ST4 = 1

Pin T4 = 1 → ST4 = 0

(see Figure 7-3 on page 38)

Status of pin T3

Pin T3 = 0 → ST3 = 1

Pin T3 = 1 → ST3 = 0

(see Figure 7-3 on page 38)

Status of pin T2

Pin T2 = 0 → ST2 = 1

Pin T2 = 1 → ST2 = 0

(see Figure 7-3 on page 38)

Status of pin T1

Pin T1 = 0 → ST1 = 1

Pin T1 = 1 → ST1 = 0

(see Figure 7-3 on page 38)

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Table 7-22. Status Register (Continued)

Status Bit

Function

Indicates that the transceiver was woken up by pin PWR_ON (rising edge

on pin PWR_ON). During Power_On = 1, the bits VSOUT_EN and CLK_ON

in control register 3 are set to “1”. (see Figure 7-4 on page 39)

Power_On

Low_Batt

Indicates that output voltage on pin VSOUT is too low

(V_VSOUT< 2.38V typically), (see Figure 7-5 on page 40)

Indicates that the auxiliary supply voltage on pin VAUX is high enough to

operate.

State transition:

P_On_Aux

a) OFF mode → AUX mode (see Figure 5-2 on page 26)

b) IDLE mode (VSOUT = VS1) → IDLE mode (VSOUT = V_REG2)

(see Figure 7-6 on page 41)

7.5

Pin Tn

To switch the transceiver from OFF to IDLE mode, pin Tn must be set to “0” (maximum 0.2 × V_VS2) for at least T_{Tn_IRQ}(see

Figure 7-2). The transceiver recognizes the negative edge, sets pin N_RESET to low and switches on DVCC, AVCC and the

power supply for external devices VSOUT.

If V_DVCCexceeds 1.5V (typically) and the XTO is settled, the digital control logic is active and sets the status bit STn to “1”

and an interrupt is issued (T_{Tn_IRQ}).

After the voltage on pin VSOUT exceeds 2.3V (typically) and the start-up time of the XTO is elapsed, the output clock on pin

CLK is available. Because the enabling of pin CLK is asynchronous, the first clock cycle may be incomplete. N_RESET is set

to high if V_VSOUTexceeds 2.38V (typically) and the XTO is settled.

Figure 7-2. Timing Pin Tn, Status Bit STn

Tn

V_{Thres_2}= 2.38V (typ)

VSOUT

V_{Thres_1}= 2.3V (typ)

1.5V (typ)

DVCC, AVCC

N_RESET

CLK

T_{Tn_IRQ}

STn

(Status register)

IRQ

OFF

Mode

IDLE

Mode

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If the transceiver is in any active mode (IDLE, AUX, TX, RX, RX_Polling), an integrated debounce logic is active. If there is

an event on pin Tn a debounce counter is set to 0 (T = 0) and started. The status is updated, an interrupt is issued and the

debounce counter is stopped after reaching the counter value T = 8195 × T_DCLK

.

An event on the same key input before reaching T = 8195 × T_DCLKstops the debounce counter. An event on an other key

input before reaching T = 8195 × T_DCLKresets and restarts the debounce counter.

While the debounce counter is running, the bits VSOUT_EN and CLK_ON in control register 3 are set to “1”.

The interrupt is deleted after reading the status register or executing the command Delete_IRQ.

If pin Tn is not used, it can be left open because of an internal pull-up resistor (typically 50kΩ).

Figure 7-3. Timing Flow Pin Tn, Status Bit STn

IDLE Mode or

AUX Mode or

TX Mode or

RX Polling Mode or

RX Mode

Event on Pin Tn ?

N

Y

T = 0

Start debounce counter

Event on Pin Tn ?

N

Y

T = 8195 x T ?

N

Y

Tn = STn ?

Y

Pin Tn = 0 ?

Y

N

Stop debounce counter

STn = 1

Stop debounce counter

STn = 0

Stop debounce counter

IRQ = 1

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7.6

Pin PWR_ON

To switch the transceiver from OFF to IDLE mode, pin PWR_ON must be set to “1” (minimum 0.8 × V_VS2) for at least

T

_{PWR_ON}(see Figure 7-4). The transceiver recognizes the positive edge, sets pin N_RESET to low, and switches on DVCC,

AVCC and the power supply for external devices VSOUT.

If V_DVCCexceeds 1.5V (typically) and the XTO is settled, the digital control logic is active and sets the status bit Power_On to

“1” and an interrupt is issued (T_{PWR_ON_IRQ_1}).

After the voltage on pin VSOUT exceeds 2.3V (typically) and the start-up time of the XTO is elapsed the output clock on pin

CLK is available. Because the enabling of pin CLK is asynchronous, the first clock cycle may be incomplete. N_RESET is set

to high if V_VSOUTexceeds 2.38V (typically) and the XTO is settled.

If the transceiver is in any active mode (IDLE, AUX, RX, RX_Polling, TX), a positive edge on pin PWR_ON sets Power_On

to “1” (after T_{PWR_ON_IRQ_2}). The state transition Power_On 0 →1 generates an interrupt. If Power_On is still “1” during the

positive edge on pin PWR_ON no interrupt is issued. Power_On and the interrupt are deleted after reading the status

register.

During Power_On = 1, the bits VSOUT_EN and CLK_ON in control register 3 are set to “1”.

Note:

It is not possible to set the transceiver to OFF mode by setting pin PWR_ON to “0”. If pin PWR_ON is not used,

it must be connected to GND.

Figure 7-4. Timing Pin PWR_ON, Status Bit Power_On

T_{PWR_ON}> T_{PWR_ON_IRQ_1}

T_{PWR_ON}> T_{PWR_ON_IRQ_2}

PWR_ON

V_{Thres_2}= 2.38V (typ)

VSOUT

V_{Thres_1}= 2.V

(typ)

1.5V (typ)

DVCC, AVCC

N_RESET

CLK

T_{PWR_ON_IRQ_1}

T_{PWR_ON_IRQ_2}

Power_ON

(Status register)

IRQ

OFF

Mode

IDLE

Mode

IDLE, AUX, RX, RX Polling, TX

Mode

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7.7

Low Battery Indicator

The status bit Low_Batt is set to “1” if the voltage V_VSOUTon pin VSOUT drops below 2.38V (typically).

Low_Batt is set to “0” if V_VSOUTexceeds V_{Thres_2}and the status register is read via the 4-wire serial interface (see Figure 5-3

on page 28).

Figure 7-5. Timing Status Bit Low_Batt

IDLE, AUX, TX, RX

or

RX Polling Mode

V_VSOUT< 2.38V (typ)

N

?

Y

Low_Batt = 1

Read Status Register

7.8

Pin VAUX

To switch the transceiver from OFF to AUX mode, the voltage V_VAUXon pin VAUX must exceed 3.5V (typically) (see Figure

7-6 on page 41). If V_VAUXexceeds 2V (typically) pin N_RESET is set to low, and DVCC and the power supply for external

devices VSOUT are switched on.

If V_VAUXexceeds 3.5V (typically) the status bit P_On_Aux is set to “1” and an interrupt is issued.

After the voltage on pin VSOUT exceeds 2.3V (typically) and the start-up time of the XTO is elapsed, the output clock on pin

CLK is available. Because the enabling of pin CLK is asynchronous, the first clock cycle may be incomplete. N_RESET is set

to high if V_VSOUTexceeds 2.38V (typically) and the XTO is settled.

If the transceiver is in any active mode (IDLE, TX, RX, RX_Polling), a positive edge on pin VAUX and V_VAUX> VS1 + 0.5V

sets P_On_Aux to “1”. The state transition P_On_Aux 0 →1 generates an interrupt. If P_On_Aux is still “1” during the positive

edge on pin VAUX no interrupt is issued. P_On_Aux and the interrupt are deleted after reading the status register.

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Figure 7-6. Timing Pin VAUX, Status Bit P_On_Aux

V

_VAUX> VS1 + 0.5V (typ)

V_VAUX> VS1 + 0.5V (typ)

3.5V (typ)

2.0V (typ)

VAUX

V_{Thres_2}= 2.38V (typ)

V_{Thres_1}= 2.3V (typ)

VSOUT

DVCC

N_RESET

CLK

P_ON_AUX

(Status register)

IRQ

OFF

Mode

AUX

Mode

IDLE, TX, RX, RX polling

Mode

8.

Transceiver Configuration

The configuration of the transceiver takes place via a 4-wire serial interface (CS, SCK, SDI_TMDI, SDO_TMDO) and is

organized in 8-bit units. The configuration is initiated with an 8-bit command. While shifting the command into pin SDI_TMDI,

the number of bytes in the TX/RX data buffer are available on pin SDO_TMDO. The read and write commands are followed

by one or more 8-bit data units. Each 8-bit data transmission begins with the MSB. The serial interface is in the reset state if

the level on pin CS = Low.

8.1

Command: Read TX/RX Data Buffer

During a RX operation, the user can read the received bytes in the TX/RX data buffer successively.

Figure 8-1. Read TX/RX Data Buffer

MSB

LSB

MSB

LSB

MSB

LSB

SDI_TMDI Command: Read TX/RX Data Buffer

X

No. Bytes in the TX/RX Data Buffer

RX Data Byte 1

SDO_TMDO

SCK

CS

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8.2

Command: Write TX/RX Data Buffer

During a TX operation the user can write the bytes in the TX/RX data buffer successively. An echo of the command and the

TX data bytes are provided for the microcontroller on pin SDO_TMDO.

Figure 8-2. Write TX/RX Data Buffer

MSB

LSB

MSB

LSB

MSB

LSB

SDI_TMDI Command: Write TX/RX Data Buffer

TX Data Byte 1

TX Data Byte 2

TX Data Byte 1

No. Bytes in the TX/RX Data Buffer

Write TX/RX Data Buffer

SDO_TMDO

SCK

CS

8.3

Command: Read Control/Status Register

The control and status registers can be read individually or successively.

Figure 8-3. Read Control/Status Register

MSB

LSB

MSB

LSB

MSB

LSB

SDI_TMDI

SDO_TMDO

SCK

Command: Read C/S Register X

Command: Read C/S Register Y

Command: Read C/S Register Z

No. Bytes in the TX/RX Data Buffer

Data C/S Register X

Data C/S Register Y

CS

8.4

Command: Write Control Register

The control registers can be written individually or successively. An echo of the command and the data bytes are provided

for the microcontroller on pin SDO_TMDO.

Figure 8-4. Write Control Register

MSB

LSB

MSB

Data Control Register X

LSB

MSB

LSB

SDI_TMDI Command: Write Control Register X

Command: Write Control Register Y

No. Bytes in the TX/RX Data Buffer

Write Control Register X

Data Control Register X

SDO_TMDO

SCK

CS

8.5

Command: OFF Command

If AVCC_EN in control register 1 is “0”, the input level on pin PWR_ON is low and on the key inputs Tn is high, then the OFF

command sets the transceiver in the OFF mode.

Figure 8-5. OFF Command

MSB

LSB

SDI_TMDI

SDO_TMDO

SCK

Command: OFF Command

No. Bytes in the TX/RX Data Buffer

CS

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8.6

Command: Delete IRQ

The delete IRQ command sets pin IRQ to low.

Figure 8-6. Delete IRQ

MSB

LSB

SDI_TMDI

Command: Delete IRQ

No. Bytes in the TX/RX Data Buffer

SDO_TMDO

SCK

CS

8.7

Command Structure

The three most significant bits of the command (bit 5 to bit 7) indicate the command type. Bit 0 to bit 4 describe the target

address when reading or writing a control or status register. In all other commands bit 0 to bit 4 have no effect and should be

set to “0” for compatibility with future products.

Table 8-1. Command Structure

MSB

LSB

Bit 0

x

Command

Bit 7

Bit 6

Bit 5

Bit 4

x

Bit 3

x

Bit 2

x

Bit 1

x

Read TX/RX data buffer

Write TX/RX data buffer

Read control/status register

Write control register

OFF command

0

1

0

1

0

1

0

1

0

1

0

1

0

1

x

A4

X

A3

X

A2

X

A1

X

A0

X

Delete IRQ

X

Not used

X

Not used

X

8.8

4-wire Serial Interface

The 4-wire serial interface consists of the Chip Select (CS), the Serial Clock (SCK), the Serial Data Input (SDI_TMDI) and

the Serial Data Output (SDO_TMDO). Data is transmitted/received bit by bit in synchronization with the serial clock.

Note:

If the output level on pin N_RESET is low, no data communication with the microcontroller is possible.

When CS is low and the transparent mode is inactive (T_MODE = 0), SDO_TMDO is in a high impedance state. When CS is

low and the transparent mode is active (T_MODE = 1), the RX data stream is available on pin SDO_TMDO.

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Figure 8-7. Serial Timing

T_{CS_disable}

CS

T_{CS_setup}

T_{SCK_setup2}

T_Cycle

T_{SCK_setup1}

T_{SCK_hold}

SCK

SDI_TMDI

X

T_Hold

T_Setup

X

MSB

X

MSB-1

X

T_{Out_enable}

T_{Out_delay}

T_{Out_disable}

SDO_TMDO

MSB

X can be either V_iLor V_iH

MSB-1

LSB

9.

Operation Modes

9.1

RX Operation

The transceiver is set to RX operation with the bits OPM0 and OPM1 in control register 1.

Table 9-1. Control Register 1

OPM1

OPM0

Function

1

0

1

RX polling mode

RX mode

The transceiver is designed to consume less than 1mA in RX operation while remaining sensitive to signals from a

corresponding transmitter. This is achieved via the polling circuit. This circuit enables the signal path periodically for a short

time. During this time the bit-check logic verifies the presence of a valid transmitter signal. Only if a valid signal is detected

does the transceiver remain active and transfer the data to the connected microcontroller. This transfer takes place either via

the TX/RX data buffer or via the pin SDO_TMDO. When there is no valid signal present, the transceiver is in sleep mode

most of the time, resulting in low current consumption. This condition is called RX polling mode. A connected microcontroller

can be disabled during this time.

All relevant parameters of the polling logic can be configured by the connected microcontroller. This flexibility enables the

user to meet the specifications in terms of current consumption, system response time, data rate, etc.

In RX mode the RF transceiver is enabled permanently and the bit-check logic verifies the presence of a valid transmitter

signal. When a valid signal is detected the transceiver transfers the data to the connected microcontroller. This transfer take

place either via the TX/RX data buffer or via the pin SDO_TMDO.

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9.1.1 RX Polling Mode

When the transceiver is in RX polling mode it stays in a continuous cycle of three different modes. In sleep mode the RF

transceiver is disabled for the time period T_Sleepwhile consuming low current of I_S= I_{IDLE_X}. During the start-up period,

_{Startup_PLL}and T_{Startup_Sig_Proc}, all signal processing circuits are enabled and settled. In the following bit-check mode, the

T

incoming data stream is analyzed bit by bit to see if it is a valid transmitter signal. If no valid signal is present, the transceiver

is set back to sleep mode after the period T_Bit-check. This period varies check by check as it is a statistical process. An

average value for T_Bit-checkis given in the electrical characteristics. During T_{Startup_PLL}the current consumption is I_S=

I

_{Startup_PLL_X}. During T_{Startup_Sig_Proc}and T_Bit-checkthe current consumption is I_S= I_{RX_X}. The condition of the transceiver is

indicated on pin RX_ACTIVE (see Figure 9-1 on page 46 and Figure 9-2 on page 47). The average current consumption in

RX polling mode I_Pis different in 1 Li battery application (3V), 2 Li battery application (6V) or Base-station Application (5V).

To calculate I_Pthe index X must be replaced by VS1,VS2 in 1 Li battery application (3V), VS2 in 2 Li battery application (6V)

or VS2,VAUX in Base-station Application (5V) (see section “Electrical Characteristics: General” on page 58).

I_{IDLE_X}× T_Sleep+ I_{Startup_PLL_X}× T_{Startup_PLL}+ I_{RX_X}× (T_{Startup_Sig_Proc}+ T_Bitcheck

I_P= ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

_Sleep+ T_{Startup_PLL}+ T_{Startup_Sig_Proc}+ T_{Bit_check}

)

T

To save current it is recommended that CLK and V_VSOUTbe disabled during RX polling mode. I_Pdoes not include the current

of the Microcontroller_Interface, I_VSINT, or the current of an external device connected to pin VSOUT (for example,

microcontroller). If CLK and/or VSOUT is enabled during RX polling mode the current consumption is calculated as follows:

I_{S_Poll}= I_P+ I_VSINT+ I_EXT

During T_Sleep, T_{Startup_PLL}and T_{Startup_Sig_Proc}, the transceiver is not sensitive to a transmitter signal. To guarantee the

reception of a transmitted command, the transmitter must start the telegram with an adequate preburst. The required length

of the preburst, T_Preburst, depends on the polling parameters T_Sleep, T_{Startup_PLL}, T_{Startup_Sig_Proc}and T_Bit-check. Thus, T_Bit-check

depends on the actual bit rate and the number of bits (N_Bit-check) to be tested.

T_Preburst≥ T_Sleep+ T_{Startup_PLL}+ T_{Startup_Sig_Proc}+ T_{Bit_check}

9.1.2 Sleep Mode

The length of period T_Sleepis defined by the 5-bit word sleep in control register 4, the extension factor X_Sleepdefined by the bit

X_Sleepin control register 4, and the basic clock cycle T_DCLK. It is calculated to be:

T_Sleep= Sleep × 1024 × T_DCLK× X_Sleep

In US and European applications, the maximum value of T_Sleepis about 38ms if X_Sleepis set to 1 (which is done by setting the

bit X_Sleepin control register 4 to “0”). The time resolution is about 1.2ms in that case. The sleep time can be extended to

about 300ms by setting X_Sleepto 8 (which is done by setting X_Sleepin control register 4 to “1”), the time resolution is then

about 9.6ms.

9.1.3 Start-up Mode

During T_{Startup_PLL}the PLL is enabled and starts up. If the PLL is locked, the signal processing circuit starts up

(T_{Startup_Sig_Proc}). After the start-up time all circuits are in stable condition and ready to receive.

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Figure 9-1. Flow Chart Polling Mode/RX Mode (T_MODE = 0, Transparent Mode Inactive)

Start RX Polling Mode

Sleep:

Defined by bits Sleep 0 to Sleep 4 in Control

Register 4

Defined by bit XSleep in Control register 4

Basic clock cycle

Sleep mode:

All circuits for analog signal processing are disabled. Only XTO and Polling logic is enabled.

Output level on pin RX_ACTIVE → Low; I_S= I_{IDLE_X}

T_Sleep= Sleep x 1024 x T_DCLKx X_Sleep

X_Sleep

:

T_DCLK

Start RX Mode

Start-up mode:

Start-up PLL:

T_{Startup_PLL}

:

798.5 x T_DCLK(typ)

The PLL is enabled and locked.

Output level on pin RX_ACTIVE → High; I_S= I_{Startup_PLL_X}; I_{Startup_PLL}

T_{Startup_Sig_Proc}

:

882 x T_DCLK

498 x T_DCLK

306 x T_DCLK

210 x T_DCLK

(BR_Range 0)

(BR_Range 1)

(BR_Range 2)

(BR_Range 3)

Start-up signal processing:

The signal processing circuit are enabled.

Output level on pin RX_ACTIVE → High; I_S= I_{RX_X}; T_{Startup_Sig_proc}

Is defined by the selected baud rate range and

_DCLK.The baud-rate range is defined by bit

T

Baud 0 and Baud 1 in Control Register 6.

Bit-check mode:

The incomming data stream is analyzed. If the timing indicates a valid transmitter signal,

the control bits VSOUT_EN, CLK_ON and OPM0 are set to 1 and the transceiver is set to

receiving mode. Otherwise it is set to Sleep mode or to Start_up mode.

Output level on pin RX_ACTIVE → High

I_S= I_{RX_X}; T_Bit-check

T_Bit-check

:

Depends on the result of the bit check.

NO

Bit check

OK ?

If the bit check is ok, T_Bit-checkdepends on the

number of bits to be checked (N_Bit-check) and

on the utilized data rate.

YES

Set VSOUT_EN = 1

Set CLK_ON = 1

Set OPM0 = 1

If the bit check fails, the average time period for

that check despends on the selected bit-rate

range and on T_XDCLK. The bit-rate range is

defined by bit Baud 0 and Baud 1 in Control

Register 6.

NO

OPM0 = 1

?

YES

NO

P_MODE = 0

?

NO

YES

T_SLEEP= 0

?

Set IRQ

YES

Receiving mode:

The incomming data stream is passed via the TX/RX Data Buffer to the connected

microcontroller. If an bit error occurs the transceiver is set back to Start-up mode.

Output level on pin RX_ACTIVE → High

If the transceiver detects a bit errror after a

successful bit check and before the start bit is

detected pin IRQ will be set to high (only if

P_MODE = 0) and the transceiver is set back to

start-up mode.

I_S= I_{RX_X}

NO

Start bit

detected ?

YES

RX data stream is

written into the TX/RX

Data Buffer

NO

Bit error ?

YES

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Figure 9-2. Flow Chart Polling Mode/RX Mode (T_MODE = 1, Transparent Mode Active)

Start RX Polling Mode

Sleep:

Defined by bits Sleep 0 to Sleep 4 in Control

Register 4

Defined by bit XSleep in Control register 4

Basic clock cycle

Sleep mode:

All circuits for analog signal processing are disabled. Only XTO and Polling logic is enabled.

Output level on pin RX_ACTIVE → Low; I_S= I_{IDLE_X}

T_Sleep= Sleep x 1024 x T_DCLKx X_Sleep

X_Sleep

:

T_DCLK

Start RX Mode

Start-up mode:

Start-up PLL:

T_{Startup_PLL}

:

798.5 x T_DCLK(typ)

The PLL is enabled and locked.

Output level on pin RX_ACTIVE → High; I_S= I_{Startup_PLL_X}; I_{Startup_PLL}

T_{Startup_Sig_Proc}

:

882 x T_DCLK

498 x T_DCLK

306 x T_DCLK

210 x T_DCLK

(BR_Range 0)

(BR_Range 1)

(BR_Range 2)

(BR_Range 3)

Start-up signal processing:

The signal processing circuit are enabled.

Output level on pin RX_ACTIVE → High; I_S= I_{RX_X}; T_{Startup_Sig_proc}

Is defined by the selected baud rate range and

_DCLK.The baud-rate range is defined by bit

T

Baud 0 and Baud 1 in Control Register 6.

Bit-check mode:

The incomming data stream is analyzed. If the timing indicates a valid transmitter signal,

the control bits VSOUT_EN, CLK_ON and OPM0 are set to 1 and the transceiver is set to

receiving mode. Otherwise the transceiver is set to Sleep mode

(if OPM0 = 0 and T_Sleep> 0) or stays in Bit-check mode.

→

Output level on pin RX_ACTIVE

High

T_Bit-check

:

Depends on the result of the bit check.

I_S= I_{RX_X}; T_Bit-check

NO

Bit check

OK ?

If the bit check is ok, T_Bit-checkdepends on the

number of bits to be checked (N_Bit-check) and

on the utilized data rate.

YES

NO

OPM0 = 1

?

If the bit check fails, the average time period for

that check despends on the selected bit-rate

range and on T_XDCLK. The bit-rate range is

defined by bit Baud 0 and Baud 1 in Control

Register 6.

YES

Set VSOUT_EN = 1

Set CLK_ON = 1

Set OPM0 = 1

NO

T_SLEEP= 0

?

YES

Receiving mode:

The incomming data stream is passed via PIN SDO_TMDO to the connected

microcontroller. If an bit error occurs the transceiver is not set back to Start-up mode.

Output level on pin RX_ACTIVE → High

If in FSK mode the datastream is interrupted the

FSK-Demodulator-PLL tends to lock out and is

further not able to lock in, even there is a valid

data stream available.

In this case the transceiver must be set back to

IDLE mode.

I_S= I_{RX_X}

NO

Level on pin

CS = Low ?

YES

RX data stream

available on pin

SDO_TMDO

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9.1.4 Bit-check Mode

In bit-check mode the incoming data stream is examined to distinguish between a valid signal from a corresponding

transmitter and signals due to noise. This is done by subsequent time frame checks where the distance between 2 signal

edges are continuously compared to a programmable time window. The maximum count of this edge-to-edge test before the

transceiver switches to receiving mode is also programmable.

9.1.5 Configuration of the Bit Check

Assuming a modulation scheme that contains two edges per bit, two time frame checks verify one bit. This is valid for

Manchester, Bi-phase and most other modulation schemes. The maximum count of bits to be checked can be set to 0, 3, 6

or 9 bits via the variable N_Bit-checkin control register 5. This implies 0, 6, 12 and 18 edge-to-edge checks, respectively. If N_Bit-

_checkis set to a higher value, the transceiver is less likely to switch to receiving mode due to noise. In the presence of a valid

transmitter signal, the bit check takes less time if N_Bit-checkis set to a lower value. In RX polling mode, the bit-check time is not

dependent on N_Bit-checkif no valid signal is present. Figure 9-3 shows an example where three bits are tested successfully.

Figure 9-3. Timing Diagram for Complete Successful Bit Check (Number of Checked Bits: 3)

RX_ACTIVE

Bit check ok

Bit check

1/2 Bit

Demod_Out

T_{Startup_Sig_Proc}

Start-up mode

T_Bit-check

Bit check mode

Receiving mode

As seen in Figure 9-4, the time window for the bit check is defined by two separate time limits. If the edge-to-edge time t_eeis

in between the lower bit-check limit T_{Lim_min}and the upper bit-check limit T_{Lim_max}, the check will be continued. If t_eeis smaller

than limit T_{Lim_min}or exceeds T_{Lim_max}, the bit check will be terminated and the transceiver switches to sleep mode.

Figure 9-4. Valid Time Window for Bit Check

1/f_Sig

Demod_Out

t_ee

T_{Lim_min}

T_{Lim_max}

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For the best noise immunity, use of a low span between T_{Lim_min}and T_{Lim_max}is recommended. This is achieved using a fixed

frequency at a 50% duty cycle for the transmitter preburst: a “11111...” or a “10101...” sequence in Manchester or Bi-phase

is a good choice. A good compromise between sensitivity and susceptibility to noise regarding the expected edge-to-edge

time, t_ee, is a time window of ±38%; to get the maximum sensitivity the time window should be ±50% and then N_Bit-check≥ 6.

Using preburst patterns that contain various edge-to-edge time periods, the bit-check limits must be programmed according

to the required span.

The bit-check limits are determined by means of the formula below:

T

_{Lim_min}= Lim_min × T_XDCLK

T_{Lim_max}= (Lim_max -1) × T_XDCLK

Lim_min is defined by the bits Lim_min 0 to Lim_min 5 in control register 5.

Lim_max is defined by the bits Lim_max 0 to Lim_max 5 in control register 6.

Using the above formulas, Lim_min and Lim_max can be determined according to the required T_{Lim_min}, T_{Lim_max}and T_XDCLK

The time resolution defining T_{Lim_min}and T_{Lim_max}is T_XDCLK. The minimum edge-to-edge time t_eeis defined in the section

“Receiving Mode” on page 51. The lower limit should be set to Lim_min ≥ 10. The maximum value of the upper limit is

Lim_max = 63.

.

Figure 9-5, Figure 9-6 on page 50, and Figure 9-7 on page 50 illustrate the bit check for the bit-check limits Lim_min = 14

and Lim_max = 24. The signal processing circuits are enabled during T_{Startup_PLL}and T_{Startup_Sig_Proc}. The output of the

ASK/FSK demodulator (Demod_Out) is undefined during that period. When the bit check becomes active, the bit-check

counter is clocked with the cycle T_XDCLK

.

Figure 9-5 shows how the bit check proceeds if the bit-check counter value CV_Lim is within the limits defined by Lim_min

and Lim_max at the occurrence of a signal edge. In Figure 9-6 on page 50 the bit check fails because the value CV_Lim is

lower than the limit Lim_min. The bit check also fails if CV_Lim reaches Lim_max. This is illustrated in Figure 9-7 on page

50.

Figure 9-5. Timing Diagram During Bit Check

(Lim_min = 14, Lim_max = 24)

RX_ACTIVE

Bit check ok

Bit check

Demod_Out

1/2 Bit

0

1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 101112131415161718 1 2 3 4 5 6 7 8 9 10 1112131415 1 2 3 4 5 6 7

Bit-check counter

T_XDCLK

T_{Startup_Sig_Proc}

Start-up mode

T_Bit-check

Bit check mode

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Figure 9-6. Timing Diagram for Failed Bit Check (Condition CV_Lim < Lim_min)

(Lim_min = 14, Lim_max = 24)

RX_ACTIVE

Bit check failed (CV_Lim < Lim_min)

Bit check

1/2 Bit

Demod_Out

0

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

9 101112

0

Bit-check counter

T_{Startup_Sig_Proc}

Start-up mode

T_{Bit_check}

Bit check mode

T_Sleep

Sleep mode

Figure 9-7. Timing Diagram for Failed Bit Check (Condition: CV_Lim ≥ Lim_max)

(Lim_min = 14, Lim_max = 24)

RX_ACTIVE

Bit check failed (CV_Lim < Lim_min)

Bit check

1/2 Bit

Demod_Out

0

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

9 101112131415161718192021222324

0

Bit-check counter

T_{Startup_Sig_Proc}

Start-up mode

T_{Bit_check}

Bit check mode

T_Sleep

Sleep mode

9.1.6 Duration of the Bit Check

If no transmitter is present during the bit check, the output of the ASK/FSK demodulator delivers random signals. The bit

check is a statistical process and T_Bit-checkvaries for each check. Therefore, an average value for T_Bit-checkis given in the

electrical characteristics. T_Bit-checkdepends on the selected bit-rate range and on T_XDCLK. A higher bit-rate range causes a

lower value for T_Bit-check, resulting in a lower current consumption in RX polling mode.

In the presence of a valid transmitter signal, T_Bit-checkis dependent on the frequency of that signal, f_Signal, and the count of the

bits, N_Bit-check. A higher value for N_Bit-checktherefore results in a longer period for T_Bit-check, requiring a higher value for the

transmitter pre-burst, T_Preburst

.

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9.1.7 Receiving Mode

If the bit check was successful for all bits specified by N_Bit-check, the transceiver switches to receiving mode. To activate a

connected microcontroller, the bits VSOUT_EN and CLK_ON in control register 3 are set to “1”. An interrupt is issued at pin

IRQ if the control bits T_MODE = 0 and P_MODE = 0.

If the transparent mode is active (T_MODE = 1) and the level on pin CS is low (no data transfer via the serial interface), the

RX data stream is available on pin SDO_TMDO (Figure 9-8).

Figure 9-8. Receiving Mode (TMODE = 1)

Preburst

Byte 1

Byte 2

Byte 3

Start

bit

Bit check ok

Demod_Out

SDO_TMDO

'0' '0' '0' '0' '0' '0' '0' '0' '0' '1' '0' '1' '0' '0' '0' '0' '0' '1' '1' '1' '1' '0' '0' '1' '1' '0' '1' '0' '1' '1' '0' '0'

Bit-check mode

Receiving mode

If the transparent mode is inactive (T_MODE = 0), the received data stream is buffered in the TX/RX data buffer (see Figure

9-9 on page 52). The TX/RX data buffer is only usable for Manchester and Bi-phase coded signals. It is always possible to

transfer the data from the data buffer via the 4-wire serial interface to a microcontroller (see Figure 8-1 on page 41).

Buffering of the data stream:

After a successful bit check, the transceiver switches from bit-check mode to receiving mode. In receiving mode the TX/RX

data buffer control logic is active and examines the incoming data stream. This is done, as in the bit check, by subsequent

time frame checks where the distance between two edges is continuously compared to a programmable time window as

illustrated in Figure 9-9 on page 52. Only two time differences between two edges in Manchester and Bi-phase coded

signals are valid (T and 2T).

The limits for T are the same as used for the bit check. They can be programmed in control register 5 and 6 (Lim_min,

Lim_max).

The limits for 2T are calculated as follows:

Lower limit of 2T:

Lim_min_2T = (Lim_min + Lim_max) – (Lim_max – Lim_min)/2

T_{Lim_min_2T}= Lim_min_2T × T_XDCLK

Upper limit of 2T:

Lim_max_2T = (Lim_min + Lim_max) + (Lim_max – Lim_min)/2

T_{Lim_max_2T}= (Lim_max_2T - 1) × T_XDCLK

If the result of Lim_min_2T or Lim_max_2T is not an integer value, it will be rounded up.

If the TX/RX data buffer control logic detects the start bit, the data stream is written in the TX/RX data buffer byte by byte.

The start bit is part of the first data byte and must be different from the bits of the preburst. If the preburst consists of a

sequence of “00000...”, the start bit must be a “1”. If the preburst consists of a sequence of “11111...”, the start bit must be a

“0”.

If the data stream consists of more than 16 bytes, a buffer overflow occurs and the TX/RX data buffer control logic overwrites

the bytes already stored in the TX/RX data buffer. Therefore, it is very important to ensure that the data is read in time so that

no buffer overflow occurs (see Figure 8-1 on page 41). There is a counter that indicates the number of received bytes in the

TX/RX data buffer (see section “Transceiver Configuration” on page 41). If a byte is transferred to the microcontroller, the

counter is decremented; if a byte is received, the counter is incremented. The counter value is available via the 4-wire serial

interface. An interrupt is issued if the counter (while counting up) reaches the value defined by the control bits IR0 and IR1 in

control register 1.

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Figure 9-9. Receiving Mode (TMODE = 0)

Preburst

Byte 1

Byte 2

Byte 3

Start

bit

T

2T

Bit check ok

Demod_Out

'0' '0' '0' '0' '0' '0' '0' '0' '0' '1' '0' '1' '0' '0' '0' '0' '0' '1' '1' '1' '1' '0' '0' '1' '1' '0' '1' '0' '1' '1' '0' '0'

Bit-check mode

Receiving mode

TX/RX Data Buf

fer

Byte 16, Byte 32, ...

Byte 15, Byte 31, ...

Byte 14, Byte 30, ...

Byte 13, Byte 29, ...

Byte 12, Byte 28, ...

Byte 11, Byte 27, ...

Byte 10, Byte 26, ...

Byte 9, Byte 25, ...

Byte 8, Byte 24, ...

Byte 7, Byte 23, ...

Byte 6, Byte 22, ...

Byte 5, Byte 21, ...

Byte 4, Byte 20, ...

Byte 3, Byte 19, ...

Byte 2, Byte 18, ...

Byte 1, Byte 17, ...

1

MSB

1

0

1

0

1

0

LSB

1

0

Readable via 4-wire serial interface

If the TX/RX data buffer control logic detects a bit error, an interrupt is issued and the transceiver is set back to the start-up

mode (see Figure 9-1 on page 46, Figure 9-2 on page 47 and Figure 9-10).

Bit error:

a) t_ee< T_{Lim_min}or T_{Lim_max}< t_ee< T_{Lim_min_2T}or t_ee> T_{Lim_max_2T}

b) Logical error (no edge detected in the bit center)

Note:

The byte consisting of the bit error will not be stored in the TX/RX data buffer. Thus, it is not available via the 4-

wire serial interface.

Writing the control register 1, 4, 5 or 6 during receiving mode resets the TX/RX data buffer control logic and the counter

which indicates the number of received bytes. If the bits OPM0 and OPM1 are still “1” after writing to a control register, the

transceiver changes to the start-up mode (start-up signal processing).

Figure 9-10. Bit Error (TMODE = 0)

Byte 1

Preburst

Byte n+1

Byte n

Byte n-1

Demod_Out

Receiving mode

Start-up mode Bit-check mode

Receiving mode

Table 9-2. RX Modulation Scheme

Bit in TX/RX Data

Buffer

Level on Pin

SD0_TMDO

Mode

ASK/_NFSK

T_MODE

RF_IN

0

1

0

1

f

_{FSK_L}→ f_{FSK_H}

1

0

–

1

0

–

X

1

0

X

1

0

f

_{FSK_H}→ f_{FSK_L}

0

f_{FSK_H}

f_{FSK_L}

RX

f_ASKoff → f_ASKon

f_ASKon → f_ASKoff

f_ASKon

1

f_ASKoff

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9.1.8 Recommended Lim_min and Lim_max for Maximum Sensitivity

The sensitivity measurements in the section “Low-IF Receiver” in Table 3-3 on page 11 and Table 3-4 on page 11 have been

done with the Lim_min and Lim_max values according to Table 9-3. These values are optimized for maximum sensitivity.

Note that since these limits are optimized for sensitivity, the number of checked bits, N_Bit-check, has to be at least 6 to prevent

the circuit from waking up to often in polling mode due to noise.

Table 9-3. Recommended Lim_min and Lim_max Values for Different Bit Rates

1.0 Kbit/s

BR_Range_0

XLim = 1

2.4 Kbit/s

BR_Range_0

XLim = 0

5 Kbit/s

BR_Range_1

XLim = 0

10 Kbit/s

BR_Range_2

XLim = 0

20 Kbit/s

BR_Range_3

XLim = 0

f_RF(f_XTAL)/

MHz

433.92

(13.25311)

Lim_min = 13 (251µs)

Lim_max = 38 (715µs)

Lim_min = 12 (116µs)

Lim_max = 34 (319µs)

Lim_min = 11 (53µs)

Lim_max = 32 (150µs)

Lim_min = 11 (27µs)

Lim_max = 32 (75µs)

Lim_min = 11 (13µs)

Lim_max = 32 (37µs)

868.3

(13.41191)

Lim_min = 13 (248µs)

Lim_max = 38 (706µs)

Lim_min = 12 (115µs)

Lim_max = 34 (315µs)

Lim_min = 11 (52µs)

Lim_max = 32 (148µs)

Lim_min = 11 (26µs)

Lim_max = 32 (74µs)

Lim_min = 11 (13µs)

Lim_max = 32 (37µs)

9.2

TX Operation

The transceiver is set to TX operation by using the bits OPM0 and OPM1 in the control register 1.

Table 9-4. Control Register 1

OPM1

OPM0

Function

TX mode

0

1

Before activating TX mode, the TX parameters (bit rate, modulation scheme, etc.) must be selected as illustrated in Figure 9-

11 on page 54. The bit rate depends on Baud 0 and Baud 1 in control register 6, Lim_min0 to Lim_min5 in control register 5

and XLIM in control register 4 (see section “Control Register” on page 31). The modulation is selected with ASK/_NFSK in

control register 4. The FSK frequency deviation is fixed to about ±16kHz. If P_Mode is set to “1”, the Manchester modulator

is disabled and pattern mode is active (NRZ, see Table 9-5 on page 56).

After the transceiver is set to TX mode, the start-up mode is active and the PLL is enabled. If the PLL is locked, the TX mode

is active.

If the transceiver is in start-up or TX mode, the TX/RX data buffer can be loaded via the 4-wire serial interface. After the first

byte is in the buffer and the TX mode is active, the transceiver starts transmitting automatically (beginning with the MSB).

While transmitting it is always possible to load new data in the TX/RX data buffer. To prevent a buffer overflow or

interruptions during transmitting, the user must ensure that data is loaded at the same speed as it is transmitted.

There is a counter that indicates the number of bytes to be transmitted (see section “Transceiver Configuration” on page 41).

If a byte is loaded, the counter is incremented, if a byte is transmitted, the counter is decremented. The counter value is

available via the 4-wire serial interface. An IRQ is issued if the counter (while counting down) reaches the value defined by

the control bits IR0 and IR1 in control register 1.

Note:

Writing to the control register 1, 4, 5 or 6 during TX mode resets the TX/RX data buffer and the counter which

indicates the number of bytes to be transmitted.

If T_Mode in control register 1 is set to “1”, the transceiver is in TX transparent mode. In this mode the TX/RX data buffer is

disabled and the TX data stream must be applied on pin SDI_TMDI. Figure 9-11 on page 54 illustrates the flow chart of the

TX transparent mode.

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Figure 9-11. TX Operation (T_MODE = 0)

Write Control Register 6

Baud1, BAUD0:

Lim_max0 to Lim_max5:

Select baud rate range

Don't care

Write Control Register 5

Lim_min0 to Lim_min5:

Bit_ck0, Bit_ck1:

Select the baud rate

Don't care

Write Control Register 4

XLim:

Select the bit rate

Select modulation

Don't care

ASK/_NFSK:

Sleep0 to Sleep4:

XSleep:

Don't care

Write Control Register 3

FR7, FR8:

VSOUT_EN:

CLK_ON:

Adjust f_RF

Set VSOUT_EN = 1

Don't care

Idle Mode

Write Control Register 2

FR0 to FR6:

P_mode:

Adjust f_RF

Enable or disable the

Manchester modulator

Write Control Register 1

IR1, IR0:

Select an event which activates

an interrupt

AVCC_EN:

FS:

OPM1, OPM0:

T_mode:

Don't care

Select operation frequency

Set OPM1 = 0 and OPM0 = 1

Set T_mode = 0

Start-up

Mode (TX)

T_Startup= 331.5 x T_DCLK

Write TX/RX Data Buffer (max. 16 byte)

N

Pin IRQ = 1 ?

Y

TX more Data

Bytes ?

Y

TX Mode

Write TX/RX Data Buffer (max. 16 - number of bytes still

in the TX/RX Data Buffer)

Command: Delete_IRQ

N

Pin IRQ = 1 ?

Y

Write Control Register 1

OPM1, OPM0:

Set IDLE

Idle Mode

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Figure 9-12. TX Transparent Mode (T_MODE = 1)

Write Control Register 4

XLim:

Don't care

ASK/_NFSK:

Sleep0 to Sleep4:

XSleep:

Select modulation

Don't care

Write Control Register 3

FR7, FR8:

VSOUT_EN:

CLK_ON:

Adjust f_RF

Set VSOUT_EN = 1

Don't care

Idle Mode

Write Control Register 2

FR0 to FR6:

P_mode:

Adjust f_RF

Don't care

Write Control Register 1

IR1, IR0:

AVCC_EN:

FS:

OPM1, OPM0:

T_mode:

Don't care

Select operation frequency

Set OPM1 = 0 and OPM0 = 1

Set T_mode = 1

Start-up

Mode (TX)

T_Startup= 331.5 x T_DCLK

Apply TX Data on Pin SDI_TMDI

TX Mode

Write Control Register 1

OPM1, OPM0:

Set IDLE (OPM1 = 0, OPM0 = 1

Idle Mode

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Table 9-5. TX Modulation Schemes

Bit in TX/RX

Data Buffer

Level on Pin

SDI_TMDI

Mode

ASK/_NFSK

P_Mode

T_Mode

RF_OUT

0

1

X

0

1

X

0

1

0

1

0

1

0

X

1

0

1

0

X

1

f

_{FSK_L}→ f_{FSK_H}

f

_{FSK_H}→ f_{FSK_L}

f_{FSK_H}

0

f_{FSK_L}

f_{FSK_H}

0

f_{FSK_L}

TX

X

1

f_ASKoff → f_ASKon

f_ASKon → f_ASKoff

f_ASKon

1

f_ASKoff

f_ASKon

0

f_ASKoff

9.3

Interrupts

Via pin IRQ, the transceiver signals different operating conditions to a connected microcontroller. If a specific operating

condition occurs, pin IRQ is set to high.

If an interrupt occurs, it is recommended to delete the interrupt immediately by reading the status register, so that a further

potential interrupt doesn’t get lost. If the Interrupt pin doesn’t switch to low by reading the status register, the interrupt was

triggered by the RX/TX data buffer. In this case read or write the RX/TX data buffer according to Table 9-6.

Table 9-6. Interrupt Handling

Operating Conditions Which Set Pin IRQ to High Level

Events in Status Register

Operations Which Set Pin IRQ to Low Level

State transition of status bit STn

(0 →1; 1 →0)

Appearance of status bit Power_On

(0 →1)

Read status register or

Command Delete IRQ

Appearance of status bit P_On_Aux

(0 →1)

Events During TX Operation (T_MODE = 0)

Write TX data buffer or

Write control register 1 or

Write control register 4 or

Write control register 5 or

Write control register 6 or

Command delete IRQ

4, 8 or 12 Bytes are in the TX data buffer or the TX data buffer

is empty (depends on IR0 and IR1 in control register 1).

Events During RX Operation (T_MODE = 0)

4, 8 or 12 received bytes are in the RX data buffer or a

receiving error is occurred (depends on IR0 and IR1 in control

register 1).

Read RX data buffer⁽¹⁾or

Write control register 1 or

Write control register 4 or

Write control register 5 or

Write control register 6 or

Command delete IRQ

Successful bit check (P_MODE = 0)

Note:

1. During reading of the RX/TX buffer, no IRQ is issued, due to the received bytes or a receiving error.

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10. Absolute Maximum Ratings

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating

only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Parameters

Symbol

T_j

Min.

Max.

150

Unit

°C

V

Junction temperature

Storage temperature

Ambient temperature

Supply voltage VS2

Supply voltage VS1

Supply voltage VAUX

Supply voltage VSINT

T_stg

–55

–40

+125

+85

+7.2

+4

T_amb

V_MaxVS2

V_MaxVS1

V_MaxVAUX

V_MaxVSINT

–0.3

V

+7.2

+5.5

V

ESD (Human Body Model ESD S 5.1)

every pin

HBM

MM

–1.5

+ 1.5

+200

kV

V

ESD (Machine Model JEDEC A115A)

every pin

–200

ESD (Field Induced Charge Device Model ESD

STM 5.3.1–1999)

every pin

FCDM

P_{in_max}

–1

+1

10

kV

Maximum input level, input matched to 50 Ω

dBm

11. Thermal Resistance

Parameters

Symbol

Value

Unit

Junction ambient

R_thJA

25

K/W

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12. Electrical Characteristics: General

This device is manufactured with an industrial (not automotive) grade process and process controls. Although this device may meet

certain automotive grade criteria in performance, Atmel can not recommend that this device be used in any automotive application.

All parameters refer to GND and are valid for T_amb= 25°C, V_VS1= V_VS2= 3.0V (1-battery application), V_VS2= 6.0V (2-battery

application) and V_VS2= V_VAUX= 5.0V (Base-station Application). Typical values are given at f_RF= 433.92 MHz unless otherwise

specified. Details about current consumption, timing and digital pin properties can be found in the specific sections of the “Electrical

Characteristics”.

No. Parameters

Test Conditions

Pin⁽¹⁾

Symbol

Min.

Typ.

Max.

Unit

Type*

1

RtX_TX_IDLE Mode

ATA5428

V_{433_N868}= AVCC

4, 10

f_RF

431.5

862

436.5

872

MHz

A

RF operating frequency

range

1.1

ATA5428

V_{433_N868}= GND

V_VS1= V_VS2= 3V,

V_VSINT= 0V

(1 battery) and

V_VS2= 6V (2 battery)

OFF mode is not

available if

V_VS2= V_VAUX= 5V

V_VSINT= 0V (base

station)

Supply current

OFF mode

1.2

I_{S_OFF}

< 10

220

nA

A

V_VSOUTdisabled,

XTO running

V_VS1= V_VS2= 3V

(1 battery)

I_{S_IDLE}

µA

B

Supply current

IDLE mode

1.3

V_VS2= 6V (2 battery)

I_{S_IDLE}

310

µA

B

V_VS2= V_VAUX= 5V

(base station)

From OFF mode to

IDLE mode including

reset and XTO start-up

(see Figure 7-4 on page

39)

1.4 System start-up time

T_{PWR_ON_IRQ_1}

0.3

ms

C

XTAL: C_m= 5fF,

C₀= 1.8pF, R_m=15Ω

From IDLE mode to

receiving mode

N

_Bit-check= 3

Bit rate = 20Kbit/s,

BR_Range_3

(see Figure 9-1 on page

46, Figure 9-2 on page

47 and Figure 9-3 on

page 48)

T_{Startup_PLL}

T_{Startup_Sig_Proc}

+ T_Bit-chek

+

1.5 RX start-up time

1.6 TX start-up time

1.39

0.4

ms

A

From IDLE mode to TX

mode (see Figure 9-11

on page 54)

T_Startup

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note:

1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 3-1 on page 11

with component values according to Table 3-2 on page 11 and RF_OUT matched to 50Ω according to Figure 3-10 on

page 18 with component values according to Table 3-7 on page 19.

58

ATA5428 [DATASHEET]

4841G–WIRE–03/14

12. Electrical Characteristics: General (Continued)

This device is manufactured with an industrial (not automotive) grade process and process controls. Although this device may meet

certain automotive grade criteria in performance, Atmel can not recommend that this device be used in any automotive application.

All parameters refer to GND and are valid for T_amb= 25°C, V_VS1= V_VS2= 3.0V (1-battery application), V_VS2= 6.0V (2-battery

application) and V_VS2= V_VAUX= 5.0V (Base-station Application). Typical values are given at f_RF= 433.92 MHz unless otherwise

specified. Details about current consumption, timing and digital pin properties can be found in the specific sections of the “Electrical

Characteristics”.

No. Parameters

Test Conditions

Pin⁽¹⁾

Symbol

Min.

Typ.

Max.

Unit

Type*

2

Receiver/RX Mode

f_RF= 433.92MHz

f_RF= 868MHz

17, 18

I_{S_RX}

10.5

10.3

mA

A

Supply current RX

mode

2.1

T_Sleep= 49.45ms

Supply current

RX polling mode

X_SLEEP= 8, Sleep = 5

Bit rate = 20Kbit/s FSK,

V_VSOUTdisabled

2.2

2.3

17, 18

I_P

444

µA

B

FSK deviation

f

_DEV= ±16kHz

limits according to

Table 9-3 on page 53,

BER = 10^-3

Input sensitivity FSK

f_RF= 433.92MHz

T_amb= 25°C

Bit rate 20Kbit/s

Bit rate 2.4bit/s

(4)

P_{REF_FSK}

–104.0

–107.5

–106.0

–109.5

–107.5

–111.0

dBm

B

ASK 100%, level of

carrier limits according

to Table 9-3 on page 53,

BER = 10^-3

Input sensitivity ASK

f_RF= 433.92MHz

2.4

2.5

T_amb= 25°C

Bit rate 10Kbit/s

Bit rate 2.4Kbit/s

(4)

P_{REF_ASK}

–110.5

–114.5

–112.5

–116.5

–114.0

–118.0

dBm

B

f_RF= 433.92 MHz

to f_RF= 868.3 MHz

Sensitivity change at

f_RF= 868.3MHz

P = P_{REF_ASK}+ ΔP_REF1

ΔP_REF2

+

(4)

ΔP_REF1

+2.7

dB

B

compared to

f_RF= 433.92MHz

P = P_{REF_FSK}+ ΔP_REF1

ΔP_REF2

Maximum frequency

difference of f_RF

between receiver and

Maximum frequency

offset in FSK mode

transmitter in FSK mode

(f_RFis the center

frequency of the FSK

signal with

2.6

(4)

Δf_OFFSET

–58

+58

kHz

B

f_DEV= ±16kHz)

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note:

1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 3-1 on page 11

with component values according to Table 3-2 on page 11 and RF_OUT matched to 50Ω according to Figure 3-10 on

page 18 with component values according to Table 3-7 on page 19.

ATA5428 [DATASHEET]

59

4841G–WIRE–03/14

12. Electrical Characteristics: General (Continued)

This device is manufactured with an industrial (not automotive) grade process and process controls. Although this device may meet

certain automotive grade criteria in performance, Atmel can not recommend that this device be used in any automotive application.

All parameters refer to GND and are valid for T_amb= 25°C, V_VS1= V_VS2= 3.0V (1-battery application), V_VS2= 6.0V (2-battery

application) and V_VS2= V_VAUX= 5.0V (Base-station Application). Typical values are given at f_RF= 433.92 MHz unless otherwise

specified. Details about current consumption, timing and digital pin properties can be found in the specific sections of the “Electrical

Characteristics”.

No. Parameters

Test Conditions

Pin⁽¹⁾

Symbol

Min.

Typ.

Max.

Unit

Type*

With up to 2dB

loss of sensitivity.

Note that the tolerable

frequency offset is for

f_DEV= ±22kHz, 6kHz

lower than for

Supported FSK

2.7

(4)

f_DEV

±14

±16

±22

kHz

B

frequency deviation

f_DEV= ±16kHz hence

Δf_OFFSET≤ ±52kHz

f_RF= 433.92MHz

f_RF= 868.3MHz

f_RF= 433.92MHz

f_RF= 868.3MHz

(4)

NF

f_IF

7.0

9.7

dB

B

A

2.8 System noise figure

223

226

kHz

2.9 Intermediate frequency

f_IF

This value is for

information only!

Note that for crystal and

system frequency offset

calculations, Δf_OFFSET

must be used.

2.10 System bandwidth

System outband

(4)

SBW

IIP2

185

+50

kHz

A

C

Δf_meas1= 1,800MHz

Δf_meas2= 2,026MHz

f_IF= Δf_meas2– Δf_meas1

2nd-order input

intercept point with

2.11

dBm

respect to f_IF

Δf_meas1= 1.8MHz

Δf_meas2= 3.6MHz

f_RF= 433.92MHz

System outband

2.12 3rd-order input intercept

point

(4)

IIP3

–21

–17

dBm

C

f_RF= 868.3MHz

Δf_meas1= 1MHz

f_RF= 433.92MHz

(4)

I1dBCP

–30

dBm

C

System outband input

2.13

1dB compression point

f_RF= 868.3MHz

f_RF= 433.92MHz

f_RF= 868.3MHz

(4)

4

I1dBCP

Z_{in_LNA}

–27

dBm

Ω

C

(32 – j169)

(21 – j78)

2.14 LNA input impedance

4

Ω

BER < 10^-3,

ASK: 100%

(4)

P_{IN_max}

+10

–10

dBm

C

Allowable peak RF input

2.15

level, ASK and FSK

FSK: f_DEV= ±16kHz

f < 1GHz

(4)

–10

–57

–47

dBm

C

f >1GHz

LO spurious emission at

2.16

LNA_IN

f_RF= 433.92MHz

f_RF= 868.3MHz

–97

–84

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note:

1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 3-1 on page 11

with component values according to Table 3-2 on page 11 and RF_OUT matched to 50Ω according to Figure 3-10 on

page 18 with component values according to Table 3-7 on page 19.

60

ATA5428 [DATASHEET]

4841G–WIRE–03/14

12. Electrical Characteristics: General (Continued)

This device is manufactured with an industrial (not automotive) grade process and process controls. Although this device may meet

certain automotive grade criteria in performance, Atmel can not recommend that this device be used in any automotive application.

All parameters refer to GND and are valid for T_amb= 25°C, V_VS1= V_VS2= 3.0V (1-battery application), V_VS2= 6.0V (2-battery

application) and V_VS2= V_VAUX= 5.0V (Base-station Application). Typical values are given at f_RF= 433.92 MHz unless otherwise

specified. Details about current consumption, timing and digital pin properties can be found in the specific sections of the “Electrical

Characteristics”.

No. Parameters

Test Conditions

Pin⁽¹⁾

Symbol

Min.

Typ.

Max.

Unit

Type*

Within the complete

image band

2.17 Image rejection

(4)

20

30

dB

A

Peak level of useful

signal to peak level of

interferer for

BER < 10^-3with any

modulation scheme of

interferer

Useful signal to

2.18

interfering signal ratio

FSK BR_Ranges 0, 1, 2

FSK BR_Range_3

(4)

SNR_FSK0-2

SNR_FSK3

SNR_ASK

D_RSSI

2

4

3

6

dB

B

A

ASK (P_RF< P_{RFIN_High}

)

(4)

10

70

12

Dynamic range

(4), 36

Lower level of range

f_RF= 433.92MHz

f_RF= 868.3MHz

(4), 36

P_{RFIN_Low}

–115

–112

dBm

A

2.19 RSSI output

Upper level of range

f_RF= 433.92 MHz

f_RF= 868.3 MHz

P_{RFIN_High}

–45

–42

dBm

Gain

(4), 36

5.5

8.0

10.5

mV/dB

mV

A

Output voltage range

OV_RSSI

R_RSSI

400

1100

Output resistance RSSI RX mode

8

32

10

40

12.5

50

2.20

36

kΩ

C

TX mode

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note: 1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 3-1 on page 11

with component values according to Table 3-2 on page 11 and RF_OUT matched to 50Ω according to Figure 3-10 on

page 18 with component values according to Table 3-7 on page 19.

ATA5428 [DATASHEET]

61

4841G–WIRE–03/14

12. Electrical Characteristics: General (Continued)

This device is manufactured with an industrial (not automotive) grade process and process controls. Although this device may meet

certain automotive grade criteria in performance, Atmel can not recommend that this device be used in any automotive application.

All parameters refer to GND and are valid for T_amb= 25°C, V_VS1= V_VS2= 3.0V (1-battery application), V_VS2= 6.0V (2-battery

application) and V_VS2= V_VAUX= 5.0V (Base-station Application). Typical values are given at f_RF= 433.92 MHz unless otherwise

specified. Details about current consumption, timing and digital pin properties can be found in the specific sections of the “Electrical

Characteristics”.

No. Parameters

Test Conditions

Pin⁽¹⁾

Symbol

Min.

Typ.

Max.

Unit

Type*

Sensitivity (BER = 10^–3)

is reduced by 6dB if a

continuous wave

blocking signal at ±Δf is

ΔP_Blockhigher than the

useful signal level

(bit rate = 20 bit/s,

FSK, f_DEV±16kHz,

Manchester code)

f_RF= 433.92MHz

Δf ±0.75MHz

Δf ±1.0MHz

Δf ±1.5MHz

Δf ±5MHz

2.21 Blocking

55

59

62

68

70

(4)

ΔP_Block

dBC

C

Δf ±10MHz

f_RF= 868.3MHz

Δf ±0.75MHz

Δf ±1.0MHz

Δf ±1.5MHz

Δf ±5MHz

50

53

57

67

69

(4)

37

ΔP_Block

dBC

nF

C

D

Δf ±10MHz

Capacitor connected to

pin 37 (CDEM)

2.22 CDEM

–5%

15

+5%

3

Power Amplifier/TX Mode

f_RF= 868.3MHz

f_RF= 433.92MHz

I_{S_TX_PAOFF}

6.50

6.95

mA

A

Supply current TX mode

power amplifier OFF

3.1

V_VS1= V_VS2= 3V

T_amb= 25°C

V_{PWR_H}= 0V

f_RF= 433.92MHz

R_{R_PWR}= 56kΩ

R_Lopt= 2.3kΩ

3.2 Output power 1

(10)

P_REF1

–2.5

0

+2.5

dBm

B

f_RF= 868.3MHz

R_{R_PWR}= 30kΩ

R_Lopt= 1.3kΩ

RF_OUT matched to

R_Lopt//

j/(2 × π × f_RF× 1.0pF)

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note:

1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 3-1 on page 11

with component values according to Table 3-2 on page 11 and RF_OUT matched to 50Ω according to Figure 3-10 on

page 18 with component values according to Table 3-7 on page 19.

62

ATA5428 [DATASHEET]

4841G–WIRE–03/14

12. Electrical Characteristics: General (Continued)

This device is manufactured with an industrial (not automotive) grade process and process controls. Although this device may meet

certain automotive grade criteria in performance, Atmel can not recommend that this device be used in any automotive application.

All parameters refer to GND and are valid for T_amb= 25°C, V_VS1= V_VS2= 3.0V (1-battery application), V_VS2= 6.0V (2-battery

application) and V_VS2= V_VAUX= 5.0V (Base-station Application). Typical values are given at f_RF= 433.92 MHz unless otherwise

specified. Details about current consumption, timing and digital pin properties can be found in the specific sections of the “Electrical

Characteristics”.

No. Parameters

Test Conditions

PA on/0 dBm

Pin⁽¹⁾

Symbol

Min.

Typ.

Max.

Unit

Type*

Supply current TX mode

3.3

f_RF= 433.92 MHz

f_RF= 868.3 MHz

V_VS1= V_VS2= 3V

17, 18

I_{S_TX_PAON1}

8.6

9.6

mA

B

power amplifier ON 1

T_amb= 25°C

V_{PWR_H}= 0V

f_RF= 433.92MHz

R_{R_PWR}= 27kΩ

R_Lopt= 1.1kΩ

3.4 Output power 2

(10)

P_REF2

3.5

5.0

6.5

dBm

B

f_RF= 868.3MHz

R_{R_PWR}= 16kΩ

R_Lopt= 0.5kΩ

RF_OUT matched to

R_Lopt//

j/(2 × π × f_RF× 1.0pF)

PA on/5 dBm

Supply current TX mode

3.5

f_RF= 433.92MHz

f_RF= 868.3MHz

17, 18

I_{S_TX_PAON2}

10.5

11.2

mA

B

power amplifier ON 2

V_VS1= V_VS2= 3V

T_amb= 25°C

V_{PWR_H}= AVCC

f_RF= 433.92MHz

R_{R_PWR}= 27kΩ

R_Lopt= 0.36kΩ

3.6 Output power 3

(10)

P_REF3

8.5

10

11.5

dBm

B

f_RF= 868.3MHz

R_{R_PWR}= 20kΩ

R_Lopt= 0.22kΩ

RF_OUT matched to

R_Lopt//

j/(2 × π × f_RF× 1.0pF)

PA on/10dBm

Supply current TX mode

3.7

f_RF= 433.92MHz

f_RF= 868.3MHz

17, 18

I_{S_TX_PAON3}

15.8

17.3

mA

B

power amplifier ON 3

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note:

1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 3-1 on page 11

with component values according to Table 3-2 on page 11 and RF_OUT matched to 50Ω according to Figure 3-10 on

page 18 with component values according to Table 3-7 on page 19.

ATA5428 [DATASHEET]

63

4841G–WIRE–03/14

12. Electrical Characteristics: General (Continued)

This device is manufactured with an industrial (not automotive) grade process and process controls. Although this device may meet

certain automotive grade criteria in performance, Atmel can not recommend that this device be used in any automotive application.

All parameters refer to GND and are valid for T_amb= 25°C, V_VS1= V_VS2= 3.0V (1-battery application), V_VS2= 6.0V (2-battery

application) and V_VS2= V_VAUX= 5.0V (Base-station Application). Typical values are given at f_RF= 433.92 MHz unless otherwise

specified. Details about current consumption, timing and digital pin properties can be found in the specific sections of the “Electrical

Characteristics”.

No. Parameters

Test Conditions

Pin⁽¹⁾

Symbol

Min.

Typ.

Max.

Unit

Type*

T_amb= –40°C to +85°C

P_out= P_REFX+ ΔP_REFX

X = 1, 2 or 3

(10)

ΔP_REF

–0.8

–1.5

dB

B

Output power variation

3.8 for full temperature and

supply voltage range

V_VS1= V_VS2= 3.0V

V_VS1= V_VS2= 2.7V

V_VS1= V_VS2= 2.4V

f_RF= 433.92MHz

f_RF= 868.3MHz

(10)

10

ΔP_REF

–2.5

–3.5

dB

Ω

B

C

Z_{RF_OUT_RX}

(19 – j366)

(2.8 – j141)

Impedance RF_OUT in

RX mode

3.9

10

Ω

at ±10MHz/at 5dBm

f_RF= 433.92MHz

f_RF= 868.3MHz

Noise floor power

amplifier

3.10

(10)

L_TX10M

–126

–125

dBC/Hz

C

This corresponds to

10Kbit/s Manchester

coding and 20Kbit/s

NRZ coding

3.11 ASK modulation rate

f_{Data_ASK}

1

10

kHz

C

4

XTO

Pulling at nominal

temperature and supply

voltage

f_XTAL= resonant

frequency of the XTAL

C₀≥ 1.0pF

Pulling XTO due to

4.1 XTO, C_L1and C_L2

tolerances

24, 25

A

R_m≤ 120Ω

C_m≤ 7.0fF

C_m≤ 14fF

–50

–100

+50

+100

Δf_XTO1

f_XTAL

ppm

ms

At start-up; after

start-up the amplitude is 24, 25

regulated to V_PPXTAL

Transconductance XTO

at start

4.2

g_{m, XTO}

19

B

A

C₀≤ 2.2pF

C_m< 14fF

4.3 XTO start-up time

24, 25 T_{PWR_ON_IRQ_1}

300

800

µs

R_m≤ 120Ω

Required for stable

operation with internal

load capacitors

4.4 Maximum C₀of XTAL

4.5 Internal capacitors

24, 25

C_0max

3.8

pF

D

B

C_L1and C_L2

C_L1, C_L2

14.8

18

21.2

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note: 1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 3-1 on page 11

with component values according to Table 3-2 on page 11 and RF_OUT matched to 50Ω according to Figure 3-10 on

page 18 with component values according to Table 3-7 on page 19.

64

ATA5428 [DATASHEET]

4841G–WIRE–03/14

12. Electrical Characteristics: General (Continued)

This device is manufactured with an industrial (not automotive) grade process and process controls. Although this device may meet

certain automotive grade criteria in performance, Atmel can not recommend that this device be used in any automotive application.

All parameters refer to GND and are valid for T_amb= 25°C, V_VS1= V_VS2= 3.0V (1-battery application), V_VS2= 6.0V (2-battery

application) and V_VS2= V_VAUX= 5.0V (Base-station Application). Typical values are given at f_RF= 433.92 MHz unless otherwise

specified. Details about current consumption, timing and digital pin properties can be found in the specific sections of the “Electrical

Characteristics”.

No. Parameters

Test Conditions

Pin⁽¹⁾

Symbol

Min.

Typ.

Max.

Unit

Type*

1.0pF ≤ C₀≤ 2.2pF

Pulling of radio

C

R

_m≤ 14.0fF

_m≤120Ω

frequency f_RFdue to

4.6 XTO, C_L1and C_L2

versus temperature and FREQ at nominal

PLL adjusted with

4, 10

Δf_XTO2

–2

+2

ppm

C

supply changes

temperature and supply

voltage

C_m= 5fF, C₀= 1.8pF

R_m=15Ω

Amplitude XTAL after

start-up

V(XTAL1, XTAL2)

peak-to-peak value

4.7

4.8

24, 25

V_PPXTAL

700

350

mVpp

C

V(XTAL1)

peak-to-peak value

C₀≤ 2.2pF, small signal

start impedance, this

Real part of XTO

impedance at start-up value is important for

crystal oscillator startup

24, 25

Re_XTO

–2,000

15

–1,500

120

Ω

B

Maximum series

4.9 resistance R_mof XTAL

after start-up

C₀≤ 2.2pF

C_m≤ 14fFΩ

24, 25

R_{m_max}

Ω

B

D

MHz

Nominal XTAL load

4.10

f_RF= 433.92MHz

f_RF= 868.3MHz

113.25311

13.41191

f_XTAL

resonant frequency

f_RF= 433.92MHz

CLK division ratio = 3

CLK has nominal 50%

duty cycle

30

f_CLK

4.418

4.471

–30

MHz

mV

D

C

4.11 External CLK frequency

f_RF= 868.3MHz

CLK division ratio = 3

CLK has nominal 50%

duty cycle

f_CLK

V_DC(XTAL1, XTAL2)

XTO running

(IDLE mode, RX mode

and TX mode)

DC voltage after

4.12

24, 25

V_DCXTO

–150

start-up

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note: 1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 3-1 on page 11

with component values according to Table 3-2 on page 11 and RF_OUT matched to 50Ω according to Figure 3-10 on

page 18 with component values according to Table 3-7 on page 19.

ATA5428 [DATASHEET]

65

4841G–WIRE–03/14

12. Electrical Characteristics: General (Continued)

This device is manufactured with an industrial (not automotive) grade process and process controls. Although this device may meet

certain automotive grade criteria in performance, Atmel can not recommend that this device be used in any automotive application.

All parameters refer to GND and are valid for T_amb= 25°C, V_VS1= V_VS2= 3.0V (1-battery application), V_VS2= 6.0V (2-battery

application) and V_VS2= V_VAUX= 5.0V (Base-station Application). Typical values are given at f_RF= 433.92 MHz unless otherwise

specified. Details about current consumption, timing and digital pin properties can be found in the specific sections of the “Electrical

Characteristics”.

No. Parameters

Synthesizer

Test Conditions

Pin⁽¹⁾

Symbol

Min.

Typ.

Max.

Unit

Type*

5

At ±f_CLK, CLK enabled

f_RF= 433.92MHz

f_RF= 868.3MHz

SP_TX

SP_RX

–68

–70

dBC

C

5.1 Spurious TX mode

5.2 Spurious RX mode

At ±f_XTO

f_RF= 433.92MHz

–66

–60

f

_RF= 868.3MHz

At ±f_CLK, CLK enabled

f_RF= 433.92MHz

f_RF= 868.3MHz

< –75

At ±f_XTO

f_RF= 433.92MHz

f_RF= 868.3MHz

–75

–68

Measured at 20kHz

distance to carrier

f_RF= 433.92MHz

f_RF= 868.3MHz

In loop phase noise

TX mode

5.3

L_TX20k

dBC/Hz

A

–80

–75

Phase noise at 1M

RX mode

f_RF= 433.92MHz

f_RF= 868.3MHz

–120

–113

5.4

L_RX1M

L_TX1M

dBC/Hz

C

Phase noise at 1M

TX mode

f_RF= 433.92MHz

f_RF= 868.3MHz

–111

–107

5.5

Phase noise at 10M

RX mode

5.6

Noise floor PLL

L_RX10M

–135

Frequency where the

absolute value loop gain

is equal to 1

Loop bandwidth PLL

TX mode

5.7

f_{Loop_PLL}

70

kHz

B

Frequency deviation

TX mode

f_RF= 433.92MHz

f_RF= 868.3MHz

±16.17

±16.37

5.8

f_{DEV_TX}

kHz

Hz

D

f_RF= 433.92MHz

f_RF= 868.3MHz

808.9

818.6

5.9 Frequency resolution

5.10 FSK modulation rate

4, 10

Δf_{Step_PLL}

This correspond to

20Kbit/s Manchester

coding and 40Kbit/s

NRZ coding

f_{Data_FSK}

1

20

kHz

B

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note: 1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 3-1 on page 11

with component values according to Table 3-2 on page 11 and RF_OUT matched to 50Ω according to Figure 3-10 on

page 18 with component values according to Table 3-7 on page 19.

66

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12. Electrical Characteristics: General (Continued)

This device is manufactured with an industrial (not automotive) grade process and process controls. Although this device may meet

certain automotive grade criteria in performance, Atmel can not recommend that this device be used in any automotive application.

All parameters refer to GND and are valid for T_amb= 25°C, V_VS1= V_VS2= 3.0V (1-battery application), V_VS2= 6.0V (2-battery

application) and V_VS2= V_VAUX= 5.0V (Base-station Application). Typical values are given at f_RF= 433.92 MHz unless otherwise

specified. Details about current consumption, timing and digital pin properties can be found in the specific sections of the “Electrical

Characteristics”.

No. Parameters

RX/TX Switch

Test Conditions

Pin⁽¹⁾

Symbol

Min.

Typ.

Max.

Unit

Type*

6

RX mode, pin 38 with

short connection to

GND, f_RF= 0Hz (DC)

39

Z_{Switch_RX}

Z_{Switch_TX}

Z_{Switch_RX}

23000

Ω

A

C

A

C

6.1 Impedance RX mode

6.2 Impedance TX mode

f_RF= 433.92MHz

f_RF= 868.3MHz

(10.3 – j153)

(8.9 – j73)

TX mode, pin 38 with

short connection to

GND, f_RF= 0Hz (DC)

5

f_RF= 433.92MHz

f_RF= 868.3MHz

(4.5 + j4.3)

(5 + j9)

7

Microcontroller Interface

I_VSINT< 10µA if CLK is 27, 28,

disabled and all

interface pins are in

stable condition and

unloaded

29, 30,

31, 32,

33, 34,

35

Voltage range for

microcontroller interface

7.1

2.4

5.25

V

A

B

f_CLK< 4.5MHz

C_L= 10pF

CLK output rise and fall C_L= Load capacitance

t_rise

t_fall

20

30

ns

7.2

30

time

on pin CLK

2.4V ≤ V_VSINT≤ 5.25V

20% to 80% V_VSINT

CLK enabled

V_VSOUTenabled

(C_CLK+ C_L) × V_VSINT× f_XTO

I_VSINT= ----------------------------------------------------------------------------

3

CLK disabled

V_VSOUTenabled

< 10µA

Current consumption of

V_VSOUTdisabled

7.4 the microcontroller

interface

27

I_VSINT

C_L= Load capacitance

on pin CLK

(All interface pins,

except pin CLK, are in

stable condition and

unloaded)

Internal equivalent

7.5

Used for current

calculation

30, 27

C_CLK

8

pF

B

capacitance

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note:

1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 3-1 on page 11

with component values according to Table 3-2 on page 11 and RF_OUT matched to 50Ω according to Figure 3-10 on

page 18 with component values according to Table 3-7 on page 19.

ATA5428 [DATASHEET]

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12. Electrical Characteristics: General (Continued)

This device is manufactured with an industrial (not automotive) grade process and process controls. Although this device may meet

certain automotive grade criteria in performance, Atmel can not recommend that this device be used in any automotive application.

All parameters refer to GND and are valid for T_amb= 25°C, V_VS1= V_VS2= 3.0V (1-battery application), V_VS2= 6.0V (2-battery

application) and V_VS2= V_VAUX= 5.0V (Base-station Application). Typical values are given at f_RF= 433.92 MHz unless otherwise

specified. Details about current consumption, timing and digital pin properties can be found in the specific sections of the “Electrical

Characteristics”.

No. Parameters

Test Conditions

Pin⁽¹⁾

Symbol

Min.

Typ.

Max.

Unit

Type*

8

Power Supply General Definitions and AUX Mode

I_VSINT

VSINT

I_EXT= I_VSOUT– I_VSINT

VSOUT

Current consumption of

an external device

connected to pin

VSOUT

I_VSOUTI_EXT

8.1

I_EXT

I_VSINT

I_EXT= I_VSOUT

VSINT

VSOUT

I_EXT= I_VSOUT

VAUX

I_{AUX_VAUX}

8.2 AUX mode

AUX mode

V_VAUX≥ 4V

Power supply output

voltage

I_VSOUT≤ 13.5mA

(3.25V regulator mode,

V_REG2, see

8.3

8.4

22

19

V_VSOUT

2.7

3.5

V

A

B

Figure 5-1 on page 25)

I_VSOUT= 0

V_VAUX= 6V

V_VAUX= 4V to 7V

Current in AUX mode on

pin VAUX

I_{AUX_VAUX}

380

500

µA

CLK enabled

V

_VSOUTenabled

I_{S_AUX}= I_{AUX_VAUX}+ I_VSINT+ I_EXT

I_{S_AUX}= I_{AUX_VAUX}+ I_EXT

Supply current

AUX mode

19, 22,

27

8.5

8.6

I_{S_AUX}

CLK disabled

V_VSOUTenabled

Supported voltage

range VAUX

19

V_VAUX

4

6

7

V

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note:

1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 3-1 on page 11

with component values according to Table 3-2 on page 11 and RF_OUT matched to 50Ω according to Figure 3-10 on

page 18 with component values according to Table 3-7 on page 19.

68

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13. Electrical Characteristics: 1 Li Battery Application (3V)

All parameters refer to GND and are valid for T_amb= 25°C, V_VS1= V_VS2= 3.0V. Application according to Figure 2-1 on page 7.

f_RF= 433.92MHz/868.3MHz unless otherwise specified

No. Parameters

Test Conditions

Symbol

Min.

Typ.

Max.

Unit

Type*

VS1

VS2

I_{IDLE_VS1,2}

9

1 Li Battery Application (3V)

or I_{RX_VS2,2}

or I_{Startup_PLL_VS1,2}

or

I_{TX_VS1,2}

Supported voltage

range (every mode

except high power TX

mode)

1 Li battery application

(3V)

PWR_H = GND

9.1

17, 18

V_VS1, V_VS2

2.4

2.7

3.6

V

A

Supported voltage

9.2 range (high power TX (3V)

1 Li battery application

V_VS1, V_VS2

mode)

PWR_H = AVCC

1 Li battery application

(3V)

V_VS1= V_VS2≥ 2.6V

VAUX open⁽¹⁾

I_VSOUT≤ 13.5mA

(no voltage regulator to

Power supply output

voltage

9.3

22

V_VSOUT

2.4

V_VS1

V

B

stabilize V_VSOUT

)

V_VS1= V_VS2≥ 2.425V

VAUX open⁽¹⁾

I_VSOUT≤ 1.5mA

(no voltage regulator to

stabilize V_VSOUT

)

Supply voltage for

9.4 microcontroller

interface

27

22

V_VSINT

ΔV_Thres

V_{Thres_1}

2.4

60

5.25

100

V

mV

V

A

B

A

9.5 Threshold hysteresis

V_{Thres_2}– V_{Thres_1}

80

Reset threshold voltage

9.6 at pin VSOUT

(N_RESET)

2.18

2.3

2.42

Reset threshold voltage

9.7 at pin VSOUT

(Low_Batt)

22

V_{Thres_2}

2.26

2.38

2

2.5

V

A

Supply current

9.8

V_VS1= V_VS2≤ 3.6V

V_VSINT= 0V

17, 18,

22, 27

I_{S_OFF}

350

nA

OFF mode

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note: 1. The voltage of VAUX may rise up to 2V. The current I_VAUXmay not exceed 100µA.

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13. Electrical Characteristics: 1 Li Battery Application (3V) (Continued)

All parameters refer to GND and are valid for T_amb= 25°C, V_VS1= V_VS2= 3.0V. Application according to Figure 2-1 on page 7.

f_RF= 433.92MHz/868.3MHz unless otherwise specified

No. Parameters

Test Conditions

Symbol

Min.

Typ.

Max.

Unit

Type*

V_VS1= V_VS2≤ 3V

I_VSOUT= 0

CLK enabled

312

260

225

430

370

320

µA

A

B

Current in IDLE mode V_VSOUTenabled

on pin VS1 and VS2

CLK disabled

9.9

17, 18

I_{IDLE_VS1, 2}

V_VSOUTenabled

V_VSOUTdisabled

Supply current

IDLE mode

17, 18,

22, 27

9.10

9.11

9.12

I_{S_IDLE}

I_{RX_VS1, 2}

I_{S_RX}

I_{S_IDLE}= I_{IDLE_VS1, 2}+ I_VSINT+ I_EXT

10.5 14 mA

I_{S_RX}= I_{RX_VS1, 2}+ I_VSINT+ I_EXT

Current in RX mode on V_VS1= V_VS2≤ 3V

pin VS1and VS2

17, 18

A

I_VSOUT= 0

Supply current

RX mode

CLK enabled

V_VSOUTenabled

17, 18,

22, 27

Current during

9.13 T_{Startup_PLL}on pin VS1

and VS2

V_VS1= V_VS2≤ 3V

I_VSOUT= 0

17, 18 I_{Startup_PLL_VS1, 2}

8.8

11.5

mA

C

Current in

I_{IDLE_VS1,2}× T_SLEEP+ I_{Startup_PLL_VS1,2}× T_{Startup_PLL}+ I_{RX_VS1,2}× (T_{Startup_Sig_Proc}+ T_Bitcheck

)

9.14 RX polling mode on pin I_P= ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

T

_Sleep+ T_{Startup_PLL}+ T_{Startup_Sig_Proc}+ T_Bitcheck

VS1 and VS2

CLK enabled

V_VSOUTenabled

I_{S_Poll}= I_P+ I_VSINT+ I_EXT

Supply current

RX polling mode

17, 18,

22, 27

9.15

CLK disabled

V_VSOUTenabled

I_{S_Poll}

I_{S_Poll}= I_P+ I_EXT

I_{S_Poll}= I_P

V_VSOUTdisabled

V_VS1= V_VS2≤ 3V

I_VSOUT= 0

Pout = 5dBm/10dBm

10.4

15.8

13.5

20.6

Current in TX mode on

pin VS1 and VS2

9.16

9.17

433.92MHz/5dBm

433.92MHz/10dBm

17, 18

I_{TX_VS1_VS2}

mA

B

10.5

15.8

13.5

20.5

868.3MHz/5dBm

868.3MHz/10dBm

11.2

17.3

14.5

22.5

CLK enabled

V_VSOUTenabled

I_{S_TX}= I_{TX_VS1, 2}+ I_VSINT+ I_EXT

Supply current

TX mode

17, 18,

22, 27

I_{S_TX}

CLK disabled

V_VSOUTenabled

I_{S_TX}= I_{TX_VS1, 2}+ I_EXT

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note:

1. The voltage of VAUX may rise up to 2V. The current I_VAUXmay not exceed 100µA.

70

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14. Electrical Characteristics: 2 Li Battery Application (6V)

All parameters refer to GND and are valid for T_amb= 25°C, V_VS2= 6.0V. Application according to Figure 2-3 on page 9

f_RF= 433.92MHz/868.3MHz unless otherwise specified

No. Parameters

Test Conditions

Symbol

Min.

Typ.

Max.

Unit

Type*

VS2

I_{IDLE_VS2}

10

2 Li Battery Application (6V)

or I_{RX_VS2}

or I_{Startup_PLL_VS2}

or

I_{TX_VS2}

Supported voltage

range

2 Li battery application

(6V)

10.1

10.2

17

22

V_VS2

4.4

6.6

3.5

V

A

2 Li battery application

(6V)

V_VS2≥ 4.4V

Power supply output

voltage

VAUX open⁽¹⁾

V_VSOUT

3.0

I_VSOUT≤ 13.5mA

(3.3V regulator mode,

V_REG1, see Figure 5-

1 on page 25)

Supply voltage for

10.3 microcontroller

interface

27

22

V_VSINT

ΔV_Thres

V_{Thres_1}

2.4

60

5.25

100

V

mV

V

A

B

A

10.4 Threshold hysteresis

V_{Thres_2}– V_{Thres_1}

80

Reset threshold

10.5 voltage at pin VSOUT

(N_RESET)

2.18

2.3

2.42

Reset threshold

10.6 voltage at pin VSOUT

(Low_Batt)

22

V_{Thres_2}

2.26

2.38

10

2.5

V

A

Supply current

10.7

V_VS2≤ 6.6V

V_VSINT= 0V

17, 22,

27

I_{S_OFF}

350

nA

OFF mode

V_VS2≤ 6V

I_VSOUT= 0

CLK enabled

Current in IDLE mode V_VSOUTenabled

on pin VS2

410

560

µA

A

10.8

17

I_{IDLE_VS2}

CLK disabled

V_VSOUTenabled

348

309

490

430

µA

B

V_VSOUTdisabled

Supply current IDLE

mode

17, 22,

27

10.9

I_{S_IDLE}

I_{S_IDLE}= I_{IDLE_VS2}+ I_VSINT+ I_EXT

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note: 1. The voltage of VAUX may rise up to 2V. The current I_VAUXmay not exceed 100µA.

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14. Electrical Characteristics: 2 Li Battery Application (6V) (Continued)

All parameters refer to GND and are valid for T_amb= 25°C, V_VS2= 6.0V. Application according to Figure 2-3 on page 9

f_RF= 433.92MHz/868.3MHz unless otherwise specified

No. Parameters

Test Conditions

Symbol

Min.

Typ.

Max.

Unit

Type*

Current in RX mode on

pin VS2

10.10

10.11

10.12

I_VSOUT= 0

17

I_{RX_VS2}

10.8

14.5

mA

B

Supply current

RX mode

CLK enabled

V_VSOUTenabled

17, 22,

27

I_{S_RX}

I_{S_RX}= I_{RX_VS2}+ I_VSINT+ I_EXT

9.1 12 mA

Current during

T_{Startup_PLL}on pin VS2

I_VSOUT= 0

17

I_{Startup_PLL_VS2}

C

Current in

I_{IDLE_VS2}× T_SLEEP+ I_{Startup_PLL_VS2}× T_{Startup_PLL}+ I_{RX_VS2}× (T_{Startup_Sig_Proc}+ T_Bitcheck

)

10.13 RX polling mode on pin I_P= ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

T

_Sleep+ T_{Startup_PLL}+ T_{Startup_Sig_Proc}+ T_Bitcheck

VS2

CLK enabled

V_VSOUTenabled

I_{S_Poll}= I_P+ I_VSINT+ I_EXT

Supply current

RX polling mode

17, 22,

27

10.14

CLK disabled

V_VSOUTenabled

I_{S_Poll}

I_{S_Poll}= I_P+ I_EXT

I_{S_Poll}= I_P

V_VSOUTdisabled

I_VSOUT= 0

P_out= 5dBm/10dBm

Current in TX mode on 433.92MHz/5dBm

10.9

16.3

14.0

21.0

10.15

10.16

17, 19

I_{TX_VS2}

mA

B

pin VS2

433.92MHz/10dBm

868.3MHz/5dBm

868.3MHz/10dBm

11.6

17.8

15.0

23.0

CLK enabled

V_VSOUTenabled

I_{S_TX}= I_{TX_VS2}+ I_VSINT+ I_EXT

Supply current

TX mode

17, 22,

27

I_{S_TX}

CLK disabled

V_VSOUTenabled

I_{S_TX}= I_{TX_VS2}+ I_EXT

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note:

1. The voltage of VAUX may rise up to 2V. The current I_VAUXmay not exceed 100µA.

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15. Electrical Characteristics: Base-station Application (5V)

All parameters refer to GND and are valid for T_amb= 25°C, V_VS2= 5.0V. Application according to Figure 2.2 on page 8

f_RF= 433.92MHz/868.3MHz unless otherwise specified.

No. Parameters

Test Conditions

Symbol

Min.

Typ.

Max.

Unit

Type*

VAUX

VS2

I_{IDLE_VS2_VAUX}

11

Base-station Application (5V)

or I_{RX_VS2_VAUX}

or I_{Startup_PLL_VS2_VAUX}

or

I_{TX_VS2_VAUX}

Supported voltage

range

Base-station

application (5V)

17, 19,

27

11.1

11.2

V_VS2, V_AUX

4.75

5.25

V

A

Base-station

application (5V)

V_VS2= V_VAUX

I_VSOUT≤ 13.5mA

(3.25V regulator mode,

V_REG2, see

Power supply output

voltage

22

V_VSOUT

3.0

3.5

Figure 5-1 on page 25)

Supply voltage for

11.3 microcontroller-

interface

27

22

V_VSINT

ΔV_Thres

V_{Thres_1}

2.4

60

5.25

100

V

mV

V

A

B

A

11.4 Threshold hysteresis

V_{Thres_2}– V_{Thres_1}

80

Reset threshold voltage

11.5 at pin VSOUT

(N_RESET)

2.18

2.3

2.42

Reset threshold voltage

11.6 at pin VSOUT

(Low_Batt)

22

V_{Thres_2}

2.26

2.38

444

2.5

V

A

I_VSOUT= 0

CLK enabled

V_VSOUTenabled

580

Current in IDLE mode

11.7

17, 19

I_{IDLE_VS2_VAUX}

µA

B

on pin VS2 and VAUX CLK disabled

V_VSOUTenabled

380

310

500

400

V_VSOUTdisabled

Supply current in IDLE

mode

17, 19,

22, 27

11.8

11.9

I_{S_IDLE}

I_{RX_VS2_VAUX}

I_{S_RX}

I_{S_IDLE}= I_{IDLE_VS2_VAUX}+ I_VSINT+ I_EXT

10.8 14.5 mA

I_{S_RX}= I_{RX_VS2_VAUX}+ I_VSINT+ I_EXT

Current in RX mode on

I_VSOUT= 0

17, 19

B

C

pin VS2 and VAUX

Supply current in RX

mode

CLK enabled V_VSOUT

enabled

17, 19,

22, 27

11.10

Current during

11.11 T_{Startup_PLL}on pin VS2 I_VSOUT= 0

and VAUX

I_{Startup_PLL_VS2,VA}

17, 19

9.1

12

mA

UX

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

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15. Electrical Characteristics: Base-station Application (5V) (Continued)

All parameters refer to GND and are valid for T_amb= 25°C, V_VS2= 5.0V. Application according to Figure 2.2 on page 8

f_RF= 433.92MHz/868.3MHz unless otherwise specified.

No. Parameters

Test Conditions

Symbol

Min.

Typ.

Max.

Unit

Type*

Current in RX_Polling_Mode on pin VS2 and VAUX

11.12

11.13

I_{IDLE_VS2,VAUX}× T_SLEEP+ I_{Startup_PLL_VS2,VAUX}× T_{Startup_PLL}+ I_{RX_VS2,VAUX}× (T_{Startup_Sig_Proc}+ T_Bitcheck

)

I_P= --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

T

_Sleep+ T_{Startup_PLL}+ T_{Startup_Sig_Proc}+ T_Bitcheck

CLK enabled

V_VSOUTenabled

I_{S_Poll}= I_P+ I_VSINT+ I_EXT

Supply current in RX

polling mode

17, 19,

22, 27

CLK disabled

V_VSOUTenabled

I_{S_Poll}

I_{S_Poll}= I_P+ I_EXT

I_{S_Poll}= I_P

V_VSOUTdisabled

I_VSOUT= 0

P_out= 5dBm/10dBm

Current in TX mode on 433.92MHz/5dBm

10.9

16.3

14.0

21.0

11.14

11.15

17, 19

I_{TX_VS2_VAUX}

mA

B

pin VS2 and VAUX

433.92MHz/10dBm

868.3MHz/10dBm

11.6

17.8

15.0

23.0

CLK enabled

V_VSOUTenabled

I_{S_TX}= I_{TX_VS2_VAUX}+ I_VSINT+ I_EXT

Supply current in

TX mode

17, 19,

22, 27

I_{S_TX}

CLK disabled

V_VSOUTenabled

I_{S_TX}= I_{TX_VS2_VAUX}+ I_EXT

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

74

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16. Digital Timing Characteristics

All parameters refer to GND and are valid for T_amb= 25°C. V_VS1= V_S2= 3.0V (1 Li battery application (3V)), V_VS2= 6.0V (2 Li battery

application (6V)) and V_VS2= 5.0V (Base-station Application(5V)) unless otherwise specified.

No. Parameters

Test Conditions

Symbol

Min.

Typ.

Max.

Unit

Type*

12 Basic Clock Cycle of the Digital Circuitry

12.1 Basic clock cycle

T_DCLK

16/f_XTO

µs

A

XLIM = 0

BR_Range_0

BR_Range_1

BR_Range_2

BR_Range_3

8

4

2

1

8

4

2

1

Extended basic clock

cycle

× T_DCLK

12.2

T_XDCLK

µs

A

XLIM = 1

BR_Range_0

BR_Range_1

BR_Range_2

BR_Range_3

16

8

4

2

16

8

4

2

× T_DCLK

13

RX Mode/RX Polling Mode

Sleep ×

X_Sleep×

1024 ×

T_DCLK

Sleep and XSleep are

defined in control

register 4

X_Sleep

×

13.1 Sleep time

T_Sleep

ms

µs

A

1024 ×

T_DCLK

798.5 × 798.5 ×

13.2 Start-up PLL RX mode from IDLE mode

BR_Range_0

T_{Startup_PLL}

T_DCLK

882

498

306

210

× T_DCLK

882

498

306

210

× T_DCLK

Start-up signal

processing

BR_Range_1

BR_Range_2

BR_Range_3

13.3

T_{Startup_Sig_Proc}

A

Average time during

polling. No RF signal

applied.

f_Signal= 1/(2 × t_ee)

Signal data rate

Manchester

(Lim_min and Lim_max

up to ±50% of t_ee, see

Figure 9-4 on page 48)

13.4 Time for bit check

Bit-check time for a valid

input signal f_Signal

N_Bit-check= 0

N_Bit-check= 3

3/f_Signal

3.5/f_Signal

N_Bit-check= 6

N_Bit-check= 9

T_{Bit_check}

6/f_Signal1/f_Signal6.5/f_Signal

ms

C

A

9/f_Signal

9.5/f_Signal

BR_Range =

BR_Range0

BR_Range1

BR_Range2

BR_Range3

1.0

2.0

4.0

8.0

2.5

5.0

10.0

20.0

13.5 Bit-rate range

BR_Range

Kbit/s

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

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16. Digital Timing Characteristics (Continued)

All parameters refer to GND and are valid for T_amb= 25°C. V_VS1= V_S2= 3.0V (1 Li battery application (3V)), V_VS2= 6.0V (2 Li battery

application (6V)) and V_VS2= 5.0V (Base-station Application(5V)) unless otherwise specified.

No. Parameters

Test Conditions

Symbol

Min.

Typ.

Max.

Unit

Type*

XLIM = 0

BR_Range_0

BR_Range_1

BR_Range_2

BR_Range_3

Minimum time period

between edges at pin

SDO_TMDO in RX

transparent mode

10 ×

T_XDCLK

13.6

31

T_{DATA_min}

µs

A

XLIM = 1

BR_Range_0

BR_Range_1

BR_Range_2

BR_Range_3

Edge-to-edge time

period of the data signal BR_Range_1

for full sensitivity in RX BR_Range_2

mode

BR_Range_0

200

100

50

500

250

125

62.5

13.7

14

T_DATA

µs

B

A

BR_Range_3

25

TX Mode

331.5

× T_DCLK× T_DCLK

331.5

14.1 Start-up time

From IDLE mode

T_Startup

15

Configuration of the Transceiver with 4-wire Serial Interface

CS set-up time to rising

33, 35

1.5 ×

T_DCLK

15.1

T_{CS_setup}

T_Cycle

µs

ns

A

C

edge of SCK

15.2 SCK cycle time

33

2

SDI_TMDI set-up time

to rising edge of SCK

15.3

15.4

32, 33

T_Setup

250

SDI_TMDI hold time

from rising edge of SCK

32, 33

31, 35

T_Hold

250

ns

C

SDO_TMDO enable

15.5 time from rising edge of

CS

T_{Out_enable}

250

SDO_TMDO output

15.6 delay from falling edge C_L= 10 pF

of SCK

31, 35

31, 33

T_{Out_delay}

ns

C

SDO_TMDO disable

15.7 time from falling edge of

CS

T_{Out_disable}

1.5 ×

T_DCLK

15.8 CS disable time period

35

T_{CS_disable}

T_{SCK_setup1}

T_{SCK_setup2}

T_{SCK_hold}

µs

ns

A

C

Time period SCK low to

CS high

15.9

33, 35

250

Time period SCK low to

CS low

15.10

Time period CS low to

SCK high

15.11

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

76

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16. Digital Timing Characteristics (Continued)

All parameters refer to GND and are valid for T_amb= 25°C. V_VS1= V_S2= 3.0V (1 Li battery application (3V)), V_VS2= 6.0V (2 Li battery

application (6V)) and V_VS2= 5.0V (Base-station Application(5V)) unless otherwise specified.

No. Parameters

Test Conditions

Symbol

Min.

Typ.

Max.

Unit

Type*

Start Time Push Button Tn and PWR_ON

Timing of Wake-up via PWR_ON or Tn

16

From OFF mode to IDLE

mode, applications

according to Figure 2-1

on page 7, Figure 2.2 on

page 8 and

Figure 2-3 on page 9

XTAL:

C_m< 14fF (typ. 5fF)

C₀< 2.2pF (typ. 1.8pF)

R_m≤ 120Ω (typ. 15Ω)

1 Li battery application

(3V)

PWR_ON high to

positive edge on pin

IRQ (see Figure 7-4 on C₃= C₄= 68nF

page 39)

C₁= C₂= 68nF

0.3

0.8

1.3

ms

16.1

29, 40 T_{PWR_ON_IRQ_1}

B

C₅= 10nF

2 Li battery application

(6V)

C₁= C₄= 68nF

C₂= C₃= 2.2µF

C₅= 10nF

0.45

Base-station Application

(5V)

C₁= C₃= C₄= 68nF

C₂= C₁₂= 2.2µF

C₅= 10nF

0.45

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

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16. Digital Timing Characteristics (Continued)

All parameters refer to GND and are valid for T_amb= 25°C. V_VS1= V_S2= 3.0V (1 Li battery application (3V)), V_VS2= 6.0V (2 Li battery

application (6V)) and V_VS2= 5.0V (Base-station Application(5V)) unless otherwise specified.

No. Parameters

PWR_ON high to

positive edge on pin

Test Conditions

Symbol

Min.

Typ.

Max.

Unit

Type*

Every mode except OFF

2 ×

T_DCLK

16.2

29, 40 T_{PWR_ON_IRQ_2}

µs

A

IRQ (see Figure 7-4 on mode

page 39)

From OFF mode to IDLE

mode, applications

according to Figure 2-1

on page 7, Figure 2.2 on

page 8 and Figure 2-3

on page 9

XTAL:

C_m< 14 fF (typ 5fF)

C₀< 2.2 pF (typ 1.8pF)

R_m≤ 120Ω (typ 15Ω)

1 Li battery application

(3V)

C₁= C₂= 68nF

C₃= C₄= 68nF

C₅= 10nF

Tn low to positive edge

16.3 on pin IRQ (see Figure

7-2 on page 37)

29, 41,

42, 43,

44, 45

0.3

0.8

1.3

ms

T_{Tn_IRQ}

B

2 Li battery application

(6V)

C₁= C₄= 68nF

C₂= C₃= 2.2µF

C₅= 10nF

0.45

Base-station Application

(5V)

C₁= C₃= C₄= 68nF

C₂= C₁₂= 2.2µF

C₅= 10nF

ms

µs

29, 41,

42, 43,

44, 45

Push button debounce Every mode except OFF

time mode

8195

× T_DCLK

8195

× T_DCLK

16.4

T_Debounce

A

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

78

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17. Digital Port Characteristics

All parameters refer to GND and are valid for T_amb= –40°C to +85°C, V_VS1= V_S2= 2.4V to 3.6V (1 Li battery application (3V)) and

V_VS2= 4.4V to 6.6V (2 Li battery application (6V)) and V_VS2= 4.75V to 5.25V (Base-station Application (5V)). Typical values at

V_VS1= V_VS2= 3V and T_amb= 25°C unless otherwise specified.

No. Parameters

Test Conditions

Symbol

Min.

Typ.

Max.

Unit

Type*

17

Digital Ports

CS input

Low level input voltage

0.2 ×

V_VSINT

V_VSINT= 2.4V to 5.25V

35

33

32

V_Il

V_Ih

V_Il

V

A

17.1

0.8 ×

V_VSINT

High level input voltage V_VSINT= 2.4V to 5.25V

V_VSINT

SCK input

0.2 ×

V_VSINT

V_VSINT= 2.4V to 5.25V

Low level input voltage

17.2

17.3

0.8 ×

V_VSINT

High level input voltage V_VSINT= 2.4V to 5.25V

V_Ih

V_Il

V_VSINT

SDI_TMDI input

0.2 ×

V_VSINT

V_VSINT= 2.4V to 5.25V

Low level input voltage

0.8 ×

V_VSINT

High level input voltage V_VSINT= 2.4V to 5.25V

V_Ih

V_VSINT

TEST1 input must

17.4 TEST1 input

17.5 TEST2 input

PWR_ON input

always be directly

connected to GND

20

23

0

V

TEST2 input must

always be direct

connected to GND

0

Internal pull-down with

series connection of

40

V_Il

0.4

V

A

Low level input voltage 40kΩ±20% resistor and

diode

17.6

Internal pull-down with

High level input

voltage⁽¹⁾

series connection of

40kΩ±20% resistor and

diode

0.8

× V_VS2

V_Ih

V_Il

V

A

41, 42,

43, 44,

45

Tn input

Internal pull-up resistor

0.2

× V_VS2

Low level input voltage of 50kΩ ±20%

17.7

17.8

41, 42,

43, 44,

45

High level input

voltage⁽¹⁾

Internal pull-up resistor

of 50kΩ ±20%

× V_VS2–

0.5V

V_Ih

V_Il

V

A

433_N868 input

Low level input voltage

6

0.25

Input current low

6

I_Il

V_Ih

I_Ih

–5

AVCC

1

µA

V

A

High level input voltage

Input current high

1.7

µA

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note:

1. If a logic high level is applied to this pin, a minimum serial impedance of 100Ω must be ensured for proper operation

over full temperature range.

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17. Digital Port Characteristics (Continued)

All parameters refer to GND and are valid for T_amb= –40°C to +85°C, V_VS1= V_S2= 2.4V to 3.6V (1 Li battery application (3V)) and

V_VS2= 4.4V to 6.6V (2 Li battery application (6V)) and V_VS2= 4.75V to 5.25V (Base-station Application (5V)). Typical values at

V_VS1= V_VS2= 3V and T_amb= 25°C unless otherwise specified.

No. Parameters

Test Conditions

Symbol

Min.

Typ.

Max.

Unit

Type*

PWR_H input

Low level input voltage

9

V_Il

0.25

V

A

Input current low

9

I_Il

V_Ih

I_Ih

–5

AVCC

1

µA

V

A

17.9

High level input voltage

Input current high

SDO_TMDO output

1.7

µA

V_VSINT= 2.4V to 5.25V

31

29

V_ol

V_oh

V_ol

0.15

0.4

V

B

Saturation voltage low I_{SDO_TMDO}= 250µA

17.10

17.11

V_VSINT= 2.4V to 5.25V

Saturation voltage high

V_VSINT

0.4

–

V_VSINT

0.15

–

I_{SDO_TMDO}= –250µA

IRQ output

Saturation voltage low

V_VSINT= 2.4V to 5.25V

I_IRQ= 250µA

0.15

0.4

V_VSINT= 2.4V to 5.25V

I_IRQ= –250µA

V_VSINT

0.4

V_VSINT

0.15

Saturation voltage high

V_oh

V_VSINT= 2.4V to 5.25V

I_CLK= 100µA

CLK output

Saturation voltage low of 1kΩ for spurious

internal series resistor

30

V_ol

0.15

0.4

V

B

emission reduction in

PLL

17.12

V_VSINT= 2.4V to 5.25V

I_CLK= –100µA

internal series resistor

V_VSINT

0.4

–

V_VSINT

0.15

–

Saturation voltage high

V_oh

of 1kΩ for spurious

emission reduction in

PLL

N_RESET output

Saturation voltage low I_{N_RESET}= 250µA

V_VSINT= 2.4V to 5.25V

28

46

34

V_ol

V_oh

V_ol

V_oh

V_ol

0.15

0.4

V

B

17.13

V_VSINT= 2.4V to 5.25V

Saturation voltage high

V_VSINT

0.4

–

V_VSINT

0.15

–

I_{N_RESET}= –250µA

RX_ACTIVE output

Saturation voltage low I_{RX_ACTIVE}= 25µA

V_VSINT= 2.4V to 5.25V

0.25

17.14

17.15

V_VSINT= 2.4V to 5.25V

Saturation voltage high

V_AVCC

0.5

V_AVCC

0.15

I_{RX_ACTIVE}= –1500µA

DEM_OUT output

Saturation voltage low I_{DEM_OUT}= 250µA

Open drain output

0.15

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note:

1. If a logic high level is applied to this pin, a minimum serial impedance of 100Ω must be ensured for proper operation

over full temperature range.

80

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18. Ordering Information

Extended Type Number

Package

Remarks

Delivery

ATA5428C-PLQW

QFN48

7mm × 7mm

Taped and reeled + Dry pack

Note:

W = RoHS compliant

19. Package Information

7

1 max.

5.5

+0

0.05-0.05

5.1

37

48

1

36

25

1

technical drawings

according to DIN

specifications

Dimensions in mm

12

24

13

0.5 nom.

Not indicated tolerances 0.05

01/14/03

TITLE

DRAWING NO.

REV.

GPC

Package Drawing Contact:

packagedrawings@atmel.com

Package: QFN48_7x7

Exposed pad 5.1x5.1

6.543-5089.02-4

1

ATA5428 [DATASHEET]

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20. Revision History

Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this

document.

Revision No.

History

4841G-WIRE-03/04

4841F-WIRE-11/12

• Put datasheet in the latest template

• Section 13 “Ordering Information” on page 82 updated

• Put datasheet in the latest template

4841E-WIRE-03/12

4841D-WIRE-10/07

• Deleted all the cancelled Parts (ATA5423, ATA5425, ATA5429)

• Put datasheet in the latest template

• kBaud replaced through Kbit/s

4841C-WIRE-05/06

• Baud replaced through bit

• Table 9-6 “Interrupt Handling” on page 65 changed

82

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21. Table of Contents

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.

2.

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1

2.2

2.3

Typical Remote Control Unit Application with 1 Li Battery (3V). . . . . . . . . . . . . . . . . . . . . . . . 7

Typical Base-station Application (5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Typical Remote Control Unit Application, 2 Li Batteries (6V) . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.

RF Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.1

Low-IF Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Input Matching at RF_IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Sensitivity versus Supply Voltage, Temperature and Frequency Offset . . . . . . . . . . . . . . . . 12

Frequency Accuracy of the Crystals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

RX Supply Current versus Temperature and Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . 13

Blocking, Selectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

In-band Disturbers, Data Filter, Quasi-peak Detector, Data Slicer . . . . . . . . . . . . . . . . . . . . 14

DEM_OUT Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

RSSI Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

3.10 Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.11 FSK/ASK Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.12 Output Power Setting and PA Matching at RF_OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.13 Output Power and TX Supply Current versus Supply Voltage and Temperature . . . . . . . . . 19

3.14 RX/TX Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.15 Matching Network in TX Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.16 Matching Network in RX Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.

5.

XTO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.1

Pin CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.2

Basic Clock Cycle of the Digital Circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.1

OFF Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

AUX Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

IDLE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Reset Timing and Reset Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

1 Li Battery Application (3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2 Li Battery Application (6V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.2

5.3

5.4

5.5

5.6

6.

7.

Microcontroller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Digital Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.1

Register Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

TX/RX Data Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Pin Tn. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Pin PWR_ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Low Battery Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Pin VAUX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.2

7.3

7.4

7.5

7.6

7.7

7.8

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83

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8.

Transceiver Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

8.1

Command: Read TX/RX Data Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Command: Write TX/RX Data Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Command: Read Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Command: Write Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Command: OFF Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Command: Delete IRQ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Command Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4-wire Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

8.2

8.3

8.4

8.5

8.6

8.7

8.8

9.

Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

9.1

9.2

9.3

RX Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

TX Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

10. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

11. Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

12. Electrical Characteristics: General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

13. Electrical Characteristics: 1 Li Battery Application (3V) . . . . . . . . . . . . . . . . . . . . . . . . 69

14. Electrical Characteristics: 2 Li Battery Application (6V) . . . . . . . . . . . . . . . . . . . . . . . . 71

15. Electrical Characteristics: Base-station Application (5V) . . . . . . . . . . . . . . . . . . . . . . . 73

16. Digital Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

17. Digital Port Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

18. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

19. Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

20. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

21. Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

84

ATA5428 [DATASHEET]

4841G–WIRE–03/14

X

X X X X

X

Atmel Corporation

1600 Technology Drive, San Jose, CA 95110 USA

T: (+1)(408) 441.0311

F: (+1)(408) 436.4200

|

www.atmel.com

Atmel^®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities^®, and others are registered trademarks or trademarks of Atmel Corporation or its

subsidiaries. Other terms and product names may be trademarks of others.

DISCLAIMER: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right

is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE

ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS

INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT

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BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this

document and reserves the right to make changes to specifications and products descriptions at any time without notice. Atmel does not make any commitment to update the information

contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel products are not intended,

authorized, or warranted for use as components in applications intended to support or sustain life.

SAFETY-CRITICAL, MILITARY, AND AUTOMOTIVE APPLICATIONS DISCLAIMER: Atmel products are not designed for and will not be used in connection with any applications where

the failure of such products would reasonably be expected to result in significant personal injury or death (“Safety-Critical Applications”) without an Atmel officer's specific written

consent. Safety-Critical Applications include, without limitation, life support devices and systems, equipment or systems for the operation of nuclear facilities and weapons systems.

Atmel products are not designed nor intended for use in military or aerospace applications or environments unless specifically designated by Atmel as military-grade. Atmel products are

not designed nor intended for use in automotive applications unless specifically designated by Atmel as automotive-grade.


型号：	ATA5428C-PLQW
厂家：	MICROCHIP
描述：	Telecom Circuit, 1-Func 电信电信集成电路
文件：	总85页 (文件大小：2658K)
中文：	中文翻译
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ATA5428C-PLQW [MICROCHIP]

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