AT24CM-WWUUM-E_技术文档

AT24CM02

I²C-Compatible (Two-Wire)

Serial EEPROM 2‑Mbit (262,144 x 8)

Features

•

Low-Voltage and Standard-Voltage Operation:

– V_CC= 1.7V to 5.5V

– V_CC= 2.5V to 5.5V

•

Internally Organized as 262,144 x 8 (2‑Mbit)

Industrial Temperature Range: -40°C to +85°C

I²C-Compatible (Two-Wire) Serial Interface:

– 100 kHz Standard Mode, 1.7V to 5.5V

– 400 kHz Fast Mode, 1.7V to 5.5V

– 1 MHz Fast Mode Plus (FM+), 2.5V to 5.5V

Schmitt Triggers, Filtered Inputs for Noise Suppression

Bidirectional Data Transfer Protocol

•

Write-Protect Pin for Full Array Hardware Data Protection

Ultra Low Active Current (3 mA maximum) and Standby Current (3 µA maximum)

256-byte Page Write Mode:

– Byte write and partial page writes allowed

Random and Sequential Read Modes

•

Self-Timed Write Cycle:

– All write operations complete within 10 ms maximum

Built-in Error Detection and Correction

•

High Reliability:

– Endurance: 1,000,000 write cycles

– Data retention: 100 years

•

Green Package Options (Lead-free/Halide-free/RoHS compliant)

Die Sale Options: Wafer Form and Bumped Wafers

Packages

•

8-Lead SOIC and 8-Ball WLCSP

DS20006197C-page 1

Datasheet

AT24CM02

Table of Contents

Features......................................................................................................................................................... 1

Packages........................................................................................................................................................1

1. Package Types (not to scale)..................................................................................................................4

2. Pin Descriptions...................................................................................................................................... 5

2.1. Device Address Input (A2)........................................................................................................... 5

2.2. Ground......................................................................................................................................... 5

2.3. Serial Data (SDA).........................................................................................................................5

2.4. Serial Clock (SCL)........................................................................................................................5

2.5. Write-Protect (WP)....................................................................................................................... 6

2.6. Device Power Supply................................................................................................................... 6

3. Description.............................................................................................................................................. 7

3.1. System Configuration Using Two-Wire Serial EEPROMs ...........................................................7

3.2. Block Diagram..............................................................................................................................8

4. Electrical Characteristics.........................................................................................................................9

4.1. Absolute Maximum Ratings..........................................................................................................9

4.2. DC and AC Operating Range.......................................................................................................9

4.3. DC Characteristics....................................................................................................................... 9

4.4. AC Characteristics......................................................................................................................10

4.5. Electrical Specifications..............................................................................................................11

5. Device Operation and Communication................................................................................................. 13

5.1. Clock and Data Transition Requirements...................................................................................13

5.2. Start and Stop Conditions.......................................................................................................... 13

5.3. Acknowledge and No-Acknowledge...........................................................................................14

5.4. Standby Mode............................................................................................................................ 14

5.5. Software Reset...........................................................................................................................14

6. Memory Organization............................................................................................................................16

6.1. Device Addressing..................................................................................................................... 16

7. Write Operations................................................................................................................................... 17

7.1. Byte Write...................................................................................................................................17

7.2. Page Write..................................................................................................................................17

7.3. Internal Writing Methodology......................................................................................................18

7.4. Acknowledge Polling.................................................................................................................. 18

7.5. Write Cycle Timing..................................................................................................................... 19

7.6. Write Protection..........................................................................................................................19

8. Read Operations...................................................................................................................................21

8.1. Current Address Read................................................................................................................21

8.2. Random Read............................................................................................................................ 21

8.3. Sequential Read.........................................................................................................................22

DS20006197C-page 2

Datasheet

AT24CM02

9. Device Default Condition from Microchip..............................................................................................23

10. Packaging Information.......................................................................................................................... 24

10.1. Package Marking Information.....................................................................................................24

11. Revision History.................................................................................................................................... 29

The Microchip Website.................................................................................................................................30

Product Change Notification Service............................................................................................................30

Customer Support........................................................................................................................................ 30

Product Identification System.......................................................................................................................31

Microchip Devices Code Protection Feature................................................................................................31

Legal Notice................................................................................................................................................. 32

Trademarks.................................................................................................................................................. 32

Quality Management System....................................................................................................................... 33

Worldwide Sales and Service.......................................................................................................................34

DS20006197C-page 3

Datasheet

AT24CM02

Package Types (not to scale)

1.

Package Types (not to scale)

8-Lead SOIC

8-Ball WLCSP

(Top View)

NC

1

2

8

7

V_CC

WP

A2

B2

A3

NC

B4 NC

NC

A2

WP

3

4

6

5

SCL

SDA

SCL

SDA

C1

C4

A2

D2

D3

GND

DS20006197C-page 4

Datasheet

AT24CM02

Pin Descriptions

2.

Pin Descriptions

The descriptions of the pins are listed in Table 2-1.

Table 2-1.ꢀPin Function Table

Name

NC

8‑Lead SOIC

8‑Ball WLCSP

Function

1

2

3

4

5

6

7

8

A3

B4

C4

D3

D2

C1

B2

A2

No Connect

NC

(1)

A2

Device Address Input

Ground

GND

SDA

SCL

Serial Data

Serial Clock

(1)

WP

Write-Protect

V

Device Power Supply

CC

Note:ꢀ

1. If the A2 or WP pins are not driven, they are internally pulled down to GND. In order to operate in a wide

variety of application environments, the pull-down mechanism is intentionally designed to be somewhat strong.

Once these pins are biased above the CMOS input buffer’s trip point (~0.5 x V_CC), the pull‑down mechanism

disengages. Microchip recommends connecting these pins to a known state whenever possible.

2.1

Device Address Input (A2)

The A2 pin is a device address input that is hard-wired (directly to GND or to V_CC) for compatibility with other two-wire

Serial EEPROM devices. When the pin is hard-wired, as many as two devices may be addressed on a single bus

system. A device is selected when a corresponding hardware and software match is true. If the pin is left floating,

the A2 pin will be internally pulled down to GND. However, due to capacitive coupling that may appear in customer

applications, Microchip recommends always connecting the address pin to a known state. When using a pull-up

resistor, Microchip recommends using 10 kΩ or less.

2.2

2.3

Ground

The ground reference for the power supply. GND should be connected to the system ground.

Serial Data (SDA)

The SDA pin is an open-drain bidirectional input/output pin used to serially transfer data to and from the device. The

SDA pin must be pulled high using an external pull-up resistor (not to exceed 10 kΩ in value) and may be wire-ORed

with any number of other open-drain or open-collector pins from other devices on the same bus.

2.4

Serial Clock (SCL)

The SCL pin is used to provide a clock to the device and to control the flow of data to and from the device. Command

and input data present on the SDA pin is always latched in on the rising edge of SCL, while output data on the SDA

pin is clocked out on the falling edge of SCL. The SCL pin must either be forced high when the serial bus is idle or

pulled high using an external pull-up resistor.

DS20006197C-page 5

Datasheet

AT24CM02

Pin Descriptions

2.5

Write-Protect (WP)

The write-protect input, when connected to GND, allows normal write operations. When the WP pin is connected

directly to V_CC, all write operations to the protected memory are inhibited.

If the pin is left floating, the WP pin will be internally pulled down to GND. However, due to capacitive coupling that

may appear in customer applications, Microchip recommends always connecting the WP pin to a known state. When

using a pull‑up resistor, Microchip recommends using 10 kΩ or less.

Table 2-2.ꢀWrite-Protect

WP Pin Status

At V_CC

Part of the Array Protected

Full Array

At GND

Normal Write Operations

2.6

Device Power Supply

The V_CCpin is used to supply the source voltage to the device. Operations at invalid V_CCvoltages may produce

spurious results and should not be attempted.

DS20006197C-page 6

Datasheet

AT24CM02

Description

3.

Description

The AT24CM02 provides 2,097,152 bits of Serial Electrically Erasable and Programmable Read-Only Memory

(EEPROM) organized as 262,144 words of 8 bits each. The device's cascading feature allows up to four devices

to share a common two-wire bus. This device is optimized for use in many industrial and commercial applications

where low-power and low-voltage operations are essential. The device is available in space-saving 8-lead SOIC and

8-ball WLCSP packages. All packages operate from 1.7V to 5.5V.

3.1

System Configuration Using Two-Wire Serial EEPROMs

V_CC

t

R(max)

R

PUP(max) =

PUP(min) =

0.8473 x C

L

V

- V

OL(max)

CC

V

CC

I

OL

SCL

SDA

WP

2

I C Bus Host:

Microcontroller

NC

A₂

V_CC

WP

NC

A₂

V_CC

WP

Client 0

AT24CXXX

Client 1

AT24CXXX

SDA

SCL

SDA

SCL

GND

DS20006197C-page 7

Datasheet

AT24CM02

Description

3.2

Block Diagram

Hardware

Address

Comparator

Power-on

Reset

Generator

Memory

System Control

Module

V_CC

High Voltage

Generation Circuit

Write

Protection

Control

WP

EEPROM Array

Address Register

and Counter

1 page

Column Decoder

Data Register

A₂

SCL

SDA

Start

Stop

Detector

Data & ACK

Input/Output Control

D_OUT

D_IN

GND

DS20006197C-page 8

Datasheet

AT24CM02

Electrical Characteristics

4.

Electrical Characteristics

4.1

Absolute Maximum Ratings

Temperature under bias

Storage temperature

V_CC

-55°C to +125°C

-65°C to +150°C

6.25V

Voltage on any pin with respect to ground

DC output current

-1.0V to +7.0V

5.0 mA

ESD protection

>3 kV

Note:ꢀ Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.

This is a stress rating only and functional operation of the device at these or any other conditions above those

indicated in the operation listings of this specification is not implied. Exposure to absolute maximum rating conditions

for extended periods may affect device reliability.

4.2

DC and AC Operating Range

Table 4-1.ꢀDC and AC Operating Range

AT24CM02

Operating Temperature (Case)

Industrial Temperature Range

Low-Voltage Grade

-40°C to +85°C

1.7V to 5.5V

2.5V to 5.5V

V_CCPower Supply

Standard-Voltage Grade

4.3

DC Characteristics

Table 4-2.ꢀDC Characteristics

Parameter

Symbol

Minimum

Typical⁽¹⁾

Maximum

Units

Test Conditions

Supply Voltage,

1.7V Option

V_CC1

1.7

—

5.5

V

Supply Voltage,

2.5V Option

V_CC2

2.5

—

5.5

0.5

V

0.1

mA

V_CC= 1.8V⁽²⁾

,

Read at 400 kHz

Supply Current,

Read

I_CC

V_CC= 5.0V,

Read at 1 MHz

—

0.3

0.4

1.0

mA

V_CC= 1.8V⁽²⁾

,

averaged during t_WR

Supply Current,

Write⁽³⁾

I_CC

V_CC= 5.0V,

averaged during t_WR

—

1.7

3.0

mA

DS20006197C-page 9

Datasheet

AT24CM02

Electrical Characteristics

...........continued

Parameter

Symbol

Minimum

Typical⁽¹⁾

Maximum

Units

Test Conditions

V_CC= 1.8V⁽²⁾

V_IN= V_CCor V_SS

,

—

0.08

1.0

μA

V_CC= 2.5V,

V_IN= V_CCor V_SS

Standby Current

I_SB

—

0.08

2.0

μA

V_CC= 5.5V,

V_IN= V_CCor V_SS

—

0.15

0.10

0.05

3.0

μA

Input Leakage

Current

I_LI

V_IN= V_CCor V_SS

Output Leakage

Current

I_LO

V_OUT= V_CCor V_SS

Input Low Level

Input High Level

V_IL

V_IH

-0.6

—

V_CCx 0.3

V_CC+ 0.5

V

Note 2

V_CCx 0.7

V_CC= 1.7V,

I_OL= 0.15 mA

Output Low Level

Note:ꢀ

V_OL1

V_OL2

—

0.2

0.4

V

V_CC= 3.0V, I_OL= 2.1 mA

1. Typical values characterized at T_A= +25°C unless otherwise noted.

2. This parameter is characterized but is not 100% tested in production.

3. Averaged during t_WR

.

4.4

AC Characteristics

Table 4-3.ꢀAC Characteristics⁽¹⁾

Standard Mode

Fast Mode

Fast Mode Plus

Parameter

Symbol V_CC= 1.7V to 5.5V V_CC= 1.7V to 5.5V V_CC= 2.5V to 5.5V

Units

Min.

—

Max.

100

—

Min.

—

Max.

400

—

Min.

—

Max.

1000

—

Clock Frequency, SCL

Clock Pulse Width Low

Clock Pulse Width High

f_SCL

t_LOW

t_HIGH

kHz

ns

4,700

4,000

1,300

600

500

400

—

ns

Input Filter Spike

t_I

—

100

4,500

—

100

900

—

50

450

—

ns

Suppression (SCL,SDA)⁽²⁾

Clock Low to Data Out

Valid

t_AA

t_BUF

Bus Free Time between

Stop and Start⁽²⁾

4,700

1,300

500

Start Hold Time

t_HD.STA

t_SU.STA

t_HD.DAT

t_SU.DAT

t_R

4,000

4,700

0

—

600

0

—

250

0

—

ns

Start Set-up Time

Data In Hold Time

Data In Set-up Time

Inputs Rise Time⁽¹⁾

Inputs Fall Time⁽¹⁾

—

200

—

100

—

100

—

1,000

300

100

t_F

—

Stop Condition Set-up

Time

t_SU.STO

4,700

—

600

—

250

—

ns

DS20006197C-page 10

Datasheet

AT24CM02

Electrical Characteristics

...........continued

Parameter

Standard Mode

Fast Mode

Fast Mode Plus

Symbol V_CC= 1.7V to 5.5V V_CC= 1.7V to 5.5V V_CC= 2.5V to 5.5V

Units

Min.

4,000

100

Max.

—

Min.

600

50

Max.

—

Min.

250

50

Max.

—

Write-Protect Setup Time

Write-Protect Hold Time

Data Out Hold Time

Write Cycle Time

t_SU.WP

t_HD.WP

t_DH

ns

ms

—

t_WR

—

10

—

10

—

10

Notes:ꢀ

1. AC measurement conditions:

– C_L: 100 pF

– R_PUP(SDA bus line pull-up resistor to V_CC): 1.3 kΩ (1000 kHz), 4 kΩ (400 kHz), 10 kΩ (100 kHz)

– Input pulse voltages: 0.3 x V_CCto 0.7 x V_CC

– Input rise and fall times: ≤50 ns

– Input and output timing reference voltages: 0.5 x V_CC

2. These parameters are determined through product characterization and are not 100% tested in production.

Figure 4-1.ꢀ Bus Timing

t_HIGH

t_F

t_R

t_LOW

SCL

t_SU.STA

t_HD.STA

t_HD.DAT

t_SU.DAT

t_SU.STO

SDA In

t_BUF

t_AA

t_DH

SDA Out

4.5

Electrical Specifications

4.5.1

Power-Up Requirements and Reset Behavior

During a power-up sequence, the V_CCsupplied to the AT24CM02 should monotonically rise from GND to the

minimum V_CClevel, as specified in Table 4-1, with a slew rate no faster than 0.1 V/µs.

4.5.1.1 Device Reset

To prevent inadvertent write operations or any other spurious events from occurring during a power-up sequence, the

AT24CM02 includes a Power-on Reset (POR) circuit. Upon power-up, the device will not respond to any commands

until the V_CClevel crosses the internal voltage threshold (V_POR) that brings the device out of Reset and into Standby

mode.

The system designer must ensure the instructions are not sent to the device until the V_CCsupply has reached a

stable value greater than or equal to the minimum V_CClevel. Additionally, once the V_CCis greater than or equal to the

minimum V_CClevel, the bus host must wait at least t_PUPbefore sending the first command to the device. See Table

4-4 for the values associated with these power-up parameters.

DS20006197C-page 11

Datasheet

AT24CM02

Electrical Characteristics

Table 4-4.ꢀPower-up Conditions⁽¹⁾

Symbol

Parameter

Min. Max. Units

t_PUP

V_POR

t_POFF

Time required after V_CCis stable before the device can accept commands

Power-on Reset Threshold Voltage

100

－

1

－

1.5

－

µs

V

Minimum time at V_CC= 0V between power cycles

ms

Note:ꢀ

1. These parameters are characterized but they are not 100% tested in production.

If an event occurs in the system where the V_CClevel supplied to the AT24CM02 drops below the maximum V_POR

level specified, it is recommended that a full power cycle sequence be performed. First, drive the V_CCpin to GND,

waiting at least the minimum t_POFFtime, and then perform a new power-up sequence in compliance with the

requirements defined in this section.

4.5.2

Pin Capacitance

Table 4-5.ꢀPin Capacitance⁽¹⁾

Symbol

C_I/O

Test Condition

Input/Output Capacitance (SDA)

Input Capacitance (A2 and SCL)

Max.

Units

pF

Conditions

V_I/O= 0V

V_IN= 0V

8

6

C_IN

pF

Note:ꢀ

1. This parameter is characterized but is not 100% tested in production.

4.5.3

EEPROM Cell Performance Characteristics

Table 4-6.ꢀEEPROM Cell Performance Characteristics

Operation

Test Condition

Min.

Max.

Units

Write Endurance⁽¹⁾

T_A= 25°C, V_CC(min.) < V_CC< V_CC(max.),

Byte⁽²⁾or Page Write mode

1,000,000

—

Write Cycles

Data Retention⁽¹⁾

T_A= 55°C

100

—

Years

Notes:ꢀ

1. Performance is determined through characterization and the qualification process.

2. Due to the memory array architecture, the Write Cycle Endurance is specified for writes in groups of four data

bytes. The beginning of any 4-byte boundaries can be determined by multiplying any integer (N) by four (i.e.,

4*N). The end address can be found by adding three to the beginning value (i.e., 4*N+3). See Internal Writing

Methodology for more details on this implementation.

DS20006197C-page 12

Datasheet

AT24CM02

Device Operation and Communication

5.

Device Operation and Communication

The AT24CM02 operates as a client device and utilizes a simple I²C-compatible two-wire digital serial interface to

communicate with a host controller, commonly referred to as the bus host. The host initiates and controls all read and

write operations to the client devices on the serial bus, and both the host and the client devices can transmit and

receive data on the bus.

The serial interface is comprised of just two signal lines: Serial Clock (SCL) and Serial Data (SDA). The SCL pin is

used to receive the clock signal from the host, while the bidirectional SDA pin is used to receive command and data

information from the host as well as to send data back to the host. Data is always latched into the AT24CM02 on

the rising edge of SCL and always output from the device on the falling edge of SCL. Both the SCL and SDA pins

incorporate integrated spike suppression filters and Schmitt Triggers to minimize the effects of input spikes and bus

noise.

All command and data information is transferred with the Most Significant bit (MSb) first. During bus communication,

one data bit is transmitted every clock cycle, and after eight bits (one byte) of data have been transferred, the

receiving device must respond with either an Acknowledge (ACK) or a No-Acknowledge (NACK) response bit during

a ninth clock cycle (ACK/NACK clock cycle) generated by the host. Therefore, nine clock cycles are required for

every one byte of data transferred. There are no unused clock cycles during any read or write operation, so there

must not be any interruptions or breaks in the data stream during each data byte transfer and ACK or NACK clock

cycle.

During data transfers, data on the SDA pin must only change while SCL is low and the data must remain stable while

SCL is high. If data on the SDA pin changes while SCL is high, then either a Start or a Stop condition will occur.

Start and Stop conditions are used to initiate and end all serial bus communication between the host and the client

devices. The number of data bytes transferred between a Start and a Stop condition is not limited and is determined

by the host. In order for the serial bus to be idle, both the SCL and SDA pins must be in the logic high state at the

same time.

5.1

Clock and Data Transition Requirements

The SDA pin is an open-drain terminal and therefore must be pulled high with an external pull‑up resistor. SCL is

an input pin that can either be driven high or pulled high using an external pull‑up resistor. Data on the SDA pin

may change only during SCL low time periods. Data changes during SCL high periods will indicate a Start or Stop

condition as defined below. The relationship of the AC timing parameters with respect to SCL and SDA for the

AT24CM02 are shown in the timing waveform in Figure 4-1. The AC timing characteristics and specifications are

outlined in AC Characteristics.

5.2

Start and Stop Conditions

5.2.1

Start Condition

A Start condition occurs when there is a high-to-low transition on the SDA pin while the SCL pin is at a stable logic

‘1’ state and will bring the device out of Standby mode. The host uses a Start condition to initiate any data transfer

sequence; therefore, every command must begin with a Start condition. The device will continuously monitor the SDA

and SCL pins for a Start condition but will not respond unless one is detected. Refer to Figure 5-1 for more details.

5.2.2

Stop Condition

A Stop condition occurs when there is a low-to-high transition on the SDA pin while the SCL pin is stable in the logic

‘1’ state.

The host can use the Stop condition to end a data transfer sequence with the AT24CM02, which will subsequently

return to Standby mode. The host can also utilize a repeated Start condition instead of a Stop condition to end the

current data transfer if the host will perform another operation. Refer to Figure 5-1 for more details.

DS20006197C-page 13

Datasheet

AT24CM02

Device Operation and Communication

5.3

Acknowledge and No-Acknowledge

After every byte of data is received, the receiving device must confirm to the transmitting device that it has

successfully received the data byte by responding with what is known as an Acknowledge (ACK). An ACK is

accomplished by the transmitting device first releasing the SDA line at the falling edge of the eighth clock cycle

followed by the receiving device responding with a logic ‘0’ during the entire high period of the ninth clock cycle.

When the AT24CM02 is transmitting data to the host, the host can indicate that it is done receiving data and wants

to end the operation by sending a logic ‘1’ response to the AT24CM02 instead of an ACK response during the ninth

clock cycle. This is known as a No-Acknowledge (NACK) and is accomplished by the host sending a logic ‘1’ during

the ninth clock cycle, at which point the AT24CM02 will release the SDA line so the host can then generate a Stop

condition.

The transmitting device, which can be the bus host or the Serial EEPROM, must release the SDA line at the

falling edge of the eighth clock cycle to allow the receiving device to drive the SDA line to a logic ‘0’ to ACK the

previous 8-bit word. The receiving device must release the SDA line at the end of the ninth clock cycle to allow the

transmitter to continue sending new data. A timing diagram has been provided in Figure 5-1 to better illustrate these

requirements.

Figure 5-1.ꢀStart Condition, Data Transitions, Stop Condition and Acknowledge

SDA

Must Be

Stable

SDA

Must Be

Stable

Acknowledge Window

1

2

8

9

SCL

SDA

Stop

Condition

Acknowledge

Valid

Start

Condition

The transmitting device (Host or Client)

The receiver (Host or Client)

SDA

Change

Allowed

SDA

Change

Allowed

must release the SDA line at this point to allow

the receiving device (Host or Client) to drive the

SDA line low to ACK the previous 8-bit word.

must release the SDA line at

this point to allow the transmitter

to continue sending new data.

5.4

5.5

Standby Mode

The AT24CM02 features a low-power Standby mode that is enabled when any one of the following occurs:

•

A valid power-up sequence is performed (see Power-Up Requirements and Reset Behavior).

A Stop condition is received by the device unless it initiates an internal write cycle (see Write Operations).

At the completion of an internal write cycle (see Write Operations).

Software Reset

After an interruption in protocol, power loss or system Reset, any two‑wire device can be protocol reset by clocking

SCL until SDA is released by the EEPROM and goes high. The number of clock cycles until SDA is released by the

EEPROM will vary. The software Reset sequence should not take more than nine dummy clock cycles. Once the

software Reset sequence is complete, new protocol can be sent to the device by sending a Start condition followed

by the protocol. Refer to Figure 5-2 for an illustration.

DS20006197C-page 14

Datasheet

AT24CM02

Device Operation and Communication

Figure 5-2.ꢀSoftware Reset

Dummy Clock Cycles

SCL

1

2

3

8

9

SDA Released

by EEPROM

Device is

Software Reset

SDA

In the event that the device is still non-responsive or remains active on the SDA bus, a power cycle must be used to

reset the device (see Power-Up Requirements and Reset Behavior).

DS20006197C-page 15

Datasheet

AT24CM02

Memory Organization

6.

Memory Organization

The AT24CM02 is internally organized as 1,024 pages of 256 bytes each.

6.1

Device Addressing

Accessing the device requires an 8-bit device address byte following a Start condition to enable the device for a read

or write operation. Since multiple client devices can reside on the serial bus, each client device must have its own

unique address so the host can access each device independently.

The Most Significant four bits of the device address byte is referred to as the device type identifier. The device type

identifier ‘1010’ (Ah) is required in bits 7‑4 of the device address byte (see Table 6‑1).

Following the 4-bit device type identifier is the hardware client address bit, A2. This bit can be used to expand the

address space by allowing up to two Serial EEPROM devices on the same bus. The hardware client address bit

must correlate with the voltage level on the corresponding hardwired device address input pin A2. The A2 pin uses

an internal proprietary circuit that automatically biases the pin to a logic ‘0’ state if the pin is allowed to float. In

order to operate in a wide variety of application environments, the pull‑down mechanism is intentionally designed to

be somewhat strong. Once the pin is biased above the CMOS input buffer's trip point (~0.5 x VCC), the pull‑down

mechanism disengages. Microchip recommends connecting the A2 pin to a known state whenever possible.

Following the A2 hardware client address bit are A17 and A16 (bit 2 and bit 1 of the device address byte), which are

the Most Significant bits of the memory array word address (see Table 6‑1).

The eighth bit (bit 0) of the device address byte is the Read/Write Select bit. A read operation is initiated if this bit is

high and a write operation is initiated if this bit is low.

Upon the successful comparison of the device address byte, the AT24CM02 will return an ACK. If a valid comparison

is not made, the device will NACK.

Table 6-1.ꢀDevice Address Byte

Most Significant Bits

of the Word Address

Device Type Identifier

Hardware Client Address Bit

R/W Select

Package

Bit 7 Bit 6 Bit 5 Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

1

0

1

0

All Packages

A₂

A17

A16

R/W

For all operations except the current address read, two 8‑bit word address bytes must be transmitted to the device

immediately following the device address byte. The word address bytes contain the lower 16 significant memory

array address bits, and are used to specify which byte location in the EEPROM to start reading or writing. See Table

6-2 and Table 6-3 to review their bit positions.

Table 6-2.ꢀFirst Word Address Byte

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

A15

A14

A13

A12

A11

A10

A9

A8

Table 6-3.ꢀSecond Word Address Byte

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

A7

A6

A5

A4

A3

A2

A1

A0

DS20006197C-page 16

Datasheet

AT24CM02

Write Operations

7.

Write Operations

All write operations for the AT24CM02 begin with the host sending a Start condition, followed by a device address

byte with the R/W bit set to logic ‘0’, and then by the word address bytes. The data value(s) to be written to the

device immediately follow the word address bytes.

7.1

Byte Write

The AT24CM02 supports the writing of a single 8-bit byte. Selecting a data word in the AT24CM02 requires 18-bit

word address.

Upon receipt of the proper device address and the word address bytes, the EEPROM will send an Acknowledge. The

device will then be ready to receive the 8-bit data word. Following receipt of the 8‑bit data word, the EEPROM will

respond with an ACK. The addressing device, such as a bus host, must then terminate the write operation with a

Stop condition. At that time, the EEPROM will enter an internally self-timed write cycle, which will be completed within

t_WR, while the data word is being programmed into the nonvolatile EEPROM. All inputs are disabled during this write

cycle and the EEPROM will not respond until the write is complete.

Figure 7-1.ꢀByte Write

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

SCL

Device Address Byte

First Word Address Byte

1

0

1

0

A₂

A₁A16

0

A15 A14 A13 A12 A11 A10 A9 A8

MSb

0

SDA

MSb

Start Condition

by Host

ACK

from Client

ACK

from Client

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

Data Word

Second Word Address Byte

D7 D6 D5 D4 D3 D2 D1 D0

MSb

0

A7 A6 A5 A4 A3 A2 A1 A0

MSb

0

Stop Condition

by Host

ACK

from Client

ACK

from Client

7.2

Page Write

A page write operation allows up to 256 bytes to be written in the same write cycle, provided all bytes are in the same

row of the memory array (where address bits A17 through A8 are the same). Partial page writes of less than 256

bytes are also allowed.

A page write is initiated the same way as a byte write, but the bus host does not send a Stop condition after the first

data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the bus host can

transmit up to 255 additional data words. The EEPROM will respond with an ACK after each data word is received.

Once all data to be written has been sent to the device, the bus host must issue a Stop condition (see Figure 7-2) at

which time the internally self-timed write cycle will begin.

The lower eight bits of the word address are internally incremented following the receipt of each data word. The

higher order address bits are not incremented and retain the memory page row location. Page write operations are

limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. When

the incremented word address reaches the page boundary, the address counter will rollover to the beginning of the

same page. Nevertheless, creating a rollover event should be avoided as previously loaded data in the page could

become unintentionally altered.

DS20006197C-page 17

Datasheet

AT24CM02

Write Operations

Figure 7-2.ꢀ Page Write

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

SCL

Device Address Byte

A₂A₁A16

First Word Address Byte

1

0

1

0

A15 A14 A13 A12 A11 A10 A9 A8

MSb

0

SDA

MSb

Start Condition

by Host

ACK

from Client

ACK

from Client

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

Second Word Address Byte

Data Word (n)

Data Word (n+x), max of 256 without rollover

A7 A6 A5 A4 A3 A2 A1 A0

MSb

0

D7 D6 D5 D4 D3 D2 D1 D0

MSb

0

D7 D6 D5 D4 D3 D2 D1 D0

MSb

0

Stop Condition

ACK

by Host

ACK

from Client

7.3

Internal Writing Methodology

The AT24CM02 incorporates a built-in error detection and correction (EDC) logic scheme. The EEPROM array is

internally organized as a group of four connected 8-bit bytes plus an additional six ECC (Error Correction Code) bits

of EEPROM. These 38 bits are referred to as the internal physical data word. During a read sequence, the EDC logic

compares each 4-byte physical data word with its corresponding six ECC bits. If a single bit out of the 4-byte region

reads incorrectly, the EDC logic will detect the bad bit and replace it with a correct value before the data is serially

clocked out. This architecture significantly improves the reliability of the AT24CM02 compared to an implementation

that does not utilize EDC.

It is important to note that data is always physically written to the part at the internal physical data word level,

regardless of the number of bytes written. Writing single bytes is still possible with the byte write operation, but

internally, the other three bytes within that 4-byte location where the single byte was written, along with the six ECC

bits, will be updated. Due to this architecture, the AT24CM02 EEPROM write endurance is rated at the internal

physical data word level (4-byte word). The system designer needs to optimize the application writing algorithms to

observe these internal word boundaries in order to reach the endurance rating.

7.4

Acknowledge Polling

An Acknowledge Polling routine can be implemented to optimize time-sensitive applications that would prefer not to

wait the fixed maximum write cycle time (t_WR). This method allows the application to know immediately when the

Serial EEPROM write cycle has completed, so a subsequent operation can be started.

Once the internally self-timed write cycle has started, an Acknowledge Polling routine can be initiated. This involves

repeatedly sending a Start condition followed by a valid device address byte with the R/W bit set at logic ‘0’. The

device will not respond with an ACK while the write cycle is ongoing. Once the internal write cycle has completed, the

EEPROM will respond with an ACK, allowing a new read or write operation to be immediately initiated. A flowchart

has been included below in Figure 7-3 to better illustrate this technique.

DS20006197C-page 18

Datasheet

AT24CM02

Write Operations

Figure 7-3.ꢀAcknowledge Polling Flowchart

Send

Stop

condition

Send Start

condition followed

by a valid

Proceed to

next Read or

Write operation.

Did

the device

ACK?

Send any

Write

protocol.

YES

to initiate the

Write cycle.

Device Address

byte with R/W = 0.

NO

7.5

Write Cycle Timing

The length of the self-timed write cycle (t_WR) is defined as the amount of time from the Stop condition that begins the

internal write cycle to the Start condition of the first device address byte sent to the AT24CM02 that it subsequently

responds to with an ACK. Figure 7-4 has been included to show this measurement. During the internally self-timed

write cycle, any attempts to read from or write to the memory array will not be processed.

Figure 7-4.ꢀWrite Cycle Timing

SCL

SDA

8

9

Data Word n

D0

ACK

First Acknowledge from the device

to a valid device address sequence after

write cycle is initiated. The minimum t_WR

can only be determined through

t_WR

the use of an ACK Polling routine.

Stop

Start

Stop

Condition

7.6

Write Protection

The AT24CM02 utilizes a hardware data protection scheme that allows the user to write‑protect the entire memory

contents when the WP pin is at V_CC(or a valid V_IH). No write protection will be set if the WP pin is at GND or left

floating.

Table 7-1.ꢀAT24CM02 Write-Protect Behavior

WP Pin Voltage

Part of the Array Protected

Full Array

V_CC

GND

None － Write Protection Not Enabled

The status of the WP pin is sampled at the Stop condition for every byte write or page write operation prior to the

start of an internally self‑timed write cycle. Changing the WP pin state after the Stop condition has been sent will not

alter or interrupt the execution of the write cycle. The WP pin state must be valid with respect to the associated setup

(tSU.WP) and hold (tHD.WP) timing as shown in Figure 7-5 below. The WP setup time is the amount of time that

the WP state must be stable before the Stop condition is issued. The WP hold time is the amount of time after the

DS20006197C-page 19

Datasheet

AT24CM02

Write Operations

Stop condition that the WP must remain stable (see Table 4-3, AC Characteristics,” for timing specs for tHD.WP and

tSU.WP).

If an attempt is made to write to the device while the WP pin has been asserted, the device will acknowledge the

device address, word address and data bytes. However, no write cycle will occur when the Stop condition is issued.

The device will immediately be ready to accept a new read or write command.

Figure 7-5.ꢀWrite-Protect Setup and Hold Timing

DS20006197C-page 20

Datasheet

AT24CM02

Read Operations

8.

Read Operations

Read operations are initiated the same way as write operations with the exception that the Read/Write Select bit in

the device address byte must be a logic ‘1’. There are three read operations:

•

Current Address Read

Random Address Read

Sequential Read

8.1

Current Address Read

The internal data word address counter maintains the last address accessed during the last read or write operation,

incremented by one. This address stays valid between operations as long as the V_CCis maintained to the part. The

address rollover during a read is from the last byte of the last page to the first byte of the first page of the memory.

A current address read operation will output data according to the location of the internal data word address counter.

This is initiated with a Start condition, followed by a valid device address byte with the R/W bit set to logic ‘1’. The

device will ACK this sequence and the current address data word is serially clocked out on the SDA line. All types

of read operations will be terminated if the bus host does not respond with an ACK (it NACKs) during the ninth clock

cycle. After the NACK response, the host may send a Stop condition to complete the protocol or it can send a Start

condition to begin the next sequence.

Figure 8-1.ꢀCurrent Address Read

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

SCL

Device Address Byte

Data Word (n)

1

0

1

0

A₂

X

1

0

D7 D6 D5 D4 D3 D2 D1 D0

MSb

1

SDA

MSb

Start Condition

by Host

Stop Condition

by Host

from Host

ACK

from Client

NACK

8.2

Random Read

A random read begins in the same way as a byte write operation does to load in a new data word address. This is

known as a “dummy write” sequence; however, the data byte and the Stop condition of the byte write must be omitted

to prevent the part from entering an internal write cycle. Once the device address and word address are clocked in

and acknowledged by the EEPROM, the bus host must generate another Start condition. The bus host now initiates

a current address read by sending a Start condition, followed by a valid device address byte with the R/W bit set to

logic ‘1’. The EEPROM will ACK the device address and serially clock out the data word on the SDA line. All types

of read operations will be terminated if the bus host does not respond with an ACK (it NACKs) during the ninth clock

cycle. After the NACK response, the host may send a Stop condition to complete the protocol, or it can send a Start

condition to begin the next sequence.

DS20006197C-page 21

Datasheet

AT24CM02

Read Operations

Figure 8-2.ꢀRandom Read

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

SCL

Device Address Byte

First Word Address Byte

A14 A13 A12 A11 A10 A9 A8

Second Word Address Byte

1

0

1

0

A₂

A₁A16

0

A7 A6 A5 A4 A3 A2 A1 A0

MSb

0

A15

MSb

SDA

MSb

Start Condition

by Host

ACK

from Client

ACK

from Client

ACK

from Client

Dummy Write

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

Data Word (n)

Device Address Byte

A₂A₁

1

0

1

0

A₀

1

0

D7 D6 D5 D4 D3 D2 D1 D0

MSb

1

MSb

Start Condition

by Host

Stop Condition

by Host

ACK

from Client

NACK

from Host

8.3

Sequential Read

Sequential reads are initiated by either a current address read or a random read. After the bus host receives a data

word, it responds with an Acknowledge. As long as the EEPROM receives an ACK, it will continue to increment the

word address and serially clock out sequential data words. When the maximum memory address is reached, the data

word address will rollover and the sequential read will continue from the beginning of the memory array. All types of

read operations will be terminated if the bus host does not respond with an ACK (it NACKs) during the ninth clock

cycle. After the NACK response, the host may send a Stop condition to complete the protocol or it can send a Start

condition to begin the next sequence.

Figure 8-3.ꢀSequential Read

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

SCL

SDA

Device Address Byte

Data Word (n)

1

0

1

0

A

1

A8

1

0

D7 D6 D5 D4 D3 D2 D1 D0

MSb

0

2

MSb

Start

by

Host

ACK

from

Client

ACK

from

Host

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

Data Word (n+1)

Data Word (n+2)

Data Word (n+x)

D7 D6 D5 D4 D3 D2 D1 D0

MSb

0

D7 D6 D5 D4 D3 D2 D1 D0

MSb

0

D7 D6 D5 D4 D3 D2 D1 D0

MSb

1

Stop

by

Host

ACK

from

Host

ACK

from

Host

NACK

from

Host

DS20006197C-page 22

Datasheet

AT24CM02

Device Default Condition from Microchip

9.

Device Default Condition from Microchip

The AT24CM02 is delivered with the EEPROM array set to logic ‘1’, resulting in FFh data in all locations.

DS20006197C-page 23

Datasheet

AT24CM02

Packaging Information

10.

Packaging Information

10.1

Package Marking Information

AT24CM02: Package Marking Information

8-ball WLCSP

8-lead SOIC

ATMLUYWW

## % CO

YYWWNNN

ATMLHYWW

## % CO

YYWWNNN

Note 1:

designates pin 1

Note 2: Package drawings are not to scale

Catalog Number Truncation

AT24CM02

Truncation Code ##: 2H

Date Codes

Voltages

YY = Year

15: 2015

16: 2016

17: 2017

18: 2018

WW = Work Week of Assembly

% = Minimum Voltage

M: 1.7V min

D: 2.5V min

19: 2019

20: 2020

21: 2021

22: 2022

02: Week 2

04: Week 4

...

52: Week 52

Country of Origin

Device Grade

H or U: Industrial Grade

Atmel Truncation

AT: Atmel

CO = Country of Origin

ATM: Atmel

ATML: Atmel

Lot Number or Trace Code

NNN = Alphanumeric Trace Code (2 Characters for small packages)

DS20006197C-page 24

Datasheet

AT24CM02

Packaging Information

8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

2X

0.10 C A–B

D

A

D

NOTE 5

N

E

2

E1

2

E1

E

2X

0.10 C A–B

2X

0.10 C A–B

1

2

NOTE 1

e

NX b

0.25

C A–B D

B

NOTE 5

TOP VIEW

0.10 C

C

A2

A

SEATING

PLANE

8X

SIDE VIEW

A1

h

R0.13

h

H

0.23

L

SEE VIEW C

(L1)

VIEW A–A

VIEW C

Microchip Technology Drawing No. C04-057-SN Rev F Sheet 1 of 2

DS20006197C-page 25

Datasheet

AT24CM02

Packaging Information

8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units

MILLIMETERS

Dimension Limits

MIN

NOM

MAX

Number of Pins

Pitch

N

e

8

1.27 BSC

Overall Height

Molded Package Thickness

Standoff

Overall Width

A

-

1.75

-

0.25

A2

A1

E

1.25

0.10

§

6.00 BSC

Molded Package Width

Overall Length

E1

D

3.90 BSC

4.90 BSC

Chamfer (Optional)

Foot Length

h

L

0.25

0.40

-

0.50

1.27

Footprint

L1

1.04 REF

Foot Angle

Lead Thickness

Lead Width

Mold Draft Angle Top

Mold Draft Angle Bottom

0°

0.17

0.31

5°

-

8°

c

0.25

0.51

15°

b

5°

15°

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or

protrusions shall not exceed 0.15mm per side.

4. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

5. Datums A & B to be determined at Datum H.

Microchip Technology Drawing No. C04-057-SN Rev F Sheet 2 of 2

DS20006197C-page 26

Datasheet

AT24CM02

Packaging Information

8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

SILK SCREEN

C

Y1

X1

E

RECOMMENDED LAND PATTERN

Units

Dimension Limits

MILLIMETERS

NOM

MIN

MAX

Contact Pitch

E

C

X1

Y1

1.27 BSC

5.40

Contact Pad Spacing

Contact Pad Width (X8)

Contact Pad Length (X8)

0.60

1.55

Notes:

1. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing C04-2057-SN Rev F

DS20006197C-page 27

Datasheet

AT24CM02

Packaging Information

TOP VIEW

BOTTOM SIDE

k 0.015 (4X)

A

A1 CORNER

1 2

3 4

4 3

2 1

A

B

e1

E

C

D

C

D

e

db

d1

d2

D

m

d0.015

C

v

d

0.05

C A B

SIDE VIEW

A2

COMMON DIMENSIONS

(Unit of Measure = mm)

_{SEATING PLANE}A

-C-

SYMBOL

A

MIN

TYP

MAX

NOTE

A1

0.456

0.495

0.534

k 0.20

C

A1

A2

D

—

0.190

0.305

—

PIN ASSIGNMENT MATRIX

Contact Microchip for details.

1.00 BSC

d1

d2

E

1

2

3

4

1.40 BSC

A

B

C

D

n/a

SCL

n/a

V_CC

WP

n/a

NC

n/a

NC

A₂

Contact Microchip for details.

0.50 BSC

e

n/a

e1

b

2.10 BSC

SDA

GND

n/a

—

0.270

—

NC = Not Connected

Note: 1. Dimensions are NOT to scale.

2. Solder ball composition is 95.5Sn-4.0Ag-0.5Cu.

4/5/16

TITLE

GPC

DRAWING NO.

REV.

8U-18, 8-ball 4x4 Array, Custom Pitch

Wafer Level Chip Scale Package (WLCSP)

GQA

8U-18

01

Note:ꢀ For the most current package drawings, please see the Microchip Packaging Specification located at http://

www.microchip.com/packaging.

DS20006197C-page 28

Datasheet

AT24CM02

Revision History

11.

Revision History

Revision C (March 2021)

Corrected SOIC Package Type drawing. Updated the SOIC package drawing.

Revision B (December 2020)

Updated Revision History to latest template. Removed thin height WLCSP product offering. Replaced terminology

“Master” and “Slave” with “Host” and “Client”, respectively.

Revision A (May 2019)

Updated to Microchip template. Microchip DS20006197 replaces Atmel document 8812. Corrected t_LOWtypo from

400 ns to 500 ns. Corrected t_AAtypo from 550 ns to 450 ns. Updated Part Marking Information. Updated the

“Software Reset” section. Added ESD rating. Removed lead finish designation. Updated trace code format in

package markings. Updated section content throughout for clarification. Updated SOIC package drawing to Microchip

format.

Atmel Document 8828 Revision E (January 2017)

Updated Power-on Requirements and Reset Behavior section.

Atmel Document 8828 Revision D (May 2016)

Added the 8U-18 standard thickness WLCSP package option. Updated the “Clock and Data Transition

Requirements” section and the “DC Characteristics” table.

Atmel Document 8828 Revision C (November 2015)

Corrected 8-ball WLCSP pinout.

Atmel Document 8828 Revision B (August 2015)

Updated the 8U-11 package drawing, data retention discrepancy and 8-ball pinout.

Atmel Document 8828 Revision A (May 2015)

Initial document release.

DS20006197C-page 29

Datasheet

AT24CM02

The Microchip Website

Microchip provides online support via our website at www.microchip.com/. This website is used to make files and

information easily available to customers. Some of the content available includes:

•

Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s

guides and hardware support documents, latest software releases and archived software

General Technical Support – Frequently Asked Questions (FAQs), technical support requests, online

discussion groups, Microchip design partner program member listing

Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of

seminars and events, listings of Microchip sales offices, distributors and factory representatives

Product Change Notification Service

Microchip’s product change notification service helps keep customers current on Microchip products. Subscribers will

receive email notification whenever there are changes, updates, revisions or errata related to a specified product

family or development tool of interest.

To register, go to www.microchip.com/pcn and follow the registration instructions.

Customer Support

Users of Microchip products can receive assistance through several channels:

•

Distributor or Representative

Local Sales Office

Embedded Solutions Engineer (ESE)

Technical Support

Customers should contact their distributor, representative or ESE for support. Local sales offices are also available to

help customers. A listing of sales offices and locations is included in this document.

Technical support is available through the website at: www.microchip.com/support

DS20006197C-page 30

Datasheet

AT24CM02

Product Identification System

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

A T 2 4 C M 0 2 - S S H D - B

Shipping Carrier Option

B

T

E

= Bulk (Tubes)

= Tape and Reel, Standard Quantity Option

= Tape and Reel, Extended Quantity Option

Product Family

24C = Standard I²C-compatible

Serial EEPROM

Operating Voltage

D = 2.5V to 5.5V

M = 1.7V to 5.5V

Device Grade or

Wafer/Die Thickness

H or U = Industrial Temperature Range

(-40°C to +85°C)

Device Density

M = Megabit Family

02 = 2 Megabit

11

= 11mil Wafer Thickness

Package Option

SS

U2

= SOIC

= WLCSP

WWU = Wafer Unsawn

Examples

Package

Package Drawing

Code

Shipping

Carrier

Option

Package

Option

Device

Voltage

Device Grade

1.7V to

5.5V

Bulk

(Tubes)

AT24CM02‑SSHM‑B

AT24CM02‑SSHM‑T

AT24CM02‑SSHD‑B

AT24CM02‑SSHD‑T

AT24CM02‑U2UM‑T⁽¹⁾

Note:ꢀ

SOIC

SN

SS

U2

1.7V to

5.5V

Tape and

Reel

Industrial Temperature

(-40°C to +85°C)

2.5V to

5.5V

Bulk

(Tubes)

SOIC

SN

2.5V to

5.5V

Tape and

Reel

SOIC

SN

1.7V to

5.5V

Tape and

Reel

WLCSP

8U-18

1. CAUTION: Exposure to ultraviolet (UV) light can degrade the data stored in EEPROM cells. Therefore,

customers who use a WLCSP package or the product at a die level must ensure that exposure to ultraviolet

light does not occur.

Microchip Devices Code Protection Feature

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specifications contained in their particular Microchip Data Sheet.

Microchip believes that its family of products is secure when used in the intended manner and under normal

conditions.

•

There are dishonest and possibly illegal methods being used in attempts to breach the code protection features

of the Microchip devices. We believe that these methods require using the Microchip products in a manner

DS20006197C-page 31

Datasheet

AT24CM02

outside the operating specifications contained in Microchip’s Data Sheets. Attempts to breach these code

protection features, most likely, cannot be accomplished without violating Microchip’s intellectual property rights.

•

Microchip is willing to work with any customer who is concerned about the integrity of its code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of its code. Code

protection does not mean that we are guaranteeing the product is “unbreakable.” Code protection is constantly

evolving. We at Microchip are committed to continuously improving the code protection features of our products.

Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act.

If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue

for relief under that Act.

Legal Notice

Information contained in this publication is provided for the sole purpose of designing with and using Microchip

products. Information regarding device applications and the like is provided only for your convenience and may be

superseded by updates. It is your responsibility to ensure that your application meets with your specifications.

THIS INFORMATION IS PROVIDED BY MICROCHIP “AS IS”. MICROCHIP MAKES NO REPRESENTATIONS

OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY

OR OTHERWISE, RELATED TO THE INFORMATION INCLUDING BUT NOT LIMITED TO ANY IMPLIED

WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE

OR WARRANTIES RELATED TO ITS CONDITION, QUALITY, OR PERFORMANCE.

IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR

CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE

INFORMATION OR ITS USE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE

POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT ALLOWED BY LAW,

MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THE INFORMATION OR ITS USE

WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR

THE INFORMATION. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk,

and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or

expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual

property rights unless otherwise stated.

Trademarks

The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime,

BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox,

KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo,

MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip

Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer,

Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology

Incorporated in the U.S.A. and other countries.

AgileSwitch, APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed

Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC,

ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra,

TimeProvider, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, Augmented Switching,

BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController,

dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, Espresso T1S, EtherGREEN, IdealBridge,

In-Circuit Serial Programming, ICSP, INICnet, Intelligent Paralleling, Inter-Chip Connectivity, JitterBlocker, maxCrypto,

maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,

Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE,

Ripple Blocker, RTAX, RTG4, SAM-ICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SMART-I.S., storClad,

SQI, SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Total Endurance, TSHARC, USBCheck, VariSense,

VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, and ZENA are trademarks of Microchip Technology

Incorporated in the U.S.A. and other countries.

DS20006197C-page 32

Datasheet

AT24CM02

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of

Microchip Technology Inc. in other countries.

GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip

Technology Inc., in other countries.

All other trademarks mentioned herein are property of their respective companies.

©

ISBN: 978-1-5224-7822-5

AMBA, Arm, Arm7, Arm7TDMI, Arm9, Arm11, Artisan, big.LITTLE, Cordio, CoreLink, CoreSight, Cortex, DesignStart,

DynamIQ, Jazelle, Keil, Mali, Mbed, Mbed Enabled, NEON, POP, RealView, SecurCore, Socrates, Thumb,

TrustZone, ULINK, ULINK2, ULINK-ME, ULINK-PLUS, ULINKpro, µVision, Versatile are trademarks or registered

trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

Quality Management System

For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality.

DS20006197C-page 33

Datasheet

Worldwide Sales and Service

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

www.microchip.com/support

Web Address:

Australia - Sydney

Tel: 61-2-9868-6733

China - Beijing

India - Bangalore

Tel: 91-80-3090-4444

India - New Delhi

Tel: 91-11-4160-8631

India - Pune

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

Denmark - Copenhagen

Tel: 45-4485-5910

Tel: 86-10-8569-7000

China - Chengdu

Tel: 86-28-8665-5511

China - Chongqing

Tel: 86-23-8980-9588

China - Dongguan

Tel: 86-769-8702-9880

China - Guangzhou

Tel: 86-20-8755-8029

China - Hangzhou

Tel: 86-571-8792-8115

China - Hong Kong SAR

Tel: 852-2943-5100

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Japan - Tokyo

Tel: 358-9-4520-820

France - Paris

www.microchip.com

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Tel: 65-6334-8870

Taiwan - Hsin Chu

Tel: 886-3-577-8366

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Tel: 886-7-213-7830

Taiwan - Taipei

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Fax: 972-818-2924

Detroit

Tel: 972-9-744-7705

Italy - Milan

Tel: 86-186-6233-1526

China - Wuhan

Tel: 886-2-2508-8600

Thailand - Bangkok

Tel: 66-2-694-1351

Vietnam - Ho Chi Minh

Tel: 84-28-5448-2100

Tel: 39-0331-742611

Fax: 39-0331-466781

Italy - Padova

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Tel: 248-848-4000

Houston, TX

Tel: 86-27-5980-5300

China - Xian

Tel: 39-049-7625286

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Norway - Trondheim

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Tel: 281-894-5983

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Tel: 86-29-8833-7252

China - Xiamen

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Tel: 86-592-2388138

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Fax: 317-773-5453

Tel: 317-536-2380

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Poland - Warsaw

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Romania - Bucharest

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Fax: 949-462-9608

Tel: 951-273-7800

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Fax: 34-91-708-08-91

Sweden - Gothenberg

Tel: 46-31-704-60-40

Sweden - Stockholm

Tel: 46-8-5090-4654

UK - Wokingham

Tel: 919-844-7510

New York, NY

Tel: 631-435-6000

San Jose, CA

Tel: 408-735-9110

Tel: 408-436-4270

Canada - Toronto

Tel: 905-695-1980

Fax: 905-695-2078

Tel: 44-118-921-5800

Fax: 44-118-921-5820

DS20006197C-page 34

Datasheet


型号：	AT24CM-WWUUM-E
厂家：	MICROCHIP
描述：	IÂ²C-Compatible (Two-Wire) Serial EEPROM 2âMbit (262,144 x 8) 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件：	总34页 (文件大小：1325K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AT24CM-WWUUM-E [MICROCHIP]

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