AT24C64D-XHM-T [MICROCHIP]
IC EEPROM 64KBIT 1MHZ 8TSSOP;型号: | AT24C64D-XHM-T |
厂家: | MICROCHIP |
描述: | IC EEPROM 64KBIT 1MHZ 8TSSOP 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 双倍数据速率 光电二极管 内存集成电路 |
文件: | 总42页 (文件大小:1633K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
AT24C64D
I²C-Compatible (Two-Wire) Serial EEPROM 64-Kbit
(8,192 x 8)
Features
•
Low-Voltage Operation:
VCC = 1.7V to 5.5V
–
•
•
•
Internally Organized as 8,192 x 8 (64K)
Industrial Temperature Range: -40°C to +85°C
I2C-Compatible (Two-Wire) Serial Interface:
–
–
–
100 kHz Standard mode, 1.7V to 5.5V
400 kHz Fast mode, 1.7V to 5.5V
1 MHz Fast Mode Plus (FM+), 2.5V to 5.5V
•
•
•
•
•
Schmitt Triggers, Filtered Inputs for Noise Suppression
Bidirectional Data Transfer Protocol
Write-Protect Pin for Full Array Hardware Data Protection
Ultra Low Active Current (3 mA maximum) and Standby Current (6 µA maximum)
32-byte Page Write Mode:
–
Partial page writes allowed
•
•
•
•
Random and Sequential Read Modes
Self-Timed Write Cycle within 5 ms Maximum
ESD Protection > 4,000V
High Reliability:
–
–
Endurance: 1,000,000 write cycles
Data retention: 100 years
•
•
Green Package Options (Lead-free/Halide-free/RoHS compliant)
Die Sale Options: Wafer Form and Bumped Wafers
Packages
•
8-lead SOIC, 8-lead TSSOP, 8-pad UDFN, 8-ball VFBGA, 8-pad XDFN and 4‑ball/6‑ball WLCSP
DS20005937B-page 1
Datasheet
© 2018 Microchip Technology Inc.
AT24C64D
Table of Contents
Features.......................................................................................................................... 1
Packages.........................................................................................................................1
1. Package Types (not to scale).................................................................................... 4
2. Pin Descriptions.........................................................................................................5
2.1. Device Address Inputs (A0, A1, A2).............................................................................................5
2.2. Ground......................................................................................................................................... 5
2.3. Serial Data (SDA).........................................................................................................................5
2.4. Serial Clock (SCL)........................................................................................................................6
2.5. Write-Protect (WP)....................................................................................................................... 6
2.6. Device Power Supply................................................................................................................... 6
3. Description.................................................................................................................7
3.1. System Configuration Using Two-Wire Serial EEPROMs ...........................................................7
3.2. Block Diagram..............................................................................................................................8
4. Electrical Characteristics........................................................................................... 9
4.1. Absolute Maximum Ratings..........................................................................................................9
4.2. DC and AC Operating Range.......................................................................................................9
4.3. DC Characteristics....................................................................................................................... 9
4.4. AC Characteristics......................................................................................................................10
4.5. Electrical Specifications..............................................................................................................11
5. Device Operation and Communication....................................................................13
5.1. Clock and Data Transition Requirements...................................................................................13
5.2. Start and Stop Conditions.......................................................................................................... 13
5.3. Acknowledge and No-Acknowledge...........................................................................................14
5.4. Standby Mode............................................................................................................................ 14
5.5. Software Reset...........................................................................................................................15
6. Memory Organization.............................................................................................. 16
6.1. Device Addressing..................................................................................................................... 16
7. Write Operations......................................................................................................18
7.1. Byte Write...................................................................................................................................18
7.2. Page Write..................................................................................................................................18
7.3. Acknowledge Polling.................................................................................................................. 19
7.4. Write Cycle Timing..................................................................................................................... 20
7.5. Write Protection..........................................................................................................................20
8. Read Operations..................................................................................................... 21
8.1. Current Address Read................................................................................................................21
8.2. Random Read............................................................................................................................ 21
DS20005937B-page 2
Datasheet
© 2018 Microchip Technology Inc.
AT24C64D
8.3. Sequential Read.........................................................................................................................22
9. Device Default Condition from Microchip................................................................ 23
10. Packaging Information.............................................................................................24
10.1. Package Marking Information.....................................................................................................24
11. Revision History.......................................................................................................37
The Microchip Web Site................................................................................................ 38
Customer Change Notification Service..........................................................................38
Customer Support......................................................................................................... 38
Product Identification System........................................................................................39
Microchip Devices Code Protection Feature................................................................. 40
Legal Notice...................................................................................................................40
Trademarks................................................................................................................... 40
Quality Management System Certified by DNV.............................................................41
Worldwide Sales and Service........................................................................................42
DS20005937B-page 3
Datasheet
© 2018 Microchip Technology Inc.
AT24C64D
Package Types (not to scale)
1.
Package Types (not to scale)
8-Lead SOIC/TSSOP
(Top View)
8-Pad UDFN/XDFN
(Top View)
A0
1
2
8
7
VCC
A0
VCC
1
2
3
4
8
7
6
5
A1
A2
WP
A1
A2
WP
3
4
6
5
SCL
SDA
SCL
SDA
GND
GND
8-Ball VFBGA
(Top View)
1
2
3
4
8
7
6
5
VCC
A0
A1
A2
WP
SCL
GND
SDA
4-Ball WLCSP(1)
(Top View)
6-Ball WLCSP(1)
(Top View)
SDA
B1
B2
B3
A1
A2
A3
SCL
VCC
A1
B1
A2
B2
GND
SDA
GND
A2
WP
VCC
SCL
Note:ꢀ
1. For use of the 4‑ball and 6‑ball WLCSP packages, refer to Device Addressing for details about
setting the A2, A1 and A0 hardware address bits.
DS20005937B-page 4
Datasheet
© 2018 Microchip Technology Inc.
AT24C64D
Pin Descriptions
2.
Pin Descriptions
The descriptions of the pins are listed in Table 2-1.
Table 2-1.ꢀPin Function Table
Name
8‑Lead
SOIC
8‑Lead
TSSOP
8‑Pad
UDFN
8‑Pad
XDFN
8‑Ball
VFBGA
4‑Ball
WLCSP
6‑Ball
WLCSP
Function
(1)
(2)
(2)
(3)
A0
1
2
3
1
2
3
1
1
2
3
1
2
3
-
-
Device Address
Input
(3)
A1
2
3
-
-
-
Device Address
Input
(3)
A2
B3
Device Address
Input
GND
SDA
SCL
4
5
6
7
8
4
5
6
7
8
4
5
6
7
8
4
5
6
7
8
4
5
6
7
8
A2
B2
B1
-
B2
B1
A1
A2
A3
Ground
Serial Data
Serial Clock
Write-Protect
(3)
WP
V
A1
Device Power
Supply
CC
Note:ꢀ
1. The exposed pad on this package can be connected to GND or left floating.
2. For use of the 4‑ball and 6‑ball WLCSP packages, refer to Device Addressing for details about
setting the A2, A1 and A0 hardware address bits.
3. If the A0, A1, A2 and WP pins are not driven, they are internally pulled down to GND. In order to
operate in a wide variety of application environments, the pull‑down mechanism is intentionally
designed to be somewhat strong. Once these pins are biased above the CMOS input buffer’s trip
point (~0.5 x VCC), the pull‑down mechanism disengages. Microchip recommends connecting these
pins to a known state whenever possible.
2.1
Device Address Inputs (A0, A1, A2)
The A0, A1 and A2 pins are device address inputs that are hard-wired (directly to GND or to VCC) for
compatibility with other two-wire Serial EEPROM devices. When the pins are hard-wired, as many as
eight devices may be addressed on a single bus system. A device is selected when a corresponding
hardware and software match is true. If these pins are left floating, the A0, A1 and A2 pins will be
internally pulled down to GND. However, due to capacitive coupling that may appear in customer
applications, Microchip recommends always connecting the address pins to a known state. When using a
pull‑up resistor, Microchip recommends using 10 kΩ or less.
2.2
2.3
Ground
The ground reference for the power supply. GND should be connected to the system ground.
Serial Data (SDA)
The SDA pin is an open-drain bidirectional input/output pin used to serially transfer data to and from the
device. The SDA pin must be pulled high using an external pull-up resistor (not to exceed 10 kΩ in value)
and may be wire-ORed with any number of other open-drain or open-collector pins from other devices on
the same bus.
DS20005937B-page 5
Datasheet
© 2018 Microchip Technology Inc.
AT24C64D
Pin Descriptions
2.4
2.5
Serial Clock (SCL)
The SCL pin is used to provide a clock to the device and to control the flow of data to and from the
device. Command and input data present on the SDA pin is always latched in on the rising edge of SCL,
while output data on the SDA pin is clocked out on the falling edge of SCL. The SCL pin must either be
forced high when the serial bus is idle or pulled high using an external pull-up resistor.
Write-Protect (WP)
The write-protect input, when connected to GND, allows normal write operations. When the WP pin is
connected directly to VCC, all write operations to the protected memory are inhibited.
If the pin is left floating, the WP pin will be internally pulled down to GND. However, due to capacitive
coupling that may appear in customer applications, Microchip recommends always connecting the WP
pin to a known state. When using a pull‑up resistor, Microchip recommends using 10 kΩ or less.
Table 2-2.ꢀWrite-Protect
WP Pin Status
At VCC
Part of the Array Protected
Full Array
At GND
Normal Write Operations
2.6
Device Power Supply
The VCC pin is used to supply the source voltage to the device. Operations at invalid VCC voltages may
produce spurious results and should not be attempted.
DS20005937B-page 6
Datasheet
© 2018 Microchip Technology Inc.
AT24C64D
Description
3.
Description
The AT24C64D provides 65,536 bits of Serial Electrically Erasable and Programmable Read-Only
Memory (EEPROM) organized as 8,192 words of 8 bits each. The device’s cascading feature allows up to
eight devices to share a common two‑wire bus. The device is optimized for use in many industrial and
commercial applications where low‑power and low‑voltage operation are essential. The devices are
available in space‑saving 8‑lead SOIC, 8‑lead TSSOP, 8‑pad UDFN, 8‑pad XDFN, 8‑ball VFBGA and
4‑ball/6‑ball WLCSP packages. All packages operate from 1.7V to 5.5V.
3.1
System Configuration Using Two-Wire Serial EEPROMs
VCC
t
R(max)
R
R
PUP(max) =
PUP(min) =
0.8473 x C
L
V
- V
OL(max)
CC
V
CC
I
OL
SCL
SDA
WP
2
I C Bus Master:
Microcontroller
A0
A1
VCC
WP
A0
VCC
WP
A0
VCC
WP
A1
A1
Slave 0
Slave 1
Slave 7
AT24CXXX
AT24CXXX
AT24CXXX
A2
SDA
SCL
A2
SDA
SCL
A2
SDA
SCL
GND
GND
GND
GND
DS20005937B-page 7
Datasheet
© 2018 Microchip Technology Inc.
AT24C64D
Description
3.2
Block Diagram
DS20005937B-page 8
Datasheet
© 2018 Microchip Technology Inc.
AT24C64D
Electrical Characteristics
4.
Electrical Characteristics
4.1
Absolute Maximum Ratings
Temperature under bias
Storage temperature
VCC
-55°C to +125°C
-65°C to +150°C
6.25V
Voltage on any pin with respect to ground
DC output current
-1.0V to +7.0V
5.0 mA
ESD protection
>4 kV
Note:ꢀ Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operation listings of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
4.2
4.3
DC and AC Operating Range
Table 4-1.ꢀDC and AC Operating Range
AT24C64D
Operating Temperature (Case)
VCC Power Supply
Industrial Temperature Range
Low Voltage Grade
-40°C to +85°C
1.7V to 5.5V
DC Characteristics
Table 4-2.ꢀDC Characteristics
(1)
Parameter
Symbol
Minimum Typical
Maximum Units Test Conditions
5.5
1.0
Supply Voltage
Supply Current
Supply Current
Standby Current
V
1.7
—
—
—
—
—
—
0.4
2.0
—
V
CC1
CC1
CC2
I
I
mA
V
V
V
V
V
= 5.0V, Read at 400 kHz
= 5.0V, Write at 400 kHz
CC
CC
CC
CC
3.0
1.0
6.0
3.0
mA
μA
μA
μA
I
= 1.7V, V = V
IN
or GND
or GND
SB1
CC
CC
—
= 5.0V, V = V
IN
Input Leakage
Current
I
0.10
= V
or GND; V
= 5.0V
CC
LI
IN
CC
Output Leakage
Current
I
—
0.05
3.0
μA
V
V
= V
= 5.0V
or GND;
CC
LO
OUT
CC
Input Low Level
Input High Level
V
-0.6
—
—
V
x 0.3
V
V
Note 2
Note 2
IL
CC
V
V
x 0.7
CC
V
+ 0.5
IH
CC
DS20005937B-page 9
Datasheet
© 2018 Microchip Technology Inc.
AT24C64D
Electrical Characteristics
...........continued
Parameter
(1)
Minimum Typical
Symbol
Maximum Units Test Conditions
Output Low Level
Output Low Level
V
V
—
—
—
—
0.2
0.4
V
V
V
V
= 1.7V, I
= 0.15 mA
= 2.1 mA
OL1
OL2
CC
CC
OL
OL
= 3.0V, I
Note:ꢀ
1. Typical values characterized at TA = +25°C unless otherwise noted.
2. This parameter is characterized but is not 100% tested in production.
4.4
AC Characteristics
Table 4-3.ꢀAC Characteristics(1)
Parameter
Symbol
Fast Mode
Fast Mode Plus
Units
Vcc = 1.7V to 2.5V Vcc = 2.5V to 5.0V
Min.
—
Max.
400
—
Min.
—
Max.
1000
—
Clock Frequency, SCL
fSCL
tLOW
tHIGH
tI
kHz
ns
Clock Pulse Width Low
Clock Pulse Width High
Noise Suppression Time(2)
Clock Low to Data Out Valid
1300
600
—
500
400
—
—
—
ns
100
900
—
50
ns
tAA
50
50
450
—
ns
Bus Free Time between Stop and
Start(2)
tBUF
1300
500
ns
Start Hold Time
tHD.STA
tSU.STA
tHD.DAT
tSU.DAT
tR
600
600
0
—
—
250
250
0
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ms
Start Set‑up Time
Data In Hold Time
Data In Set‑up Time
Inputs Rise Time(2)
Inputs Fall Time(2)
Stop Set-up Time
Data Out Hold Time
Write Cycle Time
—
—
100
—
—
100
—
—
300
300
—
300
100
—
tF
—
—
tSU.STO
tDH
600
50
250
50
—
—
tWR
—
5
—
5
Note:ꢀ
1. AC measurement conditions:
–
RPUP (SDA bus line pull-up resistor to VCC): 1.3 kΩ (1000 kHz), 4 kΩ (400 kHz), 10 kΩ
(100 kHz)
–
–
Input pulse voltages: 0.3 VCC to 0.7 VCC
Input rise and fall times: ≤ 50 ns
DS20005937B-page 10
Datasheet
© 2018 Microchip Technology Inc.
AT24C64D
Electrical Characteristics
–
Input and output timing reference voltages: 0.5 x VCC
2. This parameter is ensured by characterization and is not 100% tested.
Figure 4-1.ꢀBus Timing
tHIGH
tF
tR
tLOW
SCL
tSU.STA
tHD.STA
tHD.DAT
tSU.DAT
tSU.STO
SDA In
tBUF
tAA
tDH
SDA Out
4.5
Electrical Specifications
4.5.1
Power-Up Requirements and Reset Behavior
During a power-up sequence, the VCC supplied to the AT24C64D should monotonically rise from GND to
the minimum VCC level, as specified in Table 4-1, with a slew rate no faster than 0.1 V/µs.
4.5.1.1 Device Reset
To prevent inadvertent write operations or any other spurious events from occurring during a power-up
sequence, the AT24C64D includes a Power-on Reset (POR) circuit. Upon power-up, the device will not
respond to any commands until the VCC level crosses the internal voltage threshold (VPOR) that brings the
device out of Reset and into Standby mode.
The system designer must ensure the instructions are not sent to the device until the VCC supply has
reached a stable value greater than or equal to the minimum VCC level. Additionally, once the VCC is
greater than or equal to the minimum VCC level, the bus master must wait at least tPUP before sending the
first command to the device. See Table 4-4 for the values associated with these power-up parameters.
Table 4-4.ꢀPower-up Conditions(1)
Symbol
Parameter
Min. Max. Units
tPUP
Time required after VCC is stable before the device can accept commands 100
-
1.5
-
µs
V
VPOR Power-on Reset Threshold Voltage
-
tPOFF Minimum time at VCC = 0V between power cycles
500
ms
Note:ꢀ
1. These parameters are characterized but they are not 100% tested in production.
If an event occurs in the system where the VCC level supplied to the AT24C64D drops below the
maximum VPOR level specified, it is recommended that a full power cycle sequence be performed by first
driving the VCC pin to GND, waiting at least the minimum tPOFF time and then performing a new power-up
sequence in compliance with the requirements defined in this section.
DS20005937B-page 11
Datasheet
© 2018 Microchip Technology Inc.
AT24C64D
Electrical Characteristics
4.5.2
Pin Capacitance
Table 4-5.ꢀPin Capacitance(1)
Symbol Test Condition
Max.
Units Conditions
CI/O
CIN
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2 and SCL)
8
6
pF
pF
VI/O = 0V
VIN = 0V
Note:ꢀ
1. This parameter is characterized but is not 100% tested in production.
4.5.3
EEPROM Cell Performance Characteristics
Table 4-6.ꢀEEPROM Cell Performance Characteristics
Operation
Test Condition
Min.
Max.
Units
Write Endurance(1)
TA = 25°C, VCC = 3.3V,
Page Write mode
1,000,000
—
Write Cycles
Data Retention(1)
TA = 55°C
100
—
Years
Note:ꢀ
1. Performance is determined through characterization and the qualification process.
DS20005937B-page 12
Datasheet
© 2018 Microchip Technology Inc.
AT24C64D
Device Operation and Communication
5.
Device Operation and Communication
The AT24C64D operates as a slave device and utilizes a simple I2C-compatible two-wire digital serial
interface to communicate with a host controller, commonly referred to as the bus master. The master
initiates and controls all read and write operations to the slave devices on the serial bus, and both the
master and the slave devices can transmit and receive data on the bus.
The serial interface is comprised of just two signal lines: Serial Clock (SCL) and Serial Data (SDA).
The SCL pin is used to receive the clock signal from the master, while the bidirectional SDA pin is used to
receive command and data information from the master as well as to send data back to the master.
Data is always latched into the AT24C64D on the rising edge of SCL and always output from the device
on the falling edge of SCL. Both the SCL and SDA pin incorporate integrated spike suppression filters
and Schmitt Triggers to minimize the effects of input spikes and bus noise.
All command and data information is transferred with the Most Significant bit (MSb) first. During bus
communication, one data bit is transmitted every clock cycle, and after eight bits (one byte) of data have
been transferred, the receiving device must respond with either an Acknowledge (ACK) or a
No-Acknowledge (NACK) response bit during a ninth clock cycle (ACK/NACK clock cycle) generated by
the master. Therefore, nine clock cycles are required for every one byte of data transferred. There are no
unused clock cycles during any read or write operation, so there must not be any interruptions or breaks
in the data stream during each data byte transfer and ACK or NACK clock cycle.
During data transfers, data on the SDA pin must only change while SCL is low, and the data must remain
stable while SCL is high. If data on the SDA pin changes while SCL is high, then either a Start or a Stop
condition will occur. Start and Stop conditions are used to initiate and end all serial bus communication
between the master and the slave devices. The number of data bytes transferred between a Start and a
Stop condition is not limited and is determined by the master. In order for the serial bus to be idle, both
the SCL and SDA pins must be in the logic-high state at the same time.
5.1
Clock and Data Transition Requirements
The SDA pin is an open-drain terminal and therefore must be pulled high with an external pull‑up resistor.
SCL is an input pin that can either be driven high or pulled high using an external pull‑up resistor. Data on
the SDA pin may change only during SCL low time periods. Data changes during SCL high periods will
indicate a Start or Stop condition as defined below. The relationship of the AC timing parameters with
respect to SCL and SDA for the AT24C64D are shown in the timing waveform in Figure 4-1. The AC
timing characteristics and specifications are outlined in AC Characteristics.
5.2
Start and Stop Conditions
5.2.1
Start Condition
A Start condition occurs when there is a high-to-low transition on the SDA pin while the SCL pin is at a
stable logic ‘1’ state and will bring the device out of Standby mode. The master uses a Start condition to
initiate any data transfer sequence; therefore, every command must begin with a Start condition.
The device will continuously monitor the SDA and SCL pins for a Start condition but will not respond
unless one is detected. Refer to Figure 5-1 for more details.
5.2.2
Stop Condition
A Stop condition occurs when there is a low-to-high transition on the SDA pin while the SCL pin is stable
in the logic ‘1’ state.
DS20005937B-page 13
Datasheet
© 2018 Microchip Technology Inc.
AT24C64D
Device Operation and Communication
The master can use the Stop condition to end a data transfer sequence with the AT24C64D, which will
subsequently return to Standby mode. The master can also utilize a repeated Start condition instead of a
Stop condition to end the current data transfer if the master will perform another operation. Refer to
Figure 5-1 for more details.
5.3
Acknowledge and No-Acknowledge
After every byte of data is received, the receiving device must confirm to the transmitting device that it
has successfully received the data byte by responding with what is known as an Acknowledge (ACK).
An ACK is accomplished by the transmitting device first releasing the SDA line at the falling edge of the
eighth clock cycle followed by the receiving device responding with a logic ‘0’ during the entire high period
of the ninth clock cycle.
When the AT24C64D is transmitting data to the master, the master can indicate that it is done receiving
data and wants to end the operation by sending a logic ‘1’ response to the AT24C64D instead of an ACK
response during the ninth clock cycle. This is known as a No-Acknowledge (NACK) and is accomplished
by the master sending a logic ‘1’ during the ninth clock cycle, at which point the AT24C64D will release
the SDA line so the master can then generate a Stop condition.
The transmitting device, which can be the bus master or the Serial EEPROM, must release the SDA line
at the falling edge of the eighth clock cycle to allow the receiving device to drive the SDA line to a logic ‘0’
to ACK the previous 8-bit word. The receiving device must release the SDA line at the end of the ninth
clock cycle to allow the transmitter to continue sending new data. A timing diagram has been provided in
Figure 5-1 to better illustrate these requirements.
Figure 5-1.ꢀStart Condition, Data Transitions, Stop Condition and Acknowledge
SDA
Must Be
Stable
SDA
Must Be
Stable
Acknowledge Window
1
2
8
9
SCL
SDA
Stop
Condition
Acknowledge
Valid
Start
Condition
The transmitting device (Master or Slave)
The receiver (Master or Slave)
SDA
Change
Allowed
SDA
Change
Allowed
must release the SDA line at this point to allow
the receiving device (Master or Slave) to drive the
SDA line low to ACK the previous 8-bit word.
must release the SDA line at
this point to allow the transmitter
to continue sending new data.
5.4
Standby Mode
The AT24C64D features a low‑power Standby mode that is enabled when any one of the following
occurs:
•
•
A valid power-up sequence is performed (see Power-Up Requirements and Reset Behavior).
A Stop condition is received by the device unless it initiates an internal write cycle (see Write
Operations).
•
At the completion of an internal write cycle (see Write Operations).
DS20005937B-page 14
Datasheet
© 2018 Microchip Technology Inc.
AT24C64D
Device Operation and Communication
5.5
Software Reset
After an interruption in protocol, power loss or system Reset, any two‑wire device can be protocol reset
by clocking SCL until SDA is released by the EEPROM and goes high. The number of clock cycles until
SDA is released by the EEPROM will vary. The software Reset sequence should not take more than nine
dummy clock cycles. Once the software Reset sequence is complete, new protocol can be sent to the
device by sending a Start condition followed by the protocol. Refer to Figure 5-2 for an illustration.
Figure 5-2.ꢀSoftware Reset
Dummy Clock Cycles
SCL
1
2
3
8
9
SDA Released
by EEPROM
Device is
Software Reset
SDA
In the event that the device is still non-responsive or remains active on the SDA bus, a power cycle must
be used to reset the device (see Power-Up Requirements and Reset Behavior).
DS20005937B-page 15
Datasheet
© 2018 Microchip Technology Inc.
AT24C64D
Memory Organization
6.
Memory Organization
The AT24C64D is internally organized as 256 pages of 32 bytes each.
6.1
Device Addressing
Accessing the device requires an 8‑bit device address byte following a Start condition to enable the
device for a read or write operation. Since multiple slave devices can reside on the serial bus, each slave
device must have its own unique address so the master can access each device independently.
The Most Significant four bits of the device address byte is referred to as the device type identifier. The
device type identifier ‘1010’ (Ah) is required in bits 7 through 4 of the device address byte (see Table
6-1).
Following the 4-bit device type identifier are the hardware slave address bits, A2, A1 and A0. These bits
can be used to expand the address space by allowing up to eight Serial EEPROM devices on the same
bus. These hardware slave address bits must correlate with the voltage level on the corresponding
hardwired device address input pins A0, A1 and A2. The A0, A1 and A2 pins use an internal proprietary
circuit that automatically biases the pin to a logic ‘0’ state if the pin is allowed to float. In order to operate
in a wide variety of application environments, the pull‑down mechanism is intentionally designed to be
somewhat strong. Once the pin is biased above the CMOS input buffer's trip point (~0.5 x VCC), the
pull‑down mechanism disengages. Microchip recommends connecting the A0, A1 and A2 pins to a known
state whenever possible.
When using the 6-ball WLCSP package, the A1 and A0 pins are not accessible and are left floating. The
previously mentioned automatic pull-down circuit will set this pin to a logic ‘0’ state. As a result, to
properly communicate with the device in the 6-ball WLCSP package, the A1 and A0 software bits must
always be set to logic ‘0’ for any operation. Refer to Table 6-1 to review these bit positions.
When using the 4-ball WLCSP package, the A2, A1 and A0 pins are not accessible and are left floating.
The previously mentioned automatic pull-down circuit will set this pin to a logic ‘0’ state. As a result, to
properly communicate with the device in the 4-ball WLCSP package, the A2, A1 and A0 software bits
must always be set to logic ‘0’ for any operation. Refer to Table 6-1 to review these bit positions.
The eighth bit (bit 0) of the device address byte is the Read/Write Select bit. A read operation is initiated if
this bit is high and a write operation is initiated if this bit is low.
Upon the successful comparison of the device address byte, the AT24C64D will return an ACK. If a valid
comparison is not made, the device will NACK.
Table 6-1.ꢀDevice Addressing
Package
Device Type Identifier
Hardware Slave
Address Bits
R/W Select
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
0
1
0
SOIC, TSSOP, UDFN,
XDFN, VFBGA
A2
A1
A0
R/W
1
1
0
0
1
1
0
0
0
0
0
0
0
4-ball WLCSP
6-ball WLCSP
R/W
R/W
A2
DS20005937B-page 16
Datasheet
© 2018 Microchip Technology Inc.
AT24C64D
Memory Organization
For all operations except the current address read, two 8‑bit word address bytes must be transmitted to
the device immediately following the device address byte. The word address bytes consist of the 13‑bit
memory array word address, and are used to specify which byte location in the EEPROM to start reading
or writing.
The first word address byte contains the five Most Significant bits of the word address (A12 through A8)
in bit positions four through zero, as seen in Table 6-2. The remainder of the first word address byte are
“don’t care” bits (in bit positions seven through five) as they are outside of the addressable 64‑Kbit range.
Upon completion of the first word address byte, the AT24C64D will return an ACK.
Table 6-2.ꢀFirst Word Address Byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
A12
A11
A10
A9
A8
Next, the second word address byte is sent to the device which provides the remaining eight bits of the
word address (A7 through A0). Upon completion of the second word address byte, the AT24C64D will
return an ACK. See Table 6-3 to review these bit positions.
Table 6-3.ꢀSecond Word Address Byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
A7
A6
A5
A4
A3
A2
A1
A0
DS20005937B-page 17
Datasheet
© 2018 Microchip Technology Inc.
AT24C64D
Write Operations
7.
Write Operations
All write operations for the AT24C64D begin with the master sending a Start condition, followed by a
device address byte with the R/W bit set to logic ‘0’, and then by the word address bytes. The data
value(s) to be written to the device immediately follow the word address bytes.
7.1
Byte Write
The AT24C64D supports the writing of a single 8-bit byte. Selecting a data word in the AT24C64D
requires 13-bit word address.
Upon receipt of the proper device address and the word address bytes, the EEPROM will send an
Acknowledge. The device will then be ready to receive the 8-bit data word. Following receipt of the 8‑bit
data word, the EEPROM will respond with an ACK. The addressing device, such as a bus master, must
then terminate the write operation with a Stop condition. At that time, the EEPROM will enter an internally
self-timed write cycle, which will be completed within tWR, while the data word is being programmed into
the nonvolatile EEPROM. All inputs are disabled during this write cycle, and the EEPROM will not
respond until the write is complete.
Figure 7-1.ꢀByte Write
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
SCL
SDA
Device Address Byte
First Word Address Byte
1
0
1
0
A2
A1
A0
0
0
X
X
X
A12 A11 A10 A9 A8
0
MSB
MSB
Start Condition
by Master
ACK
from Slave
ACK
from Slave
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
0
Data Word
Second Word Address Byte
D7 D6 D5 D4 D3 D2 D1 D0
MSB
A7 A6 A5 A4 A3 A2 A1 A0
MSB
0
Stop Condition
by Master
ACK
from Slave
ACK
from Slave
7.2
Page Write
A page write operation allows up to 32 bytes to be written in the same write cycle, provided all bytes are
in the same row of the memory array (where address bits A12 through A5 are the same). Partial page
writes of less than 32 bytes are also allowed.
A page write is initiated the same way as a byte write, but the bus master does not send a Stop condition
after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data
word, the bus master can transmit up to thirty one additional data words. The EEPROM will respond with
an ACK after each data word is received. Once all data to be written has been sent to the device, the bus
master must issue a Stop condition (see Figure 7-2) at which time the internally self-timed write cycle will
begin.
The lower five bits of the word address are internally incremented following the receipt of each data word.
The higher order address bits are not incremented and retain the memory page row location. Page write
DS20005937B-page 18
Datasheet
© 2018 Microchip Technology Inc.
AT24C64D
Write Operations
operations are limited to writing bytes within a single physical page, regardless of the number of bytes
actually being written. When the incremented word address reaches the page boundary, the address
counter will roll-over to the beginning of the same page. Nevertheless, creating a roll‑over event should
be avoided as previously loaded data in the page could become unintentionally altered.
Figure 7-2.ꢀ Page Write
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
SCL
Device Address Byte
A2 A1
First Word Address Byte
1
0
1
0
A0
0
0
X
X
X
A12 A11 A10 A9 A8
0
SDA
MSB
MSB
Start Condition
by Master
ACK
from Slave
ACK
from Slave
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
Second Word Address Byte
Data Word (n)
Data Word (n+x), max of 32 without rollover
A7 A6 A5 A4 A3 A2 A1 A0
MSB
0
D7 D6 D5 D4 D3 D2 D1 D0
MSB
D7 D6 D5 D4 D3 D2 D1 D0
MSB
0
Stop Condition
ACK by Master
from Slave
ACK
from Slave
ACK
from Slave
7.3
Acknowledge Polling
An Acknowledge Polling routine can be implemented to optimize time-sensitive applications that would
prefer not to wait the fixed maximum write cycle time (tWR). This method allows the application to know
immediately when the Serial EEPROM write cycle has completed, so a subsequent operation can be
started.
Once the internally self-timed write cycle has started, an Acknowledge Polling routine can be initiated.
This involves repeatedly sending a Start condition followed by a valid device address byte with the R/W
bit set at logic ‘0’. The device will not respond with an ACK while the write cycle is ongoing. Once the
internal write cycle has completed, the EEPROM will respond with an ACK, allowing a new read or write
operation to be immediately initiated. A flowchart has been included below in Figure 7-3 to better illustrate
this technique.
Figure 7-3.ꢀAcknowledge Polling Flowchart
Send
Stop
condition
to initiate the
Write cycle.
Send Start
condition followed
by a valid
Device Address
byte with R/W = 0.
Proceed to
next Read or
Write operation.
Did
the device
ACK?
Send any
Write
protocol.
YES
NO
DS20005937B-page 19
Datasheet
© 2018 Microchip Technology Inc.
AT24C64D
Write Operations
7.4
Write Cycle Timing
The length of the self-timed write cycle (tWR) is defined as the amount of time from the Stop condition that
begins the internal write cycle to the Start condition of the first device address byte sent to the AT24C64D
that it subsequently responds to with an ACK. Figure 7-4 has been included to show this measurement.
During the internally self-timed write cycle, any attempts to read from or write to the memory array will not
be processed.
Figure 7-4.ꢀWrite Cycle Timing
SCL
SDA
8
9
9
Data Word n
D0
ACK
ACK
First Acknowledge from the device
to a valid device address sequence after
write cycle is initiated. The minimum tWR
can only be determined through
tWR
the use of an ACK Polling routine.
Stop
Start
Stop
Condition
Condition
Condition
7.5
Write Protection
The AT24C64D utilizes a hardware data protection scheme that allows the user to write‑protect the entire
memory contents when the WP pin is at VCC (or a valid VIH). No write protection will be set if the WP pin
is at GND or left floating. The 4‑ball WLCSP version of the device does not include any write protection
features.
Table 7-1.ꢀAT24C64D Write-Protect Behavior
WP Pin Voltage
Part of the Array Protected
Full Array
VCC
GND
None - Write Protection Not Enabled
The status of the WP pin is sampled at the Stop condition for every byte write or page write operation
prior to the start of an internally self‑timed write cycle. Changing the WP pin state after the Stop condition
has been sent will not alter or interrupt the execution of the write cycle.
If an attempt is made to write to the device while the WP pin has been asserted, the device will
acknowledge the device address, word address and data bytes, but no write cycle will occur when the
Stop condition is issued. The device will immediately be ready to accept a new read or write command.
DS20005937B-page 20
Datasheet
© 2018 Microchip Technology Inc.
AT24C64D
Read Operations
8.
Read Operations
Read operations are initiated the same way as write operations with the exception that the Read/Write
Select bit in the device address byte must be a logic ‘1’. There are three read operations:
•
•
•
Current Address Read
Random Address Read
Sequential Read
8.1
Current Address Read
The internal data word address counter maintains the last address accessed during the last read or write
operation, incremented by one. This address stays valid between operations as long as the VCC is
maintained to the part. The address roll-over during a read is from the last byte of the last page to the first
byte of the first page of the memory.
A current address read operation will output data according to the location of the internal data word
address counter. This is initiated with a Start condition, followed by a valid device address byte with the
R/W bit set to logic ‘1’. The device will ACK this sequence and the current address data word is serially
clocked out on the SDA line. All types of read operations will be terminated if the bus master does not
respond with an ACK (it NACKs) during the ninth clock cycle. After the NACK response, the master may
send a Stop condition to complete the protocol, or it can send a Start condition to begin the next
sequence.
Figure 8-1.ꢀCurrent Address Read
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
SCL
Device Address Byte
Data Word (n)
1
0
1
0
A2
A1
A0
1
0
D7 D6 D5 D4 D3 D2 D1 D0
MSB
1
SDA
MSB
Start Condition
by Master
Stop Condition
NACK
by Master
from Master
ACK
from Slave
8.2
Random Read
A random read begins in the same way as a byte write operation does to load in a new data word
address. This is known as a “dummy write” sequence; however, the data byte and the Stop condition of
the byte write must be omitted to prevent the part from entering an internal write cycle. Once the device
address and word address are clocked in and acknowledged by the EEPROM, the bus master must
generate another Start condition. The bus master now initiates a current address read by sending a Start
condition, followed by a valid device address byte with the R/W bit set to logic ‘1’. The EEPROM will ACK
the device address and serially clock out the data word on the SDA line. All types of read operations will
be terminated if the bus master does not respond with an ACK (it NACKs) during the ninth clock cycle.
After the NACK response, the master may send a Stop condition to complete the protocol, or it can send
a Start condition to begin the next sequence.
DS20005937B-page 21
Datasheet
© 2018 Microchip Technology Inc.
AT24C64D
Read Operations
Figure 8-2.ꢀRandom Read
1
2
3
4
5
6
7
8
0
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
SCL
Device Address Byte
A2 A1
First Word Address Byte
A12 A11 A10 A9 A8
Second Word Address Byte
1
0
1
0
A0
0
X
X
X
0
A7 A6 A5 A4 A3 A2 A1 A0
MSB
0
SDA
MSB
MSB
Start Condition
by Master
ACK
from Slave
ACK
from Slave
ACK
from Slave
Dummy Write
1
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
Data Word (n)
Device Address Byte
A2 A1
0
1
0
A0
1
0
D7 D6 D5 D4 D3 D2 D1 D0
MSB
MSB
Start Condition
by Master
Stop Condition
by Master
ACK
from Slave
NACK
from Master
8.3
Sequential Read
Sequential reads are initiated by either a current address read or a random read. After the bus master
receives a data word, it responds with an Acknowledge. As long as the EEPROM receives an ACK, it will
continue to increment the word address and serially clock out sequential data words. When the maximum
memory address is reached, the data word address will roll-over and the sequential read will continue
from the beginning of the memory array. All types of read operations will be terminated if the bus master
does not respond with an ACK (it NACKs) during the ninth clock cycle. After the NACK response, the
master may send a Stop condition to complete the protocol, or it can send a Start condition to begin the
next sequence.
Figure 8-3.ꢀSequential Read
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
SCL
Device Address Byte
A2 A1
Data Word (n)
1
0
1
0
A0
1
0
D7 D6 D5 D4 D3 D2 D1 D0
MSB
0
SDA
MSB
Start Condition
by Master
ACK
from Slave
ACK
from Master
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
Data Word (n+1)
Data Word (n+2)
Data Word (n+x)
D7 D6 D5 D4 D3 D2 D1 D0
MSB
0
D7 D6 D5 D4 D3 D2 D1 D0
MSB
0
D7 D6 D5 D4 D3 D2 D1 D0
MSB
Stop Condition
ACK
from Master
ACK
from Master
NACK by Master
from Master
DS20005937B-page 22
Datasheet
© 2018 Microchip Technology Inc.
AT24C64D
Device Default Condition from Microchip
9.
Device Default Condition from Microchip
The AT24C64D is delivered with the EEPROM array set to logic ‘1’, resulting in FFh data in all locations.
DS20005937B-page 23
Datasheet
© 2018 Microchip Technology Inc.
AT24C64D
Packaging Information
10.
Packaging Information
10.1
Package Marking Information
AT24C64D: Package Marking Information
8-lead TSSOP
8-lead SOIC
8-pad XDFN
1.8 x 2.2 mm Body
ATMLHYWW
###% CO
YYWWNNN
ATHYWW
###%CO
YYWWNNN
###
NNN
8-ball VFBGA
8-pad UDFN
4 and 6-ball WLCSP
2.0 x 3.0 mm Body
1.5 x 2.0 mm Body
###
%U
###
NNN
###U
WNNN
H%
NNN
Note 1:
designates pin 1
Note 2: Package drawings are not to scale
Catalog Number Truncation
AT24C64D
Truncation Code ###: 64D
Date Codes
Voltages
YY = Year
16: 2016
17: 2017
18: 2018
19: 2019
Y = Year
6: 2016
7: 2017
8: 2018
9: 2019
WW = Work Week of Assembly
% = Minimum Voltage
M: 1.7V min
20: 2020
21: 2021
22: 2022
23: 2023
0: 2020
1: 2021
2: 2022
3: 2023
02: Week 2
04: Week 4
...
52: Week 52
Country of Origin
Device Grade
H or U: Industrial Grade
Atmel Truncation
CO = Country of Origin
AT: Atmel
ATM: Atmel
ATML: Atmel
Lot Number or Trace Code
NNN = Alphanumeric Trace Code (2 Characters for Small Packages)
DS20005937B-page 24
Datasheet
© 2018 Microchip Technology Inc.
AT24C64D
Packaging Information
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2X
0.10 C A–B
D
A
D
NOTE 5
N
E
2
E1
2
E1
E
1
2
NOTE 1
e
NX b
0.25
C A–B D
B
NOTE 5
TOP VIEW
0.10 C
0.10 C
C
A2
A
SEATING
PLANE
8X
SIDE VIEW
A1
h
R0.13
R0.13
h
H
0.23
L
SEE VIEW C
(L1)
VIEW A–A
VIEW C
Microchip Technology Drawing No. C04-057-SN Rev D Sheet 1 of 2
DS20005937B-page 25
Datasheet
© 2018 Microchip Technology Inc.
AT24C64D
Packaging Information
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
Number of Pins
Pitch
N
e
8
1.27 BSC
Overall Height
Molded Package Thickness
Standoff
Overall Width
A
-
-
-
-
1.75
-
0.25
A2
A1
E
1.25
0.10
§
6.00 BSC
Molded Package Width
Overall Length
E1
D
3.90 BSC
4.90 BSC
Chamfer (Optional)
Foot Length
h
L
0.25
0.40
-
-
0.50
1.27
Footprint
L1
1.04 REF
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
0°
0.17
0.31
5°
-
-
-
-
-
8°
c
0.25
0.51
15°
b
5°
15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.15mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
5. Datums A & B to be determined at Datum H.
Microchip Technology Drawing No. C04-057-SN Rev D Sheet 2 of 2
DS20005937B-page 26
Datasheet
© 2018 Microchip Technology Inc.
AT24C64D
Packaging Information
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
SILK SCREEN
C
Y1
X1
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
MILLIMETERS
NOM
MIN
MAX
Contact Pitch
E
C
X1
Y1
1.27 BSC
5.40
Contact Pad Spacing
Contact Pad Width (X8)
Contact Pad Length (X8)
0.60
1.55
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2057-SN Rev B
DS20005937B-page 27
Datasheet
© 2018 Microchip Technology Inc.
AT24C64D
Packaging Information
8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
N
E
E1
NOTE 1
1
2
b
e
c
φ
A
A2
A1
L
L1
Units
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
Number of Pins
Pitch
N
e
8
0.65 BSC
Overall Height
A
–
–
1.20
1.05
0.15
Molded Package Thickness
Standoff
A2
A1
E
0.80
0.05
1.00
–
Overall Width
6.40 BSC
Molded Package Width
Molded Package Length
Foot Length
E1
D
4.30
2.90
0.45
4.40
4.50
3.10
0.75
3.00
L
0.60
Footprint
L1
φ
1.00 REF
Foot Angle
0°
–
–
–
8°
Lead Thickness
c
0.09
0.20
0.30
Lead Width
b
0.19
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-086B
DS20005937B-page 28
Datasheet
© 2018 Microchip Technology Inc.
AT24C64D
Packaging Information
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20005937B-page 29
Datasheet
© 2018 Microchip Technology Inc.
AT24C64D
Packaging Information
8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (Q4B) - 2x3 mm Body [UDFN]
Atmel Legacy YNZ Package
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
B
E
N
(DATUM A)
(DATUM B)
NOTE 1
2X
0.10 C
1
2
2X
TOP VIEW
0.10 C
A1
0.10 C
0.08 C
C
A
SEATING
PLANE
8X
(A3)
SIDE VIEW
0.10
C A B
D2
e
2
1
2
0.10
K
C A B
E2
N
L
8X b
0.10
0.05
C A B
C
e
BOTTOM VIEW
Microchip Technology Drawing C04-21355-Q4B Rev A Sheet 1 of 2
DS20005937B-page 30
Datasheet
© 2018 Microchip Technology Inc.
AT24C64D
Packaging Information
8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (Q4B) - 2x3 mm Body [UDFN]
Atmel Legacy YNZ Package
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
MILLIMETERS
NOM
MIN
MAX
Number of Terminals
Pitch
Overall Height
Standoff
Terminal Thickness
Overall Length
Exposed Pad Length
Overall Width
Exposed Pad Width
Terminal Width
Terminal Length
N
8
e
0.50 BSC
0.55
0.02
0.152 REF
2.00 BSC
1.50
3.00 BSC
1.30
A
A1
A3
D
D2
E
E2
b
L
0.50
0.00
0.60
0.05
1.40
1.60
1.20
0.18
0.35
0.20
1.40
0.30
0.45
-
0.25
0.40
-
Terminal-to-Exposed-Pad
K
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-21355-Q4B Rev A Sheet 2 of 2
DS20005937B-page 31
Datasheet
© 2018 Microchip Technology Inc.
AT24C64D
Packaging Information
8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (Q4B) - 2x3 mm Body [UDFN]
Atmel Legacy YNZ Package
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
X2
EV
G2
8
ØV
C
Y2
G1
Y1
1
2
SILK SCREEN
X1
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
MILLIMETERS
NOM
0.50 BSC
MIN
MAX
Contact Pitch
Optional Center Pad Width
Optional Center Pad Length
Contact Pad Spacing
X2
Y2
C
1.60
1.40
2.90
Contact Pad Width (X8)
Contact Pad Length (X8)
Contact Pad to Center Pad (X8)
Contact Pad to Contact Pad (X6)
Thermal Via Diameter
X1
Y1
G1
G2
V
0.30
0.85
0.20
0.33
0.30
1.00
Thermal Via Pitch
EV
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing C04-21355-Q4B Rev A
DS20005937B-page 32
Datasheet
© 2018 Microchip Technology Inc.
AT24C64D
Packaging Information
d
0.10 (4X)
d
0.08 C
f
0.10
C
A
E
C
D
2.
b
j
j
n 0.15m
0.08m
C
C
A B
n
B
PIN 1 BALL PAD CORNER
A1
A2
A
TOP VIEW
SIDE VIEW
PIN 1 BALL PAD CORNER
4
3
1
2
d
(d1)
6
5
8
7
COMMON DIMENSIONS
(Unit of Measure - mm)
e
(e1)
SYMBOL
NOM
MIN
MAX
NOTE
0.73
0.09
0.40
0.20
0.79
0.85
0.19
0.50
0.30
A
A1
A2
b
BOTTOM VIEW
8 SOLDER BALLS
0.14
0.45
Notes:
1. This drawing is for general information only.
0.25
2
1.50 BSC
2.0 BSC
0.50 BSC
0.25 REF
1.00 BSC
0.25 REF
D
E
2. Dimension ‘b’ is measured at maximum solder ball diameter.
3. Solder ball composition shall be 95.5Sn-4.0Ag-.5Cu.
e
e1
d
d1
7/1/14
REV.
TITLE
DRAWING NO.
8U3-1
GPC
GXU
8U3-1, 8-ball, 1.50mm x 2.00mm body, 0.50mm pitch,
Very Thin, Fine-Pitch Ball Grid Array Package (VFBGA)
G
Note:ꢀ For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging.
DS20005937B-page 33
Datasheet
© 2018 Microchip Technology Inc.
AT24C64D
Packaging Information
D
5
7
6
8
E
PIN #1 ID
2
4
1
3
A1
Top View
A
Side View
e1
b
L
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
–
NOM
–
MAX
0.40
0.05
1.90
2.30
0.25
NOTE
A
A1
D
E
0.10
PIN #1 ID
0.00
1.70
2.10
0.15
–
1.80
0.15
2.20
b
0.20
b
e
0.40 TYP
1.20 REF
0.30
e
e1
L
0.35
0.26
End View
9/10/2012
TITLE
DRAWING NO.
REV.
GPC
8ME1, 8-pad (1.80mm x 2.20mm body)
Extra Thin DFN (XDFN)
8ME1
B
DTP
Note:ꢀ For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging.
DS20005937B-page 34
Datasheet
© 2018 Microchip Technology Inc.
AT24C64D
Packaging Information
k 0.015 (4X)
TOP VIEW
BOTTOM VIEW
A
1
2
2
1
A1 CORNER
A1 CORNER
A
A
e1
E
B
B
B
d
b (4X)
d1
D
m
d0.015
d0.05
C
v
m
C A B
SIDE VIEW
A3
A2
A
SEATING PLANE
COMMON DIMENSIONS
(Unit of Measure = mm)
-C-
k 0.075 C
A1
MIN
MAX
TYP
NOTE
SYMBOL
A
A1
A2
A3
D
0.260
0.080
0.160
0.295
0.095
0.330
0.110
0.190
PIN ASSIGNMENT MATRIX
0.175
2
1
0.025 REF
3
Contact Microchip for details
0.400 BSC
A
B
V
CC
GND
d1
E
SCL SDA
Contact Microchip for details
0.400 BSC
e1
b
0.170
0.185
0.200
Note: 1. Dimensions are NOT to scale.
2. Solder ball composition is 95.5Sn-4.0Ag-0.5Cu.
3. Product offered with Back Side Coating (BSC)
2/14/18
TITLE
DRAWING NO.
REV.
GPC
4U-12, 4-ball, 2x2 Array, 0.40mm Pitch
GVF
4U-12
B
Wafer Level Chip Scale Package (WLCSP) with BSC
Note:ꢀ For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging.
DS20005937B-page 35
Datasheet
© 2018 Microchip Technology Inc.
AT24C64D
Packaging Information
TOP VIEW
2
BOTTOM SIDE
A
D
A1 CORNER
A1 CORNER
1
3
3
2
1
k 0.015 C
A
A
B
d1
B
db
e1
B
E
d0.015 m C
v
0.05
d
m C A B
SIDE VIEW
A3
A
A2
SEATING PLANE
C
A1
k 0.075 C
PIN ASSIGNMENT MATRIX
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
MAX
TYP
NOTE
SYMBOL
1
2
3
A
A1
A2
A3
D
0.260
0.080
0.160
0.295
0.095
0.330
0.110
0.190
SCL
SDA
WP
GND
VCC
A2
A
B
0.175
0.025 REF
3
Contact Microchip for details
0.40 BSC
d1
E
Contact Microchip for details
0.40 BSC
e1
b
0.170
0.185
0.200
Note: 1. Dimensions are NOT to scale.
2. Solder ball composition is 95.5Sn-4.0Ag-0.5Cu.
3. Product offered with Back Side Coating (BSC)
5/6/15
TITLE
GPC
DRAWING NO.
REV.
6U-2, 6-ball, 2x3 Array, 0.40mm pitch
Wafer Level Chip Scale Package (WLCSP) with BSC
GMK
6U-2
C
Note:ꢀ For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging.
DS20005937B-page 36
Datasheet
© 2018 Microchip Technology Inc.
AT24C64D
Revision History
11.
Revision History
Revision B (November 2018)
Corrected tPOFF typo from 1 ms to 500 ms. Updated the "Bus Timing" figure. Updated the section content
throughout for clarification. Replaced the 8U2-1 VFBGA Package Outline Drawing with the 8U3-1 VFBGA
Package Outline Drawing. Updated the SOIC, TSSOP and UDFN package drawings to Microchip format.
Corrected Revision A history to further document changes.
Revision A (February 2018)
Updated to the Microchip template. Microchip DS20005937 replaces Atmel document 8805. Corrected
tLOW typo from 400ns to 500ns. Corrected tAA typo from 550ns to 450ns. Updated Package Marking
Information. Removed the 5‑ball WLCSP detail and ordering code. Updated Package Drawing 4U-12.
Updated Product ID System. Updated the “Software Reset” section. Added ESD rating. Removed lead
finish designation. Updated trace code format in package markings. Updated section content throughout
for clarification. Added a figure for “System Configuration Using 2‑Wire Serial EEPROMs”. Added POR
recommendations section.
Atmel Document 8805 Revision D (May 2015)
Added the 4‑ball WLCSP, AT24C64D‑U2UM0B‑T option. Updated the 8S1 package drawing.
Atmel Document 8805 Revision C (February 2015)
Updated the 6‑ball and 5‑ball WLCSP package outline drawings to reflect offering of product with
backside coating.
Atmel Document 8805 Revision B (December 2014)
Added the AT24C64D‑MAHM‑E product offering. Updated the 8X, 8MA2, 5U‑2, and 8U2‑1 package
outline drawings and the ordering information.
Atmel Document 8805 Revision A (June 2013)
Initial document release.
DS20005937B-page 37
Datasheet
© 2018 Microchip Technology Inc.
AT24C64D
The Microchip Web Site
Microchip provides online support via our web site at http://www.microchip.com/. This web site is used as
a means to make files and information easily available to customers. Accessible by using your favorite
Internet browser, the web site contains the following information:
•
Product Support – Data sheets and errata, application notes and sample programs, design
resources, user’s guides and hardware support documents, latest software releases and archived
software
•
•
General Technical Support – Frequently Asked Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant program member listing
Business of Microchip – Product selector and ordering guides, latest Microchip press releases,
listing of seminars and events, listings of Microchip sales offices, distributors and factory
representatives
Customer Change Notification Service
Microchip’s customer notification service helps keep customers current on Microchip products.
Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata
related to a specified product family or development tool of interest.
To register, access the Microchip web site at http://www.microchip.com/. Under “Support”, click on
“Customer Change Notification” and follow the registration instructions.
Customer Support
Users of Microchip products can receive assistance through several channels:
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Customers should contact their distributor, representative or Field Application Engineer (FAE) for support.
Local sales offices are also available to help customers. A listing of sales offices and locations is included
in the back of this document.
Technical support is available through the web site at: http://www.microchip.com/support
DS20005937B-page 38
Datasheet
© 2018 Microchip Technology Inc.
AT24C64D
Product Identification System
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
A T 2 4 C 6 4 D - S S H M x x - B
Shipping Carrier Option
B
T
E
= Bulk (Tubes)
= Tape and Reel, Standard Quantity Option
= Tape and Reel, Extended Quantity Option
Product Family
24C = Standard I2C-compatible
Serial EEPROM
Product Variation
xx = Applies to select packages only.
Operating Voltage
M = 1.7V to 5.5V
Device Density
64= 64 Kilobit
Device Grade or
Wafer/Die Thickness
H or U = Industrial Temperature Range
(-40°C to +85°C)
Device Revision
11
= 11mil Wafer Thickness
Package Option
SS = SOIC
X
= TSSOP
MA = 2.0mm x 3.0mm UDFN
ME = 1.5mm x 2.0mm XDFN
U
U2
C
= 6-ball, 2x3 Grid Array, WLCSP
= 4-ball, 2x2 Grid Array, WLCSP
= VFBGA
WWU = Wafer Unsawn
Examples
Device
Package Package Package Shipping Carrier Option
Device Grade
Drawing Option
Code
AT24C64D‑SSHM‑B
AT24C64D‑SSHM‑T
AT24C64D‑XHM‑T
AT24C64D‑MAHM‑T
AT24C64D‑MAHM‑E
SOIC
SOIC
SN
SN
SS
SS
X
Bulk (Tubes)
Tape and Reel
Tape and Reel
Tape and Reel
Industrial
Temperature
(-40°C to +85°C)
TSSOP
UDFN
UDFN
ST
Q4B
Q4B
MA
MA
Extended Qty. Tape and
Reel
AT24C64D‑MEHM‑T
AT24C64D‑CUM‑T
AT24C64D‑UUM0B‑T
XDFN
VFBGA
WLCSP
8ME1
8U3‑1
6U‑2
ME
C
Tape and Reel
Tape and Reel
Tape and Reel
Tape and Reel
U
AT24C64D‑U2UM0B‑T WLCSP
4U‑12
U2
DS20005937B-page 39
Datasheet
© 2018 Microchip Technology Inc.
AT24C64D
Microchip Devices Code Protection Feature
Note the following details of the code protection feature on Microchip devices:
•
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the
market today, when used in the intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of
these methods, to our knowledge, require using the Microchip products in a manner outside the
operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is
engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their
code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the
code protection features of our products. Attempts to break Microchip’s code protection feature may be a
violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software
or other copyrighted work, you may have a right to sue for relief under that Act.
Legal Notice
Information contained in this publication regarding device applications and the like is provided only for
your convenience and may be superseded by updates. It is your responsibility to ensure that your
application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY
OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS
CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE.
Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life
support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend,
indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting
from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual
property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BitCloud,
chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq,
Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, SAM-BA, SpyNIC, SST,
SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight
Load, IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom,
CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM,
dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming,
ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi,
DS20005937B-page 40
Datasheet
© 2018 Microchip Technology Inc.
AT24C64D
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient
Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE,
Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are
trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their respective companies.
©
2018, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-3817-5
Quality Management System Certified by DNV
ISO/TS 16949
Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer
fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC®
DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design and manufacture of development
systems is ISO 9001:2000 certified.
DS20005937B-page 41
Datasheet
© 2018 Microchip Technology Inc.
Worldwide Sales and Service
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DS20005937B-page 42
Datasheet
© 2018 Microchip Technology Inc.
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