93C56AESN [MICROCHIP]
2K 5.0V Automotive Temperature Microwire Serial EEPROM; 2K 5.0V汽车温度Microwire串行EEPROM
| 型号： | 93C56AESN |
| 厂家： | 
MICROCHIP |
| 描述： | 2K 5.0V Automotive Temperature Microwire Serial EEPROM |
| 文件： | 总12页 (文件大小：169K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M
93C56A/B
2K 5.0V Automotive Temperature Microwire® Serial EEPROM
FEATURES
PACKAGE TYPE
PDIP
• Single supply 5.0V operation
• Low power CMOS technology
- 1 mA active current (typical)
- 1 µA standby current (maximum)
• 256 x 8 bit organization (93C56A)
• 128 x 16 bit organization (93C56B)
• Self-timed ERASE and WRITE cycles (including
auto-erase)
VCC
CS
CLK
DI
1
2
8
7
NC
NC
VSS
3
4
6
5
DO
• Automatic ERAL before WRAL
• Power on/off data protection circuitry
• Industry standard 3-wire serial interface
• Device status signal during ERASE/WRITE
cycles
• Sequential READ function
• 100,000 E/W cycles guaranteed
• Data retention > 200 years
SOIC
1
8
VCC
CS
CLK
2
3
4
7
6
5
NC
NC
VSS
DI
DO
• 8-pin PDIP and SOIC packages
• Available for the following temperature ranges:
BLOCK DIAGRAM
- Automotive (E):
-40°C to +125°C
DESCRIPTION
ADDRESS
DECODER
MEMORY
ARRAY
The Microchip Technology Inc. 93C56A/B is a 2K-bit,
low-voltage serial Electrically Erasable PROM. The
device memory is configured as 256 x 8 bits (93C56A)
or 128 x 16 bits (93C56B). Advanced CMOS technol-
ogy makes this device ideal for low-power, nonvolatile
memory applications. The 93C56A/B is available in
standard 8-pin DIP and surface mount SOIC packages.
This device is only recommeded for 5V automotive
temperature applications. For all commercial and
industrial applications, the 93LC56A/B is recom-
mended.
ADDRESS
COUNTER
DATA
OUTPUT
BUFFER
DO
REGISTER
DI
MEMORY
DECODE
LOGIC
CS
VCC
VSS
CLOCK
GENERATOR
CLK
Microwire is a registered trademark of National Semiconductor.
1998 Microchip Technology Inc.
Preliminary
DS21206B-page 1
93C56A/B
TABLE 1-1:
Name
PIN FUNCTION TABLE
Function
1.0
ELECTRICAL
CHARACTERISTICS
CS
CLK
DI
Chip Select
1.1
Maximum Ratings*
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
VCC ...................................................................................7.0V
All inputs and outputs w.r.t. VSS ................ -0.6V to Vcc +1.0V
Storage temperature .....................................-65°C to +150°C
Ambient temp. with power applied.................-65°C to +125°C
Soldering temperature of leads (10 seconds) .............+300°C
ESD protection on all pins................................................4 kV
DO
VSS
NC
VCC
No Connect
Power Supply
*Notice: Stresses above those listed under “Maximum ratings” may
cause permanent damage to the device.This is a stress rating only and
functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is
not implied. Exposure to maximum rating conditions for extended peri-
ods may affect device reliability.
TABLE 1-2:
DC AND AC ELECTRICAL CHARACTERISTICS
Automotive (E)VCC = +4.5V to +5.5VTamb = -40°C to +125°C
All parameters apply over the
specified operating ranges
unless otherwise noted
Parameter
Symbol
Min.
Max.
Units
Conditions
High level input voltage
Low level input voltage
Low level output voltage
High level output voltage
Input leakage current
Output leakage current
VIH
VIL
2.0
-0.3
—
VCC +1
0.8
V
V
(Note 2)
VOL
VOH
ILI
0.4
V
IOL = 2.1 mA; VCC = 4.5V
IOH = -400 µA; VCC = 4.5V
VIN = VSS to VCC
2.4
-10
-10
—
V
10
µA
µA
ILO
10
VOUT = VSS to VCC
Pin capacitance
(all inputs/outputs)
VIN/VOUT = 0 V (Notes 1 & 2)
Tamb = +25°C, FCLK = 1 MHz
CIN, COUT
—
7
pF
ICC write
ICC read
ICCS
FCLK
TCKH
TCKL
TCSS
TCSH
TCSL
TDIS
TDIH
TPD
—
—
1.5
1
mA
mA
µA
MHz
ns
Operating current
Standby current
—
1
CS = VSS
Clock frequency
—
2
Clock high time
250
250
50
—
—
—
—
—
—
—
400
100
500
2
Clock low time
ns
Chip select setup time
Chip select hold time
Chip select low time
Data input setup time
Data input hold time
Data output delay time
Data output disable time
Status valid time
ns
Relative to CLK
Relative to CLK
0
ns
250
100
100
—
ns
ns
Relative to CLK
Relative to CLK
CL = 100 pF
ns
ns
TCZ
—
ns
CL = 100 pF (Note 2)
CL = 100 pF
TSV
—
ns
TWC
TEC
—
ms
ms
ms
ERASE/WRITE mode
ERAL mode
Program cycle time
—
6
TWL
—
15
—
WRAL mode
Endurance
—
100K
cycles 25°C, VCC = 5.0V, Block Mode (Note 3)
Note 1: This parameter is tested at Tamb = 25°C and FCLK = 1 MHz.
2: This parameter is periodically sampled and not 100% tested.
3: This application is not tested but guaranteed by characterization. For endurance estimates in a specific
application, please consult the Total Endurance Model which may be obtained on Microchip’s BBS or web-
site.
DS21206B-page 2
Preliminary
1998 Microchip Technology Inc.
93C56A/B
CLK cycles are not required during the self-timed
WRITE (i.e., auto ERASE/WRITE) cycle.
2.0
PIN DESCRIPTION
2.1
Chip Select (CS)
After detecting a START condition, the specified num-
ber of clock cycles (respectively low to high transitions
of CLK) must be provided. These clock cycles are
required to clock in all required opcode, address, and
data bits before an instruction is executed (Table 2-1
and Table 2-2). CLK and DI then become don't care
inputs waiting for a new START condition to be
detected.
A high level selects the device. A low level deselects
the device and forces it into standby mode. However, a
programming cycle which is already in progress will be
completed, regardless of the CS input signal. If CS is
brought low during a program cycle, the device will go
into standby mode as soon as the programming cycle
is completed.
Note: CS must go low between consecutive
CS must be low for 250 ns minimum (TCSL) between
consecutive instructions. If CS is low, the internal con-
trol logic is held in a RESET status.
instructions.
2.3
Data In (DI)
2.2
Serial Clock (CLK)
Data In is used to clock in a START bit, opcode,
address, and data synchronously with the CLK input.
The Serial Clock is used to synchronize the communi-
cation between a master device and the 93C56A/B.
Opcode, address, and data bits are clocked in on the
positive edge of CLK. Data bits are also clocked out on
the positive edge of CLK.
2.4
Data Out (DO)
Data Out is used in the READ mode to output data syn-
chronously with the CLK input (TPD after the positive
edge of CLK).
CLK can be stopped anywhere in the transmission
sequence (at high or low level) and can be continued
anytime with respect to clock high time (TCKH) and
clock low time (TCKL). This gives the controlling master
freedom in preparing opcode, address, and data.
This pin also provides READY/BUSY status informa-
tion during ERASE and WRITE cycles. READY/BUSY
status information is available on the DO pin if CS is
brought high after being low for minimum chip select
low time (TCSL) and an ERASE or WRITE operation
has been initiated. The status signal is not available on
DO, if CS is held low during the entire ERASE or
WRITE cycle. In this case, DO is in the HIGH-Z mode.
If status is checked after the ERASE/WRITE cycle, the
data line will be high to indicate the device is ready.
CLK is a “Don't Care” if CS is low (device deselected).
If CS is high, but the START condition has not been
detected, any number of clock cycles can be received
by the device without changing its status (i.e., waiting
for a START condition).
.
TABLE 2-1:
INSTRUCTION SET FOR 93C56A
Instruction SB Opcode
Address
Data In
Data Out
Req. CLK Cycles
1
1
1
1
1
1
1
11
00
00
00
10
01
00
X
1
0
1
X
X
0
A7 A6 A5 A4 A3 A2 A1 A0
—
—
—
—
—
(RDY/BSY)
(RDY/BSY)
HIGH-Z
12
12
12
12
20
20
20
ERASE
ERAL
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
EWDS
EWEN
READ
WRITE
WRAL
HIGH-Z
A7 A6 A5 A4 A3 A2 A1 A0
D7 - D0
A7 A6 A5 A4 A3 A2 A1 A0 D7 - D0
(RDY/BSY)
(RDY/BSY)
1
X
X
X
X
X
X
X
D7 - D0
TABLE 2-2:
INSTRUCTION SET FOR 93C56B
Instruction SB Opcode
Address
Data In
Data Out
Req. CLK Cycles
1
1
1
1
1
1
1
11
00
00
00
10
01
00
X
1
0
1
X
X
0
A6 A5 A4 A3 A2 A1 A0
—
—
—
—
—
(RDY/BSY)
(RDY/BSY)
HIGH-Z
11
11
11
11
27
27
27
ERASE
ERAL
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
EWDS
EWEN
READ
WRITE
WRAL
HIGH-Z
A6 A5 A4 A3 A2 A1 A0
D15 - D0
(RDY/BSY)
(RDY/BSY)
A6 A5 A4 A3 A2 A1 A0 D15 - D0
D15 - D0
1
X
X
X
X
X
X
1998 Microchip Technology Inc.
Preliminary
DS21206B-page 4-3
93C56A/B
3.2
Data IN (DI) and Data Out (DO)
3.0
FUNCTIONAL DESCRIPTION
Instructions, addresses, and write data are clocked into
the DI pin on the rising edge of the clock (CLK).The DO
pin is normally held in a HIGH-Z state except when
reading data from the device, or when checking the
READY/BUSY status during a programming operation.
The READY/BUSY status can be verified during an
ERASE/WRITE operation by polling the DO pin; DO
low indicates that programming is still in progress, while
DO high indicates the device is ready.The DO will enter
the HIGH-Z state on the falling edge of the CS.
It is possible to connect the Data In (DI) and Data Out
(DO) pins together. However, with this configuration, if
A0 is a logic-high level, it is possible for a “bus conflict”
to occur during the “dummy zero” that precedes the
READ operation. Under such a condition, the voltage
level seen at DO is undefined and will depend upon the
relative impedances of DO and the signal source driv-
ing A0.The higher the current sourcing capability of A0,
the higher the voltage at the DO pin.
3.3
Data Protection
3.1
START Condition
During power-up, all programming modes of operation
are inhibited until Vcc has reached a level greater than
3.8V. During power-down, the source data protection
circuitry acts to inhibit all programming modes when
Vcc has fallen below 3.8V at nominal conditions.
The START bit is detected by the device if CS and DI
are both high with respect to the positive edge of CLK
for the first time.
Before a START condition is detected, CS, CLK, and DI
may change in any combination (except to that of a
START condition), without resulting in any device oper-
ation (READ, WRITE, ERASE, EWEN, EWDS, ERAL,
and WRAL). As soon as CS is high, the device is no
longer in the standby mode.
The ERASE/WRITE Disable (EWDS) and ERASE
WRTE Enable (EWEN) commands give additional pro-
tection against accidentally programming during nor-
mal operation.
After power-up, the device is automatically in the
EWDS mode.Therefore, an EWEN instruction must be
performed before any ERASE or WRITE instruction
can be executed.
An instruction following a START condition will only be
executed if the required amount of opcode, address
and data bits for any particular instruction is clocked in.
After execution of an instruction (i.e., clock in or out of
the last required address or data bit) CLK and DI
become don't care bits until a new START condition is
detected.
FIGURE 3-1: SYNCHRONOUS DATA TIMING
VIH
CS
TCSS
TCKH
TCKL
VIL
VIH
TCSH
CLK
DI
VIL
TDIS
TDIH
VIH
VIL
TCZ
TPD
TPD
VOH
DO
(READ)
TCZ
VOL
VOH
TSV
DO
(PROGRAM)
STATUS VALID
VOL
Note: AC Test Conditions: VIL = 0.4V, VIH = 2.4V.
DS21206B-page 4
Preliminary
1998 Microchip Technology Inc.
93C56A/B
3.4
ERASE
3.5
Erase All (ERAL)
The ERASE instruction forces all data bits of the spec-
ified address to the logical “1” state. This cycle begins
on the rising clock edge of the last address bit.
The ERAL instruction will erase the entire memory
array to the logical “1” state.The ERAL cycle is identical
to the ERASE cycle, except for the different opcode.
The ERAL cycle is completely self-timed and com-
mences at the rising clock edge of the last address bit.
Clocking of the CLK pin is not necessary after the
device has entered the ERAL cycle.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL). DO at logical “0” indicates that program-
ming is still in progress. DO at logical “1” indicates that
the register at the specified address has been erased
and the device is ready for another instruction.
The DO pin indicates the READY/BUSY status of the
device, if CS is brought high after a minimum of 250 ns
low (TCSL) and before the entire ERAL cycle is com-
plete.
FIGURE 3-2: ERASE TIMING
TCSL
CS
CHECK STATUS
CLK
1
1
AN
AN-1 AN-2
A0
•••
DI
1
TSV
TCZ
HIGH-Z
BUSY
READY
DO
HIGH-Z
TWC
FIGURE 3-3: ERAL TIMING
TCSL
CS
CHECK STATUS
CLK
1
0
0
1
0
X
X
DI
•••
TSV
TCZ
HIGH-Z
BUSY
READY
DO
HIGH-Z
TEC
1998 Microchip Technology Inc.
Preliminary
DS21206B-page 5
93C56A/B
3.6
ERASE/WRITE Disable and Enable
(EWDS/EWEN)
3.7
READ
The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
zero bit precedes the 8-bit (93C56A) or 16-bit
(93C56B) output string. The output data bits will toggle
on the rising edge of the CLK and are stable after the
specified time delay (TPD). Sequential read is possible
when CS is held high. The memory data will automati-
cally cycle to the next register and output sequentially.
The device powers up in the ERASE/WRITE Disable
(EWDS) state. All programming modes must be pre-
ceded by an ERASE/WRITE Enable (EWEN) instruc-
tion. Once the EWEN instruction is executed,
programming remains enabled until an EWDS instruc-
tion is executed or VCC is removed from the device. To
protect against accidental data disturbance, the EWDS
instruction can be used to disable all ERASE/WRITE
functions and should follow all programming opera-
tions. Execution of a READ instruction is independent
of both the EWEN and EWDS instructions.
FIGURE 3-4: READ TIMING
CS
CLK
•••
A0
0
DI
An
1
1
0
HIGH-Z
DO
Dx
D0
Dx
D0
Dx
D0
•••
•••
•••
FIGURE 3-5: EWDS TIMING
TCSL
CS
CLK
•••
1
0
0
0
0
X
X
DI
FIGURE 3-6: EWEN TIMING
TCSL
CS
CLK
•••
1
0
0
1
1
X
X
DI
DS21206B-page 6
Preliminary
1998 Microchip Technology Inc.
93C56A/B
3.8
WRITE
3.9
Write All (WRAL)
The WRITE instruction is followed by 8-bits (93C56A)
16-bits (93C56B) of data which are written into the
specified address. After the last data bit is clocked into
the DI pin, the self-timed auto-erase and programming
cycle begins.
The Write All (WRAL) instruction will write the entire
memory array with the data specified in the command.
The WRAL cycle is completely self-timed and com-
mences at the rising clock edge of the last data bit.
Clocking of the CLK pin is not necessary after the
device has entered the WRAL cycle. The WRAL com-
mand does include an automatic ERAL cycle for the
device. Therefore, the WRAL instruction does not
require an ERAL instruction but the chip must be in the
EWEN status.
The DO pin indicates the READY/BUSY status of the
device, if CS is brought high after a minimum of 250 ns
low (TCSL) and before the entire write cycle is complete.
DO at logical “0” indicates that programming is still in
progress. DO at logical “1” indicates that the register at
the specified address has been written with the data
specified and the device is ready for another instruc-
tion.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL).
FIGURE 3-7: WRITE TIMING
TCSL
CS
CLK
0
1
1
An
A0
Dx
D0
•••
•••
DI
TSV
TCZ
HIGH-Z
BUSY
READY
DO
HIGH-Z
Twc
FIGURE 3-8: WRAL TIMING
TCSL
CS
CLK
0
0
1
X
1
0
•••
Dx
•••
DI
X
D0
TSV
TCZ
HIGH-Z
BUSY
READY
DO
HIGH-Z
TWL
1998 Microchip Technology Inc.
Preliminary
DS21206B-page 7
93C56A/B
NOTES:
DS21206B-page 8
Preliminary
1998 Microchip Technology Inc.
93C56A/B
NOTES:
1998 Microchip Technology Inc.
Preliminary
DS21206B-page 9
93C56A/B
NOTES:
DS21206B-page 10
Preliminary
1998 Microchip Technology Inc.
93C56A/B
93C56A/B PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
93C56A/B /P
P = Plastic DIP (300 mil Body), 8-lead
SN = Plastic SOIC (150 mil Body), 8-lead
Package:
Temperature
Range:
E = -40°C to +125°C
93C56A
2K Microwire Serial EEPROM (x8)
93C56AT
93C56B
2K Microwire Serial EEPROM (x8) Tape and Reel
2K Microwire Serial EEPROM (x16)
Device:
93C56BT
2K Microwire Serial EEPROM (x16) Tape and Reel
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office.
2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277.
3. The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).
1998 Microchip Technology Inc.
Preliminary
DS21206B-page 11
M
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All rights reserved. © 1998, Microchip Technology Incorporated, USA. 1/98
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no
liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use
or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or
otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other
trademarks mentioned herein are the property of their respective companies.
DS21206B-page 12
Preliminary
1998 Microchip Technology Inc.
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