93C46B-EST_技术文档

M

93C46B

1K 5.0V Microwire Serial EEPROM

FEATURES

BLOCK DIAGRAM

• Single supply 5.0V operation

• Low power CMOS technology

- 1 mA active current (typical)

ADDRESS

DECODER

MEMORY

ARRAY

- 1 µA standby current (maximum)

• 64 x 16 bit organization

• Self-timed ERASE and WRITE cycles (including

auto-erase)

ADDRESS

COUNTER

• Automatic ERAL before WRAL

• Power on/off data protection circuitry

• Industry standard 3-wire serial interface

• Device status signal during ERASE/WRITE cycles

• Sequential READ function

• 1,000,000 E/W cycles guaranteed

• Data retention > 200 years

• 8-pin PDIP/SOIC and 8-pin TSSOP packages

• Available for the following temperature ranges:

DATA

OUTPUT

BUFFER

DO

REGISTER

DI

MEMORY

DECODE

LOGIC

CS

VCC

VSS

CLOCK

GENERATOR

CLK

- Commercial (C):

- Industrial (I):

- Automotive (E):

0°C to

-40°C to

-40°C to +125°C

+70°C

+85°C

DESCRIPTION

The Microchip Technology Inc. 93C46B is a 1K-bit,

low-voltage serial Electrically Erasable PROM. The

device memory is conﬁgured as 64 x 16 bits. Advanced

CMOS technology makes this device ideal for

low-power, nonvolatile memory applications. The

93C46B is available in standard 8-pin DIP, surface

mount SOIC, and TSSOP packages.The 93C46BX are

only offered in a 150 mil SOIC package.

PACKAGE TYPE

DIP

SOIC

TSSOP

1

2

3

4

8

7

6

5

CS

CLK

DI

1

2

8

7

VCC

NC

VCC

NC

VSS

1

8

7

1

2

8

7

NU

VCC

CS

NC

VSS

DO

DI

VCC

NC

CS

CLK

DI

2

DO

CLK

3

4

6

5

NC

3

6

5

3

4

6

5

DI

NC

VSS

DO

4

CLK

DO

VSS

Microwire is a registered trademark of National Semiconductor Incorporated.

1997 Microchip Technology Inc.

Preliminary

DS21172D-page 1

93C46B

TABLE 1-1

Name

PIN FUNCTION TABLE

Function

1.0

ELECTRICAL

CHARACTERISTICS

1.1

Maximum Ratings*

CS

CLK

DI

Chip Select

Serial Data Clock

Serial Data Input

Serial Data Output

Ground

VCC...................................................................................7.0V

All inputs and outputs w.r.t. VSS ...............-0.6V to VCC +1.0V

Storage temperature .....................................-65°C to +150°C

Ambient temp. with power applied.................-65°C to +125°C

Soldering temperature of leads (10 seconds) .............+300°C

ESD protection on all pins................................................4 kV

DO

VSS

NC

VCC

No Connect

*Notice: Stresses above those listed under “Maximum ratings” may

cause permanent damage to the device.This is a stress rating only and

functional operation of the device at those or any other conditions

above those indicated in the operational listings of this speciﬁcation is

not implied. Exposure to maximum rating conditions for extended peri-

ods may affect device reliability.

Power Supply

TABLE 1-2

DC AND AC ELECTRICAL CHARACTERISTICS

All parameters apply over the Commercial (C) VCC = +4.5V to +5.5V Tamb = 0°C to +70°C

speciﬁed operating ranges

unless otherwise noted

Industrial (I)

Automotive (E)

VCC = +4.5V to +5.5V Tamb = -40°C to +85°C

VCC = +4.5V to +5.5V Tamb = -40°C to +125°C

Parameter

Symbol

Min.

Max.

Units

Conditions

High level input voltage

Low level input voltage

Low level output voltage

High level output voltage

Input leakage current

Output leakage current

VIH

VIL

2.0

-0.3

—

VCC +1

0.8

V

(Note 2)

VOL

VOH

ILI

0.4

V

IOL = 2.1 mA; VCC = 4.5V

IOH = -400 µA; VCC = 4.5V

VIN = VSS to VCC

2.4

-10

—

V

10

µA

ILO

10

VOUT = VSS to VCC

Pin capacitance

(all inputs/outputs)

VIN/VOUT = 0 V (Notes 1 & 2)

Tamb = +25°C, FCLK = 1 MHz

CIN, COUT

ICC read

—

7

1

pF

mA

Operating current

Standby current

ICC write

ICCS

FCLK

TCKH

TCKL

TCSS

TCSH

TCSL

TDIS

TDIH

TPD

—

1.5

1

mA

µA

MHz

ns

CS = VSS

Clock frequency

—

2

VCC = 4.5V

Clock high time

250

50

0

—

400

100

500

2

Clock low time

ns

Chip select setup time

Chip select hold time

Chip select low time

Data input setup time

Data input hold time

Data output delay time

Data output disable time

Status valid time

ns

Relative to CLK

ns

250

100

—

ns

Relative to CLK

CL = 100 pF

ns

TCZ

—

ns

CL = 100 pF (Note 2)

CL = 100 pF

TSV

—

ns

TWC

TEC

—

ms

ERASE/WRITE mode

ERAL mode

Program cycle time

—

6

TWL

—

15

—

WRAL mode

Endurance

—

1M

cycles 25°C, VCC = 5.0V, Block Mode (Note 3)

Note 1: This parameter is tested at Tamb = 25°C and FCLK = 1 MHz.

2: This parameter is periodically sampled and not 100% tested.

3: This application is not tested but guaranteed by characterization. For endurance estimates in a speciﬁc appli-

cation, please consult the Total Endurance Model which may be obtained on Microchip’s BBS or website.

DS21172D-page 2

Preliminary

1997 Microchip Technology Inc.

93C46B

After detecting a START condition, the speciﬁed num-

ber of clock cycles (respectively low to high transitions

of CLK) must be provided. These clock cycles are

required to clock in all required opcodes, addresses,

and data bits before an instruction is executed

(Table 2-1). CLK and DI then become don't care inputs

waiting for a new START condition to be detected.

2.0

PIN DESCRIPTION

2.1

Chip Select (CS)

A high level selects the device; a low level deselects the

device and forces it into standby mode. However, a pro-

gramming cycle which is already in progress will be

completed, regardless of the Chip Select (CS) input

signal. If CS is brought low during a program cycle, the

device will go into standby mode as soon as the pro-

gramming cycle is completed.

Note: CS must go low between consecutive

instructions.

2.3

Data In (DI)

CS must be low for 250 ns minimum (TCSL) between

consecutive instructions. If CS is low, the internal con-

trol logic is held in a RESET status.

Data In (DI) is used to clock in a START bit, opcode,

address, and data synchronously with the CLK input.

2.4

Data Out (DO)

2.2

Serial Clock (CLK)

Data Out (DO) is used in the READ mode to output data

synchronously with the CLK input (TPD after the posi-

tive edge of CLK).

The Serial Clock (CLK) is used to synchronize the com-

munication between a master device and the 93C46B.

Opcodes, addresses, and data bits are clocked in on

the positive edge of CLK. Data bits are also clocked out

on the positive edge of CLK.

This pin also provides READY/BUSY status information

during ERASE and WRITE cycles. READY/BUSY sta-

tus information is available on the DO pin if CS is

brought high after being low for minimum chip select

low time (TCSL) and an ERASE or WRITE operation has

been initiated.

CLK can be stopped anywhere in the transmission

sequence (at high or low level) and can be continued

anytime with respect to clock high time (TCKH) and

clock low time (TCKL). This gives the controlling master

freedom in preparing the opcode, address, and data.

The status signal is not available on DO, if CS is held

low during the entire ERASE or WRITE cycle. In this

case, DO is in the HIGH-Z mode. If status is checked

after the ERASE/WRITE cycle, the data line will be high

to indicate the device is ready.

CLK is a “Don't Care” if CS is low (device deselected).

If CS is high, but START condition has not been

detected, any number of clock cycles can be received

by the device, without changing its status (i.e., waiting

for a START condition).

CLK cycles are not required during the self-timed

WRITE (i.e., auto ERASE/WRITE) cycle.

TABLE 2-1

Instruction

INSTRUCTION SET FOR 93C46B

SB

Opcode

Address

Data In

Data Out

Req. CLK Cycles

1

11

00

10

01

00

A5

1

A4

0

A3

X

A2

X

A1

X

A0

X

—

(RDY/BSY)

HIGH-Z

9

ERASE

ERAL

0

X

—

9

EWDS

EWEN

READ

WRITE

WRAL

1

X

—

HIGH-Z

9

A5

0

A4

1

A3

X

A2

X

A1

X

A0

X

—

D15 - D0

(RDY/BSY)

25

D15 - D0

1997 Microchip Technology Inc.

Preliminary

DS21172D-page 3

93C46B

3.2

Data In (DI) and Data Out (DO)

3.0

FUNCTIONAL DESCRIPTION

Instructions, addresses and write data are clocked into

the DI pin on the rising edge of the clock (CLK).The DO

pin is normally held in a HIGH-Z state except when

reading data from the device, or when checking the

READY/BUSY status during a programming operation.

The READY/BUSY status can be veriﬁed during an

ERASE/WRITE operation by polling the DO pin; DO

low indicates that programming is still in progress, while

DO high indicates the device is ready.The DO will enter

the HIGH-Z state on the falling edge of the CS.

It is possible to connect the Data In (DI)and Data Out

(DO) pins together. However, with this conﬁguration, if

A0 is a logic-high level, it is possible for a “bus conﬂict”

to occur during the “dummy zero” that precedes the

READ operation. Under such a condition, the voltage

level seen at DO is undeﬁned and will depend upon the

relative impedances of DO and the signal source driv-

ing A0.The higher the current sourcing capability of A0,

the higher the voltage at the DO pin.

3.3

Data Protection

3.1

START Condition

During power-up, all programming modes of operation

are inhibited until Vcc has reached a level greater than

3.8V. During power-down, the source data protection

circuitry acts to inhibit all programming modes when

Vcc has fallen below 3.8V at nominal conditions.

The START bit is detected by the device if CS and DI

are both high with respect to the positive edge of CLK

for the ﬁrst time.

Before a START condition is detected, CS, CLK, and DI

may change in any combination (except to that of a

START condition), without resulting in any device oper-

ation (ERASE, ERAL, EWDS, EWEN, READ, WRITE,

and WRAL). As soon as CS is high, the device is no

longer in the standby mode.

The ERASE/SRITE Disable (EWDS) and ERASE/

WRITE Enable (EWEN) commands give additional pro-

tection against accidental programming during normal

operation.

After power-up, the device is automatically in the

EWDS mode. Therefore, an EWEN instruction must be

performed before any ERASE or WRITE instruction can

be executed.

An instruction following a START condition will only be

executed if the required amount of opcodes,

addresses, and data bits for any particular instruction is

clocked in.

After execution of an instruction (i.e., clock in or out of

the last required address or data bit) CLK and DI

become don't care bits until a new START condition is

detected.

FIGURE 3-1: SYNCHRONOUS DATA TIMING

VIH

CS

TCSS

TCKH

TCKL

VIL

VIH

TCSH

CLK

DI

VIL

TDIS

TDIH

VIH

VIL

TCZ

TPD

VOH

DO

(READ)

TCZ

VOL

VOH

TSV

DO

STATUS VALID

(PROGRAM)

VOL

Note: AC test conditions: VIL = 0.4V, VIH = 2.4V

DS21172D-page 4

Preliminary

1997 Microchip Technology Inc.

93C46B

3.4

ERASE

3.5

Erase All (ERAL)

The ERASE instruction forces all data bits of the spec-

iﬁed address to the logical “1” state. This cycle begins

on the rising clock edge of the last address bit.

The Erase All (ERAL) instruction will erase the entire

memory array to the logical “1” state. The ERAL cycle

is identical to the ERASE cycle, except for the different

opcode. The ERAL cycle is completely self-timed and

commences at the rising clock edge of the last address

bit. Clocking of the CLK pin is not necessary after the

device has entered the ERAL cycle.

The DO pin indicates the READY/BUSY status of the

device if CS is brought high after a minimum of 250 ns

low (TCSL). DO at logical “0” indicates that program-

ming is still in progress. DO at logical “1” indicates that

the register at the speciﬁed address has been erased

and the device is ready for another instruction.

The DO pin indicates the READY/BUSY status of the

device, if CS is brought high after a minimum of 250 ns

low (TCSL) and before the entire ERAL cycle is

complete.

FIGURE 3-2: ERASE TIMING

TCSL

CS

CHECK STATUS

CLK

1

AN

AN-1 AN-2

A0

•••

DI

1

TSV

TCZ

HIGH-Z

BUSY

READY

DO

HIGH-Z

TWC

FIGURE 3-3: ERAL TIMING

TCSL

CS

CHECK STATUS

CLK

1

0

1

0

X

DI

•••

TSV

TCZ

HIGH-Z

BUSY

READY

DO

HIGH-Z

TEC

1997 Microchip Technology Inc.

Preliminary

DS21172D-page 5

93C46B

3.6

ERASE/WRITE Disable and Enable

(EWDS/EWEN)

3.7

READ

The READ instruction outputs the serial data of the

addressed memory location on the DO pin. A dummy

zero bit precedes the 16-bit output string. The output

data bits will toggle on the rising edge of the CLK and

are stable after the speciﬁed time delay (TPD). Sequen-

tial read is possible when CS is held high. The memory

data will automatically cycle to the next register and

output sequentially.

The device powers up in the ERASE/WRITE Disable

(EWDS) state. All programming modes must be pre-

ceded by an Erase/Write Enable (EWEN) instruction.

Once the EWEN instruction is executed, programming

remains enabled until an EWDS instruction is executed

or Vcc is removed from the device. To protect against

accidental data disturbance, the EWDS instruction can

be used to disable all ERASE/WRITE functions and

should follow all programming operations. Execution of

a READ instruction is independent of both the EWDS

and EWEN instructions.

FIGURE 3-4: EWDS TIMING

TCSL

CS

CLK

•••

X

1

0

X

DI

FIGURE 3-5: EWEN TIMING

TCSL

CS

CLK

•••

1

0

1

X

DI

FIGURE 3-6: READ TIMING

CS

CLK

•••

A0

0

DI

An

1

0

HIGH-Z

DO

Dx

D0

Dx

D0

Dx

D0

•••

DS21172D-page 6

Preliminary

1997 Microchip Technology Inc.

93C46B

3.8

WRITE

3.9

Write All (WRAL)

The WRITE instruction is followed by 16 bits of data,

which are written into the speciﬁed address. After the

last data bit is clocked into the DI pin, the self-timed

auto-erase and programming cycle begins.

The Write All (WRAL) instruction will write the entire

memory array with the data speciﬁed in the command.

The WRAL cycle is completely self-timed and com-

mences at the rising clock edge of the last data bit.

Clocking of the CLK pin is not necessary after the

device has entered the WRAL cycle. The WRAL com-

mand does include an automatic ERAL cycle for the

device. Therefore, the WRAL instruction does not

require an ERAL instruction, but the chip must be in the

EWEN status.

The DO pin indicates the READY/BUSY status of the

device, if CS is brought high after a minimum of 250 ns

low (TCSL) and before the entire write cycle is complete.

DO at logical “0” indicates that programming is still in

progress. DO at logical “1” indicates that the register at

the speciﬁed address has been written with the data

speciﬁed and the device is ready for another instruc-

tion.

The DO pin indicates the READY/BUSY status of the

device if CS is brought high after a minimum of 250 ns

low (TCSL).

FIGURE 3-7: WRITE TIMING

TCSL

CS

CLK

0

1

An

A0

Dx

D0

•••

DI

TSV

TCZ

HIGH-Z

BUSY

READY

DO

HIGH-Z

Twc

FIGURE 3-8: WRAL TIMING

TCSL

CS

CLK

0

1

X

1

0

•••

Dx

•••

DI

X

D0

TSV

TCZ

HIGH-Z

BUSY

READY

DO

HIGH-Z

TWL

1997 Microchip Technology Inc.

Preliminary

DS21172D-page 7

93C46B

NOTES:

DS21172D-page 8

Preliminary

1997 Microchip Technology Inc.

93C46B

NOTES:

1997 Microchip Technology Inc.

Preliminary

DS21172D-page 9

93C46B

NOTES:

DS21172D-page 10

Preliminary

1997 Microchip Technology Inc.

93C46B

93C46B PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales ofﬁce.

93C46B /P

—

P = Plastic DIP (300 mil Body), 8-lead

SN = Plastic SOIC (150 mil Body), 8-lead

SM = Plastic SOIC (208 mil Body), 8-lead

ST = TSSOP, 8-lead

Package:

Blank = 0°C to +70°C

I = -40°C to +85°C

E = -40°C to +125°C

Temperature

Range:

Device:

93C46B = 1K Microwire Serial EEPROM

93C46BT = 1K Microwire Serial EEPROM Tape and Reel

93C46BX = 1K Microwire Serial EEPROM in alternate pinout

(SN only)

93C46BXT = 1K Microwire Serial EEPROM in alternate pinout,

Tape and Reel (SN only)

Sales and Support

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-

mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microchip sales ofﬁce.

2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277.

3. The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).

1997 Microchip Technology Inc.

Preliminary

DS21172D-page 11

WORLDWIDE SALES & SERVICE

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Ofﬁce

Microchip Technology Inc.

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Hong Kong

Microchip Asia Paciﬁc

RM 3801B, Tower Two

Metroplaza

United Kingdom

Arizona Microchip Technology Ltd.

Unit 6, The Courtyard

Meadow Bank, Furlong Road

Tel: 602-786-7200 Fax: 602-786-7277

Technical Support: 602 786-7627

Web: http://www.microchip.com

223 Hing Fong Road

Kwai Fong, N.T., Hong Kong

Tel: 852-2-401-1200 Fax: 852-2-401-3431

Bourne End, Buckinghamshire SL8 5AJ

Tel: 44-1628-851077 Fax: 44-1628-850259

France

Arizona Microchip Technology SARL

Atlanta

India

Microchip Technology Inc.

Microchip Technology India

Zone Industrielle de la Bonde

500 Sugar Mill Road, Suite 200B

Atlanta, GA 30350

No. 6, Legacy, Convent Road

Bangalore 560 025, India

2 Rue du Buisson aux Fraises

91300 Massy, France

Tel: 770-640-0034 Fax: 770-640-0307

Tel: 91-80-229-0061 Fax: 91-80-229-0062

Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79

Boston

Microchip Technology Inc.

5 Mount Royal Avenue

Marlborough, MA 01752

Tel: 508-480-9990 Fax: 508-480-8575

Korea

Germany

Arizona Microchip Technology GmbH

Gustav-Heinemann-Ring 125

D-81739 Müchen, Germany

Tel: 49-89-627-144 0 Fax: 49-89-627-144-44

Microchip Technology Korea

168-1, Youngbo Bldg. 3 Floor

Samsung-Dong, Kangnam-Ku

Seoul, Korea

Tel: 82-2-554-7200 Fax: 82-2-558-5934

Chicago

Microchip Technology Inc.

333 Pierce Road, Suite 180

Itasca, IL 60143

Italy

Shanghai

Microchip Technology

RM 406 Shanghai Golden Bridge Bldg.

2077 Yan’an Road West, Hongiao District

Shanghai, PRC 200335

Arizona Microchip Technology SRL

Centro Direzionale Colleone

Palazzo Taurus 1 V. Le Colleoni 1

20041 Agrate Brianza

Milan, Italy

Tel: 39-39-6899939 Fax: 39-39-6899883

Tel: 630-285-0071 Fax: 630-285-0075

Dallas

Microchip Technology Inc.

14651 Dallas Parkway, Suite 816

Dallas, TX 75240-8809

Tel: 972-991-7177 Fax: 972-991-8588

Tel: 86-21-6275-5700

Fax: 86 21-6275-5060

Singapore

Microchip Technology Taiwan

Singapore Branch

200 Middle Road

#10-03 Prime Centre

JAPAN

Microchip Technology Intl. Inc.

Benex S-1 6F

Dayton

Microchip Technology Inc.

Two Prestige Place, Suite 150

Miamisburg, OH 45342

Tel: 937-291-1654 Fax: 937-291-9175

3-18-20, Shin Yokohama

Kohoku-Ku, Yokohama

Kanagawa 222 Japan

Singapore 188980

Tel: 65-334-8870 Fax: 65-334-8850

Tel: 81-4-5471- 6166 Fax: 81-4-5471-6122

Taiwan, R.O.C

Microchip Technology Taiwan

10F-1C 207

Tung Hua North Road

Taipei, Taiwan, ROC

Los Angeles

Microchip Technology Inc.

18201 Von Karman, Suite 1090

Irvine, CA 92612

5/8/97

Tel: 714-263-1888 Fax: 714-263-1338

Tel: 886 2-717-7175 Fax: 886-2-545-0139

NewYork

Microchip Technology Inc.

150 Motor Parkway, Suite 416

Hauppauge, NY 11788

Tel: 516-273-5305 Fax: 516-273-5335

San Jose

Microchip Technology Inc.

2107 North First Street, Suite 590

San Jose, CA 95131

Tel: 408-436-7950 Fax: 408-436-7955

Toronto

Microchip Technology Inc.

5925 Airport Road, Suite 200

Mississauga, Ontario L4V 1W1, Canada

Tel: 905-405-6279 Fax: 905-405-6253

M

Printed on recycled paper.

Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or

warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other

intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express

written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks

DS21172D-page 12

Preliminary

1997 Microchip Technology Inc.


型号：	93C46B-EST
厂家：	MICROCHIP
描述：	1K 5.0V Microwire Serial EEPROM 1K 5.0V Microwire串行EEPROM 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件：	总12页 (文件大小：147K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

93C46B-EST [MICROCHIP]

相关型号：

93C46B-I/MC

93C46B-I/MCG

93C46B-I/MCGX

93C46B-I/MS

93C46B-I/MSG

93C46B-I/MSGX

93C46B-I/MSX

93C46B-I/OT

93C46B-I/OTG

93C46B-I/OTGX

93C46B-I/P

93C46B-I/PG