59C11E/SN [MICROCHIP]
128 X 8 4-WIRE SERIAL EEPROM, PDSO8, 0.150 INCH, PLASTIC, SOIC-8;
| 型号： | 59C11E/SN |
| 厂家： | 
MICROCHIP |
| 描述： | 128 X 8 4-WIRE SERIAL EEPROM, PDSO8, 0.150 INCH, PLASTIC, SOIC-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总12页 (文件大小：104K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
59C11
1K 5.0V Microwire Serial EEPROM
FEATURES
PACKAGE TYPES
• Low power CMOS technology
DIP
• Pin selectable memory organization
- 128 x 8 or 64 x 16 bit organization
• Single 5V only operation
CS
CLK
DI
1
2
3
4
8
7
6
5
VCC
• Self timed WRITE, ERAL and WRAL cycles
• Automatic erase before WRITE
• RDY/BSY status information during WRITE
• Power on/off data protection circuitry
• 1,000,000 ERASE/WRITE cycles guaranteed
• Data Retention > 200 Years
RDY/BSY
ORG
DO
VSS
• 8-pin DIP or SOIC package
SOIC
• Temperature ranges supported
- Commercial (C):
- Industrial (I):
- Automotive (E):
0˚C to +70˚C
-40˚C to +85˚C
-40˚C to +125˚C
1
2
3
4
8
7
6
5
VCC
CS
CLK
DI
RDY/BSY
ORG
DESCRIPTION
The Microchip Technology Inc. 59C11 is a 1K bit Elec-
trically Erasable PROM. The device is configured as
128 x 8 or 64 x 16, selectable externally by means of
the control pin ORG. Advanced CMOS technology
makes this device ideal for low power nonvolatile mem-
ory applications. The 59C11 is available in the standard
8-pin DIP and a surface mount SOIC package.
VSS
DO
BLOCK DIAGRAM
VCC
VSS
MEMORY
ARRAY
128 x 8 or
ADDRESS
DECODER
ORG
64 x 16
OUTPUT
BUFFER
DATA REGISTER
DO
DI
MODE
DECODE
CS
LOGIC
RDY/BSY
CLOCK
GENERATOR
CLK
Microwire is a registered trademark of National Semiconductor Incorporated.
1996 Microchip Technology Inc.
DS20040J-page 1
59C11
TABLE 1-1:
Name
PIN FUNCTION TABLE
Function
1.0
ELECTRICAL CHARACTERISTICS
1.1
Maximum Ratings*
CS
CLK
Chip Select
VCC...................................................................................7.0V
All inputs and outputs w.r.t. VSS ............... -0.6V to VCC +1.0V
Storage temperature .................................. -65˚C to +150˚C
Ambient temperature with power applied...... -65˚C to +125˚C
Soldering temperature of leads (10 seconds) ............. +300˚C
ESD protection on all pins................................................4 kV
Serial Clock
DI
Data In
DO
Data Out
VSS
Ground
ORG
RDY/BSY
VCC
Memory Array Organization
Ready/Busy Status
+5V Power SUpply
*Notice: Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-2:
DC CHARACTERISTICS
VCC = +5.0V (±10%)
Commercial (C):
Tamb
= 0°C to 70°C
Industrial (I):
Automotive (E):
Tamb
Tamb
= -40°C to +85°C
= -40°C to 125°C
Parameter
Symbol
Min
Max
Units
Conditions
VCC detector threshold
High level input voltage
Low level input voltage
High level output voltage
Low level output voltage
Input leakage current
Output leakage current
VTH
VIH
VIL
2.8
2.0
-0.3
2.4
—
4.5
Vcc+1
0.8
—
V
V
V
VOH
VOL
ILI
V
IOH = -400 µA
0.4
10
V
IOL = 3.2 mA
—
µA
µA
pF
VIN = 0V to VCC (Note 1)
VOUT = 0V to VCC (Note 1)
ILO
—
10
Pin capacitance
CIN,
—
7
VIN/VOUT = 0V (Note 2)
(all inputs/outputs)
COUT
Tamb = 25°C, f = 1 MHz
Operating current (all modes)
Standby current
ICC write
ICCS
—
—
4
mA
FCLK = 1 MHz, VCC = 5.5V
CS = 0V, VCC = 5.5V
100
µA
Note 1: Internal resister pull-up at Pin 6. Active output at Pin 7.
2: This parameter is periodically sampled and not 100% tested.
FIGURE 1-1: SYNCHRONOUS DATA TIMING
TCKH
TCKL
TCSH
VIH
CLK
DI
VIL
TDIH
TDIS
TDIH
TDIS
VIH
VALID
VALID
VIL
TCSL
VIH
TCSS
CS
VIL
TPD
TPD
TCZ
VIH/ VOH
VIL/VOL
HIGH
DO
VALID
VALID
Z
DS20040J-page 2
1996 Microchip Technology Inc.
59C11
TABLE 1-3:
AC CHARACTERISTICS
Parameter
Symbol
Min
Max
Units
Conditions
Clock frequency
Clock high time
Clock low time
FCLK
TCKH
TCKL
TCSS
TCSH
TCS
1
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
500
500
50
0
—
—
Chip select setup time
—
Chip select hold time
—
Chip select low time
100
100
100
—
—
Data input setup time
TDIS
TDIH
TPD
—
Data input hold time
—
Data output delay time
400
100
400
400
CL = 100 pF
Data output disable time (from CS = low)
Data output disable time (from last clock)
RDY/BSY delay time
TCZ
0
CL = 100 pF
CL = 100 pF
TDDZ
TRBD
Twc
0
—
Program cycle time (Auto Erase and Write)
—
1
15
ms
ms
for 8-bit mode
for ERAL and WRAL
in 8/16-bit modes
Endurance
—
1M
—
cycles 25°C, Vcc = 5.0V, Block Mode
(Note 1)
Note 1: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our BBS or website.
TABLE 1-4:
INSTRUCTION SET
6 X 16 MODE, ORG = 1
Address
Number of
Req. CLK CYcles
Instruction
Start Bit
Opcode
Data In
Data Out
READ
WRITE
EWEN
EWDS
ERAL
1
1
1
1
1
1
1 0 X X
X 1 X X
0 0 1 1
0 0 0 0
0 0 1 0
0 0 0 1
A5 A4 A3 A2 A1 A0
A5 A4 A3 A2 A1 A0
—
D15-D0
—
D15-D0
High-Z
High-Z
High-Z
High-Z
High-Z
27
27
11
11
11
27
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
—
X
X
—
WRAL
D15-D0
128 X 8 MODE, ORG = 0
Number of
Req. CLK CYcles
Instruction
Start Bit
Opcode
Address
Data In
Data Out
READ
WRITE
EWEN
EWDS
ERAL
1
1
1
1
1
1
1 0 X X
X 1 X X
0 0 1 1
0 0 0 0
0 0 1 0
0 0 0 1
A6 A5 A4 A3 A2 A1 A0
A6 A5 A4 A3 A2 A1 A0
—
D7-D0
—
D7-D0
High-Z
High-Z
High-Z
High-Z
High-Z
20
20
12
12
12
20
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
—
—
WRAL
D7-D0
1996 Microchip Technology Inc.
DS20040J-page 3
59C11
2.4
READ Mode
2.0
FUNCTIONAL DESCRIPTION
The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
bit (logical 0) precedes the 8- or 16-bit output string.
The output data changes during the high state of the
system clock (CLK). The dummy bit is output TPD after
the positive edge of CLK, which was used to clock in the
last address bit (A0). Therefore, care must be taken if
DI and DO are connected together as a bus contention
will occur for one clock cycle if A0 is a one.
2.1
START Condition
The START bit is detected by the device if CS and DI
are both High with respect to the positive edge of CLK
for the first time.
Before a START condition is detected, CS, CLK, and DI
may change in any combination (except to that of a
START condition) without resulting in any device oper-
ation (READ, WRITE, EWEN, EWDS, ERAL, and
WRAL). As soon as CS is HIGH, the device is no longer
in the standby mode.
DO will go into HIGH-Z mode with the positive edge of
the next CLK cycle. This follows the output of the last
data bit D0 or the negative edge of CS, whichever
occurs first. D0 remains stable between CLK cycles for
an unlimited time as long as CS stays HIGH.
An instruction following a START condition will only be
executed if the required amount of opcode, address
and data bits for any particular instruction is clocked in.
The most significant data bit (D15 or D7) is always out-
put first, followed by the lower significant bits (D14 - D0
or D6 - D0).
After execution of an instruction (i.e. clock in or out of
the last required address or data bit) CLK and DI
become don't care bits until a new start condition is
detected.
2.5
WRITE
Note: CS must go LOW between consecutive
The WRITE instruction is followed by 8 or 16 bits of data
which are written into the specified address. The most
significant data bit (D15 or D7) has to be clocked in first
followed by the lower significant data bits (D14 – D0 or
D6 – D0). If a WRITE instruction is recognized by the
device and all data bits have been clocked in, the
device performs an automatic erase cycle on the spec-
ified address before the data are written. The WRITE
cycle is completely self timed and commences auto-
matically after the rising edge of the CLK signal for the
last data bit (D0).
instructions.
2.2
DI/DO Pins
It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a “bus conflict” to occur during the “dummy zero” that
precedes the READ operation, ifA0 is a logic high level.
Under such a condition the voltage level seen at Data
Out is undefined and will depend upon the relative
impedances of Data Out and the signal source driving
A0. The higher the current sourcing capability ofA0, the
higher the voltage at the Data Out pin.
The WRITE cycle takes 1 ms maximum for 8-bit mode
and 2 ms maximum for 16-bit mode.
2.3
Data Protection
2.6
Erase/Write Enable and Disable
(EWEN, EWDS)
During power-up, all modes of operation are inhibited
until VCC has reached a level of 2.8 V. During power-
down, the source data protection circuitry acts to inhibit
all modes when VCC has fallen below 2.8 V.
The device is automatically in the ERASE/WRITE Dis-
able mode (EWDS) after power-up. Therefore, EWEN
instruction has to be performed before any WRITE,
ERAL, or WRAL instruction is executed by the device.
For added data protection, the device should be put in
the ERASE/WRITE Disable mode (EWDS) after pro-
gramming operations are completed.
The EWEN and EWDS commands give additional pro-
tection against accidentally programming during nor-
mal operation.
After power-up, the device is automatically in the
EWDS mode. Therefore, EWEN instruction must be
performed before any WRITE, ERAL or WRAL instruc-
tion can be executed. After programming is completed,
the EWDS instruction offers added protection against
unintended data changes.
2.7
ERASE All (ERAL)
The entire chip will be erased to logical “1s” if this
instruction is received by the device and it is in the
EWEN mode. The ERAL cycle is completely self-timed
and commences after the rising edge of the CLK signal
for the last dummy address bit. ERAL takes 15 ms max-
imum.
DS20040J-page 4
1996 Microchip Technology Inc.
59C11
2.8
WRITE All (WRAL)
The entire chip will be written with the data specified in
that command. The WRAL cycle is completely self-
timed and commences after the last data bit (D0) has
been clocked in. WRAL takes 15 ms maximum.
Note: The WRAL does not include an automatic
ERASE cycle for the chip. Therefore, the
WRAL instruction must be preceded by an
ERAL instruction and the chip must be in
the EWEN status in both cases. The
WRAL instruction is used for testing and/or
device initialization.
FIGURE 2-1: READ MODE
CLK
T
CSL
CS
OPCODE
SB
1
AN
X
A0
X
DI
1
0
X
X
T
DDZ
TPD
DO
HIGH - Z
D0
0
DN
NOTE: ORGANIZATION
AN
DN
D7
128 x 8
64 x 16
A6
A5
NEW INSTRUCTION
OR STANDBY (CS = 0)
D15
FIGURE 2-2: WRITE MODE
CLK
TCSL
CS
SB
OPCODE
AN
X
A0
X
DN
D0
DI
1
X
1
X
X
X
X
DO
HIGH - Z
TRBD
RDY/BSY
TWC
NOTE: ORGANIZATION
AN
A6
A5
DN
128 x 8
64 x 16
D7
NEW INSTRUCTION
OR STANDBY (CS = 0)
D15
1996 Microchip Technology Inc.
DS20040J-page 5
59C11
FIGURE 2-3: ERASE/WRITE ENABLE AND DISABLE
CLK
TCSL
CS
SB
1
OPCODE
AN
X
A0
X
SB
DI
0
0
0
0
1
EWDS
EWEN
1
DO
HIGH - Z
NOTE: ORGANIZATION
AN
128 x 8
64 x 16
A6
A5
NEW INSTRUCTION
OR STANDBY (CS = 0)
FIGURE 2-4: ERASE ALL (ERAL)
CLK
TCSH
TCSL
SB
CS
SB
1
OPCODE
AN
A0
X
DI
0
0
1
0
X
DO
HIGH - Z
TRBD
RDY/BSY
NOTE: ORGANIZATION
AN
A6
TWC
128 x 8
64 x 16
NEW INSTRUCTION
OR STANDBY (CS = 0)
A5
FIGURE 2-5: WRITE ALL
CLK
TCSH
TCSL
CS
SB
OPCODE
0
AN
X
A0
DN
D0
X
DI
1
0
0
1
X
X
DO
HIGH - Z
TRBD
RDY/BSY
TWC
NOTE: ORGANIZATION
AN
A6
DN
D7
128 x 8
64 x 16
NEW INSTRUCTION
OR STANDBY (CS = 0)
A5
D15
DS20040J-page 6
1996 Microchip Technology Inc.
59C11
3.4
Data Out (DO)
3.0
PIN DESCRIPTION
Data Out is used in the READ mode to output data syn-
chronously with the CLK input (TPD after the positive
edge of CLK). This output is in HIGH–Z mode except
if data is clocked out as a result of a READ instruction.
3.1
Chip Select (CS)
A HIGH level selects the device. A LOW level dese-
lects the device and forces it into standby mode. How-
ever, a WRITE cycle which is already initiated and/or in
progress will be completed, regardless of the CS input
signal. If CS is brought LOW during a WRITE cycle, the
device will go into standby mode as soon as the WRITE
cycle is completed.
DI and DO can be connected together to perform a 3-
wire interface (CS, CLK, DI/DO).
Care must be taken with the leading dummy zero which
is output after a READ command has been detected.
Also, the controlling device must not drive the DI/DO
bus during WRITE cycles.
CS must be LOW for 100 ns (TCSL) minimum between
consecutive instructions. If CS is LOW, the internal
control logic is held in a RESET status.
3.5
Organization (ORG)
3.2
Serial Clock (CLK)
This input selects the memory array organization.
When the ORG pin is connected to +5 V the 64 x 16
organization is selected. When it is connected to
ground, the 128 x 8 organization is selected. If the
ORG pin is left unconnected, then an internal pull-up
device will select the 64 x 16 organization. In applica-
tions subject to electrical noise, it is recommended that
this pin not be left floating, but tied either high or low.
The Serial Clock is used to synchronize the communi-
cation between a master device and the 59C11.
Opcode, address, and data bits are clocked in on the
positive edge of CLK. Data bits are also clocked out on
the positive edge of CLK.
CLK can be stopped anywhere in the transmission
sequence (at HIGH or LOW level) and can be continued
anytime (with respect to clock high time (TCKH) and
clock low time (TCKL)). This gives freedom in preparing
opcode, address and data for the controlling master.
3.6
Ready/Busy (RDY/BSY)
Pin 7 provides RDY/BSY status information. RDY/BSY
is low if the device is performing a WRITE, ERAL, or
WRAL operation. When it is HIGH the internal, self-
timed WRITE, ERAL or WRAL operation has been
completed and the device is ready to receive a new
instruction.
CLK is a “Don't Care” if CS is LOW (device deselected).
If CS is HIGH, but a START condition has not been
detected, any number of clock cycles can be received
by the device without changing its status (i.e., waiting
for START condition).
CLK cycles are not required during the self-timed
WRITE (i.e., auto erase/write) cycle.
After detection of a START condition the specified num-
ber of clock cycles (respectively LOW to HIGH transi-
tions of CLK) must be provided. These clock cycles are
required to clock in all required opcode, address, and
data bits before an instruction is executed (see instruc-
tion set truth table). When that limit has been reached,
CLK and DI become “Don't Care” inputs until CS is
brought LOW for at least chip select low time (TCSL)
and brought HIGH again and a WRITE cycle (if any) is
completed.
3.3
Data In (DI)
Data In is used to clock in START bit, opcode, address
and data synchronously with the CLK input.
1996 Microchip Technology Inc.
DS20040J-page 7
59C11
NOTES:
DS20040J-page 8
1996 Microchip Technology Inc.
59C11
NOTES:
1996 Microchip Technology Inc.
DS20040J-page 9
59C11
NOTES:
DS20040J-page 10
1996 Microchip Technology Inc.
59C11
59C11 Product Identification System
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.
59C11
–
I
/P
Package:
P = Plastic DIP (300 mil Body)
SN = Plastic SOIC (150 mil Body)
SM = Plastic SOIC (207 mil Body)
Temperature
Range:
Blank = 0°C to +70°C
I = -40°C to +85°C
E = -40°C to +125°C
Device:
59C11
1K Microwire Serial EEPROM
59C11T
1K Microwire Serial EEPROM (Tape and Reel)
1996 Microchip Technology Inc.
DS20040J-page 11
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9/3/96
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All rights reserved. 1996, Microchip Technology Incorporated, USA. 9/96
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No repre-
sentation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement
of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not autho-
rized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and
name are registered trademarks of Microchip Technology Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
DS20040J-page 12
1996 Microchip Technology Inc.
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