5962-3826703MUX [MICROCHIP]
EEPROM, 128KX8, 200ns, Parallel, CMOS, CQCC32;
| 型号： | 5962-3826703MUX |
| 厂家： | 
MICROCHIP |
| 描述： | EEPROM, 128KX8, 200ns, Parallel, CMOS, CQCC32 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 内存集成电路 |
| 文件： | 总17页 (文件大小：432K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Fast Read Access Time - 120 ns
• Automatic Page Write Operation
– Internal Address and Data Latches for 128-Bytes
– Internal Control Timer
• Fast Write Cycle Time
AT28C010 Mil
– Page Write Cycle Time - 10 ms Maximum
– 1 to 128-Byte Page Write Operation
• Low Power Dissipation
– 80 mA Active Current
1-Megabit
(128K x 8)
Paged Parallel
EEPROMs
– 300µA CMOS Standby Current
• Hardware and Software Data Protection
• DATA Polling for End of Write Detection
• High Reliability CMOS Technology
– Endurance: 104 or 105 Cycles
– Data Retention: 10 Years
• Single 5V 10% Supply
• CMOS and TTL Compatible Inputs and Outputs
• JEDEC Approved Byte-Wide Pinout
AT28C010
Military
(continued)
Pin Configuration
32 LCC
Top View
Pin Name
A0 - A16
CE
Function
Addresses
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
No Connect
A7
A6
A5
A4
A3
A2 10
A1 11
A0 12
I/O0 13
5
6
7
8
9
29 A14
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE
21 I/O7
OE
WE
I/O0 - I/O7
NC
CERDIP, FLATPACK
Top View
44 LCC
Top View
NC
A16
A15
A12
A7
1
2
3
4
5
6
7
8
9
32 VCC
31 WE
30 NC
29 A14
28 A13
27 A8
PGA
Top View
A12
A7
7
8
9
39 A13
38 A8
37 A9
36 A11
35 NC
34 NC
33 NC
32 NC
31 OE
30 A10
29 CE
A6
A6
A5 10
NC 11
NC 12
NC 13
A4 14
A3 15
A2 16
A1 17
A5
26 A9
A4
25 A11
24 OE
23 A10
22 CE
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
A3
A2 10
A1 11
A0 12
I/O0 13
I/O1 14
I/O2 15
GND 16
Atmel-0010I-PEEPR-AT28C010-Datasheet_062015
Description
The AT28C010 is a high-performance Electrically Erasable and Programmable Read Only Mem-
ory. Its one megabit of memory is organized as 131,072 words by 8 bits. Manufactured with
Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 120 ns with
power dissipation of just 440 mW. When the device is deselected, the CMOS standby current is
less than 300A.
The AT28C010 is accessed like a Static RAM for the read or write cycle without the need for
external components. The device contains a 128-byte page register to allow writing of up to 128-
bytes simultaneously. During a write cycle, the address and 1 to 128-bytes of data are internally
latched, freeing the address and data bus for other operations. Following the initiation of a write
cycle, the device will automatically write the latched data using an internal control timer. The end
of a write cycle can be detected by DATA POLLING of I/O7. Once the end of a write cycle has
been detected a new access for a read or write can begin.
Atmel's 28C010 has additional features to ensure high quality and manufacturability. The device
utilizes internal error correction for extended endurance and improved data retention character-
istics. An optional software data protection mechanism is available to guard against inadvertent
writes. The device also includes an extra 128-bytes of EEPROM for device identification or
tracking.
Block Diagram
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Temperature Under Bias ............................... -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to VCC + 0.6V
Voltage on OE and A9
with Respect to Ground ...................................-0.6V to +13.5V
2
AT28C010 Military
Atmel-0010I-PEEPR-AT28C010-Datasheet_062015
AT28C010 Military
Device Operation
READ: The AT28C010 is accessed like a Static RAM. When CE and OE are low and WE is
high, the data stored at the memory location determined by the address pins is asserted on the
outputs. The outputs are put in the high impedance state when either CE or OE is high. This
dual-line control gives designers flexibility in preventing bus contention in their system.
BYTE WRITE: A low pulse on the WE or CE input with CE or WE low (respectively) and OE high
initiates a write cycle. The address is latched on the falling edge of CE or WE, whichever occurs
last. The data is latched by the first rising edge of CE or WE. Once a byte write has been started
it will automatically time itself to completion. Once a programming operation has been initiated
and for the duration of tWC, a read operation will effectively be a polling operation.
PAGE WRITE: The page write operation of the AT28C010 allows 1 to 128-bytes of data to be
written into the device during a single internal programming period. A page write operation is ini-
tiated in the same manner as a byte write; the first byte written can then be followed by 1 to 127
additional bytes. Each successive byte must be written within 150s (tBLC) of the previous byte.
If the tBLC limit is exceeded the AT28C010 will cease accepting data and commence the internal
programming operation. All bytes during a page write operation must reside on the same page
as defined by the state of the A7 - A16 inputs. For each WE high to low transition during the
page write operation, A7 - A16 must be the same.
The A0 to A6 inputs are used to specify which bytes within the page are to be written. The bytes
may be loaded in any order and may be altered within the same load period. Only bytes which
are specified for writing will be written; unnecessary cycling of other bytes within the page does
not occur.
DATA POLLING: The AT28C010 features DATA Polling to indicate the end of a write cycle.
During a byte or page write cycle an attempted read of the last byte written will result in the com-
plement of the written data to be presented on I/O7. Once the write cycle has been completed,
true data is valid on all outputs, and the next write cycle may begin. DATA Polling may begin at
anytime during the write cycle.
TOGGLE BIT: In addition to DATA Polling the AT28C010 provides another method for determin-
ing the end of a write cycle. During the write operation, successive attempts to read data from
the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6
will stop toggling and valid data will be read. Reading the toggle bit may begin at any time during
the write cycle.
DATA PROTECTION: If precautions are not taken, inadvertent writes may occur during transi-
tions of the host system power supply. Atmel has incorporated both hardware and software fea-
tures that will protect the memory against inadvertent writes.
HARDWARE PROTECTION: Hardware features protect against inadvertent writes to the
AT28C010 in the following ways: (a) VCC sense - if VCC is below 3.8V (typical) the write function
is inhibited; (b) VCC power-on delay - once VCC has reached 3.8V the device will automatically
time out 5 ms (typical) before allowing a write: (c) write inhibit - holding any one of OE low, CE
high or WE high inhibits write cycles; (d) noise filter - pulses of less than 15 ns (typical) on the
WE or CE inputs will not initiate a write cycle.
SOFTWARE DATA PROTECTION: A software controlled data protection feature has been
implemented on the AT28C010. When enabled, the software data protection (SDP), will prevent
inadvertent writes. The SDP feature may be enabled or disabled by the user; the AT28C010 is
shipped from Atmel with SDP disabled.
SDP is enabled by the host system issuing a series of three write commands; three specific
bytes of data are written to three specific addresses (refer to Software Data Protection Algo-
rithm). After writing the 3-byte command sequence and after tWC the entire AT28C010 will be
protected against inadvertent write operations. It should be noted, that once protected the host
may still perform a byte or page write to the AT28C010. This is done by preceding the data to be
written by the same 3-byte command sequence used to enable SDP.
3
Atmel-0010I-PEEPR-AT28C010-Datasheet_062015
Once set, SDP will remain active unless the disable command sequence is issued. Power transi-
tions do not disable SDP and SDP will protect the AT28C010 during power-up and power-down
conditions. All command sequences must conform to the page write timing specifications. The
data in the enable and disable command sequences is not written to the device and the memory
addresses used in the sequence may be written with data in either a byte or page write opera-
tion.
After setting SDP, any attempt to write to the device without the 3-byte command sequence will
start the internal write timers. No data will be written to the device; however, for the duration of
tWC, read operations will effectively be polling operations.
DEVICE IDENTIFICATION: An extra 128-bytes of EEPROM memory are available to the user
for device identification. By raising A9 to 12V 0.5V and using address locations 1FF80H to
1FFFFH the bytes may be written to or read from in the same manner as the regular memory
array.
OPTIONAL CHIP ERASE MODE: The entire device can be erased using a 6-byte software
code. Please see Software Chip Erase application note for details.
DC and AC Operating Range
AT28C010-12
-55°C - 125°C
5V 10%
AT28C010-15
-55°C - 125°C
5V 10%
AT28C010-20
-55°C - 125°C
5V 10%
AT28C010-25
-55°C - 125°C
5V 10%
Operating
Temperature (Case)
Mil.
VCC Power Supply
Operating Modes
Mode
CE
VIL
VIL
VIH
X
OE
VIL
VIH
X (1)
X
WE
VIH
VIL
X
I/O
Read
DOUT
DIN
Write (2)
Standby/Write Inhibit
Write Inhibit
Write Inhibit
Output Disable
High Z
VIH
X
X
VIL
VIH
X
X
High Z
Notes: 1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms
DC Characteristics
Symbol
Parameter
Condition
Min
Max
10
Units
A
ILI
Input Load Current
Output Leakage Current
VIN = 0V to VCC + 1V
VI/O = 0V to VCC
ILO
10
A
ISB1
ISB2
ICC
VCC Standby Current CMOS CE = VCC - 0.3V to VCC + 1V
300
3
A
VCC Standby Current TTL
VCC Active Current
CE = 2.0V to VCC + 1V
f = 5 MHz; IOUT = 0 mA
mA
mA
V
80
VIL
Input Low Voltage
0.8
4
AT28C010 Military
Atmel-0010I-PEEPR-AT28C010-Datasheet_062015
AT28C010 Military
DC Characteristics (Continued)
Symbol
Parameter
Condition
Min
Max
Units
VIH
Input High Voltage
Output Low Voltage
Output High Voltage
Output High Voltage CMOS
2.0
V
V
V
V
VOL
IOL = 2.1 mA
0.45
VOH1
VOH2
IOH = -400 A
2.4
4,2
IOH = -100 A; VCC = 4.5V
AC Read Characteristics
AT28C010-12
AT28C010-15
AT28C010-20
AT28C010-25
Symbol
Parameter
Min
Max
120
120
50
Min
Max
150
150
55
Min
Max
200
200
55
Min
Max
250
250
55
Units
tACC
Address to Output Delay
CE to Output Delay
OE to Output Delay
CE or OE to Output Float
ns
ns
ns
ns
ns
(1)
tCE
(2)
tOE
0
0
0
0
0
0
0
0
0
0
0
0
(3, 4)
tDF
50
55
55
55
tOH
Output Hold from OE, CE or
Address, whichever occurred first
(5)
tCEPH
CE Pulse High Time
50
50
50
50
ns
AC Read Waveforms(1)(2)(3)(4)
Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC
OE after an address change without impact in tACC
.
-
t
.
3. tDF is specified from OE or CE wichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
5. If CE is de-asserted, it must remain de-asserted for at least 50ns during read operations other-
wise incorrect data may be read.
5
Atmel-0010I-PEEPR-AT28C010-Datasheet_062015
Input Test Waveforms and
Measurement Level
Output Test Load
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
CIN
Typ
Max
10
Units
pF
Conditions
VIN = 0V
4
COUT
8
12
pF
VOUT = 0V
Note:
1. This parameter is 100% characterized and is not 100% tested.
AC Write Characteristics
Symbol
Parameter
Min
Max
Units
tWC
Write Cycle Time
Address Set-up Time
Address Hold Time
Data Set-up Time
Data Hold Time
10
ms
ns
ns
ns
ns
ns
s
ns
tAS
0
50
50
0
tAH
tDS
tDH
tWP
Write Pulse Width
Byte Load Cycle Time
Write Pulse Width High
100
tBLC
tWPH
150
50
6
AT28C010 Military
Atmel-0010I-PEEPR-AT28C010-Datasheet_062015
AT28C010 Military
AC Write Waveforms
WE Controlled
CE Controlled
Page Mode Characteristics
Symbol
tAS, tOES
tAH
Parameter
Min
0
Max
Units
ns
Address, OE Set-up Time
Address Hold Time
50
0
ns
tCS
Chip Select Set-up Time
Chip Select Hold Time
Write Pulse Width (WE or CE)
Data Set-up Time
ns
tCH
0
ns
tWP
100
50
0
ns
tDS
ns
tDH, tOEH
Data, OE Hold Time
ns
7
Atmel-0010I-PEEPR-AT28C010-Datasheet_062015
Page Mode Write Waveforms (1)(2)
Notes: 1. A7 through A16 must specify the page address during each high to low transition of WE (or
CE).
2. OE must be high only when WE and CE are both low.
8
AT28C010 Military
Atmel-0010I-PEEPR-AT28C010-Datasheet_062015
AT28C010 Military
Chip Erase Waveforms
tS = 5 msec (min.)
tW = tH = 10 msec (min.)
VH = 12.0V 0.5V
Software Data
Protection Enable Algorithm(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA A0
TO
ADDRESS 5555
WRITES ENABLED(2)
LOAD DATA XX
TO
ANY ADDRESS(4)
LOAD LAST BYTE
TO
LAST ADDRESS
ENTER DATA
PROTECT STATE
Notes: 1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. Write Protect state will be activated at end of write even if no other data is loaded.
3. Write Protect state will be deactivated at end of write period even if no other data if loaded.
4. 1 to 128 bytes of data are loaded.
9
Atmel-0010I-PEEPR-AT28C010-Datasheet_062015
Software Data
Protection Disable Algorithm(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 80
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 20
TO
ADDRESS 5555
EXIT DATA
PROTECT STATE(3)
LOAD DATA XX
TO
ANY ADDRESS(4)
LOAD LAST BYTE
TO
LAST ADDRESS
Software Protected Program Cycle Waveform(1)(2)(3)
Notes: 1. A0 - A14 must conform to the addressing sequence for the first 3 bytes as shown above.
2. After the command sequence has been issued and a page write operation follows, the page
address inputs (A7 - A16) must be the same for each high to low transition of WE (or CE).
3. OE must be high only when WE and CE are both low.
10
AT28C010 Military
Atmel-0010I-PEEPR-AT28C010-Datasheet_062015
AT28C010 Military
Data Polling Characterstics(1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
OE Hold Time
10
ns
OE to Output Delay (2)
Write Recovery Time
ns
tWR
0
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See AC Read Characteristics.
Data Polling Waveforms
Toggle Bit Characteristics(1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
tOEHP
tWR
OE Hold Time
10
ns
OE to Output Delay (2)
OE High Pulse
ns
150
0
ns
Write Recovery Time
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See AC Read Characteristics.
Toggle Bit Waveforms(1)(2)(3)
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit.
2. Beginning and ending state of I/O6 will vary.
3. Any addres location may be used but the address should not vary.
11
Atmel-0010I-PEEPR-AT28C010-Datasheet_062015
AT28C010 Ordering Information(1)
I
CC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
Operation Range
120
150
200
250
80
0.3
AT28C010(E)-12DM/883
AT28C010(E)-12EM/883
AT28C010(E)-12FM/883
AT28C010(E)-12LM/883
AT28C010(E)-12UM/883
32D6
32L1
32F
Military/883C
Class B, Fully Compliant
(-55C to 125C)
44L
30U
80
80
80
0.3
0.3
0.3
AT28C010(E)-15DM/883
AT28C010(E)-15EM/883
AT28C010-15FM/883
32D6
32L1
32F
Military/883C
Class B, Fully Compliant
(-55C to 125C)
AT28C010(E)-15LM/883
AT28C010(E)-15UM/883
44L
30U
AT28C010-20DM/883
AT28C010-20EM/883
AT28C010-20FM/883
AT28C010-20LM/883
AT28C010-20UM/883
32D6
32L1
32F
Military/883C
Class B, Fully Compliant
(-55C to 125C)
44L
30U
AT28C010-25DM/883
AT28C010-25EM/883
AT28C010-25FM/883
AT28C010-25LM/883
AT28C010-25UM/883
32D6
32L1
32F
Military/883C
Class B, Fully Compliant
(-55C to 125C)
44L
30U
AT28C010-W
Die Sales
Military
(-55C to 125C)
—
80
0.3
AT28C010-DWFM
Wafer Sales
Note:
1. See Valid Part Number table below.
Package Type
32D6
32-Lead, 0.600" Wide, Non-Windowed, Ceramic Dual Inline (Cerdip)
32-Lead, Non-Windowed, Ceramic Bottom-Brazed Flat Package (Flatpack)
32-Pad, Non-windowed, Combo Lid, Leadless Chip Carrier (LCC)
44-Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC)
30-Pin, Ceramic Pin Grid Array (PGA)
32F
32L1
44L
30U
W
Die
DWFM
Wafer
Options
Blank
E
Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms
High Endurance Option: Endurance = 100K Write Cycles
12
AT28C010 Military
Atmel-0010I-PEEPR-AT28C010-Datasheet_062015
AT28C010 Military
5962-38267 Ordering Information(1)
I
CC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
Operation Range
120
150
200
250
80
0.3
5962-38267 07 MXX
5962-38267 07 MUX
5962-38267 07 MZX
5962-38267 07 MYX
5962-38267 07 MTX
32D6
32L1
32F
Military/883C
Class B, Fully Compliant
(-55C to 125C)
44L
30U
80
80
80
0.3
0.3
5962-38267 05 MXX
5962-38267 05 MUX
5962-38267 05 MZX
5962-38267 05 MYX
5962-38267 05 MTX
32D6
32L1
32F
Military/883C
Class B, Fully Compliant
(-55C to 125C)
44L
30U
5962-38267 03 MXX
5962-38267 03 MUX
5962-38267 03 MZX
5962-38267 03 MYX
5962-38267 03 MTX
32D6
32L1
32F
Military/883C
Class B, Fully Compliant
(-55C to 125C)
44L
30U
0.3
5962-38267 01 MXX
5962-38267 01 MUX
5962-38267 01 MZX
5962-38267 01 MYX
5962-38267 01 MTX
32D6
32L1
32F
Military/883C
Class B, Fully Compliant
(-55C to 125C)
44L
30U
Note:
1. See Valid Part Number table below.
Package Type
32D6
32-Lead, 0.600" Wide, Non-Windowed, Ceramic Dual Inline (Cerdip)
32-Lead, Non-Windowed, Ceramic Bottom-Brazed Flat Package (Flatpack)
32-Pad, Non-windowed, Combo Lid, Leadless Chip Carrier (LCC)
44-Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC)
30-Pin, Ceramic Pin Grid Array (PGA)
32F
32L1
44L
30U
W
Die
DWFM
Wafer
Options
Blank
E
Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms
High Endurance Option: Endurance = 100K Write Cycles
13
Atmel-0010I-PEEPR-AT28C010-Datasheet_062015
Valid Part Numbers
The following table lists standard Atmel products that can be ordered.
Device Numbers
AT28C010
Speed
12
Package and Temperature Combinations
DM/883, EM/883, FM/883, LM/883, UM/883
DM/883, EM/883, LM/883, UM/883
DM/883, EM/883, FM/883, LM/883, UM/883
DM/883, EM/883, LM/883, UM/883
DM/883, EM/883, FM/883, LM/883, UM/883
DM/883, EM/883, FM/883, LM/883, UM/883
W, DWFN
AT28C010E
AT28C010
12
15
AT28C010E
AT28C010
15
20
AT28C010
25
AT28C010
–
Die Products
Reference Section: Parallel EEPROM Die Products
14
AT28C010 Military
Atmel-0010I-PEEPR-AT28C010-Datasheet_062015
AT28C010 Military
Packaging Information
32F, 32-Lead, Non-Windowed, Ceramic Bottom
32D6, 32-Lead, 0.600" Wide, Non-Windowed,
Ceramic Dual inline Package (Cerdip)
Dimensions in Millimeters and (Inches)
MIL-STD-1835 D-16 CONFIG A
Brazed Flat Package (Flatpack)
Dimensions in Millimeters and (Inches)
MIL-STD-1835 F-18 CONFIG B
42.70(1.68)
41.70(1.64)
PIN #1 ID
9.40(0.370)
6.86(0.270)
PIN
1
0.51(0.020)
0.38(0.015)
15.50(0.610)
13.00(0.510)
21.08(0.830)
20.60(0.811)
1.27(0.050) BSC
2.49(0.098)MAX
0.127(0.005)MIN
38.10(1.500) REF
5.72(0.225)
MAX
1.14(0.045) MAX
12.40(0.488)
11.99(0.472)
SEATING
PLANE
3.05(0.120)
2.49(0.098)
1.52(0.060)
0.38(0.015)
0.58(0.023)
0.36(0.014)
0.18(0.007)
0.10(0.004)
5.08(0.200)
3.18(0.125)
1.65(0.065)
1.14(0.045)
10.36(0.408)
9.02(0.355)
2.54(0.100)BSC
1.14(0.045)
0.66(0.026)
15.70(0.620)
15.00(0.590)
1.83(0.072)
0.76(0.030)
0º~ 15º REF
0.381(0.015)
0.203(0.008)
17.80(0.700) MAX
MIL-STD-1835 C-12
JEDEC OUTLINE MO-115
44L, 44-Pad, Non-Windowed, Ceramic
Leadless Chip Carrier (LCC)
32L1, 32-Pad, Non-windowed, Combo Lid, Leadless
Chip Carrier (LCC)
Dimensions in Millimeters* and (Inches)
Dimensions in Millimeters* and (Inches)
16.81(0.662)
16.26(0.640)
11.63(0.458)
11.23(0.442)
2.74(0.108)
2.16(0.085)
2.29(0.090)
1.91(0.075)
16.81(0.662)
16.26(0.640)
14.22(0.560)
13.72(0.540)
2.03(0.080)
1.40(0.055)
1.91(0.075)
1.40(0.055)
PIN 1
PIN 1
1.40(0.055)
1.14(0.045)
1.40(0.055)
1.14(0.045)
INDEX CORNER
INDEX CORNER
2.41(0.095)
1.91(0.075)
2.41(0.095)
1.91(0.075)
0.635(0.025)
X 45°
0.635(0.025)
X 45°
0.381(0.015)
0.381(0.015)
0.305(0.012)
0.178(0.007)
0.305(0.012)
0.178(0.007)
RADIUS
RADIUS
10.16(0.400) BSC
12.70(0.500) BSC
0.737(0.029)
0.533(0.021)
0.737(0.029)
0.533(0.021)
1.27(0.050) TYP
1.02(0.040) X 45°
1.27(0.050) TYP
1.02(0.040) X 45°
2.16(0.085)
1.65(0.065)
2.16(0.085)
1.65(0.065)
7.62(0.300) BSC
12.70(0.500) BSC
*Controlling dimension: millimeters
*Controlling dimension: millimeters
15
Atmel-0010I-PEEPR-AT28C010-Datasheet_062015
Packaging Information
30U, 30-Pin, Ceramic Pin Grid Array (PGA)
Dimensions in Millimeters and (Inches)
7.26(0.286)
6.50(0.256)
13.74(0.541)
13.36(0.526)
2.57(0.101)
2.06(0.081)
1.40(0.055)
1.14(0.045)
0.58(0.023)
0.43(0.017)
16.18(0.637)
15.82(0.623)
3.12(0.123)
2.62(0.103)
1.83(0.072)
1.57(0.062)
14.17(0.558)
13.77(0.542)
2.54(0.100) TYP
16.71(0.658)
16.31(0.642)
12.70(0.500) TYP
2.54(0.100) TYP
10.41(0.410)
9.91(0.390)
16
AT28C010 Military
Atmel-0010I-PEEPR-AT28C010-Datasheet_062015
X
X X X X
X
Atmel Corporation
1600 Technology Drive, San Jose, CA 95110 USA
T: (+1)(408) 441.0311
F: (+1)(408) 436.4200
|
www.atmel.com
© 2015 Atmel Corporation. / Rev.: Atmel-0010I-PEEPR-AT28C010-Military-Datasheet_062015.
Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities, and others are registered trademarks or trademarks of Atmel Corporation in U.S. and
other countries. Other terms and product names may be trademarks of others.
DISCLAIMER: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right
is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE
ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT
SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES
FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS
BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this
document and reserves the right to make changes to specifications and products descriptions at any time without notice. Atmel does not make any commitment to update the information
contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel products are not intended,
authorized, or warranted for use as components in applications intended to support or sustain life.
SAFETY-CRITICAL, MILITARY, AND AUTOMOTIVE APPLICATIONS DISCLAIMER: Atmel products are not designed for and will not be used in connection with any applications where
the failure of such products would reasonably be expected to result in significant personal injury or death (“Safety-Critical Applications”) without an Atmel officer's specific written
consent. Safety-Critical Applications include, without limitation, life support devices and systems, equipment or systems for the operation of nuclear facilities and weapons systems.
Atmel products are not designed nor intended for use in military or aerospace applications or environments unless specifically designated by Atmel as military-grade. Atmel products are
not designed nor intended for use in automotive applications unless specifically designated by Atmel as automotive-grade.
相关型号：
©2020 ICPDF网 联系我们和版权申明