34VL02T/OT [MICROCHIP]
256 X 8 I2C/2-WIRE SERIAL EEPROM, PDSO6, ROHS COMPLIANT, PLASTIC, SOT-23, 6 PIN;型号: | 34VL02T/OT |
厂家: | MICROCHIP |
描述: | 256 X 8 I2C/2-WIRE SERIAL EEPROM, PDSO6, ROHS COMPLIANT, PLASTIC, SOT-23, 6 PIN 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 双倍数据速率 光电二极管 内存集成电路 |
文件: | 总32页 (文件大小:676K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
34VL02
2K I2C™ Serial EEPROM Software Write-Protect
Features:
Package Types
PDIP/SOIC/TSSOP/MSOP/TDFN
• Permanent and Resettable Software Write-Protect
for Lower Half of the Array (00h-7Fh)
A0
A1
1
2
3
4
8
7
6
5
VCC
WP
1
VCC
A0
8
7
6
5
• Single Supply with Operation Down to 1.5V
• Low-Power CMOS Technology:
WP
2
3
4
A1
A2
SCL
SDA
A2
SCL
SDA
- Read current 1 mA, typical
VSS
- Standby current, 100 nA, typical
• 2-Wire Serial Interface Bus, I2C™ Compatible
• Cascadable up to Eight Devices
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz and 400 kHz Compatibility
• Page Write Time 3 ms, typical
VSS
SOT-23
1
SCL
VSS
6
VCC
A0
2
3
5
4
A1
SDA
• Self-Timed Erase/Write Cycle
• 16-Byte Page Write Buffer
Description:
• ESD Protection > 4,000V
The Microchip Technology Inc. 34VL02 is a 2 Kbit
Electrically Erasable PROM capable of operation
across a broad voltage range (1.5V to 3.6V). This
device has two software write-protect features for the
lower half of the array, as well as an external pin that
can be used to write-protect the entire array. This
allows the system designer to protect none, half, or all
of the array, depending on the application. The device
is organized as one block of 256 x 8-bit memory with a
2-wire serial interface. Low-voltage design permits
operation down to 1.5V, with standby and active cur-
rents of only 100 nA and 1 mA, respectively. The
34VL02 also has a page write capability for up to 16
bytes of data. The 34VL02 is available in the standard
8-pin PDIP, surface mount SOIC, TSSOP, MSOP and
TDFN packages. The 34VL02 is also available in the
6-lead, SOT-23 package.
• Hardware Write Protection for Entire Array
• More than 1 Million Erase/Write Cycles
• Data Retention > 200 Years
• 8-Lead PDIP, SOIC, TSSOP, MSOP and TDFN
packages
• 6-Lead SOT-23 Package
• Pb-free and RoHS Compliant
• Temperature Range:
- -20°C to +85°C
Device Selection Table
VCC
Range
Max. Clock
Frequency
Part Number
34VL02
1.5-3.6
400 kHz(1)
Note 1: 100 kHz for VCC <1.8V
© 2008 Microchip Technology Inc.
DS22079A-page 1
34VL02
Block Diagram
WP
A0 A1 A2
HV Generator
Software write-
protected area
(00h-7Fh)
I/O
Control
Logic
Memory
Control
Logic
XDEC
Standard
Array
SDA SCL
VCC
VSS
Write-Protect
Circuitry
YDEC
Sense Amp.
R/W Control
DS22079A-page 2
© 2008 Microchip Technology Inc.
34VL02
1.0
ELECTRICAL CHARACTERISTICS
(†)
Absolute Maximum Ratings
VCC.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ..........................................................................................................-0.3V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied..................................................................................................-20°C to +85°C
ESD protection on all pins ......................................................................................................................................................≥ 4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. These are stress ratings only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
TABLE 1-1:
DC SPECIFICATIONS
VCC = +1.5V to +3.6V
Temperature Range: -20°C to +85°C
DC CHARACTERISTICS
Param.
Symbol
No.
Characteristic
Min.
Typ.
Max.
Units
Conditions
—
A0, A1, A2, SCL, SDA
and WP pins
—
—
—
—
—
—
D1
D2
D3
VIH
High-level input voltage
Low-level input voltage
0.7 VCC
—
—
—
—
—
0.3 VCC
—
V
V
V
VIL
0.2 VCC for VCC < 2.5V
VHYS
Hysteresis of Schmitt
Trigger inputs
0.05 VCC
(Note)
D4
D5
VOL
VHV
Low-level output voltage
High-Voltage Detect
—
—
—
—
—
—
—
0.40
10
V
V
IOL = 3.0 mA, VCC = 2.5V
A0 Pin only, VCC < 2.2V
A0 Pin only, VCC ≥ 2.2V
VIN = VSS or VCC
7
VCC + 4.8
10
V
D6
D7
D8
ILI
Input leakage current
Output leakage current
—
—
—
±1
μA
μA
pF
ILO
±1
VOUT = VSS or VCC
CIN,
Pin capacitance
10
VCC = 3.6V (Note)
COUT
(all inputs/outputs)
TA = 25°C
D9
ICC write Operating current
ICC read
—
—
—
0.1
3
1
1
mA
mA
μA
VCC = 3.6V
—
D10
D11
0.05
0.01
ICCS
Standby current
SDA = SCL = VCC
A0, A1, A2, WP = VSS
Note: This parameter is periodically sampled and not 100% tested.
© 2008 Microchip Technology Inc.
DS22079A-page 3
34VL02
TABLE 1-2:
AC SPECIFICATIONS
VCC = +1.5V to +3.6V
Temperature Range: -20°C to +85°C
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristic
Clock frequency
Min.
Max.
Units
Conditions
1.5V ≤ VCC < 1.8V
1
2
3
4
5
6
7
FCLK
THIGH
TLOW
TR
—
—
100
400
kHz
1.8V ≤ VCC ≤ 3.6V
Clock high time
4000
600
—
—
ns
ns
ns
ns
ns
ns
1.5V ≤ VCC < 1.8V
1.8V ≤ VCC ≤ 3.6V
Clock low time
4700
1300
—
—
1.5V ≤ VCC < 1.8V
1.8V ≤ VCC ≤ 3.6V
SDA and SCL rise time (Note 1)
SDA and SCL fall time (Note 1)
Start condition hold time
Start condition setup time
—
—
1000
300
1.5V ≤ VCC < 1.8V
1.8V ≤ VCC ≤ 3.6V
TF
—
—
1000
300
1.5V ≤ VCC < 1.8V
1.8V ≤ VCC ≤ 3.6V
THD:STA
TSU:STA
4000
600
—
—
1.5V ≤ VCC < 1.8V
1.8V ≤ VCC ≤ 3.6V
4700
600
—
—
1.5V ≤ VCC < 1.8V
1.8V ≤ VCC ≤ 3.6V
8
9
THD:DAT
TSU:DAT
Data input hold time
Data input setup time
0
—
ns
ns
(Note 2)
250
100
—
—
1.5V ≤ VCC < 1.8V
1.8V ≤ VCC ≤ 3.6V
10
11
12
13
14
TSU:STO
TSU:WP
THD:WP
TAA
Stop condition setup time
WP setup time
4000
600
—
—
ns
ns
ns
ns
ns
1.5V ≤ VCC < 1.8V
1.8V ≤ VCC ≤ 3.6V
4000
600
—
—
1.5V ≤ VCC < 1.8V
1.8V ≤ VCC ≤ 3.6V
WP hold time
4700
600
—
—
1.5V ≤ VCC < 1.8V
1.8V ≤ VCC ≤ 3.6V
Output valid from clock (Note 2)
—
—
3500
900
1.5V ≤ VCC < 1.8V
1.8V ≤ VCC ≤ 3.6V
TBUF
Bus free time: Time the bus must be
free before a new transmission can
start
1300
4700
—
—
1.5V ≤ VCC < 1.8V
1.8V ≤ VCC ≤ 3.6V
16
TSP
Input filter spike suppression
(SDA and SCL pins)
—
50
ns
(Note 1 and Note 3)
17
18
TWC
—
Write cycle time (byte or page)
Endurance
—
5
ms
—
1M
—
cycles 25°C, VCC = 3.6V, Block mode
(Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the
falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved noise spike suppres-
sion. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult
the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com.
DS22079A-page 4
© 2008 Microchip Technology Inc.
34VL02
FIGURE 1-1:
BUS TIMING DATA
5
4
D4
2
SCL
7
3
10
8
9
SDA
In
6
16
14
12
13
SDA
Out
(protected)
WP
11
(unprotected)
© 2008 Microchip Technology Inc.
DS22079A-page 5
34VL02
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of data
bytes transferred between the Start and Stop
conditions is determined by the master device and is,
theoretically, unlimited; although only the last sixteen
will be stored when doing a write operation. When an
overwrite does occur, it will replace data in a first-in,
first-out (FIFO) fashion.
2.0
FUNCTIONAL DESCRIPTION
The 34VL02 has two Software Write-Protect features
that allow you to protect half of the array from being
written (Addresses 00h-7Fh). One command, Software
Write-Protect (SWP) will prevent writes to half of the
array and is resettable by using the Clear Software
Write-Protect (CSWP) command. The other command
is Permanent Software Write-Protect (PSWP), which is
not resettable and will permanently lock half the array
from being written to. The device still has an external
pin (WP) that allows you to protect the entire array if so
desired.
3.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an Acknowledge after the reception of each
byte. Exceptions to this rule relating to software write
protection are described in Section 7.0 “Write Protec-
tion”. The master device must generate an extra clock
pulse, which is associated with this Acknowledge bit.
The 34VL02 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, and a device
receiving data, as a receiver. The bus has to be
controlled by a master device, which generates the
Serial Clock (SCL), controls the bus access and gener-
ates the Start and Stop conditions, while the 34VL02
works as slave. Both master and slave can operate as
transmitter or receiver, but the master device
determines which mode is activated.
Note: The 34VL02 does not generate any
Acknowledge
bits
if
an
internal
programming cycle is in progress.
The device that acknowledges has to pull down the
SDA line during the Acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end-of-
data to the slave by not generating an Acknowledge bit
on the last byte that has been clocked out of the slave.
In this case, the slave (34VL02) will leave the data line
high to enable the master to generate the Stop
condition.
3.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.1
Bus Not Busy (A)
Both data and clock lines remain high.
3.2
Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
3.3
Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
3.4
Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.
DS22079A-page 6
© 2008 Microchip Technology Inc.
34VL02
FIGURE 3-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)
(B)
(D)
(D)
(C) (A)
SCL
SDA
Start
Condition
Stop
Condition
Address or
Acknowledge
Valid
Data
Allowed
to Change
3.6
Device Addressing
4.0
4.1
WRITE OPERATIONS
Byte Write
A control byte is the first byte received following the
Start condition from the master device. The first part of
the control byte consists of a 4-bit control code which is
set to ‘1010’ for normal read and write operations and
‘0110’ for writing to the write-protect register. The
control byte is followed by three Chip Select bits (A2,
A1, A0). The Chip Select bits allow the use of up to
eight 34VL02 devices on the same bus and are used to
determine which device is accessed. The Chip Select
bits in the control byte must correspond to the logic lev-
els on the corresponding A2, A1 and A0 pins for the
device to respond.
Following the Start signal from the master, the device
code(4 bits), the Chip Select bits (3 bits) and the R/W
bit, which is a logic low, are placed onto the bus by the
master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will follow,
once it has generated an Acknowledge bit during the
ninth clock cycle. Therefore, the next byte transmitted
by the master is the word address and will be written
into the Address Pointer of the 34VL02.
After receiving another Acknowledge signal from the
34VL02, the master device will transmit the data word to
be written into the addressed memory location. The
34VL02 acknowledges again and the master generates
a Stop condition. This initiates the internal write cycle,
which means that during this time, the 34VL02 will not
generate Acknowledge signals (Figure 4-1). If an
attempt is made to write to the array when the software
or hardware write protection has been enabled, the
device will acknowledge the command, but no data will
be written. The write cycle time must be observed even
if the write protection is enabled.
The eighth bit of slave address determines if the master
device wants to read or write to the 34VL02
(Figure 3-2). When set to a one, a read operation is
selected. When set to a zero, a write operation is
selected.
Control
Code
Chip
Select
Operation
R/W
Read
Write
1010
1010
0110
A2 A1 A0
A2 A1 A0
A2 A1 A0
1
0
0
Write-Protect Register
4.2
Page Write
FIGURE 3-2:
CONTROL BYTE
ALLOCATION
The write control byte, word address and the first data
byte are transmitted to the 34VL02 in the same way as
in a byte write. Instead of generating a Stop condition,
the master transmits up to 15 additional data bytes to
the 34VL02, which are temporarily stored in the on-chip
page buffer and will be written into the memory after the
master has transmitted a Stop condition. Upon receipt
of each word, the four lower order Address Pointer bits
are internally incremented by one. The higher order
four bits of the word address remain constant. If the
master should transmit more than 16 bytes prior to gen-
erating the Stop condition, the address counter will roll
over and the previously received data will be overwrit-
ten. As with the byte write operation, once the Stop
condition is received, an internal write cycle will begin
Start
Read/Write
Slave Address
R/W A
1
0
0
1
1
0
A2
A1
A1
A0
A0
OR
0
1
A2
© 2008 Microchip Technology Inc.
DS22079A-page 7
34VL02
(Figure 4-2). If an attempt is made to write to the array
when the hardware write protection has been enabled,
the device will acknowledge the command, but no data
will be written. The write cycle time must be observed
even if the write protection is enabled.
Note: Page write operations are limited to writing
bytes within single physical page,
a
regardless of the number of bytes actually
being written. Physical page boundaries
start at addresses that are integer multi-
ples of the page buffer size (or ‘page size’)
and end at addresses that are integer mul-
tiples of [page size – 1]. If a Page Write
command attempts to write across a phys-
ical page boundary, the result is that the
data wraps around to the beginning of the
current page (overwriting data previously
stored there), instead of being written to
the next page, as might be expected. It is
therefore necessary for the application
software to prevent page write operations
that would attempt to cross a page
boundary.
FIGURE 4-1:
BYTE WRITE
S
T
A
R
T
S
T
O
P
Bus Activity
Master
Control
Byte
Word
Address
Data
SDA Line
S
P
A
C
K
A
C
K
A
C
K
Bus Activity
FIGURE 4-2:
PAGE WRITE
S
S
T
T
Bus Activity
Master
Control
Byte
Word
Address (n)
A
R
T
S
O
P
Data (n)
Data (n + 1)
Data (n + 15)
SDA Line
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Bus Activity
DS22079A-page 8
© 2008 Microchip Technology Inc.
34VL02
5.0
ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a Write
command has been issued from the master, the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a Start condition followed by the control byte
for a Write command (R/W = 0). If the device is still
busy with the write cycle, then no ACK will be returned.
If the cycle is complete, then the device will return the
ACK and the master can then proceed with the next
Read or Write command. See Figure 5-1 for flow
diagram.
FIGURE 5-1:
ACKNOWLEDGE
POLLING FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
No
Yes
Next
Operation
© 2008 Microchip Technology Inc.
DS22079A-page 9
34VL02
6.3
Sequential Read
6.0
READ OPERATION
Sequential reads are initiated in the same way as a
random read, with the exception that after the 34VL02
transmits the first data byte, the master issues acknowl-
edge, as opposed to a Stop condition in a random read.
This directs the 34VL02 to transmit the next sequentially
addressed 8-bit word (Figure 6-3).
Read operations are initiated in the same way as write
operations, with the exception that the R/W bit of the
slave address is set to ‘1’. There are three basic types
of read operations: current address read, random read
and sequential read.
6.1
Current Address Read
To provide sequential reads, the 34VL02 contains an
internal Address Pointer, which is incremented by one
at the completion of each operation. This Address
Pointer allows the entire memory contents to be serially
read during one operation.
The 34VL02 contains an address counter that
maintains the address of the last word accessed, inter-
nally incremented by ‘1’. Therefore, if the previous
access (either a read or write operation) was to
address n, the next current address read operation
would access data from address n+1. Upon receipt of
the slave address with R/W bit set to ‘1’, the 34VL02
issues an acknowledge and transmits the 8-bit data
word. The master will not acknowledge the transfer, but
does generate a Stop condition and the 34VL02
discontinues transmission (Figure 6-1).
6.4
Contiguous Addressing Across
Multiple Devices
The Chip Select bits (A2, A1, A0) can be used to
expand the contiguous address space for up to 16K bits
by adding up to eight 34VL02 devices on the same bus.
In this case, software can use A0 of the control byte as
address bit A8; A1 as address bit A9, and A2 as
address bit A10. It is not possible to sequentially read
across device boundaries.
6.2
Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, the word address must first
be set. This is done by sending the word address to the
34VL02 as part of a write operation. Once the word
address is sent, the master generates a Start condition
following the acknowledge. This terminates the write
operation, but not before the internal Address Pointer is
set. The master then issues the control byte again, but
with the R/W bit set to a ‘1’. The 34VL02 then issues an
acknowledge and transmits the 8-bit data word. The
master will not acknowledge the transfer, but does
6.5
Noise Protection and Brown-Out
The 34VL02 employs a VCC threshold detector circuit
which disables the internal erase/write logic if the VCC
is below 1.35V at nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation, even on a noisy bus.
generate
a
Stop condition and the 34VL02
discontinues transmission (Figure 6-2).
FIGURE 6-1:
CURRENT ADDRESS READ
S
T
A
R
Bus Activity
Master
Control
Byte
S
T
Data (n)
O
P
T
SDA Line
S
P
A
C
K
N
O
Bus Activity
A
C
K
DS22079A-page 10
© 2008 Microchip Technology Inc.
34VL02
FIGURE 6-2:
RANDOM READ
S
T
A
R
T
S
T
A
R
T
S
T
O
P
Bus Activity
Master
Control
Byte
Word
Address (n)
Control
Byte
Data (n)
S
P
S
SDA Line
A
C
K
A
C
K
A
C
K
N
O
Bus Activity
A
C
K
FIGURE 6-3:
SEQUENTIAL READ
S
T
O
P
Bus Activity
Master
Control
Byte
Data (n)
Data (n + 1)
Data (n + 2)
Data (n + X)
SDA Line
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
Bus Activity
A
C
K
© 2008 Microchip Technology Inc.
DS22079A-page 11
34VL02
7.2
Software Write Protection (SWP)
and Clear Software Write
Protection (CSWP)
7.0
WRITE PROTECTION
The 34VL02 has two software write-protect features
(SWP and PSWP) that allows the lower half of the array
(addresses 00h-7Fh) to be write-protected, as well as
a WP pin that can be used to protect the entire array.
The permanent software write-protect feature is
enabled by sending the device a special command.
Once this feature has been enabled, it cannot be
reversed. The resettable software write-protect feature
is also enabled by sending the device a special
command but can be reset by issuing another special
command. In addition to the software protect features,
there is a WP pin that can be used to write-protect the
entire array, regardless of whether the software write-
protect register has been written or not.
In addition to hardware write-protect the 34VL02 has
an additional software write-protect feature that, when
set, protects the first 128 bytes (00-7Fh) of the array
from being written.
Setting the software write protection is done by sending
the SWPinstruction. SWP can also then be cleared by
issuing a CSWPinstruction (see Figure 7-1).
These two instructions follow the same format as the
BYTE WRITE instruction with the exception of the
Device Type Identifier, (typically ‘1010’, instead
changes to ‘0110’). Once this identifier is recognized
by the device, the rest of the Byte Write command,
address and data, are “don’t cares”. In addition to the
identifier, high voltage must be applied to the A0 pin of
the device and specific levels must be present on A1
and A2. See Table 7-1 for the available commands.
Table 7-2 and Table 7-3 describe how the 34VL02 will
acknowledge specific commands under various
circumstances.
7.1
Hardware Write Protection
The WP pin allows the user to write-protect the entire
array (00-FF) when the pin is tied to VCC. If the pin is
tied to VSS the write protection is disabled.
7.3
Permanent Software Write-Protect
(PSWP)
The Permanent software write protection, or PSWP is
another instruction that may be used to permanently
protect the first 128 byte of the array. Once this
command is issued, the user will no longer have the
ability to clear this feature regardless of instruction,
power cycling, or state of the WP pin. Also, once this
instruction has been executed, the device will no
longer acknowledge the device identifier ‘0110’.
FIGURE 7-1:
SOFTWARE WRITE PROTECTION FOR SWP, CSWP, PSWP, OR CPSWP
S
Bus Activity
Master
T
A
R
T
S
T
O
P
Control
Byte
Address
Byte
Data
A A A
SDA Line
S 0 1 1 0
0
P
2 1 0
A
C
K
A
C
K
A
C
K
Bus Activity
“Don’t Care”
“Don’t Care”
DS22079A-page 12
© 2008 Microchip Technology Inc.
34VL02
TABLE 7-1:
SOFTWARE WRITE PROTECTION INSTRUCTION SET WP = 0
Device Type
Address Pins
Chip Select Bits
R/W
B0
Identifier
A2
A1
A0
B7
B6 B5 B4
B3
B2
B1
SWP
CSWP
PSWP
VSS
VSS
A2
VSS
VCC
A1
VHV
VHV
A0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
1
1
A2
0
A1
0
A0
1
Read SWP
Read CSWP
Read PSWP
VSS
VSS
A2
VSS
VCC
A1
VHV
VHV
A0
0
1
1
A2
A1
A0
1. A0 is used to detect VHV for the SWP and CSWP commands.
2. B3, B2 and B1 are compared to the A2, A1 and A0 external pins, respectively on the 34XX02.
TABLE 7-2:
Status
ACKNOWLEDGE TABLE FOR WRITE OR WRITE PROTECTION WITH R/W = 0
Write-
Write
Cycle
Instruction
ACK Address
ACK Data Byte
ACK
Protect
No
No
Ack
PSWP, SWP, CSWP
PAGEor BYTE
Don’t Care
Ack
Don’t Care No Ack
No
No
No
Permanently Protected
x
WRITEin lower 128 Ack
Address
Ack
Data
No Ack
bytes
No
Ack
No
Ack
SWP
Don’t Care
Don’t Care No Ack
CSWP
PSWP
Ack Don’t Care Ack Don’t Care
Ack Don’t Care Ack Don’t Care
Ack
Ack
Yes
Yes
0
1
PAGEor BYTE
WRITEin lower 128 Ack
Address
Ack
Data
No Ack
No
bytes
Protected with SWP
No
Ack
No
Ack
SWP
Don’t Care
Don’t Care No Ack
No
CSWP
PSWP
Ack Don’t Care Ack Don’t Care No Ack
Ack Don’t Care Ack Don’t Care No Ack
No
No
PAGEor BYTE
Ack
Address
Ack
Data
No Ack
Ack
No
Yes
Yes
No
WRITE
PSWP, SWP, or CSWP Ack Don’t Care Ack Don’t Care
0
1
PAGEor BYTE
Ack
Address
Ack
Data
Ack
WRITE
Not Protected
PSWP, SWP, or CSWP Ack Don’t Care Ack Don’t Care No Ack
PAGEor BYTE
Ack
Address
Ack
Address
No Ack
No
WRITE
TABLE 7-3:
ACKNOWLEDGE TABLE FOR WRITE OR WRITE PROTECTION WITH R/W = 1
Status
Instruction
ACK
Permanently Protected
Protected with SWP
Not protected
PSWP, SWP, CSWP
SWP
No Ack
No Ack
Ack
CSWP
PSWP
Ack
PSWP, SWP, CSWP
Ack
© 2008 Microchip Technology Inc.
DS22079A-page 13
34VL02
8.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 8-1.
TABLE 8-1:
Symbol
PIN FUNCTION TABLE
PDIP
SOIC
TSSOP
MSOP
TDFN
SOT-23
Description
A0
A1
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
5
4
Chip Address Input
Chip Address Input
Chip Address Input
Ground
A2
NC
2
VSS
SDA
SCL
WP
VCC
3
Serial Address/Data I/O
Serial Clock
1
NC
6
Write-Protect Input
+1.5V to 3.6V Power Supply
8.1
A0, A1, A2
8.3
Serial Clock (SCL)
The levels on these inputs are compared with the
corresponding bits in the slave address. The chip is
selected if the compare is true.
This input is used to synchronize the data transfer to
and from the device.
8.4
Write-Protect (WP)
Up to eight 34VL02 devices may be connected to the
same bus by using different Chip Select bit
combinations. These inputs must be connected to
either VSS or VCC.
This is the hardware write-protect pin. It can be tied to
VCC or VSS. If tied to VCC, the hardware write protection
is enabled. If the WP pin is tied to VSS, the hardware
write protection is disabled.
The A0 pin is also used to detect VHV.
8.2
Serial Address/Data Input/Output
(SDA)
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal. Therefore, the SDA bus requires a pull-
up resistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for
400 kHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
DS22079A-page 14
© 2008 Microchip Technology Inc.
34VL02
9.0
9.1
PACKAGING INFORMATION
Package Marking Information
8-Lead PDIP (300 mil)
Example:
34VL02
XXXXXXXX
TXXXXNNN
e
3
/P
3EC
YYWW
0810
8-Lead SOIC (3.90 mm)
Example:
34VL02
XXXXXXXT
e
3
XXXXYYWW
SN
0810
NNN
3EC
Example:
8-Lead TSSOP
34V2
810
XXXX
TYWW
NNN
3EC
Example:
8-Lead MSOP
XXXXXT
34VL2
8103EC
YWWNNN
8-Lead 2x3 TDFN
Example:
AJ7
810
3E
XXX
YWW
NN
1st Line Marking Codes
Part Number
TSSOP
MSOP
TDFN
SOT-23
34VL02
34V2
34VL2T
AJ7
SMNN
© 2008 Microchip Technology Inc.
DS22079A-page 15
34VL02
Example:
SMEC
6-Lead SOT-23
XXNN
Legend: XX...X Part number or part number code
T
Temperature (I, E)
Y
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code (2 characters for small packages)
Pb-free JEDEC designator for Matte Tin (Sn)
YY
WW
NNN
e
3
Note:
For very small packages with no room for the Pb-free JEDEC designator
, the marking will only appear on the outer carton or reel label.
e
3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
Note:
Please visit www.microchip.com/Pbfree for the latest information on Pb-free conversion.
*Standard OTP marking consists of Microchip part number, year code, week code, and traceability code.
DS22079A-page 16
© 2008 Microchip Technology Inc.
34VL02
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© 2008 Microchip Technology Inc.
DS22079A-page 17
34VL02
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ꢔꢃꢌꢉꢋꢌꢍꢃꢓ ꢙꢈꢌꢍꢄꢋꢇꢋꢑꢊ ꢒꢉꢆ*ꢃꢄꢑ ,ꢕꢖꢞꢕꢘꢜ1
DS22079A-page 18
© 2008 Microchip Technology Inc.
34VL02
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ ꢕꢄꢈꢈꢆ!ꢎꢊꢈꢋꢐꢃꢆꢑ ꢛꢒꢆMꢆꢛꢄ""ꢗ#$ꢆꢓ%&ꢔꢆꢕꢕꢆꢖꢗꢅꢘꢆꢙ !ꢏ'ꢚ
ꢛꢗꢊꢃꢜ 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢓꢆꢌ4ꢆꢑꢈꢅ#ꢉꢆ*ꢃꢄꢑ!(ꢅꢓꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢔꢃꢌꢉꢋꢌꢍꢃꢓꢅꢂꢆꢌ4ꢆꢑꢃꢄꢑꢅꢐꢓꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ
ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ
© 2008 Microchip Technology Inc.
DS22079A-page 19
34VL02
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ()ꢋꢐꢆ )"ꢋꢐ*ꢆ ꢕꢄꢈꢈꢆ!ꢎꢊꢈꢋꢐꢃꢆꢑ (ꢒꢆMꢆ+%+ꢆꢕꢕꢆꢖꢗꢅꢘꢆꢙ( !ꢇꢚ
ꢛꢗꢊꢃꢜ 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢓꢆꢌ4ꢆꢑꢈꢅ#ꢉꢆ*ꢃꢄꢑ!(ꢅꢓꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢔꢃꢌꢉꢋꢌꢍꢃꢓꢅꢂꢆꢌ4ꢆꢑꢃꢄꢑꢅꢐꢓꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ
ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ
D
N
E
E1
NOTE 1
1
2
b
e
c
φ
A
A2
A1
L
L1
6ꢄꢃ&!
ꢔꢚ99ꢚꢔ.ꢙ.ꢝꢐ
ꢒꢃ'ꢈꢄ!ꢃꢋꢄꢅ9ꢃ'ꢃ&!
ꢔꢚ7
7:ꢔ
ꢔꢗ;
7"')ꢈꢉꢅꢋ%ꢅꢂꢃꢄ!
ꢂꢃ&ꢌꢍ
7
ꢈ
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ꢕꢁ?ꢘꢅ1ꢐ,
: ꢈꢉꢆꢇꢇꢅ8ꢈꢃꢑꢍ&
ꢔꢋꢇ#ꢈ#ꢅꢂꢆꢌ4ꢆꢑꢈꢅꢙꢍꢃꢌ4ꢄꢈ!!
ꢐ&ꢆꢄ#ꢋ%%ꢅ
ꢗ
M
ꢕꢁ<ꢕ
ꢕꢁꢕꢘ
M
ꢀꢁꢕꢕ
M
ꢀꢁꢎꢕ
ꢀꢁꢕꢘ
ꢕꢁꢀꢘ
ꢗꢎ
ꢗꢀ
.
: ꢈꢉꢆꢇꢇꢅ>ꢃ#&ꢍ
?ꢁꢖꢕꢅ1ꢐ,
ꢔꢋꢇ#ꢈ#ꢅꢂꢆꢌ4ꢆꢑꢈꢅ>ꢃ#&ꢍ
ꢔꢋꢇ#ꢈ#ꢅꢂꢆꢌ4ꢆꢑꢈꢅ9ꢈꢄꢑ&ꢍ
3ꢋꢋ&ꢅ9ꢈꢄꢑ&ꢍ
.ꢀ
ꢒ
9
ꢖꢁ-ꢕ
ꢎꢁꢛꢕ
ꢕꢁꢖꢘ
ꢖꢁꢖꢕ
-ꢁꢕꢕ
ꢕꢁ?ꢕ
ꢖꢁꢘꢕ
-ꢁꢀꢕ
ꢕꢁꢜꢘ
3ꢋꢋ&ꢓꢉꢃꢄ&
3ꢋꢋ&ꢅꢗꢄꢑꢇꢈ
9ꢈꢆ#ꢅꢙꢍꢃꢌ4ꢄꢈ!!
9ꢈꢆ#ꢅ>ꢃ#&ꢍ
9ꢀ
ꢀ
ꢀꢁꢕꢕꢅꢝ.3
ꢕꢟ
ꢕꢁꢕꢛ
ꢕꢁꢀꢛ
M
M
M
<ꢟ
ꢌ
)
ꢕꢁꢎꢕ
ꢕꢁ-ꢕ
ꢛꢗꢊꢃꢉꢜ
ꢀꢁ ꢂꢃꢄꢅꢀꢅ ꢃ!"ꢆꢇꢅꢃꢄ#ꢈ$ꢅ%ꢈꢆ&"ꢉꢈꢅ'ꢆꢊꢅ ꢆꢉꢊ(ꢅ)"&ꢅ'"!&ꢅ)ꢈꢅꢇꢋꢌꢆ&ꢈ#ꢅ*ꢃ&ꢍꢃꢄꢅ&ꢍꢈꢅꢍꢆ&ꢌꢍꢈ#ꢅꢆꢉꢈꢆꢁ
ꢎꢁ ꢒꢃ'ꢈꢄ!ꢃꢋꢄ!ꢅꢒꢅꢆꢄ#ꢅ.ꢀꢅ#ꢋꢅꢄꢋ&ꢅꢃꢄꢌꢇ"#ꢈꢅ'ꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢓꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢁꢅꢔꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢓꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢅ!ꢍꢆꢇꢇꢅꢄꢋ&ꢅꢈ$ꢌꢈꢈ#ꢅꢕꢁꢀꢘꢅ''ꢅꢓꢈꢉꢅ!ꢃ#ꢈꢁ
-ꢁ ꢒꢃ'ꢈꢄ!ꢃꢋꢄꢃꢄꢑꢅꢆꢄ#ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢃꢄꢑꢅꢓꢈꢉꢅꢗꢐꢔ.ꢅ0ꢀꢖꢁꢘꢔꢁ
1ꢐ,2 1ꢆ!ꢃꢌꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄꢁꢅꢙꢍꢈꢋꢉꢈ&ꢃꢌꢆꢇꢇꢊꢅꢈ$ꢆꢌ&ꢅ ꢆꢇ"ꢈꢅ!ꢍꢋ*ꢄꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ!ꢁ
ꢝ.32 ꢝꢈ%ꢈꢉꢈꢄꢌꢈꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄ(ꢅ"!"ꢆꢇꢇꢊꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ(ꢅ%ꢋꢉꢅꢃꢄ%ꢋꢉ'ꢆ&ꢃꢋꢄꢅꢓ"ꢉꢓꢋ!ꢈ!ꢅꢋꢄꢇꢊꢁ
ꢔꢃꢌꢉꢋꢌꢍꢃꢓ ꢙꢈꢌꢍꢄꢋꢇꢋꢑꢊ ꢒꢉꢆ*ꢃꢄꢑ ,ꢕꢖꢞꢕ<?1
DS22079A-page 20
© 2008 Microchip Technology Inc.
34VL02
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ,ꢋꢌ"ꢗꢆ ꢕꢄꢈꢈꢆ!ꢎꢊꢈꢋꢐꢃꢆꢇꢄꢌ*ꢄ-ꢃꢆꢑ, ꢒꢆꢙ, !ꢇꢚ
ꢛꢗꢊꢃꢜ 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢓꢆꢌ4ꢆꢑꢈꢅ#ꢉꢆ*ꢃꢄꢑ!(ꢅꢓꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢔꢃꢌꢉꢋꢌꢍꢃꢓꢅꢂꢆꢌ4ꢆꢑꢃꢄꢑꢅꢐꢓꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ
ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ
D
N
E
E1
NOTE 1
2
b
1
e
c
φ
A2
A
L
L1
A1
6ꢄꢃ&!
ꢔꢚ99ꢚꢔ.ꢙ.ꢝꢐ
ꢒꢃ'ꢈꢄ!ꢃꢋꢄꢅ9ꢃ'ꢃ&!
ꢔꢚ7
7:ꢔ
ꢔꢗ;
7"')ꢈꢉꢅꢋ%ꢅꢂꢃꢄ!
ꢂꢃ&ꢌꢍ
7
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ꢕꢁ?ꢘꢅ1ꢐ,
: ꢈꢉꢆꢇꢇꢅ8ꢈꢃꢑꢍ&
ꢔꢋꢇ#ꢈ#ꢅꢂꢆꢌ4ꢆꢑꢈꢅꢙꢍꢃꢌ4ꢄꢈ!!
ꢐ&ꢆꢄ#ꢋ%%ꢅ
: ꢈꢉꢆꢇꢇꢅ>ꢃ#&ꢍ
ꢔꢋꢇ#ꢈ#ꢅꢂꢆꢌ4ꢆꢑꢈꢅ>ꢃ#&ꢍ
: ꢈꢉꢆꢇꢇꢅ9ꢈꢄꢑ&ꢍ
3ꢋꢋ&ꢅ9ꢈꢄꢑ&ꢍ
ꢗ
M
ꢕꢁꢜꢘ
ꢕꢁꢕꢕ
M
ꢕꢁ<ꢘ
ꢀꢁꢀꢕ
ꢕꢁꢛꢘ
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ꢗꢎ
ꢗꢀ
.
.ꢀ
ꢒ
M
ꢖꢁꢛꢕꢅ1ꢐ,
-ꢁꢕꢕꢅ1ꢐ,
-ꢁꢕꢕꢅ1ꢐ,
ꢕꢁ?ꢕ
9
ꢕꢁꢖꢕ
ꢕꢁ<ꢕ
3ꢋꢋ&ꢓꢉꢃꢄ&
3ꢋꢋ&ꢅꢗꢄꢑꢇꢈ
9ꢀ
ꢀ
ꢕꢁꢛꢘꢅꢝ.3
M
ꢕꢟ
<ꢟ
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9ꢈꢆ#ꢅ>ꢃ#&ꢍ
ꢌ
)
ꢕꢁꢕ<
ꢕꢁꢎꢎ
M
M
ꢕꢁꢎ-
ꢕꢁꢖꢕ
ꢛꢗꢊꢃꢉꢜ
ꢀꢁ ꢂꢃꢄꢅꢀꢅ ꢃ!"ꢆꢇꢅꢃꢄ#ꢈ$ꢅ%ꢈꢆ&"ꢉꢈꢅ'ꢆꢊꢅ ꢆꢉꢊ(ꢅ)"&ꢅ'"!&ꢅ)ꢈꢅꢇꢋꢌꢆ&ꢈ#ꢅ*ꢃ&ꢍꢃꢄꢅ&ꢍꢈꢅꢍꢆ&ꢌꢍꢈ#ꢅꢆꢉꢈꢆꢁ
ꢎꢁ ꢒꢃ'ꢈꢄ!ꢃꢋꢄ!ꢅꢒꢅꢆꢄ#ꢅ.ꢀꢅ#ꢋꢅꢄꢋ&ꢅꢃꢄꢌꢇ"#ꢈꢅ'ꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢓꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢁꢅꢔꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢓꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢅ!ꢍꢆꢇꢇꢅꢄꢋ&ꢅꢈ$ꢌꢈꢈ#ꢅꢕꢁꢀꢘꢅ''ꢅꢓꢈꢉꢅ!ꢃ#ꢈꢁ
-ꢁ ꢒꢃ'ꢈꢄ!ꢃꢋꢄꢃꢄꢑꢅꢆꢄ#ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢃꢄꢑꢅꢓꢈꢉꢅꢗꢐꢔ.ꢅ0ꢀꢖꢁꢘꢔꢁ
1ꢐ,2 1ꢆ!ꢃꢌꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄꢁꢅꢙꢍꢈꢋꢉꢈ&ꢃꢌꢆꢇꢇꢊꢅꢈ$ꢆꢌ&ꢅ ꢆꢇ"ꢈꢅ!ꢍꢋ*ꢄꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ!ꢁ
ꢝ.32 ꢝꢈ%ꢈꢉꢈꢄꢌꢈꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄ(ꢅ"!"ꢆꢇꢇꢊꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ(ꢅ%ꢋꢉꢅꢃꢄ%ꢋꢉ'ꢆ&ꢃꢋꢄꢅꢓ"ꢉꢓꢋ!ꢈ!ꢅꢋꢄꢇꢊꢁ
ꢔꢃꢌꢉꢋꢌꢍꢃꢓ ꢙꢈꢌꢍꢄꢋꢇꢋꢑꢊ ꢒꢉꢆ*ꢃꢄꢑ ,ꢕꢖꢞꢀꢀꢀ1
© 2008 Microchip Technology Inc.
DS22079A-page 21
34VL02
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢆ.ꢈꢄꢊ$ꢆꢛꢗꢆꢂꢃꢄꢅꢆꢇꢄꢌ*ꢄ-ꢃꢆꢑ,ꢛꢒꢆMꢆ/0ꢓ0ꢔ%12ꢆꢕꢕꢆꢖꢗꢅꢘꢆꢙ(ꢍ.ꢛꢚ
ꢛꢗꢊꢃꢜ 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢓꢆꢌ4ꢆꢑꢈꢅ#ꢉꢆ*ꢃꢄꢑ!(ꢅꢓꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢔꢃꢌꢉꢋꢌꢍꢃꢓꢅꢂꢆꢌ4ꢆꢑꢃꢄꢑꢅꢐꢓꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ
ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ
DS22079A-page 22
© 2008 Microchip Technology Inc.
34VL02
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢆ.ꢈꢄꢊ$ꢆꢛꢗꢆꢂꢃꢄꢅꢆꢇꢄꢌ*ꢄ-ꢃꢆꢑ,ꢛꢒꢆMꢆ/0ꢓ0ꢔ%12ꢆꢕꢕꢆꢖꢗꢅꢘꢆꢙ(ꢍ.ꢛꢚ
ꢛꢗꢊꢃꢜ 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢓꢆꢌ4ꢆꢑꢈꢅ#ꢉꢆ*ꢃꢄꢑ!(ꢅꢓꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢔꢃꢌꢉꢋꢌꢍꢃꢓꢅꢂꢆꢌ4ꢆꢑꢃꢄꢑꢅꢐꢓꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ
ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ
© 2008 Microchip Technology Inc.
DS22079A-page 23
34VL02
3ꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ ꢕꢄꢈꢈꢆ!ꢎꢊꢈꢋꢐꢃꢆ("ꢄꢐꢉꢋꢉꢊꢗ"ꢆꢑ!(ꢒꢆꢙ !(ꢁ/ꢓꢚ
ꢛꢗꢊꢃꢜ 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢓꢆꢌ4ꢆꢑꢈꢅ#ꢉꢆ*ꢃꢄꢑ!(ꢅꢓꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢔꢃꢌꢉꢋꢌꢍꢃꢓꢅꢂꢆꢌ4ꢆꢑꢃꢄꢑꢅꢐꢓꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ
ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ
b
4
N
E
E1
PIN 1 ID BY
LASER MARK
1
2
3
e
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D
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A
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L
A1
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6ꢄꢃ&!
ꢔꢚ99ꢚꢔ.ꢙ.ꢝꢐ
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ꢔꢗ;
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ꢂꢃ&ꢌꢍ
7
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: ꢈꢉꢆꢇꢇꢅ8ꢈꢃꢑꢍ&
ꢔꢋꢇ#ꢈ#ꢅꢂꢆꢌ4ꢆꢑꢈꢅꢙꢍꢃꢌ4ꢄꢈ!!
ꢐ&ꢆꢄ#ꢋ%%
: ꢈꢉꢆꢇꢇꢅ>ꢃ#&ꢍ
ꢔꢋꢇ#ꢈ#ꢅꢂꢆꢌ4ꢆꢑꢈꢅ>ꢃ#&ꢍ
: ꢈꢉꢆꢇꢇꢅ9ꢈꢄꢑ&ꢍ
3ꢋꢋ&ꢅ9ꢈꢄꢑ&ꢍ
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9ꢈꢆ#ꢅꢙꢍꢃꢌ4ꢄꢈ!!
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ꢎꢁꢜꢕ
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DS22079A-page 24
© 2008 Microchip Technology Inc.
34VL02
APPENDIX A: REVISION HISTORY
Revision A (3/2008)
Original release of this document.
© 2008 Microchip Technology Inc.
DS22079A-page 25
34VL02
NOTES:
DS22079A-page 26
© 2008 Microchip Technology Inc.
34VL02
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
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Users of Microchip products can receive assistance
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Customers
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support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
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• General Technical Support – Frequently Asked
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© 2008 Microchip Technology Inc.
DS22079A-page 27
34VL02
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
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34VL02
DS22079A
Literature Number:
Device:
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS22079A-page 28
© 2008 Microchip Technology Inc.
34VL02
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
/XX
Examples:
Temperature Package
Range
a) 34VL02T/OT: Tape and Reel, 1.5V,
SOT-23 package
b) 34VL02T/ST: Tape and Reel, 1.5V,
TSSOP package
2
Device:
34VL02:
34VL02T:
=
=
1.5V, 2 Kbit I C Serial EEPROM
2
1.5V, 2 Kbit I C Serial EEPROM
c)
34VL02T/MNY: Tape and Reel, 1.5V,
TDFN package
(Tape and Reel)
Temperature Blank
=
-20°C to +85°C
Range:
Package:
OT
P
SN
ST
MS
=
=
=
=
=
Plastic Small Outline (SOT-23), 6-lead
Plastic DIP (300 mil body), 8-lead
Plastic SOIC (3.90 mm body), 8-lead
Plastic TSSOP (4.4 mm), 8-lead
Plastic Micro Small Outline (MSOP), 8-lead
Plastic Dual Flat (TDFN), no lead package,
2x3 mm body, 8-lead
MNY* =
Note 1: “Y” indicates a Nickel Palladium Gold (NiPdAu) finish.
ꢀ 2008 Microchip Technology Inc.
DS22079A-page29
34VL02
NOTES:
DS22079A-page 30
ꢀ 2008 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
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hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PRO MATE, rfPIC and SmartShunt are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
FilterLab, Linear Active Thermistor, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, In-Circuit Serial
Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,
32
PICDEM.net, PICtail, PIC logo, PowerCal, PowerInfo,
PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2008, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2008 Microchip Technology Inc.
DS22079A-page 31
WORLDWIDE SALES AND SERVICE
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ASIA/PACIFIC
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Technical Support:
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Fax: 86-756-3210049
01/02/08
DS22079A-page 32
© 2008 Microchip Technology Inc.
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