25LC256T-IST [MICROCHIP]
256K SPI Bus Serial EEPROM; 256K SPI总线串行EEPROM型号: | 25LC256T-IST |
厂家: | MICROCHIP |
描述: | 256K SPI Bus Serial EEPROM |
文件: | 总26页 (文件大小:353K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
25AA256/25LC256
256K SPI™ Bus Serial EEPROM
Device Selection Table
Part Number
VCC Range
Page Size
Temp. Ranges
Packages
25LC256
25AA256
2.5-5.5V
1.8-5.5V
64 Byte
64 Byte
I, E
I
P, SN, ST, MF
P, SN, ST, MF
Features
Description
• Max. clock 10 MHz
The Microchip Technology Inc. 25AA256/25LC256
(25XX256*) are 256k-bit Serial Electrically Erasable
PROMs. The memory is accessed via a simple Serial
Peripheral Interface™ (SPI™) compatible serial bus.
The bus signals required are a clock input (SCK) plus
separate data in (SI) and data out (SO) lines. Access to
the device is controlled through a Chip Select (CS)
input.
• Low-power CMOS technology
- Max. Write Current: 5 mA at 5.5V, 10 MHz
- Read Current: 5 mA at 5.5V, 10 MHz
- Standby Current: 1 µA at 5.5V
• 32,768 x 8-bit organization
• 64 byte page
• Self-timed ERASE and WRITE cycles (5 ms
max.)
Communication to the device can be paused via the
hold pin (HOLD). While the device is paused,
transitions on its inputs will be ignored, with the
exception of Chip Select, allowing the host to service
higher priority interrupts.
• Block write protection
- Protect none, 1/4, 1/2 or all of array
• Built-in write protection
The 25XX256 is available in standard packages
including 8-lead PDIP and SOIC, and advanced
packaging including 8-lead DFN and 8-lead TSSOP.
Pb-free (Pure Sn) finish is also available.
- Power-on/off data protection circuitry
- Write enable latch
- Write-protect pin
• Sequential read
• High reliability
Package Types (not to scale)
- Endurance: 1,000,000 erase/write cycles
- Data retention: > 200 years
- ESD protection: > 4000V
• Temperature ranges supported;
TSSOP
(ST)
PDIP/SOIC
(P, SN)
CS
SO
WP
VCC
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
CS
SO
WP
V
CC
- Industrial (I):
- Automotive (E):
-40°C to +85°C
-40°C to +125°C
HOLD
SCK
SI
HOLD
SCK
SI
VSS
• Standard and Pb-free packages available
VSS
Pin Function Table
DFN
(MF)
Name
Function
Chip Select Input
1
2
3
4
CS
8
7
6
5
VCC
HOLD
SCK
SI
CS
SO
SO
WP
VSS
Serial Data Output
Write-Protect
Ground
WP
VSS
SI
Serial Data Input
Serial Clock Input
Hold Input
SPI is a registered trademark of Motorola Corporation.
SCK
HOLD
VCC
Supply Voltage
* 25XX256 is used in this document as a generic part number for the 25AA256, 25LC256 devices.
2003 Microchip Technology Inc.
Preliminary
DS21822C-page 1
25AA256/25LC256
1.0
ELECTRICAL CHARACTERISTICS
(†)
Absolute Maximum Ratings
VCC.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V
Storage temperature .................................................................................................................................-65°C to 150°C
Ambient temperature under bias...............................................................................................................-40°C to 125°C
ESD protection on all pins..........................................................................................................................................4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an
extended period of time may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
Industrial (I):
Automotive (E): TA = -40°C to +125°C
TA = -40°C to +85°C
VCC = 1.8V to 5.5V
VCC = 2.5V to 5.5V
DC CHARACTERISTICS
Param.
No.
Sym.
Characteristic
Min.
Max.
Units
Test Conditions
D001
VIH1
High-level input
voltage
.7 VCC
VCC+1
V
D002
D003
D004
D005
D006
VIL1
VIL2
VOL
VOL
VOH
Low-level input
voltage
-0.3
-0.3
0.3VCC
0.2VCC
0.4
V
V
V
V
V
VCC ≥ 2.7V
VCC < 2.7V
Low-level output
voltage
—
IOL = 2.1 mA
—
0.2
IOL = 1.0 mA, VCC < 2.5V
IOH = -400 µA
High-level output
voltage
VCC -0.5
—
D007
D008
ILI
Input leakage current
—
—
±1
±1
µA
µA
CS = VCC, VIN = VSS TO VCC
CS = VCC, VOUT = VSS TO VCC
ILO
Output leakage
current
D009
D010
CINT
Internal Capacitance
(all inputs and
outputs)
—
7
pF
TA = 25°C, CLK = 1.0 MHz,
VCC = 5.0V (Note)
ICC Read
—
—
5
mA
mA
VCC = 5.5V; FCLK = 10.0 MHz;
SO = Open
VCC = 2.5V; FCLK = 5.0 MHz;
SO = Open
Operating Current
Standby Current
2.5
D011
D012
ICC Write
ICCS
—
—
5
3
mA
mA
VCC = 5.5V
VCC = 2.5V
—
—
5
µA
CS = VCC = 5.5V, Inputs tied to VCC or
VSS, 125°C
1
µA
CS = VCC = 5.5V, Inputs tied to VCC or
VSS, 85°C
Note:
This parameter is periodically sampled and not 100% tested.
DS21822C-page 2
Preliminary
2003 Microchip Technology Inc.
25AA256/25LC256
TABLE 1-2:
AC CHARACTERISTICS
Industrial (I):
Automotive (E): TA = -40°C to +125°C
TA = -40°C to +85°C
VCC = 1.8V to 5.5V
VCC = 2.5V to 5.5V
AC CHARACTERISTICS
Param.
Sym.
Characteristic
Min.
Max.
Units
Test Conditions
No.
1
2
3
FCLK Clock Frequency
—
—
—
10
5
3
MHz 4.5V ≤ Vcc ≤ 5.5V
MHz 2.5V ≤ Vcc < 4.5V
MHz 1.8V ≤ Vcc < 2.5V
TCSS CS Setup Time
TCSH CS Hold Time
TCSD CS Disable Time
50
100
150
—
—
—
ns
ns
ns
4.5V ≤ Vcc ≤ 5.5V
2.5V ≤ Vcc < 4.5V
1.8V ≤ Vcc < 2.5V
100
200
250
—
—
—
ns
ns
ns
4.5V ≤ Vcc ≤ 5.5V
2.5V ≤ Vcc < 4.5V
1.8V ≤ Vcc < 2.5V
4
5
50
—
ns
—
Tsu
Data Setup Time
10
20
30
—
—
—
ns
ns
ns
4.5V ≤ Vcc ≤ 5.5V
2.5V ≤ Vcc < 4.5V
1.8V ≤ Vcc < 2.5V
6
THD
Data Hold Time
20
40
50
—
—
—
ns
ns
ns
4.5V ≤ Vcc ≤ 5.5V
2.5V ≤ Vcc < 4.5V
1.8V ≤ Vcc < 2.5V
7
8
9
TR
TF
CLK Rise Time
CLK Fall Time
Clock High Time
—
—
2
2
µs
µs
(Note 1)
(Note 1)
THI
50
100
150
—
—
—
ns
ns
ns
4.5V ≤ Vcc ≤ 5.5V
2.5V ≤ Vcc < 4.5V
1.8V ≤ Vcc < 2.5V
10
TLO
Clock Low Time
50
100
150
—
—
—
ns
ns
ns
4.5V ≤ Vcc ≤ 5.5V
2.5V ≤ Vcc < 4.5V
1.8V ≤ Vcc < 2.5V
11
12
13
TCLD Clock Delay Time
50
50
—
—
ns
ns
—
—
TCLE
TV
Clock Enable Time
Output Valid from Clock
Low
—
—
—
50
100
160
ns
ns
ns
4.5V ≤ Vcc ≤ 5.5V
2.5V ≤ Vcc < 4.5V
1.8V ≤ Vcc < 2.5V
14
15
THO
TDIS
Output Hold Time
0
—
ns
(Note 1)
Output Disable Time
—
—
—
40
80
160
ns
ns
ns
4.5V ≤ Vcc ≤ 5.5V(Note 1)
2.5V ≤ Vcc ≤ 4.5V(Note 1)
1.8V ≤ Vcc ≤ 2.5V(Note 1)
16
THS
HOLD Setup Time
20
40
80
—
—
—
ns
ns
ns
4.5V ≤ Vcc ≤ 5.5V
2.5V ≤ Vcc < 4.5V
1.8V ≤ Vcc < 2.5V
Note 1: This parameter is periodically sampled and not 100% tested.
2: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle is
complete.
3: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from our web site:
www.microchip.com.
2003 Microchip Technology Inc.
Preliminary
DS21822C-page 3
25AA256/25LC256
TABLE 1-2:
AC CHARACTERISTICS (CONTINUED)
Industrial (I):
Automotive (E): TA = -40°C to +125°C
TA = -40°C to +85°C
VCC = 1.8V to 5.5V
VCC = 2.5V to 5.5V
AC CHARACTERISTICS
Param.
Sym.
Characteristic
Min.
Max.
Units
Test Conditions
No.
17
THH
HOLD Hold Time
20
40
80
—
—
—
ns
ns
ns
4.5V ≤ Vcc ≤ 5.5V
2.5V ≤ Vcc < 4.5V
1.8V ≤ Vcc < 2.5V
18
19
THZ
THV
HOLD Low to Output
High-Z
30
60
160
—
—
—
ns
ns
ns
4.5V ≤ Vcc ≤ 5.5V(Note 1)
2.5V ≤ Vcc < 4.5V(Note 1)
1.8V ≤ Vcc < 2.5V(Note 1)
HOLD High to Output
Valid
30
60
160
—
—
—
ns
ns
ns
4.5V ≤ Vcc ≤ 5.5V
2.5V ≤ Vcc < 4.5V
1.8V ≤ Vcc < 2.5V
20
21
TWC
—
Internal Write Cycle Time
Endurance
—
5
ms
(NOTE 2)
1M
—
E/W (NOTE 3)
Cycles
Note 1: This parameter is periodically sampled and not 100% tested.
2: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle is
complete.
3: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from our web site:
www.microchip.com.
TABLE 1-3:
AC Waveform:
VLO = 0.2V
AC TEST CONDITIONS
—
VHI = VCC - 0.2V
(Note 1)
(Note 2)
—
VHI = 4.0V
CL = 100 pF
Timing Measurement Reference Level
Input
0.5 VCC
0.5 VCC
Output
Note 1: For VCC ≤ 4.0V
2: For Vcc > 4.0V
DS21822C-page 4
Preliminary
2003 Microchip Technology Inc.
25AA256/25LC256
FIGURE 1-1: HOLD TIMING
CS
17
17
16
16
SCK
18
19
high-impedance
n
SO
n+2
n+2
n+1
n
n-1
5
don’t care
n
n+1
n
n-1
SI
HOLD
FIGURE 1-2: SERIAL INPUT TIMING
4
CS
12
11
2
7
3
8
Mode 1,1
Mode 0,0
SCK
SI
5
6
MSB in
LSB in
high-impedance
SO
FIGURE 1-3: SERIAL OUTPUT TIMING
CS
3
9
10
Mode 1,1
Mode 0,0
SCK
13
15
ISB out
14
MSB out
SO
SI
don’t care
2003 Microchip Technology Inc.
Preliminary
DS21822C-page 5
25AA256/25LC256
2.0
2.1
FUNCTIONAL DESCRIPTION
Principles of Operation
2.3
Write Sequence
The 25XX256 is a 32768 byte Serial EEPROM
designed to interface directly with the Serial Peripheral
Interface (SPI) port of many of today’s popular
Prior to any attempt to write data to the 25XX256, the
write enable latch must be set by issuing the WREN
instruction (Figure 2-4). This is done by setting CS low
and then clocking out the proper instruction into the
25XX256. After all eight bits of the instruction are
transmitted, the CS must be brought high to set the
write enable latch. If the write operation is initiated
immediately after the WREN instruction without CS
being brought high, the data will not be written to the
array because the write enable latch will not have been
properly set.
microcontroller
families,
including
Microchip’s
PICmicro® microcontrollers. It may also interface with
microcontrollers that do not have a built-in SPI port by
using discrete I/O lines programmed properly in
firmware to match the SPI protocol.
The 25XX256 contains an 8-bit instruction register. The
device is accessed via the SI pin, with data being
clocked in on the rising edge of SCK. The CS pin must
be low and the HOLD pin must be high for the entire
operation.
Once the write enable latch is set, the user may
proceed by setting the CS low, issuing a WRITE
instruction, followed by the 16-bit address, with the first
MSB of the address being a don’t care bit, and then the
data to be written. Up to 64 bytes of data can be sent to
the device before a write cycle is necessary. The only
restriction is that all of the bytes must reside in the
same page.
Table 2-1 contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses, and data are transferred MSB first, LSB
last.
Data (SI) is sampled on the first rising edge of SCK
after CS goes low. If the clock line is shared with other
peripheral devices on the SPI bus, the user can assert
the HOLD input and place the 25XX256 in ‘HOLD’
mode. After releasing the HOLD pin, operation will
resume from the point when the HOLD was asserted.
Note:
Page write operations are limited to writing
bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size (or
‘page size’) and, end at addresses that are
integer multiples of page size - 1. If a Page
Write command attempts to write across a
physical page boundary, the result is that
the data wraps around to the beginning of
the current page (overwriting data
previously stored there), instead of being
written to the next page as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
2.2
Read Sequence
The device is selected by pulling CS low. The 8-bit read
instruction is transmitted to the 25XX256 followed by
the 16-bit address, with the first MSB of the address
being a don’t care bit. After the correct read instruction
and address are sent, the data stored in the memory at
the selected address is shifted out on the SO pin. The
data stored in the memory at the next address can be
read sequentially by continuing to provide clock pulses.
The internal address pointer is automatically incre-
mented to the next higher address after each byte of
data is shifted out. When the highest address is
reached (7FFFh), the address counter rolls over to
address 0000h allowing the read cycle to be continued
indefinitely. The read operation is terminated by raising
the CS pin (Figure 2-1).
For the data to be actually written to the array, the CS
must be brought high after the Least Significant bit (D0)
of the nth data byte has been clocked in. If CS is
brought high at any other time, the write operation will
not be completed. Refer to Figure 2-2 and Figure 2-3
for more detailed illustrations on the byte write
sequence and the page write sequence respectively.
While the write is in progress, the Status register may
be read to check the status of the WPEN, WIP, WEL,
BP1 and BP0 bits (Figure 2-6). A read attempt of a
memory array location will not be possible during a
write cycle. When the write cycle is completed, the
write enable latch is reset.
DS21822C-page 6
Preliminary
2003 Microchip Technology Inc.
25AA256/25LC256
BLOCK DIAGRAM
Status
Register
HV Generator
EEPROM
Array
Memory
Control
Logic
X
I/O Control
Logic
Dec
Page Latches
Y Decoder
SI
SO
CS
SCK
Sense Amp.
R/W Control
HOLD
WP
VCC
VSS
TABLE 2-1:
INSTRUCTION SET
Instruction Name
READ
Instruction Format
Description
Read data from memory array beginning at selected address
Write data to memory array beginning at selected address
Reset the write enable latch (disable write operations)
Set the write enable latch (enable write operations)
Read Status register
0000 0011
0000 0010
0000 0100
0000 0110
0000 0101
0000 0001
WRITE
WRDI
WREN
RDSR
WRSR
Write Status register
FIGURE 2-1: READ SEQUENCE
CS
0
0
1
0
2
3
4
5
0
6
7
8
9 10 11
21 22 23 24 25 26 27 28 29 30 31
SCK
SI
instruction
16-bit address
1 15 14 13 12
0
0
0
1
2
1
0
data out
high-impedance
7
6
5
4
3
2
1
0
SO
2003 Microchip Technology Inc.
Preliminary
DS21822C-page 7
25AA256/25LC256
FIGURE 2-2: BYTE WRITE SEQUENCE
CS
Twc
0
0
1
0
2
3
4
5
0
6
1
7
8
9 10 11
21 22 23 24 25 26 27 28 29 30 31
data byte
SCK
SI
instruction
16-bit address
15 14 13 12
0
0
0
0
2
1
0
7
6
5
4
3
2
1
0
high-impedance
SO
FIGURE 2-3: PAGE WRITE SEQUENCE
CS
0
0
1
0
2
3
4
5
0
6
7
8
9
10 11
21 22 23 24 25 26 27 28 29 30 31
data byte 1
SCK
SI
instruction
16-bit address
0
0
0
1
0 15 14 13 12
2
1
0
7
6
5
4
3
2
1
0
CS
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCK
SI
data byte 2
data byte 3
data byte n (64 max)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
DS21822C-page 8
Preliminary
2003 Microchip Technology Inc.
25AA256/25LC256
The following is a list of conditions under which the
write enable latch will be reset:
2.4
Write Enable (WREN) and Write
Disable (WRDI)
• Power-up
The 25XX256 contains a write enable latch.
See
• WRDIinstruction successfully executed
• WRSRinstruction successfully executed
• WRITEinstruction successfully executed
Table 2-4 for the Write-Protect Functionality Matrix.
This latch must be set before any write operation will be
completed internally. The WRENinstruction will set the
latch, and the WRDIwill reset the latch.
FIGURE 2-4: WRITE ENABLE SEQUENCE (WREN)
CS
0
1
2
3
4
5
6
7
SCK
SI
0
0
0
0
0
1
1
0
high-impedance
SO
FIGURE 2-5: WRITE DISABLE SEQUENCE (WRDI)
CS
0
1
2
3
4
5
6
7
SCK
0
0
0
0
0
0
1
0
SI
high-impedance
SO
2003 Microchip Technology Inc.
Preliminary
DS21822C-page 9
25AA256/25LC256
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch and is read-only. When set to
a ‘1’, the latch allows writes to the array, when set to a
‘0’, the latch prohibits writes to the array. The state of
this bit can always be updated via the WRENor WRDI
commands regardless of the state of write protection
on the Status register. These commands are shown in
Figure 2-4 and Figure 2-5.
2.5
Read Status Register Instruction
(RDSR)
The Read Status Register instruction (RDSR) provides
access to the Status register. The Status register may
be read at any time, even during a write cycle. The
Status register is formatted as follows:
TABLE 2-2:
STATUS REGISTER
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the user issuing the WRSRinstruction. These
bits are nonvolatile, and are shown in Table 2-3.
7
6
–
X
5
–
X
4
–
X
3
2
1
0
W/R
W/R W/R
R
R
WPEN
BP1 BP0 WEL WIP
See Figure 2-6 for the RDSRtiming sequence.
W/R = writable/readable. R = read-only.
The Write-In-Process (WIP) bit indicates whether the
25XX256 is busy with a write operation. When set to a
‘1’, a write is in progress, when set to a ‘0’, no write is
in progress. This bit is read-only.
FIGURE 2-6: READ STATUS REGISTER TIMING SEQUENCE (RDSR)
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
instruction
0
0
0
0
0
1
0
1
SI
data from Status register
high-impedance
7
6
5
4
3
2
1
0
SO
DS21822C-page 10
Preliminary
2003 Microchip Technology Inc.
25AA256/25LC256
See Figure 2-7 for the WRSRtiming sequence.
2.6
Write Status Register Instruction
(WRSR)
TABLE 2-3:
BP1
ARRAY PROTECTION
The Write Status Register instruction (WRSR) allows the
user to write to the nonvolatile bits in the Status register
as shown in Table 2-2. The user is able to select one of
four levels of protection for the array by writing to the
appropriate bits in the Status register. The array is
divided up into four segments. The user has the ability
to write-protect none, one, two, or all four of the
segments of the array. The partitioning is controlled as
shown in Table 2-3.
Array Addresses
Write-Protected
BP0
none
0
0
0
1
upper 1/4
(6000h - 7FFFh)
upper 1/2
(4000h - 7FFFh)
1
1
0
1
The Write-Protect Enable (WPEN) bit is a nonvolatile
bit that is available as an enable bit for the WP pin. The
Write-Protect (WP) pin and the Write-Protect Enable
(WPEN) bit in the Status register control the
programmable hardware write-protect feature. Hard-
ware write protection is enabled when WP pin is low
and the WPEN bit is high. Hardware write protection is
disabled when either the WP pin is high or the WPEN
bit is low. When the chip is hardware write-protected,
only writes to nonvolatile bits in the Status register are
disabled. See Table 2-4 for a matrix of functionality on
the WPEN bit.
all
(0000h - 7FFFh)
FIGURE 2-7: WRITE STATUS REGISTER TIMING SEQUENCE (WRSR)
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1
15
0
SCK
instruction
0
data to Status register
7
6
5
4
3
2
0
0
0
0
0
0
1
SI
high-impedance
SO
Note:
An internal write cycle (TWC) is initiated on the rising edge of CS after a valid write Status Register sequence.
2003 Microchip Technology Inc.
Preliminary
DS21822C-page 11
25AA256/25LC256
2.7
Data Protection
2.8
Power-On State
The following protection has been implemented to
prevent inadvertent writes to the array:
The 25XX256 powers on in the following state:
• The device is in low-power Standby mode
(CS= 1)
• The write enable latch is reset
• SO is in high-impedance state
• A high-to-low-level transition on CS is required to
enter active state
• The write enable latch is reset on power-up
• A write enable instruction must be issued to set
the write enable latch
• After a byte write, page write or Status register
write, the write enable latch is reset
• CS must be set high after the proper number of
clock cycles to start an internal write cycle
• Access to the array during an internal write cycle
is ignored and programming is continued
TABLE 2-4:
WRITE-PROTECT FUNCTIONALITY MATRIX
WEL
(SR bit 1)
WPEN
(SR bit 7)
WP
(pin 3)
Protected Blocks
Unprotected Blocks
Status Register
0
x
0
1
1
x
Protected
Protected
Protected
Protected
Protected
Writable
Writable
Writable
Protected
Writable
Protected
Writable
1
x
1
0 (low)
1 (high)
1
x = don’t care
DS21822C-page 12
Preliminary
2003 Microchip Technology Inc.
25AA256/25LC256
The WP pin function is blocked when the WPEN bit in
the Status register is low. This allows the user to install
the 25XX256 in a system with WP pin grounded and
still be able to write to the Status register. The WP pin
functions will be enabled when the WPEN bit is set
high.
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
Name
PIN FUNCTION TABLE
Pin Number
Function
3.4
Serial Input (SI)
CS
SO
1
2
3
4
5
6
7
8
Chip Select Input
Serial Data Output
Write-Protect Pin
Ground
The SI pin is used to transfer data into the device. It
receives instructions, addresses and data. Data is
latched on the rising edge of the serial clock.
WP
VSS
SI
3.5
Serial Clock (SCK)
Serial Data Input
Serial Clock Input
Hold Input
The SCK is used to synchronize the communication
between a master and the 25XX256. Instructions,
addresses or data present on the SI pin are latched on
the rising edge of the clock input, while data on the SO
pin is updated after the falling edge of the clock input.
SCK
HOLD
VCC
Supply Voltage
3.6
Hold (HOLD)
3.1
Chip Select (CS)
The HOLD pin is used to suspend transmission to the
25XX256 while in the middle of a serial sequence with-
out having to retransmit the entire sequence again. It
must be held high any time this function is not being
used. Once the device is selected and a serial
sequence is underway, the HOLD pin may be pulled
low to pause further serial communication without
resetting the serial sequence. The HOLD pin must be
brought low while SCK is low, otherwise the HOLD
function will not be invoked until the next SCK high-to-
low transition. The 25XX256 must remain selected
during this sequence. The SI, SCK and SO pins are in
a high-impedance state during the time the device is
paused and transitions on these pins will be ignored. To
resume serial communication, HOLD must be brought
high while the SCK pin is low, otherwise serial
communication will not resume. Lowering the HOLD
line at any time will tri-state the SO line.
A low level on this pin selects the device. A high level
deselects the device and forces it into Standby mode.
However, a programming cycle which is already
initiated or in progress will be completed, regardless of
the CS input signal. If CS is brought high during a
program cycle, the device will go into Standby mode as
soon as the programming cycle is complete. When the
device is deselected, SO goes to the high-impedance
state, allowing multiple parts to share the same SPI
bus. A low-to-high transition on CS after a valid write
sequence initiates an internal write cycle. After power-
up, a low level on CS is required prior to any sequence
being initiated.
3.2
Serial Output (SO)
The SO pin is used to transfer data out of the 25XX256.
During a read cycle, data is shifted out on this pin after
the falling edge of the serial clock.
3.3
Write-Protect (WP)
This pin is used in conjunction with the WPEN bit in the
Status register to prohibit writes to the nonvolatile bits
in the Status register. When WP is low and WPEN is
high, writing to the nonvolatile bits in the Status register
is disabled. All other operations function normally.
When WP is high, all functions, including writes to the
nonvolatile bits in the Status register, operate normally.
If the WPEN bit is set, WP low during a Status register
write sequence will disable writing to the Status
register. If an internal write cycle has already begun,
WP going low will have no effect on the write.
2003 Microchip Technology Inc.
Preliminary
DS21822C-page 13
25AA256/25LC256
4.0
4.1
PACKAGING INFORMATION
Package Marking Information
8-Lead DFN
Example:
XXXXXXX
T/XXXXX
YYWW
25LC256
I/MF
0328
1L7
NNN
Example:
8-Lead PDIP
25AA256
I/P 1L7
XXXXXXXX
T/XXXNNN
0328
YYWW
Example:
8-Lead SOIC
25LC256
I/SN 0328
XXXXXXXX
T/XXYYWW
1L7
NNN
Example:
8-Lead TSSOP
TSSOP 1st Line Marking Codes
5LE
I328
1L7
XXXX
TYWW
NNN
Pb-free
Device
std mark
mark
25AA256
25LC256
5AE
5LE
NAE
NLE
Legend: XX...X Part number
T
Temperature (I, E)
Blank Commercial
YY
Year code (last 2 digits of calendar year) except TSSOP
which uses only the last 1 digit
WW
NNN
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Note: Custom marking available.
DS21822C-page 14
Preliminary
2003 Microchip Technology Inc.
25AA256/25LC256
8-Lead Plastic Dual Flat No Lead Package (MF) 6x5 mm Body (DFN-S)
E
p
B
E1
n
L
R
D1
D
D2
PIN 1
EXPOSED
METAL
PADS
ID
1
2
E2
BOTTOM VIEW
TOP VIEW
α
A2
A3
A
A1
Units
Dimension Limits
INCHES
MILLIMETERS*
MIN
NOM
MAX
MIN
NOM
8
MAX
n
p
Number of Pins
Pitch
8
.050 BSC
1.27 BSC
0.85
Overall Height
A
A2
A1
A3
E
.033
.039
1.00
Molded Package Thickness
Standoff
.026
.0004
.031
.002
0.65
0.80
0.05
.000
.152
0.00
0.01
0.20 REF.
Base Thickness
Overall Length
.008 REF.
.194 BSC
.184 BSC
.158
4.92 BSC
4.67 BSC
Molded Package Length
Exposed Pad Length
Overall Width
E1
E2
D
.163
3.85
4.00
4.15
.236 BSC
.226 BSC
.091
5.99 BSC
5.74 BSC
Molded Package Width
Exposed Pad Width
Lead Width
D1
D2
B
.085
.014
.020
.097
.019
.030
2.16
0.35
0.50
2.31
2.46
0.47
0.75
.016
0.40
0.60
.356
Lead Length
L
.024
Tie Bar Width
R
.014
α
Mold Draft Angle Top
12
12
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC equivalent: pending
Drawing No. C04-113
2003 Microchip Technology Inc.
Preliminary
DS21822C-page 15
25AA256/25LC256
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
A1
β
B1
B
p
eB
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
8
MAX
n
p
Number of Pins
Pitch
8
.100
.155
.130
2.54
Top to Seating Plane
A
.140
.170
3.56
2.92
3.94
3.30
4.32
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.115
.015
.300
.240
.360
.125
.008
.045
.014
.310
5
.145
3.68
0.38
7.62
6.10
9.14
3.18
0.20
1.14
0.36
7.87
5
.313
.250
.373
.130
.012
.058
.018
.370
10
.325
.260
.385
.135
.015
.070
.022
.430
15
7.94
6.35
9.46
3.30
0.29
1.46
0.46
9.40
10
8.26
6.60
9.78
3.43
0.38
1.78
0.56
10.92
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
DS21822C-page 16
Preliminary
2003 Microchip Technology Inc.
25AA256/25LC256
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
E
E1
p
D
2
B
n
1
h
α
45°
c
A2
A
φ
β
L
A1
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
MAX
n
p
Number of Pins
Pitch
8
8
.050
.061
.056
.007
.237
.154
.193
.015
.025
4
1.27
1.55
1.42
0.18
6.02
3.91
4.90
0.38
0.62
4
Overall Height
A
.053
.069
1.35
1.75
Molded Package Thickness
Standoff
A2
A1
E
.052
.004
.228
.146
.189
.010
.019
0
.061
.010
.244
.157
.197
.020
.030
8
1.32
0.10
5.79
3.71
4.80
0.25
0.48
0
1.55
0.25
6.20
3.99
5.00
0.51
0.76
8
§
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
φ
Foot Angle
c
Lead Thickness
Lead Width
.008
.013
0
.009
.017
12
.010
.020
15
0.20
0.33
0
0.23
0.42
12
0.25
0.51
15
B
α
Mold Draft Angle Top
Mold Draft Angle Bottom
β
0
12
15
0
12
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
2003 Microchip Technology Inc.
Preliminary
DS21822C-page 17
25AA256/25LC256
8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
E
E1
p
D
2
1
n
B
α
A
c
A1
A2
φ
β
L
Units
INCHES
NOM
MILLIMETERS*
Dimension Limits
MIN
MAX
MIN
NOM
8
MAX
n
p
Number of Pins
Pitch
8
.026
0.65
Overall Height
A
.043
1.10
0.95
0.15
6.50
4.50
3.10
0.70
8
Molded Package Thickness
Standoff
A2
A1
E
.033
.035
.004
.251
.173
.118
.024
4
.037
.006
.256
.177
.122
.028
8
0.85
0.05
0.90
0.10
6.38
4.40
3.00
0.60
4
§
.002
.246
.169
.114
.020
0
Overall Width
6.25
4.30
2.90
0.50
0
Molded Package Width
Molded Package Length
Foot Length
E1
D
L
φ
Foot Angle
c
Lead Thickness
.004
.007
0
.006
.010
5
.008
.012
10
0.09
0.19
0
0.15
0.25
5
0.20
0.30
10
Lead Width
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
0
5
10
0
5
10
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.005” (0.127mm) per side.
JEDEC Equivalent: MO-153
Drawing No. C04-086
DS21822C-page 18
Preliminary
2003 Microchip Technology Inc.
25AA256/25LC256
APPENDIX A: REVISION HISTORY
Revision C
Corrections to Section 1.0, Electrical Characteristics.
2003 Microchip Technology Inc.
Preliminary
DS21822C-page 19
25AA256/25LC256
NOTES:
DS21822C-page 20
Preliminary
2003 Microchip Technology Inc.
25AA256/25LC256
ON-LINE SUPPORT
SYSTEMS INFORMATION AND
UPGRADE HOT LINE
Microchip provides on-line support on the Microchip
World Wide Web site.
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.
Plus, this line provides information on how customers
can receive the most current upgrade kits.The Hot Line
Numbers are:
The web site is used by Microchip as a means to make
files and information easily available to customers. To
view the site, the user must have access to the Internet
and a web browser, such as Netscape® or Microsoft®
Internet Explorer. Files are also available for FTP
download from our FTP site.
1-800-755-2345 for U.S. and most of Canada, and
1-480-792-7302 for the rest of the world.
Connecting to the Microchip Internet
Web Site
042003
The Microchip web site is available at the following
URL:
www.microchip.com
The file transfer site is available by using an FTP
service to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User's Guides, Articles and Sample Programs. A
variety of Microchip specific business information is
also available, including listings of Microchip sales
offices, distributors and factory representatives. Other
data available for consideration is:
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
• Conferences for products, Development Systems,
technical information and more
• Listing of seminars and events
2003 Microchip Technology Inc.
Preliminary
DS21822C-page 21
25AA256/25LC256
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
To:
Technical Publications Manager
Reader Response
Total Pages Sent ________
RE:
From:
Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Y
N
25AA256/25LC256
DS21822C
Literature Number:
Device:
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS21822C-page 22
Preliminary
2003 Microchip Technology Inc.
25AA256/25LC256
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
/XX
X
X
–
Examples:
Tape & Reel
Package
Lead
Finish
Temp Range
a)
b)
c)
d)
25AA256-I/STG = 256k-bit, 1.8V Serial
EEPROM, Industrial temp., TSSOP package,
Pb-free
25AA256T-I/SN = 256k-bit, 1.8V Serial
EEPROM, Industrial temp., Tape & Reel, SOIC
package
Device
25AA256
25LC256
256k-bit, 1.8V, 64-Byte Page, SPI Serial EEPROM
256k-bit, 2.5V, 64-Byte Page, SPI Serial EEPROM
25AA256T-I/ST = 256k-bit, 1.8V Serial
EEPROM, Industrial temp., Tape & Reel,
TSSOP package
Tape & Reel
Blank
T
=
=
Standard packaging (tube)
Tape & Reel
25LC256-I/STG = 256k-bit, 2.5V Serial
EEPROM, Industrial temp., TSSOP package,
Pb-free
Temperature Range
I
E
=
=
-40°C to+85°C
-40°C to+125°C
e)
f)
25LC256-I/P = 256k-bit, 2.5V Serial EEPROM,
Industrial temp., P-DIP package
Package
MF
P
SN
ST
=
=
=
=
Micro Lead Frame (6 x 5 mm body), 8-lead
Plastic DIP (300 mil body), 8-lead
Plastic SOIC (150 mil body), 8-lead
TSSOP, 8-lead
25LC256T-E/ST
=
256k-bit, 2.5V Serial
EEPROM, Extended temp., Tape
TSSOP package
& Reel,
Lead Finish
Blank
G
=
=
Standard 63% / 37% Sn/Pb
Matte Tin (Pure Sn)
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
2003 Microchip Technology Inc.
Preliminary
DS21822C-page 23
25AA256/25LC256
NOTES:
DS21822C-page 24
Preliminary
2003 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical com-
ponents in life support systems is not authorized except with
express written approval by Microchip. No licenses are con-
veyed, implicitly or otherwise, under any intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE and PowerSmart are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER,
SEEVAL and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Application Maestro, dsPICDEM, dsPICDEM.net, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo,
PowerMate, PowerTool, rfLAB, rfPIC, Select Mode,
SmartSensor, SmartShunt, SmartTel and Total Endurance are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2003, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of development
systems is ISO 9001 certified.
2003 Microchip Technology Inc.
Preliminary
DS21822C-page 25
WORLDWIDE SALES AND SERVICE
Korea
AMERICAS
ASIA/PACIFIC
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea 135-882
Tel: 82-2-554-7200 Fax: 82-2-558-5932 or
82-2-558-5934
Corporate Office
Australia
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Suite 22, 41 Rawson Street
Epping 2121, NSW
Australia
Fax: 480-792-7277
Technical Support: 480-792-7627
Web Address: http://www.microchip.com
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
Singapore
200 Middle Road
#07-02 Prime Centre
Singapore, 188980
Tel: 65-6334-8870 Fax: 65-6334-8850
China - Beijing
Unit 915
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No. 6 Chaoyangmen Beidajie
Beijing, 100027, No. China
Tel: 86-10-85282100
Fax: 86-10-85282104
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Tel: 770-640-0034
Fax: 770-640-0307
Taiwan
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Taiwan
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Tel: 45-4420-9895 Fax: 45-4420-9910
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France
2767 S. Albright Road
Kokomo, IN 46902
Tel: 765-864-8360
Fax: 765-864-8387
Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
Batiment A - ler Etage
91300 Massy, France
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Los Angeles
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: 949-263-1888
Fax: 949-263-1338
Germany
Steinheilstrasse 10
D-85737 Ismaning, Germany
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Phoenix
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7966
Fax: 480-792-4338
Room 401, Hongjian Building
No. 2 Fengxiangnan Road, Ronggui Town
Shunde City, Guangdong 528303, China
Tel: 86-765-8395507 Fax: 86-765-8395571
Italy
Via Quasimodo, 12
20025 Legnano (MI)
Milan, Italy
China - Qingdao
Rm. B505A, Fullhope Plaza,
No. 12 Hong Kong Central Rd.
Qingdao 266071, China
Tel: 86-532-5027355 Fax: 86-532-5027205
San Jose
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands
P. A. De Biesbosch 14
NL-5152 SC Drunen, Netherlands
Tel: 31-416-690399
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408-436-7950
Fax: 408-436-7955
India
Toronto
Divyasree Chambers
1 Floor, Wing A (A3/A4)
No. 11, O’Shaugnessey Road
Bangalore, 560 025, India
Tel: 91-80-2290061 Fax: 91-80-2290062
Japan
6285 Northam Drive, Suite 108
Mississauga, Ontario L4V 1X5, Canada
Tel: 905-673-0699
Fax: 31-416-690340
United Kingdom
505 Eskdale Road
Winnersh Triangle
Fax: 905-673-6509
Wokingham
Berkshire, England RG41 5TU
Tel: 44-118-921-5869
Fax: 44-118-921-5820
Benex S-1 6F
3-18-20, Shinyokohama
Kohoku-Ku, Yokohama-shi
Kanagawa, 222-0033, Japan
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
07/28/03
DS21822C-page 26
Preliminary
2003 Microchip Technology Inc.
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