24LC64F-E/MNY.OT_技术文档

24AA64F/24LC64F

64K I²C^™Serial EEPROM with Quarter-Array Write-Protect

Device Selection Table

Description:

Part

Number

VCC

Range

Max. Clock

Frequency

Temp.

Ranges

The Microchip Technology Inc. 24AA64F/24LC64F

(24XX64F*) is a 64 Kbit Electrically Erasable PROM.

The device is organized as a single block of 8K x 8-bit

memory with a 2-wire serial interface. Low-voltage

design permits operation down to 1.7V, with standby

and read currents of only 1 μA and 400 μA,

24AA64F

24LC64F

1.7-5.5

2.5-5.5

400 kHz⁽¹⁾

400 kHz

I

I, E

Note 1: 100 kHz for VCC <2.5V.

respectively. It has been developed for advanced, low-

power applications such as personal communications

or data acquisition. The 24XX64F also has a page

write capability for up to 32 bytes of data. Functional

address lines allow up to eight devices on the same

bus, for up to 512 Kbits address space. The 24XX64F

is available in the standard 8-pin PDIP, surface mount

SOIC, TSSOP, TDFN and MSOP packages. The

24XX64F is also available in the 5-lead SOT-23

package.

Features:

• Single-Supply with Operation down to 1.7V for

24AA64F devices, 2.5V for 24LC64F devices

• Low-Power CMOS Technology:

- Read current 400 μA, max.

- Standby current 1 μA, max. (I-temp)

• 2-Wire Serial Interface, I²C™ Compatible

• Packages with 3 Address Pins are cascadable up

to 8 Devices

Block Diagram

• Schmitt Trigger Inputs for Noise Suppression

• Output Slope Control to Eliminate Ground Bounce

• 100 kHz and 400 kHz Clock Compatibility

• Page Write Time 5 ms, typical

HV

A0 A1 A2WP

Generator

I/O

Control

Logic

Memory

Control

Logic

EEPROM

Array

• Self-timed Erase/Write Cycle

XDEC

• 32-Byte Page Write Buffer

Page

Latches

• Hardware Write-protect for 1/4 Array

(1800h-1FFFh)

I/O

• ESD Protection > 4,000V

SCL

YDEC

• More than 1 Million Erase/Write Cycles

• Data Retention > 200 Years

SDA

• Factory Programming Available

VCC

VSS

• Packages include 8-lead PDIP, SOIC, TSSOP,

MSOP, TDFN, 5-lead SOT-23

Sense Amp.

R/W Control

• Pb-Free and RoHS Compliant

• Temperature Ranges:

- Industrial (I): -40°C to +85°C

- Automotive (E): -40°C to +125°C

Package Types

PDIP/MSOP/SOIC/TSSOP

DFN/TDFN

SOT-23

A0

1

8

VCC

SCL

VSS

WP

5

4

1

2

1

VCC

WP

A0

A1

8

7

6

5

A1

A2

2

3

7

6

WP

2

3

4

SCL

SDA

A2

SCL

VSS

VCC

3

SDA

VSS

4

5

SDA

* 24XX64F is used in this document as a generic part number for the 24AA64F/24LC64F devices.

DS22154A-page 1

24AA64F/24LC64F

1.0

ELECTRICAL CHARACTERISTICS

(†)

Absolute Maximum Ratings

VCC.............................................................................................................................................................................6.5V

All inputs and outputs w.r.t. VSS ......................................................................................................... -0.3V to VCC +1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied................................................................................................-40°C to +125°C

ESD protection on all pins ......................................................................................................................................................≥ 4 kV

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only and functional operation of the device at those or any other conditions

above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating

conditions for extended periods may affect device reliability.

TABLE 1-1:

DC CHARACTERISTICS

Industrial (I):

TA = -40°C to +85°C, VCC = +1.7V to +5.5V

DC CHARACTERISTICS

Automotive (E): TA = -40°C to +125°C, VCC = +2.5V to +5.5V

Param.

Sym.

No.

Characteristic

Min.

Typ.

Max.

Units

Conditions

—

A0, A1, A2, WP, SCL

and SDA pins

—

D1

D2

VIH

VIL

High-level input voltage

Low-level input voltage

0.7 VCC

—

V

0.3 VCC

0.2 VCC

V

VCC ≥ 2.5V

VCC < 2.5V

D3

D4

VHYS

VOL

Hysteresis of Schmitt

Trigger inputs (SDA,

SCL pins)

0.05 VCC

—

V

VCC ≥ 2.5V (Note 1)

Low-level output voltage

0.40

V

IOL = 3.0 mA @ VCC = 4.5V

IOL = 2.1 mA @ VCC = 2.5V

D5

D6

D7

ILI

Input leakage current

Output leakage current

—

±1

10

μA

pF

VIN = VSS or VCC

ILO

VOUT = VSS or VCC

CIN,

Pin capacitance

VCC = 5.0V (Note 1)

COUT

(all inputs/outputs)

TA = 25°C, FCLK = 1 MHz

D8

ICC write Operating current

—

0.1

3

mA

VCC = 5.5V, SCL = 400 kHz

D9

ICC read

0.05

400

μA

D10

ICCS

Standby current

—

.01

—

1

5

μA

Industrial

Automotive

SDA = SCL = VCC

A0, A1, A2, WP = VSS

Note 1: This parameter is periodically sampled and not 100% tested.

2: Typical measurements taken at room temperature.

DS22154A-page 2

24AA64F/24LC64F

TABLE 1-2:

AC CHARACTERISTICS

Electrical Characteristics:

Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C

Automotive (E): VCC = +2.5V to 5.5V TA = -40°C to 125°C

AC CHARACTERISTICS

Param.

Sym.

No.

Characteristic

Clock frequency

Min.

Max.

Units

Conditions

1

2

3

4

5

6

7

FCLK

THIGH

TLOW

TR

—

100

400

kHz 1.7V ≤ VCC < 2.5V

2.5V ≤ VCC ≤ 5.5V

Clock high time

Clock low time

4000

600

—

ns

1.7V ≤ VCC < 2.5V

2.5V ≤ VCC ≤ 5.5V

4700

1300

—

1.7V ≤ VCC < 2.5V

2.5V ≤ VCC ≤ 5.5V

SDA and SCL rise time

(Note 1)

—

1000

300

1.7V ≤ VCC < 2.5V

2.5V ≤ VCC ≤ 5.5V

TF

SDA and SCL fall time

(Note 1)

—

300

—

THD:STA Start condition hold time

TSU:STA Start condition setup time

4000

600

—

1.7V ≤ VCC < 2.5V

2.5V ≤ VCC ≤ 5.5V

4700

600

—

1.7V ≤ VCC < 2.5V

2.5V ≤ VCC ≤ 5.5V

8

9

THD:DAT Data input hold time

TSU:DAT Data input setup time

0

—

ns

(Note 2)

250

100

—

1.7V ≤ VCC < 2.5V

2.5V ≤ VCC ≤ 5.5V

10

11

12

13

14

TSU:STO Stop condition setup time

TSU:WP WP setup time

4000

600

—

ns

1.7 V ≤ VCC < 2.5V

2.5 V ≤ VCC ≤ 5.5V

4000

600

—

1.7V ≤ VCC < 2.5V

2.5V ≤ VCC ≤ 5.5V

THD:WP WP hold time

4700

1300

—

1.7V ≤ VCC < 2.5V

2.5V ≤ VCC ≤ 5.5V

TAA

Output valid from clock

—

3500

900

1.7V ≤ VCC < 2.5V

2.5V ≤ VCC ≤ 5.5V

(Note 2)

TBUF

Bus free time: Time the bus

must be free before a new

transmission can start

4700

1300

—

1.7V ≤ VCC < 2.5V

2.5V ≤ VCC ≤ 5.5V

15

TOF

Output fall time from VIH

minimum to VIL maximum

CB ≤ 100 pF

10 + 0.1CB

250

ns

(Note 1)

16

17

18

TSP

TWC

—

Input filter spike suppression

(SDA and SCL pins)

—

50

5

ns

(Notes 1 and 3)

Write cycle time (byte or

page)

ms

—

Endurance

1,000,000

—

cycles 25°C (Note 4)

Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved

noise spike suppression. This eliminates the need for a TI specification for standard operation.

4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific

application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site

at www.microchip.com.

DS22154A-page 3

24AA64F/24LC64F

FIGURE 1-1:

BUS TIMING DATA

5

4

D4

2

SCL

7

3

10

8

9

SDA

IN

6

16

14

12

13

SDA

OUT

(protected)

WP

11

(unprotected)

DS22154A-page 4

24AA64F/24LC64F

The descriptions of the pins are listed in Table 2-1.

2.0

PIN DESCRIPTIONS

TABLE 2-1:

Name

PIN FUNCTION TABLE

PDIP

SOIC

TSSOP

TDFN

MSOP

SOT-23

Description

Chip Address Input

A0

A1

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

—

2

Chip Address Input

Ground

A2

VSS

SDA

SCL

WP

VCC

3

Serial Address/Data I/O

Serial Clock

1

5

Write-Protect Input

+1.7V to 5.5V Power Supply

4

2.1

A0, A1, A2 Chip Address Inputs

2.3

Serial Clock (SCL)

The A0, A1 and A2 inputs are used by the 24XX64F for

multiple device operation. The levels on these inputs

are compared with the corresponding bits in the slave

address. The chip is selected if the compare is true.

The SCL input is used to synchronize the data transfer

from and to the device.

2.4

Write-Protect (WP)

Up to eight devices may be connected to the same bus

by using different Chip Select bit combinations. These

inputs must be connected to either VCC or VSS.

This pin must be connected to either VSS or VCC. If tied

to VSS, write operations are enabled. If tied to VCC,

write operations are inhibited for upper 1/4 of the array

(1800h-1FFFh), but read operations are not affected.

In most applications, the chip address inputs A0, A1

and A2 are hard-wired to logic ‘0’ or logic ‘1’. For

applications in which these pins are controlled by a

microcontroller or other programmable device, the chip

address pins must be driven to logic ‘0’ or logic ‘1’

before normal device operation can proceed. Address

pins are not available in the SOT-23 package.

3.0

FUNCTIONAL DESCRIPTION

The 24XX64F supports a bidirectional, 2-wire bus and

data transmission protocol. A device that sends data

onto the bus is defined as transmitter, while a device

receiving data is defined as a receiver. The bus has to

be controlled by a master device which generates the

Serial Clock (SCL), controls the bus access and

generates the Start and Stop conditions, while the

24XX64F works as slave. Both master and slave can

operate as transmitter or receiver, but the master

device determines which mode is activated.

2.2

Serial Data (SDA)

SDA is a bidirectional pin used to transfer addresses

and data into and out of the device. Since it is an open-

drain terminal, the SDA bus requires a pull-up resistor

to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for 400 kHz).

For normal data transfer, SDA is allowed to change

only during SCL low. Changes during SCL high are

reserved for indicating the Start and Stop conditions.

DS22154A-page 5

24AA64F/24LC64F

The data on the line must be changed during the low

period of the clock signal. There is one clock pulse per

bit of data.

4.0

BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy

Each data transfer is initiated with a Start condition and

terminated with a Stop condition. The number of data

bytes transferred between Start and Stop conditions is

determined by the master device and is, theoretically,

unlimited (although only the last thirty two will be stored

when doing a write operation). When an overwrite does

occur, it will replace data in a first-in first-out (FIFO)

fashion.

• During data transfer, the data line must remain

stable whenever the clock line is high. Changes in

the data line while the clock line is high will be

interpreted as a Start or Stop condition

Accordingly, the following bus conditions have been

defined (Figure 4-1).

4.5

Acknowledge

4.1

Bus Not Busy (A)

Each receiving device, when addressed, is obliged to

generate an acknowledge after the reception of each

byte. The master device must generate an extra clock

pulse which is associated with this Acknowledge bit.

Both data and clock lines remain high.

4.2

Start Data Transfer (B)

A high-to-low transition of the SDA line while the clock

(SCL) is high determines a Start condition. All

commands must be preceded by a Start condition.

Note:

The 24XX64F does not generate any

Acknowledge bits if an internal

programming cycle is in progress.

The device that acknowledges has to pull down the

SDA line during the Acknowledge clock pulse in such a

way that the SDA line is stable low during the high

period of the acknowledge related clock pulse. Of

course, setup and hold times must be taken into

account. During reads, a master must signal an end of

data to the slave by not generating an Acknowledge bit

on the last byte that has been clocked out of the slave.

In this case, the slave (24XX64F) will leave the data

line high to enable the master to generate the Stop

condition.

4.3

Stop Data Transfer (C)

A low-to-high transition of the SDA line while the clock

(SCL) is high determines a Stop condition. All

operations must be ended with a Stop condition.

4.4

Data Valid (D)

The state of the data line represents valid data when,

after a Start condition, the data line is stable for the

duration of the high period of the clock signal.

FIGURE 4-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A)

(B)

(D)

(C) (A)

SCL

SDA

Start

Condition

Stop

Condition

Address or

Acknowledge

Valid

Data

Allowed

to Change

DS22154A-page 6

24AA64F/24LC64F

FIGURE 5-1:

CONTROL BYTE FORMAT

5.0

DEVICE ADDRESSING

Read/Write Bit

A control byte is the first byte received following the

Start condition from the master device (Figure 5-1).

The control byte consists of a four-bit control code. For

the 24XX64F, this is set as ‘1010’ binary for read and

write operations. The next three bits of the control byte

are the Chip Select bits (A2, A1, A0). The Chip Select

bits allow the use of up to eight 24XX64F devices on

the same bus and are used to select which device is

accessed. The Chip Select bits in the control byte must

correspond to the logic levels on the corresponding A2,

A1 and A0 pins for the device to respond. These bits

are, in effect, the three Most Significant bits of the word

address.

Chip Select

Control Code

Bits

S

1

0

1

0

A2 A1 A0 R/W ACK

Slave Address

Acknowledge Bit

Start Bit

5.1

Contiguous Addressing Across

Multiple Devices

For the SOT-23 package, the address pins are not

available. During device addressing, the A2, A1 and A0

Chip Select bits (Figure 5-2) should be set to ‘0’.

The Chip Select bits A2, A1 and A0 can be used to

expand the contiguous address space for up to 512K

bits by adding up to eight 24XX64F devices on the

same bus. In this case, software can use A0 of the con-

trol byte as address bit A13; A1 as address bit A14; and

A2 as address bit A15. It is not possible to sequentially

read across device boundaries.

The last bit of the control byte defines the operation to

be performed. When set to a ‘1’, a read operation is

selected. When set to a ‘0’, a write operation is

selected. The next two bytes received define the

address of the first data byte (Figure 5-2). Because

only A12...A0 are used, the upper-three address bits

are “don’t care” bits. The upper-address bits are

transferred first, followed by the Less Significant bits.

The SOT-23 package does not support multiple device

addressing on the same bus.

Following the Start condition, the 24XX64F monitors

the SDA bus, checking the device-type identifier being

transmitted. Upon receiving a ‘1010’ code and appro-

priate device-select bits, the slave device outputs an

Acknowledge signal on the SDA line. Depending on the

state of the R/W bit, the 24XX64F will select a read or

write operation.

FIGURE 5-2:

ADDRESS SEQUENCE BIT ASSIGNMENTS

Control Byte

Address High Byte

Address Low Byte

A

2

A

1

A

0

A

9

A

8

A

7

A

0

•

1

0

1

0

R/W

x

12 11 10

Control

Code

Chip

Select

bits

x= “don’t care” bit

DS22154A-page 7

24AA64F/24LC64F

6.2

Page Write

6.0

6.1

WRITE OPERATIONS

Byte Write

The write control byte, word address and the first data

byte are transmitted to the 24XX64F in the same way

as in a byte write. However, instead of generating a

Stop condition, the master transmits up to 31 additional

bytes which are temporarily stored in the on-chip page

buffer and will be written into memory once the master

has transmitted a Stop condition. Upon receipt of each

word, the five lower Address Pointer bits are internally

incremented by one. If the master should transmit more

than 32 bytes prior to generating the Stop condition, the

address counter will roll over and the previously

received data will be overwritten. As with the byte write

operation, once the Stop condition is received, an inter-

nal write cycle will begin (Figure 6-2). If an attempt is

made to write to the array with the WP pin held high, the

device will acknowledge the command, but no write

cycle will occur, no data will be written, and the device

will immediately accept a new command.

Following the Start condition from the master, the

control code (four bits), the Chip Select (three bits) and

the R/W bit (which is a logic low) are clocked onto the

bus by the master transmitter. This indicates to the

addressed slave receiver that the address high byte will

follow once it has generated an Acknowledge bit during

the ninth clock cycle. Therefore, the next byte transmit-

ted by the master is the high-order byte of the word

address and will be written into the Address Pointer of

the 24XX64F. The next byte is the Least Significant

Address Byte. After receiving another Acknowledge

signal from the 24XX64F, the master device will trans-

mit the data word to be written into the addressed mem-

ory location. The 24XX64F acknowledges again and

the master generates a Stop condition. This initiates

the internal write cycle and, during this time, the

24XX64F will not generate Acknowledge signals

(Figure 6-1). If an attempt is made to write to the array

with the WP pin held high, the device will acknowledge

the command, but no write cycle will occur, no data will

be written and the device will immediately accept a new

command. After a byte Write command, the internal

address counter will point to the address location fol-

lowing the one that was just written.

Note:

Page write operations are limited to writing

bytes within a single physical page,

regardless of the number of bytes

actually being written. Physical page

boundaries start at addresses that are

integer multiples of the page buffer size (or

‘page size’) and end at addresses that are

integer multiples of [page size – 1]. If a

Page Write command attempts to write

across a physical page boundary, the

result is that the data wraps around to the

beginning of the current page (overwriting

data previously stored there), instead of

being written to the next page, as might be

expected. It is therefore necessary for the

application software to prevent page write

operations that would attempt to cross a

page boundary.

6.3

Write Protection

The WP pin allows the user to write-protect 1/4 of the

array (1800h-1FFFh) when the pin is tied to VCC. If tied

to VSS the write protection is disabled. The WP pin is

sampled at the Stop bit for every Write command

(Figure 4-1). Toggling the WP pin after the Stop bit will

have no effect on the execution of the write cycle.

DS22154A-page 8

24AA64F/24LC64F

FIGURE 6-1:

BYTE WRITE

S

T

Bus Activity

Master

S

Control

A

Address

High Byte

Address

Low Byte

T

O

P

Byte

R

T

Data

A A A

S 1 0 1 0

2 1 0

SDA Line

x x x

0

P

A

C

K

A

C

K

A

C

K

A

C

K

Bus Activity

x= “don’t care” bit

FIGURE 6-2:

PAGE WRITE

S

T

A

R

T

S

T

O

P

Control

Byte

Address

High Byte

Address

Low Byte

Bus Activity

Master

Data Byte 0

Data Byte 31

A A A

SDA Line

x x x

P

S

10 1 0

0

2 1 0

A

C

K

A

C

K

A

C

K

A

C

K

A

C

K

Bus Activity

x= “don’t care” bit

DS22154A-page 9

24AA64F/24LC64F

FIGURE 7-1:

ACKNOWLEDGE POLLING

FLOW

7.0

ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write

cycle, this can be used to determine when the cycle is

complete (this feature can be used to maximize bus

throughput). Once the Stop condition for a Write

command has been issued from the master, the device

initiates the internally-timed write cycle and ACK polling

can then be initiated immediately. This involves the

master sending a Start condition followed by the control

byte for a Write command (R/W = 0). If the device is still

busy with the write cycle, then no ACK will be returned.

If no ACK is returned, the Start bit and control byte must

be re-sent. If the cycle is complete, the device will

return the ACK and the master can then proceed with

the next Read or Write command. See Figure 7-1 for a

flow diagram of this operation.

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

No

Yes

DS22154A-page 10

24AA64F/24LC64F

This terminates the write operation, but not before

the internal Address Pointer is set. The master then

issues the control byte again, but with the R/W bit set

to a one. The 24XX64F will then issue an acknowl-

edge and transmit the 8-bit data word. The master

will not acknowledge the transfer, but does generate

a Stop condition, which causes the 24XX64F to

8.0

READ OPERATION

Read operations are initiated in the same way as write

operations, with the exception that the R/W bit of the

control byte is set to one. There are three basic types

of read operations: current address read, random read

and sequential read.

discontinue transmission (Figure 8-2). After

a

random Read command, the internal address coun-

ter will point to the address location following the one

that was just read.

8.1

Current Address Read

The 24XX64F contains an address counter that main-

tains the address of the last word accessed, internally

incremented by one. Therefore, if the previous read

access was to address ‘n’ (n is any legal address), the

next current address read operation would access data

from address n + 1.

8.3

Sequential Read

Sequential reads are initiated in the same way as

random reads, except that once the 24XX64F transmits

the first data byte, the master issues an acknowledge as

opposed to the Stop condition used in a random read.

This acknowledge directs the 24XX64F to transmit the

next sequentially-addressed 8-bit word (Figure 8-3).

Following the final byte being transmitted to the master,

the master will NOT generate an acknowledge, but will

generate a Stop condition. To provide sequential reads,

the 24XX64F contains an internal Address Pointer

which is incremented by one at the completion of each

operation. This Address Pointer allows the entire

memory contents to be serially read during one opera-

tion. The internal Address Pointer will automatically roll

over from address 1FFF to address 0000 if the master

acknowledges the byte received from the array address

1FFF.

Upon receipt of the control byte with R/W bit set to one,

the 24XX64F issues an acknowledge and transmits the

eight-bit data word. The master will not acknowledge

the transfer, but does generate a Stop condition and the

24XX64F discontinues transmission (Figure 8-1).

8.2

Random Read

Random read operations allow the master to access

any memory location in a random manner. To

perform this type of read operation, the word address

must first be set. This is accomplished by sending

the word address to the 24XX64F as part of a write

operation (R/W bit set to ‘0’). Once the word address

is sent, the master generates a Start condition

following the acknowledge.

FIGURE 8-1:

CURRENT ADDRESS READ

S

Bus Activity

Master

T

A

R

Control

Byte

S

T

Data (n)

O

P

T

SDA Line

S

P

A

C

K

N

O

Bus Activity

A

C

K

DS22154A-page 11

24AA64F/24LC64F

FIGURE 8-2:

RANDOM READ

S

T

A

R

T

Bus Activity

Master

T

A

R

T

S

T

O

P

Control

Byte

Address

High Byte

Address

Low Byte

Control

Byte

Data

Byte

A A A

2 1 0

A A A

2 1 0

SDA Line

x x x

S 1 0 1 0

0

S 1 01 0

1

P

A

C

K

A

C

K

A

C

K

N

O

A

C

K

A

C

K

Bus Activity

x= “don’t care” bit

FIGURE 8-3:

SEQUENTIAL READ

S

T

O

P

Bus Activity

Master

Control

Data n

Byte

Data n + 1

Data n + 2

Data n + x

P

SDA Line

A

C

K

A

C

K

A

C

K

A

C

K

N

O

A

C

K

Bus Activity

DS22154A-page 12

24AA64F/24LC64F

9.0

9.1

PACKAGING INFORMATION

Package Marking Information

8-Lead PDIP (300 mil)

Example:

24LC64F

XXXXXXXX

T/XXXNNN

I/P

13F

e

3

YYWW

0527

8-Lead SOIC (3.90 mm)

Example:

24LC64FI

XXXXXXXT

e

3

XXXXYYWW

SN

0527

13F

NNN

Example:

8-Lead TSSOP

4LBF

I527

13F

XXXX

TYWW

NNN

Example:

8-Lead MSOP

4L64FI

XXXXXT

52713F

YWWNNN

8-Lead 2x3 TDFN

Example:

XXX

YWW

NN

AT4

527

I3

DS22154A-page 13

24AA64F/24LC64F

5-Lead SOT-23

Example:

7MNN

XXNN

1st Line Marking Codes

TDFN

Part Number

TSSOP

MSOP

SOT-23

I Temp.

AT1

E Temp.

—

I Temp.

7MNN

7QNN

E Temp.

—

24AA64F

24LC64F

4ABF

4LBF

4A64FT

4L64FT

AT4

AT5

7RNN

Note:

T = Temperature grade (I, E)

Legend: XX...X Part number or part number code

T

Temperature (I, E)

Y

Year code (last digit of calendar year)

YY

WW

NNN

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code (2 characters for small packages)

Pb-free JEDEC designator for Matte Tin (Sn)

e

3

Note: For very small packages with no room for the Pb-free JEDEC designator

, the marking will only appear on the outer carton or reel label.

3

e

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

DS22154A-page 14

24AA64F/24LC64F

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DS22154A-page 15

24AA64F/24LC64F

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DS22154A-page 16

24AA64F/24LC64F

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DS22154A-page 17

24AA64F/24LC64F

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DS22154A-page 18

24AA64F/24LC64F

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DS22154A-page 19

24AA64F/24LC64F

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ.ꢋꢌ"ꢗꢆ ꢕꢄꢈꢈꢆ!ꢎꢊꢈꢋꢐꢃꢆꢇꢄꢌ,ꢄ/ꢃꢆꢑ. ꢒꢆꢙ. !ꢇꢚ

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DS22154A-page 20

24AA64F/24LC64F

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢆ0ꢈꢄꢊ$ꢆꢛꢗꢆꢂꢃꢄꢅꢆꢇꢄꢌ,ꢄ/ꢃꢆꢑ.ꢛꢒꢆMꢆ*1ꢓ1ꢔ%2(ꢆꢕꢕꢆꢖꢗꢅꢘꢆꢙ)ꢍ0ꢛꢚ

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DS22154A-page 21

24AA64F/24LC64F

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢆ0ꢈꢄꢊ$ꢆꢛꢗꢆꢂꢃꢄꢅꢆꢇꢄꢌ,ꢄ/ꢃꢆꢑ.ꢛꢒꢆMꢆ*1ꢓ1ꢔ%2(ꢆꢕꢕꢆꢖꢗꢅꢘꢆꢙ)ꢍ0ꢛꢚ

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ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ

DS22154A-page 22

24AA64F/24LC64F

APPENDIX A: REVISION HISTORY

Revision A

Original Release.

DS22154A-page 23

24AA64F/24LC64F

NOTES:

DS22154A-page 24

24AA64F/24LC64F

THE MICROCHIP WEB SITE

CUSTOMER SUPPORT

Microchip provides online support via our WWW site at

www.microchip.com. This web site is used as a means

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following

information:

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

• Product Support – Data sheets and errata,

application notes and sample programs, design

resources, user’s guides and hardware support

documents, latest software releases and archived

software

• Development Systems Information Line

Customers

should

contact

their

distributor,

representative or field application engineer (FAE) for

support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

• General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online discussion groups, Microchip consultant

program member listing

Technical support is available through the web site

at: http://support.microchip.com

• Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminars and events, listings of

Microchip sales offices, distributors and factory

representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a

specified product family or development tool of interest.

To register, access the Microchip web site at

www.microchip.com, click on Customer Change

Notification and follow the registration instructions.

DS22154A-page 25

24AA64F/24LC64F

READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-

uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation

can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

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24AA64F/24LC64F

DS22154A

Literature Number:

Device:

Questions:

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

DS22154A-page 26

24AA64F/24LC64F

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO.

Device

X

/XX

Examples:

Temperature Package

Range

a) 24AA64F-I/P: Industrial Temperature,

1.7V, PDIP package

b) 24AA64F-I/SN: Industrial Temperature,

1.7V, SOIC package

2

Device:

24AA64F: 1.7V, 64 Kbit I C™ Serial EEPROM

2

24AA64FT: 1.7V, 64 Kbit I C Serial EEPROM

c) 24AA64FT-I/ST: Industrial Temperature,

1.7V, TSSOP package, tape and reel

(Tape and Reel)

2

24LC64F: 2.5V, 64 Kbit I C Serial EEPROM

d) 24LC64F-I/P: Industrial Temperature,

2.5V, PDIP package

2

24LC64FT: 2.5V, 64 Kbit I C Serial EEPROM

(Tape and Reel)

e) 24LC64F-E/SN: Extended Temperature,

2.5V, SOIC package

Temperature

Range:

I

E

=

-40°C to +85°C

-40°C to +125°C

f)

24LC64F-I/ST: Industrial Temperature,

2.5V, TSSOP package

Package:

P

SN

ST

=

Plastic DIP (300 mil body), 8-lead

Plastic SOIC (3.90 mm body), 8-lead

Plastic TSSOP (4.4 mm), 8-lead

MS

MNY

OT

=

Plastic Micro Small Outline (MSOP), 8-lead

TDFN (2x3x0.75 mm body), 8-lead

SOT-23 (Tape and Reel only), 5-lead

(1)

=

Note 1: "Y" indicates a Nickel Palladium Gold (NiPdAu) finish.

ꢀ 2009 Microchip Technology Inc.

DS22154A-page27

24AA64F/24LC64F

NOTES:

DS22154A-page 28

ꢀ 2009 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,

PICSTART, rfPIC, SmartShunt and UNI/O are registered

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

FilterLab, Hampshire, Linear Active Thermistor, MXDEV,

MXLAB, SEEVAL, SmartSensor and The Embedded Control

Solutions Company are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, In-Circuit Serial

Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB

Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP,

32

PICkit, PICDEM, PICDEM.net, PICtail, PIC logo, PowerCal,

PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select

Mode, Total Endurance, TSHARC, WiperLock and ZENA are

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

DS22154A-page 29

WORLDWIDE SALES AND SERVICE

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

India - Bangalore

Tel: 91-80-3090-4444

Fax: 91-80-3090-4080

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://support.microchip.com

Web Address:

www.microchip.com

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

China - Beijing

Tel: 86-10-8528-2100

Fax: 86-10-8528-2104

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Korea - Daegu

Tel: 82-53-744-4301

Fax: 82-53-744-4302

Boston

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Korea - Seoul

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

China - Nanjing

Tel: 86-25-8473-2460

Fax: 86-25-8473-2470

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

Cleveland

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

Independence, OH

Tel: 216-447-0464

Fax: 216-447-0643

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Malaysia - Penang

Tel: 60-4-227-8870

Fax: 60-4-227-4068

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Detroit

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

Taiwan - Hsin Chu

Tel: 886-3-6578-300

Fax: 886-3-6578-370

Kokomo

Kokomo, IN

Tel: 765-864-8360

Fax: 765-864-8387

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Xiamen

Tel: 86-592-2388138

Fax: 86-592-2388130

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Santa Clara

China - Xian

Tel: 86-29-8833-7252

Fax: 86-29-8833-7256

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

China - Zhuhai

Tel: 86-756-3210040

Fax: 86-756-3210049

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

03/26/09

DS22154A-page 30


型号：	24LC64F-E/MNY.OT
厂家：	MICROCHIP
描述：	64K I2C™ Serial EEPROM with Quarter-Array Write-Protect 64K I2C ™串行EEPROM ，具有四分之一阵列写保护可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件：	总30页 (文件大小：470K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

24LC64F-E/MNY.OT [MICROCHIP]

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24LC64F-E/MS

24LC64F-E/P

24LC64F-E/SN

24LC64F-E/ST

24LC64F-I/MNY.OT

24LC64F-I/MS

24LC64F-I/P

24LC64F-I/SN

24LC64F-I/ST

24LC64FEMNY

24LC64FEMS

24LC64FEOT