24LC21A1T-/SN [MICROCHIP]
1K 2.5V Dual Mode I 2 C Serial EEPROM; 1K 2.5V双模式I 2 C串行EEPROM
| 型号： | 24LC21A1T-/SN |
| 厂家： | 
MICROCHIP |
| 描述： | 1K 2.5V Dual Mode I 2 C Serial EEPROM |
| 文件： | 总18页 (文件大小：241K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
24LC21A
1K 2.5V Dual Mode I2C™ Serial EEPROM
Features
Package Types
• Single supply with operation down to 2.5V
PDIP
NC
NC
1
8
7
Vcc
• Completely implements DDC1™/DDC2™
interface for monitor identification, including
recovery to DDC1
2
3
4
VCLK
• Pin and function compatible with 24LC21
• Low-power CMOS technology
NC
6
5
SCL
SDA
- 1 mA typical active current
VSS
- 10 µA standby current typical at 5.5V
• 2-wire serial interface bus, I2C™ compatible
• 100 kHz (2.5V) and 400 kHz (5V) compatibility
• Self-timed write cycle (including auto-erase)
• Page write buffer for up to eight bytes
SOIC
1
2
3
4
8
7
6
5
NC
Vcc
NC
NC
VCLK
•
1,000,000 erase/write cycles ensured
• Data retention > 200 years
SCL
SDA
• ESD Protection > 4000V
• 8-pin PDIP and SOIC package
• Available for extended temperature ranges
Vss
- Commercial (C):
- Industrial (I):
0°C to +70°C
-40°C to +85°C
Block Diagram
Description
HV Generator
The Microchip Technology Inc. 24LC21A is a 128 x 8-bit
dual-mode Electrically Erasable PROM. This device is
designed for use in applications requiring storage and
serial transmission of configuration and control informa-
tion. Two modes of operation have been implemented:
Transmit-only mode and Bidirectional mode. Upon
power-up, the device will be in the Transmit-only mode,
sending a serial bit stream of the memory array from 00h
to 7Fh, clocked by the VCLK pin. A valid high-to-low
transition on the SCL pin will cause the device to enter
the transition mode, and look for a valid control byte on
the I2C bus. If it detects a valid control byte from the
master, it will switch into Bidirectional mode, with byte
selectable read/write capability of the memory array
using SCL. If no control byte is received, the device will
revert to the Transmit-only mode after it receives 128
consecutive VCLK pulses while the SCL pin is idle. The
24LC21A is available in a standard 8-pin PDIP and
SOIC package in both commercial and industrial
temperature ranges.
I/O
Control
Logic
Memory
Control
Logic
EEPROM
Array
XDEC
Page Latches
SCL
SDA
YDEC
VCLK
Sense AMP
R/W Control
VCC
VSS
Pin Function Table
Name
Function
VSS
SDA
SCL
VCLK
VCC
Ground
Serial Address/Data I/O
Serial Clock (Bidirectional mode)
Serial Clock (Transmit-only mode)
+2.5V to 5.5V Power Supply
No Connection
DDC is a trademark of the Video Electronics Standards
Association.
NC
2
I C is a trademark of Philips Corporation.
2003 Microchip Technology Inc.
DS21160F-page 1
24LC21A
1.0
ELECTRICAL CHARACTERISTICS
(†)
Absolute Maximum Ratings
VCC.............................................................................................................................................................................7.0V
All inputs and outputs w.r.t. VSS.........................................................................................................................................-0.6V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied................................................................................................-65°C to +125°C
ESD protection on all pins ......................................................................................................................................................≥ 4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
VCC = +2.5V to 5.5V
DC CHARACTERISTICS
Commercial (C): TA = 0°C to +70°C
Industrial (I):
TA =-40°C to +85°C
Parameter
Symbol
Min
Max
Units
Conditions
SCL and SDA pins:
High-level input voltage
Low-level input voltage
VIH
VIL
0.7 VCC
—
—
0.3 VCC
V
V
Input levels on VCLK pin:
High-level input voltage
Low-level input voltage
VIH
VIL
2.0
—
—
0.2 VCC
V
V
VCC ≥ 2.7V (Note)
VCC < 2.7V (Note)
Hysteresis of Schmitt Trigger inputs
Low-level output voltage
VHYS
VOL1
VOL2
ILI
.05 VCC
—
0.4
0.6
±1
V
V
(Note)
—
—
—
—
—
IOL = 3 mA, VCC = 2.5V (Note)
IOL = 6 mA, VCC = 2.5V
VIN = 0.1V to VCC
VOUT = 0.1V to VCC
Low-level output voltage
V
Input leakage current
µA
µA
pF
Output leakage current
ILO
±1
Pin capacitance (all inputs/outputs)
CIN, COUT
10
VCC = 5.0V (Note)
TA = 25°C, FCLK = 1 MHz
Operating current
Standby current
ICC Write
ICC Read
—
—
3
1
mA
mA
VCC = 5.5V
VCC = 5.5V, SCL = 400 kHz
ICCS
—
—
30
100
µA
µA
VCC = 3.0V, SDA = SCL = VCC
VCC = 5.5V, SDA = SCL = VCC
VCLK = VSS
Note:
This parameter is periodically sampled and not 100% tested.
DS21160F-page 2
2003 Microchip Technology Inc.
24LC21A
TABLE 1-2:
AC CHARACTERISTICS
Vcc= 2.5-5.5V
Vcc= 4.5 - 5.5V
Fast Mode
Standard Mode
Parameter
Symbol
Units
Remarks
Min
Max
Min
Max
Clock frequency
FCLK
THIGH
TLOW
TR
—
4000
4700
—
100
—
—
600
1300
—
400
—
kHz
ns
Clock high time
Clock low time
—
—
ns
SDA and SCL rise time
SDA and SCL fall time
Start condition hold time
1000
300
—
300
300
—
ns
(Note 1)
TF
—
—
ns
(Note 1)
THD:STA
4000
600
ns
After this period the first clock
pulse is generated
Start condition setup time TSU:STA
4700
—
600
—
ns
Only relevant for repeated
Start condition
Data input hold time
Data input setup time
Stop condition setup time
Output valid from clock
Bus free time
THD:DAT
TSU:DAT
TSU:STO
TAA
0
—
—
0
—
—
ns
ns
ns
ns
ns
(Note 2)
250
4000
—
100
600
—
—
—
3500
—
900
—
(Note 2)
TBUF
4700
1300
Time the bus must be free
before a new transmission
can start
Output fall time from VIH
minimum to VIL maximum
TOF
TSP
TWR
—
—
—
250
50
20 + 0.1
CB
250
50
ns
ns
(Note 1), CB ≤ 100 pF
Input filter spike suppres-
sion (SDA and SCL pins)
—
(Note 3)
Write cycle time
10
—
10
ms
Byte or Page mode
Transmit-Only Mode Parameters
Output valid from VCLK
VCLK high time
TVAA
—
4000
4700
0
2000
—
—
600
1300
0
1000
—
ns
ns
ns
ns
ns
ns
ns
TVHIGH
TVLOW
TVHST
TSPVL
TVHZ
VCLK low time
—
—
VCLK setup time
VCLK hold time
—
—
4000
—
—
600
—
—
Mode transition time
1000
—
500
—
Transmit-only power-up
time
TVPU
0
0
Input filter spike suppres-
sion (VCLK pin)
TSPV
—
—
100
—
—
100
—
ns
Endurance
1M
1M
cycles 25°C, Vcc = 5.0V, Block
mode (Note 4)
Note 1: Not 100% tested. CB = Total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to Schmitt Trigger inputs which provide noise and
spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from our web site.
2003 Microchip Technology Inc.
DS21160F-page 3
24LC21A
it be initialized prior to valid data being sent in the
Transmit-only mode (Section 2.2 “Initialization Pro-
cedure”). In this mode, data is transmitted on the SDA
pin in 8-bit bytes, with each byte followed by a ninth,
null bit (Figure 2-1). The clock source for the Transmit-
only mode is provided on the VCLK pin, and a data bit
is output on the rising edge on this pin. The eight bits in
each byte are transmitted Most Significant bit first.
Each byte within the memory array will be output in
sequence. After address 7Fh in the memory array is
transmitted, the internal address pointers will wrap
around to the first memory location (00h) and continue.
The Bidirectional mode Clock (SCL) pin must be held
high for the device to remain in the Transmit-only
mode.
2.0
FUNCTIONAL DESCRIPTION
The 24LC21A is designed to comply to the DDC
Standard proposed by VESA (Figure 3-3) with the
exception that it is not Access.bus capable. It operates
in two modes, the Transmit-only mode and the
Bidirectional mode. There is a separate 2-wire protocol
to support each mode, each having a separate clock
input but sharing a common data line (SDA). The
device enters the Transmit-only mode upon power-up.
In this mode, the device transmits data bits on the SDA
pin in response to a clock signal on the VCLK pin. The
device will remain in this mode until a valid high-to-low
transition is placed on the SCL input. When a valid
transition on SCL is recognized, the device will switch
into the Bidirectional mode and look for its control byte
to be sent by the master. If it detects its control byte, it
will stay in the Bidirectional mode. Otherwise, it will
revert to the Transmit-only mode after it sees 128
VCLK pulses.
2.2
Initialization Procedure
After VCC has stabilized, the device will be in the
Transmit-only mode. Nine clock cycles on the VCLK pin
must be given to the device for it to perform internal
sychronization. During this period, the SDA pin will be
in a high-impedance state. On the rising edge of the
tenth clock cycle, the device will output the first valid
data bit which will be the Most Significant bit in address
00h. (Figure 2-2).
2.1
Transmit-Only Mode
The device will power-up in the Transmit-only mode at
address 00H. This mode supports a unidirectional
2-wire protocol for continuous transmission of the
contents of the memory array. This device requires that
FIGURE 2-1:
TRANSMIT-ONLY MODE
SCL
SDA
Tvaa
Tvaa
Null Bit
Bit 1 (LSB)
Bit 1 (MSB)
Bit 7
VCLK
Tvhigh Tvlow
FIGURE 2-2:
DEVICE INITIALIZATION
Vcc
SCL
Tvaa
Tvaa
Bit 8
High-impedance for 9 clock cycles
Tvpu
Bit 7
SDA
VCLK
1
2
8
9
10
11
DS21160F-page 4
2003 Microchip Technology Inc.
24LC21A
Once the device has switched into the Bidirectional
mode, the VCLK input is disregarded, with the
exception that a logic high level is required to enable
write capability. This mode supports a two-wire
Bidirectional data transmission protocol (I2C™). In this
protocol, a device that sends data on the bus is defined
to be the transmitter, and a device that receives data
from the bus is defined to be the receiver. The bus must
be controlled by a master device that generates the
Bidirectional mode Clock (SCL), controls access to the
bus and generates the Start and Stop conditions, while
the 24LC21A acts as the slave. Both master and slave
can operate as transmitter or receiver, but the master
device determines which mode is activated. In the
Bidirectional mode, the 24LC21A only responds to
commands for device 1010 000X.
3.0
BIDIRECTIONAL MODE
Before the 24LC21A can be switched into the
Bidirectional mode (Figure 3-1), it must enter the
Transition mode, which is done by applying a valid
high-to-low transition on the Bidirectional mode Clock
(SCL). As soon it enters the Transition mode, it looks
for a control byte 1010 000X on the I2C™ bus, and
starts to count pulses on VCLK. Any high-to-low transi-
tion on the SCL line will reset the count. If it sees a
pulse count of 128 on VCLK while the SCL line is idle,
it will revert back to the Transmit-only mode, and
transmit its contents starting with the Most Significant
bit in address 00h. However, if it detects the control
byte on the I2C™ bus, (Figure 3-2) it will switch to the
in the Bidirectional mode. Once the device has made
the transition to the Bidirectional mode, the only way to
switch the device back to the Transmit-only mode is to
remove power from the device. The mode transition
process is shown in detail in Figure 3-3.
FIGURE 3-1:
MODE TRANSITION WITH RECOVERY TO TRANSMIT-ONLY MODE
Transmit
Only
Recovery to Transmit-only mode
Bidirectional
TVHZ
MODE
SCL
SDA
(MSB of data in 00h)
Bit8
VCLK count =
1
2
3
4
127 128
VCLK
FIGURE 3-2:
SUCCESSFUL MODE TRANSITION TO BIDIRECTIONAL MODE
Bidirectional
permanently
Transmit
Only mode
Transition mode with possibility to return to Transmit-only mode
MODE
SCL
SDA
S
1
0
1
0
0
0
0
0
ACK
VCLK count =
VCLK
1
2
n
0
n < 128
2003 Microchip Technology Inc.
DS21160F-page 5
24LC21A
FIGURE 3-3:
DISPLAY OPERATION PER DDC STANDARD PROPOSED BY VESA
The 24LC21A was designed to
comply to the portion of flowchart inside dash box
Display Power-on
or
DDC Circuit Powered
from +5 volts
Communication
is idle
Is Vsync
present?
No
Yes
No
High-to-low
transition on
SCL?
Send EDID continuously
using Vsync as clock
Yes
High-to-low
transition on
SCL?
No
Yes
Stop sending EDID.
DDC2 communication
idle. Display waiting for
address byte.
Switch to DDC2 mode.
Display has
optional
No
transition state
DDC2B
address
received?
Yes
?
Yes
Receive DDC2B
command
Set Vsync counter = 0
or start timer
No
Reset counter or timer
Respond to DDC2B
command
Change on
SCL, SDA or
VCLK lines?
No
Yes
Is display
Access.bus
capable?
No
TM
High - low
transition on SCL
No
?
Yes
Yes
Reset Vsync counter = 0
No
Valid Access.bus
address?
Valid
DDC2 address
received?
Yes
Yes
No
No
See Access.bus
specification to determine
correct procedure.
VCLK
cycle?
Yes
Increment VCLK counter
(if appropriate)
No
Counter=128 or
timer expired?
Yes
Switch back to DDC1
mode.
Note 1: The base flowchart is copyright 1993, 1994, 1995 Video Electronic Standard Association (VESA) from
VESA’s Display Data Channel (DDC) Standard Proposal ver. 2p rev. 0, used by permission of VESA.
2: The dash box and text “The 24LC21A and... inside dash box.” are added by Microchip Technology Inc.
3: Vsync signal is normally used to derive a signal for VCLK pin on the 24LC21A.
DS21160F-page 6
2003 Microchip Technology Inc.
24LC21A
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device and is
theoretically unlimited, although only the last eight will
be stored when doing a write operation. When an
overwrite does occur it will replace data in a first in first
out fashion.
3.1
Bidirectional Mode Bus
Characteristics
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Note:
Once switched into Bidirectional mode, the
24LC21A will remain in that mode until
power is removed. Removing power is the
only way to reset the 24LC21A into the
Transmit-only mode.
Accordingly, the following bus conditions have been
defined (Figure 3-4).
3.1.1
BUS NOT BUSY (A)
3.1.5
ACKNOWLEDGE
Both data and clock lines remain high.
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
3.1.2
START DATA TRANSFER (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
Note:
The 24LC21A does not generate any
Acknowledge bits if an internal
programming cycle is in progress.
3.1.3
STOP DATA TRANSFER (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an Acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line high to enable
the master to generate the Stop condition.
3.1.4
DATA VALID (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.
FIGURE 3-4:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)
(B)
(D)
(D)
(C)
(A)
SCL
SDA
START
CONDITION
STOP
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
2003 Microchip Technology Inc.
DS21160F-page 7
24LC21A
FIGURE 3-5:
BUS TIMING START/STOP
SCL
VHYS
THD:STA
TSU:STO
TSU:STA
SDA
START
STOP
FIGURE 3-6:
BUS TIMING DATA
TF
TR
THIGH
TLOW
SCL
TSU:STA
THD:DAT
THD:STA
TSU:DAT
TSU:STO
SDA
IN
TSP
TBUF
TAA
TAA
SDA
OUT
3.1.6
SLAVE ADDRESS
FIGURE 3-7:
CONTROL BYTE
ALLOCATION
After generating a Start condition, the bus master
transmits the slave address consisting of a 7-bit device
code (1010000) for the 24LC21A.
START
READ/WRITE
The eighth bit of slave address determines whether the
master device wants to read or write to the 24LC21A
(Figure 3-7).
R/W
A
SLAVE ADDRESS
The 24LC21A monitors the bus for its corresponding
slave address continuously. It generates an
Acknowledge bit if the slave address was true and it is
not in a programming mode.
1
0
1
0
0
0
0
Operation
Slave Address
R/W
Read
Write
1010000
1010000
1
0
DS21160F-page 8
2003 Microchip Technology Inc.
24LC21A
4.2
Page Write
4.0
4.1
WRITE OPERATION
Byte Write
The write control byte, word address and the first data
byte are transmitted to the 24LC21A in the same way
as in a byte write. But instead of generating a Stop
condition the master transmits up to eight data bytes to
the 24LC21A which are temporarily stored in the on-
chip page buffer and will be written into the memory
after the master has transmitted a Stop condition. After
the receipt of each word, the three lower order address
pointer bits are internally incremented by one. The
higher order five bits of the word address remains
constant. If the master should transmit more than eight
words prior to generating the Stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the Stop condition is received an
internal write cycle will begin (Figure 4-3).
Following the start signal from the master, the slave
address (four bits), three zero bits (000) and the R/W bit
which is a logic low are placed onto the bus by the
master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will
follow after it has generated an Acknowledge bit during
the ninth clock cycle. Therefore, the next byte
transmitted by the master is the word address and will
be written into the address pointer of the 24LC21A.
After receiving another acknowledge signal from the
24LC21A the master device will transmit the data word
to be written into the addressed memory location. The
24LC21A acknowledges again and the master
generates a Stop condition. This initiates the internal
write cycle, and during this time the 24LC21A will not
generate acknowledge signals (Figure 4-1).
It is required that VCLK be held at a logic high level
during command and data transfer in order to program
the device. This applies to both byte write and page
write operation. Note, however, that the VCLK is
ignored during the self-timed program operation.
Changing VCLK from high-to-low during the self-timed
program operation will not halt programming of the
device.
It is required that VCLK be held at a logic high level
during command and data transfer in order to program
the device. This applies to both byte write and page
write operation. Note, however, that the VCLK is
ignored during the self-timed program operation.
Changing VCLK from high-to-low during the self-timed
program operation will not halt programming of the
device.
Note:
Page write operations are limited to writing
bytes within a single physical page,
regardless of the number of bytes actually
being written. Physical page boundaries
start at addresses that are integer multi-
ples of the page buffer size (or ‘page size’)
and end at addresses that are integer
multiples of [page size - 1]. If a Page Write
command attempts to write across a
physical page boundary, the result is that
the data wraps around to the beginning of
the current page (overwriting data
previously stored there), instead of being
written to the next page as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
2003 Microchip Technology Inc.
DS21160F-page 9
24LC21A
FIGURE 4-1:
BYTE WRITE
S
T
A
R
T
S
T
O
P
WORD
ADDRESS
CONTROL
BYTE
BUS ACTIVITY
MASTER
DATA
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
BUS ACTIVITY
VCLK
FIGURE 4-2:
VCLK WRITE ENABLE TIMING
SCL
THD:STA
THD:STO
SDA
IN
VCLK
TVHST
TSPVL
FIGURE 4-3:
PAGE WRITE
S
T
A
R
T
S
T
O
P
BUS ACTIVITY
MASTER
WORD
ADDRESS
CONTROL
BYTE
DATA n + 1
DATA n + 7
DATA (n)
P
SDA LINE
S
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
BUS ACTIVITY
VCLK
DS21160F-page 10
2003 Microchip Technology Inc.
24LC21A
5.0
ACKNOWLEDGE POLLING
6.0
WRITE PROTECTION
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a Write
command has been issued from the master, the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a Start condition followed by the control byte
for a Write command (R/W = 0). If the device is still
busy with the write cycle, then no ACK will be returned.
If the cycle is complete, then the device will return the
ACK and the master can then proceed with the next
Read or Write command. See Figure 5-1 for the flow
diagram.
When using the 24LC21A in the Bidirectional mode, the
VCLK pin can be used as a write-protect control pin.
Setting VCLK high allows normal write operations,
while setting VCLK low prevents writing to any location
in the array. Connecting the VCLK pin to VSS would
allow the 24LC21A to operate as a serial ROM,
although this configuration would prevent using the
device in the Transmit-only mode.
FIGURE 5-1:
ACKNOWLEDGE
POLLING FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
No
Yes
Next
Operation
2003 Microchip Technology Inc.
DS21160F-page 11
24LC21A
7.3
Sequential Read
7.0
READ OPERATION
Sequential reads are initiated in the same way as a
random read except that after the 24LC21A transmits
the first data byte, the master issues an acknowledge
as opposed to a Stop condition in a random read. This
directs the 24LC21A to transmit the next sequentially
addressed 8-bit word (Figure 7-3).
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one. There are three basic types
of read operations: current address read, random read
and sequential read.
7.1
Current Address Read
To provide sequential reads the 24LC21A contains an
internal address pointer which is incremented by one at
the completion of each operation. This address pointer
allows the entire memory contents to be serially read
during one operation.
The 24LC21A contains an address counter that
maintains the address of the last word accessed,
internally incremented by one. Therefore, if the
previous access (either a read or write operation) was
to address n, the next current address read operation
would access data from address n + 1. Upon receipt of
the slave address with R/W bit set to one, the 24LC21A
issues an acknowledge and transmits the eight bit data
word. The master will not acknowledge the transfer but
does generate a Stop condition and the 24LC21A
discontinues transmission (Figure 7-1).
7.4
Noise Protection
The 24LC21A employs a VCC threshold detector circuit
which disables the internal erase/write logic if the VCC
is below 1.5 volts at nominal conditions.
The SDA, SCL and VCLK inputs have Schmitt Trigger
and filter circuits which suppress noise spikes to assure
proper device operation even on a noisy bus.
FIGURE 7-1:
CURRENT ADDRESS
READ
S
T
A
R
T
S
T
O
P
BUS ACTIVITY
MASTER
CONTROL
BYTE
DATA n
SDA LINE
S 1 0 1
P
0 0 0 0 1
N
O
A
C
K
A
C
K
BUS ACTIVITY
7.2
Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24LC21A as part of a write operation. After the word
address is sent, the master generates a Start condition
following the acknowledge. This terminates the write
operation, but not before the internal address pointer is
set. Then the master issues the control byte again but
with the R/W bit set to a one. The 24LC21A will then
issue an acknowledge and transmits the 8-bit data
word. The master will not acknowledge the transfer but
does generate a Stop condition and the 24LC21A
discontinues transmission (Figure 7-2).
DS21160F-page 12
2003 Microchip Technology Inc.
24LC21A
FIGURE 7-2:
RANDOM READ
S
T
A
R
T
S
T
A
R
T
S
T
O
P
BUS ACTIVITY
CONTROL
BYTE
WORD
ADDRESS
CONTROL
BYTE
DATA n
MASTER
SDA LINE
S 1 0 1 0 0 0 0 0
S 1 0 1 0 0 0 0 1
P
N
O
A
C
K
A
C
K
A
C
K
BUS ACTIVITY
A
C
K
FIGURE 7-3:
SEQUENTIAL READ
BUS ACTIVITY
MASTER
S
T
DATA n+2
DATA n+X
O
DATA n
DATA n+1
CONTROL
BYTE
P
P
SDA LINE
A
C
K
A
C
K
A
C
K
A
C
K
N
O
BUS ACTIVITY
A
C
K
2003 Microchip Technology Inc.
DS21160F-page 13
24LC21A
8.0
8.1
PIN DESCRIPTIONS
SDA
This pin is used to transfer addresses and data into and
out of the device, when the device is in the Bidirectional
mode. In the Transmit-only mode, which only allows
data to be read from the device, data is also transferred
on the SDA pin. This pin is an open drain terminal,
therefore the SDA bus requires a pull-up resistor to
VCC (typical 10 KΩ for 100 kHz, 2 KΩ for 400 kHz).
For normal data transfer in the Bidirectional mode, SDA
is allowed to change only during SCL low. Changes
during SCL high are reserved for indicating the Start
and Stop conditions.
8.2
SCL
This pin is the clock input for the Bidirectional mode,
and is used to synchronize data transfer to and from the
device. It is also used as the signaling input to switch
the device from the Transmit-only mode to the
Bidirectional mode. It must remain high for the chip to
continue operation in the Transmit-only mode.
8.3
VCLK
This pin is the clock input for the Transmit-only mode
(DDC1). In the Transmit-only mode, each bit is clocked
out on the rising edge of this signal. In the Bidirectional
mode, a high logic level is required on this pin to enable
write capability.
DS21160F-page 14
2003 Microchip Technology Inc.
24LC21A
APPENDIX A: REVISION HISTORY
Revision F
Corrections to Section 1.0, Electrical Characteristics.
2003 Microchip Technology Inc.
DS21160F-page 15
24LC21A
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
/XX
XXX
Temperature
Range
Package
Pattern
Device
24LC21A
Dual Mode Serial EEPROM
24LC21AT Dual Mode Serial EEPROM (Tape and Reel)
Temperature Range Blank
I
0°C to +70°C
-40°C to +85°C
Package
P
SN
=
=
Plastic DIP (300 mil Body), 8-lead
Plastic SOIC (150 mil Body), 8-lead
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
DS21160F-page 16
2003 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical com-
ponents in life support systems is not authorized except with
express written approval by Microchip. No licenses are con-
veyed, implicitly or otherwise, under any intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE and PowerSmart are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER,
SEEVAL and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Application Maestro, dsPICDEM, dsPICDEM.net, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo,
PowerMate, PowerTool, rfLAB, rfPIC, Select Mode,
SmartSensor, SmartShunt, SmartTel and Total Endurance are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2003, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of development
systems is ISO 9001 certified.
2003 Microchip Technology Inc.
DS21160F-page 17
WORLDWIDE SALES AND SERVICE
Korea
AMERICAS
ASIA/PACIFIC
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Samsung-Dong, Kangnam-Ku
Seoul, Korea 135-882
Tel: 82-2-554-7200 Fax: 82-2-558-5932 or
82-2-558-5934
Corporate Office
Australia
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Tel: 480-792-7200
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Australia
Fax: 480-792-7277
Technical Support: 480-792-7627
Web Address: http://www.microchip.com
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
Singapore
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Tel: 65-6334-8870 Fax: 65-6334-8850
China - Beijing
Unit 915
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Netherlands
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India
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Tel: 81-45-471- 6166 Fax: 81-45-471-6122
07/28/03
DS21160F-page 18
2003 Microchip Technology Inc.
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