24LC1025T-I/P [MICROCHIP]
1024K I2C⑩ CMOS Serial EEPROM; 1024K I2C ？ CMOS串行EEPROM
| 型号： | 24LC1025T-I/P |
| 厂家： | 
MICROCHIP |
| 描述： | 1024K I2C⑩ CMOS Serial EEPROM |
| 文件： | 总22页 (文件大小：351K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
24AA1025/24LC1025/24FC1025
1024K I2C™ CMOS Serial EEPROM
This device is capable of both random and sequential
Device Selection Table:
reads. Reads may be sequential within address bound-
aries 0000h to FFFFh and 10000h to 1FFFFh.
Functional address lines allow up to four devices on the
same data bus. This allows for up to 4 Mbits total
system EEPROM memory. This device is available in
the standard 8-pin PDIP and SOIJ packages.
Part
Number
VCC
Range
Max. Clock
Frequency
Temp
Ranges
24AA1025
24LC1025
24FC1025
1.7-5.5V
2.5-5.5V
2.5-5.5V
400 kHz†
400 kHz*
1 MHz
I
I, E
I
†100 kHz for VCC < 2.5V.
*100 kHz for VCC < 4.5V, E-temp.
Package Type
PDIP
A0
1
8
VCC
Features:
A1
A2
2
3
4
7
6
5
WP
• Single supply with operation down to 1.7V for
24AAXX devices, 2.5V for 24LCXX devices
SCL
SDA
• Low-power CMOS technology:
- Read current 1 mA, typical
VSS
- Standby current 100 nA, typical
• 2-wire serial interface, I2C™ compatible
• Cascadable up to four devices
• Schmitt Trigger inputs for noise suppression
• Output slope control to eliminate ground bounce
• 100 kHz and 400 kHz clock compatibility
• 1 MHz clock for FC versions
SOIJ
1
2
8
7
A0
VCC
A1
A2
WP
3
4
6
5
SCL
SDA
VSS
• Page write time 3 ms, typical
• Self-timed erase/write cycle
Block Diagram
• 128-byte page write buffer
• Hardware write-protect
A0 A1 WP
HV Generator
• ESD protection >400V
• More than 1 million erase/write cycles
• Data retention >200 years
I/O
Control
Logic
Memory
Control
Logic
EEPROM
Array
XDEC
• Factory programming available
• Packages include 8-lead PDIP, SOIJ
• Pb-free and RoHS compliant
• Temperature ranges:
Page Latches
I/O
SCL
YDEC
- Industrial (I): -40°C to +85°C
- Automotive (E):-40°C to +125°C
SDA
VCC
VSS
Description:
Sense AMP
R/W Control
The Microchip Technology Inc. 24AA1025/24LC1025/
24FC1025 (24XX1025*) is a 128K x 8 (1024K bit)
Serial Electrically Erasable PROM, capable of opera-
tion across a broad voltage range (1.8V to 5.5V). It has
been developed for advanced, low-power applications
such as personal communications or data acquisition.
This device has both byte write and page write
capability of up to 128 bytes of data.
*24XX1025 is used in this document as a generic part number
for the 24AA1025/24LC1025/24FC1025 devices.
© 2007 Microchip Technology Inc.
Preliminary
DS21941E-page 1
24AA1025/24LC1025/24FC1025
1.0
ELECTRICAL CHARACTERISTICS
(†)
Absolute Maximum Ratings
VCC.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied................................................................................................-40°C to +125°C
ESD protection on all pins ......................................................................................................................................................≥ 4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C
Automotive (E): VCC = +2.5V to 5.5VTA = -40°C to +125°C
DC CHARACTERISTICS
Param.
Sym.
No.
Characteristic
Min.
Max.
Units
Conditions
D1
A0, A1, SCL, SDA and
WP pins:
—
—
—
D2
D3
VIH
VIL
High-level input voltage
Low-level input voltage
0.7 VCC
—
—
V
0.3 VCC
0.2 VCC
V
V
VCC ≥ 2.5V
VCC < 2.5V
D4
VHYS
Hysteresis of Schmitt
Trigger inputs
0.05 VCC
—
V
VCC ≥ 2.5V (Note)
(SDA, SCL pins)
D5
D6
VOL
ILI
Low-level output voltage
Input leakage current
Output leakage current
—
—
0.40
±1
V
IOL = 3.0 mA @ VCC = 4.5V
IOL = 2.1 mA @ VCC = 2.5V
μA
VIN = VSS or VCC, WP = VSS
VIN = VSS or VCC, WP = VCC
D7
D8
ILO
—
—
±1
10
μA
VOUT = VSS or VCC
CIN,
Pin capacitance
pF
VCC = 5.0V (Note)
COUT
(all inputs/outputs)
TA = 25°C, FCLK = 1 MHz
D9
ICC Read Operating current
ICC Write
—
—
—
450
5
μA
mA
μA
VCC = 5.5V, SCL = 400 kHz
VCC = 5.5V
D10
ICCS
Standby current
5
TA = -40°C to 85°C
SCL = SDA = VCC = 5.5V
A0, A1, WP = VSS, A2 = VCC
Note:
This parameter is periodically sampled and not 100% tested.
DS21941E-page 2
Preliminary
© 2007 Microchip Technology Inc.
24AA1025/24LC1025/24FC1025
TABLE 1-2:
AC CHARACTERISTICS
Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C
Automotive (E): VCC = +2.5V to 5.5V TA = -40°C to +125°C
AC CHARACTERISTICS
Param.
Sym.
No.
Characteristic
Clock frequency
Min.
Max.
Units
Conditions
1.7V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V (Note 5)
2.5V ≤ VCC ≤ 5.5V (24FC1025 only)
1
2
3
4
FCLK
THIGH
TLOW
TR
—
—
—
100
400
1000
kHz
Clock high time
Clock low time
4000
600
500
—
—
—
ns
ns
ns
1.7V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (24FC1025 only)
4700
1300
500
—
—
—
1.7V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (24FC1025 only)
SDA and SCL rise time
(Note 1)
—
—
—
1000
300
300
1.7V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (24FC1025 only)
5
6
TF
SDA and SCL fall time
(Note 1)
—
—
300
100
ns
ns
All except, 24FC1025
2.5V ≤ VCC ≤ 5.5V (24FC1025 only)
THD:STA Start condition hold time
4000
600
250
—
—
—
1.7V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (24FC1025 only)
7
TSU:STA Start condition setup time
4700
600
250
—
—
—
ns
1.7V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (24FC1025 only)
8
9
THD:DAT Data input hold time
TSU:DAT Data input setup time
0
—
ns
ns
(Note 2)
250
100
100
—
—
—
1.7V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (24FC1025 only)
10
11
12
13
14
15
16
TSU:STO Stop condition setup time
TSU:WP WP setup time
4000
600
250
—
—
—
ns
ns
ns
ns
ns
ns
ns
1.7V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (24FC1025 only)
4000
600
600
—
—
—
1.7V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (24FC1025 only)
THD:WP WP hold time
4700
1300
1300
—
—
—
1.7V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (24FC1025 only)
TAA
Output valid from clock
—
—
—
3500
900
400
1.7V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (24FC1025 only)
(Note 2)
TBUF
TOF
TSP
Bus free time: Time the bus
must be free before a new
transmission can start
4700
1300
500
—
—
—
1.7V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (24FC1025 only)
Output fall time from VIH
minimum to VIL maximum
CB ≤ 100 pF
10 + 0.1CB
250
250
All except, 24FC1025 (Note 1)
24FC1025 (Note 1)
Input filter spike suppression
(SDA and SCL pins)
—
50
All except, 24FC1025 (Notes 1 and 3)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum
300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise spike
suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but established by characterization. For endurance estimates in a specific application,
please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com.
5: Max. clock frequency is 100 kHz for E-temp devices <4.5V. 1.7-2.5V (100 kHz) timings must be used.
© 2007 Microchip Technology Inc.
Preliminary
DS21941E-page 3
24AA1025/24LC1025/24FC1025
Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C
Automotive (E): VCC = +2.5V to 5.5V TA = -40°C to +125°C
AC CHARACTERISTICS (Continued)
Param.
Sym.
Characteristic
Min.
Max.
Units
Conditions
No.
17
18
TWC
Write cycle time (byte or page)
Endurance
—
5
ms
3 ms, typical
1 M
—
cycles 25°C (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum
300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise spike
suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but established by characterization. For endurance estimates in a specific application,
please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com.
5: Max. clock frequency is 100 kHz for E-temp devices <4.5V. 1.7-2.5V (100 kHz) timings must be used.
FIGURE 1-1:
BUS TIMING DATA
5
4
D4
2
SCL
7
3
10
8
9
SDA
IN
6
16
14
12
13
SDA
OUT
(protected)
WP
11
(unprotected)
DS21941E-page 4
Preliminary
© 2007 Microchip Technology Inc.
24AA1025/24LC1025/24FC1025
2.4
Serial Clock (SCL)
2.0
PIN DESCRIPTIONS
This input is used to synchronize the data transfer from
and to the device.
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
PIN FUNCTION TABLE
2.5
Write-Protect (WP)
Name PDIP SOIJ
Function
This pin must be connected to either VSS or VCC. If tied
to VSS, write operations are enabled. If tied to VCC,
write operations are inhibited, but read operations are
not affected.
A0
A1
A2
1
2
3
1
2
3
User Configurable Chip Select
User Configurable Chip Select
Non-Configurable Chip Select.
This pin must be hard-wired to
logical 1 state (VCC). Device
will not operate with this pin
left floating or held to logical 0
(VSS).
3.0
FUNCTIONAL DESCRIPTION
The 24XX1025 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter and a device
receiving data, as a receiver. The bus must be
controlled by a master device which generates the
Serial Clock (SCL), controls the bus access, and
generates the Start and Stop conditions while the
24XX1025 works as a slave. Both master and slave
can operate as a transmitter or receiver, but the master
device determines which mode is activated.
VSS
SDA
SCL
WP
4
5
6
7
8
4
5
6
7
8
Ground
Serial Data
Serial Clock
Write-Protect Input
VCC
+1.7 to 5.5V (24AA1025)
+2.5 to 5.5V (24LC1025)
+2.5 to 5.5V (24FC1025)
2.1
A0, A1 Chip Address Inputs
The A0, A1 inputs are used by the 24XX1025 for multi-
ple device operations. The levels on these inputs are
compared with the corresponding bits in the slave
address. The chip is selected if the comparison is true.
Up to four devices may be connected to the same bus
by using different Chip Select bit combinations. In most
applications, the chip address inputs A0 and A1 are
hard-wired to logic ‘0’ or logic ‘1’. For applications in
which these pins are controlled by a microcontroller or
other programmable device, the chip address pins
must be driven to logic ‘0’ or logic ‘1’ before normal
device operation can proceed.
2.2
A2 Chip Address Input
The A2 input is non-configurable Chip Select. This pin
must be tied to VCC in order for this device to operate.
2.3
Serial Data (SDA)
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open-
drain terminal, therefore, the SDA bus requires a pull-
up resistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for
400 kHz and 1 MHz).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
© 2007 Microchip Technology Inc.
Preliminary
DS21941E-page 5
24AA1025/24LC1025/24FC1025
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
4.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
4.5
Acknowledge
Accordingly, the following bus conditions have been
defined (Figure 4-1).
Each receiving device, when addressed, is obliged to
generate an Acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse which is associated with this Acknowledge
bit.
4.1
Bus Not Busy (A)
Both data and clock lines remain high.
Note:
The 24XX1025 does not generate any
Acknowledge bits if an internal program-
ming cycle is in progress, however, the
control byte that is being polled must
match the control byte used to initiate the
write cycle.
4.2
Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
A device that acknowledges must pull-down the SDA
line during the Acknowledge clock pulse in such a way
that the SDA line is stable low during the high period of
the acknowledge related clock pulse. Of course, setup
and hold times must be taken into account. During
reads, a master must signal an end of data to the slave
by NOT generating an Acknowledge bit on the last byte
that has been clocked out of the slave. In this case, the
slave (24XX1025) will leave the data line high to enable
the master to generate the Stop condition.
4.3
Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must end with a Stop condition.
4.4
Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
FIGURE 4-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)
(B)
(D)
(D)
(C) (A)
SCL
SDA
Start
Condition
Address or
Acknowledge
Valid
Data
Allowed
To Change
Stop
Condition
FIGURE 4-2:
ACKNOWLEDGE TIMING
Acknowledge
Bit
1
2
3
4
5
6
7
8
9
1
2
3
SCL
SDA
Data from transmitter
Data from transmitter
Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
Receiver must release the SDA line at this point
so the Transmitter can continue sending data.
DS21941E-page 6
Preliminary
© 2007 Microchip Technology Inc.
24AA1025/24LC1025/24FC1025
FIGURE 5-1:
CONTROL BYTE
FORMAT
5.0
DEVICE ADDRESSING
A control byte is the first byte received following the
Start condition from the master device (Figure 5-1).
The control byte consists of a 4-bit control code; for the
24XX1025, this is set as ‘1010’ binary for read and
write operations. The next bit of the control byte is the
block select bit (B0). This bit acts as the A16 address
bit for accessing the entire array. The next two bits of
the control byte are the Chip Select bits (A1, A0). The
Chip Select bits allow the use of up to four 24XX1025
devices on the same bus and are used to select which
device is accessed. The Chip Select bits in the control
byte must correspond to the logic levels on the corre-
sponding A1 and A0 pins for the device to respond.
These bits are in effect the two Most Significant bits of
the word address.
Read/Write Bit
Block
Select
Bits
Chip
Select
Bits
Control Code
S
1
0
1
0
B0 A1 A0 R/W ACK
Slave Address
Start Bit
Acknowledge Bit
5.1
Contiguous Addressing Across
Multiple Devices
The last bit of the control byte defines the operation to
be performed. When set to a one, a read operation is
selected, and when set to a zero, a write operation is
selected. The next two bytes received define the
address of the first data byte (Figure 5-2). The upper
address bits are transferred first, followed by the Less
Significant bits.
The Chip Select bits A1, A0 can be used to expand the
contiguous address space for up to 4 Mbit by adding up
to four 24XX1025’s on the same bus. In this case,
software can use A0 of the control byte as address bit
A16 and A1 as address bit A17. It is not possible to
sequentially read across device boundaries.
Each device has internal addressing boundary
limitations. This divides each part into two segments of
512K bits. The block select bit ‘B0’ controls access to
each “half”.
Following the Start condition, the 24XX1025 monitors
the SDA bus checking the device type identifier being
transmitted. Upon receiving a ‘1010’ code and appro-
priate device select bits, the slave device outputs an
Acknowledge signal on the SDA line. Depending on the
state of the R/W bit, the 24XX1025 will select a read or
write operation.
Sequential read operations are limited to 512K blocks.
To read through four devices on the same bus, eight
random Read commands must be given.
This device has an internal addressing boundary
limitation that is divided into two segments of 512K bits.
Block select bit ‘B0’ to control access to each segment.
FIGURE 5-2:
ADDRESS SEQUENCE BIT ASSIGNMENTS
Control Byte
Address High Byte
Address Low Byte
A
A
A
A
B
0
A
1
A
0
A
A
10
A
9
A
8
A
7
A
0
•
•
•
•
•
•
1
0
1
0
R/W
12 11
15 14 13
Block
Select
Bit
Chip
Select
Bits
Control
Code
X = “don’t care” bit
© 2007 Microchip Technology Inc.
Preliminary
DS21941E-page 7
24AA1025/24LC1025/24FC1025
6.3
Write Protection
6.0
6.1
WRITE OPERATIONS
Byte Write
The WP pin allows the user to write-protect the entire
array (00000-1FFFF) when the pin is tied to VCC. If tied
to VSS the write protection is disabled. The WP pin is
sampled at the Stop bit for every Write command
(Figure 1-1). Toggling the WP pin after the Stop bit will
have no effect on the execution of the write cycle.
Following the Start condition from the master, the
control code (four bits), the block select (one bit), the
Chip Select (two bits), and the R/W bit (which is a logic
low) are clocked onto the bus by the master transmitter.
This indicates to the addressed slave receiver that the
address high byte will follow after it has generated an
Acknowledge bit during the ninth clock cycle. There-
fore, the next byte transmitted by the master is the
high-order byte of the word address and will be written
into the Address Pointer of the 24XX1025. The next
byte is the Least Significant Address Byte. After receiv-
ing another Acknowledge signal from the 24XX1025,
the master device will transmit the data word to be writ-
ten into the addressed memory location. The
24XX1025 acknowledges again and the master gener-
ates a Stop condition. This initiates the internal write
cycle and during this time, the 24XX1025 will not gen-
erate Acknowledge signals as long as the control byte
being polled matches the control byte that was used to
initiate the write (Figure 6-1). If an attempt is made to
write to the array with the WP pin held high, the device
will acknowledge the command, but no write cycle will
occur, no data will be written and the device will
immediately accept a new command. After a byte Write
command, the internal address counter will point to the
address location following the one that was just written.
Note:
Page write operations are limited to writing
bytes within a single physical page,
regardless of the number of bytes actually
being written. Physical page boundaries
start at addresses that are integer
multiples of the page buffer size (or ‘page
size’) and end at addresses that are
integer multiples of [page size – 1]. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page as might be
expected. It is therefore, necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
6.2
Page Write
The write control byte, word address and the first data
byte are transmitted to the 24XX1025 in the same way
as in a byte write. But instead of generating a Stop
condition, the master transmits up to 127 additional
bytes, which are temporarily stored in the on-chip page
buffer and will be written into memory after the master
has transmitted a Stop condition. After receipt of each
word, the seven lower Address Pointer bits are inter-
nally incremented by one. If the master should transmit
more than 128 bytes prior to generating the Stop con-
dition, the address counter will roll over and the previ-
ously received data will be overwritten. As with the byte
write operation, once the Stop condition is received, an
internal write cycle will begin (Figure 6-2). If an attempt
is made to write to the array with the WP pin held high,
the device will acknowledge the command, but no write
cycle will occur, no data will be written and the device
will immediately accept a new command.
DS21941E-page 8
Preliminary
© 2007 Microchip Technology Inc.
24AA1025/24LC1025/24FC1025
FIGURE 6-1:
BYTE WRITE
S
T
A
R
T
BUS ACTIVITY
MASTER
S
T
O
P
Control
Byte
Address
High Byte
Address
Low Byte
Data
B A A
SDA LINE
S 1 0 1 0
0
P
0 1 0
A
C
K
A
C
K
A
C
K
A
C
K
BUS ACTIVITY
X = “don’t care” bit
FIGURE 6-2:
PAGE WRITE
S
T
A
R
T
S
T
O
P
Control
Byte
Address
High Byte
Address
Low Byte
BUS ACTIVITY
MASTER
Data Byte 0
Data Byte 127
B A A
SDA LINE
P
S 1 0 1 0
0
0 1 0
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
BUS ACTIVITY
X = “don’t care” bit
© 2007 Microchip Technology Inc.
Preliminary
DS21941E-page 9
24AA1025/24LC1025/24FC1025
FIGURE 7-1:
ACKNOWLEDGE
POLLING FLOW
7.0
ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete. (This feature can be used to maximize bus
throughput.) Once the Stop condition for a Write
command has been issued from the master, the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a Start condition, followed by the control byte
for a Write command (R/W = 0). If the device is still
busy with the write cycle, then no ACK will be returned.
If no ACK is returned, then the Start bit and control byte
must be resent. If the cycle is complete, then the device
will return the ACK and the master can then proceed
with the next Read or Write command. See Figure 7-1
for flow diagram.
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Note:
Care must be taken when polling the
24XX1025. The control byte that was used
to initiate the write needs to match the
control byte used for polling.
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
No
Yes
Next
Operation
DS21941E-page 10
Preliminary
© 2007 Microchip Technology Inc.
24AA1025/24LC1025/24FC1025
8.2
Random Read
8.0
READ OPERATION
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24XX1025 as part of a write operation (R/W bit set to
0). After the word address is sent, the master gener-
ates a Start condition following the acknowledge. This
terminates the write operation, but not before the inter-
nal Address Pointer is set. Then, the master issues the
control byte again, but with the R/W bit set to a one.
The 24XX1025 will then issue an acknowledge and
transmit the 8-bit data word. The master will not
acknowledge the transfer, but does generate a Stop
condition which causes the 24XX1025 to discontinue
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
control byte is set to one. There are three basic types
of read operations: current address read, random read,
and sequential read.
8.1
Current Address Read
The 24XX1025 contains an address counter that main-
tains the address of the last word accessed, internally
incremented by one. Therefore, if the previous read
access was to address n (n is any legal address), the
next current address read operation would access data
from address n + 1.
transmission (Figure 8-2). After
command, the internal address counter will point to the
address location following the one that was just read.
a random Read
Upon receipt of the control byte with R/W bit set to one,
the 24XX1025 issues an acknowledge and transmits
the 8-bit data word. The master will not acknowledge
the transfer, but does generate a Stop condition and the
24XX1025 discontinues transmission (Figure 8-1).
8.3
Sequential Read
Sequential reads are initiated in the same way as a
random read except that after the 24XX1025 transmits
the first data byte, the master issues an acknowledge
as opposed to the Stop condition used in a random
read. This acknowledge directs the 24XX1025 to trans-
mit the next sequentially addressed 8-bit word
(Figure 8-3). Following the final byte transmitted to the
master, the master will NOT generate an acknowledge,
but will generate a Stop condition. To provide sequen-
tial reads, the 24XX1025 contains an internal Address
Pointer which is incremented by one at the completion
of each operation. This Address Pointer allows half the
memory contents to be serially read during one opera-
tion. Sequential read address boundaries are 0000h to
FFFFh and 10000h to 1FFFFh. The internal Address
Pointer will automatically roll over from address FFFF
to address 0000 if the master acknowledges the byte
received from the array address, 1FFFF. The internal
address counter will automatically roll over from
address 1FFFFh to address 10000h if the master
acknowledges the byte received from the array
address, 1FFFFh.
FIGURE 8-1:
CURRENT ADDRESS
READ
S
T
A
R
T
S
T
O
P
BUS ACTIVITY
MASTER
Control
Byte
Data
Byte
B A A
0 1 0
SDA LINE
S 1 0 1 0
1
P
A
C
K
N
O
BUS ACTIVITY
A
C
K
© 2007 Microchip Technology Inc.
Preliminary
DS21941E-page 11
24AA1025/24LC1025/24FC1025
FIGURE 8-2:
RANDOM READ
S
T
A
R
T
S
T
A
R
T
BUS ACTIVITY
MASTER
S
T
O
P
Control
Byte
Address
Address
Control
Byte
Data
Byte
High Byte
Low Byte
B A A
0 1 0
B A A
0 1 0
SDA LINE
S 1 0 1 0
0
S 1 0 1 0
1
P
N
O
A
C
K
A
C
K
A
C
K
A
C
K
BUS ACTIVITY
A
C
K
FIGURE 8-3:
SEQUENTIAL READ
S
T
O
P
Control
BUS ACTIVITY
MASTER
Byte
Data n
Data n + 1
Data n + X
Data n + 2
P
SDA LINE
A
C
K
A
C
K
A
C
K
A
C
K
N
O
BUS ACTIVITY
A
C
K
DS21941E-page 12
Preliminary
© 2007 Microchip Technology Inc.
24AA1025/24LC1025/24FC1025
9.0
9.1
PACKAGING INFORMATION
Package Marking Information
8-Lead PDIP (300 mil)
Example:
XXXXXXXX
TXXXXNNN
24LC1025
I/P 13F
e
3
YYWW
0601
8-Lead SOIJ (5.28 mm)
Example
:
24LC1025
I/SM
0510 13F
XXXXXXXX
TXXXXXXX
YYWWNNN
e
3
Legend: XX...X Part number or part number code
T
Temperature (I, E)
Y
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code (2 characters for small packages)
Pb-free JEDEC designator for Matte Tin (Sn)
YY
WW
NNN
e
3
Note:
For very small packages with no room for the Pb-free JEDEC designator
, the marking will only appear on the outer carton or reel label.
e
3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
*
Standard marking consists of Microchip part number, year code, week code, traceability code (facility
code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please
check with your Microchip Sales Office.
© 2007 Microchip Technology Inc.
Preliminary
DS21941E-page 13
24AA1025/24LC1025/24FC1025
8-Lead Plastic Dual In-Line (P or PA) – 300 mil Body [PDIP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
N
NOTE 1
E1
3
1
2
D
E
A2
A
L
A1
c
e
eB
b1
b
Units
INCHES
Dimension Limits
MIN
NOM
8
MAX
Number of Pins
Pitch
N
e
.100 BSC
–
Top to Seating Plane
A
–
.210
.195
–
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.115
.015
.290
.240
.348
.115
.008
.040
.014
–
.130
–
.310
.250
.365
.130
.010
.060
.018
–
.325
.280
.400
.150
.015
.070
.022
.430
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
b1
b
Lower Lead Width
Overall Row Spacing §
eB
Notes:
1. Pin 1 visual index feature may vary, but must be located with the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-018B
DS21941E-page 14
Preliminary
© 2007 Microchip Technology Inc.
24AA1025/24LC1025/24FC1025
8-Lead Plastic Small Outline (SM) – Medium, 5.28 mm Body [SOIJ]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
N
E
E1
1
2
e
b
α
c
φ
A2
A
β
A1
L
Units
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
Number of Pins
Pitch
N
e
8
1.27 BSC
Overall Height
A
1.77
1.75
0.05
7.62
5.11
5.13
0.51
0°
–
–
–
–
–
–
–
–
–
–
–
–
2.03
1.98
0.25
8.26
5.38
5.33
0.76
8°
Molded Package Thickness
Standoff §
A2
A1
E
Overall Width
Molded Package Width
Overall Length
E1
D
L
Foot Length
Foot Angle
φ
c
Lead Thickness
Lead Width
0.15
0.36
–
0.25
0.51
15°
b
Mold Draft Angle Top
Mold Draft Angle Bottom
α
β
–
15°
Notes:
1. SOIJ, JEITA/EIAJ Standard, formerly called SOIC.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side.
Microchip Technology Drawing C04-056B
© 2007 Microchip Technology Inc.
Preliminary
DS21941E-page 15
24AA1025/24LC1025/24FC1025
APPENDIX A: REVISION HISTORY
Revision A
Original release.
Revision B
Section 1.0 Electrical Characteristics: revised Ambient
Temperature; Revised Table 1-1; Revised Section 2.1
and Section 2.5.
Revision C
Revised Features, Maximum Read Current and Table
1-1, D9; Revised Table 2-1, VCC; Revised Section 6.3.
Revision D (01/2007)
Revised Device Selection Table; Features Section;
Changed 1.8V to 1.7V; Revised Tables 1-1, 1-2, 2-1;
Revised Product ID System; Replaced Package
Drawings.
Revision E (03/2007)
Replaced Package Drawings (Rev. AM).
DS21941E-page 16
Preliminary
© 2007 Microchip Technology Inc.
24AA1025/24LC1025/24FC1025
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• Development Systems Information Line
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
Technical support is available through the web site
at: http://support.microchip.com
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com, click on Customer Change
Notification and follow the registration instructions.
© 2007 Microchip Technology Inc.
Preliminary
DS21941E-page 17
24AA1025/24LC1025/24FC1025
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
To:
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Reader Response
Total Pages Sent ________
RE:
From:
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Company
Address
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Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Y
N
24AA1025/24LC1025/24FC1025
DS21941E
Literature Number:
Device:
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS21941E-page 18
Preliminary
© 2007 Microchip Technology Inc.
24AA1025/24LC1025/24FC1025
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
/XX
Examples:
Temperature Package
Range
a)
b)
c)
d)
24AA1025T-I/SM: Tape and Reel, Industrial
Temperature, SOIJ package.
24LC1025-I/P: Industrial Temperature,
PDIP package.
Device:
24AA1025: = 1024K Bit 1.7V I2C CMOS Serial EEPROM
24AA1025T:= 1024K Bit 1.7V I2C CMOS Serial EEPROM
(Tape and Reel)
24LC1025-E/SM: Extended Temperature,
SOIJ package.
24LC1025: = 1024K Bit 2.5V I2C CMOS Serial EEPROM
24LC1025T:= 1024K Bit 2.5V I2C CMOS Serial EEPROM
(Tape and Reel)
24LC1025T-I/SM: Tape and Reel, Industrial
Temperature, SOIJ package.
24FC1025: = 1024K Bit 2.5V I2C CMOS Serial EEPROM
24FC1025T:= 1024K Bit 2.5V I2C CMOS Serial EEPROM
(Tape and Reel)
Temperature
Range:
I
E
=
=
-40°C to +85°C
-40°C to +125°C
Package:
P
SM
=
=
Plastic DIP (300 mil Body), 8-lead
Plastic SOIJ (5.28 mm Body), 8-lead
© 2007 Microchip Technology Inc.
Preliminary
DS21941E-page 19
24AA1025/24LC1025/24FC1025
NOTES:
DS21941E-page 20
Preliminary
© 2007 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,
PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and
SmartShunt are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
AmpLab, FilterLab, Linear Active Thermistor, Migratable
Memory, MXDEV, MXLAB, PS logo, SEEVAL, SmartSensor
and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,
MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2007, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona, Gresham, Oregon and Mountain View, California. The
Company’s quality system processes and procedures are for its PIC®
MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial
EEPROMs, microperipherals, nonvolatile memory and analog
products. In addition, Microchip’s quality system for the design and
manufacture of development systems is ISO 9001:2000 certified.
© 2007 Microchip Technology Inc.
Preliminary
DS21941E-page 21
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
Asia Pacific Office
Suites 3707-14, 37th Floor
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Technical Support:
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Web Address:
www.microchip.com
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Santa Clara, CA
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Thailand - Bangkok
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Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
China - Xian
Tel: 86-29-8833-7250
Fax: 86-29-8833-7256
12/08/06
DS21941E-page 22
Preliminary
© 2007 Microchip Technology Inc.
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24LC1026-I/SM
128K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 5.28 MM, ROHS COMPLIANT, PLASTIC, SOIJ-8
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