24LC08BE/P [MICROCHIP]
256 X 8 I2C/2-WIRE SERIAL EEPROM, PDIP8, 0.300 INCH, ROHS COMPLIANT, PLASTIC, DIP-8;
| 型号： | 24LC08BE/P |
| 厂家： | 
MICROCHIP |
| 描述： | 256 X 8 I2C/2-WIRE SERIAL EEPROM, PDIP8, 0.300 INCH, ROHS COMPLIANT, PLASTIC, DIP-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总12页 (文件大小：451K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
24LC08B/16B MODULES
M
2 ™
8K/16K I C Serial EEPROMs in ISO Micromodules
FEATURES
ISO MODULE LAYOUT
• ISO 7816 compliant contact locations
• Single supply with operation from 2.5-5.5V
• Low power CMOS technology
VSS
VDD
- 1 mA active current typical
- 10 µA standby current typical at 5.5V
• Organized as 4 or 8 blocks of 256 bytes
(4 x 256 x 8) or (8 x 256 x 8)
2
• 2-wire serial interface bus, I C compatible
• Schmitt trigger inputs for noise suppression
• Output slope control to eliminate ground bounce
• 100 kHz (2.5V) and 400kHz (5V) compatibility
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 16 bytes
• 2 ms typical write cycle time for page-write
• ESD protection > 4,000V
SCL
SDA
• 1,000,000 ERASE/WRITE cycles guaranteed
• Data retention > 200 years
BLOCK DIAGRAM
• Temperature range
HV GENERATOR
- Commercial (C):
0˚C to +70˚C
DESCRIPTION
I/O
CONTROL
LOGIC
MEMORY
CONTROL
LOGIC
EEPROM
ARRAY
XDEC
The Microchip Technology Inc. 24LC08B/16B are 8K
and 16K bit Electrically Erasable PROMs in ISO mod-
ules for smart card applications. The device is orga-
nized as four or eight blocks of 256 x 8-bit memory with
a 2-wire serial interface. The 24LC08B and 24LC16B
also have a page-write capability for up to 16 bytes of
data.
PAGE LATCHES
SDA
SCL
YDEC
VCC
VSS
SENSE AMP
R/W CONTROL
I2C is a trademark of Philips Corporation.
1997 Microchip Technology Inc.
DS21224A-page 1
24LC08B/16B MODULES
TABLE 1-1:
Name
PIN FUNCTION TABLE
Function
1.0
ELECTRICAL CHARACTERISTICS
1.1
Maximum Ratings*
VSS
SDA
SCL
VCC
Ground
Serial Data
VCC...................................................................................7.0V
All inputs and outputs w.r.t. VSS ................-0.6V to VCC +1.0V
Storage temperature ..................................... -65˚C to +150˚C
Ambient temp. with power applied................. -65˚C to +125˚C
Soldering temperature of leads (10 seconds) ............. +300˚C
ESD protection on all pins..................................................≥ 4 kV
Serial Clock
+2.5V to 5.5V Power Supply
*Notice: Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-2
DC CHARACTERISTICS
All Parameters apply across the speci- Commercial (C): Tamb = 0˚C to +70˚C, VCC = 2.5V to 5.5V
fied operating ranges unless otherwise
noted.
Parameter
SCL and SDA pins:
Symbol
Min.
Max.
Units
Conditions
High level input voltage
VIH
VIL
0.7 VCC
0.05 VCC
V
V
V
V
(Note)
(Note)
Low level input voltage
0.3 VCC
—
Hysteresis of Schmitt trigger inputs
Low level output voltage
VHYS
VOL
Vcc ≥ 2.5V (Note)
0.40
IOL = 3.0 mA, VCC = 4.5V
IOL = 2.1 mA, VCC = 2.5V
Input leakage current
ILI
-10
-10
—
10
10
10
µA
µA
pF
VIN = VCC or VSS
Output leakage current
ILO
VOUT = VCC or VSS
Pin capacitance (all inputs/outputs)
CIN,
VCC = 5.0V (Note)
COUT
Tamb = 25˚C, f = 1 MHz
Operating current
ICC Write
ICC Read
ICCS
—
—
—
3
1
mA
mA
µA
VCC = 5.5V, SCL = 400 kHz
VCC = 5.5V, SCL = 400 kHz
VCC = 5.5V, SDA = SCL = VCC
Standby current
100
Note: This parameter is periodically sampled and not 100% tested.
DS21224A-page 2
1997 Microchip Technology Inc.
24LC08B/16B MODULES
TABLE 1-3
AC CHARACTERISTICS
All parameters apply across the specified operat- Vcc = 2.5V to 5.5V
ing ranges unless otherwise noted.
Commercial (C):
Tamb = 0°C to +70°C
Vcc = 2.5V - 5.5V Vcc = 4.5V - 5.5V
STD MODE
FAST MODE
Parameter
Symbol
Units
Remarks
Min.
Max.
Min.
Max.
Clock frequency
FCLK
THIGH
TLOW
TR
—
4000
4700
—
100
—
—
600
1300
—
400
—
kHz
ns
Clock high time
Clock low time
—
—
ns
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
1000
300
—
300
300
—
ns
(Note 1)
(Note 1)
TF
—
—
ns
THD:STA
4000
600
ns
After this period the first
clock pulse is generated
START condition setup time TSU:STA
4700
—
600
—
ns
Only relevant for repeated
START condition
Data input hold time
Data input setup time
STOP condition setup time
Output valid from clock
Bus free time
THD:DAT
TSU:DAT
TSU:STO
TAA
0
—
—
0
—
—
ns
ns
ns
ns
ns
(Note 2)
250
4000
—
100
600
—
—
—
3500
—
900
—
(Note 2)
TBUF
4700
1300
Time the bus must be free
before a new transmission
can start
Output fall time from VIH
minimum to VIL maximum
TOF
TSP
TWC
—
—
250
50
20 +0.1
250
50
ns
ns
(Note 1), C ≤ 100 pF
B
C
B
Input filter spike suppression
(SDA and SCL pins)
—
(Notes 1, 3)
Write cycle time
Endurance
—
10
—
—
10
—
ms Byte or Page mode
1M
1M
cycles 25°C, VCC = 5.0V, Block
Mode (Note 4)
Note 1: Not 100% tested. C = total capacitance of one bus line in pF.
B
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined TSP and VHYS specifications are due to Schmitt trigger inputs which provide improved noise
spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific
application, please consult the Total Endurance Model which can be obtained on our BBS or website.
FIGURE 1-1: BUS TIMING DATA
TR
TF
THIGH
TLOW
SCL
TSU:STA
THD:DAT
TSU:DAT
TSU:STO
THD:STA
SDA
IN
TSP
TBUF
TAA
TAA
THD:STA
SDA
OUT
1997 Microchip Technology Inc.
DS21224A-page 3
24LC08B/16B MODULES
2.0
PAD DESCRIPTIONS
4.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
2.1
SDA (Serial Data)
• Data transfer may be initiated only when the bus
is not busy.
This is a Bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pull-up
resistor to VCC (typical 10Ω).
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP condi-
tions.
Accordingly, the following bus conditions have been
defined (Figure 5-2).
4.1
Bus not Busy (A)
2.2
SCL (Serial Clock)
Both data and clock lines remain HIGH.
This input is used to synchronize the data transfer from
and to the device.
4.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition.
All commands must be preceded by a START condi-
tion.
3.0
FUNCTIONAL DESCRIPTION
The 24LC08B/16B supports a Bi-directional 2-wire bus
and data transmission protocol. A device that sends
data onto the bus is defined as transmitter, and a
device receiving data as receiver. The bus has to be
controlled by a master device which generates the
serial clock (SCL), controls the bus access, and gener-
ates the START and STOP conditions, while the
24LC08B/16B works as slave. Both, master and slave
can operate as transmitter or receiver but the master
device determines which mode is activated.
4.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
4.4
Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last 16
will be stored when doing a write operation. When an
overwrite does occur it will replace data in a first in first
out fashion.
DS21224A-page 4
1997 Microchip Technology Inc.
24LC08B/16B MODULES
4.5
Acknowledge
5.0
DEVICE ADDRESSING
A control byte is the first byte received following the
start condition from the master device.The control byte
consists of a 4-bit control code, for the 24LC08B/16B
this is set as 1010 binary for read and write operations.
The next three bits of the control byte are the block
select bits (B2, B1, B0). They are used by the master
device to select which of the eight 256 word blocks of
memory are to be accessed.These bits are in effect the
three most significant bits of the word address.
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
Note: The 24LC08B/16B does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.
The device that acknowledges, has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end of
data to the slave by NOT generating an acknowledge
bit on the last byte that has been clocked out of the
slave. In this case, the slave (24LC08B/16B) will leave
the data line HIGH to enable the master to generate the
STOP condition.
The last bit of the control byte defines the operation to
be performed. When set to one a read operation is
selected, when set to zero a write operation is selected.
Following the start condition, the 24LC08B/16B moni-
tors the SDA bus checking the device type identifier
being transmitted, upon a 1010 code the slave device
outputs an acknowledge signal on the SDA line.
Depending on the state of the R/W bit, the 24LC08B/
16B will select a read or write operation.
Control
Code
Operation
Block Select
R/W
Read
Write
1010
1010
Block Address
Block Address
1
0
FIGURE 5-1: CONTROL BYTE
ALLOCATION
START
READ/WRITE
SLAVE ADDRESS
R/W
A
1
0
1
0
B2
B1
B0
FIGURE 5-2: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)
(B)
(D)
(D)
(C)
(A)
SCL
SDA
START
CONDITION
STOP
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
1997 Microchip Technology Inc.
DS21224A-page 5
24LC08B/16B MODULES
6.2
Page Write
6.0
WRITE OPERATIONS
The write control byte, word address and the first data
byte are transmitted to the 24LC08B/16B in the same
way as in a byte write. But instead of generating a stop
condition the master transmits up to 16 data bytes to
the 24LC08B/16B which are temporarily stored in the
on-chip page buffer and will be written into the memory
after the master has transmitted a stop condition. After
the receipt of each word, the four lower order address
pointer bits are internally incremented by one. The
higher order seven bits of the word address remains
constant. If the master should transmit more than 16
words prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an inter-
nal write cycle will begin (Figure 6-2).
6.1
Byte Write
Following the start condition from the master, the
device code (4 bits), the block address (3 bits), and the
R/W bit which is a logic low is placed onto the bus by
the master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will follow
after it has generated an acknowledge bit during the
ninth clock cycle.Therefore the next byte transmitted by
the master is the word address and will be written into
the address pointer of the 24LC08B/16B. After receiv-
ing another acknowledge signal from the 24LC08B/16B
the master device will transmit the data word to be writ-
ten into the addressed memory location.The 24LC08B/
16B acknowledges again and the master generates a
stop condition. This initiates the internal write cycle,
and during this time the 24LC08B/16B will not generate
acknowledge signals (Figure 6-1).
FIGURE 6-1: BYTE WRITE
S
T
A
R
T
S
BUS ACTIVITY
MASTER
CONTROL
BYTE
WORD
ADDRESS
T
DATA
O
P
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
BUS ACTIVITY
FIGURE 6-2: PAGE WRITE
S
S
T
O
P
T
BUS ACTIVITY
MASTER
A
R
T
CONTROL
BYTE
WORD
ADDRESS (n)
DATA n
DATA n + 1
DATA n + 15
S
P
SDA LINE
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
BUS ACTIVITY
DS21224A-page 6
1997 Microchip Technology Inc.
24LC08B/16B MODULES
7.0
ACKNOWLEDGE POLLING
8.0
READ OPERATIONS
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com-
mand has been issued from the master, the device ini-
tiates the internally timed write cycle. ACK polling can
be initiated immediately.This involves the master send-
ing a start condition followed by the control byte for a
write command (R/W = 0). If the device is still busy with
the write cycle, then no ACK will be returned. If the
cycle is complete, then the device will return the ACK
and the master can then proceed with the next read or
write command. See Figure 7-1 for flow diagram.
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one. There are three basic types
of read operations: current address read, random
read, and sequential read.
8.1
Current Address Read
The 24LC08B/16B contains an address counter that
maintains the address of the last word accessed, inter-
nally incremented by one. Therefore, if the previous
access (either a read or write operation) was to
address n, the next current address read operation
would access data from address n + 1. Upon receipt of
the slave address with R/W bit set to one, the
24LC08B/16B issues an acknowledge and transmits
the 8-bit data word. The master will not acknowledge
the transfer but does generate a stop condition and the
24LC08B/16B discontinues transmission (Figure 8-1).
FIGURE 7-1: ACKNOWLEDGE POLLING
FLOW
Send
Write Command
8.2
Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set.This is done by sending the word address to the
24LC08B/16B as part of a write operation. After the
word address is sent, the master generates a start con-
dition following the acknowledge. This terminates the
write operation, but not before the internal address
pointer is set. Then the master issues the control byte
again but with the R/W bit set to a one. The 24LC08B/
16B will then issue an acknowledge and transmits the
8-bit data word. The master will not acknowledge the
transfer but does generate a stop condition and the
24LC08B/16B discontinues transmission (Figure 8-2).
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
NO
8.3
Sequential Read
Acknowledge
(ACK = 0)?
Sequential reads are initiated in the same way as a ran-
dom read except that after the 24LC08B/16B transmits
the first data byte, the master issues an acknowledge
as opposed to a stop condition in a random read. This
directs the 24LC08B/16B to transmit the next sequen-
tially addressed 8 bit word (Figure 8-3).
YES
Next
Operation
To provide sequential reads the 24LC08B/16B contains
an internal address pointer which is incremented by
one at the completion of each operation. This address
pointer allows the entire memory contents to be serially
read during one operation.
8.4
Noise Protection
The 24LC08B/16B employs a VCC threshold detector
circuit which disables the internal erase/write logic if
the VCC is below 1.5 volts at nominal conditions.
The SCL and SDA inputs have Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.
1997 Microchip Technology Inc.
DS21224A-page 7
24LC08B/16B MODULES
FIGURE 8-1: CURRENT ADDRESS READ
S
T
A
R
T
S
T
O
P
BUS ACTIVITY
MASTER
CONTROL
BYTE
DATA n
SDA LINE
S
P
A
C
K
N
O
BUS ACTIVITY
A
C
K
FIGURE 8-2: RANDOM READ
S
T
A
R
T
S
T
A
R
T
S
T
O
P
BUS ACTIVITY
MASTER
CONTROL
BYTE
WORD
ADDRESS (n)
CONTROL
BYTE
DATA (n)
S
P
S
SDA LINE
A
C
K
A
C
K
A
C
K
N
O
BUS ACTIVITY
A
C
K
FIGURE 8-3: SEQUENTIAL READ
S
T
O
P
BUS ACTIVITY
MASTER
CONTROL
BYTE
DATA n
DATA n + 1
DATA n + 2
DATA n + X
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
BUS ACTIVITY
A
C
K
DS21224A-page 8
1997 Microchip Technology Inc.
24LC08B/16B MODULES
9.0
SHIPPING METHOD
The micromodules will be shipped to customers in
clear plastic trays. Each tray holds 150 modules, and
the trays can be stacked in a manner similar to shipping
die in waffle packs. A tray drawing with dimensions is
shown in Figure 9-1.
FIGURE 9-1: TRAY DIMENSIONS
9.374 [238.09]
8.145 [206.88]
ANTISTATIC
SMART CARD MODULES
1997 Microchip Technology Inc.
DS21224A-page 9
24LC08B/16B MODULES
FIGURE 9-2: MODULE DIMENSIONS
DS21224A-page 10
1997 Microchip Technology Inc.
24LC08B/16B MODULES
24LC08B/16B MODULES PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
24LC08B/16B /MT
—
Package:
MT = Micromodules in trays
Temperature
Range:
Blank = 0˚C to +70˚C
2
24LC08B
24LC16B
8K bit 2.5V I C Serial EEPROM in ISO Module
Device:
2
16K bit 2.5V I C Serial EEPROM in ISO Module
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office.
2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277.
3. The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
1997 Microchip Technology Inc.
DS21224A-page 11
M
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intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express
written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.The Microchip logo and name are registered trademarks
of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
DS21224A-page 12
1997 Microchip Technology Inc.
相关型号：
24LC08BE/ST
256 X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 4.40 MM, ROHS COMPLIANT, PLASTIC, TSSOP-8
MICROCHIP
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