24LC014H-I/SN_技术文档

24AA014H/24LC014H

1K I²C^™Serial EEPROM with Half-Array Write-Protect

Device Selection Table

Description:

Part

Number

VCC

Range

Max.

Clock

Temp.

Range

The Microchip Technology Inc. 24AA014H/24LC014H

is a 1 Kbit Serial Electrically Erasable PROM with

operation down to 1.7V. The device is organized as a

single block of 128 x 8-bit memory with a 2-wire serial

interface. Low-current design permits operation with

maximum standby and active currents of only 1 μA and

400 μA, respectively. The device has a page write

capability for up to 16 bytes of data. Functional address

lines allow the connection of up to eight 24AA014H/

24LC014H devices on the same bus for up to 8 Kbits of

contiguous EEPROM memory. The device is available

in the standard 8-pin PDIP, 8-pin SOIC (150 mil),

TSSOP, 2x3 TDFN and MSOP packages.

24AA014H 1.7V-5.5V 400 kHz⁽¹⁾

24LC014H 2.5V-5.5V 1 MHz

I

I, E

Note 1: 100 kHz for VCC < 1.8V

Features:

• Single-Supply with Operation down to 1.7V

• Low-Power CMOS Technology:

- 400 μA active current, maximum

- 1 μA standby current, maximum (I-temp)

• Organized as a Single Block of 128 Bytes

(128 x 8)

Package Types

SOIC, TSSOP

PDIP, MSOP

• 2-Wire Serial Interface Bus, I²C™ Compatible

• Schmitt Trigger Inputs for Noise Suppression

• Output Slope Control to Eliminate Ground Bounce

• 100 kHz and 400 kHz Compatibility

A0

1

8

VCC

1

2

8

7

A0

A1

VCC

WP

A1

A2

2

3

4

7

6

5

WP

SCL

SDA

3

4

6

5

A2

SCL

SDA

VSS

• 1 MHz Compatibility (LC)

VSS

• Page Write Buffer for up to 16 Bytes

TDFN

• Self-Timed Write Cycle (including Auto-Erase)

• Hardware Write Protection for Half Array

(40h-7Fh)

1

VCC

WP

A0

8

7

6

5

A1

2

3

4

• Address Lines Allow up to Eight Devices on Bus

• 1 Million Erase/Write Cycles

SCL

SDA

A2

VSS

• ESD Protection > 4,000V

• Data Retention > 200 Years

Block Diagram

• Factory Programming (QTP) Available

• Pb-Free and RoHS Compliant

WP

A0 A1 A2

HV Generator

• 8-pin PDIP, SOIC, TSSOP, TDFN and MSOP

Packages

I/O

Control

Logic

Memory

Control

Logic

• Available for Extended Temperature Ranges:

EEPROM

Array

- Industrial (I):

-40°C to +85°C

-40°C to +125°C

XDEC

- Automotive (E):

SDA

SCL

Write-Protect

Circuitry

VCC

VSS

YDEC

Sense Amp.

R/W Control

Preliminary

DS22077B-page 1

24AA014H/24LC014H

1.0

ELECTRICAL CHARACTERISTICS

(†)

Absolute Maximum Ratings

VCC.............................................................................................................................................................................6.5V

All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied................................................................................................-40°C to +125°C

ESD protection on all pins ......................................................................................................................................................≥ 4 kV

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

TABLE 1-1:

DC CHARACTERISTICS

Electrical Characteristics:

All parameters apply across the

specified operating ranges unless

otherwise noted.

Industrial (I):

VCC = +1.7V to 5.5V

TA = -40°C to +85°C

TA = -40°C to +125°C

Automotive (E): VCC = +2.5V to 5.5V

Parameter

Symbol

Min.

Max.

Units

Conditions

SCL and SDA pins:

High-level input voltage

VIH

0.7 VCC

—

0.3 VCC

—

V

Low-level input voltage

VIL

Hysteresis of Schmitt Trigger inputs

Low-level output voltage

VHYS

VOL

0.05 VCC

—

(Note 1)

0.40

IOL = 3.0 mA, VCC = 4.5V

IOL = 2.1 mA, VCC = 2.5V

Input leakage current

ILI

—

±1

10

μΑ

μA

pF

VIN = VSS or VCC, WP = Vss

VOUT = VSS or VCC

Output leakage current

ILO

Pin capacitance (all inputs/outputs)

CIN, COUT

VCC = 5.0V (Note 1)

TA = 25°C, f = 1 MHz

Operating current

Standby current

ICC Read

ICC Write

ICCS

—

400

3

μA

mA

μA

VCC = 5.5V, SCL = 400 kHz

VCC = 5.5V

1

VCC = 5.5V, SDA = SCL = VCC

WP = VSS, A0, A1, A2 = VSS

Note 1: This parameter is periodically sampled and not 100% tested.

DS22077B-page 2

Preliminary

24AA014H/24LC014H

TABLE 1-2:

AC CHARACTERISTICS

Electrical Characteristics:

AC CHARACTERISTICS

Industrial (I):

Automotive (E):

VCC = +1.7V to 5.5V

VCC = +2.5V to 5.5V

TA = -40°C to +85°C

TA = -40°C to +125°C

Param.

Symbol

No.

Characteristic

Clock frequency

Min.

Max.

Units

Conditions

1

2

3

4

5

6

7

FCLK

THIGH

TLOW

TR

—

100

400

1000

kHz

1.7V ≤ VCC < 1.8V

1.8V ≤ VCC ≤ 5.5V

2.5V ≤ VCC ≤ 5.5V (24LC014H)

Clock high time

4000

600

500

—

ns

1.7V ≤ VCC < 1.8V

1.8V ≤ VCC ≤ 5.5V

2.5V ≤ VCC ≤ 5.5V (24LC014H)

Clock low time

4700

1300

500

—

1.7V ≤ VCC < 1.8V

1.8V ≤ VCC ≤ 5.5V

2.5V ≤ VCC ≤ 5.5V (24LC014H)

SDA and SCL rise time (Note 1)

SDA and SCL fall time (Note 1)

Start condition hold time

Start condition setup time

—

1000

300

1.7V ≤ VCC < 1.8V

1.8V ≤ VCC ≤ 5.5V

2.5V ≤ VCC ≤ 5.5V (24LC014H)

TF

—

1000

300

1.7V ≤ VCC < 1.8V

1.8V ≤ VCC ≤ 5.5V

2.5V ≤ VCC ≤ 5.5V (24LC014H)

THD:STA

TSU:STA

4000

600

250

—

1.7V ≤ VCC < 1.8V

1.8V ≤ VCC ≤ 5.5V

2.5V ≤ VCC ≤ 5.5V (24LC014H)

4700

600

250

—

1.7V ≤ VCC < 1.8V

1.8V ≤ VCC ≤ 5.5V

2.5V ≤ VCC ≤ 5.5V (24LC014H)

8

9

THD:DAT

TSU:DAT

Data input hold time

Data input setup time

0

—

ns

(Note 2)

250

100

—

1.7V ≤ VCC < 1.8V

1.8V ≤ VCC ≤ 5.5V

2.5V ≤ VCC ≤ 5.5V (24LC014H)

10

11

12

13

14

16

TSU:STO

TSU:WP

THD:WP

TAA

Stop condition setup time

WP setup time

4000

600

250

—

ns

1.7V ≤ VCC < 1.8V

1.8V ≤ VCC ≤ 5.5V

2.5V ≤ VCC ≤ 5.5V (24LC014H)

4000

600

—

1.7V ≤ VCC < 1.8V

1.8V ≤ VCC ≤ 5.5V

2.5V ≤ VCC ≤ 5.5V (24LC014H)

WP hold time

4700

600

—

1.7V ≤ VCC < 1.8V

1.8V ≤ VCC ≤ 5.5V

2.5V ≤ VCC ≤ 5.5V (24LC014H)

Output valid from clock (Note 2)

—

3500

900

400

1.7V ≤ VCC < 1.8V

1.8V ≤ VCC ≤ 5.5V

2.5V ≤ VCC ≤ 5.5V (24LC014H)

TBUF

Bus free time: Time the bus must

be free before a new transmission

can start

1300

4700

—

1.7V ≤ VCC < 1.8V

1.8V ≤ VCC ≤ 5.5V

2.5V ≤ VCC ≤ 5.5V (24LC014H)

TSP

Input filter spike suppression

(SDA and SCL pins)

—

50

ns

24AA014H

(Note 1 and Note 3)

17

18

TWC

—

Write cycle time (byte or page)

Endurance

—

5

ms

—

1M

—

cycles 25°C, VCC = 5.5V, Block mode

(Note 4)

Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum

300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved noise spike

suppression. This eliminates the need for a TI specification for standard operation.

4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please

consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com.

Preliminary

DS22077B-page 3

24AA014H/24LC014H

FIGURE 1-1:

BUS TIMING DATA

5

4

D4

2

SCL

7

3

10

8

9

SDA

In

6

16

14

12

13

SDA

Out

(protected)

WP

11

(unprotected)

DS22077B-page 4

Preliminary

24AA014H/24LC014H

2.0

PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 2-1.

TABLE 2-1:

Name

PIN FUNCTION TABLE

8-pin

SOIC

8-pin

MSOP

8-pin

Function

TDFN

PDIP

TSSOP

A0

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

User Configurable Chip Select

Ground

A1

A2

VSS

SDA

SCL

WP

VCC

Serial Data

Serial Clock

Write-Protect Input

+1.7V to 5.5V (24AA014H)

+2.5V to 5.5V (24LC014H)

2.1

SDA Serial Data

2.4

WP

This is a bidirectional pin used to transfer addresses

and data into and out of the device. It is an open drain

terminal. Therefore, the SDA bus requires a pull-up

resistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for

400 kHz).

WP is the hardware write-protect pin. It must be tied to

VCC or VSS. If tied to VCC, the hardware write protection

is enabled and will protect half of the array (40h-7Fh).

If the WP pin is tied to VSS the hardware write

protection is disabled.

For normal data transfer SDA is allowed to change only

during SCL low. Changes during SCL high are

reserved for indicating the Start and Stop conditions.

2.5

Noise Protection

The 24AA014H/24LC014H employs a VCC threshold

detector circuit that disables the internal erase/write

logic if the VCC is below 1.5 volts at nominal conditions.

2.2

SCL Serial Clock

The SCL input is used to synchronize the data transfer

to and from the device.

The SCL and SDA inputs have Schmitt Trigger and

filter circuits that suppress noise spikes to assure

proper device operation even on a noisy bus.

2.3

A0, A1, A2

The A0, A1 and A2 inputs are used by the 24AA014H/

24LC014H for multiple device operations. The levels

on these inputs are compared with the corresponding

bits in the slave address. The chip is selected if the

compare is true.

Up to eight 24AA014H/24LC014H devices may be

connected to the same bus by using different Chip

Select bit combinations. These inputs must be

connected to either VCC or VSS.

In most applications, the chip address inputs A0, A1

and A2 are hard-wired to logic ‘0’ or logic ‘1’. For

applications in which these pins are controlled by a

microcontroller or other programmable device, the chip

address pins must be driven to logic ‘0’ or logic ‘1’

before normal device operation can proceed.

Preliminary

DS22077B-page 5

24AA014H/24LC014H

4.4

Data Valid (D)

3.0

FUNCTIONAL DESCRIPTION

The state of the data line represents valid data when,

after a Start condition, the data line is stable for the

duration of the high period of the clock signal.

The 24AA014H/24LC014H supports a bidirectional,

2-wire bus and data transmission protocol. A device

that sends data onto the bus is defined as transmitter,

and a device receiving data as receiver. The bus has

to be controlled by a master device that generates the

Serial Clock (SCL), controls the bus access and gen-

erates the Start and Stop conditions while the

24AA014H/24LC014H works as slave. Both master

and slave can operate as transmitter or receiver, but

the master device determines which mode is

activated.

The data on the line must be changed during the low

period of the clock signal. There is one bit of data per

clock pulse.

Each data transfer is initiated with a Start condition and

terminated with a Stop condition. The number of the

data bytes transferred between the Start and Stop

conditions is determined by the master device and is,

theoretically, unlimited, though only the last sixteen will

be stored when doing a write operation. When an

overwrite does occur, it will replace data in a first-in

first-out fashion.

4.0

BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

4.5

Acknowledge

Each receiving device, when addressed, is required to

generate an acknowledge after the reception of each

byte. The master device must generate an extra clock

pulse which is associated with this Acknowledge bit.

• During data transfer, the data line must remain

stable whenever the clock line is high. Changes in

the data line while the clock line is high will be

interpreted as a Start or Stop condition.

Note:

The 24AA014H/24LC014H does not gen-

erate any Acknowledge bits if an internal

programming cycle is in progress.

Accordingly, the following bus conditions have been

defined (Figure 4-1).

4.1

Bus Not Busy (A)

The device that acknowledges has to pull down the

SDA line during the Acknowledge clock pulse in such a

way that the SDA line is stable low during the high

period of the acknowledge-related clock pulse. Of

course, setup and hold times must be taken into

account. A master must signal an end of data to the

slave by not generating an Acknowledge bit on the last

byte that has been clocked out of the slave. In this case,

the slave must leave the data line high to enable the

master to generate the Stop condition (Figure 4-2).

Both data and clock lines remain high.

4.2

Start Data Transfer (B)

A high-to-low transition of the SDA line while the clock

(SCL) is high determines a Start condition. All

commands must be preceded by a Start condition.

4.3

Stop Data Transfer (C)

A low-to-high transition of the SDA line while the clock

(SCL) is high determines a Stop condition. All

operations must be ended with a Stop condition.

FIGURE 4-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS CHARACTERISTICS

(A)

(B)

(C)

(D)

(C) (A)

SCL

SDA

Start

Condition

Stop

Condition

Address or

Acknowledge

Valid

Data

Allowed

to Change

DS22077B-page 6

Preliminary

24AA014H/24LC014H

FIGURE 4-2:

ACKNOWLEDGE TIMING

Acknowledge

Bit

1

2

3

4

5

6

7

8

9

1

2

3

SCL

SDA

Data from transmitter

Transmitter must release the SDA line at this point allowing

the Receiver to pull the SDA line low to acknowledge the

previous eight bits of data.

Receiver must release the SDA line at this

point so the Transmitter can continue

sending data.

Preliminary

DS22077B-page 7

24AA014H/24LC014H

FIGURE 5-1:

CONTROL BYTE FORMAT

5.0

DEVICE ADDRESSING

Read/Write Bit

A control byte is the first byte received following the

Start condition from the master device (Figure 5-1).

The control byte consists of a four-bit control code; for

the 24AA014H/24LC014H this is set as ‘1010’ binary

for read and write operations. The next three bits of the

control byte are the Chip Select bits (A2, A1, A0). The

Chip Select bits allow the use of up to eight 24AA014H/

24LC014H devices on the same bus and are used to

select which device is accessed. The Chip Select bits

in the control byte must correspond to the logic levels

on the corresponding A2, A1 and A0 pins for the device

to respond. These bits are in effect the three Most

Significant bits of the word address.

Chip Select

Control Code

Bits

S

1

0

1

0

A2 A1 A0 R/W ACK

Slave Address

Acknowledge Bit

Start Bit

5.1

Contiguous Addressing Across

Multiple Devices

The last bit of the control byte defines the operation to

be performed. When set to a ‘1’, a read operation is

selected. When set to a ‘0’, a write operation is

selected. Following the Start condition, the 24AA014H/

24LC014H monitors the SDA bus, checking the control

byte being transmitted. Upon receiving a ‘1010’ code

and appropriate Chip Select bits, the slave device

outputs an Acknowledge signal on the SDA line.

Depending on the state of the R/W bit, the 24AA014H/

24LC014H will select a read or write operation.

The Chip Select bits A2, A1 and A0 can be used to

expand the contiguous address space for up to 8K bits

by adding up to eight 24AA014H/24LC014H devices on

the same bus. In this case, software can use A0 of the

control byte as address bit A8, A1 as address bit A9,

and A2 as address bit A10. It is not possible to

sequentially read across device boundaries.

DS22077B-page 8

Preliminary

24AA014H/24LC014H

The higher order four bits of the word address remain

constant. If the master should transmit more than 16

bytes prior to generating the Stop condition, the

address counter will roll over and the previously

received data will be overwritten. As with the byte write

operation, once the Stop condition is received, an

internal write cycle will begin (Figure 6-2). If an attempt

is made to write to the protected portion of the array

when the hardware write protection has been enabled,

the device will acknowledge the command, but no data

will be written. The write cycle time must be observed

even if write protection is enabled.

6.0

6.1

WRITE OPERATIONS

Byte Write

Following the Start signal from the master, the device

code(4 bits), the Chip Select bits (3 bits) and the R/W

bit (which is a logic low) are placed onto the bus by the

master transmitter. The device will acknowledge this

control byte during the ninth clock pulse. The next byte

transmitted by the master is the word address and will

be written into the Address Pointer of the 24AA014H/

24LC014H. After receiving another Acknowledge

signal from the 24AA014H/24LC014H, the master

device will transmit the data word to be written into the

addressed memory location. The 24AA014H/

24LC014H acknowledges again and the master

generates a Stop condition. This initiates the internal

write cycle and the 24AA014H/24LC014H will not

generate Acknowledge signals during this time

(Figure 6-1). If an attempt is made to write to the

protected portion of the array when the hardware write

protection has been enabled, the device will

acknowledge the command, but no data will be written.

The write cycle time must be observed even if write

protection is enabled.

Note:

Page write operations are limited to writing

bytes within a single physical page,

regardless of the number of bytes

actually being written. Physical page

boundaries start at addresses that are

integer multiples of the page buffer size (or

‘page size’) and end at addresses that are

integer multiples of [page size – 1]. If a

Page Write command attempts to write

across a physical page boundary, the

result is that the data wraps around to the

beginning of the current page (overwriting

data previously stored there), instead of

being written to the next page, as might be

expected. It is therefore necessary that the

application software prevent page write

operations that would attempt to cross a

page boundary.

6.2

Page Write

The write-control byte, word address and the first data

byte are transmitted to the 24AA014H/24LC014H in the

same way as in a byte write. But instead of generating

a Stop condition, the master transmits up to 15

additional data bytes to the 24AA014H/24LC014H that

are temporarily stored in the on-chip page buffer and

will be written into the memory once the master has

transmitted a Stop condition. Upon receipt of each

word, the four lower order Address Pointer bits are

internally incremented by one.

6.3

Write Protection

The WP pin must be tied to VCC or VSS. If tied to VCC,

half of the array will be write-protected (40h-7Fh). If the

WP pin is tied to VSS, write operations to all address

locations are allowed.

FIGURE 6-1:

BYTE WRITE

S

T

A

R

T

S

Bus Activity

Master

Control

Byte

Word

Address

T

Data

O

P

SDA Line

S

P

A

C

K

A

C

K

A

C

K

Bus Activity

FIGURE 6-2:

PAGE WRITE

S

T

A

R

T

S

T

O

P

Bus Activity

Master

Control

Byte

Word

Address (n)

Data (n)

Data (n +1)

Data (n + 15)

SDA Line

S

P

A

C

K

A

C

K

A

C

K

A

C

K

A

C

K

Bus Activity

Preliminary

DS22077B-page 9

24AA014H/24LC014H

FIGURE 7-1:

ACKNOWLEDGE POLLING

FLOW

7.0

ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write

cycle, this can be used to determine when the cycle is

complete (this feature can be used to maximize bus

throughput). Once the Stop condition for a write

command has been issued from the master, the device

initiates the internally-timed write cycle and ACK polling

can be initiated immediately. This involves the master

sending a Start condition followed by the control byte

for a Write command (R/W = 0). If the device is still

busy with the write cycle, no ACK will be returned. If no

ACK is returned, the Start bit and control byte must be

re-sent. If the cycle is complete, the device will return

the ACK and the master can then proceed with the next

Read or Write command. See Figure 7-1 for a flow

diagram of this operation.

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

No

Yes

DS22077B-page 10

Preliminary

24AA014H/24LC014H

Once the word address is sent, the master generates a

Start condition following the acknowledge. This

terminates the write operation, but not before the

internal Address Pointer is set. The master then issues

the control byte again but with the R/W bit set to a ‘1’.

The 24AA014H/24LC014H will then issue an

acknowledge and transmits the eight-bit data word.

The master will not acknowledge the transfer, but does

8.0

READ OPERATIONS

Read operations are initiated in the same way as write

operations, with the exception that the R/W bit of the

slave address is set to ‘1’. There are three basic types

of read operations: current address read, random read

and sequential read.

generate

a Stop condition and the 24AA014H/

8.1

Current Address Read

24LC014H discontinues transmission (Figure 8-2).

After this command, the internal address counter will

point to the address location following the one that was

just read.

The 24AA014H/24LC014H contains an address coun-

ter that maintains the address of the last word

accessed, internally incremented by one. Therefore, if

the previous read access was to address n, the next

current address read operation would access data from

address n + 1. Upon receipt of the slave address with

the R/W bit set to ‘1’, the 24AA014H/24LC014H issues

an acknowledge and transmits the 8-bit data word. The

master will not acknowledge the transfer, but does

8.3

Sequential Read

Sequential reads are initiated in the same way as a

random read except that after the 24AA014H/

24LC014H transmits the first data byte, the master

issues an acknowledge as opposed to a Stop condition

in a random read. This directs the 24AA014H/

24LC014H to transmit the next sequentially addressed

8-bit word (Figure 8-3).

generate

a Stop condition and the 24AA014H/

24LC014H discontinues transmission (Figure 8-1).

8.2

Random Read

To provide sequential reads the 24AA014H/24LC014H

contains an internal Address Pointer which is

incremented by one at the completion of each

operation. This Address Pointer allows the entire

memory contents to be serially read during one

operation. The internal Address Pointer will

automatically roll over from address 07Fh to address

000h.

Random read operations allow the master to access

any memory location in a random manner. To perform

this type of read operation, the word address must first

be set. This is done by sending the word address to the

24AA014H/24LC014H as part of a write operation.

FIGURE 8-1:

CURRENT ADDRESS READ

S

T

A

R

T

S

T

O

P

Bus Activity

Master

Control

Byte

Data

SDA Line

P

S

A

C

K

N

O

A

C

Bus Activity

K

Preliminary

DS22077B-page 11

24AA014H/24LC014H

FIGURE 8-2:

RANDOM READ

S

T

S

T

A

R

T

S

T

O

P

Bus Activity

Master

Control

A

Word

Address (n)

Control

Byte

Data (n)

Byte

R

T

S

P

S

SDA Line

N

O

A

C

K

A

C

K

A

C

K

A

C

K

Bus Activity

FIGURE 8-3:

SEQUENTIAL READ

S

T

O

P

Bus Activity

Master

Control

Byte

Data (n)

Data (n + 1)

Data (n + 2)

Data (n + X)

P

SDA Line

A

C

K

A

C

K

A

C

K

A

C

K

N

O

A

C

K

Bus Activity

DS22077B-page 12

Preliminary

24AA014H/24LC014H

9.0

9.1

PACKAGING INFORMATION

Package Marking Information

8-Lead PDIP (300 mil)

Example:

24LC014H

XXXXXXXX

T/XXXNNN

I/P

e

3

12F

YYWW

0821

8-Lead SOIC (3.90 mm)

Example:

24L014HI

XXXXXXXT

e

3

XXXXYYWW

SN

0821

NNN

12F

Example:

8-Lead TSSOP

L14H

I821

12F

XXXX

TYWW

NNN

Example:

8-Lead MSOP

4L14HI

82112F

XXXXT

YWWNNN

8-Lead 2x3 TDFN

Example:

XXX

YWW

NN

AK4

821

12

Preliminary

DS22077B-page 13

24AA014H/24LC014H

1st Line Marking Codes

MSOP

Part Number

TSSOP

TDFN

I

E

—

I

E

—

I

E

—

24AA014H

24LC014H

A14A

L14H

4A14HI

4L14HI

AK1

AK4

L14A

4L14HE

AK5

Note:

T = Temperature grade (I, E)

Legend: XX...X Part number or part number code

T

Temperature (I, E)

Y

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code (2 characters for small packages)

Pb-free JEDEC designator for Matte Tin (Sn)

YY

WW

NNN

e

3

Note: For very small packages with no room for the Pb-free JEDEC designator

, the marking will only appear on the outer carton or reel label.

e

3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

Note:

Please visit www.microchip.com/Pbfree for the latest information on Pb-free conversion.

*Standard OTP marking consists of Microchip part number, year code, week code, and traceability code.

DS22077B-page 14

Preliminary

24AA014H/24LC014H

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ꢛꢗꢊꢃꢉꢜ

ꢀꢁ ꢂꢃꢄꢅꢀꢅ ꢃ!"ꢆꢇꢅꢃꢄ#ꢈ$ꢅ%ꢈꢆ&"ꢉꢈꢅ'ꢆꢊꢅ ꢆꢉꢊ(ꢅ)"&ꢅ'"!&ꢅ)ꢈꢅꢇꢋꢌꢆ&ꢈ#ꢅ*ꢃ&ꢍꢅ&ꢍꢈꢅꢍꢆ&ꢌꢍꢈ#ꢅꢆꢉꢈꢆꢁ

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1ꢐ,2ꢅ1ꢆ!ꢃꢌꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄꢁꢅꢙꢍꢈꢋꢉꢈ&ꢃꢌꢆꢇꢇꢊꢅꢈ$ꢆꢌ&ꢅ ꢆꢇ"ꢈꢅ!ꢍꢋ*ꢄꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ!ꢁ

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Preliminary

DS22077B-page 15

24AA014H/24LC014H

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ ꢕꢄꢈꢈꢆ!ꢎꢊꢈꢋꢐꢃꢆꢑ ꢛꢒꢆMꢆꢛꢄ""ꢗ#$ꢆꢓ%&ꢔꢆꢕꢕꢆꢖꢗꢅꢘꢆꢙ !ꢏ'ꢚ

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ꢝ.32 ꢝꢈ%ꢈꢉꢈꢄꢌꢈꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄ(ꢅ"!"ꢆꢇꢇꢊꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ(ꢅ%ꢋꢉꢅꢃꢄ%ꢋꢉ'ꢆ&ꢃꢋꢄꢅꢓ"ꢉꢓꢋ!ꢈ!ꢅꢋꢄꢇꢊꢁ

ꢔꢃꢌꢉꢋꢌꢍꢃꢓ ꢙꢈꢌꢍꢄꢋꢇꢋꢑꢊ ꢒꢉꢆ*ꢃꢄꢑ ,ꢕꢖꢞꢕꢘꢜ1

DS22077B-page 16

Preliminary

24AA014H/24LC014H

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ ꢕꢄꢈꢈꢆ!ꢎꢊꢈꢋꢐꢃꢆꢑ ꢛꢒꢆMꢆꢛꢄ""ꢗ#$ꢆꢓ%&ꢔꢆꢕꢕꢆꢖꢗꢅꢘꢆꢙ !ꢏ'ꢚ

ꢛꢗꢊꢃꢜ 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢓꢆꢌ4ꢆꢑꢈꢅ#ꢉꢆ*ꢃꢄꢑ!(ꢅꢓꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢔꢃꢌꢉꢋꢌꢍꢃꢓꢅꢂꢆꢌ4ꢆꢑꢃꢄꢑꢅꢐꢓꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ

ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ

Preliminary

DS22077B-page 17

24AA014H/24LC014H

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ()ꢋꢐꢆ )"ꢋꢐ*ꢆ ꢕꢄꢈꢈꢆ!ꢎꢊꢈꢋꢐꢃꢆꢑ (ꢒꢆMꢆ+%+ꢆꢕꢕꢆꢖꢗꢅꢘꢆꢙ( !ꢇꢚ

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ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ

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DS22077B-page 18

Preliminary

24AA014H/24LC014H

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ,ꢋꢌ"ꢗꢆ ꢕꢄꢈꢈꢆ!ꢎꢊꢈꢋꢐꢃꢆꢇꢄꢌ*ꢄ-ꢃꢆꢑ, ꢒꢆꢙ, !ꢇꢚ

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ꢔꢃꢌꢉꢋꢌꢍꢃꢓ ꢙꢈꢌꢍꢄꢋꢇꢋꢑꢊ ꢒꢉꢆ*ꢃꢄꢑ ,ꢕꢖꢞꢀꢀꢀ1

Preliminary

DS22077B-page 19

24AA014H/24LC014H

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢆ.ꢈꢄꢊ$ꢆꢛꢗꢆꢂꢃꢄꢅꢆꢇꢄꢌ*ꢄ-ꢃꢆꢑ,ꢛꢒꢆMꢆ/0ꢓ0ꢔ%12ꢆꢕꢕꢆꢖꢗꢅꢘꢆꢙ(ꢍ.ꢛꢚ

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DS22077B-page 20

Preliminary

24AA014H/24LC014H

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢆ.ꢈꢄꢊ$ꢆꢛꢗꢆꢂꢃꢄꢅꢆꢇꢄꢌ*ꢄ-ꢃꢆꢑ,ꢛꢒꢆMꢆ/0ꢓ0ꢔ%12ꢆꢕꢕꢆꢖꢗꢅꢘꢆꢙ(ꢍ.ꢛꢚ

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ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ

Preliminary

DS22077B-page 21

24AA014H/24LC014H

REVISION HISTORY

Revision A (03/2008)

Original release.

Revision B (09/2008)

Added new pin function table; Corrections on DC

Characteristics Table; Updated Section 2.3.

DS22077B-page 22

Preliminary

24AA014H/24LC014H

THE MICROCHIP WEB SITE

CUSTOMER SUPPORT

Microchip provides online support via our WWW site at

www.microchip.com. This web site is used as a means

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following

information:

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

• Product Support – Data sheets and errata,

application notes and sample programs, design

resources, user’s guides and hardware support

documents, latest software releases and archived

software

• Development Systems Information Line

Customers

should

contact

their

distributor,

representative or field application engineer (FAE) for

support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

• General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online discussion groups, Microchip consultant

program member listing

Technical support is available through the web site

at: http://support.microchip.com

• Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminars and events, listings of

Microchip sales offices, distributors and factory

representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a

specified product family or development tool of interest.

To register, access the Microchip web site at

www.microchip.com, click on Customer Change

Notification and follow the registration instructions.

Preliminary

DS22077B-page 23

24AA014H/24LC014H

READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-

uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation

can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

To:

Technical Publications Manager

Reader Response

Total Pages Sent ________

RE:

From:

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Company

Address

City / State / ZIP / Country

Telephone: (_______) _________ - _________

FAX: (______) _________ - _________

Application (optional):

Would you like a reply?

Y

N

24AA014H/24LC014H

DS22077B

Literature Number:

Device:

Questions:

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

DS22077B-page 24

Preliminary

24AA014H/24LC014H

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Examples:

PART NO.

Device

X

/XX

a) 24AA014H-I/P: Industrial Temperature,

1.7V, PDIP package.

Temperature Package

Range

b) 24AA014H-I/SN: Industrial Temperature,

1.7V, SOIC Package.

c) 24AA014HT-I/ST: Industrial Tempera-

ture, 1.7V, TSSOP Package, Tape and

Reel

Device:

24AA014H: 1.7V, 1 Kbit Addressable Serial EEPROM

24AA014HT: 1.7V, 1 Kbit Addressable Serial EEPROM

(Tape and Reel)

24LC014H: 2.5V, 1 Kbit Addressable Serial EEPROM

24LC014HT: 2.5V, 1 Kbit Addressable Serial EEPROM

(Tape and Reel)

a) 24LC014H-I/P: Industrial Temperature,

2.5V, PDIP Package.

Temperature Range:

Package:

I

E

=

-40°C to +85°C

-40°C to +125°C

b) 24LC014HT-E/SN: Automotive Tempera-

ture, 2.5V, SOIC Package, Tape and Reel

c) 24LC014HT-I/MS: Industrial Tempera-

ture, 2.5V, MSOP Package, Tape and

Reel.

P

SN

ST

=

Plastic DIP, (300 mil Body), 8-lead

Plastic SOIC, (3.90 mm Body)

TSSOP, (4.4 mm Body), 8-lead

MSOP, (Plastic Micro Small Outline), 8-lead

TDFN, (2x3x0.75 mm Body), 8-lead

MS

MNY⁽¹⁾

Note 1: “Y” indicates a Nickel Palladium Gold (NiPdAu) finish.

Preliminary

DS22077B-page 25

24AA014H/24LC014H

NOTES:

DS22077B-page 26

Preliminary

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,

PICSTART, rfPIC, SmartShunt and UNI/O are registered

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

FilterLab, Linear Active Thermistor, MXDEV, MXLAB,

SEEVAL, SmartSensor and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, In-Circuit Serial

Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB

Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,

32

PICDEM.net, PICtail, PIC logo, PowerCal, PowerInfo,

PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total

Endurance, WiperLock and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

Preliminary

DS22077B-page 27

WORLDWIDE SALES AND SERVICE

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

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Tel: 91-80-4182-8400

Fax: 91-80-4182-8422

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://support.microchip.com

Web Address:

www.microchip.com

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

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Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

China - Beijing

Tel: 86-10-8528-2100

Fax: 86-10-8528-2104

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Korea - Daegu

Tel: 82-53-744-4301

Fax: 82-53-744-4302

Boston

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Korea - Seoul

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

China - Nanjing

Tel: 86-25-8473-2460

Fax: 86-25-8473-2470

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Malaysia - Penang

Tel: 60-4-227-8870

Fax: 60-4-227-4068

Detroit

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Kokomo

Kokomo, IN

Tel: 765-864-8360

Fax: 765-864-8387

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

Taiwan - Hsin Chu

Tel: 886-3-572-9526

Fax: 886-3-572-6459

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Santa Clara

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

China - Xiamen

Tel: 86-592-2388138

Fax: 86-592-2388130

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

China - Xian

Tel: 86-29-8833-7252

Fax: 86-29-8833-7256

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

China - Zhuhai

Tel: 86-756-3210040

Fax: 86-756-3210049

01/02/08

DS22077B-page 28

Preliminary


型号：	24LC014H-I/SN
厂家：	MICROCHIP
描述：	1K I2C™ Serial EEPROM with Half-Array Write-Protect 1K I2C ™串行EEPROM，带有半阵列写保护存储内存集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件：	总28页 (文件大小：458K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

24LC014H-I/SN [MICROCHIP]

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