24FC512T-I/SM [MICROCHIP]
512K I2C⑩ CMOS Serial EEPROM; 512K I2C™ CMOS串行EEPROM型号: | 24FC512T-I/SM |
厂家: | MICROCHIP |
描述: | 512K I2C⑩ CMOS Serial EEPROM |
文件: | 总26页 (文件大小:476K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
24AA512/24LC512/24FC512
512K I2C™ CMOS Serial EEPROM
Device Selection Table
Description:
Part
Number
VCC
Range
Max. Clock
Frequency
Temp.
Ranges
The Microchip Technology Inc. 24AA512/24LC512/
24FC512 (24XX512*) is a 64K x 8 (512 Kbit) Serial
Electrically Erasable PROM, capable of operation
across a broad voltage range (1.8V to 5.5V). It has
been developed for advanced, low-power applications
such as personal communications and data acquisi-
tion. This device also has a page write capability of up
to 128 bytes of data. This device is capable of both
random and sequential reads up to the 512K boundary.
Functional address lines allow up to eight devices on
the same bus, for up to 4 Mbit address space. This
device is available in the standard 8-pin plastic DIP,
SOIC, DFN and 14-lead TSSOP packages.
24AA512
24LC512
24FC512
1.8-5.5V
2.5-5.5V
2.5-5.5V
400 kHz(1)
400 kHz
1 MHz
I
I, E
I
Note 1: 100 kHz for VCC < 2.5V
Features:
• Low-power CMOS technology:
- Maximum write current 5 mA at 5.5V
- Maximum read current 400 μA at 5.5V
- Standby current 100 nA, typical at 5.5V
• 2-wire serial interface bus, I2C™ compatible
• Cascadable for up to eight devices
• Self-timed erase/write cycle
Block Diagram
A0 A1 A2 WP
HV Generator
• 128-byte Page Write mode available
• 5 ms max. write cycle time
I/O
Control
Logic
Memory
Control
Logic
EEPROM
Array
XDEC
• Hardware write-protect for entire array
• Schmitt Trigger inputs for noise suppression
• 1,000,000 erase/write cycles
Page Latches
I/O
• Electrostatic discharge protection > 4000V
• Data retention > 200 years
SCL
YDEC
SDA
• 8-pin PDIP, SOIC (208 mil), and DFN packages
• 14-lead TSSOP package
VCC
VSS
• Pb-free finishes available
Sense Amp.
R/W Control
• Temperature ranges:
- Industrial (I):
-40°C to +85°C
- Automotive (E): -40°C to +125°C
Package Type
PDIP
SOIC
TSSOP
DFN
14
13
12
11
10
9
1
VCC
A0
A1
A0
1
8
VCC
1
2
3
4
A0
A1
8
7
6
5
VCC
WP
1
2
3
4
8
7
6
5
A0
A1
VCC
WP
2
3
4
5
6
7
WP
NC
NC
NC
A1
A2
2
3
7
6
WP
NC
NC
NC
A2
SCL
SDA
SCL
A2
SCL
SDA
VSS
A2
SCL
SDA
VSS
4
5
SDA
VSS
8
VSS
* 24XX512 is used in this document as a generic part number for the 24AA512/24LC512/24FC512 devices.
© 2005 Microchip Technology Inc.
DS21754G-page 1
24AA512/24LC512/24FC512
1.0
ELECTRICAL CHARACTERISTICS
(†)
Absolute Maximum Ratings
VCC.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied................................................................................................-40°C to +125°C
ESD protection on all pins ......................................................................................................................................................≥ 4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
Electrical Characteristics:
DC CHARACTERISTICS
Industrial (I):
Automotive (E): VCC = +2.5V to 5.5V
VCC = +1.8V to 5.5V
TA = -40°C to +85°C
TA = -40°C to +125°C
Param.
Sym.
No.
Characteristic
Min.
Max.
Units
Conditions
D1
—
A0, A1, A2, SCL, SDA
and WP pins:
—
—
—
—
—
D2
D3
VIH
VIL
High-level input voltage
Low-level input voltage
0.7 VCC
—
—
V
0.3 VCC
0.2 VCC
V
V
VCC ≥ 2.5V
VCC < 2.5V
D4
VHYS
Hysteresis of Schmitt
Trigger inputs
0.05 VCC
—
V
VCC ≥ 2.5V (Note)
(SDA, SCL pins)
D5
D6
VOL
ILI
Low-level output voltage
Input leakage current
Output leakage current
—
—
0.40
±1
V
IOL = 3.0 ma @ VCC = 4.5V
IOL = 2.1 ma @ VCC = 2.5V
μA
VIN = VSS or VCC, WP = VSS
VIN = VSS or VCC, WP = VCC
D7
D8
ILO
—
—
±1
10
μA
pF
VOUT = VSS or VCC
CIN,
Pin capacitance
VCC = 5.0V (Note)
COUT
(all inputs/outputs)
TA = 25°C, FCLK = 1 MHz
D9
ICC Read Operating current
ICC Write
—
—
—
400
5
μA
mA
μA
VCC = 5.5V, SCL = 400 kHz
VCC = 5.5V
D10
ICCS
Standby current
1
TA = -40°C to +85°C
SCL = SDA = VCC = 5.5V
A0, A1, A2, WP = VSS
—
5
μA
TA = -40°C to +125°C
SCL = SDA = VCC = 5.5V
A0, A1, A2, WP = VSS
Note:
This parameter is periodically sampled and not 100% tested.
DS21754G-page 2
© 2005 Microchip Technology Inc.
24AA512/24LC512/24FC512
TABLE 1-2:
AC CHARACTERISTICS
Electrical Characteristics:
AC CHARACTERISTICS
Industrial (I):
Automotive (E):
VCC = +1.8V to 5.5V
VCC = +2.5V to 5.5V
TA = -40°C to +85°C
TA = -40°C to +125°C
Param.
Sym.
No.
Characteristic
Clock frequency
Min.
Max.
Units
Conditions
FCLK
THIGH
TLOW
TR
—
—
—
100
400
1000
kHz
1.8V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V 24FC512
1
2
3
4
Clock high time
4000
600
500
—
—
—
ns
ns
ns
1.8V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V 24FC512
Clock low time
4700
1300
500
—
—
—
1.8V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V 24FC512
SDA and SCL rise time (Note 1)
SDA and SCL fall time (Note 1)
—
—
—
1000
300
300
1.8V ≤ VCC< 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V 24FC512
TF
—
—
300
100
ns
ns
All except, 24FC512
2.5V ≤ VCC ≤ 5.5V 24FC512
5
6
THD:STA Start condition hold time
TSU:STA Start condition setup time
4000
600
250
—
—
—
1.8V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V 24FC512
4700
600
250
—
—
—
ns
1.8V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V 24FC512
7
THD:DAT Data input hold time
TSU:DAT Data input setup time
0
—
ns
ns
(Note 2)
8
9
250
100
100
—
—
—
1.8V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V 24FC512
TSU:STO Stop condition setup time
TSU:WP WP setup time
4000
600
250
—
—
—
ns
ns
ns
ns
ns
1.8V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V 24FC512
10
11
12
13
14
16
4000
600
600
—
—
—
1.8V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V 24FC512
THD:WP WP hold time
4700
1300
1300
—
—
—
1.8V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V 24FC512
TAA
Output valid from clock (Note 2)
—
—
—
3500
900
400
1.8V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V 24FC512
TBUF
TSP
Bus free time: Time the bus
must be free before a new trans-
mission can start
4700
1300
500
—
—
—
1.8V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V 24FC512
Input filter spike suppression
(SDA and SCL pins)
—
50
ns
All except, 24FC512 (Notes 1 and 3)
TWC
—
Write cycle time (byte or page)
Endurance
—
5
ms
—
17
18
1,000,000
—
cycles 25°C (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum
300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise spike
suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please
consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com.
© 2005 Microchip Technology Inc.
DS21754G-page 3
24AA512/24LC512/24FC512
FIGURE 1-1:
BUS TIMING DATA
5
4
D4
2
SCL
7
3
10
8
9
SDA
IN
6
16
14
12
13
SDA
OUT
(protected)
WP
11
(unprotected)
DS21754G-page 4
© 2005 Microchip Technology Inc.
24AA512/24LC512/24FC512
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
Name
PIN FUNCTION TABLE
14-lead
TSSOP
PDIP
SOIC
DFN
Function
A0
A1
1
2
1
2
1
1
2
User Configured Chip Select
User Configured Chip Select
Not Connected
2
(NC)
A2
—
3
—
3
3, 4, 5
—
3
6
User Configured Chip Select
Ground
VSS
SDA
SCL
(NC)
WP
VCC
4
4
7
4
5
5
8
5
Serial Data
6
6
9
10, 11, 12
13
6
Serial Clock
—
7
—
7
—
7
Not Connected
Write-Protect Input
8
8
14
8
+1.8V to 5.5V (24AA512)
+2.5V to 5.5V (24LC512)
+2.5V to 5.5V (24FC512)
2.1
A0, A1 and A2 Chip Address
Inputs
2.3
Serial Clock (SCL)
This input is used to synchronize the data transfer from
and to the device.
The A0, A1 and A2 inputs are used by the 24XX512 for
multiple device operations. The logic levels on these
inputs are compared with the corresponding bits in the
slave address. The chip is selected if the compare is
true.
2.4
Write-Protect (WP)
This pin must be connected to either VSS or VCC. If tied
to VSS, write operations are enabled. If tied to VCC,
write operations are inhibited but read operations are
not affected.
Up to eight devices may be connected to the same bus
by using different Chip Select bit combinations. These
inputs must be connected to either VCC or VSS.
In most applications, the chip address inputs A0, A1
and A2 are hard-wired to logic ‘0’ or logic ‘1’. For
applications in which these pins are controlled by a
microcontroller or other programmable logic device,
the chip address pins must be driven to logic ‘0’ or logic
‘1’ before normal device operation can proceed.
3.0
FUNCTIONAL DESCRIPTION
The 24XX512 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter and a device
receiving data as a receiver. The bus must be
controlled by a master device which generates the
Serial Clock (SCL), controls the bus access and
generates the Start and Stop conditions, while the
24XX512 works as a slave. Both master and slave
can operate as a transmitter or receiver, but the
master device determines which mode is activated.
2.2
Serial Data (SDA)
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open-
drain terminal, therefore, the SDA bus requires a pull-
up resistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for
400 kHz and 1 MHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
© 2005 Microchip Technology Inc.
DS21754G-page 5
24AA512/24LC512/24FC512
4.5
Acknowledge
4.0
BUS CHARACTERISTICS
Each receiving device, when addressed, is obliged to
generate an Acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse which is associated with this Acknowledge
bit. See Figure 4-2 for acknowledge timing.
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line, while the clock line is high, will be
interpreted as a Start or Stop condition.
Note:
The 24XX512 does not generate any
Acknowledge bits if an internal programming
cycle is in progress.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
A device that acknowledges must pull down the SDA
line during the Acknowledge clock pulse in such a way
that the SDA line is stable low during the high period of
the acknowledge related clock pulse. Of course, setup
and hold times must be taken into account. During
reads, a master must signal an end of data to the slave
by NOT generating an Acknowledge bit on the last byte
that has been clocked out of the slave. In this case, the
slave (24XX512) will leave the data line high to enable
the master to generate the Stop condition.
4.1
Bus Not Busy (A)
Both data and clock lines remain high.
4.2
Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
4.3
Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must end with a Stop condition.
4.4
Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device.
DS21754G-page 6
© 2005 Microchip Technology Inc.
24AA512/24LC512/24FC512
FIGURE 4-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)
(B)
(D)
(D)
(C) (A)
SCL
SDA
Start
Condition
Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition
FIGURE 4-2:
ACKNOWLEDGE TIMING
Acknowledge
Bit
1
2
3
4
5
6
7
8
9
1
2
3
SCL
SDA
Data from transmitter
Data from transmitter
Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
Receiver must release the SDA line
at this point so the Transmitter can
continue sending data.
© 2005 Microchip Technology Inc.
DS21754G-page 7
24AA512/24LC512/24FC512
FIGURE 5-1:
CONTROL BYTE FORMAT
5.0
DEVICE ADDRESSING
A control byte is the first byte received following the
Start condition from the master device (Figure 5-1).
The control byte consists of a 4-bit control code; for the
24XX512 this is set as ‘1010’ binary for read and write
operations. The next three bits of the control byte are
the Chip Select bits (A2, A1 and A0). The Chip Select
bits allow the use of up to eight 24XX512 devices on
the same bus and are used to select which device is
accessed. The Chip Select bits in the control byte must
correspond to the logic levels on the corresponding A2,
A1 and A0 pins for the device to respond. These bits
are in effect the three Most Significant bits of the word
address.
Read/Write Bit
Chip Select
Control Code
Bits
1
S
1
0
0
A2 A1 A0 R/W ACK
Slave Address
Acknowledge Bit
Start Bit
5.1
Contiguous Addressing Across
Multiple Devices
The last bit of the control byte defines the operation to
be performed. When set to a one a read operation is
selected and when set to a zero a write operation is
selected. The next two bytes received define the
address of the first data byte (Figure 5-2). Because all
A15…A0 are used, there are no upper address bits that
are “don’t care”. The upper address bits are transferred
first, followed by the Less Significant bits.
The Chip Select bits A2, A1 and A0 can be used to
expand the contiguous address space for up to 4 Mbit
by adding up to eight 24XX512 devices on the same
bus. In this case, software can use A0 of the control
byte as address bit A16; A1 as address bit A17; and A2
as address bit A18. It is not possible to sequentially
read across device boundaries.
Following the Start condition, the 24XX512 monitors
the SDA bus checking the device type identifier being
transmitted. Upon receiving a ‘1010’ code and appro-
priate device select bits, the slave device outputs an
Acknowledge signal on the SDA line. Depending on the
state of the R/W bit, the 24XX512 will select a read or
write operation.
FIGURE 5-2:
ADDRESS SEQUENCE BIT ASSIGNMENTS
Address High Byte
Control Byte
Address Low Byte
A
A
A
A
A
2
A
1
A
0
A
A
10
A
9
A
8
A
7
A
0
•
•
•
•
•
•
1
0
1
0
R/W
12 11
15 14 13
Control
Code
Chip
Select
Bits
DS21754G-page 8
© 2005 Microchip Technology Inc.
24AA512/24LC512/24FC512
6.3
Write Protection
6.0
6.1
WRITE OPERATIONS
Byte Write
The WP pin allows the user to write-protect the entire
array (0000-FFFF) when the pin is tied to VCC. If tied to
VSS the write protection is disabled. The WP pin is
sampled at the Stop bit for every Write command
(Figure 1-1). Toggling the WP pin after the Stop bit will
have no effect on the execution of the write cycle.
Following the Start condition from the master, the
control code (four bits), the Chip Select (three bits) and
the R/W bit (which is a logic low) are clocked onto the
bus by the master transmitter. This indicates to the
addressed slave receiver that the address high byte will
follow after it has generated an Acknowledge bit during
the ninth clock cycle. Therefore, the next byte
transmitted by the master is the high-order byte of the
word address and will be written into the Address
Pointer of the 24XX512. The next byte is the Least
Significant Address Byte. After receiving another
Acknowledge signal from the 24XX512, the master
device will transmit the data word to be written into the
addressed memory location. The 24XX512 acknowl-
edges again and the master generates a Stop
condition. This initiates the internal write cycle and
during this time, the 24XX512 will not generate
Acknowledge signals (Figure 6-1). If an attempt is
made to write to the array with the WP pin held high, the
device will acknowledge the command, but no write
cycle will occur, no data will be written and the device
will immediately accept a new command. After a byte
Write command, the internal address counter will point
to the address location following the one that was just
written.
Note:
Page write operations are limited to writing
bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size (or
‘page size’) and end at addresses that are
integer multiples of [page size – 1]. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
6.2
Page Write
The write control byte, word address and the first data
byte are transmitted to the 24XX512 in the same way
as in a byte write. But instead of generating a Stop
condition, the master transmits up to 127 additional
bytes, which are temporarily stored in the on-chip page
buffer and will be written into memory after the master
has transmitted a Stop condition. After receipt of each
word, the seven lower Address Pointer bits are inter-
nally incremented by one. If the master should transmit
more than 128 bytes prior to generating the Stop con-
dition, the address counter will roll over and the previ-
ously received data will be overwritten. As with the byte
write operation, once the Stop condition is received, an
internal write cycle will begin (Figure 6-2). If an attempt
is made to write to the array with the WP pin held high,
the device will acknowledge the command, but no write
cycle will occur, no data will be written and the device
will immediately accept a new command.
© 2005 Microchip Technology Inc.
DS21754G-page 9
24AA512/24LC512/24FC512
FIGURE 6-1:
BYTE WRITE
S
T
A
R
T
Bus Activity
Master
S
T
O
P
Control
Byte
Address
High Byte
Address
Low Byte
Data
A A A
SDA Line
S 1 0 1 0
0
P
2 1 0
A
C
K
A
C
K
A
C
K
A
C
K
Bus Activity
FIGURE 6-2:
PAGE WRITE
S
T
A
R
T
S
T
O
P
Control
Byte
Address
High Byte
Address
Low Byte
Bus Activity
Master
Data Byte 0
Data Byte 127
A A A
SDA Line
P
S 1 0 1 0
0
2 1 0
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Bus Activity
DS21754G-page 10
© 2005 Microchip Technology Inc.
24AA512/24LC512/24FC512
FIGURE 7-1:
ACKNOWLEDGE POLLING
FLOW
7.0
ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a Write
command has been issued from the master, the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a Start condition, followed by the control byte
for a Write command (R/W = 0). If the device is still
busy with the write cycle, then no ACK will be returned.
If no ACK is returned, then the Start bit and control byte
must be re-sent. If the cycle is complete, then the
device will return the ACK and the master can then
proceed with the next Read or Write command. See
Figure 7-1 for flow diagram.
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
No
Yes
Next
Operation
© 2005 Microchip Technology Inc.
DS21754G-page 11
24AA512/24LC512/24FC512
8.3
Sequential Read
8.0
READ OPERATION
Sequential reads are initiated in the same way as a
random read except that after the 24XX512 transmits
the first data byte, the master issues an acknowledge
as opposed to the Stop condition used in a random
read. This acknowledge directs the 24XX512 to
transmit the next sequentially addressed 8-bit word
(Figure 8-3). Following the final byte transmitted to the
master, the master will NOT generate an acknowledge,
but will generate a Stop condition. To provide
sequential reads, the 24XX512 contains an internal
Address Pointer which is incremented by one at the
completion of each operation. This Address Pointer
allows the entire memory contents to be serially read
during one operation. The internal Address Pointer will
automatically roll over from address FFFF to address
0000 if the master acknowledges the byte received
from the array address FFFF.
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
control byte is set to ‘1’. There are three basic types of
read operations: current address read, random read
and sequential read.
8.1
Current Address Read
The 24XX512 contains an address counter that main-
tains the address of the last word accessed, internally
incremented by ‘1’. Therefore, if the previous read
access was to address ‘n’ (n is any legal address), the
next current address read operation would access data
from address n + 1.
Upon receipt of the control byte with R/W bit set to ‘1’,
the 24XX512 issues an acknowledge and transmits the
8-bit data word. The master will not acknowledge the
transfer but does generate a Stop condition and the
24XX512 discontinues transmission (Figure 8-1).
FIGURE 8-1:
CURRENT ADDRESS
READ
S
T
A
R
T
S
T
O
P
Bus Activity
Master
Control
Byte
Data
Byte
A A A
2 1 0
SDA Line
S 1 0 1 0
1
P
A
C
K
N
O
Bus Activity
A
C
K
8.2
Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24XX512 as part of a write operation (R/W bit set to
‘0’). After the word address is sent, the master
generates a Start condition following the acknowledge.
This terminates the write operation, but not before the
internal Address Pointer is set. Then, the master issues
the control byte again but with the R/W bit set to a one.
The 24XX512 will then issue an acknowledge and
transmit the 8-bit data word. The master will not
acknowledge the transfer but does generate a Stop
condition which causes the 24XX512 to discontinue
transmission (Figure 8-2). After
a random Read
command, the internal address counter will point to the
address location following the one that was just read.
DS21754G-page 12
© 2005 Microchip Technology Inc.
24AA512/24LC512/24FC512
FIGURE 8-2:
RANDOM READ
S
T
A
R
T
S
Bus Activity
Master
T
A
R
T
S
T
O
P
Control
Byte
Address
High Byte
Address
Low Byte
Control
Byte
Data
Byte
A A A
2 1 0
A A A
2 1 0
SDA Line
S 1 0 1 0
0
S 1 0 1 0
1
P
N
O
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Bus Activity
x = “don’t care” bit
FIGURE 8-3:
SEQUENTIAL READ
S
Control
Byte
Bus Activity
Master
T
Data (n)
Data (n + 1)
Data (n + x)
Data (n + 2)
O
P
P
SDA Line
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
Bus Activity
© 2005 Microchip Technology Inc.
DS21754G-page 13
24AA512/24LC512/24FC512
9.0
9.1
PACKAGING INFORMATION
Package Marking Information
8-Lead PDIP (300 mil)
Example:
24AA512
I/P 017
XXXXXXXX
T/XXXNNN
YYWW
e
3
0510
8-Lead SOIC (208 mil)
Example:
24LC512
I/SM
0510017
XXXXXXXX
T/XXXXXX
YYWWNNN
e
3
8-Lead DFN-S
Example:
24LC512
XXXXXXX
T/XXXXX
YYWW
e
3
I/MF
0510
017
NNN
14-Lead TSSOP
Example:
XXXXXXXT
YYWW
4L512I
0510
017
NNN
Legend: XX...X Customer-specific information*
Y
YY
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
WW
NNN
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
e
3
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
Temperature
)
e3
T
Blank Commercial
I
E
Industrial
Extended
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
*Standard device marking consists of Microchip part number, year code, week code, and traceability code. For
device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office.
DS21754G-page 14
© 2005 Microchip Technology Inc.
24AA512/24LC512/24FC512
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
1
n
α
E
A2
A
L
c
A1
β
B1
B
p
eB
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
8
MAX
n
p
Number of Pins
Pitch
8
.100
.155
.130
2.54
Top to Seating Plane
A
.140
.170
3.56
2.92
3.94
3.30
4.32
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.115
.015
.300
.240
.360
.125
.008
.045
.014
.310
5
.145
3.68
0.38
7.62
6.10
9.14
3.18
0.20
1.14
0.36
7.87
5
.313
.250
.373
.130
.012
.058
.018
.370
10
.325
.260
.385
.135
.015
.070
.022
.430
15
7.94
6.35
9.46
3.30
0.29
1.46
0.46
9.40
10
8.26
6.60
9.78
3.43
0.38
1.78
0.56
10.92
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
© 2005 Microchip Technology Inc.
DS21754G-page 15
24AA512/24LC512/24FC512
8-Lead Plastic Small Outline (SM) – Medium, 208 mil (SOIC)
E
E1
p
D
2
n
1
B
α
c
A2
A
φ
A1
L
β
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
8
MAX
n
p
Number of Pins
Pitch
8
.050
.075
.074
.005
.313
.208
.205
.025
4
1.27
Overall Height
A
.070
.080
1.78
1.75
1.97
1.88
0.13
7.95
5.28
5.21
0.64
4
2.03
Molded Package Thickness
Standoff
A2
A1
E
.069
.002
.300
.078
.010
.325
.212
.210
.030
8
1.98
0.25
8.26
5.38
5.33
0.76
8
§
0.05
7.62
5.11
5.13
0.51
0
Overall Width
Molded Package Width
Overall Length
E1
D
.201
.202
.020
0
Foot Length
L
φ
Foot Angle
c
Lead Thickness
Lead Width
.008
.014
0
.009
.017
12
.010
.020
15
0.20
0.36
0
0.23
0.43
12
0.25
0.51
15
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
0
12
15
0
12
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
Drawing No. C04-056
DS21754G-page 16
© 2005 Microchip Technology Inc.
24AA512/24LC512/24FC512
8-Lead Plastic Dual Flat No Lead Package (MF) 6x5 mm Body (DFN-S) – Saw Singulated
© 2005 Microchip Technology Inc.
DS21754G-page 17
24AA512/24LC512/24FC512
14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
E
E1
p
D
2
1
n
B
α
A
c
φ
A1
A2
β
L
Units
INCHES
NOM
MILLIMETERS*
Dimension Limits
MIN
MAX
MIN
NOM
14
MAX
n
p
Number of Pins
Pitch
14
.026
0.65
Overall Height
A
.043
1.10
0.95
0.15
6.50
4.50
5.10
0.70
8
Molded Package Thickness
Standoff
A2
A1
E
.033
.002
.246
.169
.193
.020
0
.035
.004
.251
.173
.197
.024
4
.037
.006
.256
.177
.201
.028
8
0.85
0.05
0.90
0.10
6.38
4.40
5.00
0.60
4
§
Overall Width
6.25
4.30
4.90
0.50
0
Molded Package Width
Molded Package Length
Foot Length
E1
D
L
φ
Foot Angle
c
Lead Thickness
.004
.007
0
.006
.010
5
.008
.012
10
0.09
0.19
0
0.15
0.25
5
0.20
0.30
10
Lead Width
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
0
5
10
0
5
10
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.005” (0.127mm) per side.
JEDEC Equivalent: MO-153
Drawing No. C04-087
DS21754G-page 18
© 2005 Microchip Technology Inc.
24AA512/24LC512/24FC512
APPENDIX A: REVISION HISTORY
Revision D
Correction to Section 1.0, Electrical Characteristics.
Revision E
Correction to Section 1.0., Ambient Temperature
Correction to Section 6.2, Page Write
Revision F
Add E3 (Pb-free) to marking examples.
Updated Marking Legend and On-line Support.
Revision G
Revised Sections 2.1, 2.4 and 6.3.
© 2005 Microchip Technology Inc.
DS21754G-page 19
24AA512/24LC512/24FC512
NOTES:
DS21754G-page 20
© 2005 Microchip Technology Inc.
24AA512/24LC512/24FC512
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• Development Systems Information Line
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
Technical support is available through the web site
at: http://support.microchip.com
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com, click on Customer Change
Notification and follow the registration instructions.
© 2005 Microchip Technology Inc.
DS21754G-page 21
24AA512/24LC512/24FC512
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
To:
Technical Publications Manager
Reader Response
Total Pages Sent ________
RE:
From:
Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Y
N
24AA512/24LC512/24FC512
DS21754G
Literature Number:
Device:
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS21754G-page 22
© 2005 Microchip Technology Inc.
24AA512/24LC512/24FC512
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
PART NO.
Device
X
/XX
X
a) 24AA512-I/P:
Industrial Temp.,
Temperature
Range
Package
Lead
Finish
1.8V, PDIP package.
b) 24AA512T-I/SM: Tape and Reel,
Industrial Temp., 1.8V, SOIC
package.
Device:
24AA512:
512 Kbit 1.8V I2C Serial
EEPROM
c) 24AA512-I/ST14: Industrial Temp.,
1.8V, 14-lead, TSSOP package.
24AA512T: 512 Kbit 1.8V I2C Serial
EEPROM (Tape and Reel)
512 Kbit 2.5V I2C Serial
EEPROM
d) 24AA512-I/MF: Industrial Temp.,
1.8V, DFN package.
24LC512:
24LC512T: 512 Kbit 2.5V I2C Serial
EEPROM (Tape and Reel)
24FC512:
e) 24LC512-E/P:
Extended Temp.,
2.5V, PDIP package.
512 Kbit 1 MHz I2C Serial
EEPROM
f) 24LC512-I/SM: Industrial Temp.,
2.5V, SOIC package.
24FC512T: 512 Kbit 1 MHz I2C Serial
EEPROM (Tape and Reel)
g) 24LC512T-I/SM: Tape and Reel,
Industrial Temp., 2.5V, SOIC
package.
Temperature
Range:
I
E
=
=
-40°C to +85°C
-40°C to +125°C
h) 24LC512-I/MF: Industrial Temp.,
2.5V, DFN package.
i) 24FC512-I/P:
Industrial Temp.,
Package:
P
= Plastic DIP (300 mil body), 8-lead
2.5V, High Speed, PDIP package.
SM = Plastic SOIC (208 mil body), 8-lead
ST14 = Plastic TSSOP (4.4 mm), 14-lead
MF = Micro Lead Frame (6x5 mm body),
8-lead
j) 24FC512-I/SM: Industrial Temp.,
2.5V, High Speed, SOIC package.
k) 24FC512T-I/SM: Tape and Reel,
Industrial Temp., 2.5V, High Speed,
SOIC package
Lead Finish:
Blank= Pb-free – Matte Tin (see Note 1)
G
= Pb-free – Matte Tin only
l) 24LC512T-I/SM: Industrial Temp.,
2.5V, SOIC package, Tape & Reel,
Pb-free
m) 24LC512-I/PG: Industrial Temp.,
2.5V, PDIP package, Pb-free
Note 1: Most products manufactured after January 2005 will have a Matte Tin (Pb-free) finish. Most products
manufactured before January 2005 will have a finish of approximately 63% Sn and 37% Pb (Sn/Pb). Please
visit www.microchip.com for the latest information on Pb-free conversion, including conversion date codes.
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
© 2005 Microchip Technology Inc.
DS21754G-page23
24AA512/24LC512/24FC512
NOTES:
DS21754G-page24
© 2005 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR WAR-
RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,
WRITTEN OR ORAL, STATUTORY OR OTHERWISE,
RELATED TO THE INFORMATION, INCLUDING BUT NOT
LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE.
Microchip disclaims all liability arising from this information and
its use. Use of Microchip’s products as critical components in
life support systems is not authorized except with express
written approval by Microchip. No licenses are conveyed,
implicitly or otherwise, under any Microchip intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
PICMASTER, SEEVAL, SmartSensor and The Embedded
Control Solutions Company are registered trademarks of
Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Linear Active Thermistor,
MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM,
PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo,
PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode,
Smart Serial, SmartTel, Total Endurance and WiperLock are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2005, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2005 Microchip Technology Inc.
DS21754G-page 25
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
Australia - Sydney
Tel: 61-2-9868-6733
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Fax: 43-7242-2244-393
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Technical Support:
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Web Address:
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08/24/05
DS21754G-page 26
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