24FC256T-E/ST14_技术文档

24AA256/24LC256/24FC256

2 ™

256K I C CMOS Serial EEPROM

Device Selection Table

Description

The Microchip Technology Inc. 24AA256/24LC256/

24FC256 (24XX256*) is a 32K x 8 (256 Kbit) Serial

Electrically Erasable PROM, capable of operation

across a broad voltage range (1.8V to 5.5V). It has

been developed for advanced, low-power applications

such as personal communications or data acquisition.

This device also has a page write capability of up to 64

bytes of data. This device is capable of both random

and sequential reads up to the 256K boundary.

Functional address lines allow up to eight devices on

the same bus, for up to 2 Mbit address space. This

device is available in the standard 8-pin plastic DIP,

SOIC, TSSOP, MSOP, DFN and 14-lead TSSOP

packages.

Part

VCC

Max. Clock

Frequency

Temp.

Number

Range

Ranges

(1)

400 kHz

24AA256

24LC256

24FC256

1.8-5.5V

2.5-5.5V

I

I, E

I

400 kHz

1 MHz

Note 1: 100 kHz for V^CC< 2.5V.

Features

• Low-power CMOS technology

- Maximum write current 3 mA at 5.5V

- Maximum read current 400 µA at 5.5V

- Standby current 100 nA typical at 5.5V

2

™

• 2-wire serial interface bus, I C compatible

• Cascadable for up to eight devices

• Self-timed ERASE/WRITE cycle

Block Diagram

A0 A1A2WP

HV Generator

• 64-byte Page Write mode available

• 5 ms max write cycle time

• Hardware write-protect for entire array

• Output slope control to eliminate ground bounce

• Schmitt Trigger inputs for noise suppression

• 1,000,000 erase/write cycles

I/O

Control

Logic

Memory

Control

Logic

EEPROM

Array

XDEC

Page Latches

• Electrostatic discharge protection > 4000V

• Data retention > 200 years

I/O

SCL

YDEC

• 8-pin PDIP, SOIC, TSSOP, MSOP and DFN

packages

SDA

• 14-lead TSSOP package

V^CC

VSS

Sense AMP

R/W Control

• Standard and Pb-free finishes available

• Temperature ranges:

- Industrial (I):

-40°C to +85°C

-40°C to +125°C

- Automotive (E):

Package Types

PDIP/SOIC

TSSOP/MSOP *

TSSOP

DFN

14

1

V^CC

A0

A1

A0

1

8

VCC

1

2

3

4

A0

A1

8

7

6

5

VCC

WP

1

2

3

4

8

7

6

5

A0

A1

V^CC

WP

13

12

11

10

9

2

3

4

5

6

7

WP

NC

A1

A2

2

3

4

7

6

5

WP

NC

A2

SCL

SDA

SCL

SDA

A2

SCL

SDA

V^SS

SCL

SDA

V^SS

VSS

8

V^SS

NOTE: Pins A0 and A1 are no connects for the MSOP package only.

*24XX256 is used in this document as a generic part number for the 24AA256/24LC256/24FC256 devices.

 2003 Microchip Technology Inc.

DS21203K-page 1

24AA256/24LC256/24FC256

1.0

ELECTRICAL

CHARACTERISTICS

(†)

Absolute Maximum Ratings

VCC.............................................................................................................................................................................6.5V

All inputs and outputs w.r.t. V^SS......................................................................................................... -0.6V to VCC +1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied................................................................................................-65°C to +125°C

ESD protection on all pins ......................................................................................................................................................≥ 4 kV

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at these or any other conditions above those

indicated in the operational listings of this specification is not implied. Exposure to Absolute Maximum Rating condi-

tions for extended periods may affect device reliability.

1.1

24XX256 DC Electrical Specifications

Electrical Characteristics:

Industrial (I): V^CC= +1.8V to 5.5V

Automotive (E): V^CC= +2.5V to 5.5V

DC Specifications

TAMB = -40°C to +85°C

TAMB = -40°C to +125°C

Param.

Sym

No.

Characteristic

Min

Max

Units

Conditions

D1

—

A0, A1, A2, SCL, SDA

and WP pins:

—

D2

D3

V^IH

V^IL

High-level input voltage

Low-level input voltage

0.7 VCC

—

V

—

0.3 VCC

0.2 VCC

V

VCC ≥ 2.5V

V^CC< 2.5V

D4

V^HYS

Hysteresis of Schmitt

Trigger inputs

0.05 VCC

—

V

VCC ≥ 2.5V (Note)

(SDA, SCL pins)

D5

D6

V^OL

Low-level output voltage

Input leakage current

Output leakage current

—

0.40

10

V

IOL = 3.0 ma @ VCC = 4.5V

I^OL= 2.1 ma @ VCC = 2.5V

I^LI

µA

VIN = VSS or VCC, WP = VSS

VIN = VSS or VCC, WP = VCC

D7

D8

ILO

—

10

µA

pF

VOUT = VSS or VCC

CIN,

Pin capacitance

VCC = 5.0V (Note)

C^OUT

(all inputs/outputs)

T^AMB= 25°C, fC = 1 MHz

D9

I^CCRead Operating current

I^CCWrite

—

400

3

µA

mA

µA

VCC = 5.5V, SCL = 400 kHz

VCC = 5.5V

D10

I^CCS

Standby current

1

TAMB = -40°C to +85°C

SCL = SDA = V^CC= 5.5V

A0, A1, A2, WP = V^SS

—

5

µA

TAMB = -40°C to +125°C

SCL = SDA = V^CC= 5.5V

A0, A1, A2, WP = V^SS

Note: This parameter is periodically sampled and not 100% tested.

DS21203K-page 2

 2003 Microchip Technology Inc.

24AA256/24LC256/24FC256

1.2

24XX256 AC Electrical Specifications

Electrical Characteristics:

Industrial (I): VCC = +1.8V to 5.5V

Automotive (E): V^CC= +2.5V to 5.5V

AC Specifications

TAMB = -40°C to +85°C

TAMB = -40°C to +125°C

Param.

Sym

No.

Characteristic

Clock frequency

Min

Max

Units

Conditions

1

2

3

4

F^CLK

T^HIGH

T^LOW

T^R

—

100

400

kHz 1.8V ≤ VCC < 2.5V

2.5V ≤ V^CC≤ 5.5V

2.5V ≤ V^CC≤ 5.5V 24FC256

1000

Clock high time

4000

600

—

ns

1.8V ≤ V^CC< 2.5V

2.5V ≤ V^CC≤ 5.5V

500

2.5V ≤ V^CC≤ 5.5V 24FC256

Clock low time

4700

1300

500

—

1.8V ≤ VCC < 2.5V

2.5V ≤ V^CC≤ 5.5V

2.5V ≤ V^CC≤ 5.5V 24FC256

SDA and SCL rise time

—

1000

300

1.8V ≤ V^CC< 2.5V

(Note 1)

2.5V ≤ V^CC≤ 5.5V

300

2.5V ≤ V^CC≤ 5.5V 24FC256

5

6

T^F

SDA and SCL fall time

—

300

100

ns

All except, 24FC256

(Note 1)

2.5V ≤ V^CC≤ 5.5V 24FC256

T^HD:STA Start condition hold time

4000

600

—

1.8V ≤ V^CC< 2.5V

2.5V ≤ V^CC≤ 5.5V

250

2.5V ≤ V^CC≤ 5.5V 24FC256

7

T^SU:STA Start condition setup time

4700

600

—

ns

1.8V ≤ VCC < 2.5V

2.5V ≤ V^CC≤ 5.5V

250

2.5V ≤ V^CC≤ 5.5V 24FC256

8

9

T^HD:DAT Data input hold time

T^SU:DAT Data input setup time

0

—

ns

(Note 2)

250

100

—

1.8V ≤ V^CC< 2.5V

2.5V ≤ V^CC≤ 5.5V

2.5V ≤ V^CC≤ 5.5V 24FC256

10

11

12

13

14

T^SU:STO Stop condition setup time

4000

600

—

ns

1.8V ≤ VCC < 2.5V

2.5V ≤ V^CC≤ 5.5V

250

2.5V ≤ V^CC≤ 5.5V 24FC256

T^SU:WP WP setup time

4000

600

—

1.8V ≤ V^CC< 2.5V

2.5V ≤ V^CC≤ 5.5V

600

2.5V ≤ V^CC≤ 5.5V 24FC256

T^HD:WP WP hold time

4700

1300

—

1.8V ≤ V^CC< 2.5V

2.5V ≤ V^CC≤ 5.5V

2.5V ≤ V^CC≤ 5.5V 24FC256

T^AA

Output valid from clock

—

3500

900

1.8 V ≤ VCC < 2.5V

(Note 2)

2.5 V ≤ V^CC≤ 5.5V

400

2.5 V ≤ V^CC≤ 5.5V 24FC256

T^BUF

Bus free time: Time the bus

must be free before a new

transmission can start

4700

1300

500

—

1.8V ≤ V^CC< 2.5V

2.5V ≤ V^CC≤ 5.5V

2.5V ≤ V^CC≤ 5.5V 24FC256

Note 1: Not 100% tested. C^B= total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

3: The combined T^SPand VHYS specifications are due to new Schmitt Trigger inputs, which provide improved

noise spike suppression. This eliminates the need for a T^Ispecification for standard operation.

4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific

application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site:

www.microchip.com.

 2003 Microchip Technology Inc.

DS21203K-page 3

24AA256/24LC256/24FC256

Electrical Characteristics:

AC Specifications (Continued)

Industrial (I):

V^CC= +1.8V to 5.5V

TAMB = -40°C to +85°C

TAMB = -40°C to +125°C

Automotive (E): V^CC= +2.5V to 5.5V

Param.

No.

Sym

Characteristic

Min

Max

Units

Conditions

15

TOF

Output fall time from VIH

minimum to VIL maximum

C^B≤ 100 pF

10 +

250

ns

All except, 24FC256 (Note 1)

0.1CB

16

17

18

T^SP

T^WC

—

Input filter spike suppression

(SDA and SCL pins)

—

50

5

ns

All except, 24FC256 (Notes 1

and 3)

Write cycle time (byte or

page)

ms

—

Endurance

1,000,000

—

cycles 25°C (Note 4)

Note 1: Not 100% tested. C^B= total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

3: The combined T^SPand VHYS specifications are due to new Schmitt Trigger inputs, which provide improved

noise spike suppression. This eliminates the need for a T^Ispecification for standard operation.

4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific

application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site:

www.microchip.com.

FIGURE 1-1:

BUS TIMING DATA

5

4

D4

2

SCL

7

3

10

8

9

SDA

IN

6

16

14

13

SDA

OUT

(protected)

WP

12

11

(unprotected)

DS21203K-page 4

 2003 Microchip Technology Inc.

24AA256/24LC256/24FC256

2.0

PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 2-1.

TABLE 2-1:

PIN FUNCTION TABLE

8-pin

PDIP

8-pin

SOIC

8-pin

14-pin

8-pin

DFN

Name

Function

TSSOP

MSOP

A0

1

2

1

2

1

2

1

—

1,2

3

1

2

User Configurable Chip Select

Not Connected

A1

2

(NC)

A2

—

3

—

3

—

3

3, 4, 5

—

3

6

User Configurable Chip Select

Ground

V^SS

SDA

SCL

(NC)

WP

V^CC

4

7

4

5

8

5

Serial Data

6

9

10, 11, 12

13

6

Serial Clock

—

7

—

7

—

7

—

7

—

7

Not Connected

Write-Protect Input

8

14

8

+1.8V to 5.5V (24AA256)

+2.5V to 5.5V (24LC256)

+2.5V to 5.5V (24FC256)

2.1

A0, A1, A2 Chip Address Inputs

2.3

Serial Clock (SCL)

The A0, A1 and A2 inputs are used by the 24XX256 for

multiple device operations. The levels on these inputs

are compared with the corresponding bits in the slave

address. The chip is selected if the compare is true.

This input is used to synchronize the data transfer to

and from the device.

2.4

Write-Protect (WP)

For the MSOP package only, pins A0 and A1 are not

connected.

This pin can be connected to either VSS, VCC or left

floating. Internal pull-down circuitry on this pin will keep

the device in the unprotected state if left floating. If tied

to V^SSor left floating, normal memory operation is

enabled (read/write the entire memory 0000-7FFF).

Up to eight devices (two for the MSOP package) may

be connected to the same bus by using different chip

select bit combinations. If these pins are left

unconnected, the inputs will be pulled down internally

to V^SS. If they are tied to VCC or driven high, the internal

pull-down circuitry is disabled.

If tied to V^CC, write operations are inhibited. Read

operations are not affected.

In most applications, the chip address inputs A0, A1

and A2 are hard-wired to logic ‘0’ or logic ‘1’. For

applications in which these pins are controlled by a

microcontroller or other programmable device, the chip

address pins must be driven to logic ‘0’ or logic ‘1’

before normal device operation can proceed.

2.2

Serial Data (SDA)

This is a bidirectional pin used to transfer addresses

and data into and out of the device. It is an open drain

terminal. Therefore, the SDA bus requires a pull-up

resistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for

400 kHz and 1 MHz).

For normal data transfer, SDA is allowed to change

only during SCL low. Changes during SCL high are

reserved for indicating the Start and Stop conditions.

 2003 Microchip Technology Inc.

DS21203K-page 5

24AA256/24LC256/24FC256

3.0

FUNCTIONAL DESCRIPTION

The 24XX256 supports a bidirectional 2-wire bus and

data transmission protocol. A device that sends data

onto the bus is defined as a transmitter and a device

receiving data as a receiver. The bus must be

controlled by a master device which generates the

serial clock (SCL), controls the bus access, and

generates the Start and Stop conditions while the

24XX256 works as a slave. Both master and slave can

operate as a transmitter or receiver, but the master

device determines which mode is activated.

DS21203K-page 6

 2003 Microchip Technology Inc.

24AA256/24LC256/24FC256

The data on the line must be changed during the low

period of the clock signal. There is one bit of data per

clock pulse.

4.0

BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

Each data transfer is initiated with a Start condition and

terminated with a Stop condition. The number of the

data bytes transferred between the Start and Stop

conditions is determined by the master device.

• During data transfer, the data line must remain

stable whenever the clock line is high. Changes

in the data line, while the clock line is high, will be

interpreted as a Start or Stop condition.

4.5

Acknowledge

Accordingly, the following bus conditions have been

defined (Figure 4-1).

Each receiving device, when addressed, is obliged to

generate an Acknowledge signal after the reception of

each byte. The master device must generate an extra

clock pulse which is associated with this Acknowledge

bit.

4.1

Bus not Busy (A)

Both data and clock lines remain high.

Note: The 24XX256 does not generate any

Acknowledge

bits

if

an

internal

4.2

Start Data Transfer (B)

programming cycle is in progress.

A high-to-low transition of the SDA line while the clock

(SCL) is high, determines a Start condition. All

commands must be preceded by a Start condition.

A device that acknowledges must pull down the SDA

line during the acknowledge clock pulse in such a way

that the SDA line is stable low during the high period of

the acknowledge related clock pulse. Of course, setup

and hold times must be taken into account. During

reads, a master must signal an end of data to the slave

by NOT generating an Acknowledge bit on the last byte

that has been clocked out of the slave. In this case, the

slave (24XX256) will leave the data line high to enable

the master to generate the Stop condition.

4.3

Stop Data Transfer (C)

A low-to-high transition of the SDA line, while the clock

(SCL) is high, determines a Stop condition. All

operations must end with a Stop condition.

4.4

Data Valid (D)

The state of the data line represents valid data when,

after a Start condition, the data line is stable for the

duration of the high period of the clock signal.

FIGURE 4-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A)

(B)

(D)

(C) (A)

SCL

SDA

Start

Condition

Address or

Acknowledge

Valid

Data

Stop

Condition

Allowed

to Change

 2003 Microchip Technology Inc.

DS21203K-page 7

24AA256/24LC256/24FC256

FIGURE 4-2:

ACKNOWLEDGE TIMING

Acknowledge

Bit

1

2

3

4

5

6

7

8

9

1

2

3

SCL

SDA

Data from transmitter

Transmitter must release the SDA line at this point,

allowing the Receiver to pull the SDA line low to

acknowledge the previous eight bits of data.

Receiver must release the SDA line

at this point so the Transmitter can

continue sending data.

DS21203K-page 8

 2003 Microchip Technology Inc.

24AA256/24LC256/24FC256

FIGURE 5-1:

CONTROL BYTE

FORMAT

5.0

DEVICE ADDRESSING

A control byte is the first byte received following the

Start condition from the master device (Figure 5-1).

The control byte consists of a 4-bit control code. For the

24XX256, this is set as 1010 binary for read and write

operations. The next three bits of the control byte are

the chip select bits (A2, A1, A0). The chip select bits

allow the use of up to eight 24XX256 devices on the

same bus and are used to select which device is

accessed. The chip select bits in the control byte must

correspond to the logic levels on the corresponding A2,

A1 and A0 pins for the device to respond. These bits

are, in effect, the three Most Significant bits of the word

address.

Read/Write Bit

Chip Select

Bits

Control Code

S

1

0

A2 A1 A0 R/W ACK

1

Slave Address

Start Bit

Acknowledge Bit

For the MSOP package, the A0 and A1 pins are not

connected. During device addressing, the A0 and A1

chip select bits (Figures 5-1 and 5-2) should be set to

‘0’. Only two 24XX256 MSOP packages can be

connected to the same bus.

5.1

Contiguous Addressing Across

Multiple Devices

The chip select bits A2, A1, A0 can be used to expand

the contiguous address space for up to 2 Mbit by

adding up to eight 24XX256s on the same bus. In this

case, software can use A0 of the control byte as

address bit A15; A1 as address bit A16; and A2 as

address bit A17. It is not possible to sequentially read

across device boundaries.

The last bit of the control byte defines the operation to

be performed. When set to a one, a read operation is

selected. When set to a zero, a write operation is

selected. The next two bytes received define the

address of the first data byte (Figure 5-2). Because

only A14…A0 are used, the upper address bits are a

don’t care. The upper address bits are transferred first,

followed by the less significant bits.

For the MSOP package, up to two 24XX256 devices

can be added for up to 512 Kbit of address space. In

this case, software can use A2 of the control byte as

address bit A17. Bits A0 (A15) and A1 (A16) of the

control byte must always be set to a logic ‘0’ for the

MSOP.

Following the Start condition, the 24XX256 monitors

the SDA bus checking the device type identifier being

transmitted. Upon receiving a 1010 code and appro-

priate device select bits, the slave device outputs an

Acknowledge signal on the SDA line. Depending on the

state of the R/W bit, the 24XX256 will select a read or

write operation.

FIGURE 5-2:

ADDRESS SEQUENCE BIT ASSIGNMENTS

CONTROL BYTE

ADDRESS HIGH BYTE

ADDRESS LOW BYTE

A

1

A

•

1

0

1

0

R/W

X

10

2

0

12 11

9

8

7

0

14 13

CONTROL

CODE

CHIP

X = Don’t Care Bit

SELECT

BITS

 2003 Microchip Technology Inc.

DS21203K-page 9

24AA256/24LC256/24FC256

pointer bits are internally incremented by one. If the

master should transmit more than 64 bytes prior to

generating the Stop condition, the address counter will

roll over and the previously received data will be over-

written. As with the byte write operation, once the Stop

condition is received, an internal write cycle will begin

(Figure 6-2). If an attempt is made to write to the array

with the WP pin held high, the device will acknowledge

the command but no write cycle will occur, no data will

be written and the device will immediately accept a new

command.

6.0

WRITE OPERATIONS

6.1

Byte Write

Following the Start condition from the master, the

control code (four bits), the chip select (three bits) and

the R/W bit (which is a logic low) are clocked onto the

bus by the master transmitter. This indicates to the

addressed slave receiver that the address high byte will

follow after it has generated an Acknowledge bit during

the ninth clock cycle. Therefore, the next byte

transmitted by the master is the high-order byte of the

word address and will be written into the address

pointer of the 24XX256. The next byte is the Least

Significant Address Byte. After receiving another

Acknowledge signal from the 24XX256, the master

device will transmit the data word to be written into the

addressed memory location. The 24XX256 acknowl-

edges again and the master generates a Stop

condition. This initiates the internal write cycle and

during this time, the 24XX256 will not generate

Acknowledge signals (Figure 6-1). If an attempt is

made to write to the array with the WP pin held high, the

device will acknowledge the command but no write

cycle will occur, no data will be written, and the device

will immediately accept a new command. After a byte

Write command, the internal address counter will point

to the address location following the one that was just

written.

6.3

Write-Protection

The WP pin allows the user to write-protect the entire

array (0000-7FFF) when the pin is tied to V^CC. If tied to

V^SSor left floating, the write-protection is disabled. The

WP pin is sampled at the Stop bit for every Write

command (Figure 1-1). Toggling the WP pin after the

Stop bit will have no effect on the execution of the write

cycle.

Note: Page write operations are limited to writing

bytes within

a single physical page,

regardless of the number of bytes actually

being written. Physical page boundaries

start at addresses that are integer multi-

ples of the page buffer size (or ‘page size’)

and end at addresses that are integer mul-

tiples of [page size - 1]. If a page Write

command attempts to write across a phys-

ical page boundary, the result is that the

data wraps around to the beginning of the

current page (overwriting data previously

stored there), instead of being written to

the next page, as might be expected. It is,

therefore, necessary for the application

software to prevent page write operations

that would attempt to cross a page

boundary.

6.2

Page Write

The write control byte, word address and the first data

byte are transmitted to the 24XX256 in much the same

way as in a byte write. The exception is that instead of

generating a Stop condition, the master transmits up to

63 additional bytes, which are temporarily stored in the

on-chip page buffer and will be written into memory

once the master has transmitted a Stop condition.

Upon receipt of each word, the six lower address

FIGURE 6-1:

BYTE WRITE

S

BUS ACTIVITY

MASTER

T

A

R

T

S

CONTROL

BYTE

ADDRESS

HIGH BYTE

ADDRESS

LOW BYTE

T

O

P

DATA

SDA LINE

A A A

X

S 1 0 1 0

0

P

2 1 0

BUS ACTIVITY

A

C

K

A

C

K

A

C

K

A

C

K

X = don’t care bit

FIGURE 6-2:

PAGE WRITE

S

T

A

R

T

BUS ACTIVITY

MASTER

S

T

CONTROL

BYTE

ADDRESS

HIGH BYTE

ADDRESS

LOW BYTE

O

P

DATA BYTE 0

DATA BYTE 63

SDA LINE

A A A

X

P

S 1 0 1 0

0

2 1 0

BUS ACTIVITY

A

C

K

A

C

K

A

C

K

A

C

K

C

X = don’t care bit

K

DS21203K-page 10

 2003 Microchip Technology Inc.

24AA256/24LC256/24FC256

FIGURE 7-1:

ACKNOWLEDGE

POLLING FLOW

7.0

ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write

cycle, this can be used to determine when the cycle is

complete (This feature can be used to maximize bus

throughput.) Once the Stop condition for a Write

command has been issued from the master, the device

initiates the internally timed write cycle. ACK polling

can be initiated immediately. This involves the master

sending a Start condition, followed by the control byte

for a Write command (R/W = 0). If the device is still

busy with the write cycle, then no ACK will be returned.

If no ACK is returned, the Start bit and control byte must

be resent. If the cycle is complete, then the device will

return the ACK and the master can then proceed with

the next Read or Write command. See Figure 7-1 for

flow diagram.

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

NO

Did Device

Acknowledge

(ACK = 0)?

YES

 2003 Microchip Technology Inc.

DS21203K-page 11

24AA256/24LC256/24FC256

8.2

Random Read

8.0

READ OPERATION

Random read operations allow the master to access

any memory location in a random manner. To perform

this type of read operation, the word address must first

be set. This is done by sending the word address to the

24XX256 as part of a write operation (R/W bit set to

‘0’). Once the word address is sent, the master gener-

ates a Start condition following the acknowledge. This

terminates the write operation, but not before the

internal address pointer is set. The master then issues

the control byte again but with the R/W bit set to a one.

The 24XX256 will then issue an acknowledge and

transmit the 8-bit data word. The master will not

acknowledge the transfer, though it does generate a

Stop condition, which causes the 24XX256 to discon-

tinue transmission (Figure 8-2). After a random Read

command, the internal address counter will point to the

address location following the one that was just read.

Read operations are initiated in much the same way as

write operations, with the exception that the R/W bit of

the control byte is set to ‘1’. There are three basic types

of read operations: current address read, random read

and sequential read.

8.1

Current Address Read

The 24XX256 contains an address counter that main-

tains the address of the last word accessed, internally

incremented by ‘1’. Therefore, if the previous read

access was to address n (n is any legal address), the

next current address read operation would access data

from address n + 1.

Upon receipt of the control byte with R/W bit set to ‘1’,

the 24XX256 issues an acknowledge and transmits the

8-bit data word. The master will not acknowledge the

transfer but does generate a Stop condition and the

24XX256 discontinues transmission (Figure 8-1).

8.3

Sequential Read

Sequential reads are initiated in the same way as a

random read except that after the 24XX256 transmits

the first data byte, the master issues an acknowledge

as opposed to the Stop condition used in a random

read. This acknowledge directs the 24XX256 to

transmit the next sequentially addressed 8-bit word

(Figure 8-3). Following the final byte transmitted to the

master, the master will NOT generate an acknowledge

but will generate a Stop condition. To provide sequen-

tial reads, the 24XX256 contains an internal address

pointer which is incremented by one at the completion

of each operation. This address pointer allows the

entire memory contents to be serially read during one

operation. The internal address pointer will

automatically roll over from address 7FFF to address

0000 if the master acknowledges the byte received

from the array address 7FFF.

FIGURE 8-1:

CURRENT ADDRESS

READ

S

T

A

R

T

S

T

BUS ACTIVITY

MASTER

CONTROL

BYTE

DATA

BYTE

O

P

A A A

SDA LINE

S 1 0 1 0

1

P

2 1 0

A

C

K

N

O

BUS ACTIVITY

A

C

K

FIGURE 8-2:

RANDOM READ

S

T

A

R

T

S

BUS ACTIVITY

MASTER

T

A

R

T

S

T

CONTROL

BYTE

ADDRESS

HIGH BYTE

ADDRESS

LOW BYTE

CONTROL

BYTE

DATA

BYTE

O

P

A A A

SDA LINE

X

S 1 0 1 0

0

S 1 0 1 0

1

P

2 1 0

A

C

K

A

C

K

A

C

K

N

O

A

C

K

BUS ACTIVITY

A

C

X = Don’t Care Bit

FIGURE 8-3:

SEQUENTIAL READ

S

CONTROL

BUS ACTIVITY

MASTER

T

BYTE

DATA (n)

DATA (n + 1)

DATA (n + X)

DATA (n + 2)

O

P

SDA LINE

A

C

K

A

C

K

A

C

K

A

C

K

N

O

BUS ACTIVITY

A

C

K

DS21203K-page 12

 2003 Microchip Technology Inc.

24AA256/24LC256/24FC256

9.0

PACKAGING INFORMATION

9.1

Package Marking Information

8-Lead PDIP (300 mil)

Example:

24AA256

I/P017

0310

XXXXXXXX

T/XXXNNN

YYWW

8-Lead SOIC (150 mil)

Example:

XXXXXXXX

T/XXYYWW

24LC256

I/SN0310

NNN

017

8-Lead SOIC (208 mil)

Example:

XXXXXXXX

T/XXXXXX

YYWWNNN

24LC256

I/SM

0310017

Example:

8-Lead TSSOP

XXXX

4LD

I301

TYWW

NNN

017

Legend: XX...X Customer specific information*

T

Temperature grade (I, E)

Y

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

YY

WW

NNN

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

Note:In the event the full Microchip part number cannot be marked on one line, it will be

carried over to the next line thus limiting the number of available characters for customer

specific information.

*Standard device marking consists of Microchip part number, year code, week code, and traceability code. For

device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office.

 2003 Microchip Technology Inc.

DS21203K-page 13

24AA256/24LC256/24FC256

Package Marking Information (Continued)

8-Lead MSOP

Example:

XXXXXT

4L256I

101017

YWWNNN

8-Lead DFN-S

Example:

24LC256

XXXXXXX

T/XXXXX

YYWW

I/MF

YYWW

NNN

14-Lead TSSOP

Example:

XXXXXXXT

YYWW

24LC256I

0110

017

NNN

TSSOP Package Codes

MSOP Package Codes

Part No.

24AA256

24LC256

24FC256

STD

4AD

4LD

4FD

Pb-free

G4AD

G4LD

G4FD

STD

Pb-free

G4AD

G4LD

G4FD

4A256

4L256

4F256

DS21203K-page 14

 2003 Microchip Technology Inc.

24AA256/24LC256/24FC256

8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)

E1

D

2

1

n

α

E

A2

A

L

c

A1

β

B1

B

p

eB

Units

INCHES*

NOM

MILLIMETERS

Dimension Limits

MIN

MAX

MIN

NOM

MAX

n

p

Number of Pins

Pitch

Top to Seating Plane

8

.100

.155

.130

2.54

A

.140

.170

3.56

2.92

3.94

3.30

4.32

Molded Package Thickness

Base to Seating Plane

Shoulder to Shoulder Width

Molded Package Width

Overall Length

A2

A1

E

.115

.015

.300

.240

.360

.125

.008

.045

.014

.310

5

.145

3.68

0.38

7.62

6.10

9.14

3.18

0.20

1.14

0.36

7.87

5

.313

.250

.373

.130

.012

.058

.018

.370

10

.325

.260

.385

.135

.015

.070

.022

.430

15

7.94

6.35

9.46

3.30

0.29

1.46

0.46

9.40

10

8.26

6.60

9.78

3.43

0.38

1.78

0.56

10.92

15

E1

D

Tip to Seating Plane

Lead Thickness

L

c

Upper Lead Width

B1

B

Lower Lead Width

Overall Row Spacing

Mold Draft Angle Top

Mold Draft Angle Bottom

§

eB

α

β

5

10

15

5

10

15

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-001

Drawing No. C04-018

 2003 Microchip Technology Inc.

DS21203K-page 15

24AA256/24LC256/24FC256

8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)

E

E1

p

D

2

B

n

1

h

α

45×

c

A2

A

f

β

L

A1

Units

INCHES*

NOM

MILLIMETERS

Dimension Limits

MIN

MAX

MIN

NOM

MAX

n

p

Number of Pins

Pitch

8

.050

.061

.056

.007

.237

.154

.193

.015

.025

4

1.27

Overall Height

A

.053

.069

1.35

1.32

1.55

1.42

0.18

6.02

3.91

4.90

0.38

0.62

4

1.75

Molded Package Thickness

Standoff

A2

A1

E

.052

.004

.228

.146

.189

.010

.019

0

.061

.010

.244

.157

.197

.020

.030

8

1.55

0.25

6.20

3.99

5.00

0.51

0.76

8

§

0.10

5.79

3.71

4.80

0.25

0.48

0

Overall Width

Molded Package Width

Overall Length

E1

D

h

Chamfer Distance

Foot Length

L

f

Foot Angle

c

Lead Thickness

Lead Width

.008

.013

0

.009

.017

12

.010

.020

15

0.20

0.33

0

0.23

0.42

12

0.25

0.51

15

B

α

β

Mold Draft Angle Top

Mold Draft Angle Bottom

0

12

15

0

12

15

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-012

Drawing No. C04-057

DS21203K-page 16

 2003 Microchip Technology Inc.

24AA256/24LC256/24FC256

8-Lead Plastic Small Outline (SM) – Medium, 208 mil (SOIC)

E

E1

p

D

2

1

n

B

α

c

A2

A

f

A1

L

β

Units

INCHES*

NOM

MILLIMETERS

Dimension Limits

MIN

MAX

MIN

NOM

MAX

n

p

Number of Pins

Pitch

8

.050

.075

.074

.005

.313

.208

.205

.025

4

1.27

Overall Height

A

.070

.080

1.78

1.75

1.97

1.88

0.13

7.95

5.28

5.21

0.64

4

2.03

Molded Package Thickness

Standoff

A2

A1

E

.069

.002

.300

.078

.010

.325

.212

.210

.030

8

1.98

0.25

8.26

5.38

5.33

0.76

8

§

0.05

7.62

5.11

5.13

0.51

0

Overall Width

Molded Package Width

Overall Length

E1

D

.201

.202

.020

0

Foot Length

L

f

Foot Angle

c

Lead Thickness

Lead Width

.008

.014

0

.009

.017

12

.010

.020

15

0.20

0.36

0

0.23

0.43

12

0.25

0.51

15

B

α

Mold Draft Angle Top

Mold Draft Angle Bottom

β

0

12

15

0

12

15

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

Drawing No. C04-056

 2003 Microchip Technology Inc.

DS21203K-page 17

24AA256/24LC256/24FC256

8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)

E

E1

p

D

2

1

n

B

α

A

c

A1

A2

φ

β

L

Units

INCHES

NOM

MILLIMETERS*

Dimension Limits

MIN

MAX

MIN

NOM

MAX

n

p

Number of Pins

Pitch

8

.026

0.65

Overall Height

A

.043

1.10

0.95

0.15

6.50

4.50

3.10

0.70

8

Molded Package Thickness

Standoff

A2

A1

E

.033

.035

.004

.251

.173

.118

.024

4

.037

.006

.256

.177

.122

.028

8

0.85

0.05

0.90

0.10

6.38

4.40

3.00

0.60

4

§

.002

.246

.169

.114

.020

0

Overall Width

6.25

4.30

2.90

0.50

0

Molded Package Width

Molded Package Length

Foot Length

E1

D

L

φ

Foot Angle

c

Lead Thickness

.004

.007

0

.006

.010

5

.008

.012

10

0.09

0.19

0

0.15

0.25

5

0.20

0.30

10

Lead Width

B

α

β

Mold Draft Angle Top

Mold Draft Angle Bottom

0

5

10

0

5

10

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.005” (0.127mm) per side.

JEDEC Equivalent: MO-153

Drawing No. C04-086

DS21203K-page 18

 2003 Microchip Technology Inc.

24AA256/24LC256/24FC256

8-Lead Plastic Micro Small Outline Package (MS) (MSOP)

E

p

E1

D

2

1

B

n

α

A2

A

c

φ

A1

(F)

L

β

Units

INCHES

NOM

MILLIMETERS*

NOM

Dimension Limits

MIN

MAX

MIN

MAX

n

p

Number of Pins

Pitch

8

.026

0.65

Overall Height

A

A2

A1

E

.044

1.18

Molded Package Thickness

Standoff

.030

.034

.038

.006

.200

.122

.028

.039

0.76

0.05

0.86

0.97

0.15

.5.08

3.10

0.70

1.00

§

.002

.184

.114

.016

.035

Overall Width

.193

.118

.022

.037

4.90

3.00

0.55

0.95

4.67

2.90

0.40

0.90

Molded Package Width

Overall Length

E1

D

Foot Length

L

Footprint (Reference)

Foot Angle

F

φ

0

6

0

6

c

Lead Thickness

Lead Width

.004

.010

.006

.012

.008

.016

0.10

0.25

0.15

0.30

0.20

0.40

B

α

Mold Draft Angle Top

Mold Draft Angle Bottom

7

β

7

*Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not

exceed .010" (0.254mm) per side.

Drawing No. C04-111

 2003 Microchip Technology Inc.

DS21203K-page 19

24AA256/24LC256/24FC256

8-Lead Micro Lead Frame Package (MF) 6x5 mm Body (DFN-S) (Formerly MLF-S)

E

p

B

E1

n

L

R

D1

D

D2

PIN 1

ID

EXPOSED

METAL

PADS

1

2

E2

TOP VIEW

BOTTOM VIEW

α

A2

A3

A

A1

Units

INCHES

NOM

MILLIMETERS*

Dimension Limits

MIN

MAX

MIN

NOM

MAX

n

p

Number of Pins

Pitch

8

.050 BSC

.033

1.27 BSC

0.85

Overall Height

A

.039

1.00

Molded Package Thickness

Standoff

A2

A1

A3

E

.026

.031

.002

0.65

0.80

0.05

.000

.0004

0.00

0.01

0.20 REF.

4.92 BSC

4.67 BSC

4.00

Base Thickness

Overall Length

.008 REF.

.194 BSC

.184 BSC

.158

Molded Package Length

Exposed Pad Length

Overall Width

E1

E2

D

.152

.163

3.85

4.15

.236 BSC

.226 BSC

.091

5.99 BSC

5.74 BSC

2.31

Molded Package Width

Exposed Pad Width

Lead Width

D1

D2

B

.085

.014

.020

.097

.019

.030

2.16

0.35

0.50

2.46

0.47

0.75

.016

0.40

Lead Length

L

.024

0.60

Tie Bar Width

R

.014

.356

α

Mold Draft Angle Top

12

*Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.

JEDEC equivalent: pending

Drawing No. C04-113

DS21203K-page 20

 2003 Microchip Technology Inc.

24AA256/24LC256/24FC256

8-Lead Micro Leadframe Package (MF) 6x5 mm Body (DFN-S) (Continued)

M

SOLDER

MASK

M

p

B

PACKAGE

EDGE

L

Units

Dimension Limits

INCHES

NOM

MILLIMETERS*

NOM

MIN

MAX

MIN

MAX

p

Pitch

.050 BSC

.016

1.27 BSC

Pad Width

Pad Length

B

L

.014

.019

0.35

0.50

0.13

0.40

0.60

0.47

.020

.005

.024

.030

.006

0.75

0.15

Pad to Solder Mask

M

*Controlling Parameter

Drawing No. C04-2113

 2003 Microchip Technology Inc.

DS21203K-page 21

24AA256/24LC256/24FC256

14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)

E

E1

p

D

2

1

n

B

α

A

c

f

A1

A2

β

L

Units

INCHES

NOM

MILLIMETERS*

Dimension Limits

MIN

MAX

MIN

NOM

14

MAX

n

p

Number of Pins

Pitch

14

.026

0.65

Overall Height

A

.043

1.10

0.95

0.15

6.50

4.50

5.10

0.70

8

Molded Package Thickness

Standoff

A2

A1

E

.033

.002

.246

.169

.193

.020

0

.035

.004

.251

.173

.197

.024

4

.037

.006

.256

.177

.201

.028

8

0.85

0.05

0.90

0.10

6.38

4.40

5.00

0.60

4

§

Overall Width

6.25

4.30

4.90

0.50

0

Molded Package Width

Molded Package Length

Foot Length

E1

D

L

f

Foot Angle

c

Lead Thickness

.004

.007

0

.006

.010

5

.008

.012

10

0.09

0.19

0

0.15

0.25

5

0.20

0.30

10

Lead Width

B

α

Mold Draft Angle Top

Mold Draft Angle Bottom

β

0

5

10

0

5

10

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.005” (0.127mm) per side.

JEDEC Equivalent: MO-153

Drawing No. C04-087

DS21203K-page 22

 2003 Microchip Technology Inc.

24AA256/24LC256/24FC256

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Examples:

PART NO.

Device

X

/XX

X

a) 24AA256-I/P:

Industrial Temper-

Temperature

Range

Package

Lead

ature, 1.8V, PDIP package.

Finish

b) 24AA256T-I/SN: Tape and Reel,

Industrial Temp., 1.8V, SOIC pack-

age.

2

256 Kbit 1.8V I C Serial

Device:

24AA256:

EEPROM

c) 24AA256-I/ST:

Industrial Temper-

2

24AA256T: 256 Kbit 1.8V I C Serial

ature, 1.8V, TSSOP package.

EEPROM Tape and Reel)

2

256 Kbit 2.5V I C Serial

d) 24AA256-I/MS: Industrial Temper-

ature, 1.8V, MSOP package.

24LC256:

EEPROM

2

24LC256T: 256 Kbit 2.5V I C Serial

e) 24LC256-E/P:

Extended Tem-

EEPROM Tape and Reel)

perature, 2.5V, PDIP package.

2

256 Kbit 1 MHz I C Serial

24FC256:

f) 24LC256-I/SN: Industrial Temper-

ature, 2.5V, SOIC package.

EEPROM

2

24FC256T: 256 Kbit 1 MHz I C Serial

EEPROM Tape and Reel)

g) 24LC256T-I/SN: Tape and Reel,

Industrial Temperature, 2.5V, SOIC

package.

Temperature

Range:

I

=

-40°C to +85°C

-40°C to +125°C

h) 24LC256-I/MS: Industrial Temper-

ature, 2.5V, MSOP package.

E

=

i) 24FC256-I/P:

Industrial Temper-

Package:

P

= Plastic DIP (300 mil body), 8-lead

ature, 2.5V, High Speed, PDIP pack-

age.

SN = Plastic SOIC (150 mil body), 8-lead

SM = Plastic SOIC (208 mil body), 8-lead

ST = Plastic TSSOP (4.4 mm), 8-lead

ST14 = Plastic TSSOP (4.4 mm), 14-lead

MF = Dual, Flat, No Lead (DFN)(6x5 mm

body), 8-lead

j) 24FC256-I/SN: Industrial Temper-

ature, 2.5V, High Speed, SOIC pack-

age.

k) 24FC256T-I/SN: Tape and Reel,

Industrial Temperature, 2.5V, High

Speed, SOIC package

MS = Plastic Micro Small Outline (MSOP),

8-lead

l) 24LC256T-I/STG: Industrial Temper-

ature, 2.5V, TSSOP package, Tape

& Reel, Pb-free

Lead Finish

Blank= Standard 63%/37% Sn/Pb

G

= Pb-free (Pure Matte Sn)

m) 24LC256-I/PG: Industrial Temper-

ature, 2.5V, PDIP package, Pb-free

Sales and Support

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences

and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of

the following:

1. Your local Microchip sales office

2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277

3. The Microchip Worldwide Site (www.microchip.com)

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

New Customer Notification System

Register on our web site (www.microchip.com/cn) to receive the most current information on our products.

 2003 Microchip Technology Inc.

DS21203K-page 23

24AA256/24LC256/24FC256

NOTES:

DS21203K-page 24

 2003 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is intended through suggestion only

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

No representation or warranty is given and no liability is

assumed by Microchip Technology Incorporated with respect

to the accuracy or use of such information, or infringement of

patents or other intellectual property rights arising from such

use or otherwise. Use of Microchip’s products as critical

components in life support systems is not authorized except

with express written approval by Microchip. No licenses are

conveyed, implicitly or otherwise, under any intellectual

property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

K^EELOQ, MPLAB, PIC, PICmicro, PICSTART, PRO MATE and

PowerSmart are registered trademarks of Microchip

Technology Incorporated in the U.S.A. and other countries.

FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL

and The Embedded Control Solutions Company are

registered trademarks of Microchip Technology Incorporated

in the U.S.A.

Accuron, Application Maestro, dsPICDEM, dsPICDEM.net,

ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-

Circuit Serial Programming, ICSP, ICEPIC, microPort,

Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,

PICC, PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo,

PowerMate, PowerTool, rfLAB, rfPIC, Select Mode,

SmartSensor, SmartShunt, SmartTel and Total Endurance are

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

Serialized Quick Turn Programming (SQTP) is a service mark

of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received QS-9000 quality system

certification for its worldwide headquarters,

design and wafer fabrication facilities in

Chandler and Tempe, Arizona in July 1999

and Mountain View, California in March 2002.

The Company’s quality system processes and

procedures are QS-9000 compliant for its

PICmicro^®8-bit MCUs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals,

non-volatile memory and analog products. In

addition, Microchip’s quality system for the

design and manufacture of development

systems is ISO 9001 certified.

 2003 Microchip Technology Inc.

DS21203K-page 25

WORLDWIDE SALES AND SERVICE

Korea

AMERICAS

ASIA/PACIFIC

168-1, Youngbo Bldg. 3 Floor

Corporate Office

Australia

Samsung-Dong, Kangnam-Ku

Seoul, Korea 135-882

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Suite 22, 41 Rawson Street

Epping 2121, NSW

Australia

Tel: 82-2-554-7200 Fax: 82-2-558-5932 or

82-2-558-5934

Fax: 480-792-7277

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

Singapore

Technical Support: 480-792-7627

Web Address: http://www.microchip.com

200 Middle Road

China - Beijing

#07-02 Prime Centre

Singapore, 188980

Unit 915

Atlanta

Bei Hai Wan Tai Bldg.

No. 6 Chaoyangmen Beidajie

Beijing, 100027, No. China

Tel: 86-10-85282100

Fax: 86-10-85282104

3780 Mansell Road, Suite 130

Alpharetta, GA 30022

Tel: 770-640-0034

Fax: 770-640-0307

Tel: 65-6334-8870 Fax: 65-6334-8850

Taiwan

Kaohsiung Branch

30F - 1 No. 8

Boston

Min Chuan 2nd Road

Kaohsiung 806, Taiwan

Tel: 886-7-536-4818

Fax: 886-7-536-4803

China - Chengdu

2 Lan Drive, Suite 120

Westford, MA 01886

Tel: 978-692-3848

Fax: 978-692-3821

Rm. 2401-2402, 24th Floor,

Ming Xing Financial Tower

No. 88 TIDU Street

Taiwan

Chengdu 610016, China

Tel: 86-28-86766200

Taiwan Branch

Chicago

11F-3, No. 207

333 Pierce Road, Suite 180

Itasca, IL 60143

Fax: 86-28-86766599

Tung Hua North Road

Taipei, 105, Taiwan

Tel: 886-2-2717-7175 Fax: 886-2-2545-0139

China - Fuzhou

Tel: 630-285-0071

Fax: 630-285-0075

Unit 28F, World Trade Plaza

No. 71 Wusi Road

Dallas

Fuzhou 350001, China

Tel: 86-591-7503506

Fax: 86-591-7503521

EUROPE

4570 Westgrove Drive, Suite 160

Addison, TX 75001

Tel: 972-818-7423

Fax: 972-818-2924

Austria

Durisolstrasse 2

China - Hong Kong SAR

A-4600 Wels

Unit 901-6, Tower 2, Metroplaza

223 Hing Fong Road

Austria

Detroit

Tel: 43-7242-2244-399

Fax: 43-7242-2244-393

Denmark

Kwai Fong, N.T., Hong Kong

Tel: 852-2401-1200

Tri-Atria Office Building

32255 Northwestern Highway, Suite 190

Farmington Hills, MI 48334

Tel: 248-538-2250

Fax: 852-2401-3431

Regus Business Centre

Lautrup hoj 1-3

China - Shanghai

Room 701, Bldg. B

Fax: 248-538-2260

Ballerup DK-2750 Denmark

Tel: 45-4420-9895 Fax: 45-4420-9910

Far East International Plaza

No. 317 Xian Xia Road

Shanghai, 200051

Kokomo

France

2767 S. Albright Road

Kokomo, IN 46902

Tel: 765-864-8360

Fax: 765-864-8387

Parc d’Activite du Moulin de Massy

43 Rue du Saule Trapu

Batiment A - ler Etage

91300 Massy, France

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

Tel: 86-21-6275-5700

Fax: 86-21-6275-5060

China - Shenzhen

Los Angeles

Rm. 1812, 18/F, Building A, United Plaza

No. 5022 Binhe Road, Futian District

Shenzhen 518033, China

Tel: 86-755-82901380

18201 Von Karman, Suite 1090

Irvine, CA 92612

Germany

Tel: 949-263-1888

Steinheilstrasse 10

D-85737 Ismaning, Germany

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Fax: 949-263-1338

Fax: 86-755-8295-1393

Phoenix

China - Shunde

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7966

Fax: 480-792-4338

Room 401, Hongjian Building

No. 2 Fengxiangnan Road, Ronggui Town

Shunde City, Guangdong 528303, China

Tel: 86-765-8395507 Fax: 86-765-8395571

Italy

Via Quasimodo, 12

20025 Legnano (MI)

Milan, Italy

China - Qingdao

San Jose

Tel: 39-0331-742611

Fax: 39-0331-466781

Netherlands

2107 North First Street, Suite 590

San Jose, CA 95131

Tel: 408-436-7950

Rm. B505A, Fullhope Plaza,

No. 12 Hong Kong Central Rd.

Qingdao 266071, China

Fax: 408-436-7955

Tel: 86-532-5027355 Fax: 86-532-5027205

P. A. De Biesbosch 14

NL-5152 SC Drunen, Netherlands

Tel: 31-416-690399

India

Toronto

Divyasree Chambers

1 Floor, Wing A (A3/A4)

No. 11, O’Shaugnessey Road

Bangalore, 560 025, India

Tel: 91-80-2290061 Fax: 91-80-2290062

Japan

6285 Northam Drive, Suite 108

Mississauga, Ontario L4V 1X5, Canada

Tel: 905-673-0699

Fax: 31-416-690340

United Kingdom

505 Eskdale Road

Fax: 905-673-6509

Winnersh Triangle

Wokingham

Berkshire, England RG41 5TU

Tel: 44-118-921-5869

Fax: 44-118-921-5820

Benex S-1 6F

3-18-20, Shinyokohama

Kohoku-Ku, Yokohama-shi

Kanagawa, 222-0033, Japan

Tel: 81-45-471- 6166 Fax: 81-45-471-6122

07/28/03

DS21203K-page 26

 2003 Microchip Technology Inc.


型号：	24FC256T-E/ST14
厂家：	MICROCHIP
描述：	32K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO14, 4.40 MM, PLASTIC, MO-153, TSSOP-14 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟光电二极管内存集成电路
文件：	总26页 (文件大小：624K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

24FC256T-E/ST14 [MICROCHIP]

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