24CS512T-I/OT [MICROCHIP]
512-Kbit, 3.4MHz I2C Serial EEPROM with 128-Bit Serial Number and Enhanced Software Write Protection;型号: | 24CS512T-I/OT |
厂家: | MICROCHIP |
描述: | 512-Kbit, 3.4MHz I2C Serial EEPROM with 128-Bit Serial Number and Enhanced Software Write Protection 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
文件: | 总66页 (文件大小:1575K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
24CS512
2
512-Kbit, 3.4 MHz I C Serial EEPROM with 128-Bit Serial Number
and Enhanced Software Write Protection
Features
Packages
• 512-Kbit EEPROM:
• 8-Lead MSOP, PDIP, SOIC, SOIJ, TSSOP,
8-Pad UDFN, 5-Lead SOT-23 and 8-Ball CSP
- Internally organized as one 65,536 x 8-bit block
- Byte or page writes up to 128 bytes
- Byte or sequential reads within a block
- Self-timed write cycle (5 ms maximum)
• High-Speed I2C Interface:
Package Types (not to scale)
8-Lead MSOP/PDIP/SOIC/
SOIJ/TSSOP
5-lead SOT-23
(Top View)
(Top View)
- High-Speed mode support for 3.4 MHz
A0
A1
1
8
VCC
WP
WP
SCL 1
5
4
- Industry standard: 1 MHz, 400 kHz and
100 kHz
VSS
2
3
2
3
4
7
6
5
VCC
SDA
- Output slope control to eliminate ground
bounce
SCL
SDA
A2
VSS
- Schmitt Trigger inputs for noise suppression
• Security Register:
8-Pad UDFN
(Top View)
8-Ball CSP
(Top View)
- Preprogrammed 128-bit serial number
- User-programmable, lockable
128-byte ID page
A0
VCC
VCC
1
8
7
6
5
WP
A0
A1 2
A2 3
WP
A1
SCL
• Built-in Error Correction Code (ECC) Logic:
- ECC Status bit via the Configuration register
• I2C Manufacturer Identification Function Support
• Versatile Data Protection Options:
SCL
SDA
A2
VSS
SDA
VSS
4
- Hardware Write-Protect (WP) pin for full array
data protection
Pin Function Table
Name
Function
- Enhanced software write protection via the
Configuration register
A0
A1
Device Address Input
Device Address Input
Device Address Input
Ground
• Operating Voltage Range of 1.7V to 5.5V
• Low-Power CMOS Technology:
A2
- Write current: 3.0 mA maximum at 5.5V
VSS
SDA
SCL
WP
VCC
- Read current: 1.0 mA maximum at 5.5V,
1 MHz
Serial Data Pin
Serial Clock Input
Write-Protect Pin
Supply Voltage
- Standby current: 1 µA at 5.5V (I-Temp.)
• High Reliability:
- More than one million erase/write cycles
- Build-in ECC logic for increased reliability
- Data retention: >200 years
- ESD protection: >4000V
• RoHS Compliant
• Temperature Ranges:
- Industrial (I): -40°C to +85°C
- Extended (E): -40°C to +125°C
2018-2021 Microchip Technology Inc.
DS20005769C-page 1
24CS512
The device also contains a Configuration register,
which allows the write protection behavior to be
configured for legacy hardware write protection or
enhanced software write protection which allows the
user to protect any of the eight independent 64-Kbit
zones. Once the desired configuration is set, the
Configuration register can be permanently locked,
thereby preventing any further changes to the device
operation.
Description
The Microchip Technology Inc. 24CS512 provides
512 Kbits of Serial EEPROM, utilizing an I2C (two-wire)
serial interface with 3.4 MHz High-Speed mode
capability. The device is organized as 65,536 bytes of
8 bits each (64 Kbytes) and is optimized for use in
consumer and industrial applications where reliable
and dependable nonvolatile memory storage is
essential. The 24CS512 allows up to eight devices to
share a common I2C (two-wire) bus and is capable of
operation across a broad voltage range (1.7V to 5.5V).
For added reliability, the 24CS512 utilizes a built-in
Error Correction Code (ECC) scheme. This scheme
can correct up to one incorrectly read bit within a
four-byte read out. Additionally, the Configuration
register includes a read-only ECC State bit (ECS) that
is set when ECC is invoked.
The 24CS512 supports the I2C Manufacturer Identifica-
tion (ID) command which will return a unique value for
the 24CS512, allowing easy identification within the
application.
The 24CS512 features a 2-Kbit Security register, sepa-
rate from the 512-Kbit memory array. The first half of the
Security register is read-only and contains a factory-pro-
grammed, ensured unique, 128-bit serial number in the
first 16 bytes. The 128-bit serial number is unique across
the entire CS series of Serial EEPROM products and
eliminates the time-consuming step of performing and
ensuring serialization of a product on a manufacturing
line. The 128-bit read-only serial number is followed by
an additional 1 Kbit (128 bytes) of user-programmable
EEPROM. The user-programmable section of the Secu-
rity register can later be permanently write-protected via
a software sequence.
System Configuration Using Serial EEPROMs
VCC
tR(max)
RPUP(max)
RPUP(min)
=
=
0.8473 CL
VCC – VOL
(max)
VCC
IOL
SCL
SDA
WP
I2C MCU
VCC
WP
VCC
WP
VCC
WP
A0
A0
A0
Client 0
Client 1
Client 7
A1
A1
A1
A2
24CSXXX
A2
24CSXXX
A2
24CSXXX
SDA
SCL
SDA
SCL
SDA
SCL
VSS
VSS
VSS
VSS
DS20005769C-page 2
2018-2021 Microchip Technology Inc.
24CS512
Block Diagram
Hardware
Address
Comparator
Power-on
Reset
enator
Memory
System Control
Module
VCC
A0
High-Voltage
Generation Circuit
Write
Protection
Control
WP
A1
EEPROM Array
1 page
Address Register
and Counter
Security Register
Column Decoder
A2
SCL
SDA
Data Register
Start
Stop
Detector
Data & ACK
Input/Output Control
DOUT
DIN
VSS
2018-2021 Microchip Technology Inc.
DS20005769C-page 3
24CS512
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)
VCC.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ...................................................................................................................-0.6V to 6.5V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature under bias.............................................................................................................-40°C to +125°C
ESD protection on all pins........................................................................................................................................≥4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
Electrical Characteristics:
DC CHARACTERISTICS
Industrial (I):
Extended (E):
VCC = 1.7V to 5.5V
VCC = 1.7V to 5.5V
TA = -40°C to +85°C
TA = -40°C to +125°C
Param.
Symbol
No.
Characteristic
Min.
Max.
Units
Test Conditions
D1
D2
D3
VIH
VIL
High-Level Input Voltage
Low-Level Input Voltage
Low-Level Output Voltage
VCC X 0.7
VCC + 1
V
V
V
V
V
-0.6
—
VCC X 0.3
VOL
0.4
0.2
—
IOL = 2.1 mA, VCC ≥ 2.5V
IOL = 0.15 mA, VCC < 2.5V
VCC ≥ 2.5V (Note 1)
—
D4
VHYS
Hysteresis of Schmitt
Trigger Inputs
VCC x 0.05
(SDA, SCL pins)
D5
D6
D7
ILI
ILO
Input Leakage Current
Output Leakage Current
—
—
—
±1
±1
7
µA
µA
pF
VIN = VSS or VCC
VOUT = VSS or VCC
CINT
Internal Capacitance
TAMB = +25°C, FCLK = 1 MHz,
(all inputs and outputs)
VCC = 5.5V (Note 1)
D8
D9
ICCREAD Operating Current
ICCWRITE Operating Current
—
—
—
—
1
3
1
1
mA VCC = 5.5V, FCLK = 1 MHz
mA VCC = 5.5V
mA VCC = 1.7V
D10
ICCS
Standby Current
µA
SCL = SDA = VCC = 5.5V, I-Temp.,
WP = VSS
—
3
µA
SCL = SDA = VCC = 5.5V, E-Temp.,
WP = VSS
Note 1: This parameter is not tested but ensured by characterization.
DS20005769C-page 4
2018-2021 Microchip Technology Inc.
24CS512
TABLE 1-2:
AC CHARACTERISTICS
Electrical Characteristics:
AC CHARACTERISTICS
Industrial (I):
Extended (E):
VCC = 1.7V to 5.5V
VCC = 1.7V to 5.5V
TA = -40°C to +85°C
TA = -40°C to +125°C
Param.
Symbol
No.
Characteristic
Clock Frequency
Min.
Max.
Units
Conditions
1
2
3
FCLK
—
—
1000
3400
kHz 1.7V ≤ VCC ≤ 5.5V
kHz 2.5V ≤ VCC ≤ 5.5V, I-Temp.,
HS Mode Enabled
THIGH Clock High Time
TLOW Clock Low Time
400
60
—
—
ns
ns
1.7V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V, I-Temp.,
HS Mode Enabled
400
160
—
—
ns
ns
1.7V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V, I-Temp.,
HS Mode Enabled
4
5
6
TR
TF
SDA and SCL Rise Time
SDA and SCL Fall Time
—
—
1000
300
—
ns
ns
ns
ns
1.7V ≤ VCC ≤ 5.5V (Note 1)
1.7V ≤ VCC ≤ 5.5V (Note 1)
1.7V ≤ VCC ≤ 5.5V
THD:STA Start Condition Hold Time
250
160
—
2.5V ≤ VCC ≤ 5.5V, I-Temp.,
HS Mode Enabled
7
TSU:STA Start Condition Setup Time
250
160
—
—
ns
ns
1.7V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V, I-Temp.,
HS Mode Enabled
8
9
THD:DAT Data Input Hold Time
TSU:DAT Data Input Setup Time
0
—
—
—
ns
ns
ns
(Note 2)
50
10
1.7V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V, I-Temp.,
HS Mode Enabled
10
TSU:STO Stop Condition Setup Time
250
160
—
—
ns
ns
1.7V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V, I-Temp.,
HS Mode Enabled
11
12
13
TSU:WP WP Setup Time
THD:WP WP Hold Time
600
1300
—
—
—
ns
ns
ns
ns
TAA
Output Valid from Clock
400
70
1.7V ≤ VCC ≤ 5.5V
—
2.5V ≤ VCC ≤ 5.5V, I-Temp.,
HS Mode Enabled
14
15
TBUF
TSP
Bus Free Time: Bus Time
must be Free before a New
Transmission can Start
500
—
ns
1.7V ≤ VCC ≤ 5.5V
Input Filter Spike Suppression
(SDA and SCL pins)
—
—
50
10
ns
ns
1.7V ≤ VCC ≤ 5.5V (Note 3)
2.5V ≤ VCC ≤ 5.5V, I-Temp.,
HS Mode Enabled (Note 3)
16
TWC
Write Cycle Time
(byte or page)
—
5
ms
Note 1: The rise/fall times must be less than the specified maximums in order to achieve the maximum clock fre-
quencies specified for FCLK. Please refer to the I2C specification for applicable timings.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region of
the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: Not 100% tested. CB = total capacitance of one bus line in pF.
2018-2021 Microchip Technology Inc.
DS20005769C-page 5
24CS512
FIGURE 1-1:
BUS TIMING DATA
5
4
D4
2
SCL
7
3
10
8
9
6
SDA
15
In
14
12
13
SDA
Out
(protected)
(unprotected)
WP
11
TABLE 1-3:
Operation
EEPROM CELL PERFORMANCE CHARACTERISTICS
Test Condition
Min.
Max.
Units
Write Endurance(1,2)
Data Retention(1)
TA = 25°C, 1.7V VCC 5.5V
1,000,000
200
—
—
Write Cycles
Years
TA = 55°C
Note 1: Performance is determined through characterization and the qualification process.
2: Due to the memory array architecture, the write cycle endurance is specified for write operations in groups
of four data bytes. The beginning of any 4-byte boundaries can be determined by multiplying any integer
(N) by four (i.e., 4*N). The end address can be found by adding three to the beginning value (i.e., 4*N+3).
See Section 6.3 “Internal Writing Methodology” for more details on this implementation.
DS20005769C-page 6
2018-2021 Microchip Technology Inc.
24CS512
The system designer must ensure that instructions are
not sent to the device until the VCC supply has reached
a stable value, greater than or equal to the minimum
VCC level. Additionally, once the VCC is greater than or
equal to the minimum VCC level, the host must wait at
least TPUP before sending the first command to the
device. See Table 1-4 for the values associated with
these power-up parameters.
1.1
Power-up Requirements and
Reset Behavior
During a power-up sequence, the VCC supplied to the
24CS512 should monotonically rise from VSS to the
minimum VCC level, as specified in Table 1-1, with a
slew rate no faster than 0.1 V/µs.
1.1.1
DEVICE RESET
If an event occurs in the system where the VCC level
supplied to the 24CS512 drops below the maximum
VPOR level specified, it is recommended that a
full-power cycle sequence be performed by first driving
the VCC pin to VSS, waiting at least the minimum TPOFF
time and then perform a new power-up sequence in
compliance with the requirements defined in
Section 1.1 “Power-up Requirements and Reset
Behavior”.
To prevent write operations or other spurious events
from happening during a power-up sequence, the
24CS512 includes a Power-on Reset (POR) circuit.
Upon power-up, the device will not respond to any
commands until the VCC level crosses the internal volt-
age threshold (VPOR) that brings the device out of
Reset and into Standby mode.
TABLE 1-4:
POWER-UP CONDITIONS
Parameter
Time Required after VCC is Stable before the Device can Accept Commands 100
Symbol
Min.
Max.
Units
TPUP
VPOR
TPOFF
—
1.5
—
µs
V
Power-on Reset Threshold Voltage
—
1
Minimum Time at VCC = 0V between Power Cycles
ms
2018-2021 Microchip Technology Inc.
DS20005769C-page 7
24CS512
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
PIN FUNCTION TABLE
8-Lead 8-Lead 8-Lead 8-Lead 8-Lead 5-Lead 8-Lead 8-Ball
Name
Function
MSOP
PDIP
SOIC
SOIJ
TSSOP SOT-23 UDFN(1)
CSP
A0
A1
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
—
—
—
2
1
2
3
4
5
6
7
8
A5
B4
C3
C5
C1
B2
A3
A1
Device Address Input
Device Address Input
Device Address Input
Ground
A2
VSS
SDA
SCL
WP
VCC
3
Serial Data
1
Serial Clock
5
Write-Protect
4
Device Power Supply
Note 1: The exposed pad on this package can be connected to VSS or left floating.
2.1
Device Address Inputs (A0, A1
and A2)
2.3
Serial Clock (SCL)
This input is used to synchronize the data transfer from
and to the device.
The A0, A1 and A2 inputs are used by the 24CS512 for
multiple device operations. The logic levels on these
inputs are compared with the corresponding bits in the
client address. The chip is selected if the compare is true.
2.4
Write-Protect (WP)
This pin must be connected to either VSS or VCC. If tied
to VSS, write operations to the memory array and
Security register are enabled. If tied to VCC, write
operations to the memory array and Security register are
inhibited, but read operations are not affected.
Up to eight devices may be connected to the same bus
by using different hardware client address bit combina-
tions. These inputs must be connected to either VCC or
VSS.
In most applications, the device address inputs, A0, A1
and A2, are hard-wired to logic ‘0’ or logic ‘1’. For
applications in which these pins are controlled by a
microcontroller or other programmable logic device,
the device address pins must be driven to a logic ‘0’ or
a logic ‘1’ before normal device operation can proceed.
Note:
This pin is ignored when using Enhanced
Software Write Protection mode and
should be tied to either VCC or VSS.
2.2
Serial Data (SDA)
This is a bidirectional pin used to transfer addresses
and data into and out of the device. It is an open-drain
terminal; therefore, the SDA bus requires a pull-up
resistor to VCC (typically 10 kΩ for 100 kHz, 2 kΩ for
400 kHz and 1 MHz and 330Ω for 3.4 MHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
DS20005769C-page 8
2018-2021 Microchip Technology Inc.
24CS512
3.2.2
The Security register is split into a read-only section and
user-programmable lockable, identification page
SECURITY REGISTER
3.0
3.1
MEMORY ORGANIZATION
EEPROM Organization
a
section. The read-only section contains a prepro-
grammed, ensured unique, 128-bit serial number. The
user-programmable (lockable ID page) section of the
Security register is ideal for applications that need to
irreversibly protect critical or sensitive application data
from ever being altered. For more details about the
Security register, refer to Section 10.0 “Security
Register”.
The 24CS512 is internally organized as 512 pages of
128 bytes each.
3.2
Device Registers
The 24CS512 contains three types of registers that
modulate device operation and/or report on the current
status of the device. These registers are:
• Configuration register
• Security register
• Manufacturer ID register
3.2.3
MANUFACTURER ID REGISTER
The Manufacturer ID register is a read-only 24-bit
register that contains data in compliance with the I2C
Manufacturer ID sequence. The 24-bit value returned
is unique to the 24CS512. Refer to Section 11.0
“Manufacturer Identification Register” for more
details.
3.2.1
CONFIGURATION REGISTER
The Configuration register allows for modification of the
device write protection behavior, as well as additional
device features. Once the device behavior is set as
desired, the Configuration register can be permanently
locked (or set to read-only), thereby preventing any
subsequent changes. Refer to Section 9.0 “Configu-
ration Register” for additional information on the
Configuration register.
FIGURE 3-1:
MEMORY ORGANIZATION
Memory Address Range
Protection Features
Legacy Protection Mode
•
•
Full Array Write Protection
via the Write-Protect Pin
512-Kbit
EEPROM
512-Kbit Address Range:
0000h-FFFFh
Enhanced Protection Mode
Individual Zone Protection
Based on Contents of
Configuration Register
128-Bit Serial Number
Address Range (0800h-080Fh)
Reserved for Future Use
Address Range (0810h-087Fh)
Read-Only
2-Kbit
Security
Register
User-Programmable Lockable ID Page
Address Range (0880h-08FFh)
Permanently Lockable by
Software
2018-2021 Microchip Technology Inc.
DS20005769C-page 9
24CS512
The 7-bit client address can be constructed in two
ways. Most communications utilize a 4-bit device type
identifier, followed by a 3-bit hardware client address.
Additionally, the 24CS512 can accept a reserved 7-bit
host code, which is then followed by a device type iden-
tifier and hardware client address. This 7-bit host code
enables access to different modes of operation within
the device.
3.3
Device Addressing
Communication with the 24CS512 begins with an 8-bit
device address byte, comprised of a 7-bit client
address and a Read/Write Select (R/W) bit. Since mul-
tiple client devices can reside on the serial bus, each
client device must have its own unique address so that
the host can access each device independently.
TABLE 3-1:
Bit 7
DEVICE ADDRESS BYTE STRUCTURE
Bit 6 Bit 5 Bit 4 Bit 3
4-Bit Device Type Identifier 3-Bit Hardware Client Address
7-Bit Reserved Host Code
Bit 2
Bit 1
Bit 0
Read/Write
Select
The 24CS512 will respond to only specific device type
identifiers, as shown in Section 3.3.1 “Valid Device
Address Byte Inputs”.
The 3-bit hardware client address is comprised of bits
A2, A1 and A0. These bits can be used to expand the
address space by allowing up to eight devices with the
same device type identifiers on the bus. These hard-
ware client address bits must correlate with the logic
level on the corresponding hardwired device address
input pins, A2, A1 and A0.
The device will respond to all valid device address byte
combinations that it receives, except for cases where
the host code sequence specifically calls for no
response.
DS20005769C-page 10
2018-2021 Microchip Technology Inc.
24CS512
3.3.1
VALID DEVICE ADDRESS BYTE
INPUTS
The 24CS512 will respond to two different device type
identifiers, as well as two reserved host codes as
shown in Table 3-2.
TABLE 3-2:
TABLE OF VALID DEVICE ADDRESS BYTES
Device Address
Byte Type
Access Region
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
512-Kbit EEPROM(1)
Security Register(1,2)
Configuration Register(1,2)
Manufacturer Identification(3)
High-Speed (HS) Mode(4)
1
1
1
1
0
0
0
0
1
0
1
1
1
1
0
0
1
1
1
0
A2
A2
A2
1
A1
A1
A1
0
A0
A0
A0
0
R/W
R/W
R/W
R/W
X
Device Type Identifier +
Hardware Address
Reserved Host Code
1
X
X
Note 1: The hardware client address bits must be set to logic ‘0’ when using the SOT-23 package.
2: Accessing the Security or Configuration register is only possible if any sequence or command to the main
EEPROM (if one has been sent) has been properly terminated with a Stop condition. Without proper termi-
nation of the previous sequence, all communications with the Security or Configuration registers will not
execute successfully.
3: See Section 11.0 “Manufacturer Identification Register” for details.
4: See Section 8.0 “High-Speed Mode” for details.
Upon the successful comparison of the device address
byte, the 24CS512 will respond. If a valid comparison
is not made, the device will not respond and will return
to a standby state.
3.3.1.1
Read/Write Select Bit
The eighth bit (bit 0) of the device address byte is the
Read/Write Select (R/W) bit. A read operation is initi-
ated if this bit is a logic ‘1’ and a write operation is initi-
ated if this bit is a logic ‘0’.
2018-2021 Microchip Technology Inc.
DS20005769C-page 11
24CS512
Next, the second word address byte is sent to the
device, which provides the remaining eight bits of the
word address (A7 through A0). Refer to Table 3-4 for
details.
3.3.2
WORD ADDRESS BYTES
Two 8-bit word address bytes are transmitted to the
device immediately following the device address byte.
The first word address byte contains the eight Most
Significant bits (MSbs) of the 16-bit memory array word
address to specify which location in the EEPROM to
start reading or writing. When accessing the Security
register, it is required that the A15 bit of the first word
address be set to a logic ‘0’, and the A11 and A10 bits
be set to ‘10b’, respectively. When accessing the
Configuration register, it is required that the A15 bit of
the first word address be set to a logic ‘1’, and the A11
and A10 bits be set to ‘10b’, respectively. Refer to
Table 3-3 for details.
TABLE 3-3:
FIRST WORD ADDRESS BYTE
Memory Region
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
512-Kbit EEPROM
A15
0
A14
x
A13
x
A12
x
A11
1
A10
0
A9
x
A8
x
Security Register Read/Write
Lock Security Register
Configuration Register
x
x
x
x
0
1
1
0
1
x
x
x
1
0
x
x
TABLE 3-4:
SECOND WORD ADDRESS BYTE
Memory Region
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
512-Kbit EEPROM
A7
A7
x
A6
A6
x
A5
A5
x
A4
A4
x
A3
A3
x
A2
A2
x
A1
A1
x
A0
A0
x
Security Register Read/Write
Lock Security Register(1)
Configuration Register(1)
x
x
x
x
x
x
x
x
Note 1: When accessing the Configuration register or locking the Security register, the second word address byte
must be transmitted to the device, despite containing only don’t care values.
DS20005769C-page 12
2018-2021 Microchip Technology Inc.
24CS512
5.4
Data Valid (D)
4.0
FUNCTIONAL DESCRIPTION
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The 24CS512 supports a bidirectional two-wire bus
and data transmission protocol. A device that sends
data onto the bus is defined as a transmitter and a
device receiving data as a receiver. The bus must be
controlled by a host device which generates the
Serial Clock (SCL), controls the bus access and
generates the Start and Stop conditions, while the
24CS512 works as a client. Both host and client can
operate as a transmitter or receiver, but the host
determines which mode is activated.
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the host device.
5.0
BUS CHARACTERISTICS
5.5
Acknowledge
The following bus protocol has been defined:
Each receiving device, when addressed, is obliged to
generate an Acknowledge (ACK) signal after the recep-
tion of each byte. The host device must generate an
extra clock pulse, which is associated with this
Acknowledge bit. See Figure 5-2 for Acknowledge
timing.
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line, while the clock line is high, will be
interpreted as a Start or Stop condition.
Note:
The 24CS512 does not generate any
Acknowledge bits if an internal write cycle
is in progress.
Accordingly, the following bus conditions have been
defined (Figure 5-1).
A device that acknowledges must pull down the SDA
line during the Acknowledge clock pulse in such a way
that the SDA line is stable low during the high period of
the Acknowledge related clock pulse. Of course, setup
and hold times must be taken into account. During read
operations, the host must signal an end of data to the
client by NOT generating an Acknowledge (NACK) bit
on the last byte that has been clocked out of the client.
In this case, the client (24CS512) will leave the data
line high to enable the host to generate the Stop
condition.
5.1
Bus Not Busy (A)
Both data and clock lines remain high.
5.2
Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
5.3
Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must end with a Stop condition.
FIGURE 5-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)
(B)
(D)
(D)
(C) (A)
SCL
SDA
Start
Condition
Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition
2018-2021 Microchip Technology Inc.
DS20005769C-page 13
24CS512
FIGURE 5-2:
ACKNOWLEDGE TIMING
Acknowledge
Bit
1
2
3
4
5
6
7
8
9
1
2
3
SCL
SDA
Data from Transmitter
Data from Transmitter
Transmitter must release the SDA line at this point,
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
Receiver must release the SDA line
at this point, so the Transmitter can
continue sending data.
5.6
Standby Mode
5.7
Software Reset
The 24CS512 features a low-power Standby mode,
which is enabled when any one of the following occurs:
After an interruption in protocol, power loss or system
Reset, any two-wire device can be protocol Reset by
clocking SCL until SDA is released by the EEPROM
and goes high. The number of clock cycles until SDA is
released by the EEPROM will vary. The Software Reset
sequence should not take more than nine dummy clock
cycles. Note that the Software Reset sequence will not
interrupt the internal write cycle and only resets the I2C
interface.
• A valid power-up sequence is performed (see
Section 1.1 “Power-up Requirements and
Reset Behavior”).
• A Stop condition is received by the device unless
it initiates an internal write cycle (see Section 6.0
“Write Operations”).
• At the completion of an internal write cycle (see
Section 6.0 “Write Operations”).
Once the Software Reset sequence is complete, new
protocol can be sent to the device by sending a Start
condition, followed by the protocol. Figure 5-3
illustrates the Software Reset sequence.
• An unsuccessful match of the device type identi-
fier or hardware client address in the device
address byte occurs (see Section 3.3 “Device
Addressing”).
In the event that the device is still non-responsive or
remains active on the SDA bus, a power cycle must be
used to reset the device (see Section 1.1.1 “Device
Reset”).
• The host does not acknowledge the receipt of a
data read out from the device; instead, it sends a
NACK response (see Section 7.0 “Read
Operations”).
FIGURE 5-3:
SOFTWARE RESET
Dummy Clock Cycles
SCL
SDA
1
2
3
8
9
SDA Released
by EEPROM
Device is
Software Reset
DS20005769C-page 14
2018-2021 Microchip Technology Inc.
24CS512
Upon receipt of the proper device address and the
word address bytes, the EEPROM will send an
Acknowledge. The device will then be ready to receive
the 8-bit data byte. Following the receipt of the data
byte, the EEPROM will respond with an Acknowledge.
The addressing device, such as a host, must then ter-
minate the write operation with a Stop condition. At that
time, the EEPROM will enter an internally self-timed
write cycle, which will be completed within TWC, while
the data byte is being programmed into the nonvolatile
EEPROM. All inputs are disabled during this write cycle
and the EEPROM will not respond until the write
operation is complete.
6.0
WRITE OPERATIONS
All write operations for the 24CS512 begin with the host
sending a Start condition, followed by a device address
byte with the R/W bit set to a logic ‘0’ and then by the
word address bytes. The data value(s) to be written to
the device immediately follow the word address bytes.
6.1
Byte Write
The 24CS512 supports the writing of a single 8-bit byte.
Selecting a data byte in the 24CS512 requires a 16-bit
word address.
If an attempt is made to write to a write-protected
portion of the array, no data will be written and the
device will immediately accept a new command.
FIGURE 6-1:
BYTE WRITE
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
SCL
Device Address Byte
A2 A1 A0
Word Address – Byte 0
SDA
1
0
1
0
0
0
A15 A14 A13 A12 A11 A10 A9 A8
MSb
0
MSb
Start
by
Host
ACK
from
Client
ACK
from
Client
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
Word Address – Byte 1
Data Byte
A7 A6 A5 A4 A3 A2 A1 A0
MSb
0
D7 D6 D5 D4 D3 D2 D1 D0
MSb
0
ACK
from
Client
ACK
from
Stop
by
Client Host
2018-2021 Microchip Technology Inc.
DS20005769C-page 15
24CS512
The lower seven bits of the word address are internally
incremented following the receipt of each data byte.
The higher order address bits are not incremented and
retain the memory page location.
6.2
Page Write
A page write operation allows up to 128 bytes to be
written in the same write cycle, provided all bytes are in
the same physical page of the memory array (where
address bits A15 through A7 are the same). Partial
page writes of less than 128 bytes are also allowed.
When the incremented word address reaches the page
boundary, the internal Address Pointer will roll over to
the beginning of the same page.
A page write is initiated the same way as a byte write,
but the host does not send a Stop condition after the
first data byte is clocked in.
Note:
Page write operations are limited to writing
bytes within single physical page,
a
regardless of the number of bytes actually
being written. Physical page boundaries
start at addresses that are integer multiples
of the page buffer size (or ‘page size’) and
end at the addresses that are integer
multiples of [page size – 1]. If a page write
operation attempts to write across a physi-
cal page boundary, the result is that the
data wraps around to the beginning of the
current page (overwriting data previously
stored there), instead of being written to the
next page as might be expected. It is there-
fore necessary for the application software
to prevent page write operations that would
attempt to cross a page boundary.
Instead, after the EEPROM acknowledges receipt of
the first data byte, the host can transmit up to
127 additional data bytes. The EEPROM will respond
with an ACK after each data byte is received.
Once all data to be written has been sent to the device,
the host must issue a Stop condition (see Figure 6-2).
Once the Stop condition is received, an internal write
cycle will begin.
If an attempt is made to write to a write-protected por-
tion of the array, no data will be written and the device
will immediately accept a new command.
FIGURE 6-2:
SCL
PAGE WRITE
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
Device Address Byte
Word Address – Byte 0
1
0
1
0
A2 A1 A0
0
0
A15 A14 A13 A12 A11 A10 A9 A8
0
SDA
MSb
MSb
MSb
Start by
Host
ACK
from
ACK
from
Client
Client
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
Data Byte (n+x), Max.
of 128 without Roll Qver
Word Address – Byte 1
Data Byte (n)
A7 A6 A5 A4 A3 A2 A1 A0
MSb
0
D7 D6 D5 D4 D3 D2 D1 D0
0
D7 D6 D5 D4 D3 D2 D1 D0
MSb
0
MSb
Stop by
Host
ACK
from
Client
ACK
from
Client
ACK
from
Client
DS20005769C-page 16
2018-2021 Microchip Technology Inc.
24CS512
The system designer needs to optimize the application
writing algorithms to observe these internal word
boundaries in order to reach the write cycle endurance
rating.
6.3
Internal Writing Methodology
The 24CS512 incorporates a built-in Error Correction
Code (ECC) logic scheme. The EEPROM array is inter-
nally organized as a group of four connected 8-bit bytes,
plus an additional six ECC (Error Correction Code) bits
of EEPROM. These 38 bits are referred to as the internal
physical data word. During a read operation, the ECC
logic compares each 4-byte physical data word with its
corresponding six ECC bits. If a single bit out of the
4-byte region reads incorrectly, the ECC logic will detect
the bad bit and replace it with the correct value before
the data is serially clocked out. This architecture signifi-
cantly improves the reliability of the 24CS512 compared
to an implementation that does not utilize ECC.
6.4
Write Cycle Timing
The length of the self-timed write cycle, or TWC, is
defined as the amount of time from the Stop condition,
that begins the internal write operation, to the Start con-
dition of the first device address byte sent to the
24CS512 that it subsequently responds to with an ACK
(see Figure 6-3).
During the internally self-timed write cycle, any
attempts to access the device will be ignored.
It is important to note that data is always physically
written to the part at the internal physical data word level,
regardless of the number of bytes written. Writing single
bytes is still possible with the byte write operation, but
internally, the other three bytes within that 4-byte loca-
tion where the single byte was written, along with the six
ECC bits, will be updated. Due to this architecture, the
write endurance is rated at the internal physical data
word level (4-byte word).
FIGURE 6-3:
WRITE CYCLE TIMING
SCL
SDA
8
9
9
Data Word n
D0
ACK
ACK
First Acknowledge from the device to
a valid device address sequence after
write cycle is initiated. The minimum
Twc can only be determined through
the use of an ACK polling routine.
TWC
Stop
Condition
Start
Condition
Stop
Condition
2018-2021 Microchip Technology Inc.
DS20005769C-page 17
24CS512
6.5
Acknowledge Polling
6.6
Write Protection
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a write opera-
tion has been issued from the host, the device initiates
the internally timed write cycle. ACK polling can be
initiated immediately. This involves the host sending a
Start condition, followed by the device address byte for a
write operation (R/W = 0). If the device is still busy with
the write cycle, then a NACK will be returned. If a NACK
is returned, then the Start condition and device address
byte must be resent. If the cycle is complete, then the
device will return the ACK and the host can then proceed
with the next read or write operation. See Figure 6-4 for
flow diagram.
The 24CS512 can be set in two different Write Protec-
tion modes. The selection between the two modes is
controlled by the Configuration register EWPM bit.
When this bit is a logic ‘0’, the device is set in Legacy
Hardware Write Protection mode and when the bit is a
logic ‘1’, the device is set for Enhanced Software Write
Protection mode.
6.6.1
LEGACY HARDWARE WRITE
PROTECTION MODE
When the EWPM bit is set to logic ‘0’, the 24CS512
utilizes a legacy hardware data protection scheme that
allows the user to write-protect the entire memory
contents when the WP pin is asserted (high). No write
protection will be set if the WP pin is deasserted (low).
Note:
Polling, while operating in High-Speed
mode, is not supported on the 24CS512.
Therefore, polling must occur while using
Fast mode plus (1 MHz) or slower clock
frequencies.
Note:
Writing to the Security register can be
inhibited by asserting the Write-Protect
pin regardless of the state of the EWPM
bit. Writing to the Configuration register
cannot be inhibited by asserting the
Write-Protect pin.
FIGURE 6-4:
ACKNOWLEDGE
POLLING FLOW
TABLE 6-1:
LEGACY HARDWARE WRITE
PROTECTION BEHAVIOR
Send
Write Operation
WP Pin
Protected Address Range
1 (high)
0 (low)
Full Array (0000h-FFFFh)
None
Send Stop
Condition to
Initiate Write Cycle
6.6.1.1
Write-Protect Pin Timing
The status of the WP pin is sampled at the Stop condi-
tion for every byte write or page write operation, prior to
the start of an internally self-timed write operation (see
Figure 1-1). Changing the WP pin state after the Stop
condition has been sent will not alter or interrupt the
execution of the write cycle.
Send Start
Send Device Address Byte
with R/W = 0
If an attempt is made to write to the device while the
WP pin has been asserted, the device will acknowl-
edge the device address, word address and data bytes,
but no write cycle will occur when the Stop condition is
issued and the device will immediately be ready to
accept a new read or write operation.
Did Device
Acknowledge
(ACK = 0)?
No
Yes
Next
Operation
DS20005769C-page 18
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24CS512
6.6.2
ENHANCED SOFTWARE WRITE
PROTECTION MODE
When the EWPM bit is set to logic ‘1’, the 24CS512 is
configured for a versatile software write protection
scheme by segmenting the EEPROM array into eight
independent 64-Kbit zones (see Table 6-2). Each of the
eight zones can be write-protected by programming the
corresponding bit in the Configuration register. The
protection behavior can be made permanent by locking
the Configuration register (see Section 9.5 “Locking
the Configuration Register” for additional details).
Note:
Enhanced software write protection does
not affect write operations to the Security
and Configuration registers.
TABLE 6-2:
24CS512 ZONE PROTECTION CONTROL
Configuration Register Bit
Protected Zone
Protected Address Range
SWP7
SWP6
SWP5
SWP4
SWP3
SWP2
SWP1
SWP0
7
6
5
4
3
2
1
0
E000h-FFFFh
C000h-DFFFh
A000h-BFFFh
8000H-9FFFh
6000h-7FFFh
4000h-5FFFh
2000h-3FFFh
0000h-1FFFh
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DS20005769C-page 19
24CS512
A current address read operation will output data
according to the location of the internal Address
Pointer. This is initiated with a Start condition, followed
by a valid device address byte with the R/W bit set to
logic ‘1’. The device will ACK this sequence and the
current address data byte is serially clocked out on the
SDA line. All types of read operations will be terminated
if the host does not respond with an ACK (it NACKs)
during the ninth clock cycle, which will force the device
into Standby mode. After the NACK response, the host
may send a Stop condition to complete the protocol or
it can send a Start condition to begin the next
sequence.
7.0
READ OPERATIONS
Read operations are initiated the same way as write
operations, with the exception that the Read/Write
Select (R/W) bit in the device address byte must be a
logic ‘1’. There are three read operations:
• Current Address Read
• Random Address Read
• Sequential Read
7.1
Current Address Read
The 24CS512 contains an internal Address Pointer that
maintains the word address of the last byte accessed,
internally incremented by one. Therefore, if the previ-
ous read access was to address ‘n’ (n is any legal
address), the next current address read operation
would access data from address ‘n+1’.
FIGURE 7-1:
CURRENT ADDRESS READ
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
SCL
Device Address Byte
A2 A1 A0
Data Byte (n)
SDA
1
0
1
0
1
0
D7 D6 D5 D4 D3 D2 D1 D0
MSb
1
MSb
Start
ACK
from
Client
NACK Stop
by
from
Host
by
Host
Host
DS20005769C-page 20
2018-2021 Microchip Technology Inc.
24CS512
internal Address Pointer is set. Then, the host issues
the device address byte again but with the R/W bit set
to a logic ‘1’. The 24CS512 will then issue an
Acknowledge and transmit the 8-bit data byte. The host
will not acknowledge the transfer, but does generate a
Stop condition which causes the 24CS512 to
discontinue transmission (Figure 7-2). After a random
read operation, the internal Address Pointer will point to
the last word address location incremented by one.
7.2
Random Read
Random read operations allow the host to access any
memory location in a random manner. To perform this
type of read operation, first the word address must be
set. This is done by sending the word address to the
24CS512 as part of a write operation (R/W bit set
to ‘0’). After the word address is sent, the host
generates a Start condition following the Acknowledge.
This terminates the write operation, but not before the
FIGURE 7-2:
RANDOM READ
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
SCL
Device Address Byte
Word Address – Byte 0
Word Address – Byte 1
SDA
1
0
1
0
A2 A1 A0
0
0
A15 A14 A13 A12 A11 A10 A9 A8
MSb
0
A7 A6 A5 A4 A3 A2 A1 A0
MSb
0
MSb
Start by
Host
ACK
from
Client
ACK
from
Client
ACK
from
Client
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
Device Address Byte
Data Byte (n)
1
0
1
0
A2 A1 A0
1
0
D7 D6 D5 D4 D3 D2 D1 D0
MSb
0
MSb
Stop by
Host
Start by
Host
ACK
from
Client
NACK
from
Host
2018-2021 Microchip Technology Inc.
DS20005769C-page 21
24CS512
All types of read operations will be terminated if the
host does not respond with an ACK (it NACKs) during
the ninth clock cycle, which will force the device into
Standby mode. After the NACK response, the host may
send a Stop condition to complete the protocol or it can
send a Start condition to begin the next sequence.
7.3
Sequential Read
A sequential read is initiated by either a current
address read or a random read. After the host receives
a data byte, the host responds with an Acknowledge.
As long as the EEPROM receives an ACK, it will con-
tinue to increment the word address and serially clock
out the sequential data byte. When the maximum mem-
ory address is reached, the internal Address Pointer
will automatically roll over from word address, FFFFh,
to word address, 0000h, if the host acknowledges the
byte received from the word address FFFFh.
FIGURE 7-3:
SEQUENTIAL READ
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
SCL
Device Address Byte
Word Address – Byte 0
Word Address – Byte 1
1
0
1
0
A2 A1 A0
0
0
A15 A14 A13 A12 A11 A10 A9 A8
MSb
0
A7 A6 A5 A4 A3 A2 A1 A0
MSb
0
SDA
MSb
Start by
Host
ACK
from
Client
ACK
from
Client
ACK
from
Client
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
Device Address Byte
Data Byte (n)
Data Byte (n+1)
1
0
1
0
A2 A1 A0
1
0
D7 D6 D5 D4 D3 D2 D1 D0
MSb
0
D7 D6 D5 D4 D3 D2 D1 D0
MSb
0
MSb
Start by
Host
ACK
from
Client
ACK
from
Host
ACK
from
Host
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
Device Byte (n+2)
Data Byte (n+3)
Data Byte (n+x)
D7 D6 D5 D4 D3 D2 D1 D0
MSb
0
D7 D6 D5 D4 D3 D2 D1 D0
MSb
0
D7 D6 D5 D4 D3 D2 D1 D0
MSb
1
Stop by
Host
ACK
from
Host
ACK
from
Host
NACK
from
Host
DS20005769C-page 22
2018-2021 Microchip Technology Inc.
24CS512
(Table 8-1). The HS mode host code must be sent to
the device at Fast mode plus (1 MHz) or slower clock
frequencies. Since the HS mode host code is meant to
be recognized by all client devices that support the HS
mode, the 24CS512 will not acknowledge (NACK) the
HS mode host code.
8.0
HIGH-SPEED MODE
The 24CS512 supports the I2C High-Speed (HS) mode
allowing it to operate at clock frequencies up to
3.4 MHz for read and write operations.
In order to place the 24CS512 into HS mode, the host
must first initiate a Start condition, followed by the
reserved HS mode host code of ‘00001xxxb’
TABLE 8-1:
HIGH-SPEED MODE HOST CODE
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ACK Bit
0
0
0
0
1
x
x
x
NACK from Clients
Once the 24CS512 receives the HS mode host code
and the NACK occurs, the 24CS512 will relax its input
filters on SDA and SCL to the HS mode tolerance to
accept transfers, at up to 3.4 MHz. The device will then
enter HS mode and wait for a Repeated Start condition
before the next operation can occur.
Note:
The internal write cycle requires a Stop
condition to be sent after the last data
byte. This Stop condition will cause the
24CS512 to exit HS mode. Therefore, if
more than one page of data is to be
written, HS mode must be re-entered for
every write operation.
Next, the host must issue a Start condition, followed by
a valid device address byte to which the device will
ACK. The host can continue with read or write
operations at the higher clock speed and the 24CS512
will continue to operate in the HS mode until one of the
following events occurs:
Once the 24CS512 exits the HS mode from one of
these events, the device will switch its input and output
filters back to the standard I2C (Legacy) mode.
Figure 8-1 illustrates the HS mode entry sequence.
• The host sends a Stop condition. Therefore, the
host should use a Repeated Start condition to
begin new HS mode operations rather than a
Stop-Start sequence.
Note:
High-Speed mode entry is ignored during
a write cycle. Therefore, polling must
occur while using Fast mode plus (1 MHz)
or slower clock frequencies. Refer to
Section 6.5 “Acknowledge Polling” for
additional information. High-Speed mode
can be re-entered after the write cycle has
completed.
• A Power-on-Reset (POR) event occurs.
FIGURE 8-1:
HIGH-SPEED MODE ENTRY SEQUENCE
1
2
3
4
5
6
7
8
9
SCL
SDA
Host Code
0
0
0
0
1
x
x
x
1
MSb
Repeated
Start by
Host
Start
NACK
from
Client(s)
by
Host
2018-2021 Microchip Technology Inc.
DS20005769C-page 23
24CS512
Accessing this register requires the use of ‘1011b’ (Bh)
as the device type identifier in the device address (see
Table 9-1). Following the device type identifier are the
hardware client address bits for which the values are
determined by the device address input pins, A2, A1
and A0 (see Section 2.0 “Pin Descriptions”). Finally,
bit 0 is the Read/Write Select (R/W) bit, where a logic
‘1’ is used for reading and a logic ‘0’ is used for writing.
9.0
CONFIGURATION REGISTER
The 24CS512 device contains a 16-bit Configuration
register, which is accessed via a specific device
address and word address. If desired, the Configura-
tion register can be locked so that it is set to read-only
and can no longer be modified, thereby making the
current data protection scheme permanent.
When accessing the Configuration register, a 16-bit
word address must be sent to the device. All bits in the
word address are ignored except for bits A15, A11 and
A10. Bits A15 and A11 must be set to logic ‘1’ and bit
A10 must be set to logic ‘0’. Refer to Table 9-2 and
Table 9-3 for additional information.
9.1
Accessing the Configuration
Register
The value of the Configuration register can be
determined by executing a random read sequence to a
specific address. Changing the value of the Configura-
tion register is accomplished with a byte write sequence
with the requirements outlined later in this section.
TABLE 9-1:
CONFIGURATION REGISTER DEVICE ADDRESS BYTE
Device Type Identifier
Hardware Address Bits(1)
Read/Write
Bit 0
Memory Region
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Configuration Register
1
0
1
1
A2
A1
A0
R/W
Note 1: The hardware client address bits must be set to logic ‘0’ when using the SOT-23 package.
TABLE 9-2:
Word Address
Word Address Byte 0
CONFIGURATION REGISTER WORD ADDRESS BYTE 0
A15
A14
A13
A12
A11
A10
A9
A8
1
x
x
x
1
0
x
x
TABLE 9-3:
Word Address
Word Address Byte 1
CONFIGURATION REGISTER WORD ADDRESS BYTE 1
A7
A6
A5
A4
A3
A2
A1
A0
x
x
x
x
x
x
x
x
DS20005769C-page 24
2018-2021 Microchip Technology Inc.
24CS512
9.2
Configuration Register Format
Following the word address bytes are the contents of
the 16-bit Configuration register. The Configuration
register format and bit definitions are seen in
Register 9-1 for the first byte (Byte 0) and in
Register 9-2 for the second byte (Byte 1).
REGISTER 9-1:
CONFIGURATION REGISTER – BYTE 0
R-0
ECS
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W
R/W
EWPM
LOCK
bit 15
bit 8
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
ECS: Error Correction State bit
1 = The previously executed read operation did require the use of the Error Correction Code (ECC)
scheme
0 = The previously executed read operation did not require the use of the Error Correction Code
(ECC) scheme
bit 14-10
bit 9
Unimplemented: Read as ‘0’
EWPM: Enhanced Software Write Protection Mode bit
1 = Enhanced Protection: WP pin is treated as a don’t care and the memory array is protected in
accordance with the SWP bits defined in Register 9-2
0 = Legacy Protection (factory default): Entire memory array and Security register contents are
protected via the WP pin
bit 8
LOCK: Lock Configuration Register bit
1 = The Configuration register is set to read-only (permanent)
0 = The Configuration register can be written to (factory default)
Error Correction State bit (ECS): This bit is used
when the user needs to determine whether the on-chip
Error Correction Code (ECC) logic scheme has been
invoked. For more information related to ECC, refer to
Section 6.3 “Internal Writing Methodology”. The
ECS bit will be set to logic ‘0’ unless the previously exe-
cuted read operation required the use of the ECC logic
scheme. When this occurs, the ECS bit will set to logic
‘1’. The ECS bit will continue to read a logic ‘1’ until
another read operation is issued and the use of the
ECC logic scheme was not required or a Power-on
Reset (POR) event occurred.
Enhanced Software Write Protection is a software
write-protect feature where the memory array is divided
into eight separate 64-Kbit (8192-byte) zones. Each
zone is independent and is configured using the
SWP<7:0> bits (Register 9-2). For additional informa-
tion related to the write protection schemes, refer to
Section 6.6 “Write Protection”.
Lock Configuration Register bit (LOCK): This bit
allows the user to lock the Configuration register so that
it is set to read-only and can no longer be modified,
thereby making the current data protection scheme
permanent. Refer to Section 9.5 “Locking the Con-
figuration Register” for additional information on lock-
ing the Configuration register.
Enhanced Software Write Protection Mode bit
(EWPM): This bit is a feature in which the user can
select between Legacy Hardware Write Protection mode
(logic ‘0’) and Enhanced Software Write Protection
mode (logic ‘1’). Legacy Hardware Write Protection
mode allows the entire memory array to be write-pro-
tected via the WP pin.
2018-2021 Microchip Technology Inc.
DS20005769C-page 25
24CS512
REGISTER 9-2:
CONFIGURATION REGISTER – BYTE 1
R/W
R/W
SWP6
R/W
R/W
R/W
R/W
R/W
R/W
SWP7
SWP5
SWP4
SWP3
SWP2
SWP1
SWP0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
If EWPM = 1:
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SWP7: Software Write Protection Memory Zone 7 bit
1 = Memory Zone 7 (E000h-FFFFh) is write-protected
0 = Memory Zone 7 (E000h-FFFFh) is not write-protected
SWP6: Software Write Protection Memory Zone 6 bit
1 = Memory Zone 6 (C000h-DFFFh) is write-protected
0 = Memory Zone 6 (C000h-DFFFh) is not write-protected
SWP5: Software Write Protection Memory Zone 5 bit
1 = Memory Zone 5 (A000h-BFFFh) is write-protected
0 = Memory Zone 5 (A000h-BFFFh) is not write-protected
SWP4: Software Write Protection Memory Zone 4 bit
1 = Memory Zone 4 (8000h-9FFFh) is write-protected
0 = Memory Zone 4 (8000h-9FFFh) is not write-protected
SWP3: Software Write Protection Memory Zone 3 bit
1 = Memory Zone 3 (6000h-7FFFh) is write-protected
0 = Memory Zone 3 (6000h-7FFFh) is not write-protected
SWP2: Software Write Protection Memory Zone 2 bit
1 = Memory Zone 2 (4000h-5FFFh) is write-protected
0 = Memory Zone 2 (4000h-5FFFh) is not write-protected
SWP1: Software Write Protection Memory Zone 1 bit
1 = Memory Zone 1 (2000h-3FFFh) is write-protected
0 = Memory Zone 1 (2000h-3FFFh) is not write-protected
SWP0: Software Write Protection Memory Zone 0 bit
1 = Memory Zone 0 (0000h-1FFFh) is write-protected
0 = Memory Zone 0 (0000h-1FFFh) is not write-protected
If EWPM = 0:
bit 7-0
Unused
Software Write Protection Memory Zone bits
(SWP<7:0>): These bits divide the memory array into
eight separate 64-Kbit (8192-byte) zones. Each zone
can be set independently from the seven other protec-
tion zones. The corresponding SWP bit should be set
to a logic ‘1’ to write-protect that zone. All of the eight
SWP bits are set to logic ‘0’ as a factory default. For
additional information on the Software Write Protection
scheme, refer to Section 6.6.2 “Enhanced Software
Write Protection Mode”.
Note:
In Legacy Hardware Write Protection
mode (EWPM = 0), the SWP<7:0> bits
are ignored. However, a dummy value
must still be sent during the write
sequence to initiate the internal write
operation.
DS20005769C-page 26
2018-2021 Microchip Technology Inc.
24CS512
9.3
Writing to the Configuration
Register
Note:
Note:
Writing to the Configuration register can-
not be inhibited by asserting the
Write-Protect pin. Refer to Section 6.6
“Write Protection”, which describes the
device behavior with respect to the
Write-Protect pin status.
When writing to the Configuration register, a write
sequence must be sent to the device (see Section 6.1
“Byte Write” for additional information). The data
address values must be compliant with the values
found in Table 9-1, Table 9-2 and Table 9-3.
If an attempt is made to write to the Con-
figuration register after the Configuration
register has been locked, the device will
acknowledge the commands, but no write
cycle will occur, no data will be written and
the device will immediately accept a new
command.
In order for the internal write process to start, both data
bytes (Byte 0 and Byte 1), along with a confirmation
byte, need to be sent to the device. Sending anything
other than these three bytes will cause the write cycle
to abort and the contents of the Configuration register
will not be changed.
The data of the confirmation byte depends on the value
being written to the LOCK bit. If the user intends to lock
the Configuration register (LOCK = 1), the confirmation
byte must be 99h. If the user intends to leave the
register unlocked (LOCK = 0), the confirmation byte
must be 66h.
Table 9-4 illustrates the valid data values for the confir-
mation byte. Figure 9-1 illustrates the Configuration
register write sequence.
Note:
The Configuration register cannot be
unlocked once it is locked.
TABLE 9-4:
CONFIGURATION REGISTER CONFIRMATION BYTE
New LOCK Bit Value
D7
D6
D5
D4
D3
D2
D1
D0
1 (locked)
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
0 (unlocked)
FIGURE 9-1:
CONFIGURATION REGISTER WRITE SEQUENCE
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
SCL
Device Address Byte
Word Address – Byte 0
Word Address – Byte 1
1
0
1
1
A2 A1 A0
0
0
1
x
x
x
1
0
x
x
0
x
x
x
x
x
x
x
x
0
SDA
MSb
MSb
MSb
Start by
Host
ACK
from
Client
ACK
from
Client
ACK
from
Client
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
Configuration Register
Byte 0
Configuration Register
Byte 1
Configuration Register
Confirmation Byte
x
x
x
x
x
x
D9 D8
0
D7 D6 D5 D4 D3 D2 D1 D0
MSb
0
D7 D6 D5 D4 D3 D2 D1 D0
MSb
0
MSb
Stop by
Host
ACK
from
Client
ACK
from
Client
ACK
from
Client
2018-2021 Microchip Technology Inc.
DS20005769C-page 27
24CS512
9.4
Reading the Configuration
Register
Accessing the Configuration register is only possible if
any sequence or command to the EEPROM (if one has
been sent) has been properly terminated with a Stop
condition. Without proper termination of that previous
sequence, all communications with the Configuration
register will not execute successfully.
When reading the Configuration register, a random
read sequence must be sent to the device (see
Section 7.2 “Random Read” for additional informa-
tion). The address values must be compliant with the
values found in Table 9-1, Table 9-2 and Table 9-3.
Note:
The 24CS512 will automatically roll over
from the second Configuration register
data byte to the first data byte if the host
continues to acknowledge the data bytes
during the read operation.
Figure 9-2 illustrates the Configuration register read
sequence. It is not possible to read the contents of the
Configuration register with a current address read
sequence as the correct word address bytes must be
sent to the device.
Note:
If a Stop condition is issued after the word
address bytes, the read operation to the
Configuration register will not execute
properly.
FIGURE 9-2:
CONFIGURATION REGISTER READ SEQUENCE
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
SCL
Device Address Byte
Word Address – Byte 0
Word Address – Byte 1
1
0
1
1
A2 A1 A0
0
0
1
x
x
x
1
0
x
x
0
x
x
x
x
x
x
x
x
0
SDA
MSb
MSb
MSb
Start by
Host
ACK
from
Client
ACK
from
Client
ACK
from
Client
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
Configuration Register
Byte 0 Contents
Configuration Register
Byte 1 Contents
Device Address Byte
1
0
1
1
A2 A1 A0
1
0
D15
0
0
0
0
0
D9 D8
0
D7 D6 D5 D4 D3 D2 D1 D0
MSb
1
MSb
MSb
Stop by
Host
Start by
Host
ACK
from
Client
ACK
from
Host
NACK
from
Host
DS20005769C-page 28
2018-2021 Microchip Technology Inc.
24CS512
9.5
Locking the Configuration
Register
Note:
Note:
Once the Configuration register has been
locked, it cannot be unlocked.
The locking mechanism of the Configuration register is
controlled through the LOCK bit. The data of the confir-
mation byte depends on the value being written to the
LOCK bit. If the user intends to lock the Configuration
register (LOCK = 1), the confirmation byte must be 99h.
If the user intends to leave the register unlocked
(LOCK = 0), the confirmation byte must be 66h. A
mismatch of the LOCK bit and the confirmation byte will
cause the operation to abort. Refer to Table 9-4 for
additional information on the confirmation byte and the
LOCK bit. Figure 9-3 illustrates the Configuration regis-
ter lock sequence.
Locking the Configuration register cannot
be inhibited by asserting the Write-Protect
pin. Refer to Section 6.6 “Write Protec-
tion”, which describes the device behavior
with respect to the Write-Protect pin status.
FIGURE 9-3:
CONFIGURATION REGISTER LOCK SEQUENCE
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
SCL
Device Address Byte
Word Address – Byte 0
Word Address – Byte 1
1
0
1
1
A2 A1 A0
0
0
1
x
x
x
1
0
x
x
0
x
x
x
x
x
x
x
x
0
SDA
MSb
MSb
MSb
Start by
Host
ACK
from
Client
ACK
from
Client
ACK
from
Client
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
Configuration Register
Byte 1
Configuration Register
Byte 0
CR Lock
Confirmation Byte
x
x
x
x
x
x
D9
1
0
D7 D6 D5 D4 D3 D2 D1 D0
MSb
0
1
0
0
1
1
0
0
1
0
MSb
MSb
Stop by
Host
ACK
from
Client
ACK
from
Client
ACK
from
Client
2018-2021 Microchip Technology Inc.
DS20005769C-page 29
24CS512
The user-programmable portion supports both byte
write and page write operations. The read-only section
contains a preprogrammed, ensured unique, 128-bit
serial number. The user-programmable portion may be
permanently locked with the lock operation.
10.0 SECURITY REGISTER
The 24CS512 includes a 256-byte Security register,
organized as two 128-byte pages. The Security register
is segmented into a 128-byte read-only section and a
128-byte user-programmable lockable identification
page section. Device and word address requirements
to access the Security register are outlined in
Section 3.3.1 “Valid Device Address Byte Inputs”
and Section 3.3.2 “Word Address Bytes”.
Note:
The entire 128-bit serial number must be
used to ensure a unique number.
TABLE 10-1: SECURITY REGISTER ORGANIZATION
Security Register Byte Number
0
1
...
14
15
16
17
Reserved for Future Use
252 253 254
...
126
127
255
Factory Programmed (read-only)
0-15: Device Serial Number
128
129
130
131
...
User-Programmable Lockable Identification Page
DS20005769C-page 30
2018-2021 Microchip Technology Inc.
24CS512
10.1 Custom Programming Option
Note:
Accessing the Security register is only
possible if any sequence or command to
the EEPROM (if one has been sent) has
been properly terminated with a Stop con-
dition. Without proper termination of the
previous sequence, communications with
the Security register will not execute suc-
cessfully.
The 24CS512 supports the preprogramming and sub-
sequent locking of customer-specific data in the
user-programmable portion of the Security register.
Contact your local sales representative for support for
custom programming options.
10.2 Read Operations in the Security
Register
Note:
If the application is to read the first byte of
the serial number, the word address input
needs to be 0800h.
Random read and sequential read operations of the
Security register require that the device type be set to
‘1011b’ (Bh) and matching the hardware client address
bits (A2, A1, A0) to their corresponding device address
input pins. Following the device address byte, the word
address bytes must be sent to the device. Bits A15 and
A10 must be set to logic ‘0’ and bit A11 must be set to
logic ‘1’. Current address reads of the Security register
are not supported.
When the end of the Security register is reached
(256 bytes of data), the word address will roll over to
the beginning of the Security register, starting with the
Most Significant Byte (Byte 0) of the 128-bit serial num-
ber.
The serial number read operation, or any read of the
Security register, is terminated when the host does not
respond with an ACK and issues a Stop condition.
The first 16 bytes of the Security register are, by defini-
tion, read-only and contain a preprogrammed, ensured
unique, 128-bit serial number. The remaining 112 bytes
on the first page of the Security register are reserved
for future use and set to read-only.
The upper 128 bytes of the Security register are
user-programmable and can be locked from any future
programming operations (see Section 10.4 “Locking
the Security Register” for more details).
FIGURE 10-1:
SECURITY REGISTER READ SEQUENCE
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
SCL
Device Address Byte
Word Address – Byte 0
Word Address – Byte 1
1
0
1
1
A2 A1 A0
0
0
0
x
x
x
1
0
x
x
0
A7 A6 A5 A4 A3 A2 A1 A0
MSb
0
SDA
MSb
MSb
Start by
Host
ACK
from
Client
ACK
from
Client
ACK
from
Client
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
Security Register Data
Byte 0
Security Register Data
Byte n
Device Address Byte
1
0
1
1
A2 A1 A0
1
0
D7 D6 D5 D4 D3 D2 D1 D0
MSb
0
D7 D6 D5 D4 D3 D2 D1 D0
MSb
1
MSb
Stop by
Host
Start by
Host
ACK
from
Client
ACK
from
Host
NACK
from
Host
2018-2021 Microchip Technology Inc.
DS20005769C-page 31
24CS512
address byte, the word address bytes must be sent to
the device. Bits A15 and A10 must be set to logic ‘0’
and bit A11 must be set to logic ‘1’. Figure 10-2 illus-
trates a byte write operation in the Security register. If
an attempt is made to write to the Security register with
the WP pin held high or after the Security register has
been locked, no write cycle will occur, no data will be
written and the device will immediately accept a new
command.
10.3 Write Operations in the Security
Register
The Security register supports byte writes, page writes
and partial page writes in the upper 128 bytes of the
region. Page writes and partial page writes in the Secu-
rity register have the same page boundary restrictions
and behavior as they do in the EEPROM region (see
Section 6.2 “Page Write”).
Writing in this region requires beginning the device
address byte with ‘1011b’ (Bh), matching the hardware
client address bits (A2, A1, A0) to their corresponding
device address input pins and sending a logic ‘0’ to the
Read/Write Select (R/W) bit. Following the device
Note:
Enhanced software write protection does
not affect write operations to the Security
register.
FIGURE 10-2:
BYTE WRITE IN THE SECURITY REGISTER
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
SCL
Device Address Byte
Word Address – Byte 0
SDA
1
0
1
1
A2 A1 A0
0
0
0
x
x
x
1
0
x
x
0
MSb
MSb
Start by
Host
ACK
from
ACK
from
Client
Client
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
Word Address – Byte 1
Data Byte
1
A6 A5 A4 A3 A2 A1 A0
0
D7 D6 D5 D4 D3 D2 D1 D0
MSb
0
MSb
Stop by
Host
ACK
from
Client
ACK
from
Client
DS20005769C-page 32
2018-2021 Microchip Technology Inc.
24CS512
ACK responses to the word address and data byte indi-
cate the Security register is not currently locked. NACK
response indicate the Security register region is
already locked.
10.4 Locking the Security Register
The user-programmable portion of the Security register
can be permanently inhibited from future writing with
the lock operation. The status of the lock state can be
determined from the check lock operation.
Refer to Section 10.4.2 “Determining the Lock State
of the Security Register” for details about determining
the lock status of the Security register.
10.4.1
LOCK OPERATION
The sequence completes with a Stop condition being
sent to the device, which initiates a self-timed internal
write cycle. The lock operation will conclude upon com-
pletion of that write cycle, subsequently making the
Security register permanently read-only.
The lock operation is an irreversible sequence that will
permanently prevent all future writing to the upper
128 bytes of the Security register. Once the lock oper-
ation has been executed, the entire 256-byte Security
register becomes read-only.
Note:
The lock operation cannot be inhibited by
asserting the Write-Protect pin. Refer to
Section 6.6 “Write Protection”, which
describes the device behavior with
respect to the Write-Protect pin status.
Note:
Once the Security register has been
locked, it cannot be unlocked.
The lock operation protocol emulates a byte write oper-
ation to the Security register, however, the A11 through
A8 bits of the word address must be set to ‘0110b’ (6h).
The remaining bits of the word address and the data
bytes are don’t care bits. Even though these bits are
don’t care bits, they still must be transmitted to the
device. If the remaining bits are not transmitted, this will
cause the write cycle to abort and the Security register
to remain unlocked.
FIGURE 10-3:
SECURITY REGISTER LOCK OPERATION
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
SCL
Device Address Byte
Word Address – Byte 0
SDA
1
0
1
1
A2 A1 A0
0
0
x
x
x
x
0
1
1
0
0
MSb
MSb
Start by
Host
ACK
from
ACK
from
Client
Client
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
Word Address – Byte 1
Data Byte
x
x
x
x
x
x
x
x
0
x
x
x
x
x
x
x
x
0
MSb
MSb
Stop by
Host
ACK
from
ACK
from
Client
Client
2018-2021 Microchip Technology Inc.
DS20005769C-page 33
24CS512
10.4.2
DETERMINING THE LOCK STATE
OF THE SECURITY REGISTER
Note:
Only the device address byte and the first
word address byte (byte 0) should be sent
to determine the lock state of the Security
register. Sending the second word
address byte (byte 1) and a data byte can
inadvertently lock the Security register.
The check lock operation follows the same sequence
as the lock operation (including ‘0110b’ in the A11
through A8 bits of the word address) with the exception
that only the device address byte and the first word
address byte (byte 0) need to be transmitted to the
device. An ACK response to the word address byte
indicates the lock has not been set while a NACK
response indicates the lock has been set. If the lock
has already been set, it cannot be undone. The check
lock operation is completed by the host sending a Stop
condition to the device. This sequence is shown in
Figure 10-4.
FIGURE 10-4:
DETERMINING THE SECURITY REGISTER LOCK STATE
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
Device Address Byte
A2 A1 A0
Word Address – Byte 0
1
0
1
1
0
0
x
x
x
x
0
1
1
0
0/1
MSb
MSb
Stop by
Host
Start by
Host
ACK
from
ACK from
Client if
Unlocked
Client
NACK from
Client if
Locked
DS20005769C-page 34
2018-2021 Microchip Technology Inc.
24CS512
device that was previously identified will return an ACK.
Now the 24CS512 is ready to return its unique 24-bit
Manufacturing ID value.
11.0 MANUFACTURER
IDENTIFICATION REGISTER
The 24CS512 offers the ability to query the device for
the manufacturer, density and revision information. By
using the reserved 7-bit host code F8h, the device will
return a 24-bit value that corresponds with the reserved
I2C identifier value, along with further data to signify a
512-Kbit density and the device revision.
Note:
A Repeated Start condition must be sent
to the 24CS512 when reading the Manu-
facturer ID. Once a Stop condition is sent,
the internal Address Pointer will reset and
the Manufacturer ID will not be read.
To read the Manufacturer ID data, the host must send
a Start condition, followed by a reserved host code F8h,
specified to which all devices on the bus that support
the Manufacturer ID will ACK. Next, the device address
byte is sent, followed by a new Start condition. The
device address byte consist of the EEPROM device type
identifier (‘1010‘), the selected hardware client address
and the don’t care value for the R/W bit. Then, the
reserved host code F9h is sent and only the specific
The first byte of Manufacturer ID data contains the eight
Most Significant bits (D23-D16) of the 24-bit data value.
The host can then return an ACK to indicate it success-
fully received the data, upon which the device will send
the second byte (D15-D8) of Manufacturer ID data. The
process repeats until all three bytes have been read out
and the host sends a NACK (logic ‘1’) to complete the
sequence. If the host ACKs (logic ‘0’) the third byte, the
internal Address Pointer will roll over back to the first
byte of Manufacturer ID data.
FIGURE 11-1:
MANUFACTURER IDENTIFICATION REGISTER READ SEQUENCE
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
SCL
Host Code F8h
Device Address Byte
Host Code F9h
1
1
1
1
1
0
0
0
0
1
0
1
0
A2 A1 A0
x
0
1
1
1
1
1
0
0
1
0
SDA
MSb
MSb
MSb
Start by
Host
ACK
from
Client
ACK
from
Client
ACK
from
Client
Repeated
Start by
Host
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
Manufacturer ID – Byte 0
Manufacturer ID – Byte 1
Manufacturer ID – Byte 2
D23 D22 D21 D20 D19 D18 D17 D16
MSb
0
D15 D14 D13 D12 D11 D10 D9 D8
MSb
0
D7 D6 D5 D4 D3 D2 D1 D0
MSb
1
Stop by
Host
ACK
from
Host
ACK
from
Host
NACK
from
Host
2018-2021 Microchip Technology Inc.
DS20005769C-page 35
24CS512
The Least Significant 12 bits of the 24-bit Manufacturer
ID is comprised of an I2C identifier defined value that
indicates the device density and revision. The D11
through D3 bits indicate the device density and the D2
through D0 bits indicate the device revision. The overall
24-bit value returned by the 24CS512 is 00D0C8h. The
output is shown more specifically in Table 11-1.
11.1 Manufacturer Identification
Register Data
The Manufacturer Identifier portion of the ID is returned
in the 12 Most Significant bits of the three bytes read
out. The manufacturer reserved I2C identifier value is
‘0000-0000-1101b’ (00Dh). Therefore, the first byte
read out by the device will be 00h. The upper nibble of
the second byte read out is Dh.
TABLE 11-1: MANUFACTURER IDENTIFICATION REGISTER FORMAT
Bit Position
within
24-Bit Value
24CS512 Response
Data Type
Field Width
Binary Value
Hex Value
Indication
Manufacturer
12 Bits
9 Bits
3 Bits
D23-D12
D11-D3
D2-D0
0000-0000-1101
0000-1100-1
000
00Dh
Reserved Value
I2C, 512-Kbit
Revision 1
Device Density
Device Revision
0C8h
DS20005769C-page 36
2018-2021 Microchip Technology Inc.
24CS512
12.0 DEVICE DEFAULT CONDITION
The 24CS512 is delivered with the EEPROM array set
to logic ‘1’, resulting in FFh data in all locations of the
EEPROM memory array.
The Security register contains a preprogrammed,
128-bit serial number in the lower 16 bytes. The
user-programmable portion (lockable ID page) is
unlocked and is set to logic ‘1’, resulting in 128 bytes of
FFh data.
The Configuration register is set for Legacy Hardware
Write Protection mode (EWPM = ‘0’) and is unlocked.
2018-2021 Microchip Technology Inc.
DS20005769C-page 37
24CS512
13.0 PACKAGING INFORMATION
13.1 Package Marking Information
8-Lead MSOP
Example
4CS512
12313F
8-Lead PDIP
Example
24CS512
P13F
2123
8-Lead 3.9 mm SOIC
Example
24CS512
SN2123
13F
NNN
8-Lead 5.28 mm SOIJ
Example
24CS512
SM
212313F
5-Lead SOT-23
Example
AAES21
2313F
DS20005769C-page 38
2018-2021 Microchip Technology Inc.
24CS512
8-Lead 4.4 mm TSSOP
Example
AADN
2123
13F
8-Lead 2x3 mm UDFN
Example
CAN
123
13
XXX
YWW
NN
8-Ball CSP
Example
• 9
13
• X
NN
1st Line Marking Codes
Part
Number
MSOP
PDIP
SOIC
SOIJ
SOT-23
TSSOP
UDFN
CSP
24CS512
4CS512 24CS512 24CS512 24CS512
AAES
AADN
CAN
• 9
Legend: XX...X Customer-specific information
Y
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
YY
WW
NNN
*
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
These packages are RoHs compliant. The JEDEC® designator
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2018-2021 Microchip Technology Inc.
DS20005769C-page 39
24CS512
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20005769C-page 40
2018-2021 Microchip Technology Inc.
24CS512
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2018-2021 Microchip Technology Inc.
DS20005769C-page 41
24CS512
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20005769C-page 42
2018-2021 Microchip Technology Inc.
24CS512
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
N
B
E1
NOTE 1
1
2
TOP VIEW
E
A2
A
C
PLANE
L
c
A1
e
eB
8X b1
8X b
.010
C
SIDE VIEW
END VIEW
Microchip Technology Drawing No. C04-018-P Rev E Sheet 1 of 2
2018-2021 Microchip Technology Inc.
DS20005769C-page 43
24CS512
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
ALTERNATE LEAD DESIGN
(NOTE 5)
DATUM A
DATUM A
b
b
e
2
e
2
e
e
Units
Dimension Limits
INCHES
NOM
8
.100 BSC
-
.130
-
.310
.250
.365
.130
.010
.060
.018
-
MIN
MAX
Number of Pins
Pitch
Top to Seating Plane
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
Tip to Seating Plane
Lead Thickness
N
e
A
A2
A1
E
E1
D
L
c
b1
b
eB
-
.210
.195
-
.115
.015
.290
.240
.348
.115
.008
.040
.014
-
.325
.280
.400
.150
.015
.070
.022
.430
Upper Lead Width
Lower Lead Width
Overall Row Spacing
§
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
5. Lead design above seating plane may vary, based on assembly vendor.
Microchip Technology Drawing No. C04-018-P Rev E Sheet 2 of 2
DS20005769C-page 44
2018-2021 Microchip Technology Inc.
24CS512
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2X
0.10 C A–B
D
A
D
NOTE 5
N
E
2
E1
2
E1
E
2X
0.10 C A–B
2X
0.10 C A–B
1
2
NOTE 1
e
NX b
0.25
C A–B D
B
NOTE 5
TOP VIEW
0.10 C
0.10 C
C
A2
A
SEATING
PLANE
8X
SIDE VIEW
A1
h
R0.13
R0.13
h
H
0.23
L
SEE VIEW C
(L1)
VIEW A–A
VIEW C
Microchip Technology Drawing No. C04-057-SN Rev F Sheet 1 of 2
2018-2021 Microchip Technology Inc.
DS20005769C-page 45
24CS512
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
MILLIMETERS
MIN
NOM
MAX
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff
N
8
e
1.27 BSC
A
-
-
-
-
1.75
-
0.25
A2
A1
E
1.25
0.10
§
Overall Width
6.00 BSC
Molded Package Width
Overall Length
Chamfer (Optional)
Foot Length
E1
D
h
3.90 BSC
4.90 BSC
0.25
0.40
-
-
0.50
1.27
L
Footprint
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
L1
1.04 REF
0°
0.17
0.31
5°
-
-
-
-
-
8°
c
b
0.25
0.51
15°
5°
15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.15mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
5. Datums A & B to be determined at Datum H.
Microchip Technology Drawing No. C04-057-SN Rev F Sheet 2 of 2
DS20005769C-page 46
2018-2021 Microchip Technology Inc.
24CS512
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
SILK SCREEN
C
Y1
X1
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
MILLIMETERS
NOM
MIN
MAX
Contact Pitch
E
C
X1
Y1
1.27 BSC
5.40
Contact Pad Spacing
Contact Pad Width (X8)
Contact Pad Length (X8)
0.60
1.55
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2057-SN Rev F
2018-2021 Microchip Technology Inc.
DS20005769C-page 47
24CS512
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20005769C-page 48
2018-2021 Microchip Technology Inc.
24CS512
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2018-2021 Microchip Technology Inc.
DS20005769C-page 49
24CS512
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20005769C-page 50
2018-2021 Microchip Technology Inc.
24CS512
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
0.20 C 2X
D
e1
A
D
N
E/2
E1/2
E1
E
(DATUM D)
(DATUM A-B)
0.15 C D
2X
NOTE 1
1
2
e
B
NX b
0.20
C A-B D
TOP VIEW
A
A2
A1
A
0.20 C
SEATING PLANE
A
SEE SHEET 2
C
SIDE VIEW
Microchip Technology Drawing C04-091-OT Rev F Sheet 1 of 2
2018-2021 Microchip Technology Inc.
DS20005769C-page 51
24CS512
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
c
T
L
L1
VIEW A-A
SHEET 1
Units
Dimension Limits
MILLIMETERS
MIN
NOM
MAX
Number of Pins
Pitch
Outside lead pitch
Overall Height
Molded Package Thickness
Standoff
Overall Width
Molded Package Width
Overall Length
Foot Length
N
5
e
0.95 BSC
1.90 BSC
e1
A
A2
A1
E
E1
D
L
0.90
0.89
-
-
-
-
1.45
1.30
0.15
2.80 BSC
1.60 BSC
2.90 BSC
0.30
-
0.60
Footprint
Foot Angle
Lead Thickness
Lead Width
L1
0.60 REF
I
0°
0.08
0.20
-
-
-
10°
0.26
0.51
c
b
Notes:
1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.25mm per side.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-091-OT Rev F Sheet 2 of 2
DS20005769C-page 52
2018-2021 Microchip Technology Inc.
24CS512
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
X
SILK SCREEN
5
Y
Z
C
G
1
2
E
GX
RECOMMENDED LAND PATTERN
Units
Dimension Limits
MILLIMETERS
MIN
NOM
0.95 BSC
2.80
MAX
Contact Pitch
E
C
Contact Pad Spacing
Contact Pad Width (X5)
Contact Pad Length (X5)
Distance Between Pads
Distance Between Pads
Overall Width
X
Y
G
GX
Z
0.60
1.10
1.70
0.35
3.90
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2091-OT Rev F
2018-2021 Microchip Technology Inc.
DS20005769C-page 53
24CS512
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DS20005769C-page 54
2018-2021 Microchip Technology Inc.
24CS512
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2018-2021 Microchip Technology Inc.
DS20005769C-page 55
24CS512
DS20005769C-page 56
2018-2021 Microchip Technology Inc.
24CS512
2018-2021 Microchip Technology Inc.
DS20005769C-page 57
24CS512
DS20005769C-page 58
2018-2021 Microchip Technology Inc.
24CS512
2018-2021 Microchip Technology Inc.
DS20005769C-page 59
24CS512
DS20005769C-page 60
2018-2021 Microchip Technology Inc.
24CS512
2018-2021 Microchip Technology Inc.
DS20005769C-page 61
24CS512
APPENDIX A: REVISION HISTORY
Revision C (07/2021)
Replaced terminology “Master” and “Slave” with “Host”
and “Client” respectively; Changed “MUY” with “Q4B”
part number for UDFN package; Updated UDFN
package drawing.
Revision B (07/2020)
Added Extended temperature range, updated PDIP,
SOIC, SOT23 and UDFN package drawings and added
the CSP package drawing.
Revision A (06/2018)
Initial release of this document.
DS20005769C-page 62
2018-2021 Microchip Technology Inc.
24CS512
THE MICROCHIP WEBSITE
CUSTOMER SUPPORT
Microchip provides online support via our website at
www.microchip.com. This website is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the website contains the following information:
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata, appli-
cation notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
Customers should contact their distributor, representa-
tive or Field Application Engineer (FAE) for support.
Local sales offices are also available to help custom-
ers. A listing of sales offices and locations is included in
the back of this document.
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
Technical support is available through the website
at: http://microchip.com/support
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of Micro-
chip sales offices, distributors and factory repre-
sentatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a spec-
ified product family or development tool of interest.
To register, access the Microchip website at
www.microchip.com. Under “Support”, click on “Cus-
tomer Change Notification” and follow the registra-
tion instructions.
2018-2021 Microchip Technology Inc.
DS20005769C-page 63
24CS512
PRODUCT IDENTIFICATION SYSTEM (NON-AUTOMOTIVE)
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
(1)
Examples:
X
/XX
[X]
PART NO.
Device
a) 24CS512T-I/MS
=
Tape and Reel, Industrial
Temp., 1.7V-5.5V, MSOP
Package.
Temperature Package
Range
Tape and Reel
Option
b) 24CS512-I/P
c) 24CS512-E/P
d) 24CS512T-I/SN
=
=
=
Industrial Temp., 1.7V-5.5V,
PDIP Package.
Extended Temp., 1.7V-5.5V,
PDIP Package.
Tape and Reel, Industrial
Temp., 1.7V-5.5V, SOIC
Package.
Extended Temp., 1.7V-5.5V,
SOIC Package.
Tape and Reel, Extended
Temp., 1.7V-5.5V, SOIC
Package.
Tape and Reel, Industrial
Temp., 1.7V-5.5V, SOIJ Pack-
age.
Extended Temp., 1.7V-5.5V,
SOIJ Package.
Tape and Reel, Industrial
Temp., 1.7V-5.5V, SOT-23
Package.
2
Device:
24CS512
=
I C-Compatible Serial EEPROM with 128-Bit
Serial Number
Tape and Reel
Option:
Blank
T
=
=
Standard Packaging (tube or tray)
Tape and Reel
(1)
e) 24CS512-E/SN
f) 24CS512T-E/SN
=
=
Temperature
Range:
I
E
=
=
-40C to +85C (Industrial)
-40C to +125C (Extended)
g) 24CS512T-I/SM
=
Package:
MS
=
=
=
=
=
=
=
=
8-Lead Plastic Micro Small Outline Package
(MSOP)
h) 24CS512-E/SM
i) 24CS512T-I/OT
=
=
P
8-Lead Plastic Dual In-Line – 300 mil Body
(PDIP)
SN
8-Lead Plastic Small Outline – Narrow,
3.90 mm Body (SOIC)
SM
8-Lead Plastic Small Outline – Medium,
5.28 mm Body (SOIJ)
j) 24CS512T-I/Q4B
=
Tape and Reel, Industrial
Temp., 1.7V-5.5V, UDFN
Package.
OT
5-Lead Plastic Small Outline Transistor
(SOT-23)
ST
8-Lead Plastic Thin Shrink Small Outline –
4.4 mm Body (TSSOP)
k) 24CS512T-I/CS0668 = Tape and Reel, Industrial
Temp., 1.7V-5.5V, CSP
Q4B
CS0668
8-Lead Plastic Dual Flat, No Lead Package –
2x3x0.6 mm (UDFN)
Package.
8-Ball Extremely Thin Fine Pitch Wafer Level
Chip Scale Package (CSP)
Note 1: Tape and Reel identifier only appears in the
catalog part number description. This identifier
is used for ordering purposes and is not
printed on the device package. Check with
your Microchip Sales Office for package avail-
ability with the Tape and Reel option.
DS20005769C-page 64
2018-2021 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
•
•
Microchip products meet the specifications contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is secure when used in the intended manner and under normal conditions.
There are dishonest and possibly illegal methods being used in attempts to breach the code protection features of the Microchip
devices. We believe that these methods require using the Microchip products in a manner outside the operating specifications
contained in Microchip's Data Sheets. Attempts to breach these code protection features, most likely, cannot be accomplished
without violating Microchip's intellectual property rights.
•
•
Microchip is willing to work with any customer who is concerned about the integrity of its code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of its code. Code protection does not
mean that we are guaranteeing the product is "unbreakable." Code protection is constantly evolving. We at Microchip are
committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection
feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or
other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication is provided for the sole
purpose of designing with and using Microchip products. Infor-
mation regarding device applications and the like is provided
only for your convenience and may be superseded by updates.
It is your responsibility to ensure that your application meets
with your specifications.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec,
AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT,
chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex,
flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck,
LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi,
Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer,
PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire,
Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST,
SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered
trademarks of Microchip Technology Incorporated in the U.S.A. and
other countries.
THIS INFORMATION IS PROVIDED BY MICROCHIP "AS IS".
MICROCHIP MAKES NO REPRESENTATIONS OR WAR-
RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,
WRITTEN OR ORAL, STATUTORY OR OTHERWISE,
RELATED TO THE INFORMATION INCLUDING BUT NOT
LIMITED TO ANY IMPLIED WARRANTIES OF NON-
INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A
PARTICULAR PURPOSE OR WARRANTIES RELATED TO
ITS CONDITION, QUALITY, OR PERFORMANCE.
AgileSwitch, APT, ClockWorks, The Embedded Control Solutions
Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight
Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3,
Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-
Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub,
TimePictra, TimeProvider, WinPath, and ZL are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDI-
RECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUEN-
TIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
WHATSOEVER RELATED TO THE INFORMATION OR ITS
USE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES
ARE FORESEEABLE. TO THE FULLEST EXTENT
ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON
ALL CLAIMS IN ANY WAY RELATED TO THE INFORMATION
OR ITS USE WILL NOT EXCEED THE AMOUNT OF FEES, IF
ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP
FOR THE INFORMATION. Use of Microchip devices in life sup-
port and/or safety applications is entirely at the buyer's risk, and
the buyer agrees to defend, indemnify and hold harmless
Microchip from any and all damages, claims, suits, or expenses
resulting from such use. No licenses are conveyed, implicitly or
otherwise, under any Microchip intellectual property rights
unless otherwise stated.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, Augmented Switching, BlueSky,
BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive,
CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net,
Dynamic Average Matching, DAM, ECAN, Espresso T1S,
EtherGREEN, IdealBridge, In-Circuit Serial Programming, ICSP,
INICnet, Intelligent Paralleling, Inter-Chip Connectivity,
JitterBlocker, maxCrypto, maxView, memBrain, Mindi, MiWi,
MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK,
NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net,
PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE,
Ripple Blocker, RTAX, RTG4, SAM-ICE, Serial Quad I/O,
simpleMAP, SimpliPHY, SmartBuffer, SMART-I.S., storClad, SQI,
SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Total
Endurance, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY,
ViewSpan, WiperLock, XpressConnect, and ZENA are trademarks
of Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage
Technology, and Symmcom are registered trademarks of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany
II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2018-2021, Microchip Technology Incorporated, All Rights
Reserved.
For information regarding Microchip’s Quality Management Systems,
please visit www.microchip.com/quality.
ISBN: 978-1-5224-7196-7
2018-2021 Microchip Technology Inc.
DS20005769C-page 65
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
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Tel: 61-2-9868-6733
India - Bangalore
Tel: 91-80-3090-4444
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
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Tel: 86-10-8569-7000
India - New Delhi
Tel: 91-11-4160-8631
Denmark - Copenhagen
Tel: 45-4485-5910
Fax: 45-4485-2829
China - Chengdu
Tel: 86-28-8665-5511
India - Pune
Tel: 91-20-4121-0141
Finland - Espoo
Tel: 358-9-4520-820
China - Chongqing
Tel: 86-23-8980-9588
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Tel: 81-6-6152-7160
Web Address:
www.microchip.com
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
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Tel: 86-769-8702-9880
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Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
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Tel: 631-435-6000
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UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Canada - Toronto
Tel: 905-695-1980
Fax: 905-695-2078
DS20005769C-page 66
2018-2021 Microchip Technology Inc.
02/28/20
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