24C08BTE/SL [MICROCHIP]
1K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO14, 0.150 INCH, PLASTIC, SOIC-14;型号: | 24C08BTE/SL |
厂家: | MICROCHIP |
描述: | 1K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO14, 0.150 INCH, PLASTIC, SOIC-14 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
文件: | 总12页 (文件大小:78K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
24C08B/16B
2
8K/16K 5.0V I C Serial EEPROMs
FEATURES
PACKAGE TYPES
PDIP
• Single supply with operation from 4.5-5.5V
• Low power CMOS technology
A0
A1
1
2
8
7
VCC
WP
- 1 mA active current typical
- 10 µA standby current typical at 5.5V
A2
3
4
6
5
SCL
SDA
• Organized as 4 or 8 blocks of 256 bytes
(4 x 256 x 8) or (8 x 256 x 8)
2
VSS
• 2-wire serial interface bus, I C compatible
• Schmitt trigger, filtered inputs for noise suppres-
sion
• Output slope control to eliminate ground bounce
• 100 kHz compatibility
8-lead
SOIC
1
2
8
A0
A1
VCC
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 16 bytes
• 2 ms typical write cycle time for page-write
• Hardware write protect for entire memory
• Can be operated as a serial ROM
7
6
5
WP
3
4
A2
SCL
SDA
VSS
• ESD protection > 4,000V
• 1,000,000 ERASE/WRITE cycles guaranteed
• Data retention > 200 years
14-lead
SOIC
14
13
12
11
1
2
3
4
5
6
7
NC
• 8-pin DIP, 8-lead or 14-lead SOIC packages
• Available for extended temperature range
NC
A0
VCC
WP
NC
- Automotive (E):
-40˚C to +125˚C
A1
DESCRIPTION
NC
10
9
SCL
SDA
NC
A2
VSS
NC
The Microchip Technology Inc. 24C08B/16B is an 8K or
16K bit Electrically Erasable PROM intended for use in
extended/automotive temperature ranges. The device
is organized as four or eight blocks of 256 x 8-bit mem-
ory with a 2-wire serial interface. The 24C08B/16B also
has a page-write capability for up to 16 bytes of data.
The 24C08B/16B is available in the standard 8-pin DIP
and both 8-lead and 14-lead surface mount SOIC pack-
ages.
8
BLOCK DIAGRAM
WP
HV GENERATOR
I/O
CONTROL
LOGIC
MEMORY
CONTROL
LOGIC
EEPROM
ARRAY
XDEC
PAGE LATCHES
SDA
SCL
YDEC
VCC
VSS
SENSE AMP
R/W CONTROL
I2C is a trademark of Philips Corporation.
1996 Microchip Technology Inc.
DS21081D-page 1
24C08B/16B
TABLE 1-1:
Name
PIN FUNCTION TABLE
Function
1.0
ELECTRICAL CHARACTERISTICS
1.1
Maximum Ratings*
VCC...................................................................................7.0V
All inputs and outputs w.r.t. VSS ............... -0.6V to VCC +1.0V
Storage temperature ..................................... -65˚C to +150˚C
Ambient temp. with power applied ................ -65˚C to +125˚C
Soldering temperature of leads (10 seconds) ............. +300˚C
ESD protection on all pins..................................................≥ 4 kV
VSS
SDA
Ground
Serial Address/Data I/O
Serial Clock
SCL
WP
Write Protect Input
+4.5V to 5.5V Power Supply
No Internal Connection
*Notice: Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
VCC
A0, A1, A2
TABLE 1-2:
DC CHARACTERISTICS
VCC = +4.5V to +5.5V
Automotive (E): Tamb = -40˚C to +125˚C
Parameter
Symbol
Min
Max
Units
Conditions
WP, SCL and SDA pins:
High level input voltage
VIH
VIL
.7 Vcc
—
—
.3 VCC
—
V
V
V
Low Level input voltage
Hysteresis of Schmitt trigger
inputs
VHYS
.05 Vcc
(Note)
Low level output voltage
Input leakage current
VOL
ILI
—
-10
-10
—
.40
10
10
10
V
IOL = 3.0 mA, VCC=4.5V
VIN =.1V to VCC
µA
µA
pF
Output leakage current
ILO
VOUT = .1V to VCC
Pin capacitance
CIN, COUT
VCC = 5.0V (Note 1)
(all inputs/outputs)
Tamb = 25˚C, FCLK=1 MHz
Operating current
ICC write
ICC read
—
—
3
1
mA
mA
VCC = 5.5V, SCL = 400 kHz
Standby current
ICCS
—
100
µA
VCC = 5.5V, SDA = SCL = VCC
Note:
This parameter is periodically sampled and not 100% tested.
FIGURE 1-1: BUS TIMING START/STOP
VHYS
SCL
THD:STA
TSU:STA
TSU:STO
SDA
START
STOP
DS21081D-page 2
1996 Microchip Technology Inc.
24C08B/16B
TABLE 1-3:
AC CHARACTERISTICS
Parameter
Symbol
Min
Max
Units
Remarks
Clock frequency
FCLK
THIGH
TLOW
TR
—
4000
4700
—
100
—
kHz
ns
Clock high time
Clock low time
—
ns
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
1000
300
—
ns
(Note1)
(Note 1)
TF
—
ns
THD:STA
4000
ns
After this period the first clock
pulse is generated
START condition setup time
TSU:STA
4700
—
ns
Only relevant for repeated
START condition
Data input hold time
Data input setup time
STOP condition setup time
Output valid from clock
Bus free time
THD:DAT
TSU:DAT
TSU:STO
TAA
0
—
—
ns
ns
ns
ns
ns
250
4000
—
—
3500
—
(Note 2)
TBUF
4700
Time the bus must be free before
a new transmission can start
Output fall time from VIH
min to VIL max
TOF
TSP
TWR
—
—
—
250
50
ns
ns
(Note 1), CB ≤ 100 pF
Input filter spike suppres-
sion (SDA and SCL pins)
(Note 3)
Write cycle time
10
ms
Byte or Page mode
Endurance
24C08B
24C16B
—
—
1M
10M
—
—
cycles
25°C, VCC = 5.0V, Block Mode
(Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a TI specification.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our BBS or website.
FIGURE 1-2: BUS TIMING DATA
TR
TF
THIGH
TLOW
SCL
TSU:STA
THD:DAT
TSU:DAT
TSU:STO
THD:STA
SDA
IN
TSP
TBUF
TAA
TAA
THD:STA
SDA
OUT
1996 Microchip Technology Inc.
DS21081D-page 3
24C08B/16B
3.4
Data Valid (D)
2.0
FUNCTIONAL DESCRIPTION
The 24C08B/16B supports a Bi-directional 2-wire bus
and data transmission protocol. A device that sends
data onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be controlled
by a master device which generates the serial clock
(SCL), controls the bus access, and generates the
START and STOP conditions, while the 24C08B/16B
works as slave. Both, master and slave can operate as
transmitter or receiver but the master device deter-
mines which mode is activated.
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last 16
will be stored when doing a write operation. When an
overwrite does occur it will replace data in a first in first
out fashion.
3.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus is
not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
3.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
Note: The 24C08B/16B does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.
3.1
Bus not Busy (A)
Both data and clock lines remain HIGH.
The device that acknowledges, has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end of
data to the slave by NOT generating an acknowledge
bit on the last byte that has been clocked out of the
slave. In this case, the slave (24C08B/16B) will leave
the data line HIGH to enable the master to generate the
STOP condition.
3.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
3.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)
(B)
(D)
(D)
(C)
(A)
SCL
SDA
START
CONDITION
STOP
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
DS21081D-page 4
1996 Microchip Technology Inc.
24C08B/16B
3.6
Device Addressing
4.0
WRITE OPERATION
A control byte is the first byte received following the
start condition from the master device. The control byte
consists of a 4-bit control code, for the 24C08B/16B this
is set as 1010 binary for read and write operations. The
next three bits of the control byte are the block select
bits (B2, B1, B0). They are used by the master device
to select which of the eight 256 word blocks of memory
are to be accessed. These bits are in effect the three
most significant bits of the word address.
4.1
Byte Write
Following the start condition from the master, the
device code (4 bits), the block address (3 bits), and the
R/W bit which is a logic low is placed onto the bus by
the master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will follow
after it has generated an acknowledge bit during the
ninth clock cycle. Therefore the next byte transmitted by
the master is the word address and will be written into
the address pointer of the 24C08B/16B. After receiving
another acknowledge signal from the 24C08B/16B the
master device will transmit the data word to be written
into the addressed memory location. The 24C08B/16B
acknowledges again and the master generates a stop
condition. This initiates the internal write cycle, and dur-
ing this time the 24C08B/16B will not generate
acknowledge signals (Figure 4-1).
The last bit of the control byte defines the operation to
be performed. When set to one a read operation is
selected, when set to zero a write operation is selected.
Following the start condition, the 24C08B/16B monitors
the SDA bus checking the device type identifier being
transmitted, upon a 1010 code the slave device outputs
an acknowledge signal on the SDA line. Depending on
the state of the R/W bit, the 24C08B/16B will select a
read or write operation.
4.2
Page Write
Control
Code
Operation
Block Select
R/W
The write control byte, word address and the first data
byte are transmitted to the 24C08B/16B in the same
way as in a byte write. But instead of generating a stop
condition the master transmits up to 16 data bytes to
the 24C08B/16B which are temporarily stored in the on-
chip page buffer and will be written into the memory
after the master has transmitted a stop condition. After
the receipt of each word, the four lower order address
pointer bits are internally incremented by one. The
higher order seven bits of the word address remains
constant. If the master should transmit more than 16
words prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an inter-
nal write cycle will begin (Figure 4-2).
Read
Write
1010
1010
Block Address
Block Address
1
0
FIGURE 3-2: CONTROL BYTE
ALLOCATION
START
READ/WRITE
SLAVE ADDRESS
R/W
A
1
0
1
0
B2
B1
B0
FIGURE 4-1: BYTE WRITE
S
T
A
R
T
S
BUS ACTIVITY
MASTER
CONTROL
BYTE
WORD
ADDRESS
T
DATA
O
P
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
BUS ACTIVITY
FIGURE 4-2: PAGE WRITE
S
S
T
O
P
T
BUS ACTIVITY
MASTER
A
CONTROL
BYTE
WORD
ADDRESS (n)
DATA n
DATA n + 1
DATA n + 15
R
T
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
BUS ACTIVITY
1996 Microchip Technology Inc.
DS21081D-page 5
24C08B/16B
7.1
Current Address Read
5.0
ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com-
mand has been issued from the master, the device ini-
tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master send-
ing a start condition followed by the control byte for a
write command (R/W = 0). If the device is still busy with
the write cycle, then no ACK will be returned. If the
cycle is complete, then the device will return the ACK
and the master can then proceed with the next read or
write command. See Figure 5-1 for flow diagram.
The 24C08B/16B contains an address counter that
maintains the address of the last word accessed, inter-
nally incremented by one. Therefore, if the previous
access (either a read or write operation) was to address
n, the next current address read operation would
access data from address n + 1. Upon receipt of the
slave address with R/W bit set to one, the 24C08B/
16B issues an acknowledge and transmits the 8-bit
data word. The master will not acknowledge the transfer
but does generate a stop condition and the 24C08B/
16B discontinues transmission (Figure 7-1).
7.2
Random Read
FIGURE 5-1: ACKNOWLEDGE POLLING
FLOW
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24C08B/16B as part of a write operation. After the word
address is sent, the master generates a start condition
following the acknowledge. This terminates the write
operation, but not before the internal address pointer is
set. Then the master issues the control byte again but
with the R/W bit set to a one. The 24C08B/16B will then
issue an acknowledge and transmits the 8-bit data
word. The master will not acknowledge the transfer but
does generate a stop condition and the 24C08B/16B
discontinues transmission (Figure 7-2).
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
7.3
Sequential Read
Sequential reads are initiated in the same way as a ran-
dom read except that after the 24C08B/16B transmits
the first data byte, the master issues an acknowledge
as opposed to a stop condition in a random read. This
directs the 24C08B/16B to transmit the next sequen-
tially addressed 8 bit word (Figure 7-3).
Send Control Byte
with R/W = 0
Did Device
NO
Acknowledge
To provide sequential reads the 24C08B/16B contains
an internal address pointer which is incremented by
one at the completion of each operation. This address
pointer allows the entire memory contents to be serially
read during one operation.
(ACK = 0)?
YES
Next
Operation
7.4
Noise Protection
The 24C08B/16B employs a VCC threshold detector cir-
cuit which disables the internal erase/write logic if the
VCC is below 1.5 volts at nominal conditions.
6.0
WRITE PROTECTION
The 24C08B/16B can be used as a serial ROM when
the WP pin is connected to VCC. Programming will be
inhibited and the entire memory will be write-protected.
The SCL and SDA inputs have Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.
7.0
READ OPERATION
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one. There are three basic types
of read operations: current address read, random read,
and sequential read.
DS21081D-page 6
1996 Microchip Technology Inc.
24C08B/16B
FIGURE 7-1: CURRENT ADDRESS READ
S
T
A
R
T
S
T
O
P
BUS ACTIVITY
MASTER
CONTROL
BYTE
DATA n
SDA LINE
S
P
A
C
K
N
O
BUS ACTIVITY
A
C
K
FIGURE 7-2: RANDOM READ
S
T
A
R
T
S
T
A
R
T
S
T
BUS ACTIVITY
MASTER
CONTROL
BYTE
WORD
ADDRESS (n)
CONTROL
BYTE
DATA (n)
O
P
S
P
S
SDA LINE
A
C
K
A
C
K
A
C
K
N
O
BUS ACTIVITY
A
C
K
FIGURE 7-3: SEQUENTIAL READ
S
T
O
P
BUS ACTIVITY
MASTER
CONTROL
BYTE
DATA n
DATA n + 1
DATA n + 2
DATA n + X
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
BUS ACTIVITY
A
C
K
8.3
WP
8.0
PIN DESCRIPTIONS
This pin must be connected to either VSS or VCC.
8.1
SDA Serial Address/Data Input/Output
If tied to VSS, normal memory operation is enabled
(read/write the entire memory 000-7FF).
This is a Bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pull-up
resistor to VCC (typical 10Ω).
If tied to VCC, WRITE operations are inhibited. The
entire memory will be write-protected. Read operations
are not affected.
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP condi-
tions.
This feature allows the user to use the 24C08B/16B as
a serial ROM when WP is enabled (tied to VCC).
8.4
A0, A1, A2
8.2
SCL Serial Clock
These pins are not used by the 24C08B/16B. They
may be left floating or tied to either VSS or VCC.
This input is used to synchronize the data transfer from
and to the device.
1996 Microchip Technology Inc.
DS21081D-page 7
24C08B/16B
NOTES:
DS21081D-page 8
1996 Microchip Technology Inc.
24C08B/16B
NOTES:
1996 Microchip Technology Inc.
DS21081D-page 9
24C08B/16B
NOTES:
DS21081D-page 10
1996 Microchip Technology Inc.
24C08B/16B
24C08B/16B Product Identification System
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.
24C08B/16B
–
E
/P
Package:
P = Plastic DIP (300 mil Body), 8-lead
SL = Plastic SOIC (150 mil Body), 14-lead
SN = Plastic SOIC (150 mil Body), 8-lead
Temperature
Range:
E = -40°C to +125°C
2
Device:
24C08B
24C08BT
24C16B
8K I C Serial EEPROM
2
8K I C Serial EEPROM (Tape and Reel)
2
16K I C Serial EEPROM
16K I C Serial EEPROM (Tape and Reel)
2
24C16BT
1996 Microchip Technology Inc.
DS21081D-page 11
WORLDWIDE SALES & SERVICE
AMERICAS
Corporate Office
ASIA/PACIFIC
China
EUROPE
United Kingdom
Microchip Technology Inc.
Microchip Technology
Arizona Microchip Technology Ltd.
Unit 6, The Courtyard
Meadow Bank, Furlong Road
Bourne End, Buckinghamshire SL8 5AJ
Tel: 44 1628 850303 Fax: 44 1628 850178
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 602 786-7200 Fax: 602 786-7277
Technical Support: 602 786-7627
Web: http://www.microchip.com
Unit 406 of Shanghai Golden Bridge Bldg.
2077 Yan’an Road West, Hongiao District
Shanghai, Peoples Republic of China
Tel: 86 21 6275 5700
Fax: 011 86 21 6275 5060
Hong Kong
Microchip Technology
RM 3801B, Tower Two
Metroplaza
223 Hing Fong Road
Kwai Fong, N.T. Hong Kong
Tel: 852 2 401 1200 Fax: 852 2 401 3431
India
Microchip Technology
No. 6, Legacy, Convent Road
Bangalore 560 025 India
Tel: 91 80 526 3148 Fax: 91 80 559 9840
France
Atlanta
Arizona Microchip Technology SARL
Zone Industrielle de la Bonde
2 Rue du Buisson aux Fraises
91300 Massy - France
Tel: 33 1 69 53 63 20 Fax: 33 1 69 30 90 79
Germany
Arizona Microchip Technology GmbH
Gustav-Heinemann-Ring 125
D-81739 Muenchen, Germany
Tel: 49 89 627 144 0 Fax: 49 89 627 144 44
Microchip Technology Inc.
500 Sugar Mill Road, Suite 200B
Atlanta, GA 30350
Tel: 770 640-0034 Fax: 770 640-0307
Boston
Microchip Technology Inc.
5 Mount Royal Avenue
Marlborough, MA 01752
Tel: 508 480-9990 Fax: 508 480-8575
Chicago
Italy
Microchip Technology Inc.
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: 708 285-0071 Fax: 708 285-0075
Dallas
Microchip Technology Inc.
14651 Dallas Parkway, Suite 816
Dallas, TX 75240-8809
Tel: 972 991-7177 Fax: 972 991-8588
Dayton
Microchip Technology Inc.
Suite 150
Arizona Microchip Technology SRL
Centro Direzionale Colleone Pas Taurus 1
Viale Colleoni 1
20041 Agrate Brianza
Milan Italy
Korea
Microchip Technology
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku,
Seoul, Korea
Tel: 82 2 554 7200 Fax: 82 2 558 5934
Singapore
Microchip Technology
200 Middle Road
#10-03 Prime Centre
Singapore 188980
Tel: 65 334 8870 Fax: 65 334 8850
Taiwan, R.O.C
Microchip Technology
10F-1C 207
Tung Hua North Road
Taipei, Taiwan, ROC
Tel: 886 2 717 7175 Fax: 886 2 545 0139
Tel: 39 39 6899939 Fax: 39 39 689 9883
JAPAN
Microchip Technology Intl. Inc.
Benex S-1 6F
3-18-20, Shin Yokohama
Kohoku-Ku, Yokohama
Kanagawa 222 Japan
Two Prestige Place
Miamisburg, OH 45342
Tel: 513 291-1654 Fax: 513 291-9175
Tel: 81 45 471 6166 Fax: 81 45 471 6122
9/3/96
Los Angeles
Microchip Technology Inc.
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: 714 263-1888 Fax: 714 263-1338
NewYork
Microchip Technmgy Inc.
150 Motor Parkway, Suite 416
Hauppauge, NY 11788
Tel: 516 273-5305 Fax: 516 273-5335
San Jose
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408 436-7950 Fax: 408 436-7955
Toronto
Microchip Technology Inc.
5925 Airport Road, Suite 200
Mississauga, Ontario L4V 1W1, Canada
Tel: 905 405-6279 Fax: 905 405-6253
All rights reserved. 1996, Microchip Technology Incorporated, USA. 9/96
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No repre-
sentation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement
of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not autho-
rized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and
name are registered trademarks of Microchip Technology Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
DS21081D-page 12
1996 Microchip Technology Inc.
相关型号:
©2020 ICPDF网 联系我们和版权申明