24AA08/SL [MICROCHIP]
1K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO14, 0.150 INCH, PLASTIC, SOIC-14;
| 型号： | 24AA08/SL |
| 厂家： | 
MICROCHIP |
| 描述： | 1K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO14, 0.150 INCH, PLASTIC, SOIC-14 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路 |
| 文件： | 总10页 (文件大小：111K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
24AA04/08
4K/8K 1.8V CMOS Serial EEPROMs
PACKAGE TYPE
DIP
FEATURES
• Single supply with operation down to 1.8V
• Low power CMOS technology
A0
1
2
3
4
8
7
6
5
VCC
WP
- 1 mA active current typical
A1
24AA04/08
- 10 µA standby current typical at 5.5V
- 3 µA standby current typical at 1.8V
A2
SCL
SDA
• Organized as 2 or 4 blocks of 256 bytes
(2 x 256 x 8) or (4 x 256 x 8)
VSS
• Two wire serial interface bus, I2C compatible
• Schmitt trigger, filtered inputs for noise suppres-
sion
8-Lead
SOIC
1
2
3
4
8
7
6
5
VCC
A0
• Output slope control to eliminate ground bounce
• 100 kHz (1.8V) and 400 kHz (5V) compatibility
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 16 bytes
• 2 ms typical write cycle time for page-write
• Hardware write protect for entire memory
• Can be operated as a serial ROM
WP
A1
A2
24AA04/08
SCL
SDA
VSS
14-Lead
SOIC
• Factory programming (QTP) available
• ESD protection > 4,000V
14
1
2
3
4
5
6
7
NC
NC
13
12
11
• 1,000,000 ERASE/WRITE cycles guaranteed*
• Data retention > 200 years
A0
VCC
WP
NC
A1
• 8-pin DIP, 8-lead or 14-lead SOIC packages
• Available for extended temperature ranges
- Commercial: 0˚C to +70˚C
24AA04/08
NC
10
9
SCL
SDA
NC
A2
VSS
NC
DESCRIPTION
8
The Microchip Technology Inc. 24AA04/08 is a 4K bit or
8K bit Electrically Erasable PROM. The device is orga-
nized as 2 or 4 blocks of 256 x 8 bit memory with a two
wire serial interface. Low voltage design permits oper-
ation down to 1.8 volts with standby and active currents
of only 3 µA and 1 mA respectively. The 24AA04/08
also has a page-write capability for up to 16 bytes of
data. The 24AA04/08 is available in the standard 8-pin
DIP and both 8-lead and 14-lead surface mount SOIC
packages.
BLOCK DIAGRAM
WP
HV GENERATOR
I/O
CONTROL
MEMORY
CONTROL
LOGIC
EEPROM ARRAY
PAGE LATCHES
XDEC
LOGIC
SDA
SCL
YDEC
VCC
SENSE AMP
R/W CONTROL
V
SS
*Future: 10,000,000 E/W cycles guaranteed
I2C is a trademark of Philips Corporation
1995 Microchip Technology Inc.
DS21053D-page 1
24AA04/08
TABLE 1-1:
Name
PIN FUNCTION TABLE
Function
1.0
ELECTRICAL CHARACTERISTICS
1.1
Maximum Ratings*
VCC........................................................................ 7.0V
All inputs and outputs w.r.t. VSS ....-0.6V to VCC +1.0V
Storage temperature ...........................-65˚C to +150˚C
Ambient temp. with power applied ......-65˚C to +125˚C
Soldering temperature of leads (10 seconds) ...+300˚C
ESD protection on all pins ......................................≥ 4 kV
VSS
SDA
Ground
Serial Address/Data I/O
Serial Clock
SCL
WP
Write Protect Input
+1.8V to 5.5V Power Supply
No Internal Connection
Vcc
*Notice: Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
A0, A1, A2
TABLE 1-2:
DC CHARACTERISTICS
VCC = +1.8V to +5.5V
Commercial (C): Tamb = 0˚C to +70˚C
Parameter
Sym
Min
Typ
Max
Units
Conditions
WP, SCL and SDA pins:
High level input voltage
VIH
VIL
.7 VCC
—
—
—
—
—
.3 VCC
—
V
V
V
Low Level input voltage
Hysteresis of Schmitt trigger
inputs
VHYS
.05 VCC
Note 1
Low level output voltage
Input leakage current
VOL
ILI
—
-10
-10
—
—
—
—
—
.40
10
10
10
V
IOL = 3.0 mA, VCC = 1.8V
VIN = .1V to VCC
µA
µA
pF
Output leakage current
ILO
VOUT = .1V to VCC
Pin capacitance
CIN, COUT
VCC = 5.0V (Note 1)
(all inputs/outputs)
Tamb = 25˚C, FCLK = 1 MHz
Operating current
ICC WRITE
ICC READ
—
—
—
—
—
0.5
—
3
—
1
mA VCC = 5.5V, SCL = 400 kHz
mA VCC = 1.8V, SCL = 100 kHz
mA VCC = 5.5V, SCL = 400 kHz
mA VCC = 1.8V, SCL = 100 kHz
0.05
—
Standby current
ICCS
—
—
—
100
30
—
µA
µA
µA
VCC = 5.5V, SDA=SCL=VCC
VCC = 3.0V, SDA=SCL=VCC
VCC = 1.8V, SDA=SCL=VCC
3
Note 1: This parameter is periodically sampled and not 100% tested.
FIGURE 1-1: BUS TIMING START/STOP
VHYS
SCL
THD:STA
TSU:STO
TSU:STA
SDA
START
STOP
DS21053D-page 2
1995 Microchip Technology Inc.
24AA04/08
TABLE 1-3:
AC CHARACTERISTICS
VCC = 4.5-5.5V
Fast Mode
Standard Mode
Parameter
Symbol
Units
Remarks
Min
Max
Min
Max
Clock frequency
FCLK
THIGH
TLOW
TR
—
4000
4700
—
100
—
—
600
1300
—
400
—
kHz
ns
Clock high time
Clock low time
—
—
ns
SDA and SCL rise time
SDA and SCL fall time
1000
300
—
300
300
—
ns
Note 2
TF
—
—
ns
Note 2
START condition hold time THD:STA
4000
600
ns
After this period the first clock
pulse is generated
START condition setup
time
TSU:STA
4700
—
600
—
ns
Only relevant for repeated
START condition
Data input hold time
Data input setup time
THD:DAT
TSU:DAT
0
—
—
0
—
—
ns
ns
ns
ns
ns
250
4000
—
100
600
—
STOP condition setup time TSU:STO
—
—
Output valid from clock
Bus free time
TAA
3500
—
900
—
Note 1
TBUF
4700
1300
Time the bus must be free before
a new transmission can start
Output fall time from VIH
min to VIL max
TOF
TSP
TWR
—
—
—
250
50
20 + 0.1
CB
250
50
ns
ns
Note 2, CB ≤ 100 pF
Input filter spike suppres-
sion (SDA and SCL pins)
—
Note 3
Write cycle time
10
—
10
ms
Byte or Page mode
Note 1: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
Note 2: Not 100% tested. CB = total capacitance of one bus line in pF.
Note 3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a TI specification for standard operation.
FIGURE 1-2: BUS TIMING DATA
t
t
F
R
t
t
HIGH
t
LOW
SCL
t
SU:STA
t
SU:STO
t
HD:DAT
SU:DAT
t
HD:STA
SDA
IN
t
SP
t
BUF
t
t
AA
AA
SDA
OUT
1995 Microchip Technology Inc.
DS21053D-page 3
24AA04/08
3.4
Data Valid (D)
2.0
FUNCTIONAL DESCRIPTION
The 24AA04/08 supports a bidirectional two wire bus
and data transmission protocol. A device that sends
data onto the bus is defined as transmitter, and a
device receiving data as receiver. The bus has to be
controlled by a master device which generates the
serial clock (SCL), controls the bus access, and gener-
ates the START and STOP conditions, while the
24AA04/08 works as slave. Both, master and slave
can operate as transmitter or receiver but the master
device determines which mode is activated.
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last six-
teen will be stored when doing a write operation. When
an overwrite does occur it will replace data in a first in
first out fashion.
3.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
3.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
Accordingly, the following bus conditions have been
defined (see Figure 3-1).
Note: The 24AA04/08 does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.
3.1
Bus not Busy (A)
Both data and clock lines remain HIGH.
The device that acknowledges, has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line HIGH to enable
the master to generate the STOP condition.
3.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition.
All commands must be preceded by a START condi-
tion.
3.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)
(B)
(D)
(D)
(C)
(A)
SCL
SDA
START CONDITION
ADDRESS
OR
ACKNOWLEDGE
VALID
DATA ALLOWED
TO CHANGE
STOP
CONDITION
DS21053D-page 4
1995 Microchip Technology Inc.
24AA04/08
4.0
BUS CHARACTERISTICS
5.0
WRITE OPERATION
4.1
Device Addressing and Operation
5.1
Byte Write
A control byte is the first byte received following the
start condition from the master device. The control
byte consists of a four bit control code, for the
24AA04/08 this is set as 1010 binary for read and write
operations. The next three bits of the control byte are
the block select bits (B2, B1, B0). B2 is a don't care for
both the 24AA04 and 24AA08; B1 is a don't care for
the 24AA04. They are used by the master device to
select which of the two or four 256 word blocks of mem-
ory are to be accessed. These bits are in effect the
most significant bits of the word address.
Following the start condition from the master, the
device code (4 bits), the block address (3 bits), and the
R/W bit which is a logic low is placed onto the bus by
the master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will fol-
low after it has generated an acknowledge bit during
the ninth clock cycle. Therefore the next byte transmit-
ted by the master is the word address and will be writ-
ten into the address pointer of the 24AA04/08. After
receiving another acknowledge signal from the
24AA04/08 the master device will transmit the data
word to be written into the addressed memory location.
The 24AA04/08 acknowledges again and the master
generates a stop condition. This initiates the internal
write cycle, and during this time the 24AA04/08 will not
generate acknowledge signals (see Figure 5-1).
The last bit of the control byte defines the operation to
be performed. When set to one a read operation is
selected, when set to zero a write operation is selected.
Following the start condition, the 24AA04/08 monitors
the SDA bus checking the device type identifier being
transmitted, upon a 1010 code the slave device outputs
an acknowledge signal on the SDA line. Depending on
the state of the R/W bit, the 24AA04/08 will select a
read or write operation.
5.2
Page Write
The write control byte, word ad dress and the first data
byte are transmitted to the 24AA04/08 in the same way
as in a byte write. But instead of generating a stop con-
dition the master transmits up to sixteen data bytes to
the 24AA04/08 which are temporarily stored in the
on-chip page buffer and will be written into the memory
after the master has transmitted a stop condition. After
the receipt of each word, the four lower order address
pointer bits are internally incremented by one. The
higher order seven bits of the word address remains
constant. If the master should transmit more than six-
teen words prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an inter-
nal write cycle will begin (see Figure 8-1).
Control
Code
Operation
Block Select
R/W
Read
Write
1010
1010
Block Address
Block Address
1
0
FIGURE 4-1: CONTROL BYTE
ALLOCATION
START
READ/WRITE
SLAVE ADDRESS
R/W
A
1
0
1
0
X
B1
B0
X = don't care, B1 is don't care for 24AA04
FIGURE 5-1: BYTE WRITE
S
T
A
R
T
S
WORD
ADDRESS
CONTROL
BYTE
T
BUS ACTIVITY:
MASTER
DATA
O
P
SDA LINE
S
P
BUS ACTIVITY:
A
C
K
A
C
K
A
C
K
1995 Microchip Technology Inc.
DS21053D-page 5
24AA04/08
6.0
ACKNOWLEDGE POLLING
7.0
WRITE PROTECTION
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com-
mand has been issued from the master, the device ini-
tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master
sending a start condition followed by the control byte
for a write command (R/W = 0). If the device is still
busy with the write cycle, then no ACK will be returned.
If the cycle is complete, then the device will return the
ACK and the master can then proceed with the next
read or write command. See Figure 6-1 for flow dia-
gram.
The 24AA04/08 can be used as a serial ROM when the
WP pin is connected to VCC. Programming will be
inhibited and the entire memory will be write-protected.
8.0
READ OPERATION
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one. There are three basic
types of read operations: current address read, ran-
dom read, and sequential read.
8.1
Current Address Read
The 24AA04/08 contains an address counter that
maintains the address of the last word accessed, inter-
nally incremented by one. Therefore, if the previous
access (either a read or write operation) was to
address n, the next current address read operation
would access data from address n + 1. Upon receipt of
the slave address with R/W bit set to one, the
24AA04/08 issues an acknowledge and transmits the
eight bit data word. The master will not acknowledge
the transfer but does generate a stop condition and the
FIGURE 6-1: ACKNOWLEDGE POLLING
FLOW
Send
Write Command
Send Stop
Condition to
24AA04/08
Figure 8-2).
discontinues
transmission
(see
Initiate Write Cycle
8.2
Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24AA04/08 as part of a write operation. After the word
address is sent, the master generates a start condition
following the acknowledge. This terminates the write
operation, but not before the internal address pointer is
set. Then the master issues the control byte again but
with the R/W bit set to a one. The 24AA04/08 will then
issue an acknowledge and transmits the eight bit data
word. The master will not acknowledge the transfer but
does generate a stop condition and the 24AA04/08 dis-
continues transmission (see Figure 8-3).
Send Start
Send Control Byte
with R/W = 0
Did Device
No
Acknowledge
(ACK = 0)?
Yes
Next
Operation
FIGURE 8-1: PAGE WRITE
S
T
A
R
T
S
T
O
P
WORD
ADDRESS (n)
CONTROL
BYTE
BUS ACTIVITY:
MASTER
DATA n
DATA n + 1
DATA n + 15
SDA LINE
S
P
BUS ACTIVITY:
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
DS21053D-page 6
1995 Microchip Technology Inc.
24AA04/08
FIGURE 8-2: CURRENT ADDRESS READ
S
T
A
R
T
S
T
O
P
CONTROL
BYTE
BUS ACTIVITY:
MASTER
DATA n
SDA LINE
S
P
BUS ACTIVITY:
A
C
K
N
O
A
C
K
FIGURE 8-3: RANDOM READ
S
T
A
R
T
S
S
T
O
P
T
A
R
T
WORD
ADDRESS (n)
CONTROL
BYTE
CONTROL
BYTE
BUS ACTIVITY:
MASTER
SDA LINE
S
S
P
BUS ACTIVITY:
A
C
K
N
O
A
C
K
A
C
K
DATA n
A
C
K
1995 Microchip Technology Inc.
DS21053D-page 7
24AA04/08
8.3
Sequential Read
9.0
PIN DESCRIPTIONS
Sequential reads are initiated in the same way as a ran-
dom read except that after the 24AA04/08 transmits
the first data byte, the master issues an acknowledge
as opposed to a stop condition in a random read. This
directs the 24AA04/08 to transmit the next sequentially
addressed 8 bit word (see Figure 9-1).
9.1
SDA Serial Address/Data Input/Output
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pullup
resistor to VCC (typical 10Ω for 100 kHz, 1Ω for 400
kHz).
To provide sequential reads the 24AA04/08 contains
an internal address pointer which is incremented by
one at the completion of each operation. This address
pointer allows the entire memory contents to be serially
read during one operation.
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP condi-
tions.
8.4
Noise Protection
9.2
SCL Serial Clock
The 24AA04/08 employs a VCC threshold detector cir-
cuit which disables the internal erase/write logic if the
VCC is below 1.5 volts at nominal conditions.
This input is used to synchronize the data transfer from
and to the device.
9.3
WP
The SCL and SDA inputs have Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.
This pin must be connected to either VSS or VCC.
If tied to Vss, normal memory operation is enabled
(read/write the entire memory).
If tied to VCC, WRITE operations are inhibited. The
entire memory will be write-protected. Read opera-
tions are not affected.
This feature allows the user to use the 24AA04/08 as a
serial ROM when WP is enabled (tied to Vcc).
9.4
A0, A1, A2
These pins are not used by the 24AA04/08. They may
be left floating or tied to either VSS or VCC.
FIGURE 9-1: SEQUENTIAL READ
S
T
O
P
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:
MASTER
CONTROL
BYTE
P
SDA LINE
N
O
A
C
K
DATA n + X
DATA n + 2
DATA n + 1
DATA n
BUS ACTIVITY:
A
C
K
DS21053D-page 8
1995 Microchip Technology Inc.
24AA04/08
NOTES:
1995 Microchip Technology Inc.
DS21053D-page 9
24AA04/08
24AA04/08 Product Identification System
To order or obtain information (e.g., on pricing or delivery), please use listed part numbers, and refer to factory or listed sales offices.
24AA04/08 -X /XX X
Revision:
Package:
P
=
=
=
=
Plastic DIP (300 mil Body), 8-lead
Plastic SOIC (150 mil Body), 14-lead
Plastic SOIC (150 mil Body), 8-lead
Plastic SOIC (207 mil Body), 8-lead
SL
SN
SM
Temperature
Range:
-
=
0°C to +70°C
Device:
24AA04
24AA04T
24AA08
24AA08T
1.8K, 4K CMOS Serial EEPROM
1.8K, 4K CMOS Serial EEPROM (Tape and Reel)
1.8K, 8K CMOS Serial EEPROM
1.8K, 8K CMOS Serial EEPROM (Tape and Reel)
EUROPE
AMERICAS (continued)
AMERICAS
United Kingdom
San Jose
Corporate Office
Arizona Microchip Technology Ltd.
Unit 6, The Courtyard
Meadow Bank, Furlong Road
Bourne End, Buckinghamshire SL8 5AJ
Tel: 44 0 1628 851077 Fax: 44 0 1628 850259
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Microchip Technology Inc.
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 602 786-7200 Fax: 602 786-7277
Technical Support: 602 786-7627
Web: http://www.mchip.com/biz/mchip
Tel: 408 436-7950 Fax: 408 436-7955
ASIA/PACIFIC
Hong Kong
Microchip Technology
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Metroplaza
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2 Rue du Buisson aux Fraises
91300 Massy - France
Tel: 33 1 69 53 63 20 Fax: 33 1 69 30 90 79
Germany
Arizona Microchip Technology GmbH
Gustav-Heinemann-Ring 125
D-81739 Muenchen, Germany
Tel: 49 89 627 144 0 Fax: 49 89 627 144 44
Atlanta
Microchip Technology Inc.
500 Sugar Mill Road, Suite 200B
Atlanta, GA 30350
Tel: 770 640-0034 Fax: 770 640-0307
Boston
Microchip Technology Inc.
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Marlborough, MA 01752
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Microchip Technology
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Seoul, Korea
Tel: 82 2 554 7200 Fax: 82 2 558 5934
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Microchip Technology
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#10-03 Prime Centre
Singapore 188980
Tel: 65 334 8870 Fax: 65 334 8850
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Microchip Technology
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Tung Hua North Road
Taipei, Taiwan, ROC
Tel: 886 2 717 7175 Fax: 886 2 545 0139
Italy
Tel: 508 480-9990
Fax: 508 480-8575
Arizona Microchip Technology SRL
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Palazzo Pegaso Ingresso No. 2
Via Paracelso 23, 20041
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Tel: 39 039 689 9939 Fax: 39 039 689 9883
Chicago
Microchip Technology Inc.
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: 708 285-0071 Fax: 708 285-0075
Dallas
Microchip Technology Inc.
14651 Dallas Parkway, Suite 816
Dallas, TX 75240-8809
Tel: 214 991-7177 Fax: 214 991-8588
Dayton
Microchip Technology Inc.
35 Rockridge Road
JAPAN
Microchip Technology Intl. Inc.
Benex S-1 6F
3-18-20, Shin Yokohama
Kohoku-Ku, Yokohama
Kanagawa 222 Japan
Tel: 81 45 471 6166 Fax: 81 45 471 6122
Englewood, OH 45322
Tel: 513 832-2543 Fax: 513 832-2841
9/5/95
Los Angeles
Microchip Technology Inc.
18201 Von Karman, Suite 455
Irvine, CA 92715
Tel: 714 263-1888 Fax: 714 263-1338
New York
Microchip Technology Inc.
150 Motor Parkway, Suite 416
Hauppauge, NY 11788
Tel: 516 273-5305 Fax: 516 273-5335
Printed in the USA, 9/95
1995, Microchip Technology Incorporated
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DS21053D-page 10
1995 Microchip Technology Inc.
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