ML4827CS-2 [MICRO-LINEAR]
Fault-Protected PFC and PWM Controller Combo; 故障保护PFC和PWM控制器组合
| 型号： | ML4827CS-2 |
| 厂家： | 
MICRO LINEAR CORPORATION |
| 描述： | Fault-Protected PFC and PWM Controller Combo |
| 文件： | 总16页 (文件大小：258K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 1998
PRELIMINARY
ML4827*
Fault-Protected PFC and PWM Controller Combo
GENERAL DESCRIPTION
FEATURES
The ML4827 is a controller for power factor corrected,
switched mode power supplies, that includes circuitry
necessary for conformance to the safety requirements of
UL1950. A direct descendent of the industry-standard
ML4824-1, the ML4827 adds a TriFault Detect™ function
to guarantee that no unsafe conditions may result from
single component failure in the PFC. Power Factor
Correction (PFC) allows the use of smaller, lower cost
bulk capacitors, reduces power line loading and stress on
the switching FETs, and results in a power supply that
fully complies with IEC1000-3-2 specification. The
ML4827 includes circuits for the implementation of a
leading edge, average current, “boost” type power factor
correction and a trailing edge, pulse width modulator
(PWM). The device is available in two versions; the
■ Pin-compatible with industry-standard ML4824-1
■ TriFault Detect™ to conform to UL1950™ requirements
■ Available in 50% or 74% max duty cycle versions
■ Low total harmonic distortion
■ Reduces ripple current in the storage capacitor
between the PFC and PWM sections
■ Average current, continuous boost leading edge PFC
■ High efficiency trailing-edge PWM can be configured
for current mode or voltage mode operation
ML4827-1 (Duty Cycle
= 50%) and the ML4827-2
MAX
(Duty Cycle
= 74%). The higher maximum duty cycle
■ Average line voltage compensation with brown-out
MAX
of the -2 allows enhanced utilization of a given
transformer core’s power handling capacity. An over-
voltage comparator shuts down the PFC section in the
event of a sudden decrease in load. The PFC section also
includes peak current limiting and input voltage brown-
out protection. The PWM section can be operated in
current or voltage mode, and includes a duty cycle limit
to prevent transformer saturation.
control
■ PFC overvoltage comparator eliminates output
“runaway” due to load removal
■ Current fed gain modulator for improved noise immunity
■ Overvoltage protection, UVLO, and soft start
BLOCK DIAGRAM
* Some Packages Are End Of Life
16
1
13
2µA
V
CC
POWER FACTOR CORRECTOR
VEAO
IEAO
V
V
CCZ
REF
V
OVP
REF
BROKEN WIRE
COMPARATOR
2.7V
7.5V
REFERENCE
V
VEA
FB
13.5V
14
+
–
IEA
3.5kΩ
15
–
+
–
+
–
2.5V
AC
+
0.5V
S
Q
I
+
–
2
4
3
–1V
+
–
GAIN
MODULATOR
V
R
S
Q
Q
RMS
PFC OUT
3.5kΩ
PFC I
I
LIMIT
12
SENSE
R
Q
RAMP 1
7
8
OSCILLATOR
RAMP 2
DUTY CYCLE
LIMIT
8V
–
+
V
1.25V
DC
6
PWM OUT
11
V
S
Q
Q
CC
–
+
V
OK
1V
IN
V
–
50µA
8V
FB
SS
–
+
R
5
9
2.5V
+
GND
10
DC I
LIMIT
DC I
LIMIT
V
UVLO
CCZ
PULSE WIDTH MODULATOR
1
ML4827
PIN CONFIGURATION
ML4827
16-Pin PDIP (P16)
16-Pin Wide SOIC (S16W)
IEAO
1
2
3
4
5
6
7
8
16 VEAO
I
15
14
13
V
V
V
AC
FB
I
SENSE
REF
CC
V
RMS
SS
12 PFC OUT
11 PWM OUT
10 GND
V
DC
RAMP 1
RAMP 2
9
DC I
LIMIT
TOP VIEW
PIN DESCRIPTION
PIN NAME
FUNCTION
PIN NAME
FUNCTION
1
IEAO
PFC transconductance current error
amplifier output
9
DC I
GND
PWM current limit comparator input
Ground
LIMIT
10
11
12
13
2
3
I
AC
PFC gain control reference input
PWM OUT PWM driver output
I
Current sense input to the PFC current
limit comparator
SENSE
PFC OUT
PFC driver output
4
5
V
RMS
Input for PFC RMS line voltage
compensation
V
CC
Positive supply (connected to an
internal shunt regulator)
SS
Connection point for the PWM soft start
capacitor
14
15
V
V
Buffered output for the internal 7.5V
reference
REF
6
7
V
DC
PWM voltage feedback input
PFC transconductance voltage error
amplifier input, and TriFault Detect
input
FB
RAMP 1
RAMP 2
PFC (master) oscillator input; f
set
OSC
by R C
T
T
16
VEAO
PFC transconductance voltage error
amplifier output
8
When in current mode, this pin
functions as as the current sense input;
when in voltage mode, it is the PWM
(slave) oscillator input.
2
ML4827
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which
the device could be permanently damaged. Absolute
maximum ratings are stress ratings only and functional
device operation is not implied.
Junction Temperature .............................................. 150°C
Storage Temperature Range ..................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec) ..................... 260°C
Thermal Resistance (θ )
JA
Plastic DIP ....................................................... 80°C/W
V
Shunt Regulator Current .................................. 55mA
Voltage ..................................................–3V to 5V
Plastic SOIC .................................................. 105°C/W
CC
I
SENSE
Voltage on Any Other Pin ... GND – 0.3V to V
+ 0.3V
CCZ
............................................................................................ 20mA
OPERATING CONDITIONS
I
REF
I
AC
Input Current .................................................... 10mA
Peak PFC OUT Current, Source or Sink ................ 500mA
Peak PWM OUT Current, Source or Sink .............. 500mA
PFC OUT, PWM OUT Energy Per Cycle .................. 1.5µJ
Temperature Range
ML4827CX ................................................. 0°C to 70°C
ML4827IX .............................................. –40°C to 85°C
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, I = 25mA, R = 21.8kΩ, C = 1000pF, T = Operating Temperature Range (Note 1)
CC
T
T
A
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VOLTAGE ERROR AMPLIFIER
Input Voltage Range
0
7
V
Ω
Transconductance
VNON INV = VINV, VEAO = 3.75V
50
85
2.55
–1
120
2.62
–2
µ
Feedback Reference Voltage
2.48
V
µA
V
Input Bias Current
Output High Voltage
Output Low Voltage
Source Current
Note 2
6.0
6.7
0.6
–80
80
1.0
V
∆VIN = ±0.5V, VOUT = 6V
∆VIN = ±0.5V, VOUT = 1.5V
–40
40
µA
µA
dB
dB
Sink Current
Open Loop Gain
60
75
Power Supply Rejection Ratio
VCCZ - 3V < VCC < VCCZ - 0.5V
60
75
CURRENT ERROR AMPLIFIER
Input Voltage Range
Transconductance
Input Offset Voltage
Input Bias Current
Output High Voltage
Output Low Voltage
Source Current
–1.5
130
2
2
V
Ω
VNON INV = VINV, VEAO = 3.75V
195
10
310
17
µ
mV
µA
V
–0.5
6.7
0.6
–90
90
–1.0
6.0
1.0
V
∆VIN = ±0.5V, VOUT = 6V
∆VIN = ±0.5V, VOUT = 1.5V
–40
40
µA
µA
dB
dB
Sink Current
Open Loop Gain
60
75
Power Supply Rejection Ratio
VCCZ - 3V < VCC < VCCZ - 0.5V
60
75
OVP COMPARATOR
Threshold Voltage
Hysteresis
2.6
80
2.7
2.8
V
115
150
mV
3
ML4827
ELECTRICAL CHARACTERISTICS (Continued)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
TRI-FAULT DETECT
FaultDetectHIGH
2.6
2.7
2.8
V
Time to Fault Detect HIGH
V
FB
= V
to V =OPEN
FAULT DETECT LOW FB
1nF from VFB to GND
1
2
ms
V
Fault Detect LOW
0.4
0.5
0.6
PFC ILIMIT COMPARATOR
Threshold Voltage
–0.8
100
–1.0
190
150
–1.15
300
V
mV
ns
∆(PFC ILIMIT VTH - Gain Modulator Output)
Delay to Output
DC ILIMIT COMPARATOR
Threshold Voltage
Input Bias Current
Delay to Output
0.9
1.0
±0.3
150
1.1
±1
V
µA
ns
300
VIN OK COMPARATOR
Threshold Voltage
Hysteresis
2.45
0.8
2.55
1.0
2.65
1.2
V
V
GAINMODULATOR
Gain (Note 3)
IAC = 100µA, VRMS = VFB = 0V
IAC = 50µA, VRMS = 1.2V, VFB = 0V
IAC = 50µA, VRMS = 1.8V, VFB = 0V
IAC = 100µA, VRMS = 3.3V, VFB = 0V
IAC = 100µA
0.36
1.20
0.55
0.14
0.55
1.80
0.80
0.20
10
0.66
2.24
1.01
0.26
Bandwidth
MHz
V
Output Voltage
IAC = 250µA, VRMS = 1.15V,
VFB = 0V
0.74
75
0.82
0.90
85
OSCILLATOR
Initial Accuracy
TA = 25°C
80
1
kHz
%
Voltage Stability
VCCZ - 3V < VCC < VCCZ - 0.5V
Temperature Stability
Total Variation
2
%
Line, Temp
72
88
kHz
V
Ramp Valley to Peak Voltage
Dead Time
2.5
600
7.5
PFC Only
450
4.5
750
9.5
ns
CT Discharge Current
VRAMP 2 = 0V, VRAMP 1 = 2.5V
mA
4
ML4827
ELECTRICAL CHARACTERISTICS (Continued)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
REFERENCE
Output Voltage
TA = 25°C, I(VREF) = 1mA
VCCZ - 3V < VCC < VCCZ - 0.5V
1mA < I(VREF) < 20mA
7.4
7.5
2
7.6
10
15
V
mV
mV
%
Line Regulation
Load Regulation
Temperature Stability
Total Variation
2
0.4
Line, Load, Temp
7.35
7.65
25
V
Long Term Stability
TJ = 125°C, 1000 Hours
5
mV
PFC
Minimum Duty Cycle
Maximum Duty Cycle
Output Low Voltage
VIEAO > 4.0V
0
%
%
V
V
V
V
V
ns
VIEAO < 1.2V
90
95
0.4
0.8
0.7
10.5
10
IOUT = -20mA
IOUT = -100mA
IOUT = 10mA, VCC = 8V
IOUT = 20mA
0.8
2.0
1.5
Output High Voltage
Rise/FallTime
10
IOUT = 100mA
CL = 1000pF
9.5
50
PWM
Duty Cycle Range
Output Low Voltage
ML4827-1
0-44
0-64
0-47
0-70
0.4
0-50
0-74
0.8
%
%
V
V
V
V
V
ns
ML4827-2
IOUT = -20mA
IOUT = -100mA
IOUT = 10mA, VCC = 8V
IOUT = 20mA
IOUT = 100mA
CL = 1000pF
0.8
2.0
0.7
1.5
Output High Voltage
Rise/FallTime
10
10.5
10
9.5
50
SUPPLY
Shunt Regulator Voltage (VCCZ
VCCZ Load Regulation
VCCZ Total Variation
Start-up Current
)
12.8
12.4
13.5
14.2
±300
14.6
1.0
V
mV
V
25mA < ICC < 55mA
Load, Temp
±100
VCC = 11.8V, CL = 0
VCC < VCCZ - 0.5V, CL = 0
0.7
16
mA
mA
V
Operating Current
19
Undervoltage Lockout Threshold
Undervoltage Lockout Hysteresis
12
13
14
2.7
3.0
3.3
V
Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
Note 2: Includes all bias currents to other circuits connected to the VFB pin.
Note 3: Gain = K x 5.3V; K = (IGAINMOD - IOFFSET) x IAC x (VEAO - 1.5V)-1
.
5
ML4827
TYPICAL PERFORMANCE CHARACTERISTICS
250
200
150
100
50
250
200
150
100
50
0
–500
0
0
500
0
1
2
3
4
5
IEA INPUT VOLTAGE (mV)
V
(V)
FB
Voltage Error Amplifier (VEA) Transconductance (g )
Current Error Amplifier (IEA) Transconductance (g )
m
m
400
300
200
100
0
0
1
2
3
4
5
V
(mV)
RMS
Gain ModulatorTransfer Characteristic (K)
16
1
13
2µA
V
CC
VEAO
VEA
IEAO
POWER FACTOR CORRECTOR
BROKEN WIRE
V
V
CCZ
REF
V
REF
OVP
7.5V
REFERENCE
V
FB
13.5V
14
+
–
IEA
COMPARATOR
3.5kΩ
15
–
+
+
–
2.7V
1V
2.5V
AC
+
–
S
Q
I
+
–
2
4
3
–1V
+
–
GAIN
MODULATOR
V
R
S
Q
Q
RMS
PFC OUT
3.5kΩ
PFC I
I
LIMIT
12
SENSE
R
Q
RAMP 1
7
OSCILLATOR
Figure 1. PFC Section Block Diagram.
6
ML4827
FUNCTIONAL DESCRIPTION
The ML4827 consists of an average current controlled,
continuous boost Power Factor Corrector (PFC) front end
and a synchronized Pulse Width Modulator (PWM) back
end. The PWM can be used in either current or voltage
mode. In voltage mode, feedforward from the PFC output
buss can be used to improve the PWM’s line regulation. In
either mode, the PWM stage uses conventional trailing-
edge duty cycle modulation, while the PFC uses leading-
edge modulation. This patented leading/trailing edge
modulation technique results in a higher useable PFC
error amplifier bandwidth, and can significantly reduce
the size of the PFC DC buss capacitor.
instantaneous amplitude, it will appear resistive to the AC
line and a unity power factor will be achieved.
To hold the input current draw of a device drawing power
from the AC line in phase with and proportional to the
input voltage, a way must be found to prevent that device
from loading the line except in proportion to the
instantaneous line voltage. The PFC section of the
ML4827 uses a boost-mode DC-DC converter to
accomplish this. The input to the converter is the full
wave rectified AC line voltage. No bulk filtering is
applied following the bridge rectifier, so the input voltage
to the boost converter ranges (at twice line frequency)
from zero volts to the peak value of the AC input and
back to zero. By forcing the boost converter to meet two
simultaneous conditions, it is possible to ensure that the
current which the converter draws from the power line
agrees with the instantaneous line voltage. One of these
conditions is that the output voltage of the boost converter
must be set higher than the peak value of the line
voltage. A commonly used value is 385VDC, to allow for
The synchronization of the PWM with the PFC simplifies
the PWM compensation due to the controlled ripple on
the PFC output capacitor (the PWM input capacitor). The
PWM section of both the ML4827-1 and the ML4827-2 run
at the same frequency as the PFC.
A number of protection features have been built into the
ML4827 to insure the final power supply will be as
reliable as possible. These include TriFault Detect, soft-
start, PFC over-voltage protection, peak current limiting,
brown-out protection, duty cycle limit, and under-voltage
lockout.
a high line of 270VAC . The other condition is that the
rms
current which the converter is allowed to draw from the
line at any given instant must be proportional to the line
voltage. The first of these requirements is satisfied by
establishing a suitable voltage control loop for the
converter, which in turn drives a current error amplifier
and switching output driver. The second requirement is
met by using the rectified AC line voltage to modulate
the output of the voltage control loop. Such modulation
causes the current error amplifier to command a power
stage current which varies directly with the input voltage.
In order to prevent ripple which will necessarily appear at
the output of the boost circuit (typically about 10VAC on
a 385V DC level) from introducing distortion back through
the voltage error amplifier, the bandwidth of the voltage
loop is deliberately kept low. A final refinement is to
adjust the overall gain of the PFC such to be proportional
to 1/VIN2, which linearizes the transfer function of the
system as the AC input voltage varies.
TRI-FAULTDETECTPROTECTION
Many power supplies manufactured for sale in the US
must meet Underwriter’s Laboratories (UL) standards. UL’s
specification UL1950 requires that no unsafe condition
may result from the failure of any single circuit
component. Typical system designs include external
active and passive circuitry to meet this requirement.
TriFault Detect is an on-chip feature of the ML4827 that
monitors the VFB pin for overvoltage, undervoltage, or
floating conditions which indicate that a component of
the feedback path may have failed. In such an event, the
PFC supply output will be disabled. These integrated
redundant protections assure system compliance with
UL1950 requirements.
Since the boost converter topology in the ML4827 PFC is
of the current-averaging type, no slope compensation is
required.
POWER FACTOR CORRECTION
Power factor correction makes a nonlinear load look like
a resistive load to the AC line. For a resistor, the current
drawn from the line is in phase with and proportional to
the line voltage, so the power factor is unity (one). A
common class of nonlinear load is the input of most
power supplies, which use a bridge rectifier and
capacitive input filter fed from the line. The peak-
charging effect which occurs on the input filter capacitor
in these supplies causes brief high-amplitude pulses of
current to flow from the power line, rather than a
sinusoidal current in phase with the line voltage. Such
supplies present a power factor to the line of less than one
(i.e. they cause significant current harmonics of the power
line frequency to appear at their input). If the input
current drawn by such a supply (or any other nonlinear
load) can be made to follow the input voltage in
PFC SECTION
Gain Modulator
Figure 1 shows a block diagram of the PFC section of the
ML4827. The gain modulator is the heart of the PFC, as it
is this circuit block which controls the response of the
current loop to line voltage waveform and frequency,
RMS line voltage, and PFC output voltage. There are three
inputs to the gain modulator. These are:
1) A current representing the instantaneous input voltage
(amplitude and waveshape) to the PFC. The rectified
AC input sine wave is converted to a proportional
current via a resistor and is then fed into the gain
7
ML4827
FUNCTIONAL DESCRIPTION (Continued)
V
REF
modulator at I . Sampling current in this way
AC
minimizes ground noise, as is required in high power
switching power conversion environments. The gain
modulator responds linearly to this current.
PFC
OUTPUT
2) A voltage proportional to the long-term RMS AC line
voltage, derived from the rectified line voltage after
scaling and filtering. This signal is presented to the gain
16
1
IEAO
VEAO
VEA
modulator at V
inversely proportional to V
low values of V
. The gain modulator’s output is
RMS
V
2
FB
(except at unusually
RMS
IEA
15
–
where special gain contouring
RMS
+
–
+
–
2.5V
AC
+
takes over, to limit power dissipation of the circuit
components under heavy brownout conditions). The
I
2
4
3
relationship between V
illustrated in the Typical Performance Characteristics.
and gain is termed K, and is
RMS
GAIN
MODULATOR
V
RMS
I
3) The output of the voltage error amplifier, VEAO. The
gain modulator responds linearly to variations in this
voltage.
SENSE
Figure 2. Compensation Network Connections for the
Voltage and Current Error Amplifiers
The output of the gain modulator is a current signal, in the
form of a full wave rectified sinusoid at twice the line
frequency. This current is applied to the virtual-ground
(negative) input of the current error amplifier. In this way
the gain modulator forms the reference for the current
error loop, and ultimately controls the instantaneous
current draw of the PFC from the power line. The general
form for the output of the gain modulator is:
arrangement of the duty cycle modulator polarities
internal to the PFC, an increase in positive current from
the gain modulator will cause the output stage to increase
IAC ´ VEAO
its duty cycle until the voltage on I
is adequately
SENSE
IGAINMOD
=
´ 1V
(1)
2
negative to cancel this increased current. Similarly, if the
gain modulator’s output decreases, the output duty cycle
will decrease, to achieve a less negative voltage on the
V
RMS
More exactly, the output current of the gain modulator is
given by:
I
pin.
SENSE
IGAINMOD = K ´ (VEAO - 1.5V) ´ IAC
Cycle-By-Cycle Current Limiter
The I pin, as well as being a part of the current
-1
where K is in units of V .
SENSE
feedback loop, is a direct input to the cycle-by-cycle
current limiter for the PFC section. Should the input
voltage at this pin ever be more negative than -1V, the
output of the PFC will be disabled until the protection
flip-flop is reset by the clock pulse at the start of the next
PFC power cycle.
Note that the output current of the gain modulator is
limited to 200µA.
Current Error Amplifier
The current error amplifier’s output controls the PFC duty
cycle to keep the average current through the boost
inductor a linear function of the line voltage. At the
inverting input to the current error amplifier, the output
current of the gain modulator is summed with a current
which results from a negative voltage being impressed
Overvoltage Protection
The OVP comparator serves to protect the power circuit
from being subjected to excessive voltages if the load
should suddenly change. A resistor divider from the high
upon the I
The negative voltage on I
pin (current into I
V
/3.5kΩ).
voltage DC output of the PFC is fed to V . When the
SENSE
SENSE
SENSE
FB
represents the sum of all
voltage on V exceeds 2.7V, the PFC output driver is shut
SENSE
FB
currents flowing in the PFC circuit, and is typically
derived from a current sense resistor in series with the
negative terminal of the input bridge rectifier. In higher
power applications, two current transformers are
down. The PWM section will continue to operate. The
OVP comparator has 125mV of hysteresis, and the PFC
will not restart until the voltage at V drops below 2.58V.
FB
The V should be set at a level where the active and
FB
sometimes used, one to monitor the I of the boost
passive external power components and the ML4827 are
within their safe operating voltages, but not so low as to
interfere with the boost voltage regulation loop.
D
MOSFET(s) and one to monitor the I of the boost diode.
F
As stated above, the inverting input of the current error
amplifier is a virtual ground. Given this fact, and the
8
ML4827
FUNCTIONAL DESCRIPTION (Continued)
ErrorAmplifier Compensation
Oscillator (RAMP 1)
The oscillator frequency is determined by the values of R
The PWM loading of the PFC can be modeled as a
negative resistor; an increase in input voltage to the PWM
causes a decrease in the input current. This response
dictates the proper compensation of the two
transconductance error amplifiers. Figure 2 shows the
types of compensation networks most commonly used for
the voltage and current error amplifiers, along with their
respective return points. The current loop compensation is
T
and C , which determine the ramp and off-time of the
T
oscillator output clock:
1
fOSC
=
(2)
(3)
tRAMP + tDEADTIME
The deadtime of the oscillator is derived from the
following equation:
returned to V
to produce a soft-start characteristic on
REF
the PFC: as the reference voltage comes up from zero
volts, it creates a differentiated voltage on IEAO which
prevents the PFC from immediately demanding a full duty
cycle on its boost converter.
F
H
I
K
V
-1.25
- 3.75
REF
= C ´R ´InGV
T
J
tRAMP
T
REF
at V
= 7.5V:
REF
There are two major concerns when compensating the
voltage loop error amplifier; stability and transient
response. Optimizing interaction between transient
response and stability requires that the error amplifier’s
open-loop crossover frequency should be 1/2 that of the
line frequency, or 23Hz for a 47Hz line (lowest
anticipated international power frequency). The gain vs.
input voltage of the ML4827’s voltage error amplifier has
a specially shaped nonlinearity such that under steady-
state operating conditions the transconductance of the
error amplifier is at a local minimum. Rapid perturbations
in line or load conditions will cause the input to the
tRAMP = CT ´RT ´0.51
The deadtime of the oscillator may be determined using:
2.5V
tDEADTIME
=
´ CT = 490 ´ CT
(4)
5.1mA
The deadtime is so small (t
operating frequency can typically be approximated by:
>> t
) that the
RAMP
DEADTIME
1
fOSC
=
(5)
voltage error amplifier (V ) to deviate from its 2.5V
tRAMP
FB
(nominal) value. If this happens, the transconductance of
the voltage error amplifier will increase significantly, as
shown in the Typical Performance Characteristics. This
raises the gain-bandwidth product of the voltage loop,
resulting in a much more rapid voltage loop response to
such perturbations than would occur with a conventional
linear gain characteristic.
EXAMPLE:
For the application circuit shown in the data sheet, with
the oscillator running at:
1
fOSC = 100kHz =
tRAMP
-5
The current amplifier compensation is similar to that of
the voltage error amplifier with the exception of the
choice of crossover frequency. The crossover frequency of
the current amplifier should be at least 10 times that of
the voltage amplifier, to prevent interaction with the
voltage loop. It should also be limited to less than 1/6th
that of the switching frequency, e.g. 16.7kHz for a
100kHz switching frequency.
tRAMP = CT ´ RT ´ 0.51= 1´ 10
-4
Solving for R x C yields 2 x 10 . Selecting standard
components values, C = 470pF, and R = 41.2kΩ.
T
T
T
T
The deadtime of the oscillator adds to the Maximum
PWM Duty Cycle (it is an input to the Duty Cycle
Limiter). With zero oscillator deadtime, the Maximum
PWM Duty Cycle is typically 45% for the ML4827-1. In
many applications of the ML4827-1, care should be taken
that C not be made so large as to extend the Maximum
Duty Cycle beyond 50%. This can be accomplished by
There is a modest degree of gain contouring applied to the
transfer characteristic of the current error amplifier, to
increase its speed of response to current-loop
T
perturbations. However, the boost inductor will usually be
the dominant factor in overall current loop response.
Therefore, this contouring is significantly less marked than
that of the voltage error amplifier.
using a stable 470pF capacitor for C .
T
For more information on compensating the current and
voltage control loops, see Application Notes 33 and 34.
Application Note 16 also contains valuable information
for the design of this class of PFC.
9
ML4827
FUNCTIONAL DESCRIPTION (Continued)
PWM SECTION
fewer turns on forward converter reset windings. Long
duty cycles, by allowing greater utilization of the PFC’s
stored charge, can also lower the cost of PFC bus
capacitors while still offering long “hold-up” times.
PulseWidth Modulator
The PWM section of the ML4827 is straightforward, but
there are several points which should be noted. Foremost
among these is its inherent synchronization to the PFC
section of the device, from which it also derives its basic
timing. The PWM is capable of current-mode or voltage
mode operation. In current-mode applications, the PWM
ramp (RAMP 2) is usually derived directly from a current
sensing resistor or current transformer in the primary of the
output stage, and is thereby representative of the current
NOTE: during the time when the PWM switch is off (the
reset or flyback periods), increasing duty cycles will result
in rapidly increasing peak voltages across the switch.
This result of high PWM duty cycles requires greater care
be used in circuit design. Relevant design issues include:
•
•
Higher voltage (>1000V) PWM switches
flowing in the converter’s output stage. DC I , which
LIMIT
More carefully designed and tested PWM
transformers
provides cycle-by-cycle current limiting, is typically
connected to RAMP 2 in such applications. For voltage-
mode operation or certain specialized applications,
RAMP 2 can be connected to a separate RC timing
network to generate a voltage ramp against which VDC
will be compared. Under these conditions, the use of
voltage feedforward from the PFC buss can assist in line
regulation accuracy and response. As in current mode
•
Clamps and/or snubbers when needed
Also, slope compensation will be required in most current
mode PWM designs.
For those who want to approach the limits of attainable
performance (most commonly high-volume, low-cost
supplies), the ML4827-2’s 70% maximum PWM duty
cycle offers several desirable design capabilities. Using a
70% duty cycle makes it essential to perform a careful
magnetics design and component stress analysis before
finalizing designs with the ML4827-2.
operation, the DC I
input would is used for output
LIMIT
stage overcurrent protection.
No voltage error amplifier is included in the PWM stage
of the ML4827, as this function is generally performed on
the output side of the PWM’s isolation boundary. To
facilitate the design of optocoupler feedback circuitry, an
offset has been built into the PWM’s RAMP 2 input which
THE ML4827-2: SPECIAL CONSIDERATIONS FOR HIGH
DUTY CYCLES
allows V to command a zero percent duty cycle for
DC
input voltages below 1.25V.
The use of the ML4827-1, especially with the type of
PWM output stage shown in the Application Circuit of
Figure 6, is straightforward due to the limitation of the
PWM duty cyle to 50% maximum. In fact, one of the
advantages of the “two-transistor single-ended forward
converter” shown in Figure 6 is that it will necessarily
reset the core, with no additional winding required, as
long as the core does not go into saturation during the
topology's maximum permissible 50% duty cycle.
Maximum Duty Cycle
In the ML4827-1, the maximum duty cycle of the PWM
section is limited to 50% for ease of use and design. In
the case of the ML4827-2, the maximum duty cycle of
the PWM section is extended to 70% (typical) for
enhanced utilization of the inductor. Operation at 70%
duty cycle requires special care in circuit design to avoid
volt-second imbalances, and/or high-voltage damage to
the PWM switch transistor(s).
For the “-2” version of the ML4827, the maximum duty
cycle (δ) of the PWM is nominally 70%. As the two-
transistor single-ended forward converter cannot be used
at duty cycles greater than 50%, high-δ applications
require the use of either a single-transistor forward
converter (with a transformer reset winding), or a flyback
output stage. In either case, special concerns arise
regarding the peak voltage appearing on the PWM switch
transistor, the PWM output transformer, and associated
power components as the duty cycle increases. For any
output stage topology, the available on-time (core “set”
Using the ML4827-2
The ML4827-2’s higher PWM duty cycle offers several
design advantages that skilled power supply and
magnetics engineers can take advantage of, including:
•
•
Reduced RMS and peak PWM switch currents
Reduced RMS and peak PWM transformer
currents
time) is (1/f ) x δ, while the reset time for the core of
PWM
the PWM output transformer is (1/f
) x (1–δ). This
PWM
•
Easier RFI/EMI filtering due to lower peak
currents
means that the magnetizing inductance of the core
charges for a period of (1/f ) x δ, and must be
PWM
completely discharged during a period of (1/f
) x
PWM
These reduced currents can result in cost savings by
allowing smaller PWM transformer primary windings and
(1–δ). The ratio of these two periods, multiplied by the
maximum value of the PFC’s V , yields the minimum
BUSS
10
ML4827
FUNCTIONAL DESCRIPTION (Continued)
voltage for which the PWM output transistor must be
rated. Frequently, the design of the tranformer’s reset
winding, and/or of the output transistor’s snubbers or
clamps, require an additional voltage margin of 100V to
200V.
at the lowest guaranteed value for δ, to ensure that the
magnetics will deliver full output power with any
individual ML4827. In actual operation, the choice of
δ
= 60% will allow some tolerance for the timing
MIN
capacitors and resistors. A tolerance on (R
x
RAMP2
C
) of ±2% is the simplest “brute force” way to
RAMP2
achieve the desired result. This should be combined with
an external duty cycle clamp. This protects the PWM
circuitry against the condition in which the output has
To put some numbers into the discussion, with a given
V
of 400V:
BUSS(MAX)
been shorted, and the error amplifier output (V ) would
1. For δ = 50%: V
= {[(1/f
) x δ]/[(1/f ) x
PWM
DC
RESET
PWM
otherwise be driven to its upper rail. One method which
works well when the PWM is used in voltage mode is to
limit the maximum input to the PWM feedback voltage
(1–δ)]} x 400V = 0.50/0.50 x 400V = 400V
2. For δ = 55%: V
3. For δ = 60%: V
= 0.55/0.45 x 400V = 489V
= 0.60/0.40 x 400V = 600V
RESET
(V ). If the voltage available to this pin is derived from
DC
the ML4827’s 7.5V V , it will be in close ratio to the
REF
RESET
charging time of the RAMP2 capacitor. This will be true
whether the RAMP2 capacitor is charged from V , or, as
4. For δ = 64% (Data Sheet Lower Limit Value): V
=
=
REF
RESET
is more commonly done in voltage-mode applications,
from the output of the PFC Stage (the “feedforward”
configuration). Figure 3 shows such a duty cycle clamp.
0.64/0.36 x 400V = 711V
5. For δ = 70%: V
= 0.70/0.30 x 400V = 933V
RESET
If the ML4827-2’s PWM is to be used in a current-mode
design, the PWM stage will require slope compensation.
This can be done by any of the standard industry
techniques. Note that the ramp to use for this slope
compensation is the voltage on RAMP1.
6. For δ = 74% (Data Sheet Upper Limit Value): V
RESET
0.74/0.26 x 400V = 1138V
It is economically desirable to design for the lowest
meaningful voltage on the output MOSFET. It is
simultaneously necessary to design the circuit to operate
PFC V
BUSS
R
R
FB1
FB2
R
RAMP2
V
FB
RAMP2
C
RAMP2
V
V
REF
R1
PWM
ERROR
AMP
DC
R2
R
R
V
2
1
REF
+ R
δ
=
V
RAMP2 (PEAK)
MAX
2
Figure 3. ML4827- PWM Duty Cycle Clamp for Voltage-Made Operation
11
ML4827
FUNCTIONAL DESCRIPTION (Continued)
It is important that the time constant of the PWM soft-start
allow the PFC time to generate sufficient output power for
the PWM section. The PWM start-up delay should be at
least 5ms.
Using the recommended values of δ
= 60% and δ
MAX
MIN
= 64% for a high-δ application, a MOSFET switch with a
Drain-Source breakdown voltage of 900V, or in some
cases as low as 800V, can reliably be used. Such parts are
readily and inexpensively available from a number of
vendors.
Solving for the minimum value of C :
SS
50µA
V
OK Comparator
IN
CSS = 5ms ×
220nF
1.25V
The V OK comparator monitors the DC output of the
PFC and inhibits the PWM if this voltage on V is less
IN
Generating V
CC
FB
than its nominal 2.5V. Once this voltage reaches 2.5V,
which corresponds to the PFC output capacitor being
charged to its rated boost voltage, the soft-start begins.
The ML4827 is a current-fed part. It has an internal shunt
voltage regulator, which is designed to regulate the
voltage internal to the part at 13.5V. This allows a low
power dissipation while at the same time delivering 10V
of gate drive at the PWM OUT and PFC OUT outputs. It is
important to limit the current through the part to avoid
overheating or destroying it. This can be easily done with
PWM Control (RAMP 2)
When the PWM section is used in current mode, RAMP 2
is generally used as the sampling point for a voltage
representing the current in the primary of the PWM’s
output transformer, derived either by a current sensing
resistor or a current transformer. In voltage mode, it is the
input for a ramp voltage generated by a second set of
a single resistor in series with the V pin, returned to a
CC
bias supply of typically 18V to 20V. The resistor’s value
must be chosen to meet the operating current requirement
of the ML4827 itself (19mA max) plus the current required
by the two gate driver outputs.
timing components (R
, C
), which will have a
RAMP2
RAMP2
minimum value of zero volts and should have a peak
value of approximately 5V. In voltage mode operation,
feedforward from the PFC output buss is an excellent way
to derive the timing ramp for the PWM stage.
EXAMPLE:
With a V
of 20V, a V limit of 14.6V (max) and the
CC
BIAS
ML4827 driving a total gate charge of 110nC at 100kHz
(e.g., 1 IRF840 MOSFET and 2 IRF830 MOSFETs), the
gate driver current required is:
Soft Start
IGATEDRIVE = 100kHz ´ 100nC = 11mA
(7)
(8)
Start-up of the PWM is controlled by the selection of the
external capacitor at SS. A current source of 50µA
supplies the charging current for the capacitor, and start-
up of the PWM begins at 1.25V. Start-up delay can be
programmed by the following equation:
20V - 14.6V
RBIAS
=
= 180Ω
19mA + 11mA
To check the maximum dissipation in the ML4827, find
the current at the minimum V (12.4V):
50µA
´
CC
CSS = tDELAY
(6)
1.25V
20V - 12.4V
ICC
=
= 42.2mA
(9)
where C is the required soft start capacitance, and
SS
180Ω
t
is the desired start-up delay.
DELAY
The maximum allowable I is 55mA, so this is an
CC
acceptable design.
V
BIAS
R
BIAS
V
CC
ML4827
GND
10nF
CERAMIC
1µF
CERAMIC
Figure 4. External Component Connections to V
CC
12
ML4827
FUNCTIONAL DESCRIPTION (Continued)
trailing edge modulation is determined during the ON
time of the switch. Figure 5 shows a typical trailing edge
control scheme.
The ML4827 should be locally bypassed with a 10nF and
a 1µF ceramic capacitor. In most applications, an
electrolytic capacitor of between 100µF and 330µF is also
required across the part, both for filtering and as part of
the start-up bootstrap circuitry.
In the case of leading edge modulation, the switch is
turned OFF right at the leading edge of the system clock.
When the modulating ramp reaches the level of the error
amplifier output voltage, the switch will be turned ON.
The effective duty-cycle of the leading edge modulation
is determined during the OFF time of the switch. Figure 6
shows a leading edge control scheme.
LEADING/TRAILING MODULATION
Conventional Pulse Width Modulation (PWM) techniques
employ trailing edge modulation in which the switch will
turn on right after the trailing edge of the system clock.
The error amplifier output voltage is then compared with
the modulating ramp. When the modulating ramp reaches
the level of the error amplifier output voltage, the switch
will be turned OFF. When the switch is ON, the inductor
current will ramp up. The effective duty cycle of the
One of the advantages of this control technique is that it
requires only one system clock. Switch 1 (SW1) turns off
and switch 2 (SW2) turns on at the same instant to
minimize the momentary “no-load” period, thus lowering
ripple voltage generated by the switching action. With
SW2
SW1
I2
I3
I4
L1
I1
+
VIN
RL
DC
RAMP
VEAO
C1
REF
U3
EA
+
–
TIME
VSW1
DFF
+
–
R
D
RAMP
CLK
Q
U1
U2
OSC
U4
Q
CLK
TIME
Figure 5. Typical Trailing Edge Control Scheme.
SW2
SW1
I2
I3
I4
L1
I1
+
VIN
RL
RAMP
DC
C1
VEAO
U3
EA
+
–
TIME
REF
VEAO
VSW1
DFF
CMP
+
–
R
RAMP
CLK
Q
Q
U1
OSC
U4
D
U2
CLK
TIME
Figure 6. Typical Leading Edge Control Scheme.
13
ML4827
LEADING/TRAILING MOD. (Continued)
TYPICAL APPLICATIONS
such synchronized switching, the ripple voltage of the
first stage is reduced. Calculation and evaluation have
shown that the 120Hz component of the PFC’s output
ripple voltage can be reduced by as much as 30% using
this method.
Figure 7 is the application circuit for a complete 100W
power factor corrected power supply. This circuit was
designed using the methods and topology detailed in
Application Note 33.
AC INPUT
85 TO 265VAC
F1
3.15A
C1
470nF
D1
L1
3.1mH
8A, 600V,
"FRED" Diode
Q2
IRF830
Q1
IRF840
R17
33Ω
C4
10nF
C5
100µF
R2A
357kΩ
C25
100nF
BR1
4A, 600V
D5
BYV26C
T1
R1A
D7
15V
R30
4.7kΩ
499kΩ
L2
33µH
D11
MBR2545CT
R27
39kΩ
2W
T2
R21
22Ω
R15
3Ω
12VDC
RTN
C24
1µF
R2B
357kΩ
C21
1800µF
D6
BYV26C
C20
1µF
D3
BYV26C
R28
180Ω
R24
1.2kΩ
C3
470nF
R1B
499kΩ
R14
33Ω
C30
330µF
C22
4.7µF
Q3
IRF830
C12
10µF
10kΩ
R23
1.5kΩ
D12
1N5401
R18
220Ω
9W
R7A
178kΩ
R3
75kΩ
R22
8.66kΩ
D13
1N5401
R20
1.1Ω
C23
100nF
C7
220pF
R26
10kΩ
R19
220Ω
R25
2.26kΩ
MOC
8102
R7B
178kΩ
C6
1nF
R12
27kΩ
TL431
C2
R4
470nF
13kΩ
1
16
15
14
13
12
11
10
9
IEAO
VEAO
C9
8.2nF
2
3
4
5
6
7
8
I
I
V
FB
AC
C31
1nF
R11
750kΩ
V
R8
2.37kΩ
SENSE
REF
C13
100nF
C14
1µF
C8
82nF
R5
300mΩ
1W
V
V
CC
RMS
C15
10nF
C16
1µF
SS
PFC OUT
PWM OUT
GND
C19
1µF
V
DC
D8
1N5818
RAMP 1
D10
1N5818
RAMP 2 DC I
ML4827-1
LIMIT
L1: Premier Magnetics #TSD-734
L2: 33µH, 10A DC
T1: Premier Magnetics #TSD-736
T2: Premier Magnetics #TSD-735
C17
220pF
C18
470pF
R6
41.2kΩ
R10
6.2kΩ
Premier Magnetics: (714) 362-4211
C11
10nF
Figure 7. 100W Power Factor Corrected Power Supply, Designed Using Micro Linear Application Note 33.
14
ML4827
PHYSICAL DIMENSIONS inches (millimeters)
Package: P16
16-Pin PDIP
0.740 - 0.760
(18.79 - 19.31)
16
0.240 - 0.260 0.295 - 0.325
(6.09 - 6.61) (7.49 - 8.26)
PIN 1 ID
1
0.02 MIN
(0.50 MIN)
(4 PLACES)
0.055 - 0.065
(1.40 - 1.65)
0.100 BSC
(2.54 BSC)
0.015 MIN
(0.38 MIN)
0.170 MAX
(4.32 MAX)
SEATING PLANE
0.008 - 0.012
(0.20 - 0.31)
0.016 - 0.022
(0.40 - 0.56)
0º - 15º
0.125 MIN
(3.18 MIN)
Package: S16N
16-Pin Narrow SOIC
0.386 - 0.396
(9.80 - 10.06)
16
0.148 - 0.158 0.228 - 0.244
(3.76 - 4.01) (5.79 - 6.20)
PIN 1 ID
1
0.017 - 0.027
(0.43 - 0.69)
(4 PLACES)
0.050 BSC
(1.27 BSC)
0.059 - 0.069
(1.49 - 1.75)
0º - 8º
0.012 - 0.020
(0.30 - 0.51)
0.015 - 0.035
(0.38 - 0.89)
0.006 - 0.010
(0.15 - 0.26)
0.055 - 0.061
(1.40 - 1.55)
0.004 - 0.010
(0.10 - 0.26)
SEATING PLANE
15
ML4827
ORDERING INFORMATION
PART NUMBER
MAX DUTY CYCLE
TEMPERATURE RANGE
PACKAGE
ML4827CP-1
ML4827CP-2
ML4827CS-1
ML4827CS-2
50%
74%
50%
74%
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
16-Pin PDIP (P16)
16-Pin PDIP (P16)
16-Pin Narrow SOIC (S16N)
16-Pin Narrow SOIC (S16N)
ML4827IP-1
ML4827IP-2
ML4827IS-1
ML4827IS-2
50%
74%
50%
74%
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
16-Pin PDIP (P16) (EOL)
16-Pin PDIP (P16)
16-Pin Narrow SOIC (S16N) (EOL)
16-Pin Narrow SOIC (S16N)
© Micro Linear 1998.
is a registered trademark of Micro Linear Corporation. All other trademarks are the property of their respective owners.
Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502;
5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; 5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167; 5,714,897;
5,717,798; 5,742,151; 5,747,977; 5,754,012; 5,757,174; 5,767,653; 5,777,514; 5,793,168; 5,798,635; 5,804,950; 5,808,455; 5,811,999; 5,818,207; 5,818,669;
5,825,165; 5,825,223; 5,838,723. Japan: 2,598,946; 2,619,299; 2,704,176; 2,821,714. Other patents are pending.
2092 Concourse Drive
San Jose, CA 95131
Tel: (408) 433-5200
Fax: (408) 432-0295
www.microlinear.com
Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability
arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits
contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits
infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult
with appropriate legal counsel before deciding on a particular application.
DS4827-01
16
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