SY10E167JCTR [MICREL]
6-BIT 2:1 MUX-REGISTER; 6位2： 1的MUX-注册。
| 型号： | SY10E167JCTR |
| 厂家： | 
MICREL SEMICONDUCTOR |
| 描述： | 6-BIT 2:1 MUX-REGISTER |
| 文件： | 总3页 (文件大小：158K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SY10E167
SY100E167
6-BIT 2:1 MUX-REGISTER
SYNERGY
SEMICONDUCTOR
FEATURES
DESCRIPTION
■ 1000MHz min. operating frequency
■ Extended 100E VEE range of –4.2V to –5.5V
■ 800ps max. clock to output
■ Single-ended outputs
The SY10/100E167 offer six 2:1 multiplexers followed
by D flip-flops with single-ended outputs, designed for use
in new, high-performance ECL systems. The Select (SEL)
control allows one of the two data inputs to the multiplexer
to pass through. The two external clock signals (CLK1,
CLK2) are gated through a logical OR operation before use
as control for the six flip-flops. The selected data are
transferred to the flip-flops on the rising edge of CLK1 or
CLK2 (or both).
■ Asynchronous Master Reset
■ Dual clocks
■ Fully compatible with industry standard 10KH,
100K ECL levels
The multiplexer operation is controlled by the Select
(SEL) signal which selects one of the two bits of input data
at each mux to be passed through.
■ Internal 75KΩ input pulldown resistors
■ ESD protection of 2000V
When a logic HIGH is applied to the Master Reset (MR)
signal, it operates asychronously to take all outputs Q to a
logic LOW.
■ Fully compatible with Motorola MC10E/100E167
■ Available in 28-pin PLCC package
BLOCK DIAGRAM
PIN CONFIGURATION
D0a
Q0
Q1
Q2
Q3
Q4
Q5
Q
Q
Q
Q
Q
Q
D
D
MUX
SEL
D0b
D1a
R
R
R
R
R
R
25 24 23 22 21 20 19
D
5b
Q
Q
5
4
26
27
28
1
18
17
16
15
14
13
12
MUX
SEL
CLK
1
CLK
2
VCC
D1b
D2a
TOP VIEW
PLCC
VEE
Q
Q
3
2
J28-1
MR
2
D
D
D
D
MUX
SEL
SEL
VCCO
3
D
0a
Q1
4
D2b
D3a
5
6
7
8
9
10 11
MUX
SEL
D3b
D4a
MUX
SEL
PIN NAMES
D4b
D5a
Pin
D0a–D5a
D0b–D5b
SEL
Function
Input Data a
Input Data b
Select Input
Clock Inputs
Master Reset
Data Outputs
VCC to Output
MUX
SEL
D5b
SEL
CLK1, CLK2
MR
CLK1
CLK2
Q0–Q5
VCCO
MR
Rev.: C
Amendment: /1
© 1999 Micrel-Synergy
Issue Date: February, 1998
5-127
SY10E167
SY100E167
SYNERGY
SEMICONDUCTOR
TRUTH TABLE
SEL
H
Data
a
b
L
DC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = 0°C
TA = +25°C
TA = +85°C
Symbol
IIH
Parameter
Input HIGH Current
Power Supply Current
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
Condition
—
—
150
—
—
150
—
—
150
µA
—
—
IEE
mA
10E
100E
—
—
94
94
113
113
—
—
94
94
113
113
—
—
94
108
113
130
AC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = 0°C
TA = +25°C
TA = +85°C
Symbol
Parameter
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
Condition
fMAX
Max. Toggle Frequency
1000 1400
—
1000 1400
—
1000 1400
—
MHz
ps
—
—
tPLH
tPHL
Propagation Delay to Output
CLK
MR
450 650 800 450 650
450 650 850 450 650
800 450 650
850 450 650
800
850
tS
tH
Set-up Time
D
SEL
ps
ps
—
—
100 –50
275 125
—
—
100 –50
275 125
—
—
100 –50
275 125
—
—
Hold Time
D
SEL
300
75 –125
50
—
—
300
75 –125
50
—
—
300
75 –125
50
—
—
tRR
tPW
Reset Recovery Time
750 550
—
—
750 550
—
—
750 550
—
—
ps
ps
—
—
Minimum Pulse Width
CLK, MR
400
—
—
400
—
—
400
—
—
tskew
Within-Device Skew
75
—
75
—
75
—
ps
ps
1
tr
tf
Rise/Fall Time
20% to 80%
300 450 800 300 450
800 300 450
800
—
NOTE:
1. Within-device skew is defined as identical transitions on similar paths through a device.
PRODUCT ORDERING CODE
Ordering
Code
Package
Type
Operating
Range
SY10E167JC
J28-1
J28-1
J28-1
J28-1
Commercial
Commercial
Commercial
Commercial
SY10E167JCTR
SY100E167JC
SY100E167JCTR
5-128
SY10E167
SY100E167
SYNERGY
SEMICONDUCTOR
28 LEAD PLASTIC LEADED CHIP CARRIER (J28-1)
5-129
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