SY100EL15L [MICREL]
3.3V 1:4 CLOCK DISTRIBUTION; 3.3V 1 : 4时钟分配型号: | SY100EL15L |
厂家: | MICREL SEMICONDUCTOR |
描述: | 3.3V 1:4 CLOCK DISTRIBUTION |
文件: | 总4页 (文件大小:57K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
3.3V 1:4 CLOCK
DISTRIBUTION
ClockWorks™
SY100EL15L
Synergy™ High-Speed Products
FEATURES
DESCRIPTION
The SY100EL15L is a low skew 1:4 clock distribution
IC designed explicitly for low skew clock distribution
applications. The device can be driven by either a
differential or single-ended ECL or, if positive power
supplies are used, PECL input signal. If a single-ended
input is to be used the VBB output should be connected
to the CLK input and bypassed to ground via a 0.01µF
capacitor. The VBB output is designed to act as the
switching reference for the input of the EL15 under single-
ended input conditions. As a result, this pin can only
source/sink up to 0.5mA of current.
■ 3.3V power supply
■ 50ps output-to-output skew
■ Low power
■ Synchronous enable/disable
■ Multiplexed clock input
■ 75KΩ internal input pull-down resistors
■ ESD protection of 2000V
■ Available in 16-pin SOIC package
The EL15 features a multiplexed clock input to allow
for the distribution of a lower speed scan or test clock
along with the high speed system clock. When LOW (or
left open and pulled LOW by the input pull-down resistor)
the SEL pin will select the differential clock input.
The common enable (EN) is synchronous so that the
outputs will only be enabled/disabled when they are
already in the LOW state. This avoids any chance of
generating a runt clock pulse when the device is enabled/
disabled as can happen with an asynchronous control.
The internal flip flop is clocked on the falling edge of the
input clock, therefore all associated specification limits
are referenced to the negative edge of the clock input.
When both differential inputs are left open, CLK input
will pull down to VEE and CLK input will bias around
VCC/2.
PIN CONFIGURATION/BLOCK DIAGRAM
CLK CLK
13 12
VBB
V
CC EN SCLK
VEE
SEL
10
16 15 14
11
9
1
0
D
Q
3
4
5
6
7
2
8
1
Q
0
Q0
Q
1
Q
1
Q
2
Q
3
3
Q
Q
2
SOIC
TOP VIEW
PIN NAMES
TRUTH TABLE
Pin
CLK
SCLK
EN
Function
CLK
L
SCLK
SEL
L
EN
L
Q
L
Differential Clock Inputs
Synchronous Clock Input
Synchronous Enable
Clock Select Input
X
X
L
H
L
L
H
L
X
H
L
SEL
VBB
X
H
X
H
L
H
L*
Reference Output
X
X
H
Q0-3
Differential Clock Outputs
* On next negative transition of CLK or SCLK
Rev.: A
Amendment:/0
© 1999 Micrel
Issue Date: December 1999
1
ClockWorks™
Micrel
SY100EL15L
(1)
ABSOLUTE MAXIMUM RATINGS
Symbol
VEE
Rating
Value
Unit
VDC
VDC
Power Supply (VCC = 0V)
Input Voltage (VCC = 0V)
Output Current
–8.0 to 0
0 to –6.0
VI
IOUT
–Continuous
–Surge
50
100
mA
TA
Operating Temperature Range
–40 to +85
°C
NOTES:
1. Absolute maximum rating, beyond which, device life may be impaired, unless otherwise specified on an individual data sheet.
2. Parametric values specified at:
3 volt Power Supply Range 100EL15L Series
–3.0V to –3.8V.
DC ELECTRICAL CHARACTERISTICS
(1)
VEE = 3.3V ±10%; VCC = GND
TA = –40°C
TA = 0°C
TA = +25°C
TA = +85°C
Min. Max.
–1025 –880
–1810 –1620
Symbol
VOH
VOL
VOHA
VOLA
VIH
Parameter
Min.
Max.
Min.
–1025
Max.
–880
–1620
—
Min.
–1025
Typ.
Max.
Unit
mV
mV
mV
mV
mV
mV
µA
Output HIGH Voltage(2)
Output LOW Voltage(2)
Output HIGH Voltage(3)
Output LOW Voltage(3)
Input HIGH Voltage
Input LOW Voltage
–1085
–880
–955
–880
–1830 –1555 –1810
–1810 –1705 –1620
–1095
—
—
–1035
—
–1035
—
—
—
—
—
—
—
–1035
—
—
–1555
–880
–1610
–880
–1475
150
–1610
–880
–1475
150
–1610
–880
–1165
–1165
–1165
–1810
—
–1165
VIL
–1810 –1475 –1810
–1810 –1475
IIH
Input High Current
—
150
—
—
150
IIL
Input LOW Current(4)
0.5
–300
—
—
0.5
–300
—
—
0.5
–300
—
—
0.5
–300
—
—
µA
CLK
—
25
—
IEE
Power Supply Current
—
35
—
35
—
35
—
38
mA
V
VBB
Output Reference Voltage
–1.38
–1.26
–1.38
–1.26
–1.38
–1.26
–1.38
–1.26
NOTES:
1. This table replaces the three traditionally seen in ECL 100K data books. Outputs are terminated through a 50Ω resistor to –2.0V.
2. VIN = VIH(Max) or VIL(Min).
3. VIN = VIH(Min) or VIL(Max).
4. VIN = VIL(Max).
2
ClockWorks™
Micrel
SY100EL15L
AC ELECTRICAL CHARACTERISTICS
(1)
VEE = 3.3V ±10%; VCC = GND
TA = –40°C
Min. Max.
TA = 0°C
TA = +25°C
TA = +85°C
Min. Max.
Symbol
Parameter
Min.
Max.
Min.
Typ.
Max.
Unit
tPLH
tPHL
Propagation Delay
CLK to Q (Diff)
CLK to Q (SE)
SCLK to Q
ps
460
410
410
660
710
710
470
420
420
670
720
720
470
420
420
—
—
—
670
720
720
500
450
470
700
750
750
tskew
Part-to-Part Skew(1)
Within-Device Skew
—
—
200
50
—
—
200
50
—
—
—
—
200
50
—
—
200
50
ps
tS
Setup Time EN
Hold Time EN
150
400
—
—
150
400
—
—
150
400
—
—
—
—
150
400
—
—
ps
ps
tH
VPP
Minimum Input Swing
CLK
250
—
250
—
250
—
—
250
—
mV
mV
VCMR
Common Mode Range(2)
VPP < 500mV
–2.0
–1.8
–0.4
–0.4
–2.1
–1.9
–0.4
–0.4
–2.1
–1.9
—
—
–0.4
–0.4
–2.1
–1.9
–0.4
–0.4
VPP ≥ 500mV
tr
tf
Output Rise/Fall TimesQ
(20% – 80%)
375
625
325
575
325
—
575
325
575
ps
NOTES:
1. Skews are specified for identical LOW-to-HIGH or HIGH-to-LOW transitions.
2. VCMR is referenced to the most positive side of the differential input signal. Normal operation is obtained when the input signals are within the VCMR range
and the input swing is greater than VPP(Min.) and <1V. The lower end of the VCMR range varies 1:1 with VEE. The numbers in the spec table assume a
nominal VEE = –3.3V. Note for PECL operation, the VCMR(Min) will be fixed at 3.3V – |VCMR(Min)|.
PRODUCT ORDERING CODE
Ordering
Code
Package
Type
Operating
Range
SY100EL15LZC
Z16-2
Z16-2
Commercial
Commercial
SY100EL15LZCTR
3
ClockWorks™
Micrel
SY100EL15L
16 LEAD PLASTIC SOIC .150" WIDE (Z16-2)
MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA
TEL + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.synergysemi.com http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
© 1999 Micrel Incorporated
4
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