DSC2021FE1-T [MICREL]
Low-Jitter Configurable Dual LVPECL-CMOS Oscillator;
| 型号： | DSC2021FE1-T |
| 厂家： | 
MICREL SEMICONDUCTOR |
| 描述： | Low-Jitter Configurable Dual LVPECL-CMOS Oscillator |
| 文件： | 总6页 (文件大小：539K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DSC2021
Low-Jitter Configurable Dual LVPECL-CMOS Oscillator
General Description
Features
The DSC2021 series of high performance
dual output oscillators utilize a proven silicon
MEMS technology to provide excellent jitter
and stability while incorporating additional
device functionality. The two outputs are
controlled by separate supply voltages to
allow for independent voltage level control.
The frequencies of the outputs can be
identical or independently derived from a
Low RMS Phase Jitter: <1 ps (typ)
High Stability: ±10, ±25, ±50 ppm
Wide Temperature Range
o Industrial: -40° to 85° C
o Ext. commercial: -20° to 70° C
High Supply Noise Rejection: -50 dBc
Two Independent Outputs
o LVPECL and CMOS
common PLL frequency source.
DSC2021 has provision for up to eight user-
defined pre-programmed, pin-selectable
output frequency combinations. The
The
Pin-Selectable Configurations
o 3-bit Output Drive Strength (CMOS)
o 3-bit Output Frequency Combinations
DSC2021 is also equipped with independent
pin-selectable output drive strengths for the
CMOS output to reduce EMI and noise.
Short Lead Times: 2 Weeks
Wide Frequency Range
o LVPECL Output: 2.3 to 460 MHz
o CMOS Output: 2.3 to 170 MHz
DSC2021 is packaged in a 14-pin 3.2x2.5
mm
QFN
package
and
available
in
temperature grades from Ext. Commercial to
Industrial.
Miniature Footprint of 3.2x2.5mm
Excellent Shock & Vibration Immunity
o Qualified to MIL-STD-883
High Reliability
o 20x better MTF than quartz oscillators
Block Diagram
Supply Range of 2.25 to 3.6 V
Lead Free & RoHS Compliant
Applications
Storage Area Networks
o SATA, SAS, Fibre Channel
Passive Optical Networks
o EPON, 10G-EPON, GPON, 10G-PON
Ethernet
o 1G, 10GBASE-T/KR/LR/SR, and FCoE
HD/SD/SDI Video & Surveillance
PCI Express
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DSC2021 Page 1 MK-Q-B-P-D-12042604-2
Low-Jitter Configurable Dual LVPECL-CMOS Oscillator
DSC2021
Pin Description
Pin
Type
I
NA
Pin No. Pin Name
Description
Enables outputs when high and disables (tri-state) them when low
Leave unconnected or grounded
1
2
Enable
NC
3
4
OS0
GND
I
Least significant bit for output drive strength selection for CMOS
Ground
Power
5
6
FS0
FS1
I
I
Least significant bit for frequency selection
Middle bit for frequency selection
7
8
9
10
11
12
13
14
FS2
I
O
O
I
O
Most significant bit for frequency selection
Positive LVPECL Output 1
Negative LVPECL Output 1
Middle bit for output drive strength selection for CMOS
CMOS output
Power Supply 2 for CMOS Output
Output1+
Output1-
OS1
Output 2
VDD2
VDD
Power
Power
Power Supply
OS2
I
Most significant bit for output drive strength selection for CMOS
Operational Description
The DSC2021 is a dual output LVPECL-CMOS
oscillator consisting of a MEMS resonator and
a support PLL IC. The two outputs, CMOS and
LVPECL, are generated through independent
8-bit programmable dividers from the output
of the internal PLL. Two constraints are
imposed on the output frequencies: 1) f2=M x
f1/N, where M and N are even integers
between 4 and 254, 2) 1.2GHz < N x f2 <
1.7GHz.
When Enable (pin 1) is floated or connected to
VDD, the DSC2021 is in operational mode.
Driving Enable to ground will tri-state both
output drivers (hi-impedance mode).
The DSC2021 has programmable output drive
strength for CMOS output. Using three control
pins (OS0-OS2), the drive strength for CMOS
output (output 2) can be adjusted to match
circuit board impedances to reduce power
supply noise, overshoot/undershoot and EMI.
Table 1 displays typical rise / fall times for the
output with a 15pf load capacitance as a
function of these control pins at VDD=3.3V
and room temperature.
The actual frequencies output by the DSC2021
are controlled by an internal pre-programmed
memory (OTP).
coefficients required by the PLL for up to eight
different frequency combinations. Three
control pins (FS0 – FS2) select the output
frequency combination. Discera supports
This memory stores all
Table 1. Rise/Fall times for drive strengths
Output Drive Strength Bits
customer defined versions of the DSC2021.
Standard frequency options are described in in
the following sections.
[OS2, OS1, OS0] - Default [111]
000 001 010 011 100 101 110 111
tr (ns) 2.1 1.7 1.6 1.4 1.3 1.3 1.2 1.1
The DSC2021 provides control of the output
voltage levels of the CMOS output. VDD2 (pin
12) sets the high voltage level of Output 2 and
must be equal to or less than VDD at all times
to insure proper operation. VDD2 can be as
low as 1.65V.
tf (ns) 2.5 2.4 2.4
2
1.8 1.6 1.3 1.3
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DSC2021 Page 2 MK-Q-B-P-D-12042604-2
Low-Jitter Configurable Dual LVPECL-CMOS Oscillator
DSC2021
Output Clock Frequencies
Table 2 lists the standard frequency configurations and the associated ordering information to be
used in conjunction with the ordering code above. Customer defined combinations are available.
Table 2. Pre-programmed pin-selectable output frequency combinations
Freq Select Bits [FS2, FS1, FS0] – Default is [111]
Ordering
Info
Freq
(MHz)
000
150
75
001
150
50
010
125
50
011
100
50
100
150
25
101
156.25
25
110
125
25
111
100
25
fOUT1
fOUT2
fOUT1
fOUT2
I0001
I000X
Contact factory for additional configurations.
Frequency select bit are weakly tied high so if left unconnected the default setting will be [111] and
the device will output the associated frequency highlighted in Bold.
Absolute Maximum Ratings
Ordering Code
Item
Min
Max
Unit Condition
Temp Range
E: -20 to 70
I: -40 to 85
Packing
T: Tape & Reel
: Tube
Supply Voltage
Input Voltage
Junction Temp
Storage Temp
Soldering Temp
-0.3
+4.0
V
V
-0.3 VDD+0.3
-
-55
-
+150
+150
+260
°C
°C
DSC2021 F I 2
xxxxx
T
°C
V
40sec max.
Package
Stability
1: ±50ppm
2: ±25ppm
5: ±10ppm
Freq (MHz)
See Freq. table
ESD
HBM
MM
-
F: 3.2x2.5mm
4000
400
CDM
1500
Note: 1000+ years of data retention on internal memory
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DSC2021 Page 3 MK-Q-B-P-D-12042604-2
Low-Jitter Configurable Dual LVPECL-CMOS Oscillator
DSC2021
Specifications (Unless specified otherwise: T=25° C, max CMOS drive strength)
Parameter
Supply Voltage1
Supply Current
Condition
Min.
2.25
Typ.
Max.
3.6
23
Unit
V
mA
VDD
IDD
EN pin low – outputs are disabled
21
EN pin high – outputs are enabled
LVPECL: RL=50Ω, FO1=125 MHz
CMOS: CL=15pF, FO2=75 MHz
Supply Current2
IDD
62
mA
Includes frequency variations due
to initial tolerance, temp. and
power supply voltage
±10
±25
±50
Frequency Stability
Δf
ppm
Aging
Startup Time3
Δf
tSU
1 year @25°C
T=25°C
±5
5
ppm
ms
Input Logic Levels
Input logic high
Input logic low
VIH
VIL
0.75xVDD
-
-
V
0.25xVDD
Output Disable Time4
Output Enable Time
Pull-Up Resistor2
tDA
5
ns
ns
tEN
20
Pull-up exists on all digital IO
40
kΩ
LVPECL Output
Output Logic Levels
Output logic high
Output logic low
VOH
VOL
RL=50Ω
VDD-1.08
-
-
V
VDD-1.55
Pk to Pk Output Swing
Output Transition time4
Rise Time
Single-Ended
800
250
mV
ps
20% to 80%
RL=50Ω, CL= 0pF (to GND)
tR
tF
Fall Time
Frequency
f0
Single Frequency
Differential
2.3
48
460
52
MHz
%
Output Duty Cycle
Period Jitter5
SYM
JPER
FO1=125 MHz
2.5
psRMS
200kHz to 20MHz @156.25MHz
100kHz to 20MHz @156.25MHz
12kHz to 20MHz @156.25MHz
0.25
0.38
1.7
Integrated Phase Noise
JCC
psRMS
2
CMOS Output
Output Logic Levels
Output logic high
Output logic low
VOH
VOL
I=±6mA
0.9xVDD
-
-
V
0.1xVDD
Output Transition time4
Rise Time
20% to 80%
CL=15pf
tR
tF
f0
1.1
1.3
2
2
170
ns
Fall Time
Frequency
Output Duty Cycle
Commercial/Industrial temp range
2.3
45
MHz
%
SYM
55
Period Jitter5
JPER
FO2=125 MHz
3
psRMS
200kHz to 20MHz @ 125MHz
100kHz to 20MHz @ 125MHz
12kHz to 20MHz @ 125MHz
0.3
0.38
1.7
Integrated Phase Noise
JCC
psRMS
2
Notes:
1.
Pin 4 VDD should be filtered with 0.01uf capacitor.
2.
3.
4.
5.
Output is enabled if Enable pad is floated or not connected.
tsu is time to stable output frequency after VDD is applied and outputs are enabled.
Output Waveform and Test Circuit figures below define the parameters.
Period Jitter includes crosstalk from adjacent output.
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DSC2021 Page 4 MK-Q-B-P-D-12042604-2
Low-Jitter Configurable Dual LVPECL-CMOS Oscillator
DSC2021
Nominal Performance Parameters (Unless specified otherwise: T=25° C, VDD=3.3 V)
2.5
2.0
1.5
1.0
0.5
0.0
2.5
2.0
1.5
1.0
0.5
0.0
25MHz-CMOS
50MHz-CMOS
106MHz-CMOS
125MHz-CMOS
156MHz-LVPECL
212MHz-LVPECL
320MHz-LVPECL
410MHz-LVPECL
0
200
400
600
800
1000
0
200
400
600
800
1000
Low-end of integration BW: x kHz to 20 MHz
Low-end of integration BW: x kHz to 20 MHz
CMOS Phase jitter (integrated phase noise)
LVPECL Phase jitter (integrated phase noise)
Output Waveform: LVPECL
tR
tF
Output
Output
80%
50%
20%
830 mv
tEN
1/fo
tDA
VIH
Enable
VIL
Output Waveform: CMOS
tR
tF
VOH
Output
VOL
tEN
1/fo
tDA
VIH
Enable
VIL
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DSC2021 Page 5 MK-Q-B-P-D-12042604-2
Low-Jitter Configurable Dual LVPECL-CMOS Oscillator
DSC2021
Solder Reflow Profile
20-40
Sec
260°C
MSL 1 @ 260°C refer to JSTD-020C
Ramp-Up Rate (200°C to Peak Temp) 3°C/Sec Max.
217°C
200°C
60-150
Sec
Preheat Time 150°C to 200°C
Time maintained above 217°C
Peak Temperature
Time within 5°C of actual Peak
Ramp-Down Rate
60-180 Sec
60-150 Sec
255-260°C
20-40 Sec
6°C/Sec Max.
8 min Max.
Reflow
60-180
Sec
150°C
Cool
Pre heat
25°C
Time 25°C to Peak Temperature
Time
8 min max
Package Dimensions
3.2 x 2.5 mm 14 Lead Plastic Package
Disclaimer:
Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This information
is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry, specifications and
descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted
by this document. Except as provided in Micrel’s terms and conditions of sale for such products, Micrel assumes no liability whatsoever, and Micrel disclaims
any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties relating to fitness for a particular purpose,
merchantability, or infringement of any patent, copyright or other intellectual property right.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the
body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or
sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any
damages resulting from such use or sale.
MICREL, Inc.
Phone: +1 (408) 944-0800
●
●
2180 Fortune Drive,
Fax: +1 (408) 474-1000
San Jose, California
95131
●
●
USA
●
Email: hbwhelp@micrel.com
www.micrel.com
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DSC2021 Page 6 MK-Q-B-P-D-12042604-2
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