WPS512K8C-20RJMGA [MERCURY]

Standard SRAM, 512KX8, 20ns, CMOS, PDSO36, ROHS COMPLIANT, PLASTIC, SOJ-36;
WPS512K8C-20RJMGA
型号: WPS512K8C-20RJMGA
厂家: MERCURY UNITED ELECTRONICS INC    MERCURY UNITED ELECTRONICS INC
描述:

Standard SRAM, 512KX8, 20ns, CMOS, PDSO36, ROHS COMPLIANT, PLASTIC, SOJ-36

静态存储器 光电二极管
文件: 总9页 (文件大小:837K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
EDI88512CA-XMXG  
WPS512K8X-XRJXG  
512Kx8 Plastic Monolithic SRAM CMOS  
WEDC's ruggedized plastic 512Kx8 SRAM that allows the user to  
capitalize on the cost advantage of using a plastic component while  
not sacricing all of the reliability available in a full military device.  
FEATURES  
 512Kx8 bit CMOS Static  
 Random Access Memory  
Extended temperature testing is performed with the test patterns  
developed for use on WEDC’s fully compliant 512Kx8 SRAMs.  
WEDC fully characterizes devices to determine the proper test  
patterns for testing at temperature extremes. This is critical because  
the operating characteristics of device change when it is operated  
beyond the commercial guarantee a device that operates reliably  
in the eld at temperature extremes. Users of WEDC’s ruggedized  
plastic benet from WEDC’s extensive experience in characterizing  
SRAMs for use in military systems.  
• Access Times of 17, 20, 25ns  
• Data Retention Function (LPA version)  
• Extended Temperature Testing  
• Data Retention Functionality Testing  
 36 lead JEDEC Approved Revolutionary Pinout  
• Plastic SOJ (Package 319)  
 Single +5V (±10%) Supply Operation  
 RoHS compliant  
WEDC ensures Low Power devices will retain data in Data  
Retention mode by characterizing the devices to determine the  
appropriate test conditions. This is crucial for systems operating  
at -40°C or below and using dense memories such as 512Kx8s.  
WEDC’s ruggedized plastic SOJ is footprint compatible with  
WEDC’s full military ceramic 36 pin SOJ.  
FIGURE 1 – PIN CONFIGURATION  
TOP VIEW  
PIN Description  
I/O0-7  
A0-18  
WE#  
CS#  
OE#  
VCC  
Data Inputs/Outputs  
Address Inputs  
Write Enables  
Chip Selects  
A0  
A1  
1
2
3
4
5
6
7
8
9
36 NC  
35 A18  
34 A17  
33 A16  
32 A15  
31 OE#  
30 I/O7  
29 I/O6  
28 VSS  
27 VCC  
26 I/O5  
25 I/O4  
24 A14  
23 A13  
22 A12  
21 A11  
20 A10  
19 NC  
Output Enable  
Power (+5V ±10%)  
Ground  
A2  
A3  
VSS  
A4  
NC  
Not Connected  
CS#  
I/O0  
I/O1  
VCC  
BLOCK DIAGRAM  
36pin  
VSS 10  
I/O2 11  
I/O3 12  
WE# 13  
A5 14  
Revolutionary  
Memory Array  
A6 15  
A7 16  
Address  
Buffer  
Address  
Decoder  
I/O  
Circuits  
AØ-18  
I/OØ-7  
A8 17  
A9 18  
WE#  
CS#  
OE#  
Microsemi Corporation reserves the right to change products or specications without notice.  
May 2014 © 2014 Microsemi Corporation. All rights reserved.  
Rev. 11  
1
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp  
EDI88512CA-XMXG  
WPS512K8X-XRJXG  
ABSOLUTE MAXIMUM RATINGS  
TRUTH TABLE  
Mode  
Standby  
Output  
High Z  
Power  
Icc2, Icc3  
Icc1  
Parameter  
Unit  
OE#  
X
CS#  
H
WE#  
X
Voltage on any pin relative to Vss  
Operating Temperature TA (Ambient)  
Commercial  
-0.5 to 7.0  
V
Output Deselect  
Read  
High Z  
H
L
H
0 to +70  
-40 to +85  
-55 to +125  
-65 to +150  
1.5  
°C  
°C  
°C  
°C  
W
Data Out  
Data In  
Icc1  
L
L
H
Industrial  
Write  
Icc1  
X
L
L
Military  
Storage Temperature, Plastic  
Power Dissipation  
Output Current  
20  
mA  
°C  
RECOMMENDED OPERATING CONDITIONS  
Junction Temperature, TJ  
175  
Parameter  
Symbol  
VCC  
Min  
4.5  
0
Typ  
5.0  
0
Max  
5.5  
Unit  
V
NOTE:  
Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.  
This is a stress rating only and functional operation of the device at these or any other conditions greater than  
those indicated in the operational sections of this specication is not implied. Exposure to absolute maximum rating  
conditions for extended periods may affect device reliability.  
Supply Voltage  
Supply Voltage  
Input High Voltage  
Input Low Voltage  
VSS  
0
V
VIH  
2.0  
-0.5  
VCC + 0.5  
+0.8  
V
VIL  
V
CAPACITANCE  
TA = +25°C  
Parameter  
Address Lines  
Data Lines  
Symbol  
CI  
Condition  
Max Unit  
VIN = Vcc or Vss, f = 1.0MHz  
VIN = Vcc or Vss, f = 1.0MHz  
8
8
pF  
pF  
CO  
These parameters are sampled, not 100% tested.  
DC CHARACTERISTICS  
VCC = 5V, VSS = 0V, -55°C TA +125°C  
Parameter  
Symbol  
ILI  
Conditions  
Min  
Max  
Units  
Input Leakage Current  
Output Leakage Current  
Operating Supply Current  
Standby Current  
VCC = 5.5, VIN = VSS to VCC  
10  
10  
μA  
μA  
mA  
mA  
V
ILO  
CS# = VIL, OE# = VIH, VOUT = VSS to VCC  
CS# = VIL, OE# = VIH, f = 5MHz, VCC = 5.5  
CS# = VIH, OE# = VIH, f = 5MHz, VCC = 5.5  
IOH = -4.0mA, VCC = 4.5  
ICC  
180  
15  
ISB  
Output High Volltage  
Output Low Voltage  
VOH  
VOL  
2.4  
IOL = 8.0mA, VCC = 4.5  
0.4  
V
NOTE: DC test conditions: VIL = 0.3V, VIH = VCC -0.3V  
AC TEST CONDITIONS  
Figure 1  
Figure 2  
Input Pulse Levels  
Input Rise and Fall Times  
VSS to 3.0V  
5ns  
Vcc  
Vcc  
Input and Output Timing Levels  
Output Load  
1.5V  
480Ω  
480Ω  
5pF  
Figure 1  
NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF (Figure 2)  
Q
Q
30pF  
255Ω  
255Ω  
Microsemi Corporation reserves the right to change products or specications without notice.  
May 2014 © 2014 Microsemi Corporation. All rights reserved.  
Rev. 11  
2
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp  
EDI88512CA-XMXG  
WPS512K8X-XRJXG  
AC CHARACTERISTICS – READ CYCLE  
VCC = 5.0V, VSS = 0V, 0°C TA +70°C  
Symbol  
17ns  
20ns  
25ns  
Parameter  
JEDEC  
Alt.  
tRC  
Min  
Max  
Min  
Max  
Min  
Max  
Units  
ns  
Read Cycle Time  
tAVAV  
17  
20  
25  
Address Access Time  
tAVQV  
tELQV  
tELQX  
tEHQZ  
tAVQX  
tGLQV  
tGLQX  
tGHQZ  
tAA  
17  
17  
20  
20  
25  
25  
ns  
Chip Enable Access Time  
tACS  
tCLZ  
tCHZ  
tOH  
ns  
Chip Enable to Output in Low Z (1)  
Chip Disable to Output in High Z (1)  
Output Hold from Address Change  
Output Enable to Output Valid  
Output Enable to Output in Low Z (1)  
Output Disable to Output in High Z(1)  
1. This parameter is guaranteed by design but not tested.  
3
0
0
3
0
0
3
0
0
ns  
7
8
7
8
10  
8
10  
12  
10  
ns  
ns  
tOE  
ns  
tOLZ  
tOHZ  
0
0
0
0
0
0
ns  
ns  
AC CHARACTERISTICS – WRITE CYCLE  
VCC = 5.0V, VSS = 0V, 0°C TA +70°C  
Symbol  
17ns  
20ns  
25ns  
Parameter  
Write Cycle Time  
JEDEC  
Alt.  
Min  
Max  
Min  
Max  
Min  
Max  
Units  
tAVAV  
tWC  
17  
20  
25  
ns  
Chip Enable to End of Write  
tELWH  
tELEH  
tCW  
tCW  
14  
14  
15  
15  
17  
17  
ns  
ns  
Address Setup Time  
Address Valid to End of Write  
Write Pulse Width  
tAVWL  
tAVEL  
tAS  
tAS  
0
0
0
0
0
0
ns  
ns  
tAVWH  
tAVEH  
tAW  
tAW  
14  
14  
15  
15  
17  
17  
ns  
ns  
tWLWH  
tWLEH  
tWP  
tWP  
14  
14  
15  
15  
17  
17  
ns  
ns  
Write Recovery Time  
Data Hold Time  
tWHAX  
tEHAX  
tWR  
tWR  
0
0
0
0
0
0
ns  
ns  
tWHDX  
tEHDX  
tDH  
tDH  
0
0
0
0
0
0
ns  
ns  
Write to Output in High Z (1)  
Data to Write Time  
tWLQZ  
tWHZ  
0
8
0
8
0
10  
ns  
tDVWH  
tDVEH  
tDW  
tDW  
8
8
10  
10  
12  
12  
ns  
ns  
Output Active from End of Write (1)  
tWHQX  
tWLZ  
0
0
0
ns  
1. This parameter is guaranteed by design but not tested.  
Microsemi Corporation reserves the right to change products or specications without notice.  
May 2014 © 2014 Microsemi Corporation. All rights reserved.  
Rev. 11  
3
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp  
EDI88512CA-XMXG  
WPS512K8X-XRJXG  
FIGURE 2 – TIMING WAVEFORM — READ CYCLE  
tAVAV  
ADDRESS  
tAVAV  
tAVQV  
ADDRESS  
DATA I/O  
ADDRESS 1  
ADDRESS 2  
CS#  
tEHQZ  
tELQV  
tELQX  
tAVQV  
tAVQX  
OE#  
DATA 1  
DATA 2  
tGLQV  
tGLQX  
tGHQZ  
DATA OUT  
READ CYCLE 1 (WE# HIGH; OE#, CS# LOW)  
READ CYCLE 2 (WE# HIGH)  
FIGURE 3 – WRITE CYCLE — WE# CONTROLLED  
tAVAV  
ADDRESS  
tAVWH  
tWHAX  
tELWH  
CS#  
tAVWL  
tWLWH  
WE#  
tDVWH  
tWHDX  
DATA IN  
DATA VALID  
tWLQZ  
tWHQX  
HIGH Z  
DATA OUT  
WRITE CYCLE 1, WE# CONTROLLED  
FIGURE 4 – WRITE CYCLE — CS# CONTROLLED  
tAVAV  
ADDRESS  
tAVEH  
tELEH  
tEHAX  
CS#  
tAVEL  
tWLEH  
WE#  
tDVEH  
tEHDX  
DATA IN  
DATA VALID  
HIGH Z  
DATA OUT  
WRITE CYCLE 2, CS# CONTROLLED  
Microsemi Corporation reserves the right to change products or specications without notice.  
May 2014 © 2014 Microsemi Corporation. All rights reserved.  
Rev. 11  
4
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp  
EDI88512CA-XMXG  
WPS512K8X-XRJXG  
DATA RETENTION CHARACTERISTICS (EDI88512LPA ONLY)  
-55°C TA +125°C  
Characteristic  
Sym  
Conditions  
Min  
Typ  
Max  
Units  
Low Power Version only  
Data Retention Voltage  
Data Retention Quiescent Current  
VDD  
ICCDR  
VDD = 2.0V  
CS# VDD -0.2V  
2
15  
V
mA  
Chip Disable to Data Retention Time  
Operation Recovery Time  
TCDR  
TR  
VIN VDD -0.2V  
or VIN 0.2V  
0
ns  
ns  
TAVAV  
FIGURE 5 – DATA RETENTION — CS# CONTROLLED  
Data Retention Mode  
4.5V  
4.5V  
Vcc  
VDD  
tCDR  
tR  
CS#  
CS# = VDD -0.2V  
DATA RETENTION, CS# CONTROLLED  
Microsemi Corporation reserves the right to change products or specications without notice.  
May 2014 © 2014 Microsemi Corporation. All rights reserved.  
Rev. 11  
5
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp  
EDI88512CA-XMXG  
WPS512K8X-XRJXG  
FIGURE 6 – NORMALIZED OPERATING GRAPHS  
rite ulse idth vs. emp.  
CC1 (20ns) vs emp  
14  
13  
12  
11  
10  
220  
210  
200  
1
1
0
0
7
6
170  
160  
-55  
25  
125  
-55  
25  
125  
emp. (C)  
emp. (C)  
A
vs. emp  
CC3vs. emp  
10  
1
22  
20  
1
1 0  
16  
14  
12  
0.1  
0.01  
-55  
25  
emp. (C)  
125  
-55  
25  
emp. (C)  
125  
CC R vs. emp  
10  
1
ormali ed curves are o ered  
as a service to our customers.  
hey are not to e construed  
as a guarantee o operating  
characterics.  
0.1  
Characteristics o actual  
devices will vary.  
0.01  
0.001  
-55  
25  
125  
emp. (C)  
R
2
R
3
Microsemi Corporation reserves the right to change products or specications without notice.  
May 2014 © 2014 Microsemi Corporation. All rights reserved.  
Rev. 11  
6
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp  
EDI88512CA-XMXG  
WPS512K8X-XRJXG  
PACKAGE 319: 36 LEAD, PLASTIC SMALL OUTLINE J-LEAD (SOJ)  
0.920  
0.930  
0.395  
0.405  
0.026  
0.032  
Pin 1 Indicator  
0.360 0.435  
0.380 0.445  
0.027  
min.  
0.148  
max.  
0.375  
TYP.  
0.050  
TYP.  
0.015  
0.021  
ALL DIMENSIONS ARE IN INCHES  
Microsemi Corporation reserves the right to change products or specications without notice.  
May 2014 © 2014 Microsemi Corporation. All rights reserved.  
Rev. 11  
7
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp  
EDI88512CA-XMXG  
WPS512K8X-XRJXG  
ORDERING INFORMATION  
EDI 8 8512 CA - X X X G  
MICROSEMI CORPORATION:  
SRAM:  
ORGANIZATION, 512Kx8:  
TECHNOLOGY:  
CA  
= CMOS Standard Power  
LPA = Low Power  
ACCESS TIME (ns):  
PACKAGE TYPE:  
M
RJ  
=
=
36 lead Plastic SOJ  
Relvoutionary  
DEVICE GRADE:  
Military Grade*  
M = Military Screened -55°C to +125°C  
B
=
I
C
=
=
Industrial  
Commercial  
-40°C to +85°C  
0°C to +70°C  
RoHS COMPLIANT:  
*This product is processed the same as the 5962-XXXXXMXX product but all test and mechanical requirements are per the Microsemi data sheet.  
ORDERING INFORMATION  
W P S 512K 8 X X - XXX RJ X G A  
MICROSEMI CORPORATION:  
PLASTIC PLUS®:  
SRAM:  
ORGANIZATION, 512K x 8:  
POWER:  
Blank = Standard Power  
L = Low Power  
IMPROVEMENT MARK:  
B
T
C
=
=
=
Burn-in  
Temperature Cycling  
Burn-in and Temperature Cycle  
ACCESS TIME (ns):  
PACKAGE:  
RJ = Revolutionary  
DEVICE GRADE:  
M = Military Temperature  
-55°C to +125°C  
I
= Industrial Temperature -40°C to +85°C  
RoHS COMPLIANT:  
SOLDER DIPPED:  
Microsemi Corporation reserves the right to change products or specications without notice.  
May 2014 © 2014 Microsemi Corporation. All rights reserved.  
Rev. 11  
8
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp  
EDI88512CA-XMXG  
WPS512K8X-XRJXG  
Document Title  
512K x 8 Plastic Monolithic SRAM CMOS  
Revision History  
Rev #  
History  
Release Date Status  
Rev 7  
Added RoHS compliance  
November 2008  
Final  
Rev 8  
Changes (Pg. 2, 8)  
February 2009  
Final  
8.1 Add solder dipped to package options  
8.2 Change CI to 8pF  
8.3 Change VIH to 2.0V and VIL to -0.5V  
Rev 9  
Changes (Pg. 9)  
March 2009  
February 2011  
May 2014  
Final  
Final  
Final  
9.1 Change document title: 512K x 8 Plastic Monolithic SRAM CMOS  
Rev 10  
Rev 11  
Changes (Pg. 1-9)  
10.1 Change document layout from White Electronic Designs to Microsemi  
Changes (Pg. 8)  
11.1 Changed EDI88512CA-XMXG Device Grade "B" description from  
"MIL-STD-883 Compliant" to "Military Grade*."  
Microsemi Corporation reserves the right to change products or specications without notice.  
May 2014 © 2014 Microsemi Corporation. All rights reserved.  
Rev. 11  
9
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp  

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