WE512K8-200CMA [MERCURY]
EEPROM Module,;
| 型号： | WE512K8-200CMA |
| 厂家： | 
MERCURY UNITED ELECTRONICS INC |
| 描述： | EEPROM Module, 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总14页 (文件大小：1145K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
512Kx8 CMOS EEPROM
SMD 5962-93091
WE512K / 256K / 128K8-XCX
512Kx8 BIT CMOS EEPROM MODULE
FEATURES
Read Access Times of 150, 200, 250, 300ns
Automatic Page Write Operation
JEDEC Standard 32 Pin, Hermetic Ceramic DIP (Package
• Internal Address and Data Latches for
• 512 Bytes, 1 to 128 Bytes/Row, Four Pages
Page Write Cycle Time 10mS Max.
Data Polling for End of Write Detection
Hardware and Software Data Protection
TTL Compatible Inputs and Outputs
300)
Commercial, Industrial and Military Temperature Ranges
MIL-STD-883 Compliant Devices Available
Write Endurance 10,000 Cycles
Data Retention at 25°C, 10 Years
Low Power CMOS Operation:
• 3mA Standby Typical/100mA Operating Maximum
FIGURE 1 – PIN CONFIGURATION
TOP VIEW
PIN DESCRIPTION
A0-18
I/O0-7
CS#
OE#
WE#
VCC
Address Inputs
Data Input/Output
Chip Select
Output Enable
Write Enable
+5.0V Power
Ground
A18
A16
A15
A12
A7
1
2
3
4
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
WE#
A17
A14
A13
A8
VSS
BLOCK DIAGRAM
5
A6
6
A0-16
I/O0-7
A5
7
A9
A4
A3
A2
A1
8
9
A11
OE#
A10
CS#
I/O7
I/O6
I/O5
I/O4
I/O3
WE#
OE#
10
11
12
13
14
15
16
A0
128K x 8
128K x 8
128K x 8
128K x 8
I/O0
I/O1
I/O2
VSS
A17
A18
Decoder
CS#
1
Mercury Corp. - Memory and Storage Solutions • (602) 437-1520 • www.mrcy.com
4312.08E-0718-ss-WE512K_256K_128K8-XCX
WE512K / 256K / 128K8-XCX
256Kx8 BIT CMOS EEPROM Module
FEATURES
Read Access Times of 150, 200ns
Automatic Page Write Operation
JEDEC Standard 32 Pin, Hermetic Ceramic DIP (Package
• Internal Address and Data Latches for
• 512 Bytes, 1 to 64 Bytes/Row, Eight Pages
Page Write Cycle Time 10mS Max.
Data Polling for End of Write Detection
Hardware and Software Data Protection
TTL Compatible Inputs and Outputs
302)
Commercial, Industrial and Military Temperature Ranges
MIL-STD-883 Compliant Devices Available
Write Endurance 10,000 Cycles
Data Retention at 25°C, 10 Years
Low Power CMOS Operation:
• 2mA Standby Typical/90mA Operating Maximum
FIGURE 2 – PIN CONFIGURATION
TOP VIEW
PIN DESCRIPTION
A0-18
I/O0-7
CS#
OE#
WE#
VCC
Address Inputs
Data Input/Output
Chip Select
Output Enable
Write Enable
+5.0V Power
Ground
NC
A16
A15
A12
A7
1
2
3
4
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
WE#
A17
A14
A13
A8
VSS
BLOCK DIAGRAM
5
A6
6
A0-14
I/O0-7
A5
7
A9
A4
A3
A2
A1
8
9
A11
OE#
A10
CS#
I/O7
I/O6
I/O5
I/O4
I/O3
WE#
OE#
10
11
12
13
14
15
16
8
1
2
A0
32K x 8
32K x 8
32K x 8
I/O0
I/O1
I/O2
VSS
A15
A16
A17
Decoder
CS#
2
4312.08E-0718-ss-WE512K_256K_128K8-XCX
Mercury Corp. - Memory and Storage Solutions • (602) 437-1520 • www.mrcy.com
WE512K / 256K / 128K8-XCX
128Kx8 BIT CMOS EEPROM Module
FEATURES
Read Access Times of 150, 200ns
Automatic Page Write Operation
JEDEC Standard 32 Pin, Hermetic Ceramic DIP (Package
• Internal Address and Data Latches for
• 256 Bytes, 1 to 64 Bytes/Row, Four Pages
Page Write Cycle Time 10mS Max.
Data Polling for End of Write Detection
Hardware and Software Data Protection
TTL Compatible Inputs and Outputs
300)
Commercial, Industrial and Military Temperature Ranges
MIL-STD-883 Compliant Devices Available
Write Endurance 10,000 Cycles
Data Retention at 25°C, 10 Years
Low Power CMOS Operation:
• 1mA Standby Typical/70mA Operating
FIGURE 3 – PIN CONFIGURATION
TOP VIEW
PIN DESCRIPTION
A0-18
I/O0-7
CS#
OE#
WE#
VCC
Address Inputs
Data Input/Output
Chip Select
Output Enable
Write Enable
+5.0V Power
Ground
NC
A16
A15
A12
A7
1
2
3
4
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
WE#
NC
A14
A13
A8
VSS
BLOCK DIAGRAM
5
A6
6
A0-14
I/O0-7
A5
7
A9
A4
A3
A2
A1
8
9
A11
OE#
A10
CS#
I/O7
I/O6
I/O5
I/O4
I/O3
WE#
OE#
10
11
12
13
14
15
16
A0
32K x 8
32K x 8
32K x 8
32K x 8
I/O0
I/O1
I/O2
VSS
A15
A16
Decoder
CS#
3
4312.08E-0718-ss-WE512K_256K_128K8-XCX
Mercury Corp. - Memory and Storage Solutions • (602) 437-1520 • www.mrcy.com
WE512K / 256K / 128K8-XCX
ABSOLUTE MAXIMUM RATINGS
TRUTH TABLE
Parameter
Operating Temperature
Storage Temperature
Signal Voltage Any Pin
Voltage on OE# and A9
Symbol
TA
TSTG
VG
Unit
°C
°C
V
V
CS#
H
OE#
X
WE#
X
Mode
Standby
Read
Data I/O
High Z
-55 to +125
-65 to +150
-0.6 to + 6.25
-0.6 to +13.5
28
L
L
H
Data Out
L
H
L
Write
Data In
X
H
X
Out Disable
Write
High Z/Data Out
Thermal Resistance junction to case
Lead Temperature (soldering -10 secs)
JC
°C/W
°C
X
X
H
+300
X
L
X
Inhibit
NOTE:
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
CAPACITANCE
TA = +25°C
512Kx8 256Kx8 128Kx8
RECOMMENDED OPERATING CONDITIONS
Parameter
Sym
Condition
Unit
Max
Max
Max
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temp. (Mil.)
Operating Temp. (Ind.)
Symbol
VCC
VIH
VIL
TA
Min
4.5
2.0
-0.3
-55
-40
Max
5.5
VCC + 0.3
+0.8
+125
+85
Unit
V
V
V
°C
°C
Input Capacitance
CIN
VIN = 0V, f = 1MHz
45
80
45
pF
pF
Output Capacitance COUT VI/O = 0V, f = 1MHz
This parameter is guaranteed by design but not tested.
60
80
60
TA
DC CHARACTERISTICS
VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C
512K x 8
Typ
256K x 8
Typ
128K x 8
Typ
Parameter
Symbol
Conditions
Unit
Min
Max Min
10
10
100
8
0.45
2.4
Max Min
10
10
90
6
Max
10
10
90
4
Input Leakage Current
Output Leakage Current
Dynamic Supply Current
Standby Current
Output Low Voltage
Output High Voltage
ILI
ILO
ICC
ISB
VOL
VOH
VCC = 5.5, VIN = GND to VCC
μA
μA
mA
mA
V
CS# = VIH, OE# = VIH, Vout = GND to VCC
CS# = VIL, OE# = VIH, f = 5MHz, VCC = 5.5
CS# = VIH, OE# = VIH, f = 5MHz, VCC = 5.5
IOL = 2.1mA, VCC = 4.5V
80
3
60
2
50
1
0.45
2.4
0.45
IOH = -400μA, VCC = 4.5V
2.4
V
NOTE: DC test conditions: Vih = Vcc -0.3V, Vil = 0.3V
FIGURE 4 – AC TEST CIRCUIT
AC TEST CONDITIONS
Parameter
Typ
VIL = 0, VIH = 3.0
Unit
V
Input Pulse Levels
Input Rise and Fall
5
ns
V
Input and Output Reference Level
Output Timing Reference Level
Notes: VZ is programmable from -2V to +7V.
1.5
1.5
V
I
OL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75Ω.
VZ is typically the midpoint of VOH and VOL
.
IOL & IOH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
4
4312.08E-0718-ss-WE512K_256K_128K8-XCX
Mercury Corp. - Memory and Storage Solutions • (602) 437-1520 • www.mrcy.com
WE512K / 256K / 128K8-XCX
READ
Figure 5 shows Read cycle waveforms. A read cycle begins with
selection address, chip select and output enable. Chip select is
accomplished by placing the CS# line low. Output enable is done
by placing the OE# line low. The memory places the selected data
byte on I/O0 through I/O7 after the access time. The output of the
memory is placed in a high impedance state shortly after either the
OE# line or CS# line is returned to a high level.
FIGURE 5 – READ WAVEFORMS
ADDRESS
CS#
OE#
OUTPUT
NOTE:
OE# may be delayed up to tACS-tOE
after the falling edge of CS# without
impact on tOE or by tACC-tOE after an
address change without impact on tACC.
AC READ CHARACTERISTICS (See Figure 5)
FOR WE512K8-XCX
VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C
-150
-200
-250
-300
Parameter
Symbol
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Read Cycle Time
trc
tacc
tacs
toh
toe
tdf
150
200
250
300
ns
ns
ns
ns
ns
ns
Address Access Time
Chip Select Access Time
150
150
200
200
250
250
300
300
Output Hold from Address Change, OE# or CS#
Output Enable to Output Valid
0
0
0
0
85
70
85
70
100
70
125
70
Chip Select or Output Enable to High Z Output
FOR WE256K8-XCX and WE128K8-XCX
-150
-200
Parameter
Symbol
Unit
Min
Max
Min
Max
Read Cycle Time
trc
tacc
tacs
toh
toe
tdf
150
200
ns
ns
ns
ns
ns
ns
Address Access Time
150
150
200
200
Chip Select Access Time
Output Hold from Address Change, OE# or CS#
Output Enable to Output Valid
Chip Select or Output Enable to High Z Output
0
0
85
70
85
70
5
4312.08E-0718-ss-WE512K_256K_128K8-XCX
Mercury Corp. - Memory and Storage Solutions • (602) 437-1520 • www.mrcy.com
WE512K / 256K / 128K8-XCX
WRITE
WRITE CYCLE TIMING
Write operations are initiated when both CS# and WE# are low
and OE# is high. The EEPROM devices support both a CS# and
WE# controlled write cycle. The address is latched by the falling
edge of either CS# or WE#, whichever occurs last.
Figures 6 and 7 show the write cycle timing relationships. A write
cycle begins with address application, write enable and chip select.
Chip select is accomplished by placing the CS# line low. Write
enable consists of setting the WE line low. The write cycle begins
when the last of either CS# or WE# goes low.
The data is latched internally by the rising edge of either CS#
or WE#, whichever occurs first. A byte write operation will
automatically continue to completion.
The WE# line transition from high to low also initiates an internal
150μsec delay timer to permit page mode operation. Each
subsequent WE# transition from high to low that occurs before the
completion of the 150μsec time out will restart the timer from zero.
The operation of the timer is the same as a retriggerable one-shot.
AC WRITE CHARACTERISTICS
VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C
512K x 8
256K x 8
128K x 8
Parameter
Symbol
Unit
Min
Max
Min
Max
Min
Max
Write Cycle Time, TYP = 6mS
Address Set-up Time
Write Pulse Width (WE# or CS#)
Chip Select Set-up Time
Address Hold Time (1)
Data Hold Time
tWC
tAS
tWP
tCS
10
10
10
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
150
0
30
150
0
30
150
0
tAH
125
10
0
50
0
50
0
tDH
Chip Select Hold Time
Data Set-up Time
tCH
0
0
tDS
100
10
10
50
100
30
0
100
30
0
Output Enable Set-up Time
Output Enable Hold Time
Write Pulse Width High
NOTES:
tOES
tOEH
tWPH
50
50
1. A17 and A18 must remain valid through WE# and CS# low pulse, for 512K x 8.
A15, A16, and A17 must remain valid through WE# and CS# low pulse, for 256K x 8.
A15 and A16 must remain valid through WE# and CS# low pulse, for 128K x 8.
6
4312.08E-0718-ss-WE512K_256K_128K8-XCX
Mercury Corp. - Memory and Storage Solutions • (602) 437-1520 • www.mrcy.com
WE512K / 256K / 128K8-XCX
FIGURE 6 – WRITE WAVEFORMS WE# CONTROLLED
OE#
ADDRESS (1)
CS#
WE#
DATA IN
NOTE:
1. Decoded Address Lines must be valid for the duration of the write.
FIGURE 7 – WRITE WAVEFORMS CS# CONTROLLED
OE#
ADDRESS (1)
CS#
WE#
DATA IN
NOTE:
1. Decoded Address Lines must be valid for the duration of the write.
7
4312.08E-0718-ss-WE512K_256K_128K8-XCX
Mercury Corp. - Memory and Storage Solutions • (602) 437-1520 • www.mrcy.com
WE512K / 256K / 128K8-XCX
DATA POLLING
Operation with data polling permits a faster method of writing to the
EEPROM. The actual time to complete the memory programming
cycle is faster than the guaranteed maximum.
A polled byte write sequence would consist of the following steps:
1. write byte to EEPROM
2. store last byte and last address written
3. release a time slice to other tasks
The EEPROM features a method to determine when the internal
programming cycle is completed.After a write cycle is initiated, the
EEPROM will respond to read cycles to provide the microprocessor
with the status of the programming cycle. The status consists
of the last data byte written being returned with data bit I/O7
complemented during the programming cycle, and I/O7 true after
completion.
4. read byte from EEPROM - last address
5. compare I/O7 to stored value
a) If different, write cycle is not completed, go to step 3.
b) If same, write cycle is completed, go to step 1 or step 3.
Data polling allows a simple bit test operation to determine the
status of the EEPROM. During the internal programming cycle,
a read of the last byte written will produce the complement of the
data on I/O7. For example, if the data written consisted of I/O7 =
HIGH, then the data read back would consist of I/O7 = LOW.
DATA POLLING AC CHARACTERISTICS
VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C
512Kx8 256Kx8
128Kx8
Parameter
Symbol
Unit
Min
10
Max
Min
0
Max
Min
0
Max
Data Hold Time
tDH
tOEH
tOE
ns
ns
ns
ns
Output Enable Hold Time
Output Enable To Output Delay
Write Recovery Time
10
0
0
100
100
100
tWR
0
0
0
FIGURE 8 – DATA POLLING WAVEFORMS
WE1-4
CS1-4
#
#
OE#
I/O7
ADDRESS
8
4312.08E-0718-ss-WE512K_256K_128K8-XCX
Mercury Corp. - Memory and Storage Solutions • (602) 437-1520 • www.mrcy.com
WE512K / 256K / 128K8-XCX
PAGE WRITE OPERATION
These devices have a page write operation that allows one to 64
bytes of data (one to 128 bytes for the WE512K8) to be written
into the device and then simultaneously written during the internal
programming period. Successive bytes may be loaded in the same
manner after the first data byte has been loaded. An internal timer
begins a time out operation at each write cycle. If another write cycle
is completed within 150μs or less, a new time out period begins.
Each write cycle restarts the delay period. The write cycles can be
continued as long as the interval is less than the time out period.
The page address must be the same for each byte load and must
be valid during each high to low transition of WE# (or CS#). The
block address also must be the same for each byte load and must
remain valid throughout the WE# (or CS#) low pulse. The page
and block address lines are summarized below:
PAGE MODE CHARACTERISTICS
VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C
The usual procedure is to increment the least significant address
lines from A0 through A5 (A0 through A6 for the WE512K8) at each
write cycle. In this manner a page of up to 64 bytes (128 bytes for
the WE512K8) can be loaded into the EEPROM in a burst mode
before beginning the relatively long interval programming cycle.
Parameter
Write Cycle Time, TYP = 6mS
Data Set-up Time
Symbol
tWC
Min
Max
Unit
ms
ns
10
tDS
100
10
Data Hold Time
tDH
ns
Write Pulse Width
tWP
150
ns
After the 150μs time out is completed, the EEPROM begins an
internal write cycle. During this cycle the entire page of bytes will
be written at the same time. The internal programming cycle is the
same regardless of the number of bytes accessed.
Byte Load Cycle Time
Write Pulse Width High
tBLC
tWPH
150
μs
ns
50
Device
Block Address
A17-A18
Page Address
A7-A16
WE512K8-XCX
WE256K8-XCX
WE128K8-XCX
A15-A17
A6-A14
A15-A16
A6-A14
FIGURE 9 – PAGE WRITE WAVEFORMS
OE#
CS#
WE#
ADDRESS (1)
DATA
NOTE:
1. Decoded Address Lines must be valid for the duration of the write.
9
4312.08E-0718-ss-WE512K_256K_128K8-XCX
Mercury Corp. - Memory and Storage Solutions • (602) 437-1520 • www.mrcy.com
WE512K / 256K / 128K8-XCX
FIGURE 10 – SOFTWARE BLOCK DATA PROTECTION ENABLE ALGORITHM
(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA A0
TO
ADDRESS 5555
WRITES ENABLED(2)
LOAD DATA XX
TO
ANY ADDRESS(4)
LOAD LAST BYTE
TO
LAST ADDRESS
ENTER DATA
PROTECT STATE
NOTES:
1. Data Format: I/O7-0 (Hex);
Address Format: A14 -A0 (Hex).
A17 and A18 control selection of one of four blocks in the 512Kx8.
A15, A16, and A17 control selection of one of 8 pages in the 256Kx8.
A15 and A16 control one of the four blocks in the 128Kx8.
2. Write Protect state will be activated at end of write even if no other data is loaded.
3. Write Protect state will be deactivated at end of write period even if no other data is loaded.
4. 1 to 128 bytes of data at each of 4 blocks may be loaded in the 512Kx8. 1 to 64 bytes of data
at each of 8 blocks may be loaded in the 256Kx8 and 1 to 64 bytes on 4 blocks in the 128Kx8.
10
4312.08E-0718-ss-WE512K_256K_128K8-XCX
Mercury Corp. - Memory and Storage Solutions • (602) 437-1520 • www.mrcy.com
WE512K / 256K / 128K8-XCX
FIGURE 11 –
SOFTWARE DATA PROTECTION
SOFTWARE BLOCK DATA
PROTECTION DISABLE ALGORITHM
A software write protection feature may be enabled or disabled
by the user. When shipped by White Microelectronics, the
devices have the feature disabled. Write access to the device is
unrestricted.
To enable software write protection, the user writes three access
code bytes to three special internal locations. Once write protection
has been enabled, each write to the EEPROM must use the same
three byte write sequence to permit writing. After setting software
data protection, any attempt to write to the device without the
three-byte command sequence will start the internal write timers.
No data will be written to the device, however, for the duration of
tWC. The write protection feature can be disabled by a six byte write
sequence of specific data to specific locations. Power transitions
will not reset the software write protection.
(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 80
TO
ADDRESS 5555
Each 32K byte block (128K bytes for the WE512K8) of EEPROM
has independent write protection. One or more blocks may be
enabled and the rest disabled in any combination. The software
write protection guards against inadvertent writes during
power transitions or unauthorized modification using a PROM
programmer. The block selection is controlled by the upper most
address lines (A17 through A18 for the WE512K8, A15 through A17
for the WE256K8, or A15 and A16 for the WE128K8).
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 20
TO
ADDRESS 5555
EXIT DATA
PROTECT STATE(3)
HARDWARE DATA PROTECTION
Several methods of hardware data protection have been
implemented in the White Microelectronics EEPROM. These are
included to improve reliability during normal operations.
LOAD DATA XX
TO
ANY ADDRESS(4)
LOAD LAST BYTE
TO
LAST ADDRESS
a) VCC power on delay
As VCC climbs past 3.8V typical the device will wait
5mSec typical before allowing write cycles.
b) VCC sense
While below 3.8V typical write cycles are inhibited.
c) Write inhibiting
Holding OE# low and either CS# or WE# high inhibits
write cycles.
d) Noise filter
NOTES:
1. Data Format: I/O7-0 (Hex);
Address Format: A14 -A0 (Hex).
Pulses of <8ns (typ) on WE# or CS# will not initiate a
write cycle.
A17 and A18 control selection of one of four blocks in the 512Kx8.
A15, A16, and A17 control selection of one of 8 pages in the 256Kx8.
A15 and A16 control one of the four blocks in the 128Kx8.
2. Write Protect state will be activated at end of write even if no other data is loaded.
3. Write Protect state will be deactivated at end of write period even if no other data
is loaded.
4. 1 to 128 bytes of data at each of 4 blocks may be loaded in the 512Kx8.
1 to 64 bytes of data at each of 8 blocks may be loaded in the 256Kx8 and
1 to 64 bytes on 4 blocks in the 128Kx8.
11
4312.08E-0718-ss-WE512K_256K_128K8-XCX
Mercury Corp. - Memory and Storage Solutions • (602) 437-1520 • www.mrcy.com
WE512K / 256K / 128K8-XCX
PACKAGE 300 – 32 PIN, CERAMIC DIP, SINGLE CAVITY SIDE BRAZED
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
PACKAGE 302 – 32 PIN, CERAMIC DIP, DUAL CAVITY BOTTOM BRAZED
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
12
4312.08E-0718-ss-WE512K_256K_128K8-XCX
Mercury Corp. - Memory and Storage Solutions • (602) 437-1520 • www.mrcy.com
WE512K / 256K / 128K8-XCX
ORDERING INFORMATION
W E XXXK8 - XXX C X X
MERCURY SYSTEMS
EEPROM
Organization, 512Kx8, 256Kx8 or 128Kx8
ACCESS TIME (ns)
PACKAGE:
C = Ceramic DIP
(Package 300 for 128Kx8)
(Package 302 for 256Kx8)
(Package 300 for 512Kx8)
PROCESSING:
Q = Military Grade*
M = Military Screened
I = Industrial
-55°C to +125°C
-40°C to +85°C
0°C to +70°C
C = Commercial
LEAD FINISH:
Blank = Gold plated leads
A
= Solder dip leads
* This product is processed the same as the 5962-XXXXXHXX product but all test
and mechanical requirements are per the Mercury Systems data sheet.
Device Type
512K x 8 EEPROM
512K x 8 EEPROM
512K x 8 EEPROM
512K x 8 EEPROM
Speed
150ns
300ns
250ns
200ns
Package
32 pin DIP (C)
32 pin DIP (C)
32 pin DIP (C)
32 pin DIP (C)
WM Part No.
WE512K8-150CQ
WE512K8-300CQ
WE512K8-250CQ
WE512K8-200CQ
SMD No.
5962-93091 01HYX
5962-93091 02HYX
5962-93091 03HYX
5962-93091 04HYX
256K x 8 EEPROM
256K x 8 EEPROM
200ns
150ns
32 pin DIP (C)
32 pin DIP (C)
WE256K8-200CQ
WE256K8-150CQ
5962-93155 01HYX
5962-93155 02HYX
128K x 8 EEPROM
128K x 8 EEPROM
200ns
150ns
32 pin DIP (C)
32 pin DIP (C)
WE128K8-200CQ
WE128K8-150CQ
5962-93154 01HXX
5962-93154 02HXX
13
4312.08E-0718-ss-WE512K_256K_128K8-XCX
Mercury Corp. - Memory and Storage Solutions • (602) 437-1520 • www.mrcy.com
WE512K / 256K / 128K8-XCX
Document Title
512Kx8 CMOS EEPROM, WE512K8-XCX, SMD 5962-93091
Revision History
Rev # History
Release Date Status
Rev 4
Changes (Pg. 1-14)
August 2011
Final
4.1 Change document layout from White Electronic Designs to Microsemi
4.2 Add document Revision History page
Rev 5
Rev 6
Change (Pg. 13)
May 2014
Final
Final
5.1 Changed Device Grade "Q" description from "MIL-STD-883 Compliant" to
"MIL-PRF-38534 Class H Compliant."
Change (Pg. 13)
August 2014
6.1 Changed Device Grade "Q" description from "MIL-PRF-38534 Class H
Compliant" to "Military Grade."
Rev 7
Rev 8
Changes (Pg. All) (ECN 10156)
August 2016
July 2018
Final
Final
7.1 Change document layout from Microsemi to Mercury Systems
Changes (Pg. All) (ECN 10957)
8.1 Update data sheet with new Mercury logo
Mercury Systems reserves the right to change products or specifications without notice.
© 2018 Mercury Systems. All rights reserved.
14
4312.08E-0718-ss-WE512K_256K_128K8-XCX
Mercury Corp. - Memory and Storage Solutions • (602) 437-1520 • www.mrcy.com
相关型号：
WE512K8-250CM
EEPROM Module, 512KX8, 250ns, Parallel, CMOS, CDIP32, HERMETIC SEALED, SINGLE CAVITY, SIDE BRAZED, CERAMIC, DIP-32
MERCURY
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