WE32K32-120G2UMA [MERCURY]
EEPROM Module, 32KX32, 120ns, Parallel, CMOS, CQFP68, 122.40 X 122.40 MM, 3.56 MM HEIGHT, HERMETIC SEALED, CERAMIC, QFP-68;
| 型号： | WE32K32-120G2UMA |
| 厂家： | 
MERCURY UNITED ELECTRONICS INC |
| 描述： | EEPROM Module, 32KX32, 120ns, Parallel, CMOS, CQFP68, 122.40 X 122.40 MM, 3.56 MM HEIGHT, HERMETIC SEALED, CERAMIC, QFP-68 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总14页 (文件大小：569K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WE32K32-XXX
32Kx32 EEPROM MODULE, SMD 5962-94614
FEATURES
Access Times of 125 and 150ns
MIL-STD-883 Compliant Devices Available
Packaging:
Automatic Page Write Operation
Page Write Cycle Time: 10ms Max
Data Polling for End of Write Detection
Hardware and Software Data Protection
TTL Compatible Inputs and Outputs
5 Volt Power Supply
• 68 lead, Hermetic CQFP (G2U), 122.4mm (0.880")
square, 3.56mm (0.140") height (Package 510).
• 66-pin, PGA Type, 1.075" square, Hermetic Ceramic HIP
(Package 400)
Low Power CMOS, 10mA Standby Typical
Data Retention at 25°C, 10 Years
Write Endurance, 10,000 Cycles
Built-in Decoupling Caps and Multiple Ground Pins for Low
Noise Operation
Organized as 32Kx32; User Configurable 64Kx16 or
* This product is subject to change without notice.
128Kx8
Commercial, Industrial and Military Temperature Ranges
FIGURE 1 – PIN CONFIGURATION FOR WE32K32N-XH1X
Top View
Pin Description
I/O0-31
A0-14
WE1-4#
CS1-4#
OE#
Data Input/Output
Address Inputs
Write Enable
Chip Selects
Output Enable
Power Supply
Ground
1
12
23
34
45
56
I/O8
I/O9
I/O10
A13
WE2#
CS2#
GND
I/O11
A10
I/O15
I/O24
I/O25
I/O26
A6
VCC
CS4#
WE4#
I/O27
A3
I/O31
I/O30
I/O29
I/O28
A0
I/O14
I/O13
I/O12
OE#
NC
VCC
GND
NC
Not Connected
A14
A7
NC
A11
NC
A4
A1
Block Diagram
WE1# CS1#
32K x 8
WE2# CS2#
WE3# CS3#
WE4# CS4#
32K x 8
NC
A12
WE1#
I/O7
A8
A5
A2
OE#
A0-14
NC
VCC
A9
WE3#
CS3#
GND
I/O19
I/O23
I/O22
I/O21
I/O20
32K x 8
32K x 8
I/O0
I/O1
I/O2
CS1#
NC
I/O6
I/O16
I/O17
I/O18
I/O5
8
8
8
8
I/O3
I/O4
I/O16-23
I/O24-31
I/O0-7
I/O8-15
11
22
33
44
55
66
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August 2014 © 2014 Microsemi Corporation. All rights reserved.
Rev. 9
1
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
WE32K32-XXX
FIGURE 2 – PIN CONFIGURATION FOR WE32K32-XG2UX
Top View
Pin Description
I/O0-31
A0-14
WE1-4#
CS1-4#
OE#
Data Input/Output
Address Inputs
Write Enable
Chip Selects
Output Enable
Power Supply
Ground
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61
60
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
GND
I/O8
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
VCC
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
GND
NC
Not Connected
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
Block Diagram
WE1# CS1#
32K x 8
WE2# CS2#
WE3# CS3#
WE4# CS4#
OE#
A0-14
32K x 8
32K x 8
32K x 8
8
8
8
8
I/O16-23
I/O24-31
I/O8-15
I/O0-7
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WE32K32-XXX
ABSOLUTE MAXIMUM RATINGS
TRUTH TABLE
Parameter
Symbol
TA
Unit
°C
°C
V
CS#
H
OE#
X
WE#
Mode
Standby
Read
Data I/O
High Z
Operating Temperature
Storage Temperature
-55 to +125
-65 to +150
-0.6 to + 6.25
-0.6 to +13.5
X
H
L
TSTG
VG
L
L
Data Out
Signal Voltage Relative to GND
Voltage on OE# and A9
L
H
Write
Data In
V
X
H
X
H
X
Out Disable
Write
High Z/Data Out
X
X
NOTE:
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
X
L
Inhibit
CAPACITANCE
TA = +25°C
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Conditions
VIN = 0 V, f = 1.0 MHz
Max Unit
Parameter
Supply Voltage
Symbol
VCC
VIH
Min
4.5
2.0
-0.3
-55
-40
Max
5.5
Unit
V
Address input capacitance
OE# capacitance
CAD
COE
50
pF
Input High Voltage
VCC + 0.3
+0.8
V
Input Low Voltage
VIL
V
WE# capacitance
CWE
CCS
CI/O
VIN = 0 V, f = 1.0 MHz
VIN = 0 V, f = 1.0 MHz
VI/O = 0 V, f = 1.0 MHz
50
25
40
pF
pF
pF
Operating Temp. (Mil.)
Operating Temp. (Ind.)
TA
+125
+85
°C
°C
CS1-4# capacitance
Data I/O capacitance
TA
This parameter is guaranteed by design but not tested.
DC CHARACTERISTICS
VCC = 5.0V, GND = 0V, -55°C ≤ TA ≤ +125°C
-80
-90
-120
-150
Parameter
Symbol
Conditions
Unit
Min Max Min Max Min Max Min Max
Input Leakage Current
Output Leakage Current
Operating Supply Current (x32)
Standby Current
ILI
VCC = 5.5, VIN = GND to VCC
10
10
10
10
10
10
10
10
μA
μA
mA
mA
V
ILOx32
ICCx32
ISB
CS# = VIH, OE# = VIH, VOUT = GND to VCC
CS# = VIL, OE# = VIH, f = 5MHz
CS# = VIH, OE# = VIH, f = 5MHz
IOL = 2.1mA, VCC = 4.5V
320
2.5
250
2.5
200
2.5
150
2.5
Output Low Voltage
VOL
0.45
0.45
0.45
0.45
Output High Voltage
VOH
IOH = -400μA, VCC = 4.5V
2.4
2.4
2.4
2.4
V
NOTE: DC test conditions: VIH = VCC -0.3V, VIL = 0.3V
AC TEST CONDITIONS
FIGURE 3 – AC TEST CIRCUIT
Parameter
Typ
Unit
Input Pulse Levels
Input Rise and Fall
VIL = 0, VIH = 3.0
V
ns
V
5
IOL
Input and Output Reference Level
Output Timing Reference Level
1.5
1.5
Current Source
V
Notes: VZ is programmable from -2V to +7V.
IOL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75Ω.
VZ ≈ 1.5V
D.U.T.
(Bipolar Supply)
V
I
Z is typically the midpoint of VOH and VOL
OL & IOH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
.
Ceff = 50 pf
IOH
Current Source
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August 2014 © 2014 Microsemi Corporation. All rights reserved.
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WE32K32-XXX
WRITE
A write cycle is initiated when OE# is high and a low pulse is on
WE# or CS# with CS# or WE# low. The address is latched on the
falling edge of CS# or WE# whichever occurs last. The data is
latched by the rising edge of CS# or WE#, whichever occurs first.
A byte write operation will automatically continue to completion.
The WE# line transition from high to low also initiates an internal
150 μsec delay timer to permit page mode operation. Each
subsequent WE# transition from high to low that occurs before the
completion of the 150 μsec time out will restart the timer from zero.
The operation of the timer is the same as a retriggerable one-shot.
WRITE CYCLE TIMING
Figures 4 and 5 show the write cycle timing relationships. A write
cycle begins with address application, write enable and chip select.
Chip select is accomplished by placing the CS# line low. Write
enable consists of setting the WE# line low. The write cycle begins
when the last of either CS# or WE# goes low.
AC WRITE CHARACTERISTICS
VCC = 5.0V, GND = 0V, -55°C ≤ TA ≤ +125°C
-80 -90
-120
-150
WRITE CYCLE
Symbol
Unit
Write Cycle Parameter
Min
Max
Min
Max
Min
Max
Min
Max
Write Cycle Time, TYP = 6ms
Address Set-up Time
tWC
tAS
tWP
tCS
10
10
10
10
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
100
0
0
100
0
30
150
0
30
150
0
Write Pulse Width (WE# or CS#)
Chip Select Set-up Time
Address Hold Time
tAH
50
0
50
0
100
10
0
100
10
0
Data Hold Time
tDH
Chip Select Hold Time
Data Set-up Time
tCSH
tDS
0
0
50
50
10
10
50
50
10
10
100
50
10
10
100
50
10
10
Write Pulse Width High
Output Enable Set-up Time
Output Enable Hold Time
tWPH
tOES
tOEH
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August 2014 © 2014 Microsemi Corporation. All rights reserved.
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WE32K32-XXX
FIGURE 4 – WRITE WAVEFORMS WE# CONTROLLED
tWC
OE#
tOES
tOEH
ADDRESS
CS1-4#
tAS
tCS
tAH
tCSH
WE1-4#
tWP
tWPH
tDH
tDS
DATA IN
FIGURE 5 – WRITE WAVEFORMS CS# CONTROLLED
tWC
OE#
tOES
tOEH
ADDRESS
WE1-4#
CS1-4#
tAS
tCS
tAH
tCSH
tWP
tWPH
tDH
tDS
DATA IN
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WE32K32-XXX
READ
The WE32K32-XXX stores data at the memory location determined
by the address pins. When CS# and OE# are low and WE# is
high, this data is present on the outputs. When CS# and OE# are
high, the outputs are in a high impedance state. This 2 line control
prevents bus contention.
AC READ CHARACTERISTICS (See Figure 6)
VCC = 5.0V, GND = 0V, -55°C ≤ TA ≤ +125°C
READ CYCLE
Symbol
-80
-90
-120
-150
Unit
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
Read Cycle Time
tRC
tACC
tACS
tOH
80
90
120
150
ns
ns
ns
ns
ns
ns
Address Access Time
80
80
90
90
120
120
150
150
CS Access Time
Output Hold from Add. Change, OE# or CS#
Output Enable to Output Valid
Chip Select or OE# to Output in High Z
0
0
0
0
tOE
40
40
50
50
85
70
85
70
tDF
FIGURE 6 – READ WAVEFORMS
tRC
ADDRESS VALID
ADDRESS
CS#
OE#
tACS
tOE
tDF
tACC
tOH
HIGH Z
OUTPUT
VALID
OUTPUT
NOTES:
1. OE# may be delayed up to tACS - tOE after the falling edge of CS# without impact on tOE or by tACC - tOE after an
address change without impact on tACC.
2. tCHZ, tOHZ are specified from OE# or CS# whichever occurs first (CL = 5pF).
3. All I/O transitions are measured ±200 mV from steady state with loading as specified in "Load Test Circuits."
Microsemi Corporation reserves the right to change products or specifications without notice.
August 2014 © 2014 Microsemi Corporation. All rights reserved.
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WE32K32-XXX
DATA POLLING CHARACTERISTICS
DATA POLLING
VCC = 5.0V, GND = 0V, -55°C ≤ TA ≤ +125°C
The WE32K32-XXX offers a data polling feature which allows a
faster method of writing to the device. Figure 7 shows the timing
diagram for this function. During a byte or page write cycle, an
attempted read of the last byte written will result in the complement
of the written data on D7 (for each chip.) Once the write cycle has
been completed, true data is valid on all outputs and the next
cycle may begin. Data polling may begin at any time during the
write cycle.
Parameter
Symbol
tDH
Min
10
Max
Unit
ns
Data Hold Time
OE# Hold Time
OE# To Output Valid
Write Recovery Time
tOEH
tOE
10
ns
100
ns
tWR
0
ns
FIGURE 7 – DATA POLLING WAVEFORMS
WE1-4#
CS1-4#
OE#
tOEH
tDH
tOE
I/O7
HIGH Z
tWR
ADDRESS
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August 2014 © 2014 Microsemi Corporation. All rights reserved.
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WE32K32-XXX
PAGE WRITE OPERATION
The WE32K32-XXX has a page write operation that allows one
to 64 bytes of data to be written into the device and consecutively
loads during the internal programming period. Successive bytes
may be loaded in the same manner after the first data byte has
been loaded.An internal timer begins a time out operation at each
write cycle. If another write cycle is completed within 150μs or less,
a new time out period begins. Each write cycle restarts the delay
period. The write cycles can be continued as long as the interval
is less than the time out period.
The usual procedure is to increment the least significant address
lines fromA0 throughA5 at each write cycle. In this manner a page
of up to 64 bytes can be loaded in to the EEPROM in a burst mode
before beginning the relatively long interval programming cycle.
After the 150μs time out is completed, the EEPROM begins an
internal write cycle. During this cycle the entire page of bytes will
be written at the same time. The internal programming cycle is the
same regardless of the number of bytes accessed.
PAGE WRITE CHARACTERISTICS
VCC = 5.0V, GND = 0V, -55°C ≤ TA ≤ +125°C
PAGE MODE WRITE CHARACTERISTICS
Parameter
-80
-90
-120
-150
Symbol
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Write Cycle Time, TYP = 6ms
Data Set-up Time
tWC
tDS
10
10
10
10
ms
ns
ns
ns
μs
ns
50
0
50
0
100
10
100
10
Data Hold Time
tDH
Write Pulse Width
tWP
tBLC
tWPH
100
100
150
150
Byte Load Cycle Time
Write Pulse Width High
150
150
150
150
50
50
50
50
FIGURE 8 – PAGE WRITE WAVEFORMS
OE#
CS#
tWP
tWP
tWP
WE#
tDS
ADDRESS (1)
DATA
VALID
ADDRESS
tWC
VALID DATA
BYTE 0
BYTE 1
BYTE 2
BYTE 3
BYTE n
BYTE n + 1
NOTE:
1. Decoded Address Lines must be valid for the duration of the write.
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August 2014 © 2014 Microsemi Corporation. All rights reserved.
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WE32K32-XXX
FIGURE 9 – SOFTWARE BLOCK DATA PROTECTION ENABLE ALGORITHM(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA A0
TO
ADDRESS 5555
WRITES ENABLED(2)
LOAD DATA XX
TO
ANY ADDRESS(4)
LOAD LAST BYTE
TO
LAST ADDRESS
ENTER DATA
PROTECT STATE
NOTES:
1. Data Format: I/O7-0 (Hex);
Address Format: A14 -A0 (Hex).
2. Write Protect state will be activated at end of write even if no other data is loaded.
3. Write Protect state will be deactivated at end of write period even if no other data is loaded.
4. 1 to 64 bytes of data to be loaded.
Microsemi Corporation reserves the right to change products or specifications without notice.
August 2014 © 2014 Microsemi Corporation. All rights reserved.
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WE32K32-XXX
FIGURE 10 –
SOFTWARE DATA PROTECTION
SOFTWARE BLOCK DATA PROTECTION DISABLE
ALGORITHM(1)
A software write protection feature may be enabled or disabled by
the user. When shipped by White Microelectronics, the WE32K32-
XXX has the feature disabled. Write access to the device is
unrestricted.
To enable software write protection, the user writes three access
code bytes to three special internal locations. Once write protection
has been enabled, each write to the EEPROM must use the same
three byte write sequence to permit writing. After setting software
data protection, any attempt to write to the device without the
three-byte command sequence will start the internal write timers.
No data will be written to the device, however, for the duration of
tWC. The write protection feature can be disabled by a six byte write
sequence of specific data to specific locations. Power transitions
will not reset the software write protection.
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
Each 32KByte block of the EEPROM has independent write
protection. One or more blocks may be enabled and the rest
disabled in any combination. The software write protection guards
against inadvertent writes during power transitions, or unauthorized
modification using a PROM programmer.
LOAD DATA 80
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
HARDWARE DATA PROTECTION
These features protect against inadvertent writes to the WE32K32-
XXX. These are included to improve reliability during normal
operation:
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 20
TO
ADDRESS 5555
a) Vcc power on delay
As Vcc climbs past 3.8V typical the device will wait 5msec
typical before allowing write cycles.
EXIT DATA
PROTECT STATE(3)
LOAD DATA XX
TO
b) Vcc sense
ANY ADDRESS(4)
While below 3.8V typical write cycles are inhibited.
LOAD LAST BYTE
TO
LAST ADDRESS
c) Write inhibiting
Holding OE# low and either CS# or WE# high inhibits write
cycles.
d) Noise filter
Pulses of <8ns (typ) on WE# or CS# will not initiate a write
cycle.
NOTES:
1. Data Format: I/O15-0 (Hex);
Address Format: A16 -A0 (Hex).
2. Write Protect state will be activated at end of write even if no other data is
loaded.
3. Write Protect state will be deactivated at end of write period even if no other
data is loaded.
4. 1 to 64 bytes of data may loaded.
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August 2014 © 2014 Microsemi Corporation. All rights reserved.
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WE32K32-XXX
PACKAGE 400 – 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H1)
27.3 (1.075) 0.25 (0.010) Sꢀ
PIN 1 IDENTIFIER
SꢀUARE PAD
ON BOTTOM
25.4 (1.0) TYP
4.60 (0.181)
MAX
3.81 (0.150)
0.13 (0.005)
0.76 (0.030) 0.13 (0.005)
2.54 (0.100)
TYP
1.27 (0.050) TYP DIA
15.24 (0.600) TYP
25.4 (1.0) TYP
0.46 (0.018) 0.05 (0.002) DIA
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
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August 2014 © 2014 Microsemi Corporation. All rights reserved.
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WE32K32-XXX
PACKAGE 510 – 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2U)
25.15 (0.990) 0.25 (0.010) Sꢀ
3.51 (0.140) MAX
22.36 (0.880) 0.25 (0.010) Sꢀ
0.25 (0.010) 0.10 (0.002)
Pin 1
0.25 (0.010) REF
R 0.25
(0.010)
24.0 (0.946)
0.25 (0.010)
0.53 (0.021)
0.18 (0.007)
1
/ 7
1.01 (0.040)
0.13 (0.005)
23.87
(0.940) REF
DETAIL A
1.27 (0.050) TYP
SEE DETAIL "A"
0.38 (0.015) 0.05 (0.002)
20.3 (0.800) REF
The White 68 lead G2U CQFP fills the
same fit and function as the JEDEC
68 lead CQFJ or 68 PLCC. But the
G2U has the TCE and lead inspection
advantage of the CQFP form.
23.88 (0.940) TYP
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
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August 2014 © 2014 Microsemi Corporation. All rights reserved.
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WE32K32-XXX
ORDERING INFORMATION
W E 32K32 X - XXX X X X
MICROSEMI CORPORATION
EEPROM
ORGANIZATION, 32K x 32
User Configurable as 64Kx16 or 128Kx8
IMPROVEMENT MARK
N = No Connect at pins 8, 21, 28, and 39 in HIP for upgrade
ACCESS TIME (ns)
PACKAGE TYPE:
H1 = Ceramic Hex In-line Package, HIP (Package 400)
G2U = 22.4mm Ceramic Quad Flat Pack, CQFP Low Profile (Package 510)
DEVICE GRADE:
Q = Military Grade*
M = Military Screened
I = Industrial
-55°C to +125°C
-40°C to +85°C
0°C to +70°C
C = Commercial
LEAD FINISH:
Blank = Gold plated leads
A = Solder dip leads
* This product is processed the same as the 5962-XXXXXHXX product but
all test and mechanical requirements are per the Microsemi data sheet.
DEVICE TYPE
SPEED
PACKAGE
SMD NO.
32K x 32 EEPROM Module
32K x 32 EEPROM Module
32K x 32 EEPROM Module
150ns
125ns
90ns
66 pin HIP (H1)
66 pin HIP (H1)
66 pin HIP (H1)
5962-94614 01HXX
5962-94614 02HXX
5962-94614 03HXX
32K x 32 EEPROM Module
32K x 32 EEPROM Module
32K x 32 EEPROM Module
150ns
125ns
90ns
68 lead CQFP/J (G2U)
68 lead CQFP/J (G2U)
68 lead CQFP/J (G2U)
5962-94614 01HZX
5962-94614 02HZX
5962-94614 03HZX
Microsemi Corporation reserves the right to change products or specifications without notice.
August 2014 © 2014 Microsemi Corporation. All rights reserved.
Rev. 9
13
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
WE32K32-XXX
Document Title
32Kx32 EEPROM MODULE, SMD 5962-94614
Revision History
Rev # History
Release Date Status
Rev 6
Changes (Pg. 1-14)
August 2011
Final
6.1 Change document layout from White Electronic Designs to Microsemi
6.2 Add document Revision History page
Rev 7
Changes (Pg. 1, 13)
September 2012
Final
7.1 Change 120ns to 125ns
7.2 Remove 80ns to 90ns
Rev 8
Rev 9
Change (Pg. 13)
May 2014
Final
Final
8.1 Changed Device Grade "Q" description from "MIL-STD-883 Compliant" to
"MIL-PRF-38534 Class H Compliant."
Change (Pg. 13)
August 2014
9.1 Changed Device Grade "Q" description from "MIL-PRF-38534 Class H
Compliant" to "Military Grade."
Microsemi Corporation reserves the right to change products or specifications without notice.
August 2014 © 2014 Microsemi Corporation. All rights reserved.
Rev. 9
14
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
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