MX26C512AQC-90 [Macronix]
EEPROM, 64KX8, 90ns, Parallel, CMOS, PQCC32, PLASTIC, MO-052, LCC-32;
| 型号： | MX26C512AQC-90 |
| 厂家： | 
MACRONIX INTERNATIONAL |
| 描述： | EEPROM, 64KX8, 90ns, Parallel, CMOS, PQCC32, PLASTIC, MO-052, LCC-32 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 内存集成电路 |
| 文件： | 总16页 (文件大小：108K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INDEX
MX26C512A
512K-BIT [64K x 8] CMOS
MULTIPLE-TIME-PROGRAMMABLE EPROM
FEATURES
• 64K x 8 organization
• Operating current: 30mA
• +5V operating power supply
• +12.75V program/erase voltage
• Electric erase instead of UV light erase
• Fast access time: 70/90/100/120/150 ns
• Totally static operation
• Standby current: 100uA
• 100 minimum erase/program cycles
• Package type:
- 28 pin plastic DIP
- 28 pin SOP
- 32 pin PLCC
- 28 pin TSOP(I)
• Completely TTL compatible
GENERAL DESCRIPTION
The MX26C512A is a 12.75V/5V, 512K-bit, MTP
EPROMTM (Multiple Time Programmable Read Only
Memory). It is organized as 64K words by 8 bits per word,
operates from a + 5 volt supply, has a static standby
mode, andfeaturesfastsingleaddresslocationprogram-
ming. It is designed to be reprogrammed and erased by
an EPROM programmer or on-board. All programming/
erasing signals are TTL levels, requiring a single pulse.
The MX26C512A supports an intelligent quick pulse
programming algorithm which can result in a program-
ming time of less than 30 seconds.
This MTP EPROMTM is packaged in industry standard 28
pin dual-in-line packages, 32 pin PLCC packages or 28
pin TSOP packages and 28 pin SOP packages.
BLOCK DIAGRAM
PIN CONFIGURATIONS
PDIP/SOP
PLCC
CE
CONTROL
LOGIC
OUTPUT
Q0~Q7
BUFFERS
VCC
A14
A13
A8
A15
A12
A7
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
OE
2
4
1
32
30
29
5
A6
A5
A4
A3
A2
A1
A0
NC
Q0
A8
3
A6
4
A9
A9
A5
5
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
Y-DECODER
X-DECODER
Y-SELECT
A11
NC
A11
OE/VPP
A10
CE
A4
6
A3
7
A0~A15
ADDRESS
INPUTS
A2
8
9
MX26C512A
25
OE/VPP
A10
CE
512K BIT
CELL
A1
9
Q7
A0
10
11
12
13
14
MAXTRIX
Q6
Q0
Q1
Q2
GND
Q5
Q7
Q4
13
14
21
Q6
Q3
17
20
VPP
VCC
GND
PIN DESCRIPTION
TSOP
SYMBOL
A0~A15
Q0~Q7
CE
PIN NAME
OE/VPP
A11
A9
22
23
24
25
26
27
28
1
21
20
19
18
17
16
15
14
13
12
11
10
9
A10
CE
Q7
Q6
Q5
Q4
Q3
GND
Q2
Q1
Q0
A0
Address Input
A8
Data Input/Output
Chip Enable Input
A13
A14
VCC
A15
A12
A7
MX26C512A
OE
Output Enable Input
Program Supply Voltage
No Internal Connection
Power Supply Pin (+5V)
Ground Pin
2
3
VPP
A6
4
A5
5
NC
A4
6
A1
VCC
A3
7
8
A2
GND
REV.1.8, JUL. 13 , 1998
P/N: PM0455
Patent#: US#5,523,307
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INDEX
MX26C512A
ERASE MODE
FUNCTIONAL DESCRIPTION
The MX26C512A is erased by EPROM programmer or
in-system. The device is set up in erase mode when
A9 =OE/VPP = 12.75V are applied, with VCC = 5V.
(AlgorithmisshowninFigure3). Theerasetimeisaround
1sec. If the erase is not verified, an additional erase
processes will be repeated for a maximum of 200 times.
When the MX26C512A is delivered, or it is erased, the
chip has all 512K bits in the "ONE", or HIGH state.
"ZEROs" are loaded into the MX26C512 through the
procedure of programming.
PROGRAMMING MODE
PROGRAMMMING ALGORITHM
PROGRAM INHIBIT MODE
The MX26C512A is programmed by an EPROM
programmer or on-board. The device is set up in the
programming mode when the programming voltage OE/
VPP = 12.75V is applied, with VCC = 5 V (Algorithm
showninFigure1). Programmingisachievedbyapplying
a single TTL low level 25us pulse to the CE input after
addresses and data lines are stable. If the data is not
verified, additional pulses are applied for a maximum of
20 pulses. After the data is verified, one 25us pulse is
applied to overprogram the byte so that program margin
is assured. This process is repeated while sequencing
througheachaddressofthedevice. When programming
is completed, the data at all the addresses are verified
at VCC = 5V ±10%.
Programming of multiple MX26C512A in parallel with
different data is also easily accomplished by using the
Program Inhibit Mode. Except for CE and OE, all like
inputs of the parallel MX26C512 may be common. A
TTL low-level program pulse applied to an MX26C512A
CE input with OE/VPP = 12.75 ± 0.25 V will program
that MX26C512A. A high-level CE input inhibits the other
MX26C512A from being programmed.
PROGRAM VERIFY MODE
Verification should be performed on the programmed bits
to determine that they were correctly programmed. The
verification should be performed with OE/VPP and CE,
at VIL. Data should be verified tDV after the falling edge
of CE.
The VCC supply of the MXIC On-Board Programming
Algorithm is designed to be 5V ± 10% particularly to
facilitate the programming operation under the on-board
application environment. But it can also be implemented
in an industrial-standard EPROM programmer.
ERASE VERIFY MODE
Verification should be performed on the erased chip to
determine that whole chip(all bits) was correctly erased.
Verification should be performed with OE/VPP and CE
at VIL and VCC = 5V.
COMPATIBILITY WITH MX27C512 FAST PROGRAMMING
ALGORITHM
Besides the On-Board Programming Algorithm, the Fast
Programming Algorithm of MX27C512 also applies to
MX26C512A. MXIC Fast Algorithm is the conventional
EPROM programing algorithm and is available in
industrial-standard EPROM programmers. A user of
industrial-standard EPROM programmer can choose
either of the algorithms base on his preference.
AUTO IDENTIFY MODE
The auto identify mode allows the reading out of a binary
code from a MTP that will identify its manufacturer and
device type. This mode is intended for use by
programming equipment for the purpose of automatically
matching the device to be programmed with its
corresponding programming algorithm. This mode is
functional in the 25°C ±5°C ambient temperature range
that is required when programming the MX26C512A.
The device is set up in the fast programming mode when
the programming voltage OE/VPP = 12.75V isapplied,
with VCC = 6.25V, (Algorithm is shown in Figure 2). The
programming is achieved by appling a single TTL low
level 25~100us pulse to the CE input after addresses and
datalinearestable. Ifthedataisnotverified,anadditional
pulseisappliedforamaximumof25pulses. Thisprocess
is repeated while sequencing through each address of
the device. When the programming mode is completed,
the data in all address is verified at VCC = 5V ±10%.
To activate this mode, the programming equipment must
force 12.75V on address line A9 of the device. Two
identifier bytes may then be sequenced from the device
outputs by toggling address line A0 from VIL to VIH. All
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MX26C512A
memory device.
SYSTEM CONSIDERATIONS
otheraddresslinesmustbeheldatVILduringautoidentify
mode.
Byte 0 ( A0 = VIL) represents the manufacturer code,
and byte 1 (A0 = VIH), the device identifier code. For
the MX26C512A, these two identifier bytes are given in
theModeSelectTable. Allidentifiersforthemanufacturer
and device codes will possess odd parity, with the MSB
(DQ7) defined as the parity bit.
Duringtheswitchbetweenactiveandstandbyconditions,
transient current peaks are produced on the rising and
falling edges of Chip Enable. The magnitude of these
transient current peaks is dependent on the output
capacitance loading of the device. At a minimum, a 0.1
uF ceramic capacitor (high frequency, low inherent
inductance) should be used on each device between
VCC and GND to minimize transient effects. In addition,
to overcome the voltage drop caused by the inductive
effects of the printed circuit board traces on EPROM
arrays, a4.7uFbulkelectrolyticcapacitorshouldbeused
between VCC and GND for each of the eight devices.
The location of the capacitor should be close to where
the power supply is connected to the array.
READ MODE
The MX26C512A has two control functions, both of
which must be logically satisfied in order to obtain data
at the outputs. Chip Enable (CE) is the power control
and should be used for device selection. Output Enable
(OE) is the output control and should be used to gate
data to the output pins, independent of device selection.
Assuming that addresses are stable, address access
time (tACC) is equal to the delay from CE to output (tCE).
Data is available at the outputs tOE after the falling edge
of OE, assuming that CE has been LOW and addresses
have been stable for at least tACC - tOE.
STANDBY MODE
The MX26C512A has a CMOS standby mode which
reducesthemaximumVCCcurrent to100uA. Itisplaced
in CMOS standby when CE is at VCC ± 0.3 V. The
MX26C512A also has a TTL-standby mode which
reduces the maximum VCC current to 1.5 mA. It is placed
in TTL-standby when CE is at VIH. When in standby
mode, the outputs are in a high-impedance state,
independent of the OE input.
TWO-LINE OUTPUT CONTROL FUNCTION
To accommodate multiple memory connections, a two-
line control function is provided to allow for:
1. Low memory power dissipation,
2. Assurance that output bus contention will not occur.
It is recommended that CE be decoded and used as the
primary device-selecting function, while OE be made a
common connection to all devices in the array and
connected to the READ line from the system control bus.
This assures that all deselected memory devices are in
their low-power standby mode and that the output pins
are only active when data is desired from a particular
REV.1.8, JUL. 13 , 1998
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INDEX
MX26C512A
MODE SELECT TABLE
PINS
A9
X
MODE
CE
OE/VPP
VIL
VIH
X
A0
X
OUTPUTS
DOUT
High Z
High Z
High Z
DIN
Read
VIL
VIL
VIH
VCC
VIL
VIL
VIL
VIL
VIH
VIL
VIL
Output Disable
Standby (TTL)
Standby (CMOS)
Program
X
X
X
X
X
X
X
VPP
VIL
VPP
VIL
X
X
X
Program Verify
Erase
X
X
DOUT
HIGH Z
DOUT
High Z
C2H
X
VPP
X
Erase Verify
Program Inhibit
Manufacturer Code
Device Code(26C512)
X
X
X
VIL
VIL
VIL
VIH
VH
VH
D1H
NOTES: 1. VH = 12.0V ±0.5V
2. X = Either VIH or VIL(For auto select)
3. A1 - A8 = A10 - A15 = VIL(For auto select)
4. See DC Programming Characteristics for VPP voltage during
programming.
FIGURE 1. PROGRAMMING FLOW CHART
START
ADDRESS = FIRST LOCATION
VCC = 5V
VPP = 12.75V
X = 0
PROGRAM ONE 25us PULSE
INCREMENT X
INTERACTIVE
SECTION
YES
X = 20 ?
NO
FAIL
VERIFY BYTE
?
PROGRAM ONE 25us PULSE
PASS
NO
LAST ADDRESS
INCREMENT ADDRESS
FAIL
YES
PROGRAM ONE 25us PULSE
VCC = 5V
VPP = VIL
VERIFY SECTION
FAIL
DEVICE FAILED
VERIFY ALL BYTES
?
PASS
DEVICE PASSED
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INDEX
MX26C512A
FIGURE 2. COMPATIBILITY WITH MX27C512 FAST PROGRAMMING FLOW CHART
START
ADDRESS = FIRST LOCATION
VCC = 6.25V
OE/VPP = 12.75V
PROGRAM ONE 25~100us PULSE
LAST
NO
INCREMENT ADDRESS
ADDRESS ?
YES
ADDRESS = FIRST LOCATION
X = 0
INCREMENT ADDRESS
NO
LAST
PASS
FAIL
INCREMENT X
VERIFY BYTE
ADDRESS ?
YES
NO
X = 25 ?
YES
PROGRAM ONE 25~100us PULSE
VCC = 5.0V
OE/VPP = VIL
COMPARE
ALL BYTES
TO ORIGINAL
DATA
FAIL
DEVICE FAILED
PASS
DEVICE PASSED
REV.1.8, JUL. 13 , 1998
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INDEX
MX26C512A
FIGURE 3. ERASING MODE FLOW CHART
START
X = 0
PROGRAM ALL "0"
A9 = 12.75V
VCC = 5V
VPP = 12.75V
CHIP ERASE (0.5s)
A9 = VIL or VIH
VCC = 5V
OE/VPP = VIL
All Bits Verify
NO
FAIL
ERASE VERIFY ?
X = 200 ?
INCREMENT X
YES
PASS
CHIP ERASE (0.5s)
DEVICE FAILED
DEVICE PASSED
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INDEX
MX26C512A
SWITCHING TEST CIRCUITS
1.8K ohm
DEVICE
UNDER
TEST
+5V
DIODES = IN3064
OR EQUIVALENT
CL
6.2K ohm
CL = 100 pF including jig capacitance(30pF for 70 ns parts)
SWITCHING TEST WAVEFORMS
3.0V
0V
TEST POINTS
1.5V
1.5V
OUTPUT
INPUT
AC TESTING: (1) Inputs are driven at 3.0V for a logic "1" and 0V for a logic "0".
Input pulse rise and fall times are < 10ns.
(2) For MX26C512A
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MX26C512A
ABSOLUTE MAXIMUM RATINGS
NOTICE:
RATING
VALUE
Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended period may affect reliability.
NOTICE:
Ambient Operating Temperature
Storage Temperature
Applied Input Voltage
Applied Output Voltage
VCC to Ground Potential
A9 & Vpp
0oC to 70oC
-65oC to 125oC
-0.5V to 7.0V
-0.5V to VCC + 0.5V
-0.5V to 7.0V
Specifications contained within the following tables are subject to
change.
-0.5V to 13.5V
DC CHARACTERISTICS TA = 0oC to 70oC, VCC = 5V ±10%
SYMBOL
VOH
VOL
VIH
PARAMETER
MIN.
MAX.
UNIT
V
CONDITIONS
IOH = -0.4mA
IOL = 2.1mA
Output High Voltage
Output Low Voltage
Input High Voltage
2.4
0.4
V
2.0
-0.3
-10
-10
VCC + 0.5
V
VIL
Input Low Voltage
0.8
10
V
ILI
Input Leakage Current
Output Leakage Current
VCC Power-Down Current
VCC Standby Current
VCC Active Current
uA
uA
uA
mA
mA
VIN = 0 to 5.5V
ILO
10
VOUT = 0 to 5.5V
CE = VCC ±0.3V
CE = VIH
ICC3
ICC2
ICC1
100
1.5
30
CE = VIL, f=5MHz, Iout = 0mA
CAPACITANCE TA = 25oC, f = 1.0 MHz (Sampled only)
SYMBOL
CIN
PARAMETER
TYP.
8
MAX.
8
UNIT
pF
CONDITIONS
VIN = 0V
Input Capacitance
Output Capacitance
VPP Capacitance
COUT
CVPP
8
12
pF
VOUT = 0V
VPP = 0V
18
25
pF
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INDEX
MX26C512A
AC CHARACTERISTICS TA = 0oC to 70oC, VCC = 5V±10%
26C512A
26C512A
-90
-70
SYMBOL PARAMETER
MIN.
MAX.
70
MIN.
MAX.
UNIT
ns
CONDITIONS
CE = OE = VIL
OE = VIL
tACC
tCE
Address to Output Delay
90
90
Chip Enable to Output Delay
70
ns
tOE
tDF
Output Enable to Output Delay
OE High to Output Float,
35
20
40
25
ns
ns
CE = VIL
0
0
0
0
or CE High to Output Float
tOH
Output Hold from Address,
ns
CE or OE which ever occurred firs
26C512A
-10
26C512A
-12
26C512A
-15
SYMBOL PARAMETER
MIN.
MAX.
MIN. MAX.
MIN.
MAX.
150
UNIT
ns
CONDITIONS
CE = OE = VIL
tACC
tCE
Address to Output Delay
100
100
120
120
50
Chip Enable to Output Delay
150
ns
OE = VIL
CE = VIL
tOE
tDF
Output Enable to Output Delay
OE High to Output Float,
45
30
65
50
ns
ns
0
0
0
0
35
0
0
or CE High to Output Float
tOH
Output Hold from Address,
ns
CE or OE which ever occurred first
DC PROGRAMMING CHARACTERISTICS TA = 25oC ±5oC
SYMBOL
VOH
VOL
VIH
PARAMETER
MIN.
MAX.
UNIT
V
CONDITIONS
Output High Voltage
2.4
IOH = -0.40mA
IOL = 2.1mA
Output Low Voltage
0.4
V
Input High Voltage
2.0
VCC + 0.5
V
VIL
Input Low Voltage
-0.3
-10
0.8
10
V
ILI
Input Leakage Current
A9 Auto Select Voltage
VCC Supply Current (Program/Erase & Verify)
VPP Supply Current(Program)/Erase
uA
V
VIN = 0 to 5.5V
VH
11.5
12.5
50
ICC3
IPP2
mA
mA
50
CE = PGM = VIL,
OE = VIH
VCC2
VPP2
IPP A9
Programming & Erase Supply Voltage
Programming & Erase Voltage
A9 Auto Select Current /Erase
4.5
6.5
13.0
1
V
12.5
V
mA
CE = PGM = VIL,
OE = VIH
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INDEX
MX26C512A
AC PROGRAMMING CHARACTERISTICS TA = 25oC ±5oC
SYMBOL
tAS
PARAMETER
MIN.
2.0
2.0
2.0
0
MAX.
UNIT
us
us
us
us
us
ns
us
us
us
ns
us
ns
s
CONDITIONS
Address Setup Time
OE Setup Time
tOES
tDS
Data Setup Time
Address Hold Time
Data Hold Time
tAH
tDH
2.0
0
tDFP
tVPS
tPW
tVCS
tDV
CE to Output Float Delay
VPP Setup Time
130
105
250
150
2.0
20
Program Pulse Width
VCC Setup Time
Data Valid from CE
CE Setup Time
2.0
tCES
tOE
2.0
Data valid from OE
Erase Recovery Time
Erase Pulse Width
Erase Verify Time
Program Verify Time
A9 Setup Time
tER
0.5
0.5
tEW
tEV
s
200
200
ns
ns
us
us
s
tPV
tA9S
tPVS
tEVS
2.0
2
Program Verify Setup
Erase Verify Setup
0.5
WAVEFORMS
READ CYCLE
ADDRESS
INPUTS
DATA ADDRESS
tACC
CE
tCE
OE
tDF
DATA
OUT
VALID DATA
tOE
tDH
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INDEX
MX26C512A
PROGRAMMING WAVEFORMS
PROGRAM
PROGRAM VERIFY
VIH
Addresses
VIL
tAS
tDS
DATA
tDFP
tAH
tDH
tDV
VPP1
OE/VPP
CE
VIL
tPRT
tPR
tVPS
tPVS
tPW
VIH
VIL
tPV
tVCS
VCC1
VCC
VCC
ERASE WAVEFORMS
ERASE
ERASE VERIFY
A9
VPP
VIH
ADDRESS
OTHERS NOT CARE
VIL
OUT
OUT
tEVS
VPP
OE/VPP
VIL
tVPS
tEV
VIH
CE
VIL
tER
tCES
tEW
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INDEX
MX26C512A
ORDERING INFORMATION
PLASTIC PACKAGE
PART NO.
ACCESS TIME(ns) OPERATING CURRENT MAX.(mA) STANDBY CURRENT MAX.(uA)
PACKAGE
MX26C512APC-70 70
MX26C512AMC-70 70
MX26C512AQC-70 70
MX26C512ATC-70 70
MX26C512APC-90 90
MX26C512AMC-90 90
MX26C512AQC-90 90
MX26C512ATC-90 90
MX26C512APC-10 100
MX26C512AMC-10 100
MX26C512AQC-10 100
MX26C512ATC-10 100
MX26C512APC-12 120
MX26C512AMC-12 120
MX26C512AQC-12 120
MX26C512ATC-12 120
MX26C512APC-15 150
MX26C512AMC-15 150
MX26C512AQC-15 150
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
28 Pin DIP
28 Pin SOP
32 Pin PLCC
28 Pin TSOP(I)
28 Pin DIP
28 Pin SOP
32 Pin PLCC
28 Pin TSOP(I)
28 Pin DIP
28 Pin SOP
32 Pin PLCC
28 Pin TSOP(I)
28 Pin DIP
28 Pin SOP
32 Pin PLCC
28 Pin TSOP(I)
28 Pin DIP
28 Pin SOP
32 Pin PLCC
28 Pin TSOP(I)
MX26C512AC-15
150
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INDEX
MX26C512A
PACKAGE INFORMATION
28-PIN PLASTIC DIP (600 mil)
ITEM
A
MILLIMETERS INCHES
15
28
37.34 max
2.03 [REF]
2.54 [TP]
.46 [Typ.]
32.99
1.470 max
.080 [REF]
.100 [TP]
B
C
D
E
.018 [Typ.]
1.300
F
1.52 [Typ.]
3.30 ±.25
.51 [REF]
3.94 ±.25
5.33 max.
15.22 ±.25
13.84 ±.25
.25 [Typ.]
.060 [Typ.]
.130 ±.010
.020 [REF]
.155 ±.010
.210 max.
.600 ±.010
.545 ±.010
.010 [Typ.]
1
14
G
H
I
K
L
A
I
J
J
K
H
G
L
M
F
C
M
0~15¡
NOTE: Each lead centerline is located within .25
mm[.01 inch] of its true position [TP] at
maximum material condition.
B
D
E
32-PIN PLASTIC LEADED CHIP CARRIER (PLCC)
A
B
1
ITEM
MILLIMETERS INCHES
4
32
30
A
B
C
D
E
F
G
H
I
12.44 ±.13
11.50 ±.13
14.04 ±.13
14.98 ±.13
1.93
.490 ±.005
.453 ±.005
.553 ±.005
.590 ±.005
.076
5
29
3.30 ±.25
2.03 ±.13
.51 ±.13
.130 ±.010
.080 ±.005
.020 ±.005
.050 [Typ.]
.028[REF]
9
25
C
D
1.27 [Typ.]
.71[REF]
13
21
J
K
L
.46 [REF]
10.40/12.94
.018 [REF]
.410/.510
14
20
17
(W) (L)
.89 R
(W) (L)
.035 R
E
M
N
.25 (TYP.)
.010 (TYP.)
F
N
G
H
NOTE: Each lead centerline is located within .25
mm[.01 inch] of its true position [TP] at
maximum material condition.
M
I
J
K
L
REV.1.8, JUL. 13 , 1998
P/N: PM0455
Patent#: US#5,523,307
13
INDEX
MX26C512A
28-PIN PLASTIC TSOP
A
B
ITEM
A
MILLIMETERS
13.4 ±.2
11.8 ±.1
8.0 ±.1
B
C
D
F
C
.15 ±.01
.2 ±.03
N
H
I
.55 [Typ.]
.425 [Typ.]
.05 [Min.]
1.00 ±.05
1.25 [Max.]
.05 ±.20
O° ~ 5°
M
J
K
L
K
L
M
N
D
J
E
I
F
H
G
NOTE: Each lead centerline is located within .25 mm
of its true position [TP] at maximum material
condition.
28-PIN PLASTIC SOP(330 mil)
ITEM
A
MILLIMETERS INCHES
28
15
18.62 max.
1.194 max
1.27 [TP]
.41 [Typ.]
.10 min.
.733 max.
.047 max
B
C
D
E
.050 [TP]
.016 [Typ.]
.004 min.
F
2.85 max.
2.49 ±.13
11.81 ±.31
8.41 ±.13
1.70 ±.20
.25 [Typ.]
.91 ±.20
.110 max.
.098 ±.005
.465 ±.012
.331±.005
.067 ±.008
.010 [Typ.]
.036 ±.008
1
14
G
H
I
A
H
I
J
J
K
G
F
L
K
NOTE: Each lead centerline is located within .25
mm[.01 inch] of its true position [TP] at
maximum material condition.
E
D
C
B
L
REV.1.8, JUL. 13 , 1998
P/N: PM0455
Patent#: US#5,523,307
14
INDEX
MX26C512A
Revision History
Revision#
Description
Date
1.2
1.3
Add 28 pin TSOP and SOP packages.
Erasing mode flow chart: Chip erase (5s)----> (1s).
Programming waveforms: CE changed.
MTP ROM--->MTP EPROM
3/28/1997
4/10/1997
1.4
5/30/1997
Chip erase(1s)--->0.5s. X = 60?--->200?
Switching Test Waveforms revise.
tEW Erase Pulse Width 1 sec---> 0.5 sec.
Programming/erase waveforms modifiction.
VPP:from 12.0~13V to 12.5V ~13V.
Erase Verify Time: 60 ---->200.
Change Part Name: 26C512 ---> 26C512A
Change tPW:Min. 95us -->Min. 20us.
Programming flow chart revised.
1.5
1.6
1.7
7/25/1997
11/05/1997
2/10/1998
Mode Select Table, Erase Mode A9=VH-->A9=Vpp.
Erase flow chart revised.
1.8
Delete IPP in DC CHARACTERISTICS
7/13/1998
REV.1.8, JUL. 13 , 1998
P/N: PM0455
Patent#: US#5,523,307
15
INDEX
MX26C512A
MACRONIX INTERNATIONAL CO., LTD.
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TEL:+886-3-578-8888
FAX:+886-3-578-8887
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http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the rignt to change product and specifications without notice.
16
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