97SD3248 [MAXWELL]
1.5Gb SDRAM 8-Meg X 48-Bit X 4-Banks; 1.5GB SDRAM的8梅格×48位× 4银行
| 型号： | 97SD3248 |
| 厂家： | 
MAXWELL TECHNOLOGIES |
| 描述： | 1.5Gb SDRAM 8-Meg X 48-Bit X 4-Banks |
| 文件： | 总40页 (文件大小：583K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
97SD3248
1.5Gb SDRAM
8-Meg X 48-Bit X 4-Banks
FEATURES:
DESCRIPTION:
• 1.5 Giggabit ( 8-Meg X 48-Bit X 4-Banks)
• RAD-PAK® radiation-hardened against natural space
radiation
• Total Dose Hardness:
>100 krad (Si), depending upon space mission
• Excellent Single Event Effects:
Maxwell Technologies’ Synchronous Dynamic Random
Access Memory (SDRAM) is ideally suited for space
applications requiring high performance computing and
high density memory storage. As microprocessors
increase in speed and demand for higher density mem-
ory escalates, SDRAM has proven to be the ultimate
solution by providing bit-counts up to 1.5 Gigabits and
speeds up to 100 Megahertz. SDRAMs represent a sig-
nificant advantage in memory technology over traditional
DRAMs including the ability to burst data synchronously
at high rates with automatic column-address generation,
the ability to interleave between banks masking pre-
charge time
SEL > 85 MeV/mg/cm2 @ 25°C
TH
• JEDEC Standard 3.3V Power Supply
• Clock Frequency: 100 MHz Operation
• Operating tremperature: -55 to +125 °C
• Auto Refresh
• Single pulsed RAS
• 2 Burst Sequence variations
Sequential (BL =1/2/4/8)
Interleave (BL = 1/2/4/8)
Maxwell Technologies’ patented RAD-PAK® packaging
technology incorporates radiation shielding in the micro-
circuit package. It eliminates the need for box shielding
for a lifetime in orbit or space mission. In a typical GEO
orbit, RAD-PAK® provides greater than 100 krads(Si)
radiation dose tolerance. This product is available with
screening up to Maxwell Technologies self-defined Class
K.
• Programmable CAS latency: 2/3
• Power Down and Clock Suspend Modes
• LVTTL Compatible Inputs and Outputs
• Package: 132 Lead Quad Stack Pack Flat Package
02.04.05 Rev 3
1
All data sheets are subject to change without notice
(858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com
©2005 Maxwell Technologies
All rights reserved.
97SD3248
1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
Pinout Description
Vcc
NC
Vss
NC
Vcc
NC
Vss
NC
NC
VSSQ
D47
D31
D15
VCCQ
NC
CS5
VSSQ
VCCQ
NC
CS3
CS6
CS4
CS1
CLK1
CS2
CLK2
NC
NC
DQM5
DQM3
DQM6
DQM4
DQM2
DQM1
D35
D19
D46
D30
D14
D3
VCCQ
VSSQ
D34
D18
D2
VCCQ
VSSQ
D45
D33
D17
D1
D32
D16
D29
D13
D44
D28
D12
D0
NC
Vss
NC
Vss
NC
Vcc
Vcc
The 97SD3248 Consists of 6, 8-Meg X 8-Bit X 4-Banks, die.
CKE 1-6, CS 1-6 and DQM 1-6 correspond to one of the die:
CKE1, CS1 and DQM1 control D0 - D7
CKE2, CS2 and DQM2 control D8 - D15
CKE3, CS3 and DQM3 control D16 - D23
CKE4, CS4 and DQM4 control D24 - D31
CKE5, CS5 and DQM5 control D32 - D39
CKE6, CS6 and DQM6 control D40 - D47
02.04.05 Rev 3
All data sheets are subject to change without notice
2
©2005 Maxwell Technologies
All rights reserved.
97SD3248
1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
‘
TABLE 1. ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
MAX
UNIT
Voltage on any pin relative to V
V
-0.5 to VCC + 0.5
(< 4.6(max))
V
SS
IN
V
OUT
Supply voltage relative to V
V
-0.5 to +4.6
50
V
mA
°C
°C
SS
CC
Short circuit output current
Operating Temperature
Storage Temperature
IOUT
TOPR
TSTG
-55 to +125
-65 to +150
TABLE 2. RECOMMENDED OPERATING CONDITIONS
(VCC = 3.3V + 0.3V, V Q = 3.3V + 0.3V, T = -55 TO 125°C, UNLESS OTHERWISE SPECIFIED)
CC
A
PARAMETER
Supply Voltage
SYMBOL
MIN
3.0
0
2.0
-0.3
MAX
3.6
0
UNIT
V
V
V
V
1,2
V , V
CC
CCQ
3
V , V
SS
SSQ
1,4
Input High Voltage
Input Low Voltage
V
V
IL
V + 0.3
IH
CC
1,5
0.8
1. All voltage referred to VSS
2. The supply voltage with all V and VCCQ pins must be on the same level
CC
3. The supply voltage with all VSS and VSSQ pins must be on the same level
4. V (max) = V +2.0V for pulse width <3ns at V
IH
CC
CC
5. V (min) = V -2.0V for pulse width <3ns at V
IL
SS
SS
TABLE 3. DELTA LIMITS
1
PARAMETER
DESCRIPTION
VARIATION
ICC1
Operating Current
Power Down Standby Current
Active Standby Current
±10%
±10%
±10%
I
CC2P ICC2PS CC2N CC2NS
ICC3P CC3PS CC3N CC3NS
1. ±10% of value specified in Table 4
I
I
I
I
I
TABLE 4. DC ELECTRICAL CHARACTERISTICS
(VCC = 3.3V + 0.3V, V Q = 3.3V + 0.3V, T = -55 TO 125°C, UNLESS OTHERWISE SPECIFIED)
CC
A
PARAMETER
Operating Current1,2,3
SYMBOL
TEST CONDITIONS
SUBGROUPS
MIN
MAX
UNITS
ICC1 Burst length CAS Latency = 2 1, 2, 3
690
690
mA
= 1
t
CAS Latency = 3
RC = min
Standby Current in Power Down4
ICC2P
CKE = V
tCK = 12 ns
1, 2, 3
1, 2, 3
18
12
mA
mA
IL
Standby Current in Power Down
( input signal stable)5
ICC2PS
CKE = V
IL
tCK = 0
02.04.05 Rev 3
All data sheets are subject to change without notice
3
©2005 Maxwell Technologies
All rights reserved.
97SD3248
1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
TABLE 4. DC ELECTRICAL CHARACTERISTICS
(V = 3.3V + 0.3V, V Q = 3.3V + 0.3V, T = -55 TO 125°C, UNLESS OTHERWISE SPECIFIED)
CC
CC
A
PARAMETER
SYMBOL
TEST CONDITIONS
SUBGROUPS
MIN
MAX
UNITS
Standby Current in non power down6
ICC2N
ICC2NS
ICC3P
CKE, CS = V
tCK = 12 ns
1, 2, 3
120
mA
IH
Standby Current in non power down7
( Input signal stable)
Active standby current in1,2,4
power down
CKE = V
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
54
24
mA
mA
mA
mA
mA
mA
IH
tCK = 0
CKE = V
IL
tCK = 12 ns
Active standby current in power down
(input signal stable)2,5
ICC3PS
ICC3N
ICC3NS
ICC4
CKE = V
18
IL
tCK = 0
Active standby power in non power
down1,2,6
CKE, CS1-6 = V
180
90
IH
tCK = 12 ns
Active standby current in non power
down ( input signal stable)2,7
Burst Operating Current1,2,8
CAS Latency = 2
CKE = V
IH
tCK = 0
tCK = min
BL = 4
660
870
CAS Latency = 3
Refresh Current3
Self Refresh current9,10
ICC5
ICC6
tRC = min
1, 2, 3
1, 2, 3
1320
18
mA
mA
V >V - 0.2V
IH CC
V < 0.2 V
IL
Input Leakage Current - CLK
Input Leakage Current - All Other
Output Leakage Current
Output high voltage
ILI
ILI
0<V <V
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
-3
-6
3
6
uA
uA
uA
V
LI CC
0<V <V
LI CC
ILO
0<V <V
-1.5
2.4
1.5
LO CC
V
IOH = -4mA
OH
Output low voltage
V
IOL = 4 mA
0.4
V
OL
1. ICC1 depends on output load conditions when the device is selected. ICC1(max) is specified with the output open.
2. One Bank Operation
3. Input signals are changed once per clock.
4. After power down mode, CLK operating current.
5. After power down mode, no CLK operating current.
6. Input signals are changed once per two clocks.
7. Input signals for VIH or VIL are fixed.
8. Input signals are changed once per four clocks.
9. After self refresh mode set, self refresh current.
10.Use Self Refresh for temperatures less than 70 °C ONLY.
02.04.05 Rev 3
All data sheets are subject to change without notice
4
©2005 Maxwell Technologies
All rights reserved.
97SD3248
1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
TABLE 5. AC Electrical Characteristics
(V =3.3V + 0.3V, V Q = 3.3V + 0.3V, T = -55 TO 125°C, UNLESS OTHERWISE SPECIFIED)
CC
CC
A
PARAMETER
SYMBOL
SUBGROUPS
MIN
TYPICAL
MAX
UNIT
System clock cycle time1
tCK
9, 10, 11
ns
(CAS latency = 2)
(CAS latency = 3)
10
7.5
CLK high pulse width1,7
CLK low pulse width1,7,
tCKH
tCKL
tAC
9, 10, 11
9, 10, 11
9, 10, 11
2.5
2.5
ns
ns
ns
1,2
Access time from CLK
(CAS latency = 2)
(CAS latency = 3)
6
6
Data-out hold time1,2,3
CLK to Data-out low impedance1,2,3,7
CLK to Data-out high impedance1,47,
(CAS latency = 2, 3)
tOH
tLZ
9, 10, 11
9, 10, 11
9, 10, 11
2.7
2
ns
ns
ns
tHZ
5.4
Input setup time1,5,6
tAS, tCS,
tDS, tCES
9, 10, 11
1.5
ns
CKE setup time for power down exit1
Input hold time1,6
tCESP
9, 10, 11
9, 10, 11
1.5
1.5
ns
ns
tAH, tCH, tDH
tCEH
Ref/Active to Ref/Active command period1
Active to Precharge command period1
Active command to column command 1
(same bank)
tRC
tRAS
tRCD
9, 10, 11
9, 10, 11
9, 10, 11
70
50
20
ns
ns
ns
120000
Precharge to Active command period1
tRP
tDPL
tRRD
tT
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
@ 105 °C
@ 85 °C
@ 70 °C
20
20
20
1
ns
ns
ns
ns
ms
Write recovery or data-in to precharge lead time1
Active( a) to Active (b) command period1
Transition time(rise and fall)7
5
Refresh Period
tREF
16
32
6.4
168
64
128
1. AC measurement assumes tT=1ns. Reference level for timing of input signals is 1.5V.
2. Access time is measured at 1.5V.
3. tLZ(min) definesthe time at which the outputs achieve the low impedance state.
4. tHZ(min) defines the time at which the outputs achieve the high impedance state.
5. tCES defines CKE setup time to CLK rising edge except for the power down exit command.
6. tAS/tAH: Address, tCS/tCH: /RAS, /CAS, /WE, DQM
7. Guarenteed by design (Not tested).
8. Guarenteed by Device Charactreization Testing. (Not 100% Tested)
02.04.05 Rev 3
All data sheets are subject to change without notice
5
©2005 Maxwell Technologies
All rights reserved.
97SD3248
1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
1
TABLE 6. CAPACITANCE
PARAMETER
SYMBOL
MAX
UNIT
Input Capacitance (CLK)
CI1
CI2
CO
21
23
4
pF
pF
pF
Input Capacitance (all other inputs)
Output Capacitance (DQ)
1. Guarenteed by design.
02.04.05 Rev 3
All data sheets are subject to change without notice
6
©2005 Maxwell Technologies
All rights reserved.
97SD3248
1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
Pin Functions:
CLK (INPUT PIN): CLK is the master clock input to this pin. The other input signals are referred at CLK rising
edge.
CS 1-6 (INPUT PINS): When CS 1-6 are low, the command input cycle becomes valid. When CS 1-6 are High,
all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held.
RAS, CAS AND WE (INPUT PINS): Although these pin names are the same as those of conventional DRAMs,
they function in a different way. These pins define operation commands (read, write, etc.) depending on the
combination of their voltage levels.
A0 TO A12 (INPUT PINS): Row address (AX0 to AX12) is determined by A0 to A12 level at the bank active
command cycle CLK rising edge. Column address (AY0 to AY9) is determined by A0 to A9 level at the read
or write command cycle CLK rising edge. And this column address becomes burst access start address.
A10 defines the precharge mode. When A10 = High at the precharge command cycle, all banks are pre-
charged. But when A10 = Low at the precharge command cycle, only the bank that is selected by BA0/BA1
(BS) is pre charged.
BA0/BA1 (INPUT PINS): BA0/BA1 are bank select signals (BS). The memory array of the 97SD3248 is divided
into bank 0, bank 1, bank 2 and bank 3. The 97SD3248 contains 8192-row X 1024-column X 48-bit. If BA0
and BA1 is Low, bank 0 is selected. If BA0 is Low and BA1 is High, bank 1 is selected. If BA0 is High and
BA1 is Low, bank 2 is selected. If BAO is High and BA1 is High, bank 3 is selected.
CKE (INPUT PIN): This pin determines whether or not the next CLK is valid. If CKE is High, the next CLK rising
edge is valid. If CKE is Low, the next CLK rising edge is invalid. This pin is used for power-down mode,
clock suspend mode and self refresh mode1.
DQM 1-6 (INPUT PINS): DQM 1-6 control input/output buffers
Read operation: If DQM 1-6 are High, the output buffer becomes High-Z. If the DQM 1-6 are Low, the output
buffer becomes Low-Z. ( The latency of DQM 1-6 during reading is 2 clock cycles.)
Write operation: If DQM 1-6 are High, the previous data is held ( the new data is not written). If the DQM 1-6
areLow, the data is written. ( The latency of DQM 1-6 during writing is 0 clock cycles.)
DQ0 TO DQ47 (DQ PINS): Data is input to and output from these pins ( DQ0 to DQ47).
V
AND V Q (POWER SUPPLY PINS): 3.3V is applied. ( V is for the internal circuit and V Q is for the output
CC CC CC
CC
buffer.)
V
AND V Q (POWER SUPPLY PINS): Ground is connected. (V is for the internal circuit and V Q is for the
SS
SS
SS
SS
output buffer.)
1. Self refresh mode should only be used at temperatures below 70°C.
02.04.05 Rev 3
All data sheets are subject to change without notice
7
©2005 Maxwell Technologies
All rights reserved.
97SD3248
1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
Command Operation
Command Truth Table
The SDRAM recognizes the following commands specified by the CS, RAS, CAS, WE and address pins:
BA0/
BA1
A0 TO
A12
COMMAND
SYMBOL
N-1
N
CS
RAS
CAS
WE
A10
Ignore command
No Operation
DESL
NOP
H
H
H
x
x
x
H
L
L
x
x
H
L
x
x
x
x
x
L
x
x
H
H
H
H
Column Address and
Read command
READ
V
V
Read with auto-pre-
charge
READ A
WRIT
H
H
H
H
H
x
x
x
x
x
L
L
L
L
L
H
H
H
L
L
L
L
H
H
H
L
L
H
L
V
V
V
V
V
H
L
V
V
V
V
x
Column Address and
write command
Write with auto-pre-
charge
WRIT A
ACTV
PRE
H
V
L
Row address strobe
and bank active
Precharge select
bank
L
Precharge all banks
Refresh
PALL
H
H
x
L
L
L
L
H
L
L
x
x
H
x
x
x
REF/
SELF
L
H
Mode register set
MRS
H
x
L
L
L
L
V
V
V
Note: H: V L: V x V or V V: Valid address input
IH
IL
IH
IL
Ignore command (DESL): When this command is set (CS = High), the SDRAM ignores command input at
the clock. However, the internal status is held.
No Operation (NOP): This command is not an execution command. However, the internal operations
continue.
Column address strobe and read command (READ): This command starts a read operation. In addition,
the start address of a burst read is determined by the column address (AY0 to AY9) and the bank select
address (BS). After the read operation, the output buffer becomes High-Z.
Read with auto-precharge (READ A): This command automatically performs a precharge operation after a
burst read with a burst length of 1, 2, 4, or 8.
02.04.05 Rev 3
All data sheets are subject to change without notice
8
©2005 Maxwell Technologies
All rights reserved.
97SD3248
1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
Column address strobe and write command (WRIT): This command starts a write operation. When the
burst write mode is selected, the column address (AY0 to AY9) and the bank select address (BA0/BA1)
become the burst write start address. When the single write mode is selected, data is only written to the
location specified by the column address (AY0 to AY9) and bank select address(BA0/BA1).
Write with auto-precharge (WRIT A): This command automatically performs a precharge operation after a
burst write with a length of 1, 2, 4, or 8, or after a single write operation.
Row address strobe and bank activate ( ACTV): This command activates the bank that is selected by
BA0/BA1 (BS) and determines the row address (AX0 to AX12). When BA0 and BA1 are Low, bank 0 is
activated. When BA0 is Low, and BA1 is High, bank 1 is activated. When BA0 is High and BA1 is Low, bank
2 is activated. When BA0 and BA1 are High, bank 3 is activated.
Precharge select bank (PRE): This command starts precharge operation for the bank selected by BA0/
BA1. If BA0 and BA1 are Low, bank 0 is selected. If BA0 is Low and BA1 is High, bank 1 is selected. If BA0
is High and BA1 is Low, bank 2 is selected. If BA0 and BA1 are High, bank 3 is selected.
Precharge all banks (PALL): This command starts a precharge operation for all banks.
Refresh (REF/SELF): This command starts the refresh operation. There are two types of refresh
operations; one is auto-refresh, and the other is self-refresh. For details, refer to the CKE truth table section.
Mode register set (MRS): The SDRAM has a mode register that defines how it operates. The mode register
is specified by the address pins (A0 to A12, BA0 andBA1) at the mode register set cycle. For details, refer to
the mode register configuration. After power on, the contents of the mode register are undefined, execute
the mode register set command to set up the mode register.
02.04.05 Rev 3
All data sheets are subject to change without notice
9
©2005 Maxwell Technologies
All rights reserved.
97SD3248
1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
DQM Truth Table
COMMAND
SYMBOL
CKE = N-1
H
CKE = N
x
DQM
L
Byte (DQ0 to DQ47) write enable/output
enable
ENB
Byte (DQ0 to DQ47) write inhibit/output dis-
able
MASK
H
x
H
Note: H: V L: V x V or V
IL
IH
IL
IH
Write: IDID is Needed
Read: IDOD is Needed
The SDRAM can mask input/output data by means of DQM.
During reading, the output buffer is set to Low-Z by setting DQM to Low, enabling data output. On the other
hand, when DQM is set High, the output buffer becomes High-Z, disabling data output.
During writing, data is written by setting DQM to Low. When DQM is set to High, the previous data is held
( the new data is not written). Desired data can be masked during burst read or burst write by setting DQM..
For more details, refer to the DQM control section of the SDRAM operating instructions.
CKE Truth Table
CURRENT STATE
COMMAND
N-1
N
CS
RAS
CAS
WE
ADDRESS
Active
Clock suspended mode entry
Clock Suspend
H
L
L
H
H
H
H
L
L
L
L
L
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Any
Clock Suspend
Clock Suspend mode exit
Auto-refresh command (REF)
Self-refresh entry (SELF)
H
H
L
x
x
x
x
Idle
Idle
Idle
L
L
L
H
x
L
L
H
x
H
H
H
x
L
L
L
Power down entry
L
HL
L
Self Refresh
Power down
Self Refresh exit (SELFX)
H
H
H
H
H
x
H
H
x
H
H
x
L
Power down exit
H
Note: H:V L:V x V or V
IL
IH
IL
IH
02.04.05 Rev 3
All data sheets are subject to change without notice 10
©2005 Maxwell Technologies
All rights reserved.
97SD3248
1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
Clock suspend mode entry: The SDRAM enters clock suspend mode from active mode by setting CKE to
Low. If a command is input in the clock suspend mode entry cycle, the command is valid. The clock suspend
mode change depending on the current status (1 clock before) as described below.
ACTIVE clock suspend: This suspend mode ignores inputs after the next clock by internally maintaining
the bank active status.
READ suspend and READ with Auto-precharge suspend: The data being output is held ( and continues
to be output).
WRITE suspend and WRIT with Auto-precharge suspended: In this mode, external signals are not
accepted. However, the internal state is held.
Clock suspend: During clock suspend mode, keep the CKE to Low.
Clock suspend mode exit: The SDRAM exits from clock suspend mode by setting CKE to High during the
clock suspend state.
IDLE: In this state, all banks are not selected, and have completed precharge operation.
Auto-refresh command (REF): When this command is input from the IDLE state, the SDRAM starts auto-
refresh operation. (The auto-refresh is the same as the CBR refresh of conventional DRAMs.) During the
auto-refresh operation, refresh address and bank select address are generated inside the SDRAM. For
every auto-refresh cycle, the internal address counter is updated. Accordingly, 8192 cycles are required to
refresh the entire memory contents. Before executing the auto-refresh command, all the banks must be in
the IDLE state. In addition, since the precharge for all banks is automatically performed after auto-refresh,
no precharge command is required after auto-refresh.
Self Refresh entry (SELF)1: When this command is input during the IDLE state, the SDRAM starts self-
refresh operation. After the execution of this command, self-refresh continues while CKE is Low. Since self-
refresh is performed internally and automatically, external refresh operations are unnecessary.
Power down mode entry: When this command is executed during the IDLE state, the SDRAM enters
power down mode. In power down mode, power consumption is suppresses by cutting off the initial input
circuit.
Self-refresh exit: When this command is executed during self-refresh mode, the SDRAM can exit from self-
refresh mode. After exiting from self-refresh mode, the SDRAM enters the IDLE state.
Power down exit: When this command is executed at power down mode, the SDRAM can exit from power
down mode. After exiting from power down mode, the SDRAM enters the IDLE state.
1. Self refresh mode should only be used at temperatures below 70°C.
02.04.05 Rev 3
All data sheets are subject to change without notice 11
©2005 Maxwell Technologies
All rights reserved.
97SD3248
1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
Function Truth Table
The following function table shows the operations that are performed when each command is issued in each
mode of the SDRAM.
The following table assumes that CKE is High.
CURRENT STATE
CS
RAS
CAS
WE
ADDRESS
COMMAND
OPERATION
Precharge
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
x
H
H
H
L
L
L
L
x
x
x
x
x
DESL
NOP
Enter IDLE after tRP
Enter IDLE after tRP
H
L
L
H
H
L
L
x
H
H
L
H
L
H
L
x
1
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
x
READ/READ A
WRIT/WRIT A
ACTV
ILLEGAL
1
ILLEGAL
1
ILLEGAL
PRE, PALL
REF, SELF
MRS
NOP2
ILLEGAL
ILLEGAL
NOP
MODE
x
Idle
DESL
H
H
H
L
L
L
L
x
H
L
L
H
H
L
L
x
H
H
L
H
L
H
L
x
x
NOP
NOP
3
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
x
READ/READ A
WRIT/WRIT A
ACTV
ILLEGAL
3
ILLEGAL
Bank and row active
NOP
PRE, PALL
REF, SELF
MRS
Refresh
MODE
x
Mode register set
NOP
Row active
DESL
H
H
H
L
H
L
L
H
H
H
L
H
x
NOP
NOP
BA, CA, A10
BA, CA, A10
BA, RA
READ/READ A
WRIT/WRIT A
ACTV
Begin read
Begin write
Other bank active
ILLEGAL on same bank4
L
L
L
L
L
L
H
L
L
L
H
L
BA, A10
x
PRE, PALL
REF, SELF
MRS
Precharge
ILLEGAL
ILLEGAL
MODE
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97SD3248
1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
CURRENT STATE
CS
RAS
CAS
WE
ADDRESS
COMMAND
OPERATION
READ
H
L
L
x
x
H
L
x
x
DESL
NOP
Continue burst to end
Continue burst to end
H
H
H
H
x
BA, CA, A10
READ/READ A
Continue burst read to CAS
latency and new read
L
L
H
L
L
L
BA, CA, A10
BA, RA
WRIT/WRIT A
ACTV
Term burst read/start write
H
H
Other bank active
ILLEGAL on same bank4
L
L
H
L
BA, A10
PRE, PALL
Term burst read and
Precharge
L
L
H
L
L
x
L
L
x
H
L
x
x
MODE
x
REF, SELF
MRS
ILLEGAL
ILLEGAL
Read with auto-
precharge
DESL
Continue burst to end and pre-
charge
L
H
H
H
x
NOP
Continue burst to end and pre-
charge
1
L
L
L
H
H
L
L
L
H
H
L
BA, CA, A10
BA, CA, A10
BA, RA
READ/READ A
WRIT/WRIT A
ACTV
ILLEGAL
1
ILLEGAL
H
Other bank active
ILLEGAL on same bank4
1
L
L
L
H
L
L
L
L
L
L
L
x
H
L
L
x
L
H
L
x
BA, A10
PRE, PALL
REF, SELF
MRS
ILLEGAL
x
MODE
x
ILLEGAL
ILLEGAL
Write
DESL
Continue burst to end
Continue burst to end
Term burst and new read
Term burst and new write
H
H
H
L
H
L
L
H
H
H
L
H
x
NOP
BA, CA, A10
BA, CA, A10
BA, RA
READ/READ A
WRIT/WRIT A
ACTV
Other bank active
ILLEGAL on same bank4
L
L
H
L
BA, A10
PRE, PALL
Term burst write and
precharge5
L
L
L
L
L
L
H
L
x
REF, SELF
MRS
ILLEGAL
ILLEGAL
MODE
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97SD3248
1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
CURRENT STATE
CS
H
RAS
x
CAS
x
WE
x
ADDRESS
COMMAND
OPERATION
Write with auto-
precharge
x
DESL
Continue burst to end and pre-
charge
L
H
H
H
x
NOP
Continue burst to end and pre-
charge
1
L
L
L
H
H
L
L
L
H
H
L
BA, CA, A10
BA, CA, A10
BA, RA
READ/READ A
WRIT/WRIT A
ACTV
ILLEGAL
1
ILLEGAL
H
Other bank active
ILLEGAL on same bank4
1
L
L
L
H
L
L
L
L
L
L
L
L
L
L
x
H
L
L
x
L
H
L
x
BA, A10
PRE, PALL
REF, SELF
MRS
ILLEGAL
x
MODE
x
ILLEGAL
ILLEGAL
Refresh ( auto-
refresh)
DESL
Enter IDLE after tRC
Enter IDLE after tRC
H
H
H
L
L
L
L
H
L
L
H
H
L
L
H
H
L
H
L
H
L
x
NOP
3
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
x
READ/READ A
WRIT/WRIT A
ACTV
ILLEGAL
3
ILLEGAL
3
ILLEGAL
3
PRE, PALL
REF, SELF
MRS
ILLEGAL
ILLEGAL
ILLEGAL
MODE
1. Illegal for same bank, except for another bank
2. NOP for same bank, except for another bank
3. Illegal for all banks
4. If tRRD is not satisfied, this operation is illegal
5. An interval of tDPL is required between the final valid data input and the precharge command
From PRECHARGE state, command operation
To [DESL], [NOP]: When these commands are executed, the SDRAM enters the IDLE state after tRP has
elapsed from the completion of precharge.
From IDLE state, command operation
To [DESL], [NOP], [PRE], or [PALL]: These commands result in no operation.
To [ACTV]: The bank specified by the address pins and the ROW address is activated.
To [REF], [SELF]: The SDRAM enters refresh mode (auto-refresh or self-refresh).
To [MRS]: The synchronous DRAM enters the mode register set cycle.
From ROW ACTIVE state, command operation
To [DESL], [NOP]: These commands result in no operation.
To [READ], [READ A]: A read operation starts. (However, an interval of tRCD is required.)
To [WRIT], [WRIT A]: A write operation starts. (However, an interval of tRCD is required.)
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97SD3248
1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
To [ACTV]: This command makes the other bank active. ( However, an interval of tRRD is required.)
Attempting to make the currently active bank active results in an illegal command.
To [PRE], [PALL]: These commands set the SDRAM to precharge mode. (However, an interval of tRAS is
required.)
From READ state, command operation
To [DESL], [NOP]: These commands continue read operations until the operation is completed.
To [READ], [READ A]: Data output by the previous read command continues to be output. After CAS
latency, the data output resulting from the next command will start.
To [WRIT], [WRIT A]: These commands stop a burst read, and start a write cycle.
To [ACTV]: This command makes other banks bank active. (However, an interval of tRRD is required.)
Attempting to make the currently active bank active results in an illegal command.
To [PRE], [PALL]: These commands stop a burst read, and the SDRAM enters precharge mode.
From READ with AUTO-PRECHARGE state, command operation
To [DESL], [NOP]: These commands continue read operations until the burst operation is completed, and
the SDRAM then enters precharge mode.
To [ACTV]: This command makes other banks active. (However, an interval of tRRD is required.) Attempting
to make the currently active bank active results in an illegal command.
From WRITE state, command operation
To [DESL], [NOP]: These commands continue write operations until the burst operation is completed.
To [READ], [READ A]: These commands stop a burst and start a read cycle.
To [WRIT], [WRIT A]: These commands stop a burst and start the next write cycle.
To [ACTV]: This command makes the other bank active. (However, an interval of tRRD is required.)
Attempting to make the currently active bank active results in an illegal command.
To [PRE], [PALL]: These commands stop burst write and the SDRAM then enters precharge mode.
From WRITE with AUTO-PRECHARGE state, command operation
To [DESL], [NOP]: These commands continue write operations until the burst is completed, and the
synchronous DRAM enters precharge mode.
To [ACTV]: This command makes the other bank active. (However, an interval of tRRD is required.)
Attempting to make the currently active bank active result in an illegal command.
From REFRESH state, command operation
To [DESL], [NOP]: After an auto-refresh cycle (after tRC) the SDRAM automatically enters the IDLE state.
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97SD3248
1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
Simplified State Diagram
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97SD3248
1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
Mode Register Configuration
The mode register is set by the input to the address pins (A0 to A12, BA0 and BA1) during mode register set
cycles. The mode register consists of five sections, each of which is assigned to address pins.
BA0, BA1, A11, A10, A12, A9, A8: (OPCODE): The SDRAM has two types of write modes. One is the burst
write mode, and the other is the single write mode. These bits specify write mode.
Burst read and burst write: Burst write is performed for the specified burst length starting from the column
address specified in the write cycle.
Burst read and single write: Data is only written to the column address specified during the write cycle,
regardless of the burst length.
A7: Keep this bit Low at the mode register set cycle. If this pin is high, the vender test mode is set.
A6, A5, A4: (LMODE): These pins specify the CAS latency.
A3: (BT): A burst type is specified.
A2, A1, A0: (BL): These pins specify the burst length.
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97SD3248
1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
02.04.05 Rev 3
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97SD3248
1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
Burst Sequence
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97SD3248
1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
Operation of the SDRAM
The following section shows operation examples of 97SD32488.
Note: The SDRAM should be used according to the product capability ( See Pin Description and AC
Characteristics.)
Read/Write Operations:
Bank Active: Before executing a read or write operation, the corresponding bank and the row address must
be activated by the bank active (ACTV) command. An interval of tRCD is required between the bank active
command input and the following read/write command input.
Read operation: A read operation starts when a read command is input. The output buffer becomes Low-Z
in the (CAS latency - 1) cycle after read command set. The SDRAM can perform a burst read operation.
The burst length can be set to 1, 2, 4, or 8. The start address for a burst read is specified by the column
address and the bank select address (BA0/BA1) at the read command set cycle. In a read operation, data
output starts after the number of clocks specified by the CAS latency. The CAS latency can be set to 2 or 3.
When the burst length is 1, 2, 4, or 8, the DOUT buffer automatically becomes High-Z at the next clock after
the successive burst-length data has been output.
The CAS latency and burst length must be specified at the mode register.
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97SD3248
1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
CAS Latency
Burst Length
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97SD3248
1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
Write Operation: Burst write or single write mode is selected by the OPCODE (BA1, BA0, A12, A11, A10,
A9, A8) of the mode register.
1. Burst write: A burst write operation is enabled by setting OPCODE (A9, A8) to (0, 0). A burst write starts
in the same clock as a write command set. (The latency of data input is 0 clock.) The burst length can be set
to 1, 2, 4, or 8, like burst read operations. The write start address is specified by the column address and the
bank select address (BA0/BA1) at the write command set cycle.
2. Single write: A single write operation is enabled by setting OPCODE ( A9, A8) to (1, 0). In a single write
operation, data is only written to the column address and the bank select address (BA0/BA1) specified by
the write command set cycle without regard to the burst length setting. ( The latency of data input is 0 clock.)
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97SD3248
1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
Auto Precharge
Read with auto-precharge: In this operation, since precharge is automatically performed after completing a
read operation, a precharge command need not be executed after each read operation. The command
executed for the same bank after the execution of this command must be the bank active (ACTV) command.
In addition, an interval defined by IARP is required before execution of the next command.
CAS latency
Precharge start cycle
3
2
2 cycles before the final data is output
1 cycle before the final data is output
Burst Read (Burst Length = 4)
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97SD3248
1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
Write with auto-precharge: In this operation, since precharge is automatically preformed after completing a
burst write or single write operation, a precharge command need not be executed after each write operation.
The command executed for the same bank after the execution of this command must be the bank active
(ACTV) command. In addition, an interval of IAPW is required between the final valid data input and input of
next command.
Burst Write (Burst Length = 4)
Single Write
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97SD3248
1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
Command Intervals
READ command to READ command interval
1. Same bank, same ROW address: When another read command is executed at the same ROW address
of the same bank as the preceding read command execution, the second read can be performed after an
interval of no less than 1 clock. Even when the first command is a burst read that is not yet finished, the data
read by second command will be valid.
READ to READ Command Interval (Same ROW address in same bank)
2. Same bank, different ROW address: When the ROW address changes on the same bank, consecutive
read commands cannot be executed; it is necessary to separate the two read commands with a precharge
command and a bank-active command.
3. Different bank: When the bank changes, the second read can be performed after an interval of no less
than 1 clock, provided that the other bank is in the bank-active state. Even when the first command is a burst
read that is not yet finished, the data read by the second command will be valid.
READ to READ Command Interval ( Different Bank)
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97SD3248
1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
Write command to Write command interval:
1. Same bank, same ROW address: When another write command is executed at the same ROW address
of the same bank as the preceding write command, the second write can be performed after as interval of no
less than 1 clock. In the case of burst writes, the second write command has priority.
Write to Write Command Interval (Same ROW address in same bank)
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands
cannot be executed; it is necessary to separate the two write commands with a precharge command and a
bank-active command.
3. Different bank: When the bank changes, the second write can be performed after an interval of no less
than 1 clock, provided that the other bank is in the bank-active state. In the case of burst write, the second
write command has priority.
WRITE to WRITE Command Interval (Different bank)
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97SD3248
1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
Read command to Write command Interval:
1. Same bank, same ROW address: When the write command is executed at the same ROW address of
the same bank as the preceding read command, the write command can be performed after an interval of no
less than 1 clock. However, DQM must be set High so the output buffer becomes High-Z before data input.
READ to WRITE Command Interval (1)
READ to WRITE Command Interval (2)
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands
cannot be executed; it is necessary to separate the two commands with a precharge command and a bank-
active command.
3. Different bank: When the bank changes, the write command can be performed after an interval of no
less than 1 cycle, provided that the other bank is in the bank-active state. However, DQM must be set High
so that the output buffer becomes High-Z before data input.
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97SD3248
1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
Write command to READ command interval:
1. Same bank, same ROW address: When the read command is executed at the same ROW address of
the same bank as the preceding write command, the read command can be performed after an interval of no
less than 1 clock. However, in the case of a burst write, data will continue to be written until one clock before
the read command is executed.
WRITE to READ Command Interval (1)
Write to READ Command Interval (2)
2. Same bank, different ROW address: When the ROW address changes, consecutive read commands
cannot be executed; it is necessary to separate the two commands with a precharge command and a bank-
active command.
3. Different bank: When the bank changes, the read command can be performed after an interval of no less
than 1 clock, provided that the other bank is in the bank-active state. However, in the case of a burst write,
data will continue to be written until one clock before the read command is executed (as in the case of the
same bank and the same address).
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97SD3248
1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
Read with Auto Precharge to READ command interval
1. Different bank: When some banks are in the active state, the second read command ( another bank) is
executed. Even when the first read with auto-precharge is a burst read that is not yet finished, the data read
by the second command is valid. The interval auto-precharge of one bank starts at the next clock of the
second command.
Read with Auto Precharge to Read Command Interval (Different Bank)
2. Same Bank: The consecutive read command (the same bank) is illegal.
Write with Auto Precharge to Write command interval
1. Different bank: When some banks are in the active state, the second write command (another bank) is
executed. In the case of burst writes, the second write command has priority. The internal auto-precharge of
one bank starts at the next clock of the second command.
Write with Auto Precharge to Write Command Interval (Different bank)
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97SD3248
1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
2. Same bank: The consecutive write command ( the same bank) is illegal.
Read with Auto Precharge to Write command interval
1. Different bank: When some banks are in the active state, the second write command (another bank) is
executed. However, DQM must be set High so that the output buffer becomes High-Z before data input. The
internal auto-precharge of one bank starts at the next clock of the second command.
Read with Auto Precharge to Write Command Interval (Different bank)
2. Same bank: The consecutive write command from read with auto precharge ( the same bank) is illegal. It
is necessary to separate the two commands with a bank active command.
Write with Auto Precharege to Read command interval
1. Different bank: When some banks are in the active state, the second read command (another bank) is
executed. However, in the case of a burst write, data will continue to be written until one clock before the
read command is executed. The internal auto precharge of one bank starts at the next clock of the second
command.
Write with Auto Precharge to Read command Interval (Different bank)
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97SD3248
1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
2. Same Bank: The consecutive read command from write with auto precharge (the same bank) is illegal. It
is necessary to separate the two commands with a bank active command.
Read command to Precharge command Interval (same bank)
When the precharge command is executed for the same bank as the read command that preceded it, the
minimum interval between the two commands is one clock. However, since the output buffer than becomes
High-Z after the clock defined by IHZP , there is a case of interruption to burst read data. Output will be
interrupted if the precharge command is input during burst read. To read all data by burst read, the clocks
defined by IEP must be assured as an interval from the final data output to precharge command execution.
READ to PRECHARGE command Interval (same bank: To output all data)
CAS Latency = 2, Burst Length = 4
CAS Latency = 3, Burst Length = 4
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97SD3248
1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
Recharge command Interval (same bank): To stop output data
CAS Latency = 2, Burst Length = 1, 2, 4, 8
CAS Latency = 3, Burst Length = 1, 2, 4, 8
d to Precharge command interval (same bank): When the precharge command is executed for the same
bank as the write command that preceded it, the minimum interval between the two commands is 1 clock.
However, if the burst write operation is unfinished, the data must be masked by means of DQM for
assurance of the clock defined by tDPL.
WRITE to PRECHARGE Command Interval (same bank)
Burst Length = 4 (To stop write operation)
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97SD3248
1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
Burst Length = 4 (To write to all data)
Bank active command interval:
1. Same bank: The interval between the two bank-active commands must be no less than tRC.
2. In the case of different bank-active commands: The interval between the two bank-active commands
must be no less than tRRD
.
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97SD3248
1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
Bank Active to Bank Active for Same Bank
Bank Active to Bank Active for Different Bank
Mode register set to Bank-active interval: The interval between setting the mode register and executing a
bank-active command must be no less than IRSA.
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97SD3248
1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
DQM Control
The DQM mask the bytes of the DQ data. The timing of DQM is different during reading and writing.
Reading: When data is read, the output buffer can be controlled by DQM. By setting DQM to Low, the output
buffer becomes Low-Z, enabling data output. By setting DQM to High, the output buffer becomes High-Z and
the corresponding data is not output. However, internal reading operations continue. The latency of DQM
during reading is 2 clocks.
Writing: Input data can be masked by DQM. By setting DQM to Low, data can be written. In addition, when
DQM is set to High, the corresponding data is not written, and previous data is held. The latency of DQM
during writing is 0 clock.
Reading
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97SD3248
1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
Writing
Refresh
Auto-Refresh: All the banks must be precharged before executing an auto-refresh command. Since the
auto-refresh command updates the internal counter every time it is executed and determines the banks and
the ROW addresses to be refreshed, external address specification is not required. The refresh cycle is
8192 cycles/6.4 ms. (8192 cycles are requires to refresh all the ROW addresses.) The output buffer
becomes High-Z after auto-refresh start. In addition, since a precharge has been completed by an internal
operation after the auto-refresh, an additional precharge operation by the precharge command is not
required.
Self-refresh1: After executing a self-refresh command, the self-refresh operation continues while CKE is
held Low. During self-refresh operation, all ROW addresses are refreshed by the internal refresh timer. A
self-refresh is terminated by a self-refresh exit command. Before and after self-refresh mode, execute auto-
refresh to all refresh addresses in or within 6.4ms period on the condition (1) and (2) below.
(1) Enter self-refresh mode within 7.8 us after either burst refresh or distributed refresh at equal interval until
all refresh addresses are completed.
(2) Start burst refresh or distributed refresh at equal interval to all refresh addreses within 7.8 us after exiting
from self-refresh mode.
Others
Power-down mode: The SDRAM enters power-down mode when CKE goes Low in the IDLE state. In
power-down mode, power consumption is suppressed by deactivating the input initial circuit. Power-down
mode continues while CKE is held Low. In addition, by setting CKE to High, the SDRAM exits from the
power-down mode, and command input is enabled from the next clock. In this mode, internal refresh is not
performed.
1. Self refresh mode should only be used at temperatures below 70°C.
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97SD3248
1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
Clock suspend mode: By driving CKE to Low during a bank-active or read/write operation, the SDRAM
enters clock suspend mode. During clock suspend mode, external input signals are ignored and the internal
state is maintained. When CKE is driven High, the SDRAM terminates clock suspend mode, and command
input is enabled from the next clock. For more details, refer to the “CKE Truth Table”.
Power-up sequence: The SDRAM should use the following sequence during power-up:
The CLK, CKE, CS, DQM and DQ pins stay low until power stabilizes.
The CLK pin is stable within 100ms after power stabilizes before the following initialization sequence.
The CKE and DQM is driven high between when power stabilizes and the initialization sequence.
This SDRAM has V clamp diodes for CLK, CKE, CS, DQM and DQ pins. If these pins go high before
power up, the largeCcCurrent flows from these pins to V through the diodes.
CC
Initialization sequence: When 200ms or more has past after the power up sequence, all banks must be
precharged using the precharge command (PALL). After tRP delay, set 8 or more auto refresh commands
(REF). Set the mode register set command (MRS) to initialize the mode register. It is recommended that by
keeping DQM and CKE High, the output buffer becomes High-Z during initialization sequence, to avoid DQ
bus contention on a memory system formed with a number of devices.
02.04.05 Rev 3
All data sheets are subject to change without notice 37
©2005 Maxwell Technologies
All rights reserved.
97SD3248
1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
132-LEAD QUAD RAD-STACK PACKAGE
DIMENSION (INCHES)
SYMBOL
MIN
NOM
MAX
A
b
.385
.006
.005
1.337
.795
.398
.008
.411
.010
.008
1.363
.805
c
.006
D
D1
e
1.350
.800
.025
S1
F1
L
.266
.997
2.485
1.685
.355
1.000
2.500
1.700
.368
1.003
2.505
1.715
.381
L1
A1
X
Y
Z
1.030
.965
1.040
.975
1.050
.985
.060
.065
.070
U
V
N
1.160
1.160
1.260
1.160
132
1.360
1.360
Note: All dimensions in inches.
02.04.05 Rev 3
All data sheets are subject to change without notice 38
©2005 Maxwell Technologies
All rights reserved.
97SD3248
1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
Important Notice:
These data sheets are created using the chip manufacturer’s published specifications. Maxwell Technologies verifies
functionality by testing key parameters either by 100% testing, sample testing or characterization.
The specifications presented within these data sheets represent the latest and most accurate information available to
date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no
responsibility for the use of this information.
Maxwell Technologies’ products are not authorized for use as critical components in life support devices or systems
without express written approval from Maxwell Technologies.
Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell
Techoogies. Maxwell Technologies’ liability shall be limited to replacement of defective parts.
02.04.05 Rev 3
All data sheets are subject to change without notice 39
©2005 Maxwell Technologies
All rights reserved.
97SD3248
1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
PRODUCT ORDERING OPTIONS
Model Number
Q
97SD3248
RP
X
Option Details
Feature
MCM
K= Maxwell Self-defined Class K
H= Maxwell Self-defined Class H
I = Industrial (testing @ -55°C,
+25°C, +125°C)
Screening Flow
1
1
E = Engineering (testing @ +25°C)
Q = Quad Flat Pack
Package
RP = RAD-PAK® package
Radiation Feature
1.5Gb (8-Meg X 48-Bit X 4-Banks)
SDRAM
Base Product
Nomenclature
1) Products are manufactured and screened to Maxwell Technologies self-defined Class H and K flows in a MIL-PRF-38535
qualified facility.
02.04.05 Rev 3
All data sheets are subject to change without notice 40
©2005 Maxwell Technologies
All rights reserved.
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