7025ERPQS-35 [MAXWELL]
(8K x 16-Bit) Dual Port RAM High-Speed CMOS; （ 8K ×16位），双端口RAM的高速CMOS
| 型号： | 7025ERPQS-35 |
| 厂家： | 
MAXWELL TECHNOLOGIES |
| 描述： | (8K x 16-Bit) Dual Port RAM High-Speed CMOS |
| 文件： | 总20页 (文件大小：524K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
7025E
(8K x 16-Bit) Dual Port RAM
High-Speed CMOS
Logic Diagram
FEATURES:
DESCRIPTION:
•
8K x 16-bit dual port RAM
- Stand Alone
- Master Slave
RAD-PAK® radiation-hardened against natural space
radiation
Maxwell Technologies’ 7025E Dual Port RAM High Speed
CMOS® microcircuit features a greater than 100 krad (Si) total
dose tolerance, depending upon space mission. The 7025E is
designed to be used as a stand-alone 128k-bit Dual Port RAM
or as a combination MASTER/SLAVE Dual-Port RAM for 32-
bit or more word systems. This design results in full-speed,
error-free operation without the need for additional discrete
logic. The 7025E provides two independent ports with sepa-
rate control, address, and I/O pins that permit independent,
asynchronous access for reads or writes to any location in
memory. An automatic power down feature controlled by CS
permits the on-chip circuitry of each port to enter a very low
standby power mode.
•
•
•
Total dose hardness:
- > 100 krad (Si), depending upon space mission
Excellent Single Event Effects:
-SELTH LET = >100 MeV/mg/cm2
-SEUTH LET = 7 MeV/mg/cm2
Package:
-84 Pin RAD-PAK® quad flat pack
Separate upper byte and lower byte control for multiplexed
bus compatibility
•
•
•
•
High speed access time: 35/45 ns
Expandable to 32 bits or more using master/slave select
when cascading
High speed CMOS technology
-TTL compatible, single 5V power supply
-Interrupt flag for port-to-port communication
-On chip port arbitration logic
-Asynchronous operation from either port
Maxwell Technologies' patented RAD-PAK® packaging technol-
ogy incorporates radiation shielding in the microcircuit pack-
age. It eliminates the need for box shielding while providing
the required radiation shielding for a lifetime in orbit or space
mission. In a GEO orbit, RAD-PAK provides greater than 100
krad (Si) radiation dose tolerance. This product is available
with screening up to Class S.
•
08.15.02 Rev 2
1
All data sheets are subject to change without notice
(619) 503-3300- Fax: (619) 503-3301- www.maxwell.com
©2002 Maxwell Technologies
All rights reserved.
(8K x 16-Bit) Dual Port RAM High-Speed CMOS
7025E
TABLE 1. 7025E PINOUT DESCRIPTION
NAMES
LEFT PORT
RIGHT PORT
Chip Select
CSL
R/WL
CSR
R/WR
Read/Write Select
Output Select
Address
OSL
OSR
AOL-A12L
I/OOL-I/O15L
SEML
AOR-A12R
I/OOR-I/O15R
SEMR
Data Input/Output
Semaphore Select
Upper Byte Select
Lower Byte Select
Interrupt Flag
UBL
UBR
LBL
LBR
INTL
INTR
Busy Flag
BUSYL
BUSYR
M/S
VCC
Master or Slave Select
Power
GND
Ground
TABLE 2. 7025E ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
MIN
MAX
UNITS
Supply Voltage (Relative to VSS)
Operating Temperature Range
Input or Output Voltage Applied
Storage Temperature Range
VCC
TA
-0.3
-55
7.0
125
V
°C
V
--
GND -0.3V
-65
V
CC+ 0.3
150
TSTG
°C
TABLE 3. DELTA LIMITS
PARAMETER
VARIATION
ICCOP
ICCOP1
ICCSB
ICCSB1
± 10% AS STATED I TABLE 6
± 10% AS STATED I TABLE 6
± 10% AS STATED I TABLE 6
± 10% AS STATED I TABLE 6
TABLE 4. 7025E RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
MIN
MAX
UNITS
Supply Voltage Positive
Input Voltage
VCC
4.5
5.5
V
V
VIL
VIH
-0.5
2.2
0.8
6.0
08.15.02 Rev 2
All data sheets are subject to change without notice
2
©2002 Maxwell Technologies
All rights reserved.
(8K x 16-Bit) Dual Port RAM High-Speed CMOS
7025E
TABLE 4. 7025E RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
MIN
MAX
UNITS
Thermal Impedance
ΘJC
--
1.02
125
°C/W
°C
Operating Temperature Range
TA
-55
TABLE 5. 7025E CAPACITANCE
PARAMETER
SYMBOL
MIN
MAX
UNITS
Input Capacitance: VIN = 0V1
Output Capacitance: VOUT = 0V1
CIN
--
--
5
7
pF
pF
COUT
1. Guaranteed by design.
TABLE 6. 7025E DC ELECTRICAL CHARACTERISTICS
(VCC = 5V ± 10%, TA = -55 TO 125 °C UNLESS OTHERWISE)
PARAMETER
SYMBOL
SUBGROUPS
MIN
MAX
UNITS
Input Leakage Current 1
Output Leakage Current 2
ILI
ILO
1, 2, 3
1, 2, 3
1, 2, 3
--
--
±10
±10
µA
µA
mA
Standby Supply Current, Both ports TTL level inputs
ICCSB
-35
-45
--
--
50
50
Standby Supply Current, Both ports CMOS level inputs
-35
-45
ICCSB1
1, 2, 3
1, 2, 3
1, 2, 3
mA
mA
mA
--
--
5
5
Operating Supply Current, Both ports Active
-35
-45
ICCOP
--
--
320
280
Operating Supply Current, One Port Active, One Port Standby
ICCOP1
-35
-45
--
--
190
180
Input Low Voltage3
Input High Voltage
Output Low Voltage 4
Output High Voltage
VIL
VIH
1, 2, 3
1, 2, 3
--
2.2
0.8
--
V
V
VOL
VOH
--
2.4
0.4
--
1. VCC = 5.5V, VIN = GND to VCC, CS = VIH, VOUT = 0 to VCC.
2. Vcc=5.5V; Vout = GND to Vcc
3. VIH max = VCC + 0.3V, VIL min = -0.3V or -1V pulse width 50 ns
4. VCC min, IOL = 4 mA, IOH = -4 mA.
08.15.02 Rev 2
All data sheets are subject to change without notice
3
©2002 Maxwell Technologies
All rights reserved.
(8K x 16-Bit) Dual Port RAM High-Speed CMOS
7025E
TABLE 7. 7025E AC ELECTRICAL CHARACTERISTICS FOR READ CYCLE
(VCC = 5V ± 10%, VSS = 0V, TA = -55 TO 125 °C)
PARAMETER
SYMBOL
SUBGROUPS
MIN
MAX
UNIT
Read Cycle Time
-35
-45
tRC
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
ns
35
45
--
--
Address Access Time
-35
-45
tAA
tACS
tABE
tAOE
tLZ
ns
ns
ns
ns
ns
--
--
35
45
Chip Select Access Time 1
-35
-45
--
--
35
45
Byte Select Access Time 1
-35
-45
--
--
35
45
Output Select to Output Valid
-35
-45
--
--
20
25
Output Low Z Time 2,3
-35
-45
3
3
--
--
Output High Z Time 2,3
tHZ
-35
-45
--
--
20
20
ns
Chip Enable to Power Up Time 2
tPU
tPD
9, 10, 11
9, 10, 11
9, 10, 11
0
--
--
50
--
ns
ns
ns
Chip Disable to Power Up Time 2
Semaphore Flag Update Pulse (OE or SEM)
tSOP
15
1. To access RAM, CS = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CS = VIN and SEM = VIL. Either condition must be
valid for the entire tEW time.
2. Guaranteed by design.
3. Transition is measured ± 500 mV from low or high impedance voltage with load.
TABLE 8. 7025E AC ELECTRICAL CHARACTERISTICS FOR WRITE CYCLE
(VCC = 5V ± 10%, VSS = 0V, TA = -55 TO 125 °C)
PARAMETER
SYMBOL
SUBGROUPS
MIN
MAX
UNIT
Write Cycle Time
tWC
9, 10, 11
ns
-35
-45
35
45
--
--
Address Valid to End of Write
tAW
9, 10, 11
ns
-35
-45
30
40
--
--
08.15.02 Rev 2
All data sheets are subject to change without notice
4
©2002 Maxwell Technologies
All rights reserved.
(8K x 16-Bit) Dual Port RAM High-Speed CMOS
7025E
TABLE 8. 7025E AC ELECTRICAL CHARACTERISTICS FOR WRITE CYCLE
(VCC = 5V ± 10%, VSS = 0V, TA = -55 TO 125 °C)
PARAMETER
SYMBOL
SUBGROUPS
MIN
MAX
UNIT
Chip Select to End of Write 1
-35
-45
tSW
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
ns
30
40
--
--
Address Setup Time
-35
-45
tAS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
0
--
--
Write Pulse Width
-35
-45
tWP
30
35
--
--
Write Recovery Time
-35
-45
tWR
tDW
tHZ
0
0
--
--
Data Valid to End of Write
-35
-45
Output High Z Time 2,3
-35
-45
25
25
--
--
--
--
20
20
Data Hold Time
-35
-45
Write Select to Output in High Z 2,3
-35
-45
tDH
0
0
--
--
tWZ
--
--
20
20
2,3,4
Output Active from End of Write
-35
-45
tOW
tSWRD
tSPS
0
0
--
--
SEM Flag Write to Read Time
-35
-45
10
10
--
--
SEM Flag Contention Window
-35
-45
10
10
--
--
1. To access RAM, CS = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CS = VIN and SEM = VIL. Either condition must be
valid for the entire tEW time.
2. Guaranteed by design.
3. Transition is measured ± 500 mV from low or high impedance voltage with load.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH
and tDW
.
08.15.02 Rev 2
All data sheets are subject to change without notice
5
©2002 Maxwell Technologies
All rights reserved.
(8K x 16-Bit) Dual Port RAM High-Speed CMOS
7025E
TABLE 9. 7025E AC ELECTRICAL CHARACTERISTICS FOR WRITE MASTER/SLAVE CONFIGURATION
(VCC = 5V ± 10%, VSS = 0V, TA = -55 TO 125 °C)
PARAMETER
SYMBOL
MIN
MAX
UNIT
For Master Only
BUSY Access Time to Address Match
tBAA
ns
-35
-45
--
--
35
35
BUSY Disable Time to Address Not Matched
-35
-45
tBDA
tBAC
tBDC
tWDD
tDDD
tAPS
tBDD
ns
ns
ns
ns
ns
ns
ns
--
--
30
30
BUSY Access Time to Chip Select Low
-35
-45
--
--
30
30
BUSY Disable Time to Chip Select High
-35
-45
Write Pulse to Data Delay 1
-35
-45
Write Data Valid to Read Data Delay 1
-35
-45
Arbitration Priority Setup Time 2
-35
-45
--
--
25
25
--
--
60
70
--
--
45
55
5
5
--
--
BUSY Disable to Valid Data
-35
-45
3
3
--
--
For Slave Only
Write to BUSY Input 4
Write Hold after BUSY 5
Write Pulse to Data Delay 1
tWB
tWH
0
--
--
ns
ns
ns
25
tWDD
-35
-45
--
--
60
70
Write Data Valid to Read Data Delay 1
tDDD
ns
-35
-45
--
--
45
55
1. Port to port timing delay through RAM cells from writing port to reading port.
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD - tWP (actual) or tDDD - tWD (actual).
4. To ensure that the write cycle is inhibited during contention.
5. To ensure that a write cycle is completed after contention.
08.15.02 Rev 2
All data sheets are subject to change without notice
6
©2002 Maxwell Technologies
All rights reserved.
(8K x 16-Bit) Dual Port RAM High-Speed CMOS
7025E
TABLE 10. 7025E AC PARAMETERS FOR INTERRUPT TIMING
(VCC = 5V ± 10%, TA = -55 TO 125 °C, f = 1 MHZ)
PARAMETER
SYMBOL
MIN
MAX
UNITS
Address Setup Time
Write Recovery Time
tAS
tWR
tINS
0
0
--
--
ns
ns
ns
Interrupt Set Time
-35
-45
--
--
30
35
Interrupt Reset Time
tINR
ns
-35
-45
--
--
30
35
1
TABLE 11. 7025E TRUTH TABLE FOR INTERRUPT FLAG CONTROL
A0-A12
FUNCTION
R/W
CS
OS
INT
Left Port
Set right INTL flag
Reset right INTL flag
Set left INTL flag
Reset left INTL flag
Right Port
L
X
X
X
L
X
X
L
X
X
X
L
1FFF
X
X
X
X
L 2
H 3
1FFE
Set right INTR flag
Reset right INTR flag
Set left INTR flag
Reset left INTR flag
X
X
L
X
L
L
X
X
L
X
L 3
H 2
X
1FFF
1FFE
X
X
X
X
X
1. Assumes BUSYL = BUSYR = H.
2. If BUSYR = L, then no change.
3. If BUSYL = L, then no change.
08.15.02 Rev 2
All data sheets are subject to change without notice
7
©2002 Maxwell Technologies
All rights reserved.
(8K x 16-Bit) Dual Port RAM High-Speed CMOS
7025E
TABLE 12. 7025E TRUTH TABLE FOR ARBITRATION OPTIONS
OPTIONS
INPUTS
OUTPUTS
CS
UB
LB
M/S
SEM
BUSY
INT
--
Busy Logic Master
Busy Logic Slave
Interrupt Logic
L
L
X
L
L
X
H
H
H
H
Output Signal
L
L
X
L
L
X
L
L
H
H
Input Signal
--
--
L
L
X
L
L
X
X
X
H
H
Output Signal
--
Semaphore Logic
H
H
X
X
X
X
H
L
L
L
H
HI-Z
TABLE 13. 7025E NON-CONTENTION READ/WRITE CONTROL
1
MODE
OUTPUTS
INPUTS
CS
R/W
OE
UB
LB
SEM
I/O8-I/O15
I/O0-I/O7
H
X
X
X
X
X
X
H
X
H
H
H
HI-Z
HI-Z
HI-Z
HI-Z
Deselected power down
Both bytes deselected:
Power down
L
L
L
L
L
L
X
L
L
X
X
X
L
L
H
L
H
L
H
H
H
H
H
H
X
DATAIN
HI-Z
HI-Z
DATAIN
DATAIN
HI-Z
Write to upper byte only
Write to lower byte only
Write to both bytes
L
L
DATAIN
DATAOUT
HI-Z
H
H
H
X
L
H
L
Read upper byte only
L
H
L
DATAOUT Read lower byte only
DATAOUT Read both bytes
L
L
DATAOUT
HI-Z
H
X
X
HI-Z
Outputs disabled
1. AOL - A12L = AOR-A12R.
08.15.02 Rev 2
All data sheets are subject to change without notice
8
©2002 Maxwell Technologies
All rights reserved.
(8K x 16-Bit) Dual Port RAM High-Speed CMOS
7025E
1
TABLE 14. 7025E SEMAPHORE READ/WRITE CONTROL
INPUTS
OUTPUTS
MODE
CS
H
R/W
H
OE
L
UB
X
LB
X
SEM
L
I/O8-I/O15
DATAOUT
I/O0-I/O7
DATAOUT Read data in semaphore
flag
X
H
X
H
L
X
X
H
X
H
H
X
H
L
L
L
DATAOUT
DATAIN
DATAOUT Read data in semaphore
flag
DATAIN
Write DinO into semaphore
flagf
DATAIN
DATAIN
Write DinO into semaphore
flag
L
L
X
X
X
X
L
X
L
L
L
--
--
--
--
Not allowed
Not allowed
X
1. AOL - A12L = AOR-A12R.
08.15.02 Rev 2
All data sheets are subject to change without notice
9
©2002 Maxwell Technologies
All rights reserved.
(8K x 16-Bit) Dual Port RAM High-Speed CMOS
7025E
1,2,3
FIGURE 1. TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE
1,4,5
FIGURE 2. TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE
1. F/W is high for read cycles.
2. Device is continuously enabled, CS = VIL, UB or LB = VL. This waveform cannot be used for semaphore reads.
3. CE = VIL.
4. Addresses valid prior to or coincident with CS transition.
5. To access RAM, CS = VL, UB or LB = VIL, SEM = VIH. To access semaphore, CS = VIH, SEM = VIL.
08.15.02 Rev 2
All data sheets are subject to change without notice 10
©2002 Maxwell Technologies
All rights reserved.
(8K x 16-Bit) Dual Port RAM High-Speed CMOS
7025E
1,3,4,5
FIGURE 3. TIMING WAVEFORM OF READ CYCLE NO. 3, EITHER SIDE
FIGURE 4. TIMING WAVEFORM OF READ WITH BUSY 2,3,4 (FOR MASTER)
1. To ensure math, the earlier of the two ports wins.
2. Write cycle parameters should be adhered to, to ensure proper writing.
3. Device is continuously enable for both ports.
4. OE = L for the reading port.
08.15.02 Rev 2
All data sheets are subject to change without notice 11
©2002 Maxwell Technologies
All rights reserved.
(8K x 16-Bit) Dual Port RAM High-Speed CMOS
7025E
FIGURE 5. TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT 1,2,3 (FOR SLAVE ONLY)
1. Assume BUSY Input = H or the writing port, and OE = L for the reading port.
2. Write cycle parameters should be adhered to, to ensure proper writing.
3. Device is continuously enable for both ports.
1,2,3,7
FIGURE 6. TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/W CONTROLLED TIMING
08.15.02 Rev 2
All data sheets are subject to change without notice 12
©2002 Maxwell Technologies
All rights reserved.
(8K x 16-Bit) Dual Port RAM High-Speed CMOS
7025E
1,2,3,5
FIGURE 7. TIMING WAVEFORM OF WRITE CYCLE NO. 2, CS CONTROLLED TIMING
FIGURE 8. TIMING WAVEFORM OF WRITE WITH BUSY (FOR SLAVE)
1. R/W must be high during all address transitions.
2. A write occurs during the overlap (tSW to tWF) of a low CS or SEM and a low R/W.
3. T.WF is measured from the earlier of CS or R/W (or SEM or R/W) going high to the end of write cycle.
4. During this period, the I/O pins are in the output state, and input signals must not be applied.
5. If the CS or SEM low transition occurs simultaneously with or after the R/W low transition, the outputs remain in the
high impedance state.
6. Transitions measured = 500 mV from steady state with a 5 pF load (including scope and jig). This parameter is sam-
ple and not 100% tested.
7. If OE is low during a R/W controlled write cycle, the write pulse width must be the larger of two or (tWZ +tDW) to allow
the I/O driver to turn off and data to be placed on the bus for the required tDW. If OE is high during an R/W controlled
write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP
.
8. To access RAM, CS = VIL, SEM = VIH.
9. To access upper byte, CS = VIL, UB = VIL, SEM = VIH.
To access lower byte, CS = VIL, LB = VIL, SEM = VIH.
08.15.02 Rev 2
All data sheets are subject to change without notice 13
©2002 Maxwell Technologies
All rights reserved.
(8K x 16-Bit) Dual Port RAM High-Speed CMOS
7025E
FIGURE 9. TIMING WAVEFORM OF CONTENTION CYCLE NO. 1, CS ARBITRATION (FOR MASTER)
FIGURE 10. TIMING WAVEFORM OF CONTENTION CYCLE NO. 2, ADDRESS VALID ARBITRATION (FOR MASTER
ONLY) 1
LEFT ADDRESS VALID FIRST
08.15.02 Rev 2
All data sheets are subject to change without notice 14
©2002 Maxwell Technologies
All rights reserved.
(8K x 16-Bit) Dual Port RAM High-Speed CMOS
7025E
RIGHT ADDRESS VALID FIRST
1. CSL = CSR = VIL.
1
FIGURE 11. WAVEFORM OF INTERRUPT TIMING
SET ADDRESS
CLEAR ADDRESS
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite
from “A”.
2. See interrupt truth table.
3. Timing depends on which enable signal is asserted last.
4. Timing depends on which enable signal is de-asserted first.
08.15.02 Rev 2
All data sheets are subject to change without notice 15
©2002 Maxwell Technologies
All rights reserved.
(8K x 16-Bit) Dual Port RAM High-Speed CMOS
7025E
FIGURE 12. 32-BIT MASTER/SLAVE DUAL-PORT MEMORY SYSTEMS
1. No arbitration in Master/Slave. BUSY - IN inhibits write in Master/Slave.
1
FIGURE 13. TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE
1. CS = VIH for the duration of the above timing (both write and read cycle).
08.15.02 Rev 2
All data sheets are subject to change without notice 16
©2002 Maxwell Technologies
All rights reserved.
(8K x 16-Bit) Dual Port RAM High-Speed CMOS
7025E
1,3,4
FIGURE 14. TIMING WAVEFORM OF SEMAPHORE CONTENTION
1. DOR = DOL = VIL, CSR = CSL = VIH, semaphore Flag is released from both sides (reads as ones from both sides) at
cycle start.
2. Either side “A” = left and side “B” = right, or side “A” = right and side “B” = left.
3. This parameter is measured from the point where R/WA or SEMA goes high until R/WB or SEMB goes high.
4. If tSPS is violated, the semaphore will fall positively to one side or the other, but there is no guaranty which side will
obtain the flag.
08.15.02 Rev 2
All data sheets are subject to change without notice 17
©2002 Maxwell Technologies
All rights reserved.
(8K x 16-Bit) Dual Port RAM High-Speed CMOS
7025E
84 PIN RAD-PAK® FLAT PACKAGE
SYMBOL
DIMENSION
MIN
NOM
MAX
A
A1
b
0.163
0.113
0.006
0.004
0.635
0.176
0.123
0.189
0.133
0.014
0.010
0.665
0.010
c
0.006
D
0.650
D1
e
0.500 BSC
0.025 BSC
0.070
S1
F1
F2
F3
F4
L
0.013
0.540
0.415
0.412
0.560
--
--
0.545
0.550
0.425
0.418
0.570
1.635
1.615
0.960
0.420
0.415
0.565
1.620
L1
L2
N
1.595
0.940
1.600
0.950
84
08.15.02 Rev 2
All data sheets are subject to change without notice 18
©2002 Maxwell Technologies
All rights reserved.
(8K x 16-Bit) Dual Port RAM High-Speed CMOS
7025E
Q84-01
Note: All dimensions in inches
Important Notice:
These data sheets are created using the chip manufacturers published specifications. Maxwell Technologies verifies
functionality by testing key parameters either by 100% testing, sample testing or characterization.
The specifications presented within these data sheets represent the latest and most accurate information available to
date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no
responsibility for the use of this information.
Maxwell Technologies’ products are not authorized for use as critical components in life support devices or systems
without express written approval from Maxwell Technologies.
Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Tech-
nologies. Maxwell Technologies’ liability shall be limited to replacement of defective parts.
08.15.02 Rev 2
All data sheets are subject to change without notice 19
©2002 Maxwell Technologies
All rights reserved.
(8K x 16-Bit) Dual Port RAM High-Speed CMOS
7025E
Product Ordering Options
Model Number
7025E
RP
Q
X
-XX
Option Details
Feature
Access Time
35 = 35 ns
45 = 45 ns
Monolithic
Screening Flow
S = Maxwell Class S
B = Maxwell Class B
I = Industrial (testing @ -55°C,
+25°C, +125°C)
E = Engineering (testing @ +25°C)
Q = Quad Flat Pack
Package
RP = RAD-PAK® package
Radiation Feature
(8K x 16-Bit) Dual Port RAM High-
Speed CMOS
Base Product
Nomenclature
08.15.02 Rev 2
All data sheets are subject to change without notice 20
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