33C408RTFS-30 [MAXWELL]
4 Megabit (512K x 8-Bit) CMOS SRAM; 4兆位（ 512K ×8位） CMOS SRAM
| 型号： | 33C408RTFS-30 |
| 厂家： | 
MAXWELL TECHNOLOGIES |
| 描述： | 4 Megabit (512K x 8-Bit) CMOS SRAM |
| 文件： | 总12页 (文件大小：233K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
33C408
4 Megabit (512K x 8-Bit)
CMOS SRAM
Logic Diagram
FEATURES:
DESCRIPTION:
• RAD-PAK® Technology radiation-hardened
against natural space radiation
• 524,288 x 8 bit organization
Maxwell Technologies’ 33C408 high-density 4
Megabit SRAM microcircuit features a greater than
100 krad (Si) total dose tolerance, depending upon
space mission. Using Maxwell’s radiation-hard-
ened RAD-PAK® packaging technology, the 33C408
realizes a high density, high performance, and low
power consumption. Its fully static design elimi-
nates the need for external clocks, while the
CMOS circuitry reduces power consumption and
provides higher reliability. The 33C408 is equipped
with eight common input/output lines, chip select
and output enable, allowing for greater system flex-
ibility and eliminating bus contention. The 33C408
features the same advanced 512K x 8-bit SRAM,
high-speed, and low-power demand as the com-
mercial counterpart.
· Total dose hardness:
- > 100 krad (Si), depending upon space mis-
sion
• Excellent Single Event Effect
· - SELTH: > 68 MeV/mg/cm2
· - SEUTH: = 3 MeV/mg/cm2
- SEU saturated cross section: 6E-9 cm2/bit
• Package:
- 32-Pin RAD-PAK® flat pack
- 32-Pin Non-RAD-PAK® flat pack
• Fast access time:
- 20, 25, 30 ns maximum times available
• Single 5V + 10% power supply
• Fully static operation
Maxwell Technologies' patented RAD-PAK packag-
ing technology incorporates radiation shielding in
the microcircuit package. It eliminates the need for
box shielding while providing the required radiation
shielding for a lifetime in orbit or space mission. In
a GEO orbit, RAD-PAK provides greater than 100
krad (Si) radiation dose tolerance. This product is
available with screening up to Class S.
- No clock or refresh required
• Three state outputs
• TTL compatible inputs and outputs
• Low power:
- Standby: 60 mA (TTL); 10 mA (CMOS)
- Operation: 180 mA (20 ns); 170 mA (25 ns);
160 mA (30 ns)
04.16.02 REV 8
1
All data sheets are subject to change without notice
(858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com
©2002 Maxwell Technologies
All rights reserved.
33C408
4 Megabit (512K x 8-Bit) CMOS SRAM
TABLE 1. PINOUT DESCRIPTION
PIN
SYMBOL
DESCRIPTION
12-5, 27, 26, 23, 25, 4,
28, 3, 31, 2, 30, 1
A0-A18
Address Inputs
29
WE
CS
Write Enable
Chip Select
22
24
OE
Output Enable
13-15, 17-21
I/O 1-I/O 8 Data Inputs/Outputs
32
16
V
Power (+5.0V)
Ground
CC
V
SS
TABLE 2. 33C408 ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
MIN
MAX
UNIT
Voltage on VCC supply relative to V
V
-0.5
-0.5
--
7.0
V
SS
CC
Voltage on any pin relative to V
V , V
V +0.5
V
W
°C
°C
SS
IN OUT
CC
Power Dissipation
PD
TS
1.0
Storage Temperature
Operating Temperature
-65
-55
+150
+125
T
A
TABLE 3. DELTA LIMITS
PARAMETER
VARIATION
ICC1
ISB
ISB1
ILI
±10% of stated vaule in Table 6
±10% of stated vaule in Table 6
±10% of stated vaule in Table 6
±10% of stated vaule in Table 6
04.16.02 REV 8
All data sheets are subject to change without notice
2
©2002 Maxwell Technologies
All rights reserved.
33C408
4 Megabit (512K x 8-Bit) CMOS SRAM
TABLE 4. 33C408 RECOMMENDED OPERATING CONDITIONS
(VCC = 5.0 + 10%, TA = -55 TO +125 °C, UNLESS OTHERWISE NOTED)
PARAMETER
SYMBOL
MIN
MAX
UNIT
Supply Voltage
Ground
V
4.5
0
5.5
0
V
V
CC
V
SS
Input High Voltage 1
Input Low Voltage 2
Thermal Impedance
V
2.2
-0.5
--
V +0.5
V
V
IH
CC
V
0.8
IL
ΘJC
1.21
°C/W
1. V (max) = VCC +2.0V ac (pulse width < 10 ns) for I < 20 mA
IH
2. V (min) = -2.0V ac(pulse width < 10 ns) for I < 20 mA
IL
TABLE 5. 33C408 DC ELECTRICAL CHARACTERISTICS
(VCC = 5V + 10%, TA = -55 TO +125 °C, UNLESS OTHERWISE SPECIFIED)
PARAMETER
SYMBOL
CONDITION
SUBGROUPS
MIN
MAX
UNIT
Input Leakage Current
Output Leakage Current
ILI
V = V to V
CC
1, 2, 3
1, 2, 3
-2
-2
2
2
µA
µA
IN
SS
ILO
CS=V or OE=V or WE=V ,
IH IH IL
V
OUT =V to V
SS CC
Output Low Voltage
Output High Voltage
V
IOL = 8mA
1, 2, 3
1, 2, 3
1, 2, 3
--
0.4
--
V
V
OL
V
IOH = -4mA
2.4
OH
Operating Current
ICC
Min cycle, 100% Duty, CS=V , IOUT=0mA,
mA
IL
-20
-25
-30
V = V or V
--
--
--
180
170
160
IN
IH
IL
Standby Power
Supply Current
ISB
CS = V , Min Cycle
1, 2, 3
1, 2, 3
--
60
mA
mA
IH
CMOS Standby Power
Supply Current
ISB1
CS > V - 0.2V, f = 0 MHz, V > V - 0.2V
--
10
CC
IN
CC
or
IN < 0.2V
V
Input Capacitance 1
Output Capacitance 1
C
V = 0V, f = 1MHz, T = 25 °C
1, 2, 3
4, 5, 6
--
--
7
8
pF
pF
IN
IN
A
C
V = 0V
I/O
I/O
1. Guaranteed by design.
TABLE 6. 33C408 AC TEST CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 + 10%, TA = -55 TO +125 °C, UNLESS OTHERWISE NOTED)
PARAMETER
MIN
TYP
MAX
UNITS
Input Pulse Level
0.0
--
--
--
3.0
1.5
V
V
Output Timing Measurement Reference Level
04.16.02 REV 8
All data sheets are subject to change without notice
3
©2002 Maxwell Technologies
All rights reserved.
33C408
4 Megabit (512K x 8-Bit) CMOS SRAM
TABLE 6. 33C408 AC TEST CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 + 10%, TA = -55 TO +125 °C, UNLESS OTHERWISE NOTED)
PARAMETER
MIN
TYP
MAX
UNITS
Input Rise/Fall Time
--
--
--
--
3.0
1.5
ns
V
Input Timing Measurement Reference Level
TABLE 7. 33C408 AC CHARACTERISTICS FOR READ CYCLE
(VCC = 5V + 10%, TA = -55 TO +125 °C, UNLESS OTHERWISE SPECIFIED)
PARAMETER
SYMBOL
SUBGROUPS
MIN
TYP
MAX
UNIT
Read Cycle Time
tRC
9, 10, 11
ns
-20
-25
-30
20
25
30
--
--
--
--
--
--
Address Access Time
tAA
tCO
tOE
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
ns
ns
-20
-25
-30
--
--
--
--
--
--
20
25
30
Chip Select Access Time
-20
-25
-30
--
--
--
--
--
--
20
25
30
Output Enable to Output Valid
-20
-25
-30
--
--
--
--
--
--
10
12
14
ns
ns
Chip Enable to Output in Low-Z
tLZ
-20
-25
-30
--
--
--
3
3
3
--
--
--
Output Enable to Output in Low-Z
tOLZ
ns
ns
ns
ns
-20
-25
-30
--
--
--
0
0
0
--
--
--
Chip Deselect to Output in High-Z
tHZ
-20
-25
-30
--
--
--
5
6
8
--
--
--
Output Disable to Output in High-Z
tOHZ
-20
-25
-30
--
--
--
5
6
8
--
--
--
Output Hold from Address Change
tOH
-20
-25
-30
3
5
6
--
--
--
--
--
--
04.16.02 REV 8
All data sheets are subject to change without notice
4
©2002 Maxwell Technologies
All rights reserved.
33C408
4 Megabit (512K x 8-Bit) CMOS SRAM
TABLE 7. 33C408 AC CHARACTERISTICS FOR READ CYCLE
(VCC = 5V + 10%, TA = -55 TO +125 °C, UNLESS OTHERWISE SPECIFIED)
PARAMETER
SYMBOL
SUBGROUPS
MIN
TYP
MAX
UNIT
Chip Select to Power Up Time
tPU
9, 10, 11
ns
-20
-25
-30
--
--
--
0
0
0
--
--
--
Chip Select to Power Down Time
tPD
9, 10, 11
ns
-20
-25
-30
--
--
--
10
15
20
--
--
--
TABLE 8. 33C408 FUNCTIONAL DESCRIPTION
CS
WE
OE
MODE
I/O PIN
SUPPLY CURRENT
1
1
H
L
L
L
X
X
Not Select
Output Disable
Read
High-Z
High-Z
DOUT
ISB, ISB1
ICC
H
H
L
H
L
ICC
1
X
Write
D
ICC
IN
1. X = don’t care.
Subgroups
TABLE 9. 33C408 AC CHARACTERISTICS FOR WRITE CYCLE
(VCC = 5V + 10%, TA = -55 TO +125 °C, UNLESS OTHERWISE SPECIFIED)
PARAMETER
SUBGROUPS
SYMBOL
MIN
TYP
MAX
UNIT
Write Cycle Time
9, 10, 11
tWC
ns
-20
-25
-30
20
25
30
--
--
--
--
--
--
Chip Select to End of Write
9, 10, 11
9, 10, 11
9, 10, 11
tCW
ns
ns
ns
-20
-25
-30
14
15
17
--
--
--
--
--
--
Address Setup Time
tAS
-20
-25
-30
0
0
0
--
--
--
--
--
--
Address Valid to End of Write
tAW
-20
-25
-30
14
15
17
--
--
--
--
--
--
04.16.02 REV 8
All data sheets are subject to change without notice
5
©2002 Maxwell Technologies
All rights reserved.
33C408
4 Megabit (512K x 8-Bit) CMOS SRAM
TABLE 9. 33C408 AC CHARACTERISTICS FOR WRITE CYCLE
(VCC = 5V + 10%, TA = -55 TO +125 °C, UNLESS OTHERWISE SPECIFIED)
PARAMETER
SUBGROUPS
SYMBOL
MIN
TYP
MAX
UNIT
Write Pulse Width (OE High)
9, 10, 11
tWP
ns
-20
-25
-30
14
15
17
--
--
--
--
--
--
Write Recovery Time
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
tWR
tWHZ
tWP1
tDW
tOW
tDH
ns
ns
ns
ns
ns
ns
-20
-25
-30
0
0
0
--
--
--
--
--
--
Write to Output in High-Z
-20
-25
-30
--
--
--
5
5
6
--
--
--
Write Pulse Width (OE Low)
-20
-25
-30
--
--
--
20
25
30
--
--
--
Data to Write Time Overlap
-20
-25
-30
9
10
11
--
--
--
--
--
--
End Write to Output Low-Z
-20
-25
-30
--
--
--
6
7
8
--
--
--
Data Hold from Write Time
-20
-25
-30
0
0
0
--
--
--
--
--
--
04.16.02 REV 8
All data sheets are subject to change without notice
6
©2002 Maxwell Technologies
All rights reserved.
33C408
4 Megabit (512K x 8-Bit) CMOS SRAM
FIGURE 1. AC TEST LOADTIMING WAVEFORM OF READ CYCLE(1)
FIGURE 2. TIMING WAVEFORM OF READ CYCLE (2)
Read Cycle Notes:
1. WE is high for read cycle.
2. All read cycle timing is referenced form the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not
referenced to VOH or VOL levels.
4. At any given temperature and voltage condition, tHZ(max) is less than tLZ(min) both for a given device and
from device to device.
5. Transition is measured + 200mV from steady state voltage. This parameter is sampled and not 100%
tested.
6. Device is continuously selected with CS = VIL.
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention condition is necessary dur-
ing read and write cycle.
04.16.02 REV 8
All data sheets are subject to change without notice
7
©2002 Maxwell Technologies
All rights reserved.
33C408
4 Megabit (512K x 8-Bit) CMOS SRAM
FIGURE 3. TIMING WAVEFORM OF WRITE CYCLE(1)
FIGURE 4. TIMING WAVEFORM OF WRITE CYCLE(2)
FIGURE 5. TIMING WAVEFORM OF WRITE CYCLE (3)
04.16.02 REV 8
All data sheets are subject to change without notice
8
©2002 Maxwell Technologies
All rights reserved.
33C408
4 Megabit (512K x 8-Bit) CMOS SRAM
WRITE CYCLE NOTE:
1.
2.
All write cycle timing is referenced from the last valid address to the first transition address.
A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition
among CS going low and WE going low: A write ends at the earliest transition among CS going high
and WE going high. tWP is measured from beginning of write to the end of write.
tCW is measured from the later of CS going low to end of write.
3.
4.
5.
tAS is measured from the address valid to the beginning of write.
tWR is measured form the end of write to the address change. TWR applied in case a write ends as CS,
or WR going high.
6.
7.
8.
9.
If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state.
Inputs of opposite phase of the output must not be applied because bus contention can occur.
For common I/O applications, minimization or elimination of bus contention conditions is necessary
during read and write cycle.
IC CS goes low simultaneously with WE going low or after WE going low, the outputs remain high
impedance state.
DOUT is the read data of the new address.
10. When CS is low: I/O pins are in the output state. The input signals in the opposite phase leading
to the output should not be applied.
04.16.02 REV 8
All data sheets are subject to change without notice
9
©2002 Maxwell Technologies
All rights reserved.
33C408
4 Megabit (512K x 8-Bit) CMOS SRAM
32 PIN RAD-PAK® FLAT PACKAGE
DIMENSION
SYMBOL
MIN
NOM
MAX
A
b
0.120
0.013
0.008
--
0.135
0.015
0.010
0.930
0.645
--
0.155
0.020
0.012
0.940
0.655
0.690
--
c
D
E
0.635
--
E1
E2
E3
e
0.550
0.030
0.565
0.040
0.050 BSC
0.400
0.098
0.082
32
--
L
0.390
0.026
0.005
0.410
--
Q
S1
N
--
F32-06
Note: All dimensions in inchesImportant Notice:
04.16.02 REV 8
All data sheets are subject to change without notice 10
©2002 Maxwell Technologies
All rights reserved.
33C408
4 Megabit (512K x 8-Bit) CMOS SRAM
These data sheets are created using the chip manufacturers published specifications. Maxwell
Technologies verifies functionality by testing key parameters either by 100% testing, sample test-
ing or characterization.
The specifications presented within these data sheets represent the latest and most accurate
information available to date. However, these specifications are subject to change without notice
and Maxwell Technologies assumes no responsibility for the use of this information.
Maxwell Technologies’ products are not authorized for use as critical components in life support
devices or systems without express written approval from Maxwell Technologies.
Any claim against Maxwell Technologies must be made within 90 days from the date of shipment
from Maxwell Technologies. Maxwell Technologies’ liability shall be limited to replacement of
defective parts.
04.16.02 REV 8
All data sheets are subject to change without notice 11
©2002 Maxwell Technologies
All rights reserved.
33C408
4 Megabit (512K x 8-Bit) CMOS SRAM
Product Ordering Options
Model Number
33C408
XX
F
X
-XX
Option Details
20 = 20 ns
Feature
Access Time
25 = 25 ns
30 = 30 ns
Monolithic
Screening Flow
S = Maxwell Class S
B = Maxwell Class B
E = Engineering (testing @ +25°C)
I = Industrial (testing @ -55°C,
+25°C, +125°C)
F = Flat Pack
Package
RP = RAD-PAK® package
RT = Non-RAD-PAK® package
Radiation Feature
4 Megabit CMOS SRAM
Base Product
Nomenclature
04.16.02 REV 8
All data sheets are subject to change without notice 12
©2002 Maxwell Technologies
All rights reserved.
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