MX7705EUE+ [MAXIM]
16-Bit, Low-Power, 2-Channel, Sigma-Delta ADC; 16位，低功耗， 2通道， Σ-Δ ADC
| 型号： | MX7705EUE+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 16-Bit, Low-Power, 2-Channel, Sigma-Delta ADC |
| 文件： | 总33页 (文件大小：451K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3051; Rev 4; 2/10
16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADC
MX705
General Description
Features
The MX7705 low-power, 2-channel, serial-output ana-
log-to-digital converter (ADC) includes a sigma-delta
modulator with a digital filter to achieve 16-bit resolution
with no missing codes. This ADC is pin compatible and
software compatible with the AD7705. The MX7705 fea-
tures an on-chip input buffer and programmable-gain
amplifier (PGA). The device offers an SPI™-/QSPI™-/
MICROWIRE™-compatible serial interface.
The MX7705 operates from a single 2.7V to 5.25V supply.
The operating supply current is 320µA (typ) with a 3V
supply. Power-down mode reduces the supply current to
2µA (typ).
o Pin Compatible and Software Compatible with the
AD7705
o 16-Bit Sigma-Delta ADC
o Two Fully Differential Input Channels
o 0.003% Integral Nonlinearity with No Missing Codes
o Interface with Schmitt Triggers on Inputs
o Internal Analog Input Buffers
o PGA from 1 to 128
o Single (2.7V to 3.6V) or (4.75V to 5.25V) Supply
Self-calibration and system calibration allow the MX7705
to correct for gain and offset errors. Excellent DC perfor-
mance ( 0.003ꢀ ꢁSR IꢂN) and low noise (650nV) maꢃe
the MX7705 ideal for measuring low-frequency signals
with a wide dynamic range. The device accepts fully dif-
ferential bipolar/unipolar inputs. An internal input buffer
allows for input signals with high source impedances. An
on-chip digital filter, with a programmable cutoff and out-
put data rate, processes the output of the sigma-delta
modulator. The first notch frequency of the digital filter is
chosen to provide 150dB rejection of common-mode
50Hz or 60Hz noise and 98dB rejection of normal-mode
50Hz or 60Hz noise. A PGA and digital filtering allow sig-
nals to be directly acquired with little or no signal-condi-
tioning requirements.
o Low Power
1mW (max), 3V Supply
2μA (typ) Power-Down Current
o SPI-/QSPI-/MICROWIRE-Compatible 3-Wire Serial
Interface
Ordering Information
PART
TEMP RANGE
PIN- PACKAGE
MX7705EUE+
-40°C to +85°C
16 TSSOP
+Denotes a lead(Pb)-free/RoHS-compliant pacꢃage.
The MX7705 is available in a 16-pin TSSOP pacꢃage.
Applications
Pin Configuration
Industrial Instruments
Weigh Scales
TOP VIEW
Strain-Gauge Measurements
Noop-Powered Systems
ꢁlow and Gas Meters
Medical Instrumentation
Pressure Transducers
Thermocouple Measurements
RTD Measurements
SCLK
1
2
3
4
5
6
7
8
16 GND
15
CLKIN
V
DD
CLKOUT
CS
14 DIN
MX7705
13 DOUT
12 DRDY
11 AIN2-
10 REF-
RESET
AIN2+
AIN1+
AIN1-
9
REF+
TSSOP
SPI/QSPI are trademarꢃs of Motorola, Inc.
MICROWIRE is a trademarꢃ of ꢂational Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADC
ABSOLUTE MAXIMUM RATINGS
V
DD
to GND..............................................................-0.3V to +6V
Operating Temperature Range ..........................-40°C to +85°C
Storage Temperature Range.............................-60°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
All Other Pins to GND.................................-0.3V to (V
Maximum Current Input into Any Pin ..................................50mA
+ 0.3V)
DD
Continuous Power Dissipation (T = +70°C)
A
TSSOP (derate 9.4mW/°C above +70°C) ....................755mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
MX705
ELECTRICAL CHARACTERISTICS
(V
= 3V or 5V, GND = 0, V
= 1.225V for V
= 3V and V
= 2.5V for V
= 5V, V
= GND, external f
=
CLKIN
DD
REF+
DD
REF+
DD
REF-
2.4576MHz, CLKDIV bit = 0, C
to GND = 0.1µF, C
- to GND = 0.1µF, T = T
to T
, unless otherwise noted.)
MAX
REF+
REF
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY
Resolution (No Missing Codes)
Output Noise
16
Bits
µV
Tables 1, 3
Integral Nonlinearity
Unipolar Offset Error
Unipolar Offset Drift
Bipolar Zero Error
INL
Gain = 1, unbuffered
After calibration
(Note 2)
0.003 %FSR
(Note 1)
0.5
µV
µV/°C
µV
After calibration
Gain = 1 to 4
(Note 1)
0.5
Bipolar Zero Drift (Note 2)
µV/°C
Gain = 8 to 128
After calibration
(Notes 2, 4)
0.1
Positive Full-Scale Error
Full-Scale Drift
(Notes 1, 3)
0.5
µV
µV/°C
µV
Gain Error
After calibration
(Notes 1, 5)
ppm of
FSR/°C
Gain Drift
(Notes 2, 6)
0.5
Bipolar Negative Full-Scale Error
After calibration
Gain = 1 to 4
0.003
1
%FSR
Bipolar Negative Full-Scale Drift
(Note 2)
µV/°C
Gain = 8 to 128
0.6
ANALOG INPUTS (AIN1+, AIN1-, AIN2+, AIN2-)
V
GAIN
/
REF
Unipolar input range
Bipolar input range
Unbuffered
0
AIN Differential Input Voltage
Range (Note 7)
V
-V
/
V
GAIN
/
REF
REF
GAIN
GND -
30mV
V
+
DD
30mV
AIN Absolute Input Voltage
Range (Note 8)
V
GND +
50mV
V
1.5V
-
DD
Buffered
AIN DC Leakage Current
Unselected input channel
1
nA
2
_______________________________________________________________________________________
16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADC
MX705
ELECTRICAL CHARACTERISTICS (continued)
(V
= 3V or 5V, GND = 0, V
= 1.225V for V
= 3V and V
= 2.5V for V
= 5V, V
= GND, external f
=
DD
REF+
DD
REF+
DD
REF-
CLKIN
2.4576MHz, CLKDIV bit = 0, C
to GND = 0.1µF, C
- to GND = 0.1µF, T = T
to T
, unless otherwise noted.)
REF+
REF
A
MIN
MAX
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
34
MAX
UNITS
Gain = 1
Gain = 2
Gain = 4
38
AIN Input Capacitance
AIN Input Sampling Rate
pF
45
Gain = 8 to 128
60
f
/
CLKIN
64
f
Gain = 1 to 128
MHz
s
Gain = 1
Gain = 2
Gain = 4
96
105
110
130
105
110
120
130
V
V
= 5V
= 3V
DD
DD
Gain = 8 to 128
Gain = 1
Input Common-Mode Rejection
CMR
dB
Gain = 2
Gain = 4
Gain = 8 to 128
For filter notches of 25Hz, 50Hz,
0.02 × f
Normal-Mode 50Hz Rejection
Normal-Mode 60Hz Rejection
Common-Mode 50Hz Rejection
Common-Mode 60Hz Rejection
98
98
dB
dB
dB
dB
NOTCH
For filter notches of 20Hz, 60Hz,
0.02 × f
NOTCH
For filter notches of 25Hz, 50Hz,
0.02 × f
150
150
NOTCH
For filter notches of 20Hz, 60Hz,
0.02 × f
NOTCH
EXTERNAL REFERENCE (REF+, REF-)
V
V
= 4.75V to 5.25V
= 2.7V to 3.6V
1.0
1.00
GND
3.5
DD
DD
REF Differential Input Voltage
Range (Note 9)
V
V
REF
1.75
REF Absolute Input Voltage Range
REF Input Capacitance
V
V
DD
Gain = 1 to 128
10
pF
f
/
CLKIN
64
REF Input Sampling Rate
f
MHz
s
DIGITAL INPUTS (DIN, SCLK, CS, RESET)
Input High Voltage
V
2
V
V
IH
V
V
= 4.75V to 5.25V
= 2.7V to 3.6V
0.8
0.4
DD
DD
Input Low Voltage
V
IL
DIN, CS, RESET
250
500
Input Hysteresis
V
mV
HYST
SCLK
Input Current
I
1
µA
pF
IN
Input Capacitance
5
_______________________________________________________________________________________
3
16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADC
ELECTRICAL CHARACTERISTICS (continued)
(V
= 3V or 5V, GND = 0, V
= 1.225V for V
= 3V and V
= 2.5V for V
= 5V, V
= GND, external f
=
CLKIN
DD
REF+
DD
REF+
DD
REF-
2.4576MHz, CLKDIV bit = 0, C
to GND = 0.1µF, C
- to GND = 0.1µF, T = T
to T
, unless otherwise noted.)
REF+
REF
A
MIN
MAX
PARAMETER
CLKIN INPUT
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
V
V
= 4.75V to 5.25V
= 2.7V to 3.6V
= 4.75V to 5.25V
= 2.7V to 3.6V
3.5
2.5
DD
DD
DD
DD
MX705
CLKIN Input High Voltage
V
V
CLKINH
0.8
0.4
10
CLKIN Input Low Voltage
CLKIN Input Current
V
V
CLKINL
I
µA
CLKIN
DIGITAL OUTPUTS (DOUT, DRDY, CLKOUT)
DOUT and DRDY,
= 800µA
0.4
0.4
0.4
0.4
I
SINK
V
V
V
V
= 5V
= 3V
= 5V
= 3V
DD
DD
DD
DD
CLKOUT,
= 10µA
I
SINK
Output Voltage Low
V
V
OL
DOUT and DRDY,
= 100µA
I
SINK
CLKOUT,
= 10µA
I
SINK
DOUT and DRDY,
4.0
4.0
I
= 200µA
SOURCE
CLKOUT,
I
= 10µA
SOURCE
Output Voltage High
V
V
OH
DOUT and DRDY,
V
-
DD
I
= 100µA
0.6V
SOURCE
CLKOUT,
V
-
DD
I
= 10µA
0.6V
SOURCE
Tri-State Leakage Current
Tri-State Output Capacitance
SYSTEM CALIBRATION
I
DOUT only
DOUT only
10
µA
pF
L
C
9
OUT
-1.05 ×
1.05 ×
GAIN = selected PGA gain (1 to 128)
(Note 10)
Full-Scale Calibration Range
Offset Calibration Range
Input Span
V
/
V
/
V
V
V
REF
REF
GAIN
GAIN
-1.05 ×
1.05 ×
GAIN = selected PGA gain (1 to 128)
(Note 10)
V
/
V
/
REF
REF
GAIN
GAIN
0.8 ×
2.1 ×
GAIN = selected PGA gain (1 to 128)
(Notes 10, 11)
V
/
V
/
REF
REF
GAIN
GAIN
4
_______________________________________________________________________________________
16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADC
MX705
ELECTRICAL CHARACTERISTICS (continued)
(V
= 3V or 5V, GND = 0, V
= 1.225V for V
= 3V and V
= 2.5V for V
= 5V, V
= GND, external f
=
DD
REF+
DD
REF+
DD
REF-
CLKIN
2.4576MHz, CLKDIV bit = 0, C
to GND = 0.1µF, C
- to GND = 0.1µF, T = T
to T
, unless otherwise noted.)
REF+
REF
A
MIN
MAX
PARAMETER
POWER REQUIREMENTS
Power-Supply Voltage
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
2.70
5.25
0.45
V
DD
Unbuffered
=1MHz,
gain =1 to 128
V
V
= 5V
= 3V
DD
DD
f
CLKIN
0.32
0.7
Buffered,
V
V
V
= 5V
= 3V
= 5V,
DD
DD
DD
f
=1MHz,
CLKIN
0.6
gain =1 to 128
0.6
0.85
0.4
0.6
0.9
1.3
0.7
1.1
gain = 1 to 4
V
= 5V,
DD
gain = 8 to 128
Unbuffered,
f
= 2.4576MHz
CLKIN
V
= 3V,
DD
mA
gain = 1 to 4
Power-Supply Current (Note 12)
I
DD
V
= 3V,
DD
gain = 8 to 128
V
= 5V,
DD
gain = 1 to 4
V
= 5V,
DD
gain = 8 to 128
Buffered,
= 2.4576MHz
V
= 3V,
DD
f
CLKIN
gain = 1 to 4
V
= 3V,
DD
gain = 8 to 128
V
V
= 5V
= 3V
16
8
DD
DD
Power-down mode
(Note 13)
µA
dB
V
V
= 4.75V to 5.25V
= 2.7V to 3.6V
(Note 14)
(Note 14)
DD
DD
Power-Supply Rejection Ratio
PSRR
EXTERNAL CLOCK TIMING SPECIFICATIONS
CLKIN Frequency
Duty Cycle
f
(Note 15)
400
40
2500
60
kHz
%
CLKIN
_______________________________________________________________________________________
5
16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADC
TIMING CHARACTERISTICS
(V
= 3V or 5V, GND = 0, V
= 1.225V for V
= 3V and V
= 2.5V for V
= 5V, V
= GND, external f
=
CLKIN
DD
REF+
DD
REF+
DD
REF-
2.4576MHz, CLKDIV bit = 0, C
(Figures 8, 9)
to GND = 0.1µF, C
- to GND = 0.1µF, T = T
to T
, unless otherwise noted.) (Note 16)
REF+
REF
A
MIN
MAX
PARAMETER
DRDY High Time
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
500 /
CLKIN
100
s
f
MX705
Reset Pulse-Width Low
ns
ns
ns
DRDY Fall to CS Fall Setup Time
CS Fall to SCLK Rise Setup Time
t
t
0
120
0
1
2
V
V
= 4.75V to 5.25V
= 2.7V to 3.6V
80
DD
DD
SCLK Fall to DOUT Valid Delay
t
ns
3
0
100
SCLK Pulse-Width High
t
4
t
5
t
6
100
100
0
ns
ns
ns
SCLK Pulse-Width Low
CS Rise to SCLK Rise Hold Time
V
V
= 4.75V to 5.25V
= 2.7V to 3.6V
60
DD
DD
Bus Relinquish Time After SCLK
Rising Edge
t
ns
7
100
100
SCLK Fall to DRDY Rise Delay
DIN to SCLK Setup Time
DIN to SCLK Hold Time
t
t
ns
ns
ns
8
9
30
20
t
10
6
_______________________________________________________________________________________
16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADC
MX705
TIMING CHARACTERISTICS (continued)
(V
= 3V or 5V, GND = 0, V
= 1.225V for V
= 3V and V
= 2.5V for V
= 5V, V
= GND, external f
=
CLKIN
DD
REF+
DD
REF+
DD
REF-
2.4576MHz, CLKDIV bit = 0, C
(Figures 8, 9)
to GND = 0.1µF, C
- to GND = 0.1µF, T = T
to T
, unless otherwise noted.) (Note 16)
MAX
REF+
REF
A
MIN
Note 1: These errors are in the order of the conversion noise shown in Tables 1 and 3. This applies after calibration at the given
temperature.
Note 2: Recalibration at any temperature removes these drift errors.
Note 3: Positive full-scale error includes zero-scale errors (unipolar offset error or bipolar zero error) and applies to both unipolar
and bipolar input ranges.
Note 4: Full-scale drift includes zero-scale drift (unipolar offset drift or bipolar zero drift) and applies to both unipolar and bipolar
input ranges.
Note 5: Gain error does not include zero-scale errors. It is calculated as (full-scale error - unipolar offset error) for unipolar ranges,
and (full-scale error - bipolar zero error) for bipolar ranges.
Note 6: Gain-error drift does not include unipolar offset drift or bipolar zero drift. Effectively, it is the drift of the part if only zero-
scale calibrations are performed.
Note 7: The analog input voltage range on AIN+ is given with respect to the voltage on AIN- on the MX7705.
Note 8: This common-mode voltage range is allowed, provided that the input voltage on analog inputs does not go more positive
than (V
+ 30mV) or more negative than (GND - 30mV). Parts are functional with voltages down to (GND - 200mV), but
DD
with increased leakage at high temperature.
Note 9: The REF differential voltage, V
, is the voltage on REF+ referenced to REF- (V
= V
- V
.
REF-)
REF
REF
REF+
Note 10: Guaranteed by design.
Note 11: These calibration and span limits apply, provided that the absolute voltage on the analog inputs does not exceed (V
+
DD
30mV) or go more negative than (GND - 30mV). The offset calibration limit applies to both the unipolar zero point and the
bipolar zero point.
Note 12: When using a crystal or ceramic resonator across the CLKIN and CLKOUT as the clock source for the device, the supply
current and power dissipation varies depending on the crystal or resonator type. Supply current is measured with the digi-
tal inputs connected to 0 or V , CLKIN connected to an external clock source, and CLKDIS = 1.
DD
Note 13: If the external master clock continues to run in power-down mode, the power-down current typically increases to 67µA at
3V. When using a crystal or ceramic resonator across the CLKIN and CLKOUT as the clock source for the device, the
clock generator continues to run in power-down mode and the power dissipation depends on the crystal or resonator type
(see the Power-Down Modes section).
Note 14: Measured at DC and applied in the selected passband. PSRR at 50Hz exceeds 120dB with filter notches of 25Hz or 50Hz.
PSRR at 60Hz exceeds 120dB with filter notches of 20Hz or 60Hz. PSRR depends on both gain and V
.
DD
PSRR (dB)
(V = 5V)
PSRR (dB)
(V = 3V)
GAIN
DD
DD
1
90
86
2
4
78
84
91
78
85
93
8 to 128
Note 15: Provide f
whenever the MX7705 is not in power-down mode. If no clock is present, the device can draw higher than
specified current and can possibly become uncalibrated.
CLKIN
Note 16: All input signals are specified with t = t = 5ns (10% to 90% of V ) and timed from a voltage level of 1.6V.
r
f
DD
_______________________________________________________________________________________
7
16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADC
Table 1. Output RMS Noise vs. Gain and Output Data Rate (V
= 5V)
DD
TYPICAL OUTPUT RMS NOISE (µV)
FILTER FIRST
NOTCH AND
-3dB FREQUENCY
GAIN
OUTPUT DATA RATE
1
2
4
8
16
32
64
128
BUFFERED (f
20Hz
= 1MHz)
CLKIN
5.24Hz
6.55Hz
26.2Hz
52.4Hz
4.44
5.11
2.28
2.79
1.29
1.55
0.79
0.92
0.70
0.81
0.70
0.80
0.64
0.73
2.25
9.14
0.63
0.74
2.24
9.22
MX705
25Hz
100Hz
200Hz
102.35
586.93
49.59
272.83
23.04
224.79
11.78
70.78
6.32
3.63
33.94
17.57
UNBUFFERED (f
20Hz
= 1MHz)
CLKIN
5.24Hz
6.55Hz
26.2Hz
52.4Hz
4.32
5.16
2.50
2.85
1.35
1.63
0.81
0.96
0.73
0.83
0.70
0.81
0.64
0.74
2.22
8.95
0.64
0.74
2.23
9.08
25Hz
100Hz
105.78
526.60
49.86
260.51
24.67
132.16
12.16
67.25
6.42
3.80
200Hz
34.09
18.20
BUFFERED (f
50Hz
= 2.4576MHz)
CLKIN
13.1Hz
3.53
4.41
1.86
2.23
1.09
1.29
0.73
0.83
0.72
0.79
0.71
0.77
0.67
0.72
2.32
9.43
0.66
0.73
2.35
9.40
60Hz
15.72Hz
65.5Hz
131Hz
250Hz
500Hz
99.66
608.86
46.85
288.39
16.98
110.80
12.48
67.51
6.38
3.78
36.75
17.98
UNBUFFERED (f
50Hz
= 2.4576MHz)
CLKIN
13.1Hz
15.72Hz
65.5Hz
131Hz
3.65
4.56
1.94
2.41
1.17
1.32
0.79
0.87
0.70
0.80
0.69
0.79
0.66
0.71
2.36
9.80
0.65
0.74
2.36
9.44
60Hz
250Hz
101.56
556.06
49.64
278.91
25.39
142.88
12.92
74.78
6.65
3.69
500Hz
35.41
18.99
8
_______________________________________________________________________________________
16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADC
MX705
Table 2. Peak-to-Peak Resolution vs. Gain and Output Data Rate (V
= 5V)
DD
TYPICAL PEAK-TO-PEAK RESOLUTION (BITS)
FILTER FIRST
NOTCH AND
-3dB FREQUENCY
GAIN
OUTPUT DATA RATE
1
2
4
8
16
32
64
128
BUFFERED (f
20Hz
= 1MHz)
CLKIN
5.24Hz
6.55Hz
26.2Hz
52.4Hz
16
16
12
10
16
16
12
10
16
16
12
10
16
16
12
10
16
16
12
10
15
15
12
10
14
14
12
10
13
13
11
9
25Hz
100Hz
200Hz
UNBUFFERED (f
20Hz
= 1MHz)
CLKIN
5.24Hz
6.55Hz
26.2Hz
52.4Hz
16
16
12
10
16
16
12
10
16
16
12
10
16
16
12
10
16
16
12
10
15
15
12
10
14
14
12
10
13
13
11
9
25Hz
100Hz
200Hz
BUFFERED (f
50Hz
= 2.4576MHz)
CLKIN
13.1Hz
16
16
12
10
16
16
12
10
16
16
13
11
16
16
12
10
16
16
12
10
15
15
12
10
14
14
12
10
13
13
11
9
60Hz
15.72Hz
65.5Hz
250Hz
500Hz
131Hz
UNBUFFERED (f
50Hz
= 2.4576MHz)
13.1Hz
CLKIN
16
16
12
10
16
16
12
10
16
16
12
10
16
16
12
10
16
16
12
10
15
15
12
10
14
14
12
10
13
13
11
9
60Hz
15.72Hz
65.5Hz
250Hz
500Hz
131Hz
_______________________________________________________________________________________
9
16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADC
Table 3. Output RMS Noise vs. Gain and Output Data Rate (V
= 3V)
DD
TYPICAL OUTPUT RMS NOISE (µV)
FILTER FIRST
NOTCH AND
-3dB FREQUENCY
GAIN
OUTPUT DATA RATE
1
2
4
8
16
32
64
128
BUFFERED (f
20Hz
= 1MHz)
CLKIN
5.24Hz
6.55Hz
26.2Hz
52.4Hz
3.52
4.24
1.84
2.23
2.19
1.19
0.73
0.84
0.66
0.74
0.62
0.69
2.23
8.76
0.62
0.69
1.70
4.70
0.62
0.69
1.69
4.70
MX705
25Hz
100Hz
200Hz
50.36
268.02
25.12
175.98
12.06
65.77
6.04
3.38
34.89
16.73
UNBUFFERED (f
20Hz
= 1MHz)
CLKIN
5.24Hz
6.55Hz
26.2Hz
52.4Hz
3.58
4.16
1.92
2.27
1.13
1.27
0.72
0.83
0.66
0.74
0.64
0.70
0.70
8.47
0.61
0.69
1.66
4.66
0.62
0.67
1.63
4.68
25Hz
100Hz
50.48
256.43
23.89
135.78
12.10
65.62
5.90
3.26
200Hz
33.18
16.65
BUFFERED (f
50Hz
= 2.4576MHz)
CLKIN
13.1Hz
2.84
3.27
1.68
1.84
2.00
1.12
0.71
0.78
0.67
0.75
0.65
0.70
2.32
9.20
0.63
0.68
1.64
5.16
0.61
0.67
1.66
4.92
60Hz
15.72Hz
65.5Hz
250Hz
500Hz
47.90
281.03
24.43
104.19
12.56
69.58
6.48
3.45
131Hz
34.59
17.44
UNBUFFERED (f
50Hz
= 2.4576MHz)
13.1Hz
CLKIN
3.04
3.35
1.74
1.80
1.03
1.13
0.72
0.81
0.64
0.73
0.64
0.69
2.22
9.55
0.62
0.67
1.68
4.90
0.63
0.68
1.65
5.18
60Hz
15.72Hz
65.5Hz
250Hz
49.63
279.13
23.82
134.82
13.03
69.47
6.23
3.42
500Hz
131Hz
35.42
17.47
10 ______________________________________________________________________________________
16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADC
MX705
Table 4. Peak-to-Peak Resolution vs. Gain and Output Data Rate (V
= 3V)
DD
TYPICAL PEAK-TO-PEAK RESOLUTION (BITS)
FILTER FIRST
NOTCH AND
-3dB FREQUENCY
GAIN
OUTPUT DATA RATE
1
2
4
8
16
32
64
128
BUFFERED (f
20Hz
= 1MHz)
CLKIN
5.24Hz
6.55Hz
26.2Hz
52.4Hz
16
16
12
10
16
16
12
10
16
16
12
10
16
16
12
10
15
15
12
10
14
14
12
10
13
13
12
10
12
12
11
9
25Hz
100Hz
200Hz
UNBUFFERED (f
20Hz
= 1MHz)
CLKIN
5.24Hz
6.55Hz
26.2Hz
52.4Hz
16
16
12
10
16
16
12
10
16
16
12
10
16
16
12
10
15
15
12
10
14
14
14
10
13
13
12
10
12
12
11
9
25Hz
100Hz
200Hz
BUFFERED (f
50Hz
= 2.4576MHz)
CLKIN
13.1Hz
16
16
12
10
16
16
12
11
16
16
12
10
16
16
12
10
15
15
12
10
14
14
12
10
13
13
11
10
12
12
11
9
60Hz
15.72Hz
65.5Hz
131Hz
250Hz
500Hz
UNBUFFERED (f
50Hz
= 2.4576MHz)
CLKIN
13.1Hz
15.72Hz
65.5Hz
131Hz
16
16
12
10
16
16
12
10
16
16
12
10
16
16
12
10
15
15
12
10
14
14
12
10
13
13
11
10
12
12
11
9
60Hz
250Hz
500Hz
Typical Operating Characteristics
(V
= 3V or 5V, V
= 1.225V for V
= 3V, V
= 2.5V for V
= 5V, V - = GND, T = +25°C, unless otherwise noted.)
REF A
DD
REF+
DD
REF+
DD
OFFSET ERROR vs. SUPPLY VOLTAGE (3V)
TYPICAL OUTPUT NOISE
HISTOGRAM OF TYPICAL OUTPUT NOISE
0.0015
0.0010
0.0005
0
32776
32774
32772
32770
32768
32766
32764
32762
32760
32758
32756
400
V
= 5V, V = 2.5V
REF
V
V
= 5V,
GAIN = 128
ODR = 60Hz
RMS NOISE = 1.3μV
RMS NOISE = 1.3μV
DD
DD
V
= 3V
DD
GAIN = 128
ODR = 60Hz
= 2.5V
REF
300
200
100
0
-0.0005
-0.0010
-0.0015
2.70 2.85 3.00 3.15 3.30 3.45 3.60
SUPPLY VOLTAGE (V)
0
400
800
1200
1600
2000
READING NUMBER
CODE
______________________________________________________________________________________ 11
16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADC
Typical Operating Characteristics (continued)
(V
= 3V or 5V, V
= 1.225V for V
= 3V, V
= 2.5V for V
= 5V, V
- = GND, T = +25°C, unless otherwise noted.)
REF A
DD
REF+
DD
REF+
DD
OFFSET ERROR vs. SUPPLY VOLTAGE (5V)
OFFSET ERROR vs. TEMPERATURE
GAIN ERROR vs. SUPPLY VOLTAGE (3V)
0.003
0.002
0.001
0
0.003
0.0015
0.0010
0.0005
0
V
= 5V
V
= 3V
DD
DD
V
V
= 5V
= 3V
0.002
0.001
0
DD
DD
MX705
-0.001
-0.002
-0.003
-0.001
-0.002
-0.003
-0.0005
-0.0010
-0.0015
4.75
4.85
4.95
5.05
5.15
5.25
-40
-15
10
35
60
85
2.70 2.85 3.00 3.15 3.30 3.45 3.60
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
GAIN ERROR vs. SUPPLY VOLTAGE (5V)
GAIN ERROR vs. TEMPERATURE
0.005
0.003
0.002
0.001
0
V
= 5V
DD
0.004
0.003
0.002
0.001
0
V
= 3V
DD
-0.001
-0.002
-0.003
-0.004
-0.005
-0.001
-0.002
-0.003
V
= 5V
DD
-40
-15
10
35
60
85
4.75
4.85
4.95
5.05
5.15
5.25
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
12 ______________________________________________________________________________________
16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADC
MX705
Typical Operating Characteristics (continued)
(V
= 3V or 5V, V
= 1.225V for V
= 3V, V
= 2.5V for V
= 5V, V - = GND, T = +25°C, unless otherwise noted.)
REF A
DD
REF+
DD
REF+
DD
SUPPLY CURRENT vs. SUPPLY VOLTAGE (5V)
SUPPLY CURRENT vs. SUPPLY VOLTAGE (3V)
0.65
0.6
A
V
= 5V
DD
V
= 3V
DD
A
B
0.55
0.45
0.35
0.25
0.5
0.4
0.3
0.2
B
C
E
C
D
D
E
4.75
4.85
4.95
SUPPLY VOLTAGE (V)
B: BUFFERED MODE C: BUFFERED MODE
= 2.4576MHz, = 1MHz,
5.05
5.15
5.25
2.70 2.85 3.00 3.15 3.30 3.45 3.60
SUPPLY VOLTAGE (V)
A: BUFFERED MODE
= 2.4576MHz,
A: BUFFERED MODE
= 2.4576MHz,
B: BUFFERED MODE C: BUFFERED MODE
= 2.4576MHz, = 1MHz,
f
f
f
CLKIN
GAIN = 1 TO 128
f
f
f
CLKIN
CLKIN
CLKIN
CLKIN
CLKIN
GAIN = 8 TO 128
GAIN = 1 TO 4
GAIN = 8 TO 128
GAIN = 1 TO 4
GAIN = 1 TO 128
D: UNBUFFERED MODE E: UNBUFFERED MODE
D: UNBUFFERED MODE E: UNBUFFERED MODE
f
= 2.4576MHz, = 1MHz,
f
f
= 2.4576MHz, = 1MHz,
f
CLKIN
CLKIN
CLKIN
CLKIN
GAIN = 1 TO 128
GAIN = 1 TO 128
GAIN = 1 TO 128
GAIN = 1 TO 128
SUPPLY CURRENT vs. TEMPERATURE (3V)
SUPPLY CURRENT vs. TEMPERATURE (5V)
0.6
0.5
0.4
0.3
0.2
0.65
0.55
0.45
0.35
0.25
A
V
= 5V
DD
V
= 3V
DD
A
B
B
C
C
D
D
E
E
-40
-15
10
TEMPERATURE (°C)
B: BUFFERED MODE C: BUFFERED MODE
= 2.4576MHz, = 1MHz,
35
60
85
-40
-15
10
TEMPERATURE (°C)
B: BUFFERED MODE C: BUFFERED MODE
= 2.4576MHz, = 1MHz,
35
60
85
A: BUFFERED MODE
= 2.4576MHz,
A: BUFFERED MODE
= 2.4576MHz,
f
f
f
CLKIN
f
f
f
CLKIN
CLKIN
CLKIN
CLKIN
CLKIN
GAIN = 8 TO 128
GAIN = 1 TO 4
GAIN = 1 TO 128
GAIN = 8 TO 128
GAIN = 1 TO 4
GAIN = 1 TO 128
D: UNBUFFERED MODE E: UNBUFFERED MODE
D: UNBUFFERED MODE E: UNBUFFERED MODE
f
= 2.4576MHz, = 1MHz,
f
f
= 2.4576MHz, = 1MHz,
f
CLKIN
CLKIN
CLKIN
CLKIN
GAIN = 1 TO 128
GAIN = 1 TO 128
GAIN = 1 TO 128
GAIN = 1 TO 128
______________________________________________________________________________________ 13
16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADC
Typical Operating Characteristics (continued)
(V
= 3V or 5V, V
= 1.225V for V
= 3V, V
= 2.5V for V
= 5V, V
- = GND, T = +25°C, unless otherwise noted.)
REF A
DD
REF+
DD
REF+
DD
SUPPLY CURRENT vs. f
(3V)
SUPPLY CURRENT vs. f
(5V)
CLKIN
CLKIN
MX705
0.6
0.5
0.4
0.3
0.2
0.65
V
= 3V
V
= 5V
DD
DD
B
B
A
A
0.55
0.45
0.35
0.25
C
C
D
D
E
E
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6
(MHz)
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6
(MHz)
f
f
CLKIN
CLKIN
A: BUFFERED MODE
CLK = 1,
GAIN = 128
B: BUFFERED MODE C: BUFFERED MODE
A: BUFFERED MODE
CLK = 1,
GAIN = 128
B: BUFFERED MODE C: BUFFERED MODE
CLK = 1,
GAIN = 1
CLK = 0,
GAIN = 1, 128
CLK = 1,
GAIN = 1
CLK = 0,
GAIN = 1, 128
D: UNBUFFERED MODE E: UNBUFFERED MODE
D: UNBUFFERED MODE
CLK = 1,
GAIN = 1, 128
E: UNBUFFERED MODE
CLK = 0,
GAIN = 1, 128
CLK = 1,
CLK = 0,
GAIN = 1, 128
GAIN = 1, 128
SUPPLY CURRENT vs. GAIN (3V)
SUPPLY CURRENT vs. GAIN (5V)
0.6
0.65
0.55
0.45
0.35
0.25
A
V
= 5V
V
= 3V
DD
DD
A
B
0.5
0.4
0.3
0.2
B
C
C
D
E
D
E
F
F
1
2
4
8
16
GAIN
32
64 128
1
2
4
8
16
32
64 128
GAIN
A: BUFFERED MODE
CLK = 1, CLKDIV = 1,
= 2.4576MHz
B: BUFFERED MODE C: BUFFERED MODE
CLK = 1, CLKDIV = 0, CLK = 0, CLKDIV = 0,
A: BUFFERED MODE
CLK = 1, CLKDIV = 0,
B: BUFFERED MODE C: BUFFERED MODE
CLK = 1, CLKDIV = 1, CLK = 0, CLKDIV = 0,
f
f
= 2.4576MHz
f
= 1MHz
f
= 2.4576MHz
f
= 2.4576MHz
f
= 1MHz
CLKIN
CLKIN
CLKIN
CLKIN
CLKIN
CLKIN
D: UNBUFFERED MODE E: UNBUFFERED MODE F: UNBUFFERED MODE
CLK = 1, CLKDIV = 1, CLK = 1, CLKDIV = 0, CLK = 0, CLKDIV = 0,
= 2.4576MHz = 2.4576MHz = 1MHz
D: UNBUFFERED MODE E: UNBUFFERED MODE F: UNBUFFERED MODE
CLK = 1, CLKDIV = 1, CLK = 1, CLKDIV = 0, CLK = 0, CLKDIV = 0,
= 2.4576MHz = 2.4576MHz = 1MHz
f
f
f
CLKIN
f
f
f
CLKIN
CLKIN
CLKIN
CLKIN
CLKIN
14 ______________________________________________________________________________________
16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADC
MX705
Typical Operating Characteristics (continued)
(V
= 3V or 5V, V
= 1.225V for V
= 3V, V
= 2.5V for V
= 5V, V
- = GND, T = +25°C, unless otherwise noted.)
REF A
DD
REF+
DD
REF+
DD
POWER-DOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE (3V)
POWER-DOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE (5V)
POWER-DOWN SUPPLY CURRENT
vs. TEMPERATURE
100
200
300
250
200
150
100
50
V
= 3V
DD
V
= 5V
DD
80
60
40
20
0
180
160
140
120
100
V
= 5V
DD
V
= 3V
DD
0
2.70 2.85 3.00 3.15 3.30 3.45 3.60
SUPPLY VOLTAGE (V)
4.75
4.85
4.95
5.05
5.15
5.25
-40
-15
10
35
60
85
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
EXTERNAL OSCILLATOR STARTUP TIME
MX7705 toc20
V
DD
5V/div
4.9152MHz CRYSTAL
CLKOUT
5V/div
CLKOUT
5V/div
2.4576MHz CRYSTAL
2ms/div
______________________________________________________________________________________ 15
16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADC
Pin Description
PIN
NAME
FUNCTION
Serial Clock Input. Apply an external serial clock to transfer data to and from the device at data rates
of up to 5MHz.
1
SCLK
Clock Input. Connect a crystal/resonator between CLKIN and CLKOUT, or drive CLKIN externally with
a CMOS-compatible clock source with CLKOUT left unconnected.
2
3
CLKIN
MX705
Clock Output. Connect a crystal/resonator between CLKIN and CLKOUT. When enabled, CLKOUT
provides a CMOS-compatible, inverted clock output. Set CLKDIS = 0 in the clock register to enable
CLKOUT. Set CLKDIS = 1 in the clock register to disable CLKOUT to conserve power.
CLKOUT
Active-Low Chip-Select Input. CS selects the active device in systems with more than one device on
the serial bus. Drive CS low to clock data in on DIN and to clock data out on DOUT. When CS is high,
DOUT is high impedance. Connect CS to GND for 3-wire operation.
4
CS
5
6
RESET
AIN2+
AIN1+
AIN1-
REF+
REF-
Active-Low Reset Input. Drive RESET low to reset the MX7705 to power-on reset status.
Channel 2 Positive Differential Analog Input
7
Channel 1 Positive Differential Analog Input
8
Channel 1 Negative Differential Analog Input
Positive Differential Reference Input
9
10
11
Negative Differential Reference Input
AIN2-
Channel 2 Negative Differential Analog Input
Active-Low Data-Ready Output. DRDY goes low when a new conversion result is available in the data
register. When a read-operation of a full output word completes, DRDY returns high.
12
13
DRDY
Serial Data Output. DOUT outputs serial data from the data register. DOUT changes on the falling
edge of SCLK and is valid on the rising edge of SCLK. When CS is high, DOUT is high impedance.
DOUT
DIN
14
15
16
Serial Data Input. Data on DIN is clocked in on the rising edge of SCLK when CS is low.
V
Power Input
Ground
DD
GND
16 ______________________________________________________________________________________
16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADC
MX705
Functional Diagram
CLKIN
CLOCK
GENERATOR
DIVIDER
CLKOUT
MX7705
BUFFER
AIN1+
AIN1-
AIN2+
AIN2-
V
2ND-ORDER
SIGMA-DELTA
MODULATOR
DD
SWITCHING
NETWORK
S1
S2
DIGITAL
FILTER
PGA
GND
BUFFER
CS
SCLK
DIN
DOUT
DRDY
RESET
SERIAL INTERFACE,
REGISTERS,
AND
S1 AND S2 ARE OPEN IN
BUFFERED MODE AND CLOSED
IN UNBUFFERED MODE
CONTROL
REF+
REF-
Analog Inputs
Detailed Description
The MX7705 accepts four analog inputs (AIN1+, AIN1-,
AIN2+, and AIN2-) in buffered or unbuffered mode.
Use Table 8 to select the positive and negative input
pair for a fully differential channel. The input buffer iso-
lates the inputs from the capacitive load presented by
the PGA/modulator, allowing for high source-imped-
ance analog transducers. The value of the BUF bit in
the setup register (see the Setup Register section) deter-
mines whether the input buffer is enabled or disabled.
The MX7705 low-power, 2-channel, serial-output ADC
uses a sigma-delta modulator with a digital filter to
achieve 16-bit resolution with no missing codes. The
device includes a PGA, an on-chip input buffer, and a
bidirectional communications port. The MX7705 oper-
ates with a single 2.7V to 5.25V supply.
Fully differential inputs, an internal input buffer, and an
on-chip PGA (gain = 1 to 128) allow low-level signals to
be directly measured, minimizing the requirements for
external signal conditioning. Self-calibration corrects for
gain and offset errors. A programmable digital filter
allows for the selection of the output data rate and first-
notch frequency from 20Hz to 500Hz.
Internal protection diodes, which clamp the analog
input to V
and/or GND, allow the input to swing from
DD
(GND - 0.3V) to (V
+ 0.3V), without damaging the
DD
device. If the analog input exceeds 300mV beyond the
supplies, limit the input current to 10mA.
The bidirectional serial SPI-/QSPI-/MICROWIRE-compati-
ble interface consists of four digital control lines (SCLK,
CS, DOUT, and DIN) and provides an easy interface to
microcontrollers (µCs). Connect CS to GND to configure
the MX7705 for 3-wire operation.
Input Buffers
When the analog input buffer is disabled, the analog
input drives a typical 7pF (gain = 1) capacitor, C
,
TOTAL
in series with the 7kΩ typical on-resistance of the track
and hold (T/H) switch (Figure 1). C is comprised
TOTAL
of the sampling capacitor, C
, and the stray capac-
SAMP
itance, C
. During the conversion, C
charges
STRAY
SAMP
to (AIN+ - AIN-). The gain determines the value of
(Table 5).
C
SAMP
______________________________________________________________________________________ 17
16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADC
To minimize gain errors in unbuffered mode, select a
source impedance less than the maximum values
shown in Figures 2 and 3. These are the maximum
external resistance/capacitance combinations allowed
AIN(+)
R
(7kΩ TYP)
SW
HIGH
IMPEDANCE
before gain errors greater than 1 LSB are introduced in
unbuffered mode.
AIN(-)
C
(7pF TYP FOR GAIN = 1)
TOTAL
Enable the internal input buffer for a high source imped-
ance. This isolates the inputs from the sampling capaci-
tor and reduces the sampling-related gain error. When
using the internal buffer, limit the absolute input voltage
MX705
C
= C
+ C
SAMP STRAY
TOTAL
V
BIAS
range to (V
+ 50mV) to (V
- 1.5V). Set gain and
DD
GND
common-mode voltage range properly to minimize lin-
earity errors.
Figure 1. Unbuffered Analog Input Structure
Input Voltage Range
In unbuffered mode, the absolute analog input voltage
100
range is from (GND - 30mV) to (V
+ 30mV) (see the
DD
GAIN = 1
Electrical Characteristics). In buffered mode, the ana-
log input voltage range is reduced to (GND + 50mV) to
GAIN = 2
(V
- 1.5V). In both buffered and unbuffered modes,
DD
10
GAIN = 4
the differential analog input range (V
- V
)
AIN-
AIN+
decreases at higher gains (see the Programmable-Gain
Amplifier and the Unipolar and Bipolar Modes sections).
GAIN = 8 TO 128
1
Reference
The MX7705 provides differential inputs, REF+ and REF-,
for an external reference voltage. Connect the external
reference directly across REF+ and REF- to obtain the
0.1
1
10
100
1000
10,000
differential reference voltage, V
. The common-mode
REF
EXTERNAL CAPACITANCE (pF)
voltage range for V
and V
is between GND
REF+
REF-
and V . For specified operation, the nominal voltage,
DD
V
(V
- V
), is 2.5V for V
= 2.7V to 3.6V.
= 4.75V to 5.25V
DD
REF REF+
REF-
Figure 2. Maximum External Resistance vs. Maximum External
Capacitance for Unbuffered Mode (1MHz)
and 1.225V for V
DD
The MX7705 samples REF+ and REF- at f
/ 64
CLKIN
(CLKDIV = 0) or f
/ 128 (CLKDIV = 1) with an
CLKIN
internal 10pF (typ for gain = 1) sampling capacitor in
series with a 7kΩ (typ) switch on-resistance.
100
GAIN = 1
GAIN = 2
Programmable-Gain Amplifier
A PGA provides selectable levels of gain: 1, 2, 4, 8, 16,
32, 64, and 128. Bits G0, G1, and G2 in the setup reg-
ister control the gain (Table 9). As the gain increases,
10
GAIN = 4
the value of the input sampling capacitor, C
, also
SAMP
increases (Table 5). The dynamic load presented to the
analog inputs increases with clock frequency and gain
in unbuffered mode (see the Input Buffers section and
Figure 1).
1
GAIN = 8 TO 128
0.1
1
10
100
1000
10,000
EXTERNAL CAPACITANCE (pF)
Figure 3. Maximum External Resistance vs. Maximum External
Capacitance for Unbuffered Mode (2.4576MHz)
18 ______________________________________________________________________________________
16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADC
MX705
Table 5. Input Sampling Capacitor vs. Gain
V
/ GAIN
REF
GAIN
INPUT SAMPLING CAPACITOR (C ) (pF)
SAMP
1111 1111 1111 1111
1111 1111 1111 1110
1111 1111 1111 1101
1111 1111 1111 1100
1
3.75
7.5
15
FULL-SCALE TRANSITION
2
4
8–128
30
V
REF
1 LSB =
(GAIN) (65,536)
Increasing the gain increases the resolution of the ADC
(LSB size decreases), but reduces the differential input
voltage range. Calculate 1 LSB in unipolar mode using
the following equation:
0000 0000 0000 0011
0000 0000 0000 0010
0000 0000 0000 0001
0000 0000 0000 0000
V
REF
1 LSB=
GAIN (65,536)
where V
= V
- V
REF-.
REF
REF+
0
1
2
3
65,533
DIFFERENTIAL INPUT VOLTAGE (LSB)
65,535
For a gain of one and V
= 2.5V, the full-scale volt-
REF
age in unipolar mode is 2.5V and 1 LSB ≈ 38.1µV. For a
Figure 4. MX7705 Unipolar Transfer Function
gain of four, the full-scale voltage in unipolar mode is
0.625V (V
/ GAIN) and 1 LSB ≈ 9.5µV. The differen-
REF
tial input voltage range in this example reduces from
2.5V to 0.625V, and the resolution increases, since the
LSB size decreased from 38.1µV to 9.5µV.
V
/ GAIN
V
/ GAIN
REF
REF
1111 1111 1111 1111
Calculate 1 LSB in bipolar mode using the following
equation:
1111 1111 1111 1110
1111 1111 1111 1101
V
V
REF
REF
1 LSB=
× 2
1 LSB =
x 2
(GAIN) (65,536)
GAIN (65,536)
- V
REF+ REF-.
1000 0000 0000 0001
1000 0000 0000 0000
0111 1111 1111 1111
where V
= V
REF
Unipolar and Bipolar Modes
The B/U bit in the setup register (Table 9) configures
the MX7705 for unipolar or bipolar transfer functions.
Figures 4 and 5 illustrate the unipolar and bipolar trans-
fer functions, respectively.
0000 0000 0000 0010
0000 0000 0000 0001
0000 0000 0000 0000
In unipolar mode, the digital output code is straight
binary. When AIN+ = AIN-, the outputs are at zero
scale, which is the lower endpoint of the transfer func-
tion. The full-scale endpoint is given by AIN+ - AIN- =
-32,768
-32,766
-1
0
+1
+32,765 +32,767
DIFFERENTIAL INPUT VOLTAGE (LSB)
Figure 5. MX7705 Bipolar Transfer Function
V
REF
/ GAIN, where V
= V
- V
.
REF-
REF
REF+
In bipolar mode, the digital output code is in offset
binary. Positive full scale is given by AIN+ - AIN- =
When the MX7705 is in buffered mode, the absolute and
common-mode analog input voltage ranges reduce to
+V
/ GAIN and negative full scale is given by AIN+ -
REF
AIN- = -V
between (GND + 50mV) and (V
- 1.5V). The differential
DD
/ GAIN. When AIN+ = AIN-, the outputs
REF
input voltage range is not affected in buffered mode.
are at zero scale, which is the midpoint of the bipolar
transfer function.
______________________________________________________________________________________ 19
16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADC
The output data rate for the digital filter corresponds with
Modulator
The MX7705 performs analog-to-digital conversions
using a single-bit, 2nd-order, switched-capacitor,
sigma-delta modulator. The sigma-delta modulation
converts the input signal into a digital pulse train whose
average duty cycle represents the digitized signal infor-
mation. A single comparator within the modulator quan-
tizes the input signal at a much higher sample rate than
the bandwidth of the input.
the positioning of the first notch of the filter’s frequency
response. Therefore, for the plot in Figure 6, where the first
notch of the filter is 60Hz, the output data rate is 60Hz. The
notches of the SINC3 filter are repeated at multiples of the
first notch frequency. The SINC3 filter provides an attenua-
tion of better than 100dB at these notches.
MX705
Determine the cutoff frequency of the digital filter by load-
ing the appropriate values into the CLK, FS0, and FS1
bits in the clock register (Table 13). Programming a differ-
ent cutoff frequency with FS0 and FS1 changes the fre-
quency of the notches, but it does not alter the profile of
the frequency response.
The MX7705 modulator provides 2nd-order frequency
shaping of the quantization noise resulting from the sin-
gle-bit quantizer. The modulator is fully differential for
maximum signal-to-noise ratio and minimum suscepti-
bility to power-supply and common-mode noise. A sin-
gle-bit data stream is then presented to the digital filter
for processing to remove the frequency-shaped quanti-
zation noise.
For step changes at the input, allow a settling time
before valid data is read. The settling time depends on
the output data rate chosen for the filter. The worst-
case settling time of a SINC3 filter for a full-scale step
input is four times the output data period. By synchro-
nizing the step input using FSYNC, the settling time
reduces to three times the output data period. If FSYNC
is high during the step input, the filter settles in three
times the output data period after FSYNC falls low.
The modulator sampling frequency is f
/ 128,
CLKIN
(CLKDIV = 0) is the
regardless of gain, where f
CLKIN
frequency of the signal at CLKIN.
Digital Filtering
The MX7705 contains an on-chip, digital lowpass filter
that processes the 1-bit data stream from the modulator
using a SINC3 (sinx/x)3 response. The SINC3 filter has a
settling time of three output data periods.
Analog Filtering
The digital filter does not provide any rejection close to
the harmonics of the modulator sample frequency. Due
to the high oversampling ratio of the MX7705, these
bands occupy only a small fraction of the spectrum and
most broadband noise is filtered. The analog filtering
requirements in front of the MX7705 are reduced com-
pared to a conventional converter with no on-chip filtering.
In addition, the devices provide excellent common-mode
rejection of 90db to reduce the common-mode noise sus-
ceptibility.
Filter Characteristics
Figure 6 shows the filter frequency response. The
SINC3 characteristic -3dB cutoff frequency is 0.262
times the first-notch frequency. This results in a cutoff
frequency of 15.72Hz for a first filter-notch frequency of
60Hz (output data rate of 60Hz). The response shown
in Figure 5 is repeated at either side of the digital filter’s
sample frequency, f (f = 19.2kHz for 60Hz output
M
M
Additional filtering prior to the MX7705 eliminates
unwanted frequencies the digital filter does not reject.
Use additional filtering to ensure that differential noise
signals outside the frequency band of interest do not
saturate the analog modulator.
data rate), and at either side of the related harmonics
(2f , 3f , etc.).
M
M
0
-20
-40
-60
-80
f
= 2.4576MHz
CLKIN
CLK = 1
FS1 = 0
FS0 = 1
If passive components are in the path of the analog
inputs when the device is in unbuffered mode, ensure
the source impedance is low enough (Figure 2) not to
introduce gain errors in the system. This significantly
limits the amount of passive anti-aliasing filtering that
can be applied in front of the MX7705 in unbuffered
mode. In buffered mode, large source impedance
causes a small DC-offset error, which can be removed
by calibration.
f
= 60Hz
N
-100
-120
-140
-160
0
20 40 60 80 100 120 140 160 180 200
FREQUENCY (Hz)
3
Figure 6. Frequency Response of the SINC Filter (Notch at 60Hz)
20 ______________________________________________________________________________________
16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADC
MX705
External Oscillator
The oscillator requires time to stabilize when enabled.
Startup time for the oscillator depends on supply voltage,
temperature, load capacitances, and center frequency.
Depending on the load capacitance, a 1MΩ feedback
resistor across the crystal can reduce the startup time
(Figure 7). The MX7705 was tested with an ECS-24-32-1
(2.4576MHz crystal) and an ECS-49-20-1 (4.9152MHz
crystal) (see the Typical Operating Characteristics). In
power-down mode, the supply current with the external
oscillator enabled is typically 67µA with a 3V supply and
227µA with a 5V supply.
CS
t
6
t
2
SCLK
DIN
t
10
t
9
MSB
LSB
Serial-Digital Interface
The MX7705 interface is fully compatible with SPI-, QSPI-,
and MICROWIRE-standard serial interfaces. The serial
interface provides access to seven on-chip registers. The
registers are 8, 16, and 24 bits in size.
Figure 8. Write Timing Diagram
DRDY
t
8
Drive CS low to transfer data in and out of the MX7705.
Clock in data at DIN on the rising edge of SCLK. Data at
DOUT changes on the falling edge of SCLK and is valid
on the rising edge of SCLK. DIN and DOUT are trans-
ferred MSB first. Drive CS high to force DOUT high
impedance and cause the MX7705 to ignore any signals
on SCLK and DIN. Connect CS low for 3-wire operation.
Figures 8 and 9 show the timings for write and read
operations, respectively.
t
1
CS
t
6
t
t
4
2
SCLK
DOUT
t
5
t
7
t
3
MSB
LSB
On-Chip Registers
The MX7705 contains seven internal registers (Figure 10),
which are accessed by the serial interface. These regis-
ters control the various functions of the device and allow
the results to be read. Table 7 lists the address, power-on
default value, and size of each register.
Figure 9. Read Timing Diagram
The second register is the 8-bit setup register, which con-
trols calibration modes, gain setting, unipolar/bipolar
inputs, and buffered/unbuffered modes. The third register
is the 8-bit clock register, which sets the digital filter char-
acteristics and the clock control bits. The fourth register is
the 16-bit data register, which holds the output result. The
24-bit offset and gain registers store the calibration coeffi-
cients for the MX7705. The 8-bit test register is used for
factory testing only.
The first of these registers is the communications register.
The 8-bit communications register controls the acquisition
channel selection, whether the next data transfer is a read
or write operation, and which register is to be accessed.
The default state of the MX7705 is to wait for a write to
the communications register. Any write or read opera-
tion on the MX7705 is a two-step process. First, a com-
mand byte is written to the communications register.
This command selects the input channel, the desired
register for the next read or write operation, and
whether the next operation is a read or a write. The sec-
ond step is to read from or write to the selected regis-
ter. At the end of the data-transfer cycle, the device
returns to the default state. See the Performing a
Conversion section for examples.
CRYSTAL OR
CERAMIC
RESONATOR
CLKIN
C
C
L
MX7705
CLKOUT
L
OPTIONAL
1MΩ
If the serial communication is lost, write 32 ones to the
serial interface to return the MX7705 to the default
state. The registers are not reset after this operation.
Figure 7. Using a Crystal or Ceramic Oscillator
______________________________________________________________________________________ 21
16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADC
PD: (Default = 0) Power-Down Control Bit. Set PD = 1
to initiate power-down mode. Set PD = 0 to take the
device out of power-down mode. If CLKDIS = 0, CLKOUT
remains active during power-down mode to provide a
clock source for other devices in the system.
DIN
RS2 RS1 RS0
CH0, CH1: (Default = 0, 0) Channel-Select Bit. Write to
the CH0 and CH1 bits to select the conversion channel or
to access the calibration data shown in Table 8. The cali-
bration coefficients of a particular channel are stored in
one of the three offset and gain-register pairs in Table 8.
Set CH1 = 1 and CH0 = 0 to evaluate the noise perfor-
mance of the part without external noise sources. In this
noise evaluation mode, connect AIN1- to an external volt-
age within the allowable common-mode range.
COMMUNICATIONS REGISTER
MX705
SETUP REGISTER (8 BITS)
CLOCK REGISTER (8 BITS)
DATA REGISTER (16 BITS)
TEST REGISTER (8 BITS)*
OFFSET REGISTER (24 BITS)
GAIN REGISTER (24 BITS)
REGISTER
SELECT
DECODER
DOUT
Setup Register
The byte-wide setup register is bidirectional, so it can
be written and read. The byte written to the setup regis-
ter sets the calibration modes, PGA gain, unipolar/bipo-
lar mode, buffer enable, and conversion start (Table 9).
MD1, MD0: (Default = 0, 0) Mode-Select Bits. See
Table 10 for normal operating mode, self-calibration,
zero-scale calibration, or full-scale calibration-mode
selection.
*THE TEST REGISTER IS USED FOR FACTORY TESTING ONLY.
G2, G1, G0: (Default = 0, 0, 0) Gain-Selection Bits. See
Figure 10. Register Summary
Table 11 for PGA gain settings.
B/U: (Default = 0) Bipolar/Unipolar Mode Selection. Set
B/U = 0 to select bipolar mode. Set B/U = 1 to select
unipolar mode.
Communications Register
The byte-wide communications register is bidirectional
so it can be written and read. The byte written to the
communications register indicates the next read or write
operation on the selected register, the power-down
mode, and the analog input channel (Table 6). The
DRDY bit indicates the conversion status.
BUF: (Default = 0) Buffer-Enable Bit. For unbuffered
mode, disable the internal buffer of the MX7705 to reduce
power consumption by writing a 0 to the BUF bit. Write a
1 to this bit to enable the buffer. Use the internal buffer
when acquiring high source-impedance input signals.
FSYNC: (Default
= 1) Filter-Synchronization/
0/DRDY: (Default = 0) Communication-Start/Data-Ready
Bit. Write a 0 to the 0/DRDY bit to start a write operation to
the communications register. If 0/DRDY = 1, then the
device waits until a 0 is written to 0/DRDY before continu-
ing to load the remaining bits. For a read operation, the
0/DRDY bit shows the status of the conversion. The
DRDY bit returns a 0 if the conversion is complete and
the data is ready. DRDY returns a 1 if the new data has
been read and the next conversion is not yet complete. It
has the same value as the DRDY output pin.
Conversion-Start Bit. Set FSYNC = 0 to begin calibration
or conversion. The MX7705 performs free-running con-
versions while FSYNC = 0. Set FSYNC = 1 to stop con-
verting data and to hold the nodes of the digital filter, the
filter-control logic, the calibration-control logic, and the
analog modulator in a reset state. The DRDY output does
not reset high if it is low (indicating that valid data has not
yet been read from the data register) when FSYNC goes
high. To clear the DRDY output, read the data register.
Clock Register
The byte-wide clock register is bidirectional, so it can
be written and read. The byte written to the setup regis-
ter sets the clock, filter first-notch frequency, and the
output data rate (Table 12).
RS2, RS1, RS0: (Default = 0, 0, 0) Register-Select Bits.
RS0, RS1, and RS2 select the next register to be
accessed as shown in Table 7.
R/W: (Default = 0) Read-/Write-Select Bit. Use this bit to
select if the next register access is a read or a write
operation. Set R/W = 0 to select a write operation or set
R/W = 1 for a read operation on the selected register.
MXID: (Default = 1) Maxim-Identifier Bit. This is a read-
only bit. Values written to this bit are ignored.
22 ______________________________________________________________________________________
16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADC
MX705
Table 6. Communications Register
FIRST BIT (MSB)
(LSB)
COMMUNICATION
START/DATA READY
READ/WRITE
SELECT
POWER-DOWN
MODE
FUNCTION
REGISTER SELECT
CHANNEL SELECT
Name
0/DRDY
RS2
0
RS1
0
RS0
0
R/W
PD
0
CH1
0
CH0
0
Defaults
0
0
Table 7. Register Selection
RS2
RS1
RS0
REGISTER
POWER-ON RESET STATUS
REGISTER SIZE (BITS)
0
0
0
Communications Register
Setup Register
Clock Register
Data Register
0x00
0x01
8
8
0
0
1
0
1
0
0x05
8
0
1
1
N/A
16
8
1
0
0
Test Register*
N/A
1
0
1
No Operation
—
—
24
24
1
1
0
Offset Register
Gain Register
0x1F 40 00
0x57 61 AB
1
1
1
*The test register is used for factory testing only.
Table 8. Channel Selection
OFFSET/GAIN
REGISTER PAIR
CH1
CH0
AIN+
AIN-
0
0
1
1
0
1
0
1
AIN1+
AIN2+
AIN1-
AIN1-
AIN1-
AIN2-
AIN1-
AIN2-
0
1
0
2
Table 9. Setup Register
FIRST BIT (MSB)
(LSB)
BIPOLAR/UNIPOLAR
MODE
FUNCTION
MODE CONTROL
PGA GAIN CONTROL
BUFFER ENABLE
FSYNC
Name
Defaults
MD1
0
MD0
0
G2
0
G1
0
G0
0
B/U
0
BUF
0
FSYNC
1
ZERO: (Default = 0) Zero Bit. This is a read-only bit.
CLKDIV: (Default = 0) Clock-Divider Control Bit. The
MX7705 has an internal clock divider. Set this bit to 1 to
divide the input clock by two. When this bit is set to 0, the
MX7705 operates at the external oscillator frequency.
Values written to this bit are ignored.
CLKDIS: (Default = 0) Clock-Disable Bit. Set CLKDIS =
1 to disable the clock when using a crystal or resonator
across CLKIN and CLKOUT. Set CLKDIS = 1 to disable
CLKOUT when using a CMOS clock source at CLKIN.
CLKOUT is held low during clock disable to save
power. Set CLKDIS = 0 to allow other devices to use
the output signal on CLKOUT as a clock source and/or
to enable the external oscillator.
CLK: (Default = 1) Clock Bit. Set CLK = 1 for f
=
CLKIN
2.4576MHz with CLKDIV = 0, or 4.9152MHz with
CLKDIV = 1.
______________________________________________________________________________________ 23
16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADC
Table 10. Operating-Mode Selection
MD1
MD0
OPERATING MODE
0
0
Normal Mode. Use this mode to perform normal conversions on the selected analog input channel.
Self-Calibration Mode. This mode performs self-calibration on the selected channel determined from CH0 and
CH1 selection bits in the communications register (Table 6). Upon completion of self-calibration, the device
returns to normal mode with MD0, MD1 returning to 0, 0. The DRDY output bit goes high when self-calibration is
requested and returns low when the calibration is complete and a new data word is in the data register. Self-
calibration performs an internal zero-scale and full-scale calibration. The analog inputs of the device are shorted
MX705
0
1
together internally during zero-scale calibration and connected to an internally generated (V
/ selected gain)
REF
voltage during full-scale calibration. The offset and gain registers for the selected channel are automatically
updated with the calibration data.
Zero-Scale System-Calibration Mode. This mode performs zero-scale calibration on the selected channel
determined from CH0 and CH1 selection bits in the communications register (Table 6). The DRDY output bit
goes high when calibration is requested and returns low when the calibration is complete and a new data word
is in the data register. Performing zero-scale calibration compensates for any DC offset voltage present in the
ADC and system. Ensure that the analog input voltage is stable within 1/2 LSB for the duration of the calibration
sequence. The offset register for the selected channel is updated with the zero-scale system-calibration data.
Upon completion of calibration, the device returns to normal mode with MD0, MD1 returning to 0, 0.
1
1
0
1
Full-Scale System-Calibration Mode. This mode performs full-scale system calibration on the selected channel
determined by the CH0 and CH1 selection bits in the communications register. This calibration assigns a full-
scale output code to the voltage present on the selected channel. Ensure that the analog input voltage is stable
within 1/2 LSB for the duration of the calibration sequence. The DRDY output bit goes high during calibration
and returns low when the calibration is complete and a new data word is in the data register. The gain register
for the selected channel is updated with the full-scale system-calibration data. Upon completion of calibration,
the device returns to normal mode with MD0, MD1 returning to 0, 0.
Data Register
Table 11. PGA Gain Selection
The data register is a 16-bit register that can be read
and written. Figure 9 shows how to read conversion
results using the data register. A write to the data regis-
ter is not required, but if the data register is written, the
device does not return to its normal state of waiting for
a write to the communications register until all 16 bits
have been written. The 16-bit data word written to the
data register is ignored.
G2
G1
G0
PGA GAIN
0
0
0
1
2
0
0
1
0
1
0
4
0
1
1
8
1
0
0
16
32
64
128
The data from the data register is read through DOUT.
DOUT changes on the falling edge of SCLK and is valid
on the rising edge of SCLK. The data register format is
16-bit straight binary for unipolar mode with zero scale
equal to 0x0000, and offset binary for bipolar mode
with zero scale equal to 0x1000.
1
0
1
1
1
0
1
1
1
Set CLK = 0 for optimal performance if the external
clock frequency is 1MHz with CLKDIV = 0 or 2MHz with
CLKDIV = 1.
FS1, FS0: (Default = 0, 1) Filter-Selection Bits. These bits
determine the output data rate and the digital-filter cutoff
frequency. See Table 13 for FS1 and FS0 settings.
Recalibrate when the filter characteristics are changed.
24 ______________________________________________________________________________________
16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADC
MX705
Test Register
This register is reserved for factory testing of the device.
For proper operation of the MX7705, do not change this
register from its default power-on reset values.
Write to the calibration registers in normal mode only.
After writing to the calibration registers, the devices
implement the new offset and gain-register calibration
coefficients at the beginning of a new acquisition. To
ensure the results are valid, discard the first conversion
result after writing to the calibration registers.
Offset and Gain-Calibration Registers
The MX7705 contains one offset register and one gain
register for each input channel. Each register is 24 bits
wide and can be written and read. The offset registers
store the calibration coefficients resulting from a zero-
scale calibration, and the gain registers store the cali-
bration coefficients resulting from a full-scale
calibration. The data stored in these registers are 24-bit
straight binary values representing the offset or gain
errors associated with the selected channel. A 24-bit
read or write operation can be performed on the cali-
bration registers for any selected channel. During a
write operation, 24 bits of data must be written to the
register, or no data is transferred.
To ensure that a conversion is not made using invalid
calibration data, drive FSYNC high prior to writing to the
calibration registers, and then release FSYNC low to ini-
tiate conversion.
Power-On Reset
At power-up, the serial-interface, logic, digital-filter, and
modulator circuits are reset. The registers are set to
their default values. The device returns to wait for a
write to the communications register. For accurate
measurements, perform calibration routines after
power-up. Allow time for the external reference and
oscillator to start up before starting calibration. See the
Typical Operating Characteristics for typical external-
oscillator startup times.
Table 12. Clock Register
FIRST BIT (MSB)
(LSB)
CLKOUT
DISABLE
CLOCK
DIVIDER
CLOCK
SELECT
FUNCTION
RESERVED
FILTER SELECT
Name
MXID ZERO ZERO
CLKDIS
0
CLKDIV
0
CLK
1
FS1
0
FS0
1
Defaults
1
0
0
Table 13. Output Data Rate and Notch Frequency vs. Filter Select and CLKIN Frequency
CLKIN FREQUENCY
(MHz)*
OUTPUT DATA RATE
(FIRST NOTCH) (Hz)
-3dB FILTER CUTOFF**
(Hz)
CLK
FS1
FS0
f
CLKIN
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
20
25
5.24
6.55
1
1
100
200
50
26.20
52.40
13.10
15.70
65.50
131.00
1
2.4576
2.4576
2.4576
2.4576
60
250
500
*These values are given for CLKDIV = 0. External clock frequency, f
, can be two times the values in this column if CLKDIV = 1.
**The filter -3dB filter cutoff frequency = 0.262 x filter first-notch frequency.
CLKIN
______________________________________________________________________________________ 25
16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADC
Reset
Table 14. Filter Select and Decimation Rate
Drive RESET low to reset the MX7705 to power-on reset
status. DRDY goes high and all communication to the
MX7705 is ignored while RESET is low. Upon releasing
RESET, the device must be reconfigured to begin a con-
version. The device returns to waiting for a write to the
communication register after a reset has been performed.
Perform a calibration sequence following a reset for
accurate conversions.
CLK
FS1
FS0
DECIMATION RATE
0
0
0
0
1
1
1
1
0
0
391
313
78
0
1
1
0
1
1
39
MX705
0
0
384
320
77
0
1
The MX7705 clock generator continues to run when
RESET is pulled low. This allows any device running from
CLKOUT to be uninterrupted when the device is in reset.
1
0
1
1
38
Selecting Custom Output Data Rates and
First-Notch Frequency
Writing to the clock and setup registers after configuring
and initializing the host processor serial port sets up the
MX7705. Use self- or system calibrations to minimize off-
set and gain errors (see the Calibration section for more
details). Set FSYNC = 0 to begin calibration or conver-
sion. The MX7705 performs free-running acquisitions
when FSYNC is low (see the Using FSYNC section). The
µC can poll the DRDY bit of the communications register
and read the data register when the DRDY bit returns a
0. For hardware polling, the DRDY output goes low when
the new data is valid in the data register.
The recommended frequency range of the external clock
is 400kHz to 5MHz. The output data rate and first notch
frequency are dependent on the decimation rate of the
digital filter. Table 14 shows the available decimation
rates of the digital filter. The output data rate and filter first
notch is calculated using the following formula:
f
CLKIN
output data rate =
× 0.5
128 × Decimation Rate
(if CLKDIV = 1)
The data register can be read multiple times while the
next conversion takes place.
f
CLKIN
output data rate =
The flow diagram in Figure 11 shows an example
sequence required to perform a conversion on channel
1 (AIN1+ / AIN1-) after a power-on reset.
128 × Decimation Rate
(if CLKDIV = 0)
Note: First-notch filter frequency = output data rate.
Performing a Conversion
At power-on reset, the MX7705 expects a write to the
communications register. Writing to the communica-
tions register selects the acquisition channel, read/write
operation for the next register, power-down/normal
mode, and address of the following register to be
accessed. The MX7705 has six user-accessible regis-
ters, which control the function of the device and allow
the result to be read. Write to the communications reg-
ister before accessing any other registers.
26 ______________________________________________________________________________________
16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADC
MX705
POWER-ON RESET
INITIALIZE μC/μP SERIAL
PORT
WRITE TO THE COMMUNICATIONS
REGISTER. SELECT CHANNEL 1 AND SET
NEXT OPERATION AS A WRITE TO THE
CLOCK REGISTER.
(0x20)
WRITE TO THE CLOCK REGISTER. ENABLE
EXTERNAL OSCILLATOR. SELECT
OUTPUT UPDATE RATE OF 60Hz.
(0xA5)
WRITE TO THE COMMUNICATIONS
REGISTER. SELECT CHANNEL 1 AND SET
NEXT OPERATION AS A WRITE TO THE
SETUP REGISTER.
(0x10)
WRITE TO THE SETUP REGISTER. SET
SELF-CALIBRATION MODE, GAIN TO 0,
UNIPOLAR MODE, UNBUFFERED MODE.
BEGIN SELF-CALIBRATION/CONVERSION
BY CLEARING FSYNC.
(0x44)
HARDWARE POLLING
SOFTWARE POLLING
WRITE TO COMMUNICATIONS REGISTER.
SET NEXT OPERATION AS A READ FROM
THE COMMUNICATIONS REGISTER.
(0x08)
POLL DRDY
OUTPUT
1 (DATA
NOT
READ THE COMMUNICATIONS REGISTER
(8 BITS)
READY)
POLL DRDY
BIT
1 (DATA NOT
READY)
WRITE TO THE COMMUNICATIONS
REGISTER. SET NEXT OPERATION AS A
READ FROM THE DATA REGISTER.
(0x38)
0 (DATA
READY)
0 (DATA
READY)
READ THE DATA REGISTER
(16 BITS)
Figure 11. Sample Flow Diagram for Data Conversion
______________________________________________________________________________________ 27
16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADC
Using FSYNC
When FSYNC = 1, the digital filter and analog modula-
tor are in a reset state, inhibiting normal operation. Set
FSYNC = 0 to begin calibration or conversion.
When zero-scale or full-scale calibration is selected,
DRDY goes low 4 x 1/output data rate + t after FSYNC
P
goes low (or while the zero-scale or full-scale calibra-
tion command is issued when FSYNC is already low) to
indicate new data in the data register (see the
Calibration section).
When configured for normal operation (MD0 and MD1
set to 0), DRDY goes low 3 x 1/output data rate after
FSYNC goes low to indicate that the new conversion
result is ready to be read from the data register. DRDY
returns high when a read operation on the data register
is complete. As long as FSYNC remains low, the
MX7705 performs free-running conversions with the
data registers updating at the output data rate. If the
valid data is not read before the next conversion result
Calibration
To compensate for errors introduced by temperature
variations or system DC offsets, perform an on-chip cal-
ibration. Select calibration options by writing to the
MD1 and MD0 bits in the setup register (Table 9).
Calibration removes gain and offset errors from the
device and/or the system. Recalibrate with changes in
ambient temperature, supply voltage, bipolar/unipolar
mode, PGA gain, and output data rate.
MX705
is ready, DRDY returns high for 500 x 1/f
before
CLKIN
going low again to indicate a new conversion. Set
FSYNC = 1 to stop converting data.
The MX7705 offers two calibration modes, self-calibra-
tion and system calibration. The channels of the
MX7705 are independently calibrated (Table 8). The
calibration coefficients resulting from a calibration
sequence on a selected channel are stored in the corre-
sponding offset and gain-register pair.
If FSYNC goes high while DRDY is low (indicating that
valid data has not yet been read from the data regis-
ter), DRDY does not reset high. DRDY remains low until
the new data is read from the data register or until
FSYNC goes low to begin a new conversion.
Table 15 provides the duration-to-mode bits and dura-
tion-to-DRDY for each calibration sequence. Duration-to-
mode bits provide the time required for the calibration
sequence to complete (MD1 and MD0 return to 0).
Duration-to-DRDY provides the time until the first conver-
sion result is valid in the data register (DRDY goes low).
Self- and system calibration automatically calculate the
offset and gain coefficients, which are written to the off-
set and gain registers. These offset and gain coeffi-
cients provide offset and gain-error correction for the
specified channel.
Self-Calibration
Self-calibration compensates for offset and gain errors
internal to the ADC. Prior to calibration, set the PGA gain,
unipolar/bipolar mode, and input channel setting. During
self-calibration, AIN+ and AIN- of the selected channel
are internally shorted together. The ADC calibrates this
condition as the zero-scale output level. For bipolar
mode, this zero-scale point is the midscale of the bipolar
transfer function.
The pipeline delay necessary to ensure that the first
conversion result is valid is t (t = 2000 x 1/f ).
CLKIN
P
P
When selecting self-calibration (MD1 = 0, MD0 = 1),
DRDY goes low 9 x 1/output data rate + t after FSYNC
P
goes low (or after a write operation to the setup register
with MD1 = 0 and MD0 = 1 is performed while FSYNC
is already low) to indicate new data in the data register.
The pipeline delay required to ensure that the first con-
version result is valid is t (t = 2000 x 1/f ).
CLKIN
P
P
Table 15. Calibration Sequences
CALIBRATION TYPE
DURATION-TO-MODE
DURATION TO DRDY**
BITS*
CALIBRATION SEQUENCE
(MD1, MD0)
Internal zero-scale calibration at
Self-calibration (0,1)
selected gain + internal full-scale
calibration at selected gain
6 x 1/output data rate
9 x 1/output data rate + t
P
Zero-scale calibration on AIN at
selected gain
Zero-scale system calibration (1,0)
Full-scale system calibration (1,1)
3 x 1/output data rate
3 x 1/output data rate
4 x 1/output data rate + t
4 x 1/output data rate + t
P
Full-scale calibration on AIN at
selected gain
P
*Duration-to-mode bits represents the completion of the calibration sequence.
**Duration to DRDY represents the time at which a new conversion result is available in the data register.
28 ______________________________________________________________________________________
16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADC
MX705
Next, an internally generated voltage (V
applied across AIN+ and AIN-. This condition results in
the full-scale calibration.
/ GAIN) is
After performing a zero-scale calibration, connect the
analog inputs to the full-scale voltage level (V
REF
/
REF
GAIN). Perform a full-scale calibration by setting MD1 =
1 and MD0 = 1. After 3 x 1/output data rate, MD1 and
MD0 both return to zero at the completion of full-scale
calibration. DRDY goes high at the beginning of cali-
bration and returns low after calibration is complete
and new data is in the data register (4 x 1/output data
rate). The time until DRDY goes low is comprised of
one full-scale calibration sequence (3 x 1/output data
rate) and one conversion on the AIN voltage (1 x 1/out-
put data rate). If DRDY is low before or goes low during
the calibration-command write to the setup register,
DRDY takes up to one additional modulator cycle
Start self-calibration by setting MD1 = 0, MD0 = 1, and
FSYNC = 0 in the setup register. Self-calibration com-
pletes in 6 x 1/output data rate. The MD1 and MD0 bits
both return to zero at the end of calibration. The device
returns to normal acquisition mode and performs a con-
version, which completes in 3 x 1/output data rate after
the self-calibration sequence.
The DRDY output goes high at the start of calibration
and falls low when the calibration is complete and the
next conversion result is valid in the data register. The
total time for self-calibration and one conversion (time
until DRDY goes low) is 9 x 1/output data rate. If DRDY
is low before or goes low during the calibration com-
mand write to the setup register, DRDY takes up to one
(128/f
) to return high to indicate a calibration or
CLKIN
conversion in progress.
In bipolar mode, the midpoint (zero scale) and positive
full scale of the transfer function are used to calculate the
calibration coefficients of the gain and offset registers. In
unipolar mode, system calibration is performed using the
two endpoints of the transfer function (Figures 4 and 5).
additional modulator cycle (128/f
) to return high to
CLKIN
indicate a calibration or conversion in progress.
System Calibration
System calibration compensates for offset and gain
errors for the entire analog signal path including the
ADC, signal conditioning, and signal source. System
calibration is a two-step process and requires individ-
ual zero-scale and full-scale calibrations on the select-
ed channel at a specified PGA gain. Recalibration is
recommended with changes in ambient temperature,
supply voltage, bipolar/unipolar mode, PGA gain, and
output data rate. Before starting calibration, set the
PGA gain and the desired channel.
Power-Down Modes
The MX7705 includes a power-down mode to save
power. Select power-down mode by setting PD = 1 in
the communications register. The PD bit does not affect
the serial interface or the status of the DRDY line. While
in power-down mode, the MX7705 retains the contents
of all of its registers. Placing the part in power-down
mode reduces current consumption to 2µA (typ) when
in external clock mode and with CLKIN connected to
V
or GND. If DRDY is high before the part enters
DD
Set the zero-scale reference point across AIN+ and AIN-.
Start the zero-scale calibration by setting MD1 = 1, MD0
= 0, and FSYNC = 0 in the setup register. When zero-
scale calibration is complete (3 x 1/output data rate),
MD1 and MD0 both return to zero. DRDY goes high at the
start of the zero-scale system calibration and returns low
when there is a valid word in the data register (4 x 1/out-
put data rate). The time until DRDY goes low is com-
prised of one zero-scale calibration sequence (3 x
1/output data rate) and one conversion on the AIN volt-
age (1 x 1/output data rate). If DRDY is low before or
goes low during the calibration command write to the
setup register, DRDY takes up to one additional modula-
power-down mode, then DRDY remains high until the
part returns to normal operation mode and new data is
available in the data register. If DRDY is low before the
part enters power-down mode, indicating new data in
the data register, the data register can be read during
power-down mode. DRDY goes high at the end of this
read operation. If the new data remains unread, DRDY
stays low until the MX7705 is taken out of power-down
mode and resumes data conversion. Resume normal
operation by setting PD = 0. The device begins a new
conversion with a result appearing in 3 x 1/output data
rate + t , where t = 2000 x 1/f , after PD is set to
CLKIN
P
P
0. If the clock is stopped during power-down mode,
allow sufficient time for the clock to start up before
resuming conversion.
tor cycle (128/f
) to return high to indicate a calibra-
CLKIN
tion or conversion in progress.
If CLKDIS = 0, CLKOUT remains active during power-
down mode to provide a clock source for other devices
in the system.
______________________________________________________________________________________ 29
16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADC
Applications Information
V
DD
Applications Examples
10μF
Strain-Gauge Measurement
Connect the differential inputs of the MX7705 to the
bridge network of the strain gauge. In Figure 12, the ana-
log positive supply voltage powers the bridge network
and the MX7705, along with the reference voltage in a
ratiometric configuration. The on-chip PGA allows the
MX7705 to handle an analog input voltage range as low
0.1μF
MX705
CLKIN
REF+
REF-
V
DD
0.1μF
R
REF
as 20mV to full scale.
CLKOUT
Temperature Measurement
0.1μF
Use the MX7705 for temperature measurements from a
thermocouple (Figure 13). Operate the MX7705 in
buffered mode to allow large decoupling capacitors at
the analog inputs. The decoupling capacitors eliminate
any noise pickup from the thermocouple leads. AIN1- is
biased up at the reference voltage to accommodate the
reduced common-mode input range in buffered mode.
CS
SCLK
DIN
MX7705
ACTIVE
GAUGE
R
AIN1+
AIN1-
DOUT
DRDY
RESET
DUMMY
GAUGE
R
GND
Optical Isolation
For applications that require an optically isolated inter-
face, see Figure 14. With 6N136-type optocouplers,
maximum clock speed is 4MHz. Maximum clock speed
is limited by the degree of mismatch between the indi-
vidual optocouplers. Faster optocouplers allow faster
signaling at a higher cost.
Figure 12. Strain-Gauge Measurement
Layout, Grounding, Bypassing
Use PC boards with separate analog and digital
ground planes. Connect the two ground planes togeth-
er at the MX7705 GND. Isolate the digital supply from
the analog with a low-value resistor (10Ω) or ferrite
bead when the analog and digital supplies come from
the same source.
V
DD
= 3V/5V*
10
μ
F
F
10
μ
V
DD
CLKIN
Ensure that digital return currents do not pass through
the analog ground and that return-current paths are low
impedance. A 5mA current flowing through a PC board
ground trace impedance of only 0.05Ω creates an error
voltage of about 250µV.
AIN1+
AIN1-
THERMOCOUPLE
JUNCTION
CLKOUT
MX7705
Layout the PC board to ensure digital and analog sig-
nal lines are kept separate. Do not run digital lines
(especially the SCLK and DOUT) parallel to any analog
lines. If they must cross another, do so at right angles.
SCLK
DIN
1.225V/2.5V
REFERENCE*
REF+
REF-
0.1
μ
F
F
DOUT
DRDY
RESET
Bypass V
to the analog ground plane with a 0.1µF
DD
0.1μ
capacitor in parallel with a 1µF to 10µF low-ESR capac-
itor. Keep capacitor leads short for best supply-noise
rejection. Bypass REF+ and REF- with a 0.1µF capaci-
tor to GND. Place all bypass capacitors as close to the
device as possible to achieve the best decoupling.
GND
*USE A 1.225V REFERENCE FOR V = 3V OR A 2.5V REFERENCE FOR V = 5V.
DD
DD
Figure 13. Temperature Measurement
30 ______________________________________________________________________________________
16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADC
MX705
Definitions
ISO
3V/5V
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line is either a best-straight-line fit or a line
drawn between the endpoints of the transfer function,
once offset and gain errors have been nullified. INL for
the MX7705 is measured using the endpoint method.
This is the more conservative method.
V
CC
V
DD
2kΩ
V
CC
DIN
6N136
100Ω
MOSI
MX7705
Unipolar Offset Error
For an ideal converter, the first transition occurs at 0.5
LSB above zero. Offset error is the amount of deviation
between the measured first transition point and the
ideal point.
2kΩ
V
CC
SCLK
6N136
100Ω
Bipolar Zero Error
In bipolar mode, the ideal midscale transition occurs at
AIN+ - AIN- = 0. Bipolar zero error is the measured
deviation from this ideal value.
SCK
V
CC
2kΩ
6N136
Gain Error
With a full-scale analog input voltage applied to the
ADC (resulting in all ones in the digital code), gain error
is defined as the amount of deviation between the ideal
transfer function and the measured transfer function
(with the offset error or bipolar zero error removed).
Gain error is usually expressed in LSB or a percent of
full-scale range (%FSR).
MISO
DOUT
CS
100Ω
CS
Positive Full-Scale Error
For the ideal transfer curve, the code edge transition
that causes a full-scale transition to occur is 1.5 LSB
below full scale. The positive full-scale error is the dif-
ference between this code transition of the ideal trans-
fer function and the actual measured value at this code
transition. Unlike gain error, unipolar offset error and
bipolar zero error are included in the positive full-scale
error measurement.
Figure 14. Optically Isolated Interface
both input terminals. The common-mode signal can be
either an AC or a DC signal or a combination of the two.
CMR is often expressed in decibels. Common-mode
rejection ratio (CMRR) is the ratio of the differential sig-
nal gain to the common-mode signal gain.
Bipolar Negative Full-Scale Error
For the ideal transfer curve, the code edge transition that
causes a negative full-scale transition to occur is 0.5 LSB
above negative full scale. The negative full-scale error is
the difference between this code transition of the ideal
transfer function and the actual measured value at this
code transition.
Power-Supply Rejection Ratio
Power-supply rejection ratio (PSRR) is the ratio of the
input signal change (V) to the change in the converter
output (V). It is typically measured in decibels.
Input Common-Mode Rejection
Input common-mode rejection (CMR) is the ability of a
device to reject a signal that is common to or applied to
______________________________________________________________________________________ 31
16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADC
Package Information
Chip Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in
the package code indicates RoHS status only. Package draw-
ings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.
TRANSISTOR COUNT: 42,000
PROCESS: BiCMOS
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
MX705
16 TSSOP
U16-2
21-0066
32 ______________________________________________________________________________________
16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADC
MX705
Revision History
REVISION REVISION
PAGES
DESCRIPTION
CHANGED
NUMBER
DATE
3
4
6/09
2/10
Corrected values in Reference section
Removed unreleased package options
18
1, 2, 32
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 33
© 2010 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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