MX7575KCWN [MAXIM]
CMOS, uP-Compatible, 5レs/10レs, 8-Bit ADCs; CMOS ，最高兼容，レ5秒/ 10レS， 8位ADC
| 型号： | MX7575KCWN |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | CMOS, uP-Compatible, 5レs/10レs, 8-Bit ADCs |
| 文件： | 总12页 (文件大小：106K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-0876; Rev 1; 5/96
CMOS , µP -Co m p a t ib le , 5 µs /1 0 µs , 8 -Bit ADCs
/MX576
_______________Ge n e ra l De s c rip t io n
____________________________Fe a t u re s
Maxim’s MX7575/MX7576 are high-speed (5µs/10µs),
microprocessor (µP) compatible, 8-bit analog-to-digital
converters (ADCs). The MX7575 provides an on-chip
track/hold function that allows full-scale signals up to
50kHz (386mV/µs slew rate) to be acquired and digi-
tized accurately. Both ADCs use a successive-approxi-
mation technique to achieve their fast conversions and
low power dissipation. The MX7575/MX7576 operate
with a +5V supply and a 1.23V external reference. They
♦ Fast Conversion Time: 5µs (MX7575)
10µs (MX7576)
♦ Built-In Track/Hold Function (MX7575)
♦ Low Total Unadjusted Error (±1LSB max)
♦ 50kHz Full-Power Signal Bandwidth (MX7575)
♦ Single +5V Supply Operation
♦ 8-Bit µP Interface
accept input voltages ranging from 0V to 2V
.
REF
♦ 100ns Data-Access Time
The MX7575/MX7576 are easily interfaced to all popu-
lar 8-bit µPs through standard CS and RD control sig-
nals. These signals control conversion start and data
access. A BUSY signal indicates the beginning and
end of a conversion. Since all the data outputs are
latched and three-state buffered, the MX7575/MX7576
can be directly tied to a µP data bus or system l/O port.
♦ Low Power: 15mW
♦ Small-Footprint Packages
______________Ord e rin g In fo rm a t io n
INL
(LSB)
PART
TEMP. RANGE
PIN-PACKAGE
Maxim also makes the MAX165, a plug-in replacement
for the MX7575 with an internal 1.23V reference. For
applications that require a differential analog input and
an internal reference, the MAX166 is recommended.
MX7575JN
MX7575KN
MX7575JCWN
MX7575KCWN
MX7575JP
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
-25°C to +85°C
-25°C to +85°C
18 Plastic DIP
18 Plastic DIP
18 Wide SO
18 Wide SO
20 PLCC
±1
±1/2
±1
±1/2
±1
________________________Ap p lic a t io n s
Digital Signal Processing
High-Speed Data Acquisition
Telecommunications
MX7575KP
MX7575J/D
MX7575AQ
MX7575BQ
20 PLCC
±1/2
±1
Dice*
18 CERDIP**
18 CERDIP**
±1
±1/2
Audio Systems
Ordering Information continued at end of data sheet.
Contact factory for dice specifications.
** Contact factory for availability.
High-Speed Servo Loops
Low-Power Data Loggers
*
_________________P in Co n fig u ra t io n s
_______________Fu n c t io n a l Dia g ra m s
V
DD
TOP VIEW
18
1
2
3
4
5
6
7
8
9
CS
RD
V
DD
18
MX7575
16
TRACK/
HOLD
17 REF
16 AIN
AIN
COMP
MX7575
MX7576
TP (MODE)
BUSY
CLK
15
17
AGND
REF
15
14
13
12
11
10
AGND
D0 (LSB)
D1
DAC
SAR
CLOCK
OSCILLATOR
5
CLK
D7 (MSB)
D6
D2
6
1
2
3
CS
RD
TP
D7
.
LATCH AND
THREE-STATE
OUTPUT DRIVERS
D5
D3
CONTROL
LOGIC
.
D0
DGND
D4
14
4
9
DIP/SO
( ) ARE FOR MX7576 ONLY.
BUSY
DGND
Pin Configurations continued at end of data sheet.
Functional Diagrams continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
CMOS , µP -Co m p a t ib le , 5 µs /1 0 µs , 8 -Bit ADCs
ABSOLUTE MAXIMUM RATINGS
V
DD
to AGND...............................................................-0.3V, +7V
Continuous Power Dissipation (T = +70°C)
A
V
to DGND ..............................................................-0.3V, +7V
Plastic DIP (derate 11.11mW/°C above +70°C) ...............889mW
Wide SO (derate 9.52mW/°C above +70°C)..................762mW
CERDIP (derate 10.53mW/°C above +70°C).................842mW
PLCC (derate 10.00mW/°C above +70°C) ....................800mW
Operating Temperature Ranges
DD
AGND to DGND...............................................-0.3V, V + 0.3V
Digital Input Voltage to DGND
(CS, RD, TP, MODE)......................................-0.3V, V + 0.3V
Digital Output Voltage to DGND
DD
DD
(BUSY, D0–D7) ..............................................-0.3V, V + 0.3V
MX757_J/K............................................................0°C to +70°C
MX757_A/B ........................................................-25°C to +85°C
MX757_JE/KE ....................................................-40°C to +85°C
MX757_S/T.......................................................-55°C to +125°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering,10sec) ..............................+300°C
DD
CLK Input Voltage to DGND............................-0.3V, V + 0.3V
DD
REF to AGND...................................................-0.3V, V + 0.3V
DD
AIN to AGND....................................................-0.3V, V + 0.3V
DD
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
/MX576
ELECTRICAL CHARACTERISTICS
(V
= +5V; V
= 1.23V; AGND = DGND = 0V; f
= 4MHz e xte rna l for MX7575; f
= 2MHz e xte rna l for MX7576;
DD
REF
CLK
CLK
T
A
= T
to T , unless otherwise noted.)
MAX
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ACCURACY
Resolution
8
Bits
MX757_K/B/T
MX757_J/A/S
MX757_K/B/T
MX757_J/A/S
±1
±2
Total Unadjusted Error
Relative Accuracy
TUE
INL
LSB
±1/2
±1
LSB
No-Missing-Codes Resolution
Full-Scale Error
8
Bits
LSB
±1
Full-Scale Tempco
Offset Error (Note 1)
Offset Tempco
±5
±5
ppm/°C
LSB
±1/2
ppm/°C
ANALOG INPUT
Voltage Range
1LSB = 2V /256
REF
0
2V
V
MΩ
V/µs
dB
REF
DC Input Impedance
Slew Rate, Tracking
Signal-to-Noise Ratio (Note 2)
REFERENCE INPUT
Reference Voltage
10
MX7575
0.386
SNR
MX7575, V = 2.46V at 10kHz, Figure 13
45
IN
p-p
V
REF
±5% variation for specified performance
1.23
V
Reference Current
I
500
0.8
µA
REF
LOGIC INPUTS CS, RD, MODE
Input Low Voltage
V
V
V
INL
Input High Voltage
V
2.4
INH
T
= +25°C
±1
±10
10
A
Input Current
I
V
IN
= 0V or V
DD
µA
pF
IN
T
A
= T to T
MIN MAX
Input Capacitance (Note 2)
C
IN
2
_______________________________________________________________________________________
CMOS , µP -Co m p a t ib le , 5 µs /1 0 µs , 8 -Bit ADCs
/MX576
ELECTRICAL CHARACTERISTICS (continued)
(V
= +5V; V
= 1.23V; AGND = DGND = 0V; f
= 4MHz e xte rna l for MX7575; f
= 2MHz e xte rna l for MX7576;
DD
REF
CLK
CLK
T
A
= T
to T , unless otherwise noted.)
MAX
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CLOCK
Input Low Voltage
Input High Voltage
V
0.8
V
V
INL
V
INH
2.4
MX757_J/A/K/B
MX757_S/T
700
800
700
800
Input Low Current
Input High Current
I
V
= 0V
µA
µA
INL
IN
MX757_J/A/K/B
MX757_S/T
I
V
= V
INH
IN DD
LOGIC OUTPUTS (D0–D7, BUSY)
Output Low Voltage
V
I
= 1.6mA
0.4
V
V
OL
SINK
Output High Voltage
V
OH
I
= 40µA
4.0
SOURCE
T
= +25°C
±1
A
Floating State Leakage Current
V
= 0V to V , D0–D7
µA
pF
OUT
DD
T
A
= T
to T
MAX
±10
MIN
Floating State Output
Capacitance (Note 2)
D0–D7
10
CONVERSION TIME (Note 3)
MX7575: f
MX7576: f
= 4MHz
= 2MHz
5
Conversion Time with
External Clock
CLK
µs
µs
10
CLK
Using recommended
clock components:
MX7575
MX7576
5
15
30
Conversion Time with
Internal Clock
R
C
= 100kΩ,
= 100pF;
CLK
CLK
10
T
A
= +25°C
POWER REQUIREMENTS (Note 4)
Supply Voltage
V
±5% for specified performance
MX757_J/A/K/B
5
3
V
DD
6
7
Supply Current
I
DD
mA
MX757_S/T
Power Dissipation
15
mW
LSB
Power-Supply Rejection
4.75V < V < 5.25V
±1/4
DD
Note 1: Offset Error is measured with respect to an ideal first-code transition that occurs at 1/2LSB.
Note 2: Sample tested at +25°C to ensure compliance.
Note 3: Accuracy may degrade at conversion times other than those specified.
Note 4: Power-supply current is measured when MX7575/MX7576 are inactive, i.e.:
For MX7575 CS = RD = BUSY = high;
For MX7576 CS = RD = BUSY = MODE = high.
_______________________________________________________________________________________
3
CMOS , µP -Co m p a t ib le , 5 µs /1 0 µs , 8 -Bit ADCs
TIMING CHARACTERISTICS (Note 5)
(V = +5V, V
= 1.23V, AGND = DGND = 0V.)
DD
REF
T
A
= +25°C
ALL
T
= T
to T
MIN MAX
A
PARAMETER
SYMBOL CONDITIONS
J/K/A/B
S/T
UNITS
MIN
MAX
MIN
MAX
MIN
MAX
t
t
t
t
t
t
t
t
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
CS to RD Setup Time
RD to BUSY Propagation Time
Data-Access Time after RD
RD Pulse Width
1
2
3
4
5
6
7
8
100
100
100
100
120
120
(Note 6)
100
0
100
0
120
0
CS to RD Hold Time
(Note 6)
(Note 7)
80
80
80
80
100
100
Data-Access Time after BUSY
Data-Hold Time
10
0
10
0
10
0
/MX576
BUSY to CS Delay
Note 5: Timing specifications are sample tested at +25°C to ensure compliance. All input control signals are specified with
t = t = 20ns (10% to 90% of +5V) and timed from a voltage level of 1.6V.
r
f
Note 6: t and t are measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8V or 2.4V.
3
6
Note 7: t is defined as the time required for the data lines to change 0.5V when loaded with the circuits of Figure 2.
7
______________________________________________________________P in De s c rip t io n
PIN
NAME
FUNCTION
DIP/SO
PLCC
1
2
CS
RD
Chip Select Input. CS must be low for the device to be selected or to recognize the RD input.
Read Input. RD must be low to access data. RD is also used to start conversions. See the
Microprocessor Interface section.
2
3
4
3
4
5
TP
(MX7575)
Test Point. Connect to V
.
DD
MODE
Mode Input. MODE = low puts the ADC into its asynchronous conversion mode. MODE has to be
(MX7576) tied high for the synchronous conversion mode and the ROM interface mode.
BUSY Output. BUSY going low indicates the start of a conversion. BUSY going high indicates the
end of a conversion.
BUSY
5
6
6
7
CLK
D7
External Clock Input/Internal Oscillator Pin for frequency setting RC components.
Three-State Data Output, bit 7 (MSB)
Three-State Data Outputs, bits 6 and 5
Digital Ground
7, 8
9
8, 9
10
D6, D5
DGND
D4–D1
D0
10–13
14
12–15
16
Three-State Data Outputs, bits 4–1
Three-State Data Output, bit 0 (LSB)
Analog Ground
15
17
AGND
AIN
16
18
Analog Input. 0V to 2V
input range.
REF
17
19
REF
Reference Input. +1.23V nominal.
Power-Supply Voltage. +5V nominal.
No Connect
18
20
V
DD
—
1, 11
N.C.
4
_______________________________________________________________________________________
CMOS , µP -Co m p a t ib le , 5 µs /1 0 µs , 8 -Bit ADCs
/MX576
+5V
+5V
3k
3k
D_
D_
D_
D_
3k
100pF
100pF
3k
10pF
10pF
DGND
DGND
b) HIGH-Z TO V
DGND
a) V TO HIGH-Z
DGND
b) V TO HIGH-Z
a) HIGH-Z TO V
OH
OL
OH
OL
NOTE: D_ REPRESENTS ANY OF THE DATA OUTPUTS
NOTE: D_ REPRESENTS ANY OF THE DATA OUTPUTS
Figure 2. Load Circuits for Data-Hold Time Test
Figure 1. Load Circuits for Data-Access Time Test
are performed. In the slow-memory interface mode, CS
and RD are taken low to start a conversion and they
remain low until the conversion ends, at which time the
conversion result is latched. This mode is designed for
µPs that can be forced into a wait state. In the ROM
interface mode, however, the µP is not forced into a wait
state. A conversion is started by taking CS and RD low,
and data from the previous conversion is read. At the
end of the most recent conversion, the µP executes a
read instruction and starts another conversion.
_______________De t a ile d De s c rip t io n
Co n ve rt e r Op e ra t io n
The MX7575 and MX7576 use the successive-approxi-
mation technique to convert an unknown analog input
voltage to an 8-bit digital output code (see Functional
Diagrams). The MX7575 samples the input voltage on
an internal capacitor once (at the beginning of the con-
version), while the MX7576 samples the input signal
e ig ht time s d uring the c onve rs ion (s e e MX7575
Track/Hold and MX7576 Analog Input sections). The
internal DAC is initially set to half scale, and the com-
parator determines whether the input signal is larger
than or smaller than half scale. If it is larger than half
scale, the DAC MSB is kept. But if it is smaller, the MSB
is dropped. At the end of each comparison phase, the
SAR (successive-approximation register) stores the
results of the previous decision and determines the
next trial bit. This information is then loaded into the
DAC after each decision. As the conversion proceeds,
the analog input is approximated more closely by com-
paring it to the combination of the previous DAC bits
and a new DAC trial bit. After eight comparison cycles,
the eight bits stored in the SAR are latched into the out-
put latches. At the end of the conversion, the BUSY sig-
nal goes high, and the data in the output latches is
ready for microprocessor (µP) access. Furthermore, the
DAC is reset to half scale in preparation for the next
conversion.
For the MX7575, TP should be hard-wired to V
to
DD
ensure proper operation of the device. Spurious signals
may occur on TP, or excessive currents may be drawn
from V if TP is left open or tied to a voltage other than
DD
V
DD
.
Slow-Memory Mode
Figure 3 shows the timing diagram for slow-memory
interface mode. This is used with µPs that have a wait-
state capability of at least 10µs (such as the 8085A),
where a read instruction is extended to accommodate
slow-memory devices. A conversion is started by exe-
cuting a memory read to the device (taking CS and RD
low). The BUSY signal (which is connected to the µP
READY input) then goes low and forces the µP into a
wait state. The MX7575 track/hold, which had been
tracking the analog input signal, holds the signal on the
third falling clock edge after RD goes low (Figure 12).
The MX7576, however, samples the analog input eight
times during a conversion (once before each compara-
tor d e c is ion). At the e nd of the c onve rs ion, BUSY
returns high, the output latches and buffers are updat-
ed with the new conversion result, and the µP com-
pletes the memory read by acquiring this new data.
Mic ro p ro c e s s o r In t e rfa c e
The CS and RD logic inputs are used to initiate conver-
sions and to access data from the devices. The MX7575
and MX7576 have two common interface modes: slow-
memory interface mode and ROM interface mode. In
addition, the MX7576 has an asynchronous conversion
mode (MODE pin = low) where continuous conversions
The fa s t c onve rs ion time of the MX7575/MX7576
ensures that the µP is not forced into a wait state for an
excessive amount of time. Faster versions of many µPs,
_______________________________________________________________________________________
5
CMOS , µP -Co m p a t ib le , 5 µs /1 0 µs , 8 -Bit ADCs
CS
RD
CS
t
5
t
1
t
1
t
5
RD
t
4
t
2
t
8
t
2
t
CONV
BUSY
DATA
BUSY
DATA
t
t
6
t
7
t
3
t
3
t
t
7
7
3
HIGH-
HIGH-
IMPEDANCE
BUS
HIGH-
IMPEDANCE
BUS
HIGH-
IMPEDANCE
BUS
NEW
DATA
OLD
DATA
NEW
DATA
OLD DATA
IMPEDANCE
BUS
HIGH-IMPEDANCE BUS
Figure 5. ROM Interface Timing Diagram
Figure 3. Slow-Memory Interface Timing Diagram
A8–A15
8085A-2
ADDRESS BUS
A0–A15
ADDRESS BUS
ADDRESS
+5V
+5V
TP/MODE
CS
TP/MODE
6502-6809
R/W
/MX576
ADDRESS
DECODE
MX7575*
CS
EN
MX7575*
MX7576
DECODE
MX7576
S0
RD
BUSY
RD
Φ2 OR E
ADDRESS
LATCH
ALE
D0–D7
D0–D7
AD0–AD7
READY
DATA BUS
D0–D7
DATA BUS
* SOME CIRCUITRY OMITTED FOR CLARITY
S0 IS LOW FOR READ CYCLES
* SOME CIRCUITRY OMITTED FOR CLARITY
Figure 4. MX7575/MX7576 to 8085A-2 Slow-Memory Interface
Figure 6. MX7575/MX7576 to 6502/6809 ROM Interface
including the 8085A-2, test the status of the READY
input immediately after the start of an instruction cycle.
Therefore, if the MX7575/MX7576 are to be effective in
placing the µP in a wait state, their BUSY output should
go low very early in the cycle. When using the 8085A-2,
the earliest possible indication of an upcoming read
operation is provided by the S0 status signal. Thus, S0,
which is low for a read cycle, should be connected to
the RD input of the MX7575/MX7576. Figure 4 shows
the c onne c tion d ia g ra m for the 8085A-2 to the
MX7575/MX7576 in slow-memory interface mode.
external clock period of BUSY going high, then the sec-
ond conversion is not started. Furthermore, for correct
operation in this mode, RD and CS should not go low
before BUSY returns high.
Figures 6 and 7 show the connection diagrams for
interfacing the MX7575/MX7576 in the ROM interface
mode. Figure 6 shows the connection diagram for the
6502/6809 µPs, and Figure 7 shows the connections for
the Z-80.
Due to their fast interface timing, the MX7575/MX7576
will interface to the TMS32010 running at up to 18MHz.
Fig ure 8 s hows the c onne c tion d ia g ra m for the
TMS32010. In this example, the MX7575/MX7576 are
mapped as a port address. A conversion is initiated by
using an IN A and a PA instruction, and the conversion
result is placed in the TMS32010 accumulator.
ROM Interface Mode
Figure 5 shows the timing diagram for ROM interface
mode. In this mode, the µP does not need to be placed
in a wait state. A conversion is started with a read
ins truc tion (RD a nd CS g o low), a nd old d a ta is
accessed. The BUSY signal then goes low to indicate
the s ta rt of a c onve rs ion. As b e fore , the MX7575
track/hold acquires the signal on the third falling clock
edge after RD goes low, while the MX7576 samples it
eight times during a conversion. At the end of a conver-
sion (BUSY going high), another read instruction always
accesses the new data and normally starts a second
conversion. However, if RD and CS go low within one
Asynchronous Conversion Mode (MX7576)
Tying the MODE pin low places the MX7576 into a con-
tinuous conversion mode. The RD and CS inputs are
only used for reading data from the converter. Figure 9
shows the timing diagram for this mode of operation,
and Figure 10 shows the connection diagram for the
8085A. In this mode, the MX7576 looks like a ROM to
6
_______________________________________________________________________________________
CMOS , µP -Co m p a t ib le , 5 µs /1 0 µs , 8 -Bit ADCs
/MX576
UPDATE
LATCH
DEFER
UPDATING
ADDRESS BUS
Z-80
+5V
TP/MODE
CS
CS
ADDRESS
DECODE
MREQ
EN
MX7575*
t
1
t
5
MX7576
t
4
RD
RD
RD
D7
D0
BUSY
t
t
7
3
DB7
DB0
HIGH-
IMPEDANCE
BUS
HIGH-
IMPEDANCE
BUS
DATA BUS
VALID
DATA
VALID
DATA
DATA
HIGH-IMPEDANCE BUS
* SOME CIRCUITRY OMITTED FOR CLARITY
Figure 7. MX7575/MX7576 to Z-80 ROM Interface
Figure 9. MX7576 Asynchronous Conversion Mode Timing
Diagram
PA2
A0–A15
ADDRESS BUS
ADDRESS BUS
PA0
+5V
MODE
CS
TP/MODE
TMS32010
8085A
ADDRESS
ENCODE
ADDRESS
MEN
CS
EN
MX7576*
MX7575*
MX7576
DECODE
RD
RD
RD
DEN
ADDRESS
LATCH
ALE
D7
D0
D0–D7
AD0–AD7
DATA BUS
DB7
DB0
DATA BUS
* SOME CIRCUITRY OMITTED FOR CLARITY
* SOME CIRCUITRY OMITTED FOR CLARITY
Figure 10. MX7576 to 8085A Asynchronous Conversion Mode
Interface
Figure 8. MX7575/MX7576 to TMS32010 ROM Interface
the µP, in that data can be accessed independently of
the clock. The output latches are normally updated on
the rising edge of BUSY. But if CS and RD are low
when BUSY goes high, the data latches are not updat-
ed until one of these inputs returns high. Additionally,
the MX7576 stops converting and BUSY stays high until
RD or CS goes high. This mode of operation allows a
simple interface to the µP.
the CLK input to the ADC (both should be derived from
the same source), because the sampling instants occur
three clock cycles after CS and RD go low. Therefore,
the sampling instants occur at exactly equal intervals if
the conversions are started at equal intervals. In this
scheme, the output data is fed into a FIFO latch, which
allows the µP to access data at its own rate. This guar-
antees that data is not read from the ADC in the middle
of a conversion. If data is read from the ADC during a
conversion, the conversion in progress may be dis -
turbed, but the accessed data that belonged to the pre-
vious conversion will be correct.
Processor Interface for Signal Acquisition (MX7575)
In many applications, it is necessary to sample the
input signal at exactly equal intervals to minimize errors
due to sampling uncertainty or jitter. In order to achieve
this objective with the previously discussed interfaces,
the user must match software delays or count the num-
ber of elapsed clock cycles. This becomes difficult in
interrupt-driven systems where the uncertainty in inter-
rupt servicing delays is another complicating factor.
The tra c k/hold sta rts hold ing the input on the third
falling edge of the clock after CS and RD go low. If CS
and RD go low within 20ns of a falling clock edge, the
ADC may or may not consider this falling edge as the
first of the three edges that determine the sampling
ins ta nt. The re fore , the CS a nd RD s hould not b e
allowed to go low within this period when sampling
accuracy is required.
The solution is to use a real-time clock to control the
start of a conversion. This should be synchronous with
_______________________________________________________________________________________
7
CMOS , µP -Co m p a t ib le , 5 µs /1 0 µs , 8 -Bit ADCs
MX7 5 7 5 Tra c k /Ho ld
The track/hold consists of a sampling capacitor and a
switch to capture the input signal. The simplified dia-
gram of this block is shown in Figure 11. At the begin-
ning of the conversion, switch S1 is closed, and the
input signal is tracked. The input signal is held (switch
S1 opens) on the third falling edge of clock after CS
and RD go low (Figure 12). This allows a minimum of
two clock cycles for the input capacitor to be charged
to the input voltage through the switch resistance. The
time required for the hold capacitor to settle to ±1/4LSB
is typically 7ns. Therefore, the input signal is allowed
a mp le time to s e ttle b e fore it is a c q uire d b y the
track/hold. When a conversion ends, switch S1 closes,
and the input signal is tracked.
MX7 5 7 6 An a lo g In p u t
The MX7576 analog input can also be modeled with the
switch and capacitor as shown in Figure 11. However,
unlike the MX7575, the MX7576 samples the input volt-
age eight times during a conversion (once before each
comparator decision). Therefore, the precautions that
apply to the MX7575 also apply to the MX7576. These
include minimizing the analog source impedance and
reducing noise coupling from the digital circuitry during
a conversion, especially near a sampling instant.
Re fe re n c e In p u t
The high speed of this ADC can be partially attributed to
the “inverted voltage output” topology of the DAC that it
uses. This topology provides low offset and gain errors
and fast settling times. The input current to the DAC,
however, is not constant. During a conversion, as differ-
ent DAC codes are tried, the DC impedance of the DAC
can vary between 6kΩ and 18kΩ. Furthermore, when
the DAC codes change, small amounts of transient cur-
rent are drawn from the reference input. These charac-
teristics require a low DC and AC driving impedance for
the reference circuitry to minimize conversion errors.
The track/hold is capable of acquiring signals with slew
rates of up to 386mV/µs (or equivalently a 50kHz sine
wave with 2.46Vp-p amplitude). Figure 13 shows the
signal-to-noise ratio (SNR) versus input frequency for
the ADC. The SNR plot is generated at a sampling rate
of 200kHz using sinusoidal inputs with a peak-to-peak
amplitude of 2.46V. The reconstructed sine wave is
passed through a 50kHz 8th-order Chebychev filter.
The improvement in SNR at high frequencies is due to
the filter cutoff.
/MX576
Figure 15 shows the reference circuitry recommended
to drive the reference input of the MX7575/MX7576.
The switching nature of the analog input results in tran-
sient currents that charge the input capacitance of the
track/hold. Keep the driving source impedance low
(below 2kΩ), so that the settling characteristics of the
track/hold are not degraded. A low driving impedance
also minimizes undesirable noise pickup and reduces
DC errors caused by transient currents at the analog
input. As with any ADC, it is important to keep external
sources of noise to a minimum during a conversion.
Therefore, keep the data bus as quiet as possible dur-
ing a conversion, especially when the track/hold is
making the transition to the hold mode.
CS
RD
BUSY
EXTERNAL
CLOCK
INPUT SIGNAL HELD HERE
a) WITH EXTERNAL CLOCK
For conversion times that are significantly longer than
5µs, the device’s accuracy may degrade slightly, as
shown in Figure 14. This degradation is due to the
charge that is lost from the hold capacitor in the pres-
ence of small on-chip leakage currents.
CS
RD
BUSY
R
500Ω
ON
S1
V
IN
INTERNAL
INPUT SIGNAL HELD HERE
CLOCK
C
S
C
H
0.5pF
2pF
b) WITH INTERNAL CLOCK
Figure 12. MX7575 Track/Hold (Slow-Memory Interface)
Timing Diagrams
Figure 11. Equivalent Input Circuit
8
_______________________________________________________________________________________
CMOS , µP -Co m p a t ib le , 5 µs /1 0 µs , 8 -Bit ADCs
/MX576
The decoupling capacitors are necessary to provide a
low AC source impedance.
40
T = +25°C
A
In t e rn a l/Ex t e rn a l Clo c k
The MX7575/MX7576 can be run with either an exter-
nally applied clock or their internal clock. In either case,
the signal appearing at the clock pin is internally divid-
ed by two to provide an internal clock signal that is rela-
tive ly ins e ns itive to the inp ut c loc k d uty c yc le .
Therefore, a single conversion takes 20 input clock
cycles, which corresponds to 10 internal clock cycles.
42
44
46
48
50
52
54
Internal Clock
The internal oscillator frequency is set by an external
capacitor, C
, and an external resistor, R
, which
CLK
CLK
100
1k
10k
100k
are connected as shown in Figure 16a. During a con-
version, a sawtooth waveform is generated on the CLK
INPUT FREQUENCY (Hz)
pin by charging C
through R
and discharging it
CLK
CLK
through an internal switch. At the end of a conversion,
the internal oscillator is shut down by clamping the CLK
Figure 13. MX7575 SNR vs. Input Frequency
pin to V through an internal switch. The circuit for the
DD
inte rna l os c illa tor c a n e a s ily b e ove rd rive n with a n
external clock source.
The inte rna l os c illa tor p rovid e s a c onve nie nt c loc k
source for the MX7575. Figure 17 shows typical conver-
sion times versus temperature for the recommended
2.5
A: T = +125°C
A
B: T = +85°C
A
C: T = +25°C
A
2.0
R
and C
combination. Due to process varia-
CLK
CLK
tions, the oscillation frequency for this R
/C
com-
CLK CLK
1.5
1.0
0.5
b ina tion ma y va ry b y a s muc h a s ± 50% from the
nominal value shown in Figure 17. Therefore, an exter-
nal clock should be used in the following situations:
1) Applications that require the conversion time to be
within 50% of the minimum conversion time for the
specified accuracy (5µs MX7575/10µs MX7576).
A
B
C
2) Applications in which time-related software con-
straints cannot accommodate conversion-time differ-
e nc e s tha t ma y oc c ur from unit to unit or ove r
temperature for a given device.
0
10
100
1000
10000
CONVERSION TIME (µs)
Figure 14. MX7575 Accuracy vs. Conversion Time
External Clock
The CLK input of the MX7575/MX7576 may be driven
directly by a 74HC or 4000B series buffer (e g., 4049),
or by an LS TTL output with a 5.6kΩ pull-up resistor. At
the end of a conversion, the device ignores the clock
input and disables its internal clock signal. Therefore,
the external clock may continue to run between conver-
sions without being disabled. The duty cycle of the
e xte rna l c loc k ma y va ry from 30% to 70%. As d is -
cussed previously, in order to maintain accuracy, clock
ra te s s ig nific a ntly lowe r tha n the d a ta s he e t limits
(4MHz for MX7575 and 2MHz for MX7576) should not
be used.
+5V
3.3k
1.23V
REF
+
+
ICL8069
47µF
0.1µF
_
Figure 15. External Reference Circuit
_______________________________________________________________________________________
9
CMOS , µP -Co m p a t ib le , 5 µs /1 0 µs , 8 -Bit ADCs
OUTPUT
CODE
+5V
FULL-SCALE
TRANSITION
(FS - 3/2LSB)
47µF
0.1µF
+5V
1111 1111
1111 1110
1111 1101
R
CLK
+5V
18
V
DD
AIN
REF
100k, 2%
5
4
1
2
3
16
17
15
CLK
BUSY
CS
2.46V(max)
3.3k
C
CLK
100pF, 1%
+1.23V
0.1µF
0000 0011
0000 0010
0000 0001
0000 0000
FS = 2V
REF
+
47µF
2FS
RD
TP/
MODE
1LSB = –––
CONTROL INPUTS
256
-
AGND
D7–D0
DATA OUT
MX7575
MX7576
0
1LSB 3LSBs
2LSBs
AIN, INPUT VOLTAGE (IN TERMS OF LSBs)
FS - 1LSB
9
/MX576
Figure 16a. Unipolar Configuration
Figure 16b. Nominal Transfer Characteristic for Unipolar
Operation
accurate enough that calibration will not be necessary. If
calibration is not needed, resistors R1–R7 should have a
0.1% tolerance, with R4 and R5 replaced by one 10kΩ
resistor, and R2 and R3 with one 1kΩ resistor. If calibra-
tion is required, follow the steps in the sections below.
______________ Typ ic a l Ap p lic a t io n s
Un ip o la r Op e ra t io n
Figure 16a shows the analog circuit connections for
unipolar operation, and Figure 16b shows the nominal
transfer characteristic for unipolar operation. Since the
offset and full-scale errors of the MX7575/MX7576 are
very small, it is not necessary to null these errors in
most cases. If calibration is required, follow the steps in
the sections below.
Offset Adjust
Adjust the offset error by applying an analog input volt-
age of 2.43V (+FS - 3/2LSB). Then adjust resistor R5
until the output code flickers between 1111 1110 and
1111 1111.
Offset Adjust
The offset error can be adjusted by using the offset trim
capability of an op amp (when it is used as a voltage fol-
lower) to drive the analog input, AIN. The op amp should
have a common-mode input range that includes 0V. Set
its initial input to 4.8mV (1/2LSB), while varying its offset
until the ADC output code flickers between 0000 0000
and 0000 0001.
Full-Scale Adjust
Null the full-scale error by applying an analog input
voltage of -2.45V (-FS + 1/2LSB). Then adjust resistor
R3 until the output code flickers between 0000 0000
and 0000 0001.
14
13
MX7576
Full-Scale Adjustment
Make the full-scale adjustment by forcing the analog
input, AIN, to 2.445V (FS - 3/2LSB). Then vary the refer-
ence input voltage until the ADC output code flickers
between 1111 1110 and 1111 1111.
MX7575
12
11
10
Bip o la r Op e ra t io n
Figure 18a shows an example of the circuit connection
for bipolar operation, and Figure 18b shows the nominal
transfer characteristic for bipolar operation. The output
code provided by the MX7575 is offset binary. The ana-
log inp ut ra ng e for this c irc uit is ± 2.46V (1LSB =
19.22mV), even though the voltage appearing at AIN is
in the 0V to 2.46V range. In most cases, the MX7575 is
9
8
R
C
CLK
= 100kΩ
= 100pF
CLK
7
-55 -25
0
25 50
75 100 125
AMBIENT TEMPERATURE (°C)
Figure 17. Typical Conversion Times vs. Temperature Using
Internal Clock
10 ______________________________________________________________________________________
CMOS , µP -Co m p a t ib le , 5 µs /1 0 µs , 8 -Bit ADCs
/MX576
+5V
47µF
+5V
OUTPUT
CODE
0.1µF
+5V
R
CLK
18
V
DD
111...111
5
R6
17
CLK
REF
111...110
3.3k
C
L
+5V
TLC271
100pF
2%
100...010
100...001
100...000
011...111
011...110
0.1µF 47µF
+
MX7575
ICL8069
1.2V
REFERENCE
-FS
2
-1/2LSB
R1
1k
R5
5k
AIN
FS
2
16
-1LSB
1/2LSB
AIN
AGND DGND
D7–D0
DATA OUT
R4
8.2k
R2
820Ω
15
9
FS = 2V
REF
000...001
000...000
2FS
256
R7
10k
R3
500Ω
1LSB =
INPUT VOLTAGE
Figure 18a. MX7575 Bipolar Configuration
Figure 18b. Nominal Transfer Characteristic for Bipolar
Operation
__________Ap p lic a t io n s In fo rm a t io n
__Fu n c t io n a l Dia g ra m s (c o n t in u e d )
No is e
To minimize noise coupling, keep both the input signal
lead to AIN and the signal return lead from AGND as
short as possible. If this is not possible, a shielded
cable or a twisted-pair transmission line is recommend-
ed. Additionally, potential differences between the ADC
ground and the signal-source ground should be mini-
mize d , s inc e the s e volta g e d iffe re nc e s a p p e a r a s
errors superimposed on the input signal. To minimize
system noise pickup, keep the driving source resis-
tance below 2kΩ.
V
DD
18
16
AIN
MX7576
COMP
15
17
AGND
REF
DAC
SAR
CLOCK
OSCILLATOR
5
CLK
6
1
2
3
CS
RD
MODE
D7
.
LATCH AND
THREE-STATE
OUTPUT DRIVERS
P ro p e r La yo u t
For PC board layouts, take care to keep digital lines
well separated from any analog lines. Establish a sin-
gle-point, analog ground (separate from the digital sys-
tem ground) near the MX7575/MX7576. This analog
ground point should be connected to the digital system
ground through a single-track connection only. Any
supply or reference bypass capacitors, analog input fil-
te r c a p a c itors , or inp ut s ig na l s hie ld ing s hould b e
returned to the analog ground point.
CONTROL
LOGIC
.
D0
14
4
9
BUSY
DGND
______________________________________________________________________________________ 11
CMOS , µP -Co m p a t ib le , 5 µs /1 0 µs , 8 -Bit ADCs
____P in Co n fig u ra t io n s (c o n t in u e d )
_Ord e rin g In fo rm a t io n (c o n t in u e d )
INL
(LSB)
PART
TEMP. RANGE
PIN-PACKAGE
TOP VIEW
MX7575JEWN -40°C to +85°C
MX7575KEWN -40°C to +85°C
MX7575JEQP -40°C to +85°C
MX7575KEQP -40°C to +85°C
18 Wide SO
18 Wide SO
20 PLCC
±1
3
2
1
20 19
±1/2
±1
20 PLCC
±1/2
±1
TP (MODE)
BUSY
AIN
18
17
16
15
4
5
6
7
8
MX7575SQ
MX7575TQ
MX7576JN
MX7576KN
MX7576JCWN
MX7576KCWN
MX7576JP
-55°C to +125°C
-55°C to +125°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
-25°C to +85°C
-25°C to +85°C
18 CERDIP**
18 CERDIP**
18 Plastic DIP
18 Plastic DIP
18 Wide SO
18 Wide SO
20 PLCC
AGND
D0 (LSB)
D1
±1/2
±1
MX7575
MX7576
CLK
±1/2
±1
D7 (MSB)
D6
±1/2
±1
D2
14
/MX576
MX7576KP
MX7576J/D
MX7576AQ
MX7576BQ
20 PLCC
±1/2
±1
9
10 11 12
13
Dice*
18 CERDIP**
18 CERDIP**
18 Wide SO
18 Wide SO
20 PLCC
±1
±1/2
±1
PLCC
MX7576JEWN -40°C to +85°C
MX7576KEWN -40°C to +85°C
MX7576JEQP -40°C to +85°C
MX7576KEQP -40°C to +85°C
( ) ARE FOR MX7576 ONLY.
±1/2
±1
20 PLCC
±1/2
±1
MX7576SQ
MX7576TQ
-55°C to +125°C
-55°C to +125°C
18 CERDIP**
18 CERDIP**
±1/2
*
Contact factory for dice specifications.
** Contact factory for availability.
__________________________________________________________Ch ip To p o g ra p h ie s
MX7575
MX7576
D6
D7
CLK
N. C.
D6
CLK
MODE
BUSY
D7
(MSB)
BUSY
D5
DGND
D4
D5
DGND
D4
TP
N. C.
RD
RD
CS
CS
0. 081"
0. 081"
V
DD
V
DD
(2. 057mm)
(2. 057mm)
REF
REF
D3
D3
AIN
AGND*
D0
(LSB)
AIN
AGND*
D2
D1
D0
AGND*
D2
D1
AGND*
0. 130"
0. 130"
(3. 302mm)
(3. 302mm)
*The two AGND pads must both be used (bonded together).
*The two AGND pads must both be used (bonded together).
TRANSISTOR COUNT: 768
TRANSISTOR COUNT: 768
SUBSTRATE CONNECTED TO V
DD
SUBSTRATE CONNECTED TO V
DD
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 __________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 (4 0 8 ) 7 3 7 -7 6 0 0
© 1996 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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